mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "mini-amd64.h"
  30 #include "inssel.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * xmmregs [] = {
 121         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 122         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 123 };
 124
 125 const char*
 126 mono_arch_fregname (int reg)
 127 {
 128         if (reg < AMD64_XMM_NREG)
 129                 return xmmregs [reg];
 130         else
 131                 return "unknown";
 132 }
 133
 134 G_GNUC_UNUSED static void
 135 break_count (void)
 136 {
 137 }
 138
 139 G_GNUC_UNUSED static gboolean
 140 debug_count (void)
 141 {
 142         static int count = 0;
 143         count ++;
 144
 145         if (!getenv ("COUNT"))
 146                 return TRUE;
 147
 148         if (count == atoi (getenv ("COUNT"))) {
 149                 break_count ();
 150         }
 151
 152         if (count > atoi (getenv ("COUNT"))) {
 153                 return FALSE;
 154         }
 155
 156         return TRUE;
 157 }
 158
 159 static gboolean
 160 debug_omit_fp (void)
 161 {
 162 #if 0
 163         return debug_count ();
 164 #else
 165         return TRUE;
 166 #endif
 167 }
 168
 169 static inline gboolean
 170 amd64_is_near_call (guint8 *code)
 171 {
 172         /* Skip REX */
 173         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 174                 code += 1;
 175
 176         return code [0] == 0xe8;
 177 }
 178
 179 static inline void
 180 amd64_patch (unsigned char* code, gpointer target)
 181 {
 182         guint8 rex = 0;
 183
 184         /* Skip REX */
 185         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 186                 rex = code [0];
 187                 code += 1;
 188         }
 189
 190         if ((code [0] & 0xf8) == 0xb8) {
 191                 /* amd64_set_reg_template */
 192                 *(guint64*)(code + 1) = (guint64)target;
 193         }
 194         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 195                 /* mov 0(%rip), %dreg */
 196                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 197         }
 198         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 199                 /* call *<OFFSET>(%rip) */
 200                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 201         }
 202         else if ((code [0] == 0xe8)) {
 203                 /* call <DISP> */
 204                 gint64 disp = (guint8*)target - (guint8*)code;
 205                 g_assert (amd64_is_imm32 (disp));
 206                 x86_patch (code, (unsigned char*)target);
 207         }
 208         else
 209                 x86_patch (code, (unsigned char*)target);
 210 }
 211
 212 void
 213 mono_amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         amd64_patch (code, target);
 216 }
 217
 218 typedef enum {
 219         ArgInIReg,
 220         ArgInFloatSSEReg,
 221         ArgInDoubleSSEReg,
 222         ArgOnStack,
 223         ArgValuetypeInReg,
 224         ArgValuetypeAddrInIReg,
 225         ArgNone /* only in pair_storage */
 226 } ArgStorage;
 227
 228 typedef struct {
 229         gint16 offset;
 230         gint8  reg;
 231         ArgStorage storage;
 232
 233         /* Only if storage == ArgValuetypeInReg */
 234         ArgStorage pair_storage [2];
 235         gint8 pair_regs [2];
 236 } ArgInfo;
 237
 238 typedef struct {
 239         int nargs;
 240         guint32 stack_usage;
 241         guint32 reg_usage;
 242         guint32 freg_usage;
 243         gboolean need_stack_align;
 244         ArgInfo ret;
 245         ArgInfo sig_cookie;
 246         ArgInfo args [1];
 247 } CallInfo;
 248
 249 #define DEBUG(a) if (cfg->verbose_level > 1) a
 250
 251 #define NEW_ICONST(cfg,dest,val) do {   \
 252                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 253                 (dest)->opcode = OP_ICONST;     \
 254                 (dest)->inst_c0 = (val);        \
 255                 (dest)->type = STACK_I4;        \
 256         } while (0)
 257
 258 #ifdef PLATFORM_WIN32
 259 #define PARAM_REGS 4
 260
 261 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 262
 263 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 264 #else
 265 #define PARAM_REGS 6
 266
 267 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 268
 269  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 270 #endif
 271
 272 static void inline
 273 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 274 {
 275     ainfo->offset = *stack_size;
 276
 277     if (*gr >= PARAM_REGS) {
 278                 ainfo->storage = ArgOnStack;
 279                 (*stack_size) += sizeof (gpointer);
 280     }
 281     else {
 282                 ainfo->storage = ArgInIReg;
 283                 ainfo->reg = param_regs [*gr];
 284                 (*gr) ++;
 285     }
 286 }
 287
 288 #ifdef PLATFORM_WIN32
 289 #define FLOAT_PARAM_REGS 4
 290 #else
 291 #define FLOAT_PARAM_REGS 8
 292 #endif
 293
 294 static void inline
 295 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 296 {
 297     ainfo->offset = *stack_size;
 298
 299     if (*gr >= FLOAT_PARAM_REGS) {
 300                 ainfo->storage = ArgOnStack;
 301                 (*stack_size) += sizeof (gpointer);
 302     }
 303     else {
 304                 /* A double register */
 305                 if (is_double)
 306                         ainfo->storage = ArgInDoubleSSEReg;
 307                 else
 308                         ainfo->storage = ArgInFloatSSEReg;
 309                 ainfo->reg = *gr;
 310                 (*gr) += 1;
 311     }
 312 }
 313
 314 typedef enum ArgumentClass {
 315         ARG_CLASS_NO_CLASS,
 316         ARG_CLASS_MEMORY,
 317         ARG_CLASS_INTEGER,
 318         ARG_CLASS_SSE
 319 } ArgumentClass;
 320
 321 static ArgumentClass
 322 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 323 {
 324         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 325         MonoType *ptype;
 326
 327         ptype = mini_type_get_underlying_type (NULL, type);
 328         switch (ptype->type) {
 329         case MONO_TYPE_BOOLEAN:
 330         case MONO_TYPE_CHAR:
 331         case MONO_TYPE_I1:
 332         case MONO_TYPE_U1:
 333         case MONO_TYPE_I2:
 334         case MONO_TYPE_U2:
 335         case MONO_TYPE_I4:
 336         case MONO_TYPE_U4:
 337         case MONO_TYPE_I:
 338         case MONO_TYPE_U:
 339         case MONO_TYPE_STRING:
 340         case MONO_TYPE_OBJECT:
 341         case MONO_TYPE_CLASS:
 342         case MONO_TYPE_SZARRAY:
 343         case MONO_TYPE_PTR:
 344         case MONO_TYPE_FNPTR:
 345         case MONO_TYPE_ARRAY:
 346         case MONO_TYPE_I8:
 347         case MONO_TYPE_U8:
 348                 class2 = ARG_CLASS_INTEGER;
 349                 break;
 350         case MONO_TYPE_R4:
 351         case MONO_TYPE_R8:
 352 #ifdef PLATFORM_WIN32
 353                 class2 = ARG_CLASS_INTEGER;
 354 #else
 355                 class2 = ARG_CLASS_SSE;
 356 #endif
 357                 break;
 358
 359         case MONO_TYPE_TYPEDBYREF:
 360                 g_assert_not_reached ();
 361
 362         case MONO_TYPE_GENERICINST:
 363                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 364                         class2 = ARG_CLASS_INTEGER;
 365                         break;
 366                 }
 367                 /* fall through */
 368         case MONO_TYPE_VALUETYPE: {
 369                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 370                 int i;
 371
 372                 for (i = 0; i < info->num_fields; ++i) {
 373                         class2 = class1;
 374                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 375                 }
 376                 break;
 377         }
 378         default:
 379                 g_assert_not_reached ();
 380         }
 381
 382         /* Merge */
 383         if (class1 == class2)
 384                 ;
 385         else if (class1 == ARG_CLASS_NO_CLASS)
 386                 class1 = class2;
 387         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 388                 class1 = ARG_CLASS_MEMORY;
 389         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 390                 class1 = ARG_CLASS_INTEGER;
 391         else
 392                 class1 = ARG_CLASS_SSE;
 393
 394         return class1;
 395 }
 396
 397 static void
 398 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 399                gboolean is_return,
 400                guint32 *gr, guint32 *fr, guint32 *stack_size)
 401 {
 402         guint32 size, quad, nquads, i;
 403         ArgumentClass args [2];
 404         MonoMarshalType *info = NULL;
 405         MonoClass *klass;
 406         MonoGenericSharingContext tmp_gsctx;
 407
 408         /*
 409          * The gsctx currently contains no data, it is only used for checking whenever
 410          * open types are allowed, some callers like mono_arch_get_argument_info ()
 411          * don't pass it to us, so work around that.
 412          */
 413         if (!gsctx)
 414                 gsctx = &tmp_gsctx;
 415
 416         klass = mono_class_from_mono_type (type);
 417         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 418 #ifndef PLATFORM_WIN32
 419         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 420                 /* We pass and return vtypes of size 8 in a register */
 421         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 422 #else
 423         if (!sig->pinvoke) {
 424 #endif
 425                 /* Allways pass in memory */
 426                 ainfo->offset = *stack_size;
 427                 *stack_size += ALIGN_TO (size, 8);
 428                 ainfo->storage = ArgOnStack;
 429
 430                 return;
 431         }
 432
 433         /* FIXME: Handle structs smaller than 8 bytes */
 434         //if ((size % 8) != 0)
 435         //      NOT_IMPLEMENTED;
 436
 437         if (size > 8)
 438                 nquads = 2;
 439         else
 440                 nquads = 1;
 441
 442         if (!sig->pinvoke) {
 443                 /* Always pass in 1 or 2 integer registers */
 444                 args [0] = ARG_CLASS_INTEGER;
 445                 args [1] = ARG_CLASS_INTEGER;
 446                 /* Only the simplest cases are supported */
 447                 if (is_return && nquads != 1) {
 448                         args [0] = ARG_CLASS_MEMORY;
 449                         args [1] = ARG_CLASS_MEMORY;
 450                 }
 451         } else {
 452                 /*
 453                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 454                  * The X87 and SSEUP stuff is left out since there are no such types in
 455                  * the CLR.
 456                  */
 457                 info = mono_marshal_load_type_info (klass);
 458                 g_assert (info);
 459
 460 #ifndef PLATFORM_WIN32
 461                 if (info->native_size > 16) {
 462                         ainfo->offset = *stack_size;
 463                         *stack_size += ALIGN_TO (info->native_size, 8);
 464                         ainfo->storage = ArgOnStack;
 465
 466                         return;
 467                 }
 468 #else
 469                 switch (info->native_size) {
 470                 case 1: case 2: case 4: case 8:
 471                         break;
 472                 default:
 473                         if (is_return) {
 474                                 ainfo->storage = ArgOnStack;
 475                                 ainfo->offset = *stack_size;
 476                                 *stack_size += ALIGN_TO (info->native_size, 8);
 477                         }
 478                         else {
 479                                 ainfo->storage = ArgValuetypeAddrInIReg;
 480
 481                                 if (*gr < PARAM_REGS) {
 482                                         ainfo->pair_storage [0] = ArgInIReg;
 483                                         ainfo->pair_regs [0] = param_regs [*gr];
 484                                         (*gr) ++;
 485                                 }
 486                                 else {
 487                                         ainfo->pair_storage [0] = ArgOnStack;
 488                                         ainfo->offset = *stack_size;
 489                                         *stack_size += 8;
 490                                 }
 491                         }
 492
 493                         return;
 494                 }
 495 #endif
 496
 497                 args [0] = ARG_CLASS_NO_CLASS;
 498                 args [1] = ARG_CLASS_NO_CLASS;
 499                 for (quad = 0; quad < nquads; ++quad) {
 500                         int size;
 501                         guint32 align;
 502                         ArgumentClass class1;
 503
 504                         if (info->num_fields == 0)
 505                                 class1 = ARG_CLASS_MEMORY;
 506                         else
 507                                 class1 = ARG_CLASS_NO_CLASS;
 508                         for (i = 0; i < info->num_fields; ++i) {
 509                                 size = mono_marshal_type_size (info->fields [i].field->type,
 510                                                                                            info->fields [i].mspec,
 511                                                                                            &align, TRUE, klass->unicode);
 512                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 513                                         /* Unaligned field */
 514                                         NOT_IMPLEMENTED;
 515                                 }
 516
 517                                 /* Skip fields in other quad */
 518                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 519                                         continue;
 520                                 if ((quad == 1) && (info->fields [i].offset < 8))
 521                                         continue;
 522
 523                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 524                         }
 525                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 526                         args [quad] = class1;
 527                 }
 528         }
 529
 530         /* Post merger cleanup */
 531         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 532                 args [0] = args [1] = ARG_CLASS_MEMORY;
 533
 534         /* Allocate registers */
 535         {
 536                 int orig_gr = *gr;
 537                 int orig_fr = *fr;
 538
 539                 ainfo->storage = ArgValuetypeInReg;
 540                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 541                 for (quad = 0; quad < nquads; ++quad) {
 542                         switch (args [quad]) {
 543                         case ARG_CLASS_INTEGER:
 544                                 if (*gr >= PARAM_REGS)
 545                                         args [quad] = ARG_CLASS_MEMORY;
 546                                 else {
 547                                         ainfo->pair_storage [quad] = ArgInIReg;
 548                                         if (is_return)
 549                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 550                                         else
 551                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 552                                         (*gr) ++;
 553                                 }
 554                                 break;
 555                         case ARG_CLASS_SSE:
 556                                 if (*fr >= FLOAT_PARAM_REGS)
 557                                         args [quad] = ARG_CLASS_MEMORY;
 558                                 else {
 559                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 560                                         ainfo->pair_regs [quad] = *fr;
 561                                         (*fr) ++;
 562                                 }
 563                                 break;
 564                         case ARG_CLASS_MEMORY:
 565                                 break;
 566                         default:
 567                                 g_assert_not_reached ();
 568                         }
 569                 }
 570
 571                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 572                         /* Revert possible register assignments */
 573                         *gr = orig_gr;
 574                         *fr = orig_fr;
 575
 576                         ainfo->offset = *stack_size;
 577                         if (sig->pinvoke)
 578                                 *stack_size += ALIGN_TO (info->native_size, 8);
 579                         else
 580                                 *stack_size += nquads * sizeof (gpointer);
 581                         ainfo->storage = ArgOnStack;
 582                 }
 583         }
 584 }
 585
 586 /*
 587  * get_call_info:
 588  *
 589  *  Obtain information about a call according to the calling convention.
 590  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 591  * Draft Version 0.23" document for more information.
 592  */
 593 static CallInfo*
 594 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 595 {
 596         guint32 i, gr, fr;
 597         MonoType *ret_type;
 598         int n = sig->hasthis + sig->param_count;
 599         guint32 stack_size = 0;
 600         CallInfo *cinfo;
 601
 602         if (mp)
 603                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 604         else
 605                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 606
 607         gr = 0;
 608         fr = 0;
 609
 610         /* return value */
 611         {
 612                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 613                 switch (ret_type->type) {
 614                 case MONO_TYPE_BOOLEAN:
 615                 case MONO_TYPE_I1:
 616                 case MONO_TYPE_U1:
 617                 case MONO_TYPE_I2:
 618                 case MONO_TYPE_U2:
 619                 case MONO_TYPE_CHAR:
 620                 case MONO_TYPE_I4:
 621                 case MONO_TYPE_U4:
 622                 case MONO_TYPE_I:
 623                 case MONO_TYPE_U:
 624                 case MONO_TYPE_PTR:
 625                 case MONO_TYPE_FNPTR:
 626                 case MONO_TYPE_CLASS:
 627                 case MONO_TYPE_OBJECT:
 628                 case MONO_TYPE_SZARRAY:
 629                 case MONO_TYPE_ARRAY:
 630                 case MONO_TYPE_STRING:
 631                         cinfo->ret.storage = ArgInIReg;
 632                         cinfo->ret.reg = AMD64_RAX;
 633                         break;
 634                 case MONO_TYPE_U8:
 635                 case MONO_TYPE_I8:
 636                         cinfo->ret.storage = ArgInIReg;
 637                         cinfo->ret.reg = AMD64_RAX;
 638                         break;
 639                 case MONO_TYPE_R4:
 640                         cinfo->ret.storage = ArgInFloatSSEReg;
 641                         cinfo->ret.reg = AMD64_XMM0;
 642                         break;
 643                 case MONO_TYPE_R8:
 644                         cinfo->ret.storage = ArgInDoubleSSEReg;
 645                         cinfo->ret.reg = AMD64_XMM0;
 646                         break;
 647                 case MONO_TYPE_GENERICINST:
 648                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 649                                 cinfo->ret.storage = ArgInIReg;
 650                                 cinfo->ret.reg = AMD64_RAX;
 651                                 break;
 652                         }
 653                         /* fall through */
 654                 case MONO_TYPE_VALUETYPE: {
 655                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 656
 657                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 658                         if (cinfo->ret.storage == ArgOnStack)
 659                                 /* The caller passes the address where the value is stored */
 660                                 add_general (&gr, &stack_size, &cinfo->ret);
 661                         break;
 662                 }
 663                 case MONO_TYPE_TYPEDBYREF:
 664                         /* Same as a valuetype with size 24 */
 665                         add_general (&gr, &stack_size, &cinfo->ret);
 666                         ;
 667                         break;
 668                 case MONO_TYPE_VOID:
 669                         break;
 670                 default:
 671                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 672                 }
 673         }
 674
 675         /* this */
 676         if (sig->hasthis)
 677                 add_general (&gr, &stack_size, cinfo->args + 0);
 678
 679         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 680                 gr = PARAM_REGS;
 681                 fr = FLOAT_PARAM_REGS;
 682
 683                 /* Emit the signature cookie just before the implicit arguments */
 684                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 685         }
 686
 687         for (i = 0; i < sig->param_count; ++i) {
 688                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 689                 MonoType *ptype;
 690
 691 #ifdef PLATFORM_WIN32
 692                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 693                 if (gr > fr)
 694                         fr = gr;
 695                 else if (fr > gr)
 696                         gr = fr;
 697 #endif
 698
 699                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 700                         /* We allways pass the sig cookie on the stack for simplicity */
 701                         /*
 702                          * Prevent implicit arguments + the sig cookie from being passed
 703                          * in registers.
 704                          */
 705                         gr = PARAM_REGS;
 706                         fr = FLOAT_PARAM_REGS;
 707
 708                         /* Emit the signature cookie just before the implicit arguments */
 709                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 710                 }
 711
 712                 if (sig->params [i]->byref) {
 713                         add_general (&gr, &stack_size, ainfo);
 714                         continue;
 715                 }
 716                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 717                 switch (ptype->type) {
 718                 case MONO_TYPE_BOOLEAN:
 719                 case MONO_TYPE_I1:
 720                 case MONO_TYPE_U1:
 721                         add_general (&gr, &stack_size, ainfo);
 722                         break;
 723                 case MONO_TYPE_I2:
 724                 case MONO_TYPE_U2:
 725                 case MONO_TYPE_CHAR:
 726                         add_general (&gr, &stack_size, ainfo);
 727                         break;
 728                 case MONO_TYPE_I4:
 729                 case MONO_TYPE_U4:
 730                         add_general (&gr, &stack_size, ainfo);
 731                         break;
 732                 case MONO_TYPE_I:
 733                 case MONO_TYPE_U:
 734                 case MONO_TYPE_PTR:
 735                 case MONO_TYPE_FNPTR:
 736                 case MONO_TYPE_CLASS:
 737                 case MONO_TYPE_OBJECT:
 738                 case MONO_TYPE_STRING:
 739                 case MONO_TYPE_SZARRAY:
 740                 case MONO_TYPE_ARRAY:
 741                         add_general (&gr, &stack_size, ainfo);
 742                         break;
 743                 case MONO_TYPE_GENERICINST:
 744                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 745                                 add_general (&gr, &stack_size, ainfo);
 746                                 break;
 747                         }
 748                         /* fall through */
 749                 case MONO_TYPE_VALUETYPE:
 750                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 751                         break;
 752                 case MONO_TYPE_TYPEDBYREF:
 753 #ifdef PLATFORM_WIN32
 754                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 755 #else
 756                         stack_size += sizeof (MonoTypedRef);
 757                         ainfo->storage = ArgOnStack;
 758 #endif
 759                         break;
 760                 case MONO_TYPE_U8:
 761                 case MONO_TYPE_I8:
 762                         add_general (&gr, &stack_size, ainfo);
 763                         break;
 764                 case MONO_TYPE_R4:
 765                         add_float (&fr, &stack_size, ainfo, FALSE);
 766                         break;
 767                 case MONO_TYPE_R8:
 768                         add_float (&fr, &stack_size, ainfo, TRUE);
 769                         break;
 770                 default:
 771                         g_assert_not_reached ();
 772                 }
 773         }
 774
 775         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 776                 gr = PARAM_REGS;
 777                 fr = FLOAT_PARAM_REGS;
 778
 779                 /* Emit the signature cookie just before the implicit arguments */
 780                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 781         }
 782
 783 #ifdef PLATFORM_WIN32
 784         // There always is 32 bytes reserved on the stack when calling on Winx64
 785         stack_size += 0x20;
 786 #endif
 787
 788         if (stack_size & 0x8) {
 789                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 790                 cinfo->need_stack_align = TRUE;
 791                 stack_size += 8;
 792         }
 793
 794         cinfo->stack_usage = stack_size;
 795         cinfo->reg_usage = gr;
 796         cinfo->freg_usage = fr;
 797         return cinfo;
 798 }
 799
 800 /*
 801  * mono_arch_get_argument_info:
 802  * @csig:  a method signature
 803  * @param_count: the number of parameters to consider
 804  * @arg_info: an array to store the result infos
 805  *
 806  * Gathers information on parameters such as size, alignment and
 807  * padding. arg_info should be large enought to hold param_count + 1 entries.
 808  *
 809  * Returns the size of the argument area on the stack.
 810  */
 811 int
 812 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 813 {
 814         int k;
 815         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 816         guint32 args_size = cinfo->stack_usage;
 817
 818         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 819         if (csig->hasthis) {
 820                 arg_info [0].offset = 0;
 821         }
 822
 823         for (k = 0; k < param_count; k++) {
 824                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 825                 /* FIXME: */
 826                 arg_info [k + 1].size = 0;
 827         }
 828
 829         g_free (cinfo);
 830
 831         return args_size;
 832 }
 833
 834 static int
 835 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 836 {
 837 #ifndef _MSC_VER
 838         __asm__ __volatile__ ("cpuid"
 839                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 840                 : "a" (id));
 841 #else
 842         int info[4];
 843         __cpuid(info, id);
 844         *p_eax = info[0];
 845         *p_ebx = info[1];
 846         *p_ecx = info[2];
 847         *p_edx = info[3];
 848 #endif
 849         return 1;
 850 }
 851
 852 /*
 853  * Initialize the cpu to execute managed code.
 854  */
 855 void
 856 mono_arch_cpu_init (void)
 857 {
 858 #ifndef _MSC_VER
 859         guint16 fpcw;
 860
 861         /* spec compliance requires running with double precision */
 862         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 863         fpcw &= ~X86_FPCW_PRECC_MASK;
 864         fpcw |= X86_FPCW_PREC_DOUBLE;
 865         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 866         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 867 #else
 868         /* TODO: This is crashing on Win64 right now.
 869         * _control87 (_PC_53, MCW_PC);
 870         */
 871 #endif
 872 }
 873
 874 /*
 875  * Initialize architecture specific code.
 876  */
 877 void
 878 mono_arch_init (void)
 879 {
 880         InitializeCriticalSection (&mini_arch_mutex);
 881 }
 882
 883 /*
 884  * Cleanup architecture specific code.
 885  */
 886 void
 887 mono_arch_cleanup (void)
 888 {
 889         DeleteCriticalSection (&mini_arch_mutex);
 890 }
 891
 892 /*
 893  * This function returns the optimizations supported on this cpu.
 894  */
 895 guint32
 896 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 897 {
 898         int eax, ebx, ecx, edx;
 899         guint32 opts = 0;
 900
 901         /* FIXME: AMD64 */
 902
 903         *exclude_mask = 0;
 904         /* Feature Flags function, flags returned in EDX. */
 905         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 906                 if (edx & (1 << 15)) {
 907                         opts |= MONO_OPT_CMOV;
 908                         if (edx & 1)
 909                                 opts |= MONO_OPT_FCMOV;
 910                         else
 911                                 *exclude_mask |= MONO_OPT_FCMOV;
 912                 } else
 913                         *exclude_mask |= MONO_OPT_CMOV;
 914         }
 915
 916         return opts;
 917 }
 918
 919 GList *
 920 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 921 {
 922         GList *vars = NULL;
 923         int i;
 924
 925         for (i = 0; i < cfg->num_varinfo; i++) {
 926                 MonoInst *ins = cfg->varinfo [i];
 927                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 928
 929                 /* unused vars */
 930                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 931                         continue;
 932
 933                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 934                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 935                         continue;
 936
 937                 if (mono_is_regsize_var (ins->inst_vtype)) {
 938                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 939                         g_assert (i == vmv->idx);
 940                         vars = g_list_prepend (vars, vmv);
 941                 }
 942         }
 943
 944         vars = mono_varlist_sort (cfg, vars, 0);
 945
 946         return vars;
 947 }
 948
 949 /**
 950  * mono_arch_compute_omit_fp:
 951  *
 952  *   Determine whenever the frame pointer can be eliminated.
 953  */
 954 static void
 955 mono_arch_compute_omit_fp (MonoCompile *cfg)
 956 {
 957         MonoMethodSignature *sig;
 958         MonoMethodHeader *header;
 959         int i, locals_size;
 960         CallInfo *cinfo;
 961
 962         if (cfg->arch.omit_fp_computed)
 963                 return;
 964
 965         header = mono_method_get_header (cfg->method);
 966
 967         sig = mono_method_signature (cfg->method);
 968
 969         if (!cfg->arch.cinfo)
 970                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 971         cinfo = cfg->arch.cinfo;
 972
 973         /*
 974          * FIXME: Remove some of the restrictions.
 975          */
 976         cfg->arch.omit_fp = TRUE;
 977         cfg->arch.omit_fp_computed = TRUE;
 978
 979         if (cfg->disable_omit_fp)
 980                 cfg->arch.omit_fp = FALSE;
 981
 982         if (!debug_omit_fp ())
 983                 cfg->arch.omit_fp = FALSE;
 984         /*
 985         if (cfg->method->save_lmf)
 986                 cfg->arch.omit_fp = FALSE;
 987         */
 988         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 989                 cfg->arch.omit_fp = FALSE;
 990         if (header->num_clauses)
 991                 cfg->arch.omit_fp = FALSE;
 992         if (cfg->param_area)
 993                 cfg->arch.omit_fp = FALSE;
 994         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 995                 cfg->arch.omit_fp = FALSE;
 996         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 997                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 998                 cfg->arch.omit_fp = FALSE;
 999         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1000                 ArgInfo *ainfo = &cinfo->args [i];
1001
1002                 if (ainfo->storage == ArgOnStack) {
1003                         /*
1004                          * The stack offset can only be determined when the frame
1005                          * size is known.
1006                          */
1007                         cfg->arch.omit_fp = FALSE;
1008                 }
1009         }
1010
1011         locals_size = 0;
1012         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1013                 MonoInst *ins = cfg->varinfo [i];
1014                 int ialign;
1015
1016                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1017         }
1018
1019         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1020                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1021                 cfg->arch.omit_fp = FALSE;
1022         }
1023 }
1024
1025 GList *
1026 mono_arch_get_global_int_regs (MonoCompile *cfg)
1027 {
1028         GList *regs = NULL;
1029
1030         mono_arch_compute_omit_fp (cfg);
1031
1032         if (cfg->globalra) {
1033                 if (cfg->arch.omit_fp)
1034                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1035
1036                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1037                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1041
1042                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1043                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1044                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1045                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1046                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1047                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1050         } else {
1051                 if (cfg->arch.omit_fp)
1052                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1053
1054                 /* We use the callee saved registers for global allocation */
1055                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1056                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1057                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1058                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1059                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1060         }
1061
1062         return regs;
1063 }
1064
1065 GList*
1066 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1067 {
1068         GList *regs = NULL;
1069         int i;
1070
1071         /* All XMM registers */
1072         for (i = 0; i < 16; ++i)
1073                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1074
1075         return regs;
1076 }
1077
1078 GList*
1079 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1080 {
1081         static GList *r = NULL;
1082
1083         if (r == NULL) {
1084                 GList *regs = NULL;
1085
1086                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1092
1093                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1094                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1095                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1096                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1097                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1098                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1099                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1100                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1101
1102                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1103         }
1104
1105         return r;
1106 }
1107
1108 GList*
1109 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1110 {
1111         int i;
1112         static GList *r = NULL;
1113
1114         if (r == NULL) {
1115                 GList *regs = NULL;
1116
1117                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1118                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1119
1120                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1121         }
1122
1123         return r;
1124 }
1125
1126 /*
1127  * mono_arch_regalloc_cost:
1128  *
1129  *  Return the cost, in number of memory references, of the action of
1130  * allocating the variable VMV into a register during global register
1131  * allocation.
1132  */
1133 guint32
1134 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1135 {
1136         MonoInst *ins = cfg->varinfo [vmv->idx];
1137
1138         if (cfg->method->save_lmf)
1139                 /* The register is already saved */
1140                 /* substract 1 for the invisible store in the prolog */
1141                 return (ins->opcode == OP_ARG) ? 0 : 1;
1142         else
1143                 /* push+pop */
1144                 return (ins->opcode == OP_ARG) ? 1 : 2;
1145 }
1146
1147 /*
1148  * mono_arch_fill_argument_info:
1149  *
1150  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1151  * of the method.
1152  */
1153 void
1154 mono_arch_fill_argument_info (MonoCompile *cfg)
1155 {
1156         MonoMethodSignature *sig;
1157         MonoMethodHeader *header;
1158         MonoInst *ins;
1159         int i;
1160         CallInfo *cinfo;
1161
1162         header = mono_method_get_header (cfg->method);
1163
1164         sig = mono_method_signature (cfg->method);
1165
1166         cinfo = cfg->arch.cinfo;
1167
1168         /*
1169          * Contrary to mono_arch_allocate_vars (), the information should describe
1170          * where the arguments are at the beginning of the method, not where they can be
1171          * accessed during the execution of the method. The later makes no sense for the
1172          * global register allocator, since a variable can be in more than one location.
1173          */
1174         if (sig->ret->type != MONO_TYPE_VOID) {
1175                 switch (cinfo->ret.storage) {
1176                 case ArgInIReg:
1177                 case ArgInFloatSSEReg:
1178                 case ArgInDoubleSSEReg:
1179                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1180                                 cfg->vret_addr->opcode = OP_REGVAR;
1181                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1182                         }
1183                         else {
1184                                 cfg->ret->opcode = OP_REGVAR;
1185                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1186                         }
1187                         break;
1188                 case ArgValuetypeInReg:
1189                         cfg->ret->opcode = OP_REGOFFSET;
1190                         cfg->ret->inst_basereg = -1;
1191                         cfg->ret->inst_offset = -1;
1192                         break;
1193                 default:
1194                         g_assert_not_reached ();
1195                 }
1196         }
1197
1198         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1199                 ArgInfo *ainfo = &cinfo->args [i];
1200                 MonoType *arg_type;
1201
1202                 ins = cfg->args [i];
1203
1204                 if (sig->hasthis && (i == 0))
1205                         arg_type = &mono_defaults.object_class->byval_arg;
1206                 else
1207                         arg_type = sig->params [i - sig->hasthis];
1208
1209                 switch (ainfo->storage) {
1210                 case ArgInIReg:
1211                 case ArgInFloatSSEReg:
1212                 case ArgInDoubleSSEReg:
1213                         ins->opcode = OP_REGVAR;
1214                         ins->inst_c0 = ainfo->reg;
1215                         break;
1216                 case ArgOnStack:
1217                         ins->opcode = OP_REGOFFSET;
1218                         ins->inst_basereg = -1;
1219                         ins->inst_offset = -1;
1220                         break;
1221                 case ArgValuetypeInReg:
1222                         /* Dummy */
1223                         ins->opcode = OP_NOP;
1224                         break;
1225                 default:
1226                         g_assert_not_reached ();
1227                 }
1228         }
1229 }
1230
1231 void
1232 mono_arch_allocate_vars (MonoCompile *cfg)
1233 {
1234         MonoMethodSignature *sig;
1235         MonoMethodHeader *header;
1236         MonoInst *ins;
1237         int i, offset;
1238         guint32 locals_stack_size, locals_stack_align;
1239         gint32 *offsets;
1240         CallInfo *cinfo;
1241
1242         header = mono_method_get_header (cfg->method);
1243
1244         sig = mono_method_signature (cfg->method);
1245
1246         cinfo = cfg->arch.cinfo;
1247
1248         mono_arch_compute_omit_fp (cfg);
1249
1250         /*
1251          * We use the ABI calling conventions for managed code as well.
1252          * Exception: valuetypes are never passed or returned in registers.
1253          */
1254
1255         if (cfg->arch.omit_fp) {
1256                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1257                 cfg->frame_reg = AMD64_RSP;
1258                 offset = 0;
1259         } else {
1260                 /* Locals are allocated backwards from %fp */
1261                 cfg->frame_reg = AMD64_RBP;
1262                 offset = 0;
1263         }
1264
1265         if (cfg->method->save_lmf) {
1266                 /* Reserve stack space for saving LMF */
1267                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1268                 g_assert (offset == 0);
1269                 if (cfg->arch.omit_fp) {
1270                         cfg->arch.lmf_offset = offset;
1271                         offset += sizeof (MonoLMF);
1272                 }
1273                 else {
1274                         offset += sizeof (MonoLMF);
1275                         cfg->arch.lmf_offset = -offset;
1276                 }
1277         } else {
1278                 if (cfg->arch.omit_fp)
1279                         cfg->arch.reg_save_area_offset = offset;
1280                 /* Reserve space for caller saved registers */
1281                 for (i = 0; i < AMD64_NREG; ++i)
1282                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1283                                 offset += sizeof (gpointer);
1284                         }
1285         }
1286
1287         if (sig->ret->type != MONO_TYPE_VOID) {
1288                 switch (cinfo->ret.storage) {
1289                 case ArgInIReg:
1290                 case ArgInFloatSSEReg:
1291                 case ArgInDoubleSSEReg:
1292                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1293                                 if (cfg->globalra) {
1294                                         cfg->vret_addr->opcode = OP_REGVAR;
1295                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1296                                 } else {
1297                                         /* The register is volatile */
1298                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1299                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1300                                         if (cfg->arch.omit_fp) {
1301                                                 cfg->vret_addr->inst_offset = offset;
1302                                                 offset += 8;
1303                                         } else {
1304                                                 offset += 8;
1305                                                 cfg->vret_addr->inst_offset = -offset;
1306                                         }
1307                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1308                                                 printf ("vret_addr =");
1309                                                 mono_print_ins (cfg->vret_addr);
1310                                         }
1311                                 }
1312                         }
1313                         else {
1314                                 cfg->ret->opcode = OP_REGVAR;
1315                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1316                         }
1317                         break;
1318                 case ArgValuetypeInReg:
1319                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1320                         cfg->ret->opcode = OP_REGOFFSET;
1321                         cfg->ret->inst_basereg = cfg->frame_reg;
1322                         if (cfg->arch.omit_fp) {
1323                                 cfg->ret->inst_offset = offset;
1324                                 offset += 16;
1325                         } else {
1326                                 offset += 16;
1327                                 cfg->ret->inst_offset = - offset;
1328                         }
1329                         break;
1330                 default:
1331                         g_assert_not_reached ();
1332                 }
1333                 if (!cfg->globalra)
1334                         cfg->ret->dreg = cfg->ret->inst_c0;
1335         }
1336
1337         /* Allocate locals */
1338         if (!cfg->globalra) {
1339                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1340                 if (locals_stack_align) {
1341                         offset += (locals_stack_align - 1);
1342                         offset &= ~(locals_stack_align - 1);
1343                 }
1344                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1345                         if (offsets [i] != -1) {
1346                                 MonoInst *ins = cfg->varinfo [i];
1347                                 ins->opcode = OP_REGOFFSET;
1348                                 ins->inst_basereg = cfg->frame_reg;
1349                                 if (cfg->arch.omit_fp)
1350                                         ins->inst_offset = (offset + offsets [i]);
1351                                 else
1352                                         ins->inst_offset = - (offset + offsets [i]);
1353                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1354                         }
1355                 }
1356                 offset += locals_stack_size;
1357         }
1358
1359         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1360                 g_assert (!cfg->arch.omit_fp);
1361                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1362                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1363         }
1364
1365         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1366                 ins = cfg->args [i];
1367                 if (ins->opcode != OP_REGVAR) {
1368                         ArgInfo *ainfo = &cinfo->args [i];
1369                         gboolean inreg = TRUE;
1370                         MonoType *arg_type;
1371
1372                         if (sig->hasthis && (i == 0))
1373                                 arg_type = &mono_defaults.object_class->byval_arg;
1374                         else
1375                                 arg_type = sig->params [i - sig->hasthis];
1376
1377                         if (cfg->globalra) {
1378                                 /* The new allocator needs info about the original locations of the arguments */
1379                                 switch (ainfo->storage) {
1380                                 case ArgInIReg:
1381                                 case ArgInFloatSSEReg:
1382                                 case ArgInDoubleSSEReg:
1383                                         ins->opcode = OP_REGVAR;
1384                                         ins->inst_c0 = ainfo->reg;
1385                                         break;
1386                                 case ArgOnStack:
1387                                         g_assert (!cfg->arch.omit_fp);
1388                                         ins->opcode = OP_REGOFFSET;
1389                                         ins->inst_basereg = cfg->frame_reg;
1390                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1391                                         break;
1392                                 case ArgValuetypeInReg:
1393                                         ins->opcode = OP_REGOFFSET;
1394                                         ins->inst_basereg = cfg->frame_reg;
1395                                         /* These arguments are saved to the stack in the prolog */
1396                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1397                                         if (cfg->arch.omit_fp) {
1398                                                 ins->inst_offset = offset;
1399                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1400                                         } else {
1401                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1402                                                 ins->inst_offset = - offset;
1403                                         }
1404                                         break;
1405                                 default:
1406                                         g_assert_not_reached ();
1407                                 }
1408
1409                                 continue;
1410                         }
1411
1412                         /* FIXME: Allocate volatile arguments to registers */
1413                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1414                                 inreg = FALSE;
1415
1416                         /*
1417                          * Under AMD64, all registers used to pass arguments to functions
1418                          * are volatile across calls.
1419                          * FIXME: Optimize this.
1420                          */
1421                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1422                                 inreg = FALSE;
1423
1424                         ins->opcode = OP_REGOFFSET;
1425
1426                         switch (ainfo->storage) {
1427                         case ArgInIReg:
1428                         case ArgInFloatSSEReg:
1429                         case ArgInDoubleSSEReg:
1430                                 if (inreg) {
1431                                         ins->opcode = OP_REGVAR;
1432                                         ins->dreg = ainfo->reg;
1433                                 }
1434                                 break;
1435                         case ArgOnStack:
1436                                 g_assert (!cfg->arch.omit_fp);
1437                                 ins->opcode = OP_REGOFFSET;
1438                                 ins->inst_basereg = cfg->frame_reg;
1439                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1440                                 break;
1441                         case ArgValuetypeInReg:
1442                                 break;
1443                         case ArgValuetypeAddrInIReg: {
1444                                 MonoInst *indir;
1445                                 g_assert (!cfg->arch.omit_fp);
1446
1447                                 MONO_INST_NEW (cfg, indir, 0);
1448                                 indir->opcode = OP_REGOFFSET;
1449                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1450                                         indir->inst_basereg = cfg->frame_reg;
1451                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1452                                         offset += (sizeof (gpointer));
1453                                         indir->inst_offset = - offset;
1454                                 }
1455                                 else {
1456                                         indir->inst_basereg = cfg->frame_reg;
1457                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1458                                 }
1459
1460                                 ins->opcode = OP_VTARG_ADDR;
1461                                 ins->inst_left = indir;
1462
1463                                 break;
1464                         }
1465                         default:
1466                                 NOT_IMPLEMENTED;
1467                         }
1468
1469                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1470                                 ins->opcode = OP_REGOFFSET;
1471                                 ins->inst_basereg = cfg->frame_reg;
1472                                 /* These arguments are saved to the stack in the prolog */
1473                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1474                                 if (cfg->arch.omit_fp) {
1475                                         ins->inst_offset = offset;
1476                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1477                                 } else {
1478                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1479                                         ins->inst_offset = - offset;
1480                                 }
1481                         }
1482                 }
1483         }
1484
1485         cfg->stack_offset = offset;
1486 }
1487
1488 void
1489 mono_arch_create_vars (MonoCompile *cfg)
1490 {
1491         MonoMethodSignature *sig;
1492         CallInfo *cinfo;
1493
1494         sig = mono_method_signature (cfg->method);
1495
1496         if (!cfg->arch.cinfo)
1497                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1498         cinfo = cfg->arch.cinfo;
1499
1500         if (cinfo->ret.storage == ArgValuetypeInReg)
1501                 cfg->ret_var_is_local = TRUE;
1502
1503         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1504                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1505                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1506                         printf ("vret_addr = ");
1507                         mono_print_ins (cfg->vret_addr);
1508                 }
1509         }
1510 }
1511
1512 static void
1513 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1514 {
1515         MonoInst *ins;
1516
1517         switch (storage) {
1518         case ArgInIReg:
1519                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1520                 ins->dreg = mono_alloc_ireg (cfg);
1521                 ins->sreg1 = tree->dreg;
1522                 MONO_ADD_INS (cfg->cbb, ins);
1523                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1524                 break;
1525         case ArgInFloatSSEReg:
1526                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1527                 ins->dreg = mono_alloc_freg (cfg);
1528                 ins->sreg1 = tree->dreg;
1529                 MONO_ADD_INS (cfg->cbb, ins);
1530
1531                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1532                 break;
1533         case ArgInDoubleSSEReg:
1534                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1535                 ins->dreg = mono_alloc_freg (cfg);
1536                 ins->sreg1 = tree->dreg;
1537                 MONO_ADD_INS (cfg->cbb, ins);
1538
1539                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1540
1541                 break;
1542         default:
1543                 g_assert_not_reached ();
1544         }
1545 }
1546
1547 static int
1548 arg_storage_to_load_membase (ArgStorage storage)
1549 {
1550         switch (storage) {
1551         case ArgInIReg:
1552                 return OP_LOAD_MEMBASE;
1553         case ArgInDoubleSSEReg:
1554                 return OP_LOADR8_MEMBASE;
1555         case ArgInFloatSSEReg:
1556                 return OP_LOADR4_MEMBASE;
1557         default:
1558                 g_assert_not_reached ();
1559         }
1560
1561         return -1;
1562 }
1563
1564 static void
1565 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1566 {
1567         MonoInst *arg;
1568         MonoMethodSignature *tmp_sig;
1569         MonoInst *sig_arg;
1570
1571         if (call->tail_call)
1572                 NOT_IMPLEMENTED;
1573
1574         /* FIXME: Add support for signature tokens to AOT */
1575         cfg->disable_aot = TRUE;
1576
1577         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1578
1579         /*
1580          * mono_ArgIterator_Setup assumes the signature cookie is
1581          * passed first and all the arguments which were before it are
1582          * passed on the stack after the signature. So compensate by
1583          * passing a different signature.
1584          */
1585         tmp_sig = mono_metadata_signature_dup (call->signature);
1586         tmp_sig->param_count -= call->signature->sentinelpos;
1587         tmp_sig->sentinelpos = 0;
1588         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1589
1590         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1591         sig_arg->dreg = mono_alloc_ireg (cfg);
1592         sig_arg->inst_p0 = tmp_sig;
1593         MONO_ADD_INS (cfg->cbb, sig_arg);
1594
1595         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1596         arg->sreg1 = sig_arg->dreg;
1597         MONO_ADD_INS (cfg->cbb, arg);
1598 }
1599
1600 #define NEW_VARSTORE(cfg,dest,var,vartype,inst) do {    \
1601         MONO_INST_NEW ((cfg), (dest), OP_MOVE); \
1602                 (dest)->opcode = mono_type_to_regmove ((cfg), (vartype));    \
1603                 (dest)->klass = (var)->klass;   \
1604         (dest)->sreg1 = (inst)->dreg; \
1605                 (dest)->dreg = (var)->dreg;   \
1606         if ((dest)->opcode == OP_VMOVE) (dest)->klass = mono_class_from_mono_type ((vartype)); \
1607         } while (0)
1608
1609 #define NEW_ARGSTORE(cfg,dest,num,inst) NEW_VARSTORE ((cfg), (dest), cfg->args [(num)], cfg->arg_types [(num)], (inst))
1610
1611 #define EMIT_NEW_ARGSTORE(cfg,dest,num,inst) do { NEW_ARGSTORE ((cfg), (dest), (num), (inst)); MONO_ADD_INS ((cfg)->cbb, (dest)); } while (0)
1612
1613 void
1614 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1615 {
1616         MonoInst *arg, *in;
1617         MonoMethodSignature *sig;
1618         int i, n, stack_size;
1619         CallInfo *cinfo;
1620         ArgInfo *ainfo;
1621
1622         stack_size = 0;
1623
1624         sig = call->signature;
1625         n = sig->param_count + sig->hasthis;
1626
1627         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1628
1629         if (cinfo->need_stack_align) {
1630                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1631         }
1632
1633         /*
1634          * Emit all parameters passed in registers in non-reverse order for better readability
1635          * and to help the optimization in emit_prolog ().
1636          */
1637         for (i = 0; i < n; ++i) {
1638                 ainfo = cinfo->args + i;
1639
1640                 in = call->args [i];
1641
1642                 if (ainfo->storage == ArgInIReg)
1643                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1644         }
1645
1646         for (i = n - 1; i >= 0; --i) {
1647                 ainfo = cinfo->args + i;
1648
1649                 in = call->args [i];
1650
1651                 switch (ainfo->storage) {
1652                 case ArgInIReg:
1653                         /* Already done */
1654                         break;
1655                 case ArgInFloatSSEReg:
1656                 case ArgInDoubleSSEReg:
1657                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1658                         break;
1659                 case ArgOnStack:
1660                 case ArgValuetypeInReg:
1661                 case ArgValuetypeAddrInIReg:
1662                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1663                                 MonoInst *call_inst = (MonoInst*)call;
1664                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1665                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1666                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1667                                 guint32 align;
1668                                 guint32 size;
1669
1670                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1671                                         size = sizeof (MonoTypedRef);
1672                                         align = sizeof (gpointer);
1673                                 }
1674                                 else {
1675                                         if (sig->pinvoke)
1676                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1677                                         else {
1678                                                 /*
1679                                                  * Other backends use mono_type_stack_size (), but that
1680                                                  * aligns the size to 8, which is larger than the size of
1681                                                  * the source, leading to reads of invalid memory if the
1682                                                  * source is at the end of address space.
1683                                                  */
1684                                                 size = mono_class_value_size (in->klass, &align);
1685                                         }
1686                                 }
1687                                 g_assert (in->klass);
1688
1689                                 if (size > 0) {
1690                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1691                                         arg->sreg1 = in->dreg;
1692                                         arg->klass = in->klass;
1693                                         arg->backend.size = size;
1694                                         arg->inst_p0 = call;
1695                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1696                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1697
1698                                         MONO_ADD_INS (cfg->cbb, arg);
1699                                 }
1700                         } else {
1701                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1702                                 arg->sreg1 = in->dreg;
1703                                 if (!sig->params [i - sig->hasthis]->byref) {
1704                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1705                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1706                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
1707                                                 arg->inst_destbasereg = X86_ESP;
1708                                                 arg->inst_offset = 0;
1709                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1710                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1711                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
1712                                                 arg->inst_destbasereg = X86_ESP;
1713                                                 arg->inst_offset = 0;
1714                                         }
1715                                 }
1716                                 MONO_ADD_INS (cfg->cbb, arg);
1717                         }
1718                         break;
1719                 default:
1720                         g_assert_not_reached ();
1721                 }
1722
1723                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1724                         /* Emit the signature cookie just before the implicit arguments */
1725                         emit_sig_cookie (cfg, call, cinfo);
1726         }
1727
1728         /* Handle the case where there are no implicit arguments */
1729         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1730                 emit_sig_cookie (cfg, call, cinfo);
1731
1732         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1733                 MonoInst *vtarg;
1734
1735                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1736                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1737                                 /*
1738                                  * Tell the JIT to use a more efficient calling convention: call using
1739                                  * OP_CALL, compute the result location after the call, and save the
1740                                  * result there.
1741                                  */
1742                                 call->vret_in_reg = TRUE;
1743                                 /*
1744                                  * Nullify the instruction computing the vret addr to enable
1745                                  * future optimizations.
1746                                  */
1747                                 if (call->vret_var)
1748                                         NULLIFY_INS (call->vret_var);
1749                         } else {
1750                                 if (call->tail_call)
1751                                         NOT_IMPLEMENTED;
1752                                 /*
1753                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1754                                  * the stack. Push the address here, so the call instruction can
1755                                  * access it.
1756                                  */
1757                                 if (!cfg->arch.vret_addr_loc) {
1758                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1759                                         /* Prevent it from being register allocated or optimized away */
1760                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1761                                 }
1762
1763                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1764                         }
1765                 }
1766                 else {
1767                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1768                         vtarg->sreg1 = call->vret_var->dreg;
1769                         vtarg->dreg = mono_alloc_preg (cfg);
1770                         MONO_ADD_INS (cfg->cbb, vtarg);
1771
1772                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1773                 }
1774         }
1775
1776 #ifdef PLATFORM_WIN32
1777         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1778                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1779         }
1780 #endif
1781
1782         if (cfg->method->save_lmf) {
1783                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1784                 MONO_ADD_INS (cfg->cbb, arg);
1785         }
1786
1787         call->stack_usage = cinfo->stack_usage;
1788 }
1789
1790 void
1791 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1792 {
1793         MonoInst *arg;
1794         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1795         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1796         int size = ins->backend.size;
1797
1798         if (ainfo->storage == ArgValuetypeInReg) {
1799                 MonoInst *load;
1800                 int part;
1801
1802                 for (part = 0; part < 2; ++part) {
1803                         if (ainfo->pair_storage [part] == ArgNone)
1804                                 continue;
1805
1806                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
1807                         load->inst_basereg = src->dreg;
1808                         load->inst_offset = part * sizeof (gpointer);
1809
1810                         switch (ainfo->pair_storage [part]) {
1811                         case ArgInIReg:
1812                                 load->dreg = mono_alloc_ireg (cfg);
1813                                 break;
1814                         case ArgInDoubleSSEReg:
1815                         case ArgInFloatSSEReg:
1816                                 load->dreg = mono_alloc_freg (cfg);
1817                                 break;
1818                         default:
1819                                 g_assert_not_reached ();
1820                         }
1821                         MONO_ADD_INS (cfg->cbb, load);
1822
1823                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
1824                 }
1825         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
1826                 MonoInst *vtaddr, *load;
1827                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
1828
1829                 MONO_INST_NEW (cfg, load, OP_LDADDR);
1830                 load->inst_p0 = vtaddr;
1831                 vtaddr->flags |= MONO_INST_INDIRECT;
1832                 load->type = STACK_MP;
1833                 load->klass = vtaddr->klass;
1834                 load->dreg = mono_alloc_ireg (cfg);
1835                 MONO_ADD_INS (cfg->cbb, load);
1836                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
1837
1838                 if (ainfo->pair_storage [0] == ArgInIReg) {
1839                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
1840                         arg->dreg = mono_alloc_ireg (cfg);
1841                         arg->sreg1 = load->dreg;
1842                         arg->inst_imm = 0;
1843                         MONO_ADD_INS (cfg->cbb, arg);
1844                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
1845                 } else {
1846                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1847                         arg->sreg1 = load->dreg;
1848                         MONO_ADD_INS (cfg->cbb, arg);
1849                 }
1850         } else {
1851                 if (size == 8) {
1852                         /* Can't use this for < 8 since it does an 8 byte memory load */
1853                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1854                         arg->inst_basereg = src->dreg;
1855                         arg->inst_offset = 0;
1856                         MONO_ADD_INS (cfg->cbb, arg);
1857                 } else if (size <= 40) {
1858                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
1859                         mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1860                 } else {
1861                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1862                         arg->inst_basereg = src->dreg;
1863                         arg->inst_offset = 0;
1864                         arg->inst_imm = size;
1865                         MONO_ADD_INS (cfg->cbb, arg);
1866                 }
1867         }
1868 }
1869
1870 void
1871 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1872 {
1873         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
1874
1875         if (!ret->byref) {
1876                 if (ret->type == MONO_TYPE_R4) {
1877                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
1878                         return;
1879                 } else if (ret->type == MONO_TYPE_R8) {
1880                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1881                         return;
1882                 }
1883         }
1884
1885         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1886 }
1887
1888 #define EMIT_COND_BRANCH(ins,cond,sign) \
1889 if (ins->flags & MONO_INST_BRLABEL) { \
1890         if (ins->inst_i0->inst_c0) { \
1891                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1892         } else { \
1893                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1894                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1895                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1896                         x86_branch8 (code, cond, 0, sign); \
1897                 else \
1898                         x86_branch32 (code, cond, 0, sign); \
1899         } \
1900 } else { \
1901         if (ins->inst_true_bb->native_offset) { \
1902                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1903         } else { \
1904                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1905                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1906                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1907                         x86_branch8 (code, cond, 0, sign); \
1908                 else \
1909                         x86_branch32 (code, cond, 0, sign); \
1910         } \
1911 }
1912
1913 /* emit an exception if condition is fail */
1914 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1915         do {                                                        \
1916                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1917                 if (tins == NULL) {                                                                             \
1918                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1919                                         MONO_PATCH_INFO_EXC, exc_name);  \
1920                         x86_branch32 (code, cond, 0, signed);               \
1921                 } else {        \
1922                         EMIT_COND_BRANCH (tins, cond, signed);  \
1923                 }                       \
1924         } while (0);
1925
1926 #define EMIT_FPCOMPARE(code) do { \
1927         amd64_fcompp (code); \
1928         amd64_fnstsw (code); \
1929 } while (0);
1930
1931 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1932     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1933         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1934         amd64_ ##op (code); \
1935         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1936         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1937 } while (0);
1938
1939 static guint8*
1940 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1941 {
1942         gboolean no_patch = FALSE;
1943
1944         /*
1945          * FIXME: Add support for thunks
1946          */
1947         {
1948                 gboolean near_call = FALSE;
1949
1950                 /*
1951                  * Indirect calls are expensive so try to make a near call if possible.
1952                  * The caller memory is allocated by the code manager so it is
1953                  * guaranteed to be at a 32 bit offset.
1954                  */
1955
1956                 if (patch_type != MONO_PATCH_INFO_ABS) {
1957                         /* The target is in memory allocated using the code manager */
1958                         near_call = TRUE;
1959
1960                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1961                                 if (((MonoMethod*)data)->klass->image->aot_module)
1962                                         /* The callee might be an AOT method */
1963                                         near_call = FALSE;
1964                                 if (((MonoMethod*)data)->dynamic)
1965                                         /* The target is in malloc-ed memory */
1966                                         near_call = FALSE;
1967                         }
1968
1969                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1970                                 /*
1971                                  * The call might go directly to a native function without
1972                                  * the wrapper.
1973                                  */
1974                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1975                                 if (mi) {
1976                                         gconstpointer target = mono_icall_get_wrapper (mi);
1977                                         if ((((guint64)target) >> 32) != 0)
1978                                                 near_call = FALSE;
1979                                 }
1980                         }
1981                 }
1982                 else {
1983                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
1984                                 /*
1985                                  * This is not really an optimization, but required because the
1986                                  * generic class init trampolines use R11 to pass the vtable.
1987                                  */
1988                                 near_call = TRUE;
1989                         } else {
1990                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1991                                 if (info) {
1992                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1993                                                 strstr (cfg->method->name, info->name)) {
1994                                                 /* A call to the wrapped function */
1995                                                 if ((((guint64)data) >> 32) == 0)
1996                                                         near_call = TRUE;
1997                                                 no_patch = TRUE;
1998                                         }
1999                                         else if (info->func == info->wrapper) {
2000                                                 /* No wrapper */
2001                                                 if ((((guint64)info->func) >> 32) == 0)
2002                                                         near_call = TRUE;
2003                                         }
2004                                         else {
2005                                                 /* See the comment in mono_codegen () */
2006                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2007                                                         near_call = TRUE;
2008                                         }
2009                                 }
2010                                 else if ((((guint64)data) >> 32) == 0) {
2011                                         near_call = TRUE;
2012                                         no_patch = TRUE;
2013                                 }
2014                         }
2015                 }
2016
2017                 if (cfg->method->dynamic)
2018                         /* These methods are allocated using malloc */
2019                         near_call = FALSE;
2020
2021                 if (cfg->compile_aot) {
2022                         near_call = TRUE;
2023                         no_patch = TRUE;
2024                 }
2025
2026 #ifdef MONO_ARCH_NOMAP32BIT
2027                 near_call = FALSE;
2028 #endif
2029
2030                 if (near_call) {
2031                         /*
2032                          * Align the call displacement to an address divisible by 4 so it does
2033                          * not span cache lines. This is required for code patching to work on SMP
2034                          * systems.
2035                          */
2036                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2037                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2038                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2039                         amd64_call_code (code, 0);
2040                 }
2041                 else {
2042                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2043                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2044                         amd64_call_reg (code, GP_SCRATCH_REG);
2045                 }
2046         }
2047
2048         return code;
2049 }
2050
2051 static inline guint8*
2052 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2053 {
2054 #ifdef PLATFORM_WIN32
2055         if (win64_adjust_stack)
2056                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2057 #endif
2058         code = emit_call_body (cfg, code, patch_type, data);
2059 #ifdef PLATFORM_WIN32
2060         if (win64_adjust_stack)
2061                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2062 #endif
2063
2064         return code;
2065 }
2066
2067 static inline int
2068 store_membase_imm_to_store_membase_reg (int opcode)
2069 {
2070         switch (opcode) {
2071         case OP_STORE_MEMBASE_IMM:
2072                 return OP_STORE_MEMBASE_REG;
2073         case OP_STOREI4_MEMBASE_IMM:
2074                 return OP_STOREI4_MEMBASE_REG;
2075         case OP_STOREI8_MEMBASE_IMM:
2076                 return OP_STOREI8_MEMBASE_REG;
2077         }
2078
2079         return -1;
2080 }
2081
2082 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2083
2084 /*
2085  * mono_arch_peephole_pass_1:
2086  *
2087  *   Perform peephole opts which should/can be performed before local regalloc
2088  */
2089 void
2090 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2091 {
2092         MonoInst *ins, *n;
2093
2094         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2095                 MonoInst *last_ins = ins->prev;
2096
2097                 switch (ins->opcode) {
2098                 case OP_ADD_IMM:
2099                 case OP_IADD_IMM:
2100                 case OP_LADD_IMM:
2101                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2102                                 /*
2103                                  * X86_LEA is like ADD, but doesn't have the
2104                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2105                                  * its operand to 64 bit.
2106                                  */
2107                                 ins->opcode = OP_X86_LEA_MEMBASE;
2108                                 ins->inst_basereg = ins->sreg1;
2109                         }
2110                         break;
2111                 case OP_LXOR:
2112                 case OP_IXOR:
2113                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2114                                 MonoInst *ins2;
2115
2116                                 /*
2117                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2118                                  * the latter has length 2-3 instead of 6 (reverse constant
2119                                  * propagation). These instruction sequences are very common
2120                                  * in the initlocals bblock.
2121                                  */
2122                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2123                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2124                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2125                                                 ins2->sreg1 = ins->dreg;
2126                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2127                                                 /* Continue */
2128                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2129                                                 NULLIFY_INS (ins2);
2130                                                 /* Continue */
2131                                         } else {
2132                                                 break;
2133                                         }
2134                                 }
2135                         }
2136                         break;
2137                 case OP_COMPARE_IMM:
2138                 case OP_LCOMPARE_IMM:
2139                         /* OP_COMPARE_IMM (reg, 0)
2140                          * -->
2141                          * OP_AMD64_TEST_NULL (reg)
2142                          */
2143                         if (!ins->inst_imm)
2144                                 ins->opcode = OP_AMD64_TEST_NULL;
2145                         break;
2146                 case OP_ICOMPARE_IMM:
2147                         if (!ins->inst_imm)
2148                                 ins->opcode = OP_X86_TEST_NULL;
2149                         break;
2150                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2151                         /*
2152                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2153                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2154                          * -->
2155                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2156                          * OP_COMPARE_IMM reg, imm
2157                          *
2158                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2159                          */
2160                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2161                             ins->inst_basereg == last_ins->inst_destbasereg &&
2162                             ins->inst_offset == last_ins->inst_offset) {
2163                                         ins->opcode = OP_ICOMPARE_IMM;
2164                                         ins->sreg1 = last_ins->sreg1;
2165
2166                                         /* check if we can remove cmp reg,0 with test null */
2167                                         if (!ins->inst_imm)
2168                                                 ins->opcode = OP_X86_TEST_NULL;
2169                                 }
2170
2171                         break;
2172                 }
2173
2174                 mono_peephole_ins (bb, ins);
2175         }
2176 }
2177
2178 void
2179 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2180 {
2181         MonoInst *ins, *n;
2182
2183         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2184                 switch (ins->opcode) {
2185                 case OP_ICONST:
2186                 case OP_I8CONST: {
2187                         /* reg = 0 -> XOR (reg, reg) */
2188                         /* XOR sets cflags on x86, so we cant do it always */
2189                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2190                                 ins->opcode = OP_LXOR;
2191                                 ins->sreg1 = ins->dreg;
2192                                 ins->sreg2 = ins->dreg;
2193                                 /* Fall through */
2194                         } else {
2195                                 break;
2196                         }
2197                 }
2198                 case OP_LXOR:
2199                         /*
2200                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2201                          * 0 result into 64 bits.
2202                          */
2203                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2204                                 ins->opcode = OP_IXOR;
2205                         }
2206                         /* Fall through */
2207                 case OP_IXOR:
2208                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2209                                 MonoInst *ins2;
2210
2211                                 /*
2212                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2213                                  * the latter has length 2-3 instead of 6 (reverse constant
2214                                  * propagation). These instruction sequences are very common
2215                                  * in the initlocals bblock.
2216                                  */
2217                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2218                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2219                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2220                                                 ins2->sreg1 = ins->dreg;
2221                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2222                                                 /* Continue */
2223                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2224                                                 NULLIFY_INS (ins2);
2225                                                 /* Continue */
2226                                         } else {
2227                                                 break;
2228                                         }
2229                                 }
2230                         }
2231                         break;
2232                 case OP_IADD_IMM:
2233                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2234                                 ins->opcode = OP_X86_INC_REG;
2235                         break;
2236                 case OP_ISUB_IMM:
2237                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2238                                 ins->opcode = OP_X86_DEC_REG;
2239                         break;
2240                 }
2241
2242                 mono_peephole_ins (bb, ins);
2243         }
2244 }
2245
2246 #define NEW_INS(cfg,ins,dest,op) do {   \
2247                 MONO_INST_NEW ((cfg), (dest), (op)); \
2248         (dest)->cil_code = (ins)->cil_code; \
2249         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2250         } while (0)
2251
2252 /*
2253  * mono_arch_lowering_pass:
2254  *
2255  *  Converts complex opcodes into simpler ones so that each IR instruction
2256  * corresponds to one machine instruction.
2257  */
2258 void
2259 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2260 {
2261         MonoInst *ins, *n, *temp;
2262
2263         if (bb->max_vreg > cfg->rs->next_vreg)
2264                 cfg->rs->next_vreg = bb->max_vreg;
2265
2266         /*
2267          * FIXME: Need to add more instructions, but the current machine
2268          * description can't model some parts of the composite instructions like
2269          * cdq.
2270          */
2271         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2272                 switch (ins->opcode) {
2273                 case OP_DIV_IMM:
2274                 case OP_REM_IMM:
2275                 case OP_IDIV_IMM:
2276                 case OP_IDIV_UN_IMM:
2277                 case OP_IREM_UN_IMM:
2278                         mono_decompose_op_imm (cfg, bb, ins);
2279                         break;
2280                 case OP_IREM_IMM:
2281                         /* Keep the opcode if we can implement it efficiently */
2282                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2283                                 mono_decompose_op_imm (cfg, bb, ins);
2284                         break;
2285                 case OP_COMPARE_IMM:
2286                 case OP_LCOMPARE_IMM:
2287                         if (!amd64_is_imm32 (ins->inst_imm)) {
2288                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2289                                 temp->inst_c0 = ins->inst_imm;
2290                                 if (cfg->globalra)
2291                                         temp->dreg = mono_alloc_ireg (cfg);
2292                                 else
2293                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2294                                 ins->opcode = OP_COMPARE;
2295                                 ins->sreg2 = temp->dreg;
2296                         }
2297                         break;
2298                 case OP_LOAD_MEMBASE:
2299                 case OP_LOADI8_MEMBASE:
2300                         if (!amd64_is_imm32 (ins->inst_offset)) {
2301                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2302                                 temp->inst_c0 = ins->inst_offset;
2303                                 if (cfg->globalra)
2304                                         temp->dreg = mono_alloc_ireg (cfg);
2305                                 else
2306                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2307                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2308                                 ins->inst_indexreg = temp->dreg;
2309                         }
2310                         break;
2311                 case OP_STORE_MEMBASE_IMM:
2312                 case OP_STOREI8_MEMBASE_IMM:
2313                         if (!amd64_is_imm32 (ins->inst_imm)) {
2314                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2315                                 temp->inst_c0 = ins->inst_imm;
2316                                 if (cfg->globalra)
2317                                         temp->dreg = mono_alloc_ireg (cfg);
2318                                 else
2319                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2320                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2321                                 ins->sreg1 = temp->dreg;
2322                         }
2323                         break;
2324                 default:
2325                         break;
2326                 }
2327         }
2328
2329         bb->max_vreg = cfg->rs->next_vreg;
2330 }
2331
2332 static const int
2333 branch_cc_table [] = {
2334         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2335         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2336         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2337 };
2338
2339 /* Maps CMP_... constants to X86_CC_... constants */
2340 static const int
2341 cc_table [] = {
2342         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2343         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2344 };
2345
2346 static const int
2347 cc_signed_table [] = {
2348         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2349         FALSE, FALSE, FALSE, FALSE
2350 };
2351
2352 /*#include "cprop.c"*/
2353
2354 static unsigned char*
2355 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2356 {
2357         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2358
2359         if (size == 1)
2360                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2361         else if (size == 2)
2362                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2363         return code;
2364 }
2365
2366 static unsigned char*
2367 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2368 {
2369         int sreg = tree->sreg1;
2370         int need_touch = FALSE;
2371
2372 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2373         if (!tree->flags & MONO_INST_INIT)
2374                 need_touch = TRUE;
2375 #endif
2376
2377         if (need_touch) {
2378                 guint8* br[5];
2379
2380                 /*
2381                  * Under Windows:
2382                  * If requested stack size is larger than one page,
2383                  * perform stack-touch operation
2384                  */
2385                 /*
2386                  * Generate stack probe code.
2387                  * Under Windows, it is necessary to allocate one page at a time,
2388                  * "touching" stack after each successful sub-allocation. This is
2389                  * because of the way stack growth is implemented - there is a
2390                  * guard page before the lowest stack page that is currently commited.
2391                  * Stack normally grows sequentially so OS traps access to the
2392                  * guard page and commits more pages when needed.
2393                  */
2394                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2395                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2396
2397                 br[2] = code; /* loop */
2398                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2399                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2400                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2401                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2402                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2403                 amd64_patch (br[3], br[2]);
2404                 amd64_test_reg_reg (code, sreg, sreg);
2405                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2406                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2407
2408                 br[1] = code; x86_jump8 (code, 0);
2409
2410                 amd64_patch (br[0], code);
2411                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2412                 amd64_patch (br[1], code);
2413                 amd64_patch (br[4], code);
2414         }
2415         else
2416                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2417
2418         if (tree->flags & MONO_INST_INIT) {
2419                 int offset = 0;
2420                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2421                         amd64_push_reg (code, AMD64_RAX);
2422                         offset += 8;
2423                 }
2424                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2425                         amd64_push_reg (code, AMD64_RCX);
2426                         offset += 8;
2427                 }
2428                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2429                         amd64_push_reg (code, AMD64_RDI);
2430                         offset += 8;
2431                 }
2432
2433                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2434                 if (sreg != AMD64_RCX)
2435                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2436                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2437
2438                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2439                 amd64_cld (code);
2440                 amd64_prefix (code, X86_REP_PREFIX);
2441                 amd64_stosl (code);
2442
2443                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2444                         amd64_pop_reg (code, AMD64_RDI);
2445                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2446                         amd64_pop_reg (code, AMD64_RCX);
2447                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2448                         amd64_pop_reg (code, AMD64_RAX);
2449         }
2450         return code;
2451 }
2452
2453 static guint8*
2454 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2455 {
2456         CallInfo *cinfo;
2457         guint32 quad;
2458
2459         /* Move return value to the target register */
2460         /* FIXME: do this in the local reg allocator */
2461         switch (ins->opcode) {
2462         case OP_CALL:
2463         case OP_CALL_REG:
2464         case OP_CALL_MEMBASE:
2465         case OP_LCALL:
2466         case OP_LCALL_REG:
2467         case OP_LCALL_MEMBASE:
2468                 g_assert (ins->dreg == AMD64_RAX);
2469                 break;
2470         case OP_FCALL:
2471         case OP_FCALL_REG:
2472         case OP_FCALL_MEMBASE:
2473                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2474                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2475                 }
2476                 else {
2477                         if (ins->dreg != AMD64_XMM0)
2478                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2479                 }
2480                 break;
2481         case OP_VCALL:
2482         case OP_VCALL_REG:
2483         case OP_VCALL_MEMBASE:
2484         case OP_VCALL2:
2485         case OP_VCALL2_REG:
2486         case OP_VCALL2_MEMBASE:
2487                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2488                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2489                         MonoInst *loc = cfg->arch.vret_addr_loc;
2490
2491                         /* Load the destination address */
2492                         g_assert (loc->opcode == OP_REGOFFSET);
2493                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2494
2495                         for (quad = 0; quad < 2; quad ++) {
2496                                 switch (cinfo->ret.pair_storage [quad]) {
2497                                 case ArgInIReg:
2498                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2499                                         break;
2500                                 case ArgInFloatSSEReg:
2501                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2502                                         break;
2503                                 case ArgInDoubleSSEReg:
2504                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2505                                         break;
2506                                 case ArgNone:
2507                                         break;
2508                                 default:
2509                                         NOT_IMPLEMENTED;
2510                                 }
2511                         }
2512                 }
2513                 break;
2514         }
2515
2516         return code;
2517 }
2518
2519 /*
2520  * mono_amd64_emit_tls_get:
2521  * @code: buffer to store code to
2522  * @dreg: hard register where to place the result
2523  * @tls_offset: offset info
2524  *
2525  * mono_amd64_emit_tls_get emits in @code the native code that puts in
2526  * the dreg register the item in the thread local storage identified
2527  * by tls_offset.
2528  *
2529  * Returns: a pointer to the end of the stored code
2530  */
2531 guint8*
2532 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2533 {
2534 #ifdef PLATFORM_WIN32
2535         g_assert (tls_offset < 64);
2536         x86_prefix (code, X86_GS_PREFIX);
2537         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2538 #else
2539         if (optimize_for_xen) {
2540                 x86_prefix (code, X86_FS_PREFIX);
2541                 amd64_mov_reg_mem (code, dreg, 0, 8);
2542                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2543         } else {
2544                 x86_prefix (code, X86_FS_PREFIX);
2545                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2546         }
2547 #endif
2548         return code;
2549 }
2550
2551 /*
2552  * emit_load_volatile_arguments:
2553  *
2554  *  Load volatile arguments from the stack to the original input registers.
2555  * Required before a tail call.
2556  */
2557 static guint8*
2558 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2559 {
2560         MonoMethod *method = cfg->method;
2561         MonoMethodSignature *sig;
2562         MonoInst *ins;
2563         CallInfo *cinfo;
2564         guint32 i, quad;
2565
2566         /* FIXME: Generate intermediate code instead */
2567
2568         sig = mono_method_signature (method);
2569
2570         cinfo = cfg->arch.cinfo;
2571
2572         /* This is the opposite of the code in emit_prolog */
2573         if (sig->ret->type != MONO_TYPE_VOID) {
2574                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2575                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2576         }
2577
2578         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2579                 ArgInfo *ainfo = cinfo->args + i;
2580                 MonoType *arg_type;
2581                 ins = cfg->args [i];
2582
2583                 if (sig->hasthis && (i == 0))
2584                         arg_type = &mono_defaults.object_class->byval_arg;
2585                 else
2586                         arg_type = sig->params [i - sig->hasthis];
2587
2588                 if (ins->opcode != OP_REGVAR) {
2589                         switch (ainfo->storage) {
2590                         case ArgInIReg: {
2591                                 guint32 size = 8;
2592
2593                                 /* FIXME: I1 etc */
2594                                 amd64_mov_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset, size);
2595                                 break;
2596                         }
2597                         case ArgInFloatSSEReg:
2598                                 amd64_movss_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2599                                 break;
2600                         case ArgInDoubleSSEReg:
2601                                 amd64_movsd_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2602                                 break;
2603                         case ArgValuetypeInReg:
2604                                 for (quad = 0; quad < 2; quad ++) {
2605                                         switch (ainfo->pair_storage [quad]) {
2606                                         case ArgInIReg:
2607                                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
2608                                                 break;
2609                                         case ArgInFloatSSEReg:
2610                                         case ArgInDoubleSSEReg:
2611                                                 g_assert_not_reached ();
2612                                                 break;
2613                                         case ArgNone:
2614                                                 break;
2615                                         default:
2616                                                 g_assert_not_reached ();
2617                                         }
2618                                 }
2619                                 break;
2620                         case ArgValuetypeAddrInIReg:
2621                                 if (ainfo->pair_storage [0] == ArgInIReg)
2622                                         amd64_mov_reg_membase (code, ainfo->pair_regs [0], ins->inst_left->inst_basereg, ins->inst_left->inst_offset,  sizeof (gpointer));
2623                                 break;
2624                         default:
2625                                 break;
2626                         }
2627                 }
2628                 else {
2629                         g_assert (ainfo->storage == ArgInIReg);
2630
2631                         amd64_mov_reg_reg (code, ainfo->reg, ins->dreg, 8);
2632                 }
2633         }
2634
2635         return code;
2636 }
2637
2638 #define REAL_PRINT_REG(text,reg) \
2639 mono_assert (reg >= 0); \
2640 amd64_push_reg (code, AMD64_RAX); \
2641 amd64_push_reg (code, AMD64_RDX); \
2642 amd64_push_reg (code, AMD64_RCX); \
2643 amd64_push_reg (code, reg); \
2644 amd64_push_imm (code, reg); \
2645 amd64_push_imm (code, text " %d %p\n"); \
2646 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2647 amd64_call_reg (code, AMD64_RAX); \
2648 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2649 amd64_pop_reg (code, AMD64_RCX); \
2650 amd64_pop_reg (code, AMD64_RDX); \
2651 amd64_pop_reg (code, AMD64_RAX);
2652
2653 /* benchmark and set based on cpu */
2654 #define LOOP_ALIGNMENT 8
2655 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2656
2657 #ifndef DISABLE_JIT
2658
2659 void
2660 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2661 {
2662         MonoInst *ins;
2663         MonoCallInst *call;
2664         guint offset;
2665         guint8 *code = cfg->native_code + cfg->code_len;
2666         MonoInst *last_ins = NULL;
2667         guint last_offset = 0;
2668         int max_len, cpos;
2669
2670         if (cfg->opt & MONO_OPT_LOOP) {
2671                 int pad, align = LOOP_ALIGNMENT;
2672                 /* set alignment depending on cpu */
2673                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2674                         pad = align - pad;
2675                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2676                         amd64_padding (code, pad);
2677                         cfg->code_len += pad;
2678                         bb->native_offset = cfg->code_len;
2679                 }
2680         }
2681
2682         if (cfg->verbose_level > 2)
2683                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2684
2685         cpos = bb->max_offset;
2686
2687         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2688                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2689                 g_assert (!cfg->compile_aot);
2690                 cpos += 6;
2691
2692                 cov->data [bb->dfn].cil_code = bb->cil_code;
2693                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2694                 /* this is not thread save, but good enough */
2695                 amd64_inc_membase (code, AMD64_R11, 0);
2696         }
2697
2698         offset = code - cfg->native_code;
2699
2700         mono_debug_open_block (cfg, bb, offset);
2701
2702     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2703                 x86_breakpoint (code);
2704
2705         MONO_BB_FOR_EACH_INS (bb, ins) {
2706                 offset = code - cfg->native_code;
2707
2708                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2709
2710                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2711                         cfg->code_size *= 2;
2712                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2713                         code = cfg->native_code + offset;
2714                         mono_jit_stats.code_reallocs++;
2715                 }
2716
2717                 if (cfg->debug_info)
2718                         mono_debug_record_line_number (cfg, ins, offset);
2719
2720                 switch (ins->opcode) {
2721                 case OP_BIGMUL:
2722                         amd64_mul_reg (code, ins->sreg2, TRUE);
2723                         break;
2724                 case OP_BIGMUL_UN:
2725                         amd64_mul_reg (code, ins->sreg2, FALSE);
2726                         break;
2727                 case OP_X86_SETEQ_MEMBASE:
2728                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2729                         break;
2730                 case OP_STOREI1_MEMBASE_IMM:
2731                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2732                         break;
2733                 case OP_STOREI2_MEMBASE_IMM:
2734                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2735                         break;
2736                 case OP_STOREI4_MEMBASE_IMM:
2737                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2738                         break;
2739                 case OP_STOREI1_MEMBASE_REG:
2740                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2741                         break;
2742                 case OP_STOREI2_MEMBASE_REG:
2743                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2744                         break;
2745                 case OP_STORE_MEMBASE_REG:
2746                 case OP_STOREI8_MEMBASE_REG:
2747                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2748                         break;
2749                 case OP_STOREI4_MEMBASE_REG:
2750                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2751                         break;
2752                 case OP_STORE_MEMBASE_IMM:
2753                 case OP_STOREI8_MEMBASE_IMM:
2754                         g_assert (amd64_is_imm32 (ins->inst_imm));
2755                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2756                         break;
2757                 case OP_LOAD_MEM:
2758                 case OP_LOADI8_MEM:
2759                         // FIXME: Decompose this earlier
2760                         if (amd64_is_imm32 (ins->inst_imm))
2761                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2762                         else {
2763                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2764                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2765                         }
2766                         break;
2767                 case OP_LOADI4_MEM:
2768                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2769                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2770                         break;
2771                 case OP_LOADU4_MEM:
2772                         // FIXME: Decompose this earlier
2773                         if (amd64_is_imm32 (ins->inst_imm))
2774                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2775                         else {
2776                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2777                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2778                         }
2779                         break;
2780                 case OP_LOADU1_MEM:
2781                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2782                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2783                         break;
2784                 case OP_LOADU2_MEM:
2785                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2786                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2787                         break;
2788                 case OP_LOAD_MEMBASE:
2789                 case OP_LOADI8_MEMBASE:
2790                         g_assert (amd64_is_imm32 (ins->inst_offset));
2791                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2792                         break;
2793                 case OP_LOADI4_MEMBASE:
2794                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2795                         break;
2796                 case OP_LOADU4_MEMBASE:
2797                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2798                         break;
2799                 case OP_LOADU1_MEMBASE:
2800                         /* The cpu zero extends the result into 64 bits */
2801                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2802                         break;
2803                 case OP_LOADI1_MEMBASE:
2804                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2805                         break;
2806                 case OP_LOADU2_MEMBASE:
2807                         /* The cpu zero extends the result into 64 bits */
2808                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2809                         break;
2810                 case OP_LOADI2_MEMBASE:
2811                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2812                         break;
2813                 case OP_AMD64_LOADI8_MEMINDEX:
2814                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2815                         break;
2816                 case OP_LCONV_TO_I1:
2817                 case OP_ICONV_TO_I1:
2818                 case OP_SEXT_I1:
2819                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2820                         break;
2821                 case OP_LCONV_TO_I2:
2822                 case OP_ICONV_TO_I2:
2823                 case OP_SEXT_I2:
2824                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2825                         break;
2826                 case OP_LCONV_TO_U1:
2827                 case OP_ICONV_TO_U1:
2828                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2829                         break;
2830                 case OP_LCONV_TO_U2:
2831                 case OP_ICONV_TO_U2:
2832                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2833                         break;
2834                 case OP_ZEXT_I4:
2835                         /* Clean out the upper word */
2836                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2837                         break;
2838                 case OP_SEXT_I4:
2839                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2840                         break;
2841                 case OP_COMPARE:
2842                 case OP_LCOMPARE:
2843                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2844                         break;
2845                 case OP_COMPARE_IMM:
2846                 case OP_LCOMPARE_IMM:
2847                         g_assert (amd64_is_imm32 (ins->inst_imm));
2848                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2849                         break;
2850                 case OP_X86_COMPARE_REG_MEMBASE:
2851                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2852                         break;
2853                 case OP_X86_TEST_NULL:
2854                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2855                         break;
2856                 case OP_AMD64_TEST_NULL:
2857                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2858                         break;
2859
2860                 case OP_X86_ADD_REG_MEMBASE:
2861                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2862                         break;
2863                 case OP_X86_SUB_REG_MEMBASE:
2864                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2865                         break;
2866                 case OP_X86_AND_REG_MEMBASE:
2867                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2868                         break;
2869                 case OP_X86_OR_REG_MEMBASE:
2870                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2871                         break;
2872                 case OP_X86_XOR_REG_MEMBASE:
2873                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2874                         break;
2875
2876                 case OP_X86_ADD_MEMBASE_IMM:
2877                         /* FIXME: Make a 64 version too */
2878                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2879                         break;
2880                 case OP_X86_SUB_MEMBASE_IMM:
2881                         g_assert (amd64_is_imm32 (ins->inst_imm));
2882                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2883                         break;
2884                 case OP_X86_AND_MEMBASE_IMM:
2885                         g_assert (amd64_is_imm32 (ins->inst_imm));
2886                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2887                         break;
2888                 case OP_X86_OR_MEMBASE_IMM:
2889                         g_assert (amd64_is_imm32 (ins->inst_imm));
2890                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2891                         break;
2892                 case OP_X86_XOR_MEMBASE_IMM:
2893                         g_assert (amd64_is_imm32 (ins->inst_imm));
2894                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2895                         break;
2896                 case OP_X86_ADD_MEMBASE_REG:
2897                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2898                         break;
2899                 case OP_X86_SUB_MEMBASE_REG:
2900                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2901                         break;
2902                 case OP_X86_AND_MEMBASE_REG:
2903                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2904                         break;
2905                 case OP_X86_OR_MEMBASE_REG:
2906                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2907                         break;
2908                 case OP_X86_XOR_MEMBASE_REG:
2909                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2910                         break;
2911                 case OP_X86_INC_MEMBASE:
2912                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2913                         break;
2914                 case OP_X86_INC_REG:
2915                         amd64_inc_reg_size (code, ins->dreg, 4);
2916                         break;
2917                 case OP_X86_DEC_MEMBASE:
2918                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2919                         break;
2920                 case OP_X86_DEC_REG:
2921                         amd64_dec_reg_size (code, ins->dreg, 4);
2922                         break;
2923                 case OP_X86_MUL_REG_MEMBASE:
2924                 case OP_X86_MUL_MEMBASE_REG:
2925                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2926                         break;
2927                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2928                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2929                         break;
2930                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2931                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2932                         break;
2933                 case OP_AMD64_COMPARE_MEMBASE_REG:
2934                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2935                         break;
2936                 case OP_AMD64_COMPARE_MEMBASE_IMM:
2937                         g_assert (amd64_is_imm32 (ins->inst_imm));
2938                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2939                         break;
2940                 case OP_X86_COMPARE_MEMBASE8_IMM:
2941                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2942                         break;
2943                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2944                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2945                         break;
2946                 case OP_AMD64_COMPARE_REG_MEMBASE:
2947                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2948                         break;
2949
2950                 case OP_AMD64_ADD_REG_MEMBASE:
2951                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2952                         break;
2953                 case OP_AMD64_SUB_REG_MEMBASE:
2954                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2955                         break;
2956                 case OP_AMD64_AND_REG_MEMBASE:
2957                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2958                         break;
2959                 case OP_AMD64_OR_REG_MEMBASE:
2960                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2961                         break;
2962                 case OP_AMD64_XOR_REG_MEMBASE:
2963                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2964                         break;
2965
2966                 case OP_AMD64_ADD_MEMBASE_REG:
2967                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2968                         break;
2969                 case OP_AMD64_SUB_MEMBASE_REG:
2970                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2971                         break;
2972                 case OP_AMD64_AND_MEMBASE_REG:
2973                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2974                         break;
2975                 case OP_AMD64_OR_MEMBASE_REG:
2976                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2977                         break;
2978                 case OP_AMD64_XOR_MEMBASE_REG:
2979                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2980                         break;
2981
2982                 case OP_AMD64_ADD_MEMBASE_IMM:
2983                         g_assert (amd64_is_imm32 (ins->inst_imm));
2984                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2985                         break;
2986                 case OP_AMD64_SUB_MEMBASE_IMM:
2987                         g_assert (amd64_is_imm32 (ins->inst_imm));
2988                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2989                         break;
2990                 case OP_AMD64_AND_MEMBASE_IMM:
2991                         g_assert (amd64_is_imm32 (ins->inst_imm));
2992                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2993                         break;
2994                 case OP_AMD64_OR_MEMBASE_IMM:
2995                         g_assert (amd64_is_imm32 (ins->inst_imm));
2996                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2997                         break;
2998                 case OP_AMD64_XOR_MEMBASE_IMM:
2999                         g_assert (amd64_is_imm32 (ins->inst_imm));
3000                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3001                         break;
3002
3003                 case OP_BREAK:
3004                         amd64_breakpoint (code);
3005                         break;
3006                 case OP_RELAXED_NOP:
3007                         x86_prefix (code, X86_REP_PREFIX);
3008                         x86_nop (code);
3009                         break;
3010                 case OP_HARD_NOP:
3011                         x86_nop (code);
3012                         break;
3013                 case OP_NOP:
3014                 case OP_DUMMY_USE:
3015                 case OP_DUMMY_STORE:
3016                 case OP_NOT_REACHED:
3017                 case OP_NOT_NULL:
3018                         break;
3019                 case OP_ADDCC:
3020                 case OP_LADD:
3021                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3022                         break;
3023                 case OP_ADC:
3024                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3025                         break;
3026                 case OP_ADD_IMM:
3027                 case OP_LADD_IMM:
3028                         g_assert (amd64_is_imm32 (ins->inst_imm));
3029                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3030                         break;
3031                 case OP_ADC_IMM:
3032                         g_assert (amd64_is_imm32 (ins->inst_imm));
3033                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3034                         break;
3035                 case OP_SUBCC:
3036                 case OP_LSUB:
3037                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3038                         break;
3039                 case OP_SBB:
3040                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3041                         break;
3042                 case OP_SUB_IMM:
3043                 case OP_LSUB_IMM:
3044                         g_assert (amd64_is_imm32 (ins->inst_imm));
3045                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3046                         break;
3047                 case OP_SBB_IMM:
3048                         g_assert (amd64_is_imm32 (ins->inst_imm));
3049                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3050                         break;
3051                 case OP_LAND:
3052                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3053                         break;
3054                 case OP_AND_IMM:
3055                 case OP_LAND_IMM:
3056                         g_assert (amd64_is_imm32 (ins->inst_imm));
3057                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3058                         break;
3059                 case OP_LMUL:
3060                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3061                         break;
3062                 case OP_MUL_IMM:
3063                 case OP_LMUL_IMM:
3064                 case OP_IMUL_IMM: {
3065                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3066
3067                         switch (ins->inst_imm) {
3068                         case 2:
3069                                 /* MOV r1, r2 */
3070                                 /* ADD r1, r1 */
3071                                 if (ins->dreg != ins->sreg1)
3072                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3073                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3074                                 break;
3075                         case 3:
3076                                 /* LEA r1, [r2 + r2*2] */
3077                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3078                                 break;
3079                         case 5:
3080                                 /* LEA r1, [r2 + r2*4] */
3081                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3082                                 break;
3083                         case 6:
3084                                 /* LEA r1, [r2 + r2*2] */
3085                                 /* ADD r1, r1          */
3086                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3087                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3088                                 break;
3089                         case 9:
3090                                 /* LEA r1, [r2 + r2*8] */
3091                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3092                                 break;
3093                         case 10:
3094                                 /* LEA r1, [r2 + r2*4] */
3095                                 /* ADD r1, r1          */
3096                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3097                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3098                                 break;
3099                         case 12:
3100                                 /* LEA r1, [r2 + r2*2] */
3101                                 /* SHL r1, 2           */
3102                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3103                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3104                                 break;
3105                         case 25:
3106                                 /* LEA r1, [r2 + r2*4] */
3107                                 /* LEA r1, [r1 + r1*4] */
3108                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3109                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3110                                 break;
3111                         case 100:
3112                                 /* LEA r1, [r2 + r2*4] */
3113                                 /* SHL r1, 2           */
3114                                 /* LEA r1, [r1 + r1*4] */
3115                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3116                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3117                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3118                                 break;
3119                         default:
3120                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3121                                 break;
3122                         }
3123                         break;
3124                 }
3125                 case OP_LDIV:
3126                 case OP_LREM:
3127                         /* Regalloc magic makes the div/rem cases the same */
3128                         if (ins->sreg2 == AMD64_RDX) {
3129                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3130                                 amd64_cdq (code);
3131                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3132                         } else {
3133                                 amd64_cdq (code);
3134                                 amd64_div_reg (code, ins->sreg2, TRUE);
3135                         }
3136                         break;
3137                 case OP_LDIV_UN:
3138                 case OP_LREM_UN:
3139                         if (ins->sreg2 == AMD64_RDX) {
3140                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3141                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3142                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3143                         } else {
3144                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3145                                 amd64_div_reg (code, ins->sreg2, FALSE);
3146                         }
3147                         break;
3148                 case OP_IDIV:
3149                 case OP_IREM:
3150                         if (ins->sreg2 == AMD64_RDX) {
3151                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3152                                 amd64_cdq_size (code, 4);
3153                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3154                         } else {
3155                                 amd64_cdq_size (code, 4);
3156                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3157                         }
3158                         break;
3159                 case OP_IDIV_UN:
3160                 case OP_IREM_UN:
3161                         if (ins->sreg2 == AMD64_RDX) {
3162                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3163                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3164                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3165                         } else {
3166                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3167                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3168                         }
3169                         break;
3170                 case OP_IREM_IMM: {
3171                         int power = mono_is_power_of_two (ins->inst_imm);
3172
3173                         g_assert (ins->sreg1 == X86_EAX);
3174                         g_assert (ins->dreg == X86_EAX);
3175                         g_assert (power >= 0);
3176
3177                         /* Based on gcc code */
3178
3179                         /* Add compensation for negative dividents */
3180                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3181                         if (power > 1)
3182                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3183                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3184                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3185                         /* Compute remainder */
3186                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3187                         /* Remove compensation */
3188                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3189                         break;
3190                 }
3191                 case OP_LMUL_OVF:
3192                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3193                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3194                         break;
3195                 case OP_LOR:
3196                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3197                         break;
3198                 case OP_OR_IMM:
3199                 case OP_LOR_IMM:
3200                         g_assert (amd64_is_imm32 (ins->inst_imm));
3201                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3202                         break;
3203                 case OP_LXOR:
3204                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3205                         break;
3206                 case OP_XOR_IMM:
3207                 case OP_LXOR_IMM:
3208                         g_assert (amd64_is_imm32 (ins->inst_imm));
3209                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3210                         break;
3211                 case OP_LSHL:
3212                         g_assert (ins->sreg2 == AMD64_RCX);
3213                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3214                         break;
3215                 case OP_LSHR:
3216                         g_assert (ins->sreg2 == AMD64_RCX);
3217                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3218                         break;
3219                 case OP_SHR_IMM:
3220                         g_assert (amd64_is_imm32 (ins->inst_imm));
3221                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3222                         break;
3223                 case OP_LSHR_IMM:
3224                         g_assert (amd64_is_imm32 (ins->inst_imm));
3225                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3226                         break;
3227                 case OP_SHR_UN_IMM:
3228                         g_assert (amd64_is_imm32 (ins->inst_imm));
3229                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3230                         break;
3231                 case OP_LSHR_UN_IMM:
3232                         g_assert (amd64_is_imm32 (ins->inst_imm));
3233                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3234                         break;
3235                 case OP_LSHR_UN:
3236                         g_assert (ins->sreg2 == AMD64_RCX);
3237                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3238                         break;
3239                 case OP_SHL_IMM:
3240                         g_assert (amd64_is_imm32 (ins->inst_imm));
3241                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3242                         break;
3243                 case OP_LSHL_IMM:
3244                         g_assert (amd64_is_imm32 (ins->inst_imm));
3245                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3246                         break;
3247
3248                 case OP_IADDCC:
3249                 case OP_IADD:
3250                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3251                         break;
3252                 case OP_IADC:
3253                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3254                         break;
3255                 case OP_IADD_IMM:
3256                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3257                         break;
3258                 case OP_IADC_IMM:
3259                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3260                         break;
3261                 case OP_ISUBCC:
3262                 case OP_ISUB:
3263                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3264                         break;
3265                 case OP_ISBB:
3266                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3267                         break;
3268                 case OP_ISUB_IMM:
3269                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3270                         break;
3271                 case OP_ISBB_IMM:
3272                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3273                         break;
3274                 case OP_IAND:
3275                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3276                         break;
3277                 case OP_IAND_IMM:
3278                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3279                         break;
3280                 case OP_IOR:
3281                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3282                         break;
3283                 case OP_IOR_IMM:
3284                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3285                         break;
3286                 case OP_IXOR:
3287                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3288                         break;
3289                 case OP_IXOR_IMM:
3290                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3291                         break;
3292                 case OP_INEG:
3293                         amd64_neg_reg_size (code, ins->sreg1, 4);
3294                         break;
3295                 case OP_INOT:
3296                         amd64_not_reg_size (code, ins->sreg1, 4);
3297                         break;
3298                 case OP_ISHL:
3299                         g_assert (ins->sreg2 == AMD64_RCX);
3300                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3301                         break;
3302                 case OP_ISHR:
3303                         g_assert (ins->sreg2 == AMD64_RCX);
3304                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3305                         break;
3306                 case OP_ISHR_IMM:
3307                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3308                         break;
3309                 case OP_ISHR_UN_IMM:
3310                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3311                         break;
3312                 case OP_ISHR_UN:
3313                         g_assert (ins->sreg2 == AMD64_RCX);
3314                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3315                         break;
3316                 case OP_ISHL_IMM:
3317                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3318                         break;
3319                 case OP_IMUL:
3320                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3321                         break;
3322                 case OP_IMUL_OVF:
3323                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3324                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3325                         break;
3326                 case OP_IMUL_OVF_UN:
3327                 case OP_LMUL_OVF_UN: {
3328                         /* the mul operation and the exception check should most likely be split */
3329                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3330                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3331                         /*g_assert (ins->sreg2 == X86_EAX);
3332                         g_assert (ins->dreg == X86_EAX);*/
3333                         if (ins->sreg2 == X86_EAX) {
3334                                 non_eax_reg = ins->sreg1;
3335                         } else if (ins->sreg1 == X86_EAX) {
3336                                 non_eax_reg = ins->sreg2;
3337                         } else {
3338                                 /* no need to save since we're going to store to it anyway */
3339                                 if (ins->dreg != X86_EAX) {
3340                                         saved_eax = TRUE;
3341                                         amd64_push_reg (code, X86_EAX);
3342                                 }
3343                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3344                                 non_eax_reg = ins->sreg2;
3345                         }
3346                         if (ins->dreg == X86_EDX) {
3347                                 if (!saved_eax) {
3348                                         saved_eax = TRUE;
3349                                         amd64_push_reg (code, X86_EAX);
3350                                 }
3351                         } else {
3352                                 saved_edx = TRUE;
3353                                 amd64_push_reg (code, X86_EDX);
3354                         }
3355                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3356                         /* save before the check since pop and mov don't change the flags */
3357                         if (ins->dreg != X86_EAX)
3358                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3359                         if (saved_edx)
3360                                 amd64_pop_reg (code, X86_EDX);
3361                         if (saved_eax)
3362                                 amd64_pop_reg (code, X86_EAX);
3363                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3364                         break;
3365                 }
3366                 case OP_ICOMPARE:
3367                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3368                         break;
3369                 case OP_ICOMPARE_IMM:
3370                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3371                         break;
3372                 case OP_IBEQ:
3373                 case OP_IBLT:
3374                 case OP_IBGT:
3375                 case OP_IBGE:
3376                 case OP_IBLE:
3377                 case OP_LBEQ:
3378                 case OP_LBLT:
3379                 case OP_LBGT:
3380                 case OP_LBGE:
3381                 case OP_LBLE:
3382                 case OP_IBNE_UN:
3383                 case OP_IBLT_UN:
3384                 case OP_IBGT_UN:
3385                 case OP_IBGE_UN:
3386                 case OP_IBLE_UN:
3387                 case OP_LBNE_UN:
3388                 case OP_LBLT_UN:
3389                 case OP_LBGT_UN:
3390                 case OP_LBGE_UN:
3391                 case OP_LBLE_UN:
3392                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3393                         break;
3394
3395                 case OP_CMOV_IEQ:
3396                 case OP_CMOV_IGE:
3397                 case OP_CMOV_IGT:
3398                 case OP_CMOV_ILE:
3399                 case OP_CMOV_ILT:
3400                 case OP_CMOV_INE_UN:
3401                 case OP_CMOV_IGE_UN:
3402                 case OP_CMOV_IGT_UN:
3403                 case OP_CMOV_ILE_UN:
3404                 case OP_CMOV_ILT_UN:
3405                 case OP_CMOV_LEQ:
3406                 case OP_CMOV_LGE:
3407                 case OP_CMOV_LGT:
3408                 case OP_CMOV_LLE:
3409                 case OP_CMOV_LLT:
3410                 case OP_CMOV_LNE_UN:
3411                 case OP_CMOV_LGE_UN:
3412                 case OP_CMOV_LGT_UN:
3413                 case OP_CMOV_LLE_UN:
3414                 case OP_CMOV_LLT_UN:
3415                         g_assert (ins->dreg == ins->sreg1);
3416                         /* This needs to operate on 64 bit values */
3417                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3418                         break;
3419
3420                 case OP_LNOT:
3421                         amd64_not_reg (code, ins->sreg1);
3422                         break;
3423                 case OP_LNEG:
3424                         amd64_neg_reg (code, ins->sreg1);
3425                         break;
3426
3427                 case OP_ICONST:
3428                 case OP_I8CONST:
3429                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3430                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3431                         else
3432                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3433                         break;
3434                 case OP_AOTCONST:
3435                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3436                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3437                         break;
3438                 case OP_JUMP_TABLE:
3439                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3440                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3441                         break;
3442                 case OP_MOVE:
3443                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3444                         break;
3445                 case OP_AMD64_SET_XMMREG_R4: {
3446                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3447                         break;
3448                 }
3449                 case OP_AMD64_SET_XMMREG_R8: {
3450                         if (ins->dreg != ins->sreg1)
3451                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3452                         break;
3453                 }
3454                 case OP_JMP:
3455                 case OP_TAILCALL: {
3456                         /*
3457                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3458                          * Keep in sync with the code in emit_epilog.
3459                          */
3460                         int pos = 0, i;
3461
3462                         /* FIXME: no tracing support... */
3463                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3464                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3465
3466                         g_assert (!cfg->method->save_lmf);
3467
3468                         if (ins->opcode == OP_JMP)
3469                                 code = emit_load_volatile_arguments (cfg, code);
3470
3471                         if (cfg->arch.omit_fp) {
3472                                 guint32 save_offset = 0;
3473                                 /* Pop callee-saved registers */
3474                                 for (i = 0; i < AMD64_NREG; ++i)
3475                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3476                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3477                                                 save_offset += 8;
3478                                         }
3479                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3480                         }
3481                         else {
3482                                 for (i = 0; i < AMD64_NREG; ++i)
3483                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3484                                                 pos -= sizeof (gpointer);
3485
3486                                 if (pos)
3487                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3488
3489                                 /* Pop registers in reverse order */
3490                                 for (i = AMD64_NREG - 1; i > 0; --i)
3491                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3492                                                 amd64_pop_reg (code, i);
3493                                         }
3494
3495                                 amd64_leave (code);
3496                         }
3497
3498                         offset = code - cfg->native_code;
3499                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3500                         if (cfg->compile_aot)
3501                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3502                         else
3503                                 amd64_set_reg_template (code, AMD64_R11);
3504                         amd64_jump_reg (code, AMD64_R11);
3505                         break;
3506                 }
3507                 case OP_CHECK_THIS:
3508                         /* ensure ins->sreg1 is not NULL */
3509                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3510                         break;
3511                 case OP_ARGLIST: {
3512                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3513                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3514                         break;
3515                 }
3516                 case OP_CALL:
3517                 case OP_FCALL:
3518                 case OP_LCALL:
3519                 case OP_VCALL:
3520                 case OP_VCALL2:
3521                 case OP_VOIDCALL:
3522                         call = (MonoCallInst*)ins;
3523                         /*
3524                          * The AMD64 ABI forces callers to know about varargs.
3525                          */
3526                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3527                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3528                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3529                                 /*
3530                                  * Since the unmanaged calling convention doesn't contain a
3531                                  * 'vararg' entry, we have to treat every pinvoke call as a
3532                                  * potential vararg call.
3533                                  */
3534                                 guint32 nregs, i;
3535                                 nregs = 0;
3536                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3537                                         if (call->used_fregs & (1 << i))
3538                                                 nregs ++;
3539                                 if (!nregs)
3540                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3541                                 else
3542                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3543                         }
3544
3545                         if (ins->flags & MONO_INST_HAS_METHOD)
3546                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3547                         else
3548                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3549                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3550                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3551                         code = emit_move_return_value (cfg, ins, code);
3552                         break;
3553                 case OP_FCALL_REG:
3554                 case OP_LCALL_REG:
3555                 case OP_VCALL_REG:
3556                 case OP_VCALL2_REG:
3557                 case OP_VOIDCALL_REG:
3558                 case OP_CALL_REG:
3559                         call = (MonoCallInst*)ins;
3560
3561                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3562                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3563                                 ins->sreg1 = AMD64_R11;
3564                         }
3565
3566                         /*
3567                          * The AMD64 ABI forces callers to know about varargs.
3568                          */
3569                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3570                                 if (ins->sreg1 == AMD64_RAX) {
3571                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3572                                         ins->sreg1 = AMD64_R11;
3573                                 }
3574                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3575                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3576                                 /*
3577                                  * Since the unmanaged calling convention doesn't contain a
3578                                  * 'vararg' entry, we have to treat every pinvoke call as a
3579                                  * potential vararg call.
3580                                  */
3581                                 guint32 nregs, i;
3582                                 nregs = 0;
3583                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3584                                         if (call->used_fregs & (1 << i))
3585                                                 nregs ++;
3586                                 if (ins->sreg1 == AMD64_RAX) {
3587                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3588                                         ins->sreg1 = AMD64_R11;
3589                                 }
3590                                 if (!nregs)
3591                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3592                                 else
3593                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3594                         }
3595
3596                         amd64_call_reg (code, ins->sreg1);
3597                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3598                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3599                         code = emit_move_return_value (cfg, ins, code);
3600                         break;
3601                 case OP_FCALL_MEMBASE:
3602                 case OP_LCALL_MEMBASE:
3603                 case OP_VCALL_MEMBASE:
3604                 case OP_VCALL2_MEMBASE:
3605                 case OP_VOIDCALL_MEMBASE:
3606                 case OP_CALL_MEMBASE:
3607                         call = (MonoCallInst*)ins;
3608
3609                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3610                                 /*
3611                                  * Can't use R11 because it is clobbered by the trampoline
3612                                  * code, and the reg value is needed by get_vcall_slot_addr.
3613                                  */
3614                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3615                                 ins->sreg1 = AMD64_RAX;
3616                         }
3617
3618                         if (call->method && ins->inst_offset < 0) {
3619                                 gssize val;
3620
3621                                 /*
3622                                  * This is a possible IMT call so save the IMT method in the proper
3623                                  * register. We don't use the generic code in method-to-ir.c, because
3624                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3625                                  * maintain control over the layout of the code.
3626                                  * Also put the base reg in %rax to simplify find_imt_method ().
3627                                  */
3628                                 if (ins->sreg1 != AMD64_RAX) {
3629                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3630                                         ins->sreg1 = AMD64_RAX;
3631                                 }
3632                                 val = (gssize)(gpointer)call->method;
3633
3634                                 // FIXME: Generics sharing
3635 #if 0
3636                                 if ((((guint64)val) >> 32) == 0)
3637                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3638                                 else
3639                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3640 #endif
3641                         }
3642
3643                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3644                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3645                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3646                         code = emit_move_return_value (cfg, ins, code);
3647                         break;
3648                 case OP_AMD64_SAVE_SP_TO_LMF:
3649                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3650                         break;
3651                 case OP_OUTARG:
3652                 case OP_X86_PUSH:
3653                         amd64_push_reg (code, ins->sreg1);
3654                         break;
3655                 case OP_X86_PUSH_IMM:
3656                         g_assert (amd64_is_imm32 (ins->inst_imm));
3657                         amd64_push_imm (code, ins->inst_imm);
3658                         break;
3659                 case OP_X86_PUSH_MEMBASE:
3660                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3661                         break;
3662                 case OP_X86_PUSH_OBJ: {
3663                         int size = ALIGN_TO (ins->inst_imm, 8);
3664                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3665                         amd64_push_reg (code, AMD64_RDI);
3666                         amd64_push_reg (code, AMD64_RSI);
3667                         amd64_push_reg (code, AMD64_RCX);
3668                         if (ins->inst_offset)
3669                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3670                         else
3671                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3672                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3673                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3674                         amd64_cld (code);
3675                         amd64_prefix (code, X86_REP_PREFIX);
3676                         amd64_movsd (code);
3677                         amd64_pop_reg (code, AMD64_RCX);
3678                         amd64_pop_reg (code, AMD64_RSI);
3679                         amd64_pop_reg (code, AMD64_RDI);
3680                         break;
3681                 }
3682                 case OP_X86_LEA:
3683                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3684                         break;
3685                 case OP_X86_LEA_MEMBASE:
3686                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3687                         break;
3688                 case OP_X86_XCHG:
3689                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3690                         break;
3691                 case OP_LOCALLOC:
3692                         /* keep alignment */
3693                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3694                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3695                         code = mono_emit_stack_alloc (code, ins);
3696                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3697                         break;
3698                 case OP_LOCALLOC_IMM: {
3699                         guint32 size = ins->inst_imm;
3700                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3701
3702                         if (ins->flags & MONO_INST_INIT) {
3703                                 if (size < 64) {
3704                                         int i;
3705
3706                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3707                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3708
3709                                         for (i = 0; i < size; i += 8)
3710                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3711                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3712                                 } else {
3713                                         amd64_mov_reg_imm (code, ins->dreg, size);
3714                                         ins->sreg1 = ins->dreg;
3715
3716                                         code = mono_emit_stack_alloc (code, ins);
3717                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3718                                 }
3719                         } else {
3720                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3721                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3722                         }
3723                         break;
3724                 }
3725                 case OP_THROW: {
3726                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3727                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3728                                              (gpointer)"mono_arch_throw_exception", FALSE);
3729                         break;
3730                 }
3731                 case OP_RETHROW: {
3732                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3733                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3734                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
3735                         break;
3736                 }
3737                 case OP_CALL_HANDLER:
3738                         /* Align stack */
3739                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3740                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3741                         amd64_call_imm (code, 0);
3742                         /* Restore stack alignment */
3743                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3744                         break;
3745                 case OP_START_HANDLER: {
3746                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3747                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3748                         break;
3749                 }
3750                 case OP_ENDFINALLY: {
3751                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3752                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3753                         amd64_ret (code);
3754                         break;
3755                 }
3756                 case OP_ENDFILTER: {
3757                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3758                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3759                         /* The local allocator will put the result into RAX */
3760                         amd64_ret (code);
3761                         break;
3762                 }
3763
3764                 case OP_LABEL:
3765                         ins->inst_c0 = code - cfg->native_code;
3766                         break;
3767                 case OP_BR:
3768                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3769                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3770                         //break;
3771                         if (ins->flags & MONO_INST_BRLABEL) {
3772                                 if (ins->inst_i0->inst_c0) {
3773                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3774                                 } else {
3775                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3776                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3777                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3778                                                 x86_jump8 (code, 0);
3779                                         else
3780                                                 x86_jump32 (code, 0);
3781                                 }
3782                         } else {
3783                                 if (ins->inst_target_bb->native_offset) {
3784                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3785                                 } else {
3786                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3787                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3788                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3789                                                 x86_jump8 (code, 0);
3790                                         else
3791                                                 x86_jump32 (code, 0);
3792                                 }
3793                         }
3794                         break;
3795                 case OP_BR_REG:
3796                         amd64_jump_reg (code, ins->sreg1);
3797                         break;
3798                 case OP_CEQ:
3799                 case OP_LCEQ:
3800                 case OP_ICEQ:
3801                 case OP_CLT:
3802                 case OP_LCLT:
3803                 case OP_ICLT:
3804                 case OP_CGT:
3805                 case OP_ICGT:
3806                 case OP_LCGT:
3807                 case OP_CLT_UN:
3808                 case OP_LCLT_UN:
3809                 case OP_ICLT_UN:
3810                 case OP_CGT_UN:
3811                 case OP_LCGT_UN:
3812                 case OP_ICGT_UN:
3813                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3814                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3815                         break;
3816                 case OP_COND_EXC_EQ:
3817                 case OP_COND_EXC_NE_UN:
3818                 case OP_COND_EXC_LT:
3819                 case OP_COND_EXC_LT_UN:
3820                 case OP_COND_EXC_GT:
3821                 case OP_COND_EXC_GT_UN:
3822                 case OP_COND_EXC_GE:
3823                 case OP_COND_EXC_GE_UN:
3824                 case OP_COND_EXC_LE:
3825                 case OP_COND_EXC_LE_UN:
3826                 case OP_COND_EXC_IEQ:
3827                 case OP_COND_EXC_INE_UN:
3828                 case OP_COND_EXC_ILT:
3829                 case OP_COND_EXC_ILT_UN:
3830                 case OP_COND_EXC_IGT:
3831                 case OP_COND_EXC_IGT_UN:
3832                 case OP_COND_EXC_IGE:
3833                 case OP_COND_EXC_IGE_UN:
3834                 case OP_COND_EXC_ILE:
3835                 case OP_COND_EXC_ILE_UN:
3836                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3837                         break;
3838                 case OP_COND_EXC_OV:
3839                 case OP_COND_EXC_NO:
3840                 case OP_COND_EXC_C:
3841                 case OP_COND_EXC_NC:
3842                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3843                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3844                         break;
3845                 case OP_COND_EXC_IOV:
3846                 case OP_COND_EXC_INO:
3847                 case OP_COND_EXC_IC:
3848                 case OP_COND_EXC_INC:
3849                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3850                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3851                         break;
3852
3853                 /* floating point opcodes */
3854                 case OP_R8CONST: {
3855                         double d = *(double *)ins->inst_p0;
3856
3857                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
3858                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3859                         }
3860                         else {
3861                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3862                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3863                         }
3864                         break;
3865                 }
3866                 case OP_R4CONST: {
3867                         float f = *(float *)ins->inst_p0;
3868
3869                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
3870                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3871                         }
3872                         else {
3873                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3874                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3875                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3876                         }
3877                         break;
3878                 }
3879                 case OP_STORER8_MEMBASE_REG:
3880                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3881                         break;
3882                 case OP_LOADR8_SPILL_MEMBASE:
3883                         g_assert_not_reached ();
3884                         break;
3885                 case OP_LOADR8_MEMBASE:
3886                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3887                         break;
3888                 case OP_STORER4_MEMBASE_REG:
3889                         /* This requires a double->single conversion */
3890                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3891                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3892                         break;
3893                 case OP_LOADR4_MEMBASE:
3894                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3895                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3896                         break;
3897                 case OP_ICONV_TO_R4: /* FIXME: change precision */
3898                 case OP_ICONV_TO_R8:
3899                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3900                         break;
3901                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3902                 case OP_LCONV_TO_R8:
3903                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3904                         break;
3905                 case OP_FCONV_TO_R4:
3906                         /* FIXME: nothing to do ?? */
3907                         break;
3908                 case OP_FCONV_TO_I1:
3909                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3910                         break;
3911                 case OP_FCONV_TO_U1:
3912                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3913                         break;
3914                 case OP_FCONV_TO_I2:
3915                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3916                         break;
3917                 case OP_FCONV_TO_U2:
3918                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3919                         break;
3920                 case OP_FCONV_TO_U4:
3921                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3922                         break;
3923                 case OP_FCONV_TO_I4:
3924                 case OP_FCONV_TO_I:
3925                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3926                         break;
3927                 case OP_FCONV_TO_I8:
3928                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3929                         break;
3930                 case OP_LCONV_TO_R_UN: {
3931                         guint8 *br [2];
3932
3933                         /* Based on gcc code */
3934                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3935                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3936
3937                         /* Positive case */
3938                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3939                         br [1] = code; x86_jump8 (code, 0);
3940                         amd64_patch (br [0], code);
3941
3942                         /* Negative case */
3943                         /* Save to the red zone */
3944                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3945                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3946                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3947                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3948                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3949                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3950                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3951                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3952                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3953                         /* Restore */
3954                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3955                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3956                         amd64_patch (br [1], code);
3957                         break;
3958                 }
3959                 case OP_LCONV_TO_OVF_U4:
3960                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3961                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3962                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3963                         break;
3964                 case OP_LCONV_TO_OVF_I4_UN:
3965                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3966                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3967                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3968                         break;
3969                 case OP_FMOVE:
3970                         if (ins->dreg != ins->sreg1)
3971                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3972                         break;
3973                 case OP_FADD:
3974                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3975                         break;
3976                 case OP_FSUB:
3977                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3978                         break;
3979                 case OP_FMUL:
3980                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3981                         break;
3982                 case OP_FDIV:
3983                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3984                         break;
3985                 case OP_FNEG: {
3986                         static double r8_0 = -0.0;
3987
3988                         g_assert (ins->sreg1 == ins->dreg);
3989
3990                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3991                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3992                         break;
3993                 }
3994                 case OP_SIN:
3995                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3996                         break;
3997                 case OP_COS:
3998                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3999                         break;
4000                 case OP_ABS: {
4001                         static guint64 d = 0x7fffffffffffffffUL;
4002
4003                         g_assert (ins->sreg1 == ins->dreg);
4004
4005                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4006                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4007                         break;
4008                 }
4009                 case OP_SQRT:
4010                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4011                         break;
4012                 case OP_IMIN:
4013                         g_assert (cfg->opt & MONO_OPT_CMOV);
4014                         g_assert (ins->dreg == ins->sreg1);
4015                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4016                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4017                         break;
4018                 case OP_IMIN_UN:
4019                         g_assert (cfg->opt & MONO_OPT_CMOV);
4020                         g_assert (ins->dreg == ins->sreg1);
4021                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4022                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4023                         break;
4024                 case OP_IMAX:
4025                         g_assert (cfg->opt & MONO_OPT_CMOV);
4026                         g_assert (ins->dreg == ins->sreg1);
4027                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4028                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4029                         break;
4030                 case OP_IMAX_UN:
4031                         g_assert (cfg->opt & MONO_OPT_CMOV);
4032                         g_assert (ins->dreg == ins->sreg1);
4033                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4034                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4035                         break;
4036                 case OP_LMIN:
4037                         g_assert (cfg->opt & MONO_OPT_CMOV);
4038                         g_assert (ins->dreg == ins->sreg1);
4039                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4040                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4041                         break;
4042                 case OP_LMIN_UN:
4043                         g_assert (cfg->opt & MONO_OPT_CMOV);
4044                         g_assert (ins->dreg == ins->sreg1);
4045                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4046                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4047                         break;
4048                 case OP_LMAX:
4049                         g_assert (cfg->opt & MONO_OPT_CMOV);
4050                         g_assert (ins->dreg == ins->sreg1);
4051                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4052                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4053                         break;
4054                 case OP_LMAX_UN:
4055                         g_assert (cfg->opt & MONO_OPT_CMOV);
4056                         g_assert (ins->dreg == ins->sreg1);
4057                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4058                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4059                         break;
4060                 case OP_X86_FPOP:
4061                         break;
4062                 case OP_FCOMPARE:
4063                         /*
4064                          * The two arguments are swapped because the fbranch instructions
4065                          * depend on this for the non-sse case to work.
4066                          */
4067                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4068                         break;
4069                 case OP_FCEQ: {
4070                         /* zeroing the register at the start results in
4071                          * shorter and faster code (we can also remove the widening op)
4072                          */
4073                         guchar *unordered_check;
4074                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4075                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4076                         unordered_check = code;
4077                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4078                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4079                         amd64_patch (unordered_check, code);
4080                         break;
4081                 }
4082                 case OP_FCLT:
4083                 case OP_FCLT_UN:
4084                         /* zeroing the register at the start results in
4085                          * shorter and faster code (we can also remove the widening op)
4086                          */
4087                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4088                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4089                         if (ins->opcode == OP_FCLT_UN) {
4090                                 guchar *unordered_check = code;
4091                                 guchar *jump_to_end;
4092                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4093                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4094                                 jump_to_end = code;
4095                                 x86_jump8 (code, 0);
4096                                 amd64_patch (unordered_check, code);
4097                                 amd64_inc_reg (code, ins->dreg);
4098                                 amd64_patch (jump_to_end, code);
4099                         } else {
4100                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4101                         }
4102                         break;
4103                 case OP_FCGT:
4104                 case OP_FCGT_UN: {
4105                         /* zeroing the register at the start results in
4106                          * shorter and faster code (we can also remove the widening op)
4107                          */
4108                         guchar *unordered_check;
4109                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4110                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4111                         if (ins->opcode == OP_FCGT) {
4112                                 unordered_check = code;
4113                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4114                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4115                                 amd64_patch (unordered_check, code);
4116                         } else {
4117                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4118                         }
4119                         break;
4120                 }
4121                 case OP_FCLT_MEMBASE:
4122                 case OP_FCGT_MEMBASE:
4123                 case OP_FCLT_UN_MEMBASE:
4124                 case OP_FCGT_UN_MEMBASE:
4125                 case OP_FCEQ_MEMBASE: {
4126                         guchar *unordered_check, *jump_to_end;
4127                         int x86_cond;
4128
4129                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4130                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4131
4132                         switch (ins->opcode) {
4133                         case OP_FCEQ_MEMBASE:
4134                                 x86_cond = X86_CC_EQ;
4135                                 break;
4136                         case OP_FCLT_MEMBASE:
4137                         case OP_FCLT_UN_MEMBASE:
4138                                 x86_cond = X86_CC_LT;
4139                                 break;
4140                         case OP_FCGT_MEMBASE:
4141                         case OP_FCGT_UN_MEMBASE:
4142                                 x86_cond = X86_CC_GT;
4143                                 break;
4144                         default:
4145                                 g_assert_not_reached ();
4146                         }
4147
4148                         unordered_check = code;
4149                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4150                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4151
4152                         switch (ins->opcode) {
4153                         case OP_FCEQ_MEMBASE:
4154                         case OP_FCLT_MEMBASE:
4155                         case OP_FCGT_MEMBASE:
4156                                 amd64_patch (unordered_check, code);
4157                                 break;
4158                         case OP_FCLT_UN_MEMBASE:
4159                         case OP_FCGT_UN_MEMBASE:
4160                                 jump_to_end = code;
4161                                 x86_jump8 (code, 0);
4162                                 amd64_patch (unordered_check, code);
4163                                 amd64_inc_reg (code, ins->dreg);
4164                                 amd64_patch (jump_to_end, code);
4165                                 break;
4166                         default:
4167                                 break;
4168                         }
4169                         break;
4170                 }
4171                 case OP_FBEQ: {
4172                         guchar *jump = code;
4173                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4174                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4175                         amd64_patch (jump, code);
4176                         break;
4177                 }
4178                 case OP_FBNE_UN:
4179                         /* Branch if C013 != 100 */
4180                         /* branch if !ZF or (PF|CF) */
4181                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4182                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4183                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4184                         break;
4185                 case OP_FBLT:
4186                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4187                         break;
4188                 case OP_FBLT_UN:
4189                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4190                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4191                         break;
4192                 case OP_FBGT:
4193                 case OP_FBGT_UN:
4194                         if (ins->opcode == OP_FBGT) {
4195                                 guchar *br1;
4196
4197                                 /* skip branch if C1=1 */
4198                                 br1 = code;
4199                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4200                                 /* branch if (C0 | C3) = 1 */
4201                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4202                                 amd64_patch (br1, code);
4203                                 break;
4204                         } else {
4205                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4206                         }
4207                         break;
4208                 case OP_FBGE: {
4209                         /* Branch if C013 == 100 or 001 */
4210                         guchar *br1;
4211
4212                         /* skip branch if C1=1 */
4213                         br1 = code;
4214                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4215                         /* branch if (C0 | C3) = 1 */
4216                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4217                         amd64_patch (br1, code);
4218                         break;
4219                 }
4220                 case OP_FBGE_UN:
4221                         /* Branch if C013 == 000 */
4222                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4223                         break;
4224                 case OP_FBLE: {
4225                         /* Branch if C013=000 or 100 */
4226                         guchar *br1;
4227
4228                         /* skip branch if C1=1 */
4229                         br1 = code;
4230                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4231                         /* branch if C0=0 */
4232                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4233                         amd64_patch (br1, code);
4234                         break;
4235                 }
4236                 case OP_FBLE_UN:
4237                         /* Branch if C013 != 001 */
4238                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4239                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4240                         break;
4241                 case OP_CKFINITE:
4242                         /* Transfer value to the fp stack */
4243                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4244                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4245                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4246
4247                         amd64_push_reg (code, AMD64_RAX);
4248                         amd64_fxam (code);
4249                         amd64_fnstsw (code);
4250                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4251                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4252                         amd64_pop_reg (code, AMD64_RAX);
4253                         amd64_fstp (code, 0);
4254                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4255                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4256                         break;
4257                 case OP_TLS_GET: {
4258                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4259                         break;
4260                 }
4261                 case OP_MEMORY_BARRIER: {
4262                         /* Not needed on amd64 */
4263                         break;
4264                 }
4265                 case OP_ATOMIC_ADD_I4:
4266                 case OP_ATOMIC_ADD_I8: {
4267                         int dreg = ins->dreg;
4268                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4269
4270                         if (dreg == ins->inst_basereg)
4271                                 dreg = AMD64_R11;
4272
4273                         if (dreg != ins->sreg2)
4274                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4275
4276                         x86_prefix (code, X86_LOCK_PREFIX);
4277                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4278
4279                         if (dreg != ins->dreg)
4280                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4281
4282                         break;
4283                 }
4284                 case OP_ATOMIC_ADD_NEW_I4:
4285                 case OP_ATOMIC_ADD_NEW_I8: {
4286                         int dreg = ins->dreg;
4287                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4288
4289                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4290                                 dreg = AMD64_R11;
4291
4292                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4293                         amd64_prefix (code, X86_LOCK_PREFIX);
4294                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4295                         /* dreg contains the old value, add with sreg2 value */
4296                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4297
4298                         if (ins->dreg != dreg)
4299                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4300
4301                         break;
4302                 }
4303                 case OP_ATOMIC_EXCHANGE_I4:
4304                 case OP_ATOMIC_EXCHANGE_I8:
4305                 case OP_ATOMIC_CAS_IMM_I4: {
4306                         guchar *br[2];
4307                         int sreg2 = ins->sreg2;
4308                         int breg = ins->inst_basereg;
4309                         guint32 size;
4310                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4311
4312                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4313                                 size = 8;
4314                         else
4315                                 size = 4;
4316
4317                         /*
4318                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4319                          * an explanation of how this works.
4320                          */
4321
4322                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4323                          * hack to overcome limits in x86 reg allocator
4324                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4325                          */
4326                         g_assert (ins->dreg == AMD64_RAX);
4327
4328                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4329                                 /* Highly unlikely, but possible */
4330                                 need_push = TRUE;
4331
4332                         /* The pushes invalidate rsp */
4333                         if ((breg == AMD64_RAX) || need_push) {
4334                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4335                                 breg = AMD64_R11;
4336                         }
4337
4338                         /* We need the EAX reg for the comparand */
4339                         if (ins->sreg2 == AMD64_RAX) {
4340                                 if (breg != AMD64_R11) {
4341                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4342                                         sreg2 = AMD64_R11;
4343                                 } else {
4344                                         g_assert (need_push);
4345                                         amd64_push_reg (code, AMD64_RDX);
4346                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4347                                         sreg2 = AMD64_RDX;
4348                                         rdx_pushed = TRUE;
4349                                 }
4350                         }
4351
4352                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4353                                 if (ins->backend.data == NULL)
4354                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4355                                 else
4356                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4357
4358                                 amd64_prefix (code, X86_LOCK_PREFIX);
4359                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4360                         } else {
4361                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4362
4363                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4364                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4365                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4366                                 amd64_patch (br [1], br [0]);
4367                         }
4368
4369                         if (rdx_pushed)
4370                                 amd64_pop_reg (code, AMD64_RDX);
4371
4372                         break;
4373                 }
4374                 default:
4375                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4376                         g_assert_not_reached ();
4377                 }
4378
4379                 if ((code - cfg->native_code - offset) > max_len) {
4380                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4381                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4382                         g_assert_not_reached ();
4383                 }
4384
4385                 cpos += max_len;
4386
4387                 last_ins = ins;
4388                 last_offset = offset;
4389         }
4390
4391         cfg->code_len = code - cfg->native_code;
4392 }
4393
4394 #endif /* DISABLE_JIT */
4395
4396 void
4397 mono_arch_register_lowlevel_calls (void)
4398 {
4399         /* The signature doesn't matter */
4400         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4401 }
4402
4403 void
4404 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4405 {
4406         MonoJumpInfo *patch_info;
4407         gboolean compile_aot = !run_cctors;
4408
4409         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4410                 unsigned char *ip = patch_info->ip.i + code;
4411                 unsigned char *target;
4412
4413                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4414
4415                 if (compile_aot) {
4416                         switch (patch_info->type) {
4417                         case MONO_PATCH_INFO_BB:
4418                         case MONO_PATCH_INFO_LABEL:
4419                                 break;
4420                         default:
4421                                 /* No need to patch these */
4422                                 continue;
4423                         }
4424                 }
4425
4426                 switch (patch_info->type) {
4427                 case MONO_PATCH_INFO_NONE:
4428                         continue;
4429                 case MONO_PATCH_INFO_METHOD_REL:
4430                 case MONO_PATCH_INFO_R8:
4431                 case MONO_PATCH_INFO_R4:
4432                         g_assert_not_reached ();
4433                         continue;
4434                 case MONO_PATCH_INFO_BB:
4435                         break;
4436                 default:
4437                         break;
4438                 }
4439
4440                 /*
4441                  * Debug code to help track down problems where the target of a near call is
4442                  * is not valid.
4443                  */
4444                 if (amd64_is_near_call (ip)) {
4445                         gint64 disp = (guint8*)target - (guint8*)ip;
4446
4447                         if (!amd64_is_imm32 (disp)) {
4448                                 printf ("TYPE: %d\n", patch_info->type);
4449                                 switch (patch_info->type) {
4450                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4451                                         printf ("V: %s\n", patch_info->data.name);
4452                                         break;
4453                                 case MONO_PATCH_INFO_METHOD_JUMP:
4454                                 case MONO_PATCH_INFO_METHOD:
4455                                         printf ("V: %s\n", patch_info->data.method->name);
4456                                         break;
4457                                 default:
4458                                         break;
4459                                 }
4460                         }
4461                 }
4462
4463                 amd64_patch (ip, (gpointer)target);
4464         }
4465 }
4466
4467 static int
4468 get_max_epilog_size (MonoCompile *cfg)
4469 {
4470         int max_epilog_size = 16;
4471
4472         if (cfg->method->save_lmf)
4473                 max_epilog_size += 256;
4474
4475         if (mono_jit_trace_calls != NULL)
4476                 max_epilog_size += 50;
4477
4478         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4479                 max_epilog_size += 50;
4480
4481         max_epilog_size += (AMD64_NREG * 2);
4482
4483         return max_epilog_size;
4484 }
4485
4486 /*
4487  * This macro is used for testing whenever the unwinder works correctly at every point
4488  * where an async exception can happen.
4489  */
4490 /* This will generate a SIGSEGV at the given point in the code */
4491 #define async_exc_point(code) do { \
4492     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4493          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4494              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4495          cfg->arch.async_point_count ++; \
4496     } \
4497 } while (0)
4498
4499 guint8 *
4500 mono_arch_emit_prolog (MonoCompile *cfg)
4501 {
4502         MonoMethod *method = cfg->method;
4503         MonoBasicBlock *bb;
4504         MonoMethodSignature *sig;
4505         MonoInst *ins;
4506         int alloc_size, pos, max_offset, i, cfa_offset, quad, max_epilog_size;
4507         guint8 *code;
4508         CallInfo *cinfo;
4509         gint32 lmf_offset = cfg->arch.lmf_offset;
4510         gboolean args_clobbered = FALSE;
4511         gboolean trace = FALSE;
4512
4513         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4514
4515         code = cfg->native_code = g_malloc (cfg->code_size);
4516
4517         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4518                 trace = TRUE;
4519
4520         /* Amount of stack space allocated by register saving code */
4521         pos = 0;
4522
4523         /* Offset between RSP and the CFA */
4524         cfa_offset = 0;
4525
4526         /*
4527          * The prolog consists of the following parts:
4528          * FP present:
4529          * - push rbp, mov rbp, rsp
4530          * - save callee saved regs using pushes
4531          * - allocate frame
4532          * - save rgctx if needed
4533          * - save lmf if needed
4534          * FP not present:
4535          * - allocate frame
4536          * - save rgctx if needed
4537          * - save lmf if needed
4538          * - save callee saved regs using moves
4539          */
4540
4541         // CFA = sp + 8
4542         cfa_offset = 8;
4543         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4544         // IP saved at CFA - 8
4545         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4546         async_exc_point (code);
4547
4548         if (!cfg->arch.omit_fp) {
4549                 amd64_push_reg (code, AMD64_RBP);
4550                 cfa_offset += 8;
4551                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4552                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4553                 async_exc_point (code);
4554 #ifdef PLATFORM_WIN32
4555                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4556 #endif
4557
4558                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4559                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4560                 async_exc_point (code);
4561 #ifdef PLATFORM_WIN32
4562                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4563 #endif
4564         }
4565
4566         /* Save callee saved registers */
4567         if (!cfg->arch.omit_fp && !method->save_lmf) {
4568                 int offset = cfa_offset;
4569
4570                 for (i = 0; i < AMD64_NREG; ++i)
4571                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4572                                 amd64_push_reg (code, i);
4573                                 pos += sizeof (gpointer);
4574                                 offset += 8;
4575                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4576                                 async_exc_point (code);
4577                         }
4578         }
4579
4580         if (cfg->arch.omit_fp) {
4581                 /*
4582                  * On enter, the stack is misaligned by the the pushing of the return
4583                  * address. It is either made aligned by the pushing of %rbp, or by
4584                  * this.
4585                  */
4586                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4587                 if ((alloc_size % 16) == 0)
4588                         alloc_size += 8;
4589         } else {
4590                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4591
4592                 alloc_size -= pos;
4593         }
4594
4595         cfg->arch.stack_alloc_size = alloc_size;
4596
4597         /* Allocate stack frame */
4598         if (alloc_size) {
4599                 /* See mono_emit_stack_alloc */
4600 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4601                 guint32 remaining_size = alloc_size;
4602                 while (remaining_size >= 0x1000) {
4603                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4604                         if (cfg->arch.omit_fp) {
4605                                 cfa_offset += 0x1000;
4606                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4607                         }
4608                         async_exc_point (code);
4609 #ifdef PLATFORM_WIN32
4610                         if (cfg->arch.omit_fp)
4611                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4612 #endif
4613
4614                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4615                         remaining_size -= 0x1000;
4616                 }
4617                 if (remaining_size) {
4618                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4619                         if (cfg->arch.omit_fp) {
4620                                 cfa_offset += remaining_size;
4621                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4622                                 async_exc_point (code);
4623                         }
4624 #ifdef PLATFORM_WIN32
4625                         if (cfg->arch.omit_fp)
4626                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4627 #endif
4628                 }
4629 #else
4630                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4631                 if (cfg->arch.omit_fp) {
4632                         cfa_offset += alloc_size;
4633                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4634                         async_exc_point (code);
4635                 }
4636 #endif
4637         }
4638
4639         /* Stack alignment check */
4640 #if 0
4641         {
4642                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4643                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4644                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4645                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4646                 amd64_breakpoint (code);
4647         }
4648 #endif
4649
4650         /* Save LMF */
4651         if (method->save_lmf) {
4652                 /*
4653                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4654                  */
4655                 /* sp is saved right before calls */
4656                 /* Skip method (only needed for trampoline LMF frames) */
4657                 /* Save callee saved regs */
4658                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4659                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4660                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4661                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4662                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4663                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4664         }
4665
4666         /* Save callee saved registers */
4667         if (cfg->arch.omit_fp && !method->save_lmf) {
4668                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4669
4670                 /* Save caller saved registers after sp is adjusted */
4671                 /* The registers are saved at the bottom of the frame */
4672                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4673                 for (i = 0; i < AMD64_NREG; ++i)
4674                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4675                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4676                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
4677                                 save_area_offset += 8;
4678                                 async_exc_point (code);
4679                         }
4680         }
4681
4682         /* store runtime generic context */
4683         if (cfg->rgctx_var) {
4684                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4685                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4686
4687                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4688         }
4689
4690         /* compute max_offset in order to use short forward jumps */
4691         max_offset = 0;
4692         max_epilog_size = get_max_epilog_size (cfg);
4693         if (cfg->opt & MONO_OPT_BRANCH) {
4694                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4695                         MonoInst *ins;
4696                         bb->max_offset = max_offset;
4697
4698                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4699                                 max_offset += 6;
4700                         /* max alignment for loops */
4701                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4702                                 max_offset += LOOP_ALIGNMENT;
4703
4704                         MONO_BB_FOR_EACH_INS (bb, ins) {
4705                                 if (ins->opcode == OP_LABEL)
4706                                         ins->inst_c1 = max_offset;
4707
4708                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4709                         }
4710
4711                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4712                                 /* The tracing code can be quite large */
4713                                 max_offset += max_epilog_size;
4714                 }
4715         }
4716
4717         sig = mono_method_signature (method);
4718         pos = 0;
4719
4720         cinfo = cfg->arch.cinfo;
4721
4722         if (sig->ret->type != MONO_TYPE_VOID) {
4723                 /* Save volatile arguments to the stack */
4724                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4725                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4726         }
4727
4728         /* Keep this in sync with emit_load_volatile_arguments */
4729         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4730                 ArgInfo *ainfo = cinfo->args + i;
4731                 gint32 stack_offset;
4732                 MonoType *arg_type;
4733
4734                 ins = cfg->args [i];
4735
4736                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4737                         /* Unused arguments */
4738                         continue;
4739
4740                 if (sig->hasthis && (i == 0))
4741                         arg_type = &mono_defaults.object_class->byval_arg;
4742                 else
4743                         arg_type = sig->params [i - sig->hasthis];
4744
4745                 stack_offset = ainfo->offset + ARGS_OFFSET;
4746
4747                 if (cfg->globalra) {
4748                         /* All the other moves are done by the register allocator */
4749                         switch (ainfo->storage) {
4750                         case ArgInFloatSSEReg:
4751                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
4752                                 break;
4753                         case ArgValuetypeInReg:
4754                                 for (quad = 0; quad < 2; quad ++) {
4755                                         switch (ainfo->pair_storage [quad]) {
4756                                         case ArgInIReg:
4757                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4758                                                 break;
4759                                         case ArgInFloatSSEReg:
4760                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4761                                                 break;
4762                                         case ArgInDoubleSSEReg:
4763                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4764                                                 break;
4765                                         case ArgNone:
4766                                                 break;
4767                                         default:
4768                                                 g_assert_not_reached ();
4769                                         }
4770                                 }
4771                                 break;
4772                         default:
4773                                 break;
4774                         }
4775
4776                         continue;
4777                 }
4778
4779                 /* Save volatile arguments to the stack */
4780                 if (ins->opcode != OP_REGVAR) {
4781                         switch (ainfo->storage) {
4782                         case ArgInIReg: {
4783                                 guint32 size = 8;
4784
4785                                 /* FIXME: I1 etc */
4786                                 /*
4787                                 if (stack_offset & 0x1)
4788                                         size = 1;
4789                                 else if (stack_offset & 0x2)
4790                                         size = 2;
4791                                 else if (stack_offset & 0x4)
4792                                         size = 4;
4793                                 else
4794                                         size = 8;
4795                                 */
4796                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4797                                 break;
4798                         }
4799                         case ArgInFloatSSEReg:
4800                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4801                                 break;
4802                         case ArgInDoubleSSEReg:
4803                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4804                                 break;
4805                         case ArgValuetypeInReg:
4806                                 for (quad = 0; quad < 2; quad ++) {
4807                                         switch (ainfo->pair_storage [quad]) {
4808                                         case ArgInIReg:
4809                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4810                                                 break;
4811                                         case ArgInFloatSSEReg:
4812                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4813                                                 break;
4814                                         case ArgInDoubleSSEReg:
4815                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4816                                                 break;
4817                                         case ArgNone:
4818                                                 break;
4819                                         default:
4820                                                 g_assert_not_reached ();
4821                                         }
4822                                 }
4823                                 break;
4824                         case ArgValuetypeAddrInIReg:
4825                                 if (ainfo->pair_storage [0] == ArgInIReg)
4826                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
4827                                 break;
4828                         default:
4829                                 break;
4830                         }
4831                 } else {
4832                         /* Argument allocated to (non-volatile) register */
4833                         switch (ainfo->storage) {
4834                         case ArgInIReg:
4835                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4836                                 break;
4837                         case ArgOnStack:
4838                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4839                                 break;
4840                         default:
4841                                 g_assert_not_reached ();
4842                         }
4843                 }
4844         }
4845
4846         /* Might need to attach the thread to the JIT  or change the domain for the callback */
4847         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4848                 guint64 domain = (guint64)cfg->domain;
4849
4850                 args_clobbered = TRUE;
4851
4852                 /*
4853                  * The call might clobber argument registers, but they are already
4854                  * saved to the stack/global regs.
4855                  */
4856                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4857                         guint8 *buf, *no_domain_branch;
4858
4859                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4860                         if ((domain >> 32) == 0)
4861                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4862                         else
4863                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4864                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4865                         no_domain_branch = code;
4866                         x86_branch8 (code, X86_CC_NE, 0, 0);
4867                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4868                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4869                         buf = code;
4870                         x86_branch8 (code, X86_CC_NE, 0, 0);
4871                         amd64_patch (no_domain_branch, code);
4872                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4873                                           (gpointer)"mono_jit_thread_attach", TRUE);
4874                         amd64_patch (buf, code);
4875 #ifdef PLATFORM_WIN32
4876                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4877                         /* FIXME: Add a separate key for LMF to avoid this */
4878                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4879 #endif
4880                 } else {
4881                         g_assert (!cfg->compile_aot);
4882                         if ((domain >> 32) == 0)
4883                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4884                         else
4885                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4886                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4887                                           (gpointer)"mono_jit_thread_attach", TRUE);
4888                 }
4889         }
4890
4891         if (method->save_lmf) {
4892                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4893                         /*
4894                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4895                          * through the mono_lmf_addr TLS variable.
4896                          */
4897                         /* %rax = previous_lmf */
4898                         x86_prefix (code, X86_FS_PREFIX);
4899                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4900
4901                         /* Save previous_lmf */
4902                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4903                         /* Set new lmf */
4904                         if (lmf_offset == 0) {
4905                                 x86_prefix (code, X86_FS_PREFIX);
4906                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4907                         } else {
4908                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4909                                 x86_prefix (code, X86_FS_PREFIX);
4910                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4911                         }
4912                 } else {
4913                         if (lmf_addr_tls_offset != -1) {
4914                                 /* Load lmf quicky using the FS register */
4915                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4916 #ifdef PLATFORM_WIN32
4917                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4918                                 /* FIXME: Add a separate key for LMF to avoid this */
4919                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4920 #endif
4921                         }
4922                         else {
4923                                 /*
4924                                  * The call might clobber argument registers, but they are already
4925                                  * saved to the stack/global regs.
4926                                  */
4927                                 args_clobbered = TRUE;
4928                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4929                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
4930                         }
4931
4932                         /* Save lmf_addr */
4933                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4934                         /* Save previous_lmf */
4935                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4936                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4937                         /* Set new lmf */
4938                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4939                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4940                 }
4941         }
4942
4943         if (trace) {
4944                 args_clobbered = TRUE;
4945                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4946         }
4947
4948         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4949                 args_clobbered = TRUE;
4950
4951         /*
4952          * Optimize the common case of the first bblock making a call with the same
4953          * arguments as the method. This works because the arguments are still in their
4954          * original argument registers.
4955          * FIXME: Generalize this
4956          */
4957         if (!args_clobbered) {
4958                 MonoBasicBlock *first_bb = cfg->bb_entry;
4959                 MonoInst *next;
4960
4961                 next = mono_bb_first_ins (first_bb);
4962                 if (!next && first_bb->next_bb) {
4963                         first_bb = first_bb->next_bb;
4964                         next = mono_bb_first_ins (first_bb);
4965                 }
4966
4967                 if (first_bb->in_count > 1)
4968                         next = NULL;
4969
4970                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4971                         ArgInfo *ainfo = cinfo->args + i;
4972                         gboolean match = FALSE;
4973
4974                         ins = cfg->args [i];
4975                         if (ins->opcode != OP_REGVAR) {
4976                                 switch (ainfo->storage) {
4977                                 case ArgInIReg: {
4978                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4979                                                 if (next->dreg == ainfo->reg) {
4980                                                         NULLIFY_INS (next);
4981                                                         match = TRUE;
4982                                                 } else {
4983                                                         next->opcode = OP_MOVE;
4984                                                         next->sreg1 = ainfo->reg;
4985                                                         /* Only continue if the instruction doesn't change argument regs */
4986                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4987                                                                 match = TRUE;
4988                                                 }
4989                                         }
4990                                         break;
4991                                 }
4992                                 default:
4993                                         break;
4994                                 }
4995                         } else {
4996                                 /* Argument allocated to (non-volatile) register */
4997                                 switch (ainfo->storage) {
4998                                 case ArgInIReg:
4999                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
5000                                                 NULLIFY_INS (next);
5001                                                 match = TRUE;
5002                                         }
5003                                         break;
5004                                 default:
5005                                         break;
5006                                 }
5007                         }
5008
5009                         if (match) {
5010                                 next = next->next;
5011                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
5012                                 if (!next)
5013                                         break;
5014                         }
5015                 }
5016         }
5017
5018         cfg->code_len = code - cfg->native_code;
5019
5020         g_assert (cfg->code_len < cfg->code_size);
5021
5022         return code;
5023 }
5024
5025 void
5026 mono_arch_emit_epilog (MonoCompile *cfg)
5027 {
5028         MonoMethod *method = cfg->method;
5029         int quad, pos, i;
5030         guint8 *code;
5031         int max_epilog_size;
5032         CallInfo *cinfo;
5033         gint32 lmf_offset = cfg->arch.lmf_offset;
5034
5035         max_epilog_size = get_max_epilog_size (cfg);
5036
5037         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5038                 cfg->code_size *= 2;
5039                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5040                 mono_jit_stats.code_reallocs++;
5041         }
5042
5043         code = cfg->native_code + cfg->code_len;
5044
5045         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5046                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5047
5048         /* the code restoring the registers must be kept in sync with OP_JMP */
5049         pos = 0;
5050
5051         if (method->save_lmf) {
5052                 /* check if we need to restore protection of the stack after a stack overflow */
5053                 if (mono_get_jit_tls_offset () != -1) {
5054                         guint8 *patch;
5055                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5056                         /* we load the value in a separate instruction: this mechanism may be
5057                          * used later as a safer way to do thread interruption
5058                          */
5059                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
5060                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5061                         patch = code;
5062                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
5063                         /* note that the call trampoline will preserve eax/edx */
5064                         x86_call_reg (code, X86_ECX);
5065                         x86_patch (patch, code);
5066                 } else {
5067                         /* FIXME: maybe save the jit tls in the prolog */
5068                 }
5069                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5070                         /*
5071                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5072                          * through the mono_lmf_addr TLS variable.
5073                          */
5074                         /* reg = previous_lmf */
5075                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5076                         x86_prefix (code, X86_FS_PREFIX);
5077                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5078                 } else {
5079                         /* Restore previous lmf */
5080                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5081                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5082                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5083                 }
5084
5085                 /* Restore caller saved regs */
5086                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5087                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5088                 }
5089                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5090                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5091                 }
5092                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5093                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5094                 }
5095                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5096                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5097                 }
5098                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5099                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5100                 }
5101                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5102                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5103                 }
5104         } else {
5105
5106                 if (cfg->arch.omit_fp) {
5107                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5108
5109                         for (i = 0; i < AMD64_NREG; ++i)
5110                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5111                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5112                                         save_area_offset += 8;
5113                                 }
5114                 }
5115                 else {
5116                         for (i = 0; i < AMD64_NREG; ++i)
5117                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5118                                         pos -= sizeof (gpointer);
5119
5120                         if (pos) {
5121                                 if (pos == - sizeof (gpointer)) {
5122                                         /* Only one register, so avoid lea */
5123                                         for (i = AMD64_NREG - 1; i > 0; --i)
5124                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5125                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5126                                                 }
5127                                 }
5128                                 else {
5129                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5130
5131                                         /* Pop registers in reverse order */
5132                                         for (i = AMD64_NREG - 1; i > 0; --i)
5133                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5134                                                         amd64_pop_reg (code, i);
5135                                                 }
5136                                 }
5137                         }
5138                 }
5139         }
5140
5141         /* Load returned vtypes into registers if needed */
5142         cinfo = cfg->arch.cinfo;
5143         if (cinfo->ret.storage == ArgValuetypeInReg) {
5144                 ArgInfo *ainfo = &cinfo->ret;
5145                 MonoInst *inst = cfg->ret;
5146
5147                 for (quad = 0; quad < 2; quad ++) {
5148                         switch (ainfo->pair_storage [quad]) {
5149                         case ArgInIReg:
5150                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5151                                 break;
5152                         case ArgInFloatSSEReg:
5153                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5154                                 break;
5155                         case ArgInDoubleSSEReg:
5156                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5157                                 break;
5158                         case ArgNone:
5159                                 break;
5160                         default:
5161                                 g_assert_not_reached ();
5162                         }
5163                 }
5164         }
5165
5166         if (cfg->arch.omit_fp) {
5167                 if (cfg->arch.stack_alloc_size)
5168                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5169         } else {
5170                 amd64_leave (code);
5171         }
5172         async_exc_point (code);
5173         amd64_ret (code);
5174
5175         cfg->code_len = code - cfg->native_code;
5176
5177         g_assert (cfg->code_len < cfg->code_size);
5178
5179         if (cfg->arch.omit_fp) {
5180                 /*
5181                  * Encode the stack size into used_int_regs so the exception handler
5182                  * can access it.
5183                  */
5184                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5185                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5186         }
5187 }
5188
5189 void
5190 mono_arch_emit_exceptions (MonoCompile *cfg)
5191 {
5192         MonoJumpInfo *patch_info;
5193         int nthrows, i;
5194         guint8 *code;
5195         MonoClass *exc_classes [16];
5196         guint8 *exc_throw_start [16], *exc_throw_end [16];
5197         guint32 code_size = 0;
5198
5199         /* Compute needed space */
5200         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5201                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5202                         code_size += 40;
5203                 if (patch_info->type == MONO_PATCH_INFO_R8)
5204                         code_size += 8 + 15; /* sizeof (double) + alignment */
5205                 if (patch_info->type == MONO_PATCH_INFO_R4)
5206                         code_size += 4 + 15; /* sizeof (float) + alignment */
5207         }
5208
5209         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5210                 cfg->code_size *= 2;
5211                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5212                 mono_jit_stats.code_reallocs++;
5213         }
5214
5215         code = cfg->native_code + cfg->code_len;
5216
5217         /* add code to raise exceptions */
5218         nthrows = 0;
5219         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5220                 switch (patch_info->type) {
5221                 case MONO_PATCH_INFO_EXC: {
5222                         MonoClass *exc_class;
5223                         guint8 *buf, *buf2;
5224                         guint32 throw_ip;
5225
5226                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5227
5228                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5229                         g_assert (exc_class);
5230                         throw_ip = patch_info->ip.i;
5231
5232                         //x86_breakpoint (code);
5233                         /* Find a throw sequence for the same exception class */
5234                         for (i = 0; i < nthrows; ++i)
5235                                 if (exc_classes [i] == exc_class)
5236                                         break;
5237                         if (i < nthrows) {
5238                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5239                                 x86_jump_code (code, exc_throw_start [i]);
5240                                 patch_info->type = MONO_PATCH_INFO_NONE;
5241                         }
5242                         else {
5243                                 buf = code;
5244                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5245                                 buf2 = code;
5246
5247                                 if (nthrows < 16) {
5248                                         exc_classes [nthrows] = exc_class;
5249                                         exc_throw_start [nthrows] = code;
5250                                 }
5251                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5252
5253                                 patch_info->type = MONO_PATCH_INFO_NONE;
5254
5255                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5256
5257                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5258                                 while (buf < buf2)
5259                                         x86_nop (buf);
5260
5261                                 if (nthrows < 16) {
5262                                         exc_throw_end [nthrows] = code;
5263                                         nthrows ++;
5264                                 }
5265                         }
5266                         break;
5267                 }
5268                 default:
5269                         /* do nothing */
5270                         break;
5271                 }
5272         }
5273
5274         /* Handle relocations with RIP relative addressing */
5275         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5276                 gboolean remove = FALSE;
5277
5278                 switch (patch_info->type) {
5279                 case MONO_PATCH_INFO_R8:
5280                 case MONO_PATCH_INFO_R4: {
5281                         guint8 *pos;
5282
5283                         /* The SSE opcodes require a 16 byte alignment */
5284                         code = (guint8*)ALIGN_TO (code, 16);
5285
5286                         pos = cfg->native_code + patch_info->ip.i;
5287
5288                         if (IS_REX (pos [1]))
5289                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5290                         else
5291                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5292
5293                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5294                                 *(double*)code = *(double*)patch_info->data.target;
5295                                 code += sizeof (double);
5296                         } else {
5297                                 *(float*)code = *(float*)patch_info->data.target;
5298                                 code += sizeof (float);
5299                         }
5300
5301                         remove = TRUE;
5302                         break;
5303                 }
5304                 default:
5305                         break;
5306                 }
5307
5308                 if (remove) {
5309                         if (patch_info == cfg->patch_info)
5310                                 cfg->patch_info = patch_info->next;
5311                         else {
5312                                 MonoJumpInfo *tmp;
5313
5314                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5315                                         ;
5316                                 tmp->next = patch_info->next;
5317                         }
5318                 }
5319         }
5320
5321         cfg->code_len = code - cfg->native_code;
5322
5323         g_assert (cfg->code_len < cfg->code_size);
5324
5325 }
5326
5327 void*
5328 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5329 {
5330         guchar *code = p;
5331         CallInfo *cinfo = NULL;
5332         MonoMethodSignature *sig;
5333         MonoInst *inst;
5334         int i, n, stack_area = 0;
5335
5336         /* Keep this in sync with mono_arch_get_argument_info */
5337
5338         if (enable_arguments) {
5339                 /* Allocate a new area on the stack and save arguments there */
5340                 sig = mono_method_signature (cfg->method);
5341
5342                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5343
5344                 n = sig->param_count + sig->hasthis;
5345
5346                 stack_area = ALIGN_TO (n * 8, 16);
5347
5348                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5349
5350                 for (i = 0; i < n; ++i) {
5351                         inst = cfg->args [i];
5352
5353                         if (inst->opcode == OP_REGVAR)
5354                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5355                         else {
5356                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5357                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5358                         }
5359                 }
5360         }
5361
5362         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5363         amd64_set_reg_template (code, AMD64_ARG_REG1);
5364         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5365         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5366
5367         if (enable_arguments)
5368                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5369
5370         return code;
5371 }
5372
5373 enum {
5374         SAVE_NONE,
5375         SAVE_STRUCT,
5376         SAVE_EAX,
5377         SAVE_EAX_EDX,
5378         SAVE_XMM
5379 };
5380
5381 void*
5382 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5383 {
5384         guchar *code = p;
5385         int save_mode = SAVE_NONE;
5386         MonoMethod *method = cfg->method;
5387         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5388
5389         switch (rtype) {
5390         case MONO_TYPE_VOID:
5391                 /* special case string .ctor icall */
5392                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5393                         save_mode = SAVE_EAX;
5394                 else
5395                         save_mode = SAVE_NONE;
5396                 break;
5397         case MONO_TYPE_I8:
5398         case MONO_TYPE_U8:
5399                 save_mode = SAVE_EAX;
5400                 break;
5401         case MONO_TYPE_R4:
5402         case MONO_TYPE_R8:
5403                 save_mode = SAVE_XMM;
5404                 break;
5405         case MONO_TYPE_GENERICINST:
5406                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5407                         save_mode = SAVE_EAX;
5408                         break;
5409                 }
5410                 /* Fall through */
5411         case MONO_TYPE_VALUETYPE:
5412                 save_mode = SAVE_STRUCT;
5413                 break;
5414         default:
5415                 save_mode = SAVE_EAX;
5416                 break;
5417         }
5418
5419         /* Save the result and copy it into the proper argument register */
5420         switch (save_mode) {
5421         case SAVE_EAX:
5422                 amd64_push_reg (code, AMD64_RAX);
5423                 /* Align stack */
5424                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5425                 if (enable_arguments)
5426                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5427                 break;
5428         case SAVE_STRUCT:
5429                 /* FIXME: */
5430                 if (enable_arguments)
5431                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5432                 break;
5433         case SAVE_XMM:
5434                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5435                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5436                 /* Align stack */
5437                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5438                 /*
5439                  * The result is already in the proper argument register so no copying
5440                  * needed.
5441                  */
5442                 break;
5443         case SAVE_NONE:
5444                 break;
5445         default:
5446                 g_assert_not_reached ();
5447         }
5448
5449         /* Set %al since this is a varargs call */
5450         if (save_mode == SAVE_XMM)
5451                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5452         else
5453                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5454
5455         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5456         amd64_set_reg_template (code, AMD64_ARG_REG1);
5457         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5458
5459         /* Restore result */
5460         switch (save_mode) {
5461         case SAVE_EAX:
5462                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5463                 amd64_pop_reg (code, AMD64_RAX);
5464                 break;
5465         case SAVE_STRUCT:
5466                 /* FIXME: */
5467                 break;
5468         case SAVE_XMM:
5469                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5470                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5471                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5472                 break;
5473         case SAVE_NONE:
5474                 break;
5475         default:
5476                 g_assert_not_reached ();
5477         }
5478
5479         return code;
5480 }
5481
5482 void
5483 mono_arch_flush_icache (guint8 *code, gint size)
5484 {
5485         /* Not needed */
5486 }
5487
5488 void
5489 mono_arch_flush_register_windows (void)
5490 {
5491 }
5492
5493 gboolean
5494 mono_arch_is_inst_imm (gint64 imm)
5495 {
5496         return amd64_is_imm32 (imm);
5497 }
5498
5499 /*
5500  * Determine whenever the trap whose info is in SIGINFO is caused by
5501  * integer overflow.
5502  */
5503 gboolean
5504 mono_arch_is_int_overflow (void *sigctx, void *info)
5505 {
5506         MonoContext ctx;
5507         guint8* rip;
5508         int reg;
5509         gint64 value;
5510
5511         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5512
5513         rip = (guint8*)ctx.rip;
5514
5515         if (IS_REX (rip [0])) {
5516                 reg = amd64_rex_b (rip [0]);
5517                 rip ++;
5518         }
5519         else
5520                 reg = 0;
5521
5522         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5523                 /* idiv REG */
5524                 reg += x86_modrm_rm (rip [1]);
5525
5526                 switch (reg) {
5527                 case AMD64_RAX:
5528                         value = ctx.rax;
5529                         break;
5530                 case AMD64_RBX:
5531                         value = ctx.rbx;
5532                         break;
5533                 case AMD64_RCX:
5534                         value = ctx.rcx;
5535                         break;
5536                 case AMD64_RDX:
5537                         value = ctx.rdx;
5538                         break;
5539                 case AMD64_RBP:
5540                         value = ctx.rbp;
5541                         break;
5542                 case AMD64_RSP:
5543                         value = ctx.rsp;
5544                         break;
5545                 case AMD64_RSI:
5546                         value = ctx.rsi;
5547                         break;
5548                 case AMD64_RDI:
5549                         value = ctx.rdi;
5550                         break;
5551                 case AMD64_R12:
5552                         value = ctx.r12;
5553                         break;
5554                 case AMD64_R13:
5555                         value = ctx.r13;
5556                         break;
5557                 case AMD64_R14:
5558                         value = ctx.r14;
5559                         break;
5560                 case AMD64_R15:
5561                         value = ctx.r15;
5562                         break;
5563                 default:
5564                         g_assert_not_reached ();
5565                         reg = -1;
5566                 }
5567
5568                 if (value == -1)
5569                         return TRUE;
5570         }
5571
5572         return FALSE;
5573 }
5574
5575 guint32
5576 mono_arch_get_patch_offset (guint8 *code)
5577 {
5578         return 3;
5579 }
5580
5581 /**
5582  * mono_breakpoint_clean_code:
5583  *
5584  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5585  * breakpoints in the original code, they are removed in the copy.
5586  *
5587  * Returns TRUE if no sw breakpoint was present.
5588  */
5589 gboolean
5590 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5591 {
5592         int i;
5593         gboolean can_write = TRUE;
5594         /*
5595          * If method_start is non-NULL we need to perform bound checks, since we access memory
5596          * at code - offset we could go before the start of the method and end up in a different
5597          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5598          * instead.
5599          */
5600         if (!method_start || code - offset >= method_start) {
5601                 memcpy (buf, code - offset, size);
5602         } else {
5603                 int diff = code - method_start;
5604                 memset (buf, 0, size);
5605                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5606         }
5607         code -= offset;
5608         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5609                 int idx = mono_breakpoint_info_index [i];
5610                 guint8 *ptr;
5611                 if (idx < 1)
5612                         continue;
5613                 ptr = mono_breakpoint_info [idx].address;
5614                 if (ptr >= code && ptr < code + size) {
5615                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5616                         can_write = FALSE;
5617                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5618                         buf [ptr - code] = saved_byte;
5619                 }
5620         }
5621         return can_write;
5622 }
5623
5624 gpointer
5625 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5626 {
5627         guint8 buf [10];
5628         guint32 reg;
5629         gint32 disp;
5630         guint8 rex = 0;
5631
5632         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5633         code = buf + 9;
5634
5635         *displacement = 0;
5636
5637         /* go to the start of the call instruction
5638          *
5639          * address_byte = (m << 6) | (o << 3) | reg
5640          * call opcode: 0xff address_byte displacement
5641          * 0xff m=1,o=2 imm8
5642          * 0xff m=2,o=2 imm32
5643          */
5644         code -= 7;
5645
5646         /*
5647          * A given byte sequence can match more than case here, so we have to be
5648          * really careful about the ordering of the cases. Longer sequences
5649          * come first.
5650          */
5651 #ifdef MONO_ARCH_HAVE_IMT
5652         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5653                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5654                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5655                  * ff 50 fc                call   *0xfffffffc(%rax)
5656                  */
5657                 reg = amd64_modrm_rm (code [5]);
5658                 disp = (signed char)code [6];
5659                 /* R10 is clobbered by the IMT thunk code */
5660                 g_assert (reg != AMD64_R10);
5661         }
5662 #else
5663         if (0) {
5664         }
5665 #endif
5666         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5667                         /*
5668                          * This is a interface call
5669                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5670                          * ff 10                  callq  *(%rax)
5671                          */
5672                 if (IS_REX (code [4]))
5673                         rex = code [4];
5674                 reg = amd64_modrm_rm (code [6]);
5675                 disp = 0;
5676                 /* R10 is clobbered by the IMT thunk code */
5677                 g_assert (reg != AMD64_R10);
5678         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5679                 /* call OFFSET(%rip) */
5680                 disp = *(guint32*)(code + 3);
5681                 return (gpointer*)(code + disp + 7);
5682         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5683                 /* call *[r12+disp32] */
5684                 if (IS_REX (code [-1]))
5685                         rex = code [-1];
5686                 reg = AMD64_RSP;
5687                 disp = *(gint32*)(code + 3);
5688         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5689                 /* call *[reg+disp32] */
5690                 if (IS_REX (code [0]))
5691                         rex = code [0];
5692                 reg = amd64_modrm_rm (code [2]);
5693                 disp = *(gint32*)(code + 3);
5694                 /* R10 is clobbered by the IMT thunk code */
5695                 g_assert (reg != AMD64_R10);
5696         } else if (code [2] == 0xe8) {
5697                 /* call <ADDR> */
5698                 return NULL;
5699         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5700                 /* call *[r12+disp32] */
5701                 if (IS_REX (code [2]))
5702                         rex = code [2];
5703                 reg = AMD64_RSP;
5704                 disp = *(gint8*)(code + 6);
5705         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5706                 /* call *%reg */
5707                 return NULL;
5708         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5709                 /* call *[reg+disp8] */
5710                 if (IS_REX (code [3]))
5711                         rex = code [3];
5712                 reg = amd64_modrm_rm (code [5]);
5713                 disp = *(gint8*)(code + 6);
5714                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5715         }
5716         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5717                         /*
5718                          * This is a interface call: should check the above code can't catch it earlier
5719                          * 8b 40 30   mov    0x30(%eax),%eax
5720                          * ff 10      call   *(%eax)
5721                          */
5722                 if (IS_REX (code [4]))
5723                         rex = code [4];
5724                 reg = amd64_modrm_rm (code [6]);
5725                 disp = 0;
5726         }
5727         else
5728                 g_assert_not_reached ();
5729
5730         reg += amd64_rex_b (rex);
5731
5732         /* R11 is clobbered by the trampoline code */
5733         g_assert (reg != AMD64_R11);
5734
5735         *displacement = disp;
5736         return regs [reg];
5737 }
5738
5739 gpointer*
5740 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5741 {
5742         gpointer vt;
5743         int displacement;
5744         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5745         if (!vt)
5746                 return NULL;
5747         return (gpointer*)((char*)vt + displacement);
5748 }
5749
5750 int
5751 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5752 {
5753         int this_reg = AMD64_ARG_REG1;
5754
5755         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5756                 CallInfo *cinfo;
5757
5758                 if (!gsctx && code)
5759                         gsctx = mono_get_generic_context_from_code (code);
5760
5761                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5762
5763                 if (cinfo->ret.storage != ArgValuetypeInReg)
5764                         this_reg = AMD64_ARG_REG2;
5765                 g_free (cinfo);
5766         }
5767
5768         return this_reg;
5769 }
5770
5771 gpointer
5772 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5773 {
5774         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
5775 }
5776
5777 #define MAX_ARCH_DELEGATE_PARAMS 10
5778
5779 gpointer
5780 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5781 {
5782         guint8 *code, *start;
5783         int i;
5784
5785         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5786                 return NULL;
5787
5788         /* FIXME: Support more cases */
5789         if (MONO_TYPE_ISSTRUCT (sig->ret))
5790                 return NULL;
5791
5792         if (has_target) {
5793                 static guint8* cached = NULL;
5794
5795                 if (cached)
5796                         return cached;
5797
5798                 start = code = mono_global_codeman_reserve (64);
5799
5800                 /* Replace the this argument with the target */
5801                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5802                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5803                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5804
5805                 g_assert ((code - start) < 64);
5806
5807                 mono_debug_add_delegate_trampoline (start, code - start);
5808
5809                 mono_memory_barrier ();
5810
5811                 cached = start;
5812         } else {
5813                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5814                 for (i = 0; i < sig->param_count; ++i)
5815                         if (!mono_is_regsize_var (sig->params [i]))
5816                                 return NULL;
5817                 if (sig->param_count > 4)
5818                         return NULL;
5819
5820                 code = cache [sig->param_count];
5821                 if (code)
5822                         return code;
5823
5824                 start = code = mono_global_codeman_reserve (64);
5825
5826                 if (sig->param_count == 0) {
5827                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5828                 } else {
5829                         /* We have to shift the arguments left */
5830                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5831                         for (i = 0; i < sig->param_count; ++i) {
5832 #ifdef PLATFORM_WIN32
5833                                 if (i < 3)
5834                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5835                                 else
5836                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
5837 #else
5838                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5839 #endif
5840                         }
5841
5842                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5843                 }
5844                 g_assert ((code - start) < 64);
5845
5846                 mono_debug_add_delegate_trampoline (start, code - start);
5847
5848                 mono_memory_barrier ();
5849
5850                 cache [sig->param_count] = start;
5851         }
5852
5853         return start;
5854 }
5855
5856 /*
5857  * Support for fast access to the thread-local lmf structure using the GS
5858  * segment register on NPTL + kernel 2.6.x.
5859  */
5860
5861 static gboolean tls_offset_inited = FALSE;
5862
5863 void
5864 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5865 {
5866         if (!tls_offset_inited) {
5867 #ifdef PLATFORM_WIN32
5868                 /*
5869                  * We need to init this multiple times, since when we are first called, the key might not
5870                  * be initialized yet.
5871                  */
5872                 appdomain_tls_offset = mono_domain_get_tls_key ();
5873                 lmf_tls_offset = mono_get_jit_tls_key ();
5874                 thread_tls_offset = mono_thread_get_tls_key ();
5875                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
5876
5877                 /* Only 64 tls entries can be accessed using inline code */
5878                 if (appdomain_tls_offset >= 64)
5879                         appdomain_tls_offset = -1;
5880                 if (lmf_tls_offset >= 64)
5881                         lmf_tls_offset = -1;
5882                 if (thread_tls_offset >= 64)
5883                         thread_tls_offset = -1;
5884 #else
5885                 tls_offset_inited = TRUE;
5886 #ifdef MONO_XEN_OPT
5887                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5888 #endif
5889                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5890                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5891                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5892                 thread_tls_offset = mono_thread_get_tls_offset ();
5893 #endif
5894         }
5895 }
5896
5897 void
5898 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5899 {
5900 }
5901
5902 #ifdef MONO_ARCH_HAVE_IMT
5903
5904 #define CMP_SIZE (6 + 1)
5905 #define CMP_REG_REG_SIZE (4 + 1)
5906 #define BR_SMALL_SIZE 2
5907 #define BR_LARGE_SIZE 6
5908 #define MOV_REG_IMM_SIZE 10
5909 #define MOV_REG_IMM_32BIT_SIZE 6
5910 #define JUMP_REG_SIZE (2 + 1)
5911
5912 static int
5913 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5914 {
5915         int i, distance = 0;
5916         for (i = start; i < target; ++i)
5917                 distance += imt_entries [i]->chunk_size;
5918         return distance;
5919 }
5920
5921 /*
5922  * LOCKING: called with the domain lock held
5923  */
5924 gpointer
5925 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5926         gpointer fail_tramp)
5927 {
5928         int i;
5929         int size = 0;
5930         guint8 *code, *start;
5931         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5932
5933         for (i = 0; i < count; ++i) {
5934                 MonoIMTCheckItem *item = imt_entries [i];
5935                 if (item->is_equals) {
5936                         if (item->check_target_idx) {
5937                                 if (!item->compare_done) {
5938                                         if (amd64_is_imm32 (item->key))
5939                                                 item->chunk_size += CMP_SIZE;
5940                                         else
5941                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5942                                 }
5943                                 if (vtable_is_32bit)
5944                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5945                                 else
5946                                         item->chunk_size += MOV_REG_IMM_SIZE;
5947                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5948                         } else {
5949                                 if (fail_tramp) {
5950                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
5951                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
5952                                 } else {
5953                                         if (vtable_is_32bit)
5954                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5955                                         else
5956                                                 item->chunk_size += MOV_REG_IMM_SIZE;
5957                                         item->chunk_size += JUMP_REG_SIZE;
5958                                         /* with assert below:
5959                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5960                                          */
5961                                 }
5962                         }
5963                 } else {
5964                         if (amd64_is_imm32 (item->key))
5965                                 item->chunk_size += CMP_SIZE;
5966                         else
5967                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5968                         item->chunk_size += BR_LARGE_SIZE;
5969                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5970                 }
5971                 size += item->chunk_size;
5972         }
5973         if (fail_tramp)
5974                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5975         else
5976                 code = mono_code_manager_reserve (domain->code_mp, size);
5977         start = code;
5978         for (i = 0; i < count; ++i) {
5979                 MonoIMTCheckItem *item = imt_entries [i];
5980                 item->code_target = code;
5981                 if (item->is_equals) {
5982                         if (item->check_target_idx) {
5983                                 if (!item->compare_done) {
5984                                         if (amd64_is_imm32 (item->key))
5985                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5986                                         else {
5987                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5988                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5989                                         }
5990                                 }
5991                                 item->jmp_code = code;
5992                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5993                                 /* See the comment below about R10 */
5994                                 if (fail_tramp) {
5995                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5996                                         amd64_jump_reg (code, AMD64_R10);
5997                                 } else {
5998                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5999                                         amd64_jump_membase (code, AMD64_R10, 0);
6000                                 }
6001                         } else {
6002                                 if (fail_tramp) {
6003                                         if (amd64_is_imm32 (item->key))
6004                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6005                                         else {
6006                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6007                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6008                                         }
6009                                         item->jmp_code = code;
6010                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6011                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
6012                                         amd64_jump_reg (code, AMD64_R10);
6013                                         amd64_patch (item->jmp_code, code);
6014                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
6015                                         amd64_jump_reg (code, AMD64_R10);
6016                                         item->jmp_code = NULL;
6017
6018                                 } else {
6019                                         /* enable the commented code to assert on wrong method */
6020 #if 0
6021                                         if (amd64_is_imm32 (item->key))
6022                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6023                                         else {
6024                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6025                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6026                                         }
6027                                         item->jmp_code = code;
6028                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6029                                         /* See the comment below about R10 */
6030                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6031                                         amd64_jump_membase (code, AMD64_R10, 0);
6032                                         amd64_patch (item->jmp_code, code);
6033                                         amd64_breakpoint (code);
6034                                         item->jmp_code = NULL;
6035 #else
6036                                         /* We're using R10 here because R11
6037                                            needs to be preserved.  R10 needs
6038                                            to be preserved for calls which
6039                                            require a runtime generic context,
6040                                            but interface calls don't. */
6041                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6042                                         amd64_jump_membase (code, AMD64_R10, 0);
6043 #endif
6044                                 }
6045                         }
6046                 } else {
6047                         if (amd64_is_imm32 (item->key))
6048                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6049                         else {
6050                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6051                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6052                         }
6053                         item->jmp_code = code;
6054                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6055                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6056                         else
6057                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6058                 }
6059                 g_assert (code - item->code_target <= item->chunk_size);
6060         }
6061         /* patch the branches to get to the target items */
6062         for (i = 0; i < count; ++i) {
6063                 MonoIMTCheckItem *item = imt_entries [i];
6064                 if (item->jmp_code) {
6065                         if (item->check_target_idx) {
6066                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6067                         }
6068                 }
6069         }
6070
6071         if (!fail_tramp)
6072                 mono_stats.imt_thunks_size += code - start;
6073         g_assert (code - start <= size);
6074
6075         return start;
6076 }
6077
6078 MonoMethod*
6079 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6080 {
6081         return regs [MONO_ARCH_IMT_REG];
6082 }
6083
6084 MonoObject*
6085 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6086 {
6087         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6088 }
6089
6090 void
6091 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6092 {
6093         /* Done by the implementation of the CALL_MEMBASE opcodes */
6094 }
6095 #endif
6096
6097 MonoVTable*
6098 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6099 {
6100         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6101 }
6102
6103 MonoInst*
6104 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6105 {
6106         MonoInst *ins = NULL;
6107         int opcode = 0;
6108
6109         if (cmethod->klass == mono_defaults.math_class) {
6110                 if (strcmp (cmethod->name, "Sin") == 0) {
6111                         opcode = OP_SIN;
6112                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6113                         opcode = OP_COS;
6114                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6115                         opcode = OP_SQRT;
6116                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6117                         opcode = OP_ABS;
6118                 }
6119
6120                 if (opcode) {
6121                         MONO_INST_NEW (cfg, ins, opcode);
6122                         ins->type = STACK_R8;
6123                         ins->dreg = mono_alloc_freg (cfg);
6124                         ins->sreg1 = args [0]->dreg;
6125                         MONO_ADD_INS (cfg->cbb, ins);
6126                 }
6127
6128                 opcode = 0;
6129                 if (cfg->opt & MONO_OPT_CMOV) {
6130                         if (strcmp (cmethod->name, "Min") == 0) {
6131                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6132                                         opcode = OP_IMIN;
6133                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6134                                         opcode = OP_IMIN_UN;
6135                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6136                                         opcode = OP_LMIN;
6137                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6138                                         opcode = OP_LMIN_UN;
6139                         } else if (strcmp (cmethod->name, "Max") == 0) {
6140                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6141                                         opcode = OP_IMAX;
6142                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6143                                         opcode = OP_IMAX_UN;
6144                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6145                                         opcode = OP_LMAX;
6146                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6147                                         opcode = OP_LMAX_UN;
6148                         }
6149                 }
6150
6151                 if (opcode) {
6152                         MONO_INST_NEW (cfg, ins, opcode);
6153                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6154                         ins->dreg = mono_alloc_ireg (cfg);
6155                         ins->sreg1 = args [0]->dreg;
6156                         ins->sreg2 = args [1]->dreg;
6157                         MONO_ADD_INS (cfg->cbb, ins);
6158                 }
6159
6160 #if 0
6161                 /* OP_FREM is not IEEE compatible */
6162                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6163                         MONO_INST_NEW (cfg, ins, OP_FREM);
6164                         ins->inst_i0 = args [0];
6165                         ins->inst_i1 = args [1];
6166                 }
6167 #endif
6168         }
6169
6170         /*
6171          * Can't implement CompareExchange methods this way since they have
6172          * three arguments.
6173          */
6174
6175         return ins;
6176 }
6177
6178 gboolean
6179 mono_arch_print_tree (MonoInst *tree, int arity)
6180 {
6181         return 0;
6182 }
6183
6184 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6185 {
6186         MonoInst* ins;
6187
6188         if (appdomain_tls_offset == -1)
6189                 return NULL;
6190
6191         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6192         ins->inst_offset = appdomain_tls_offset;
6193         return ins;
6194 }
6195
6196 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6197 {
6198         MonoInst* ins;
6199
6200         if (thread_tls_offset == -1)
6201                 return NULL;
6202
6203         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6204         ins->inst_offset = thread_tls_offset;
6205         return ins;
6206 }
6207
6208 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6209
6210 gpointer
6211 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6212 {
6213         switch (reg) {
6214         case AMD64_RCX: return (gpointer)ctx->rcx;
6215         case AMD64_RDX: return (gpointer)ctx->rdx;
6216         case AMD64_RBX: return (gpointer)ctx->rbx;
6217         case AMD64_RBP: return (gpointer)ctx->rbp;
6218         case AMD64_RSP: return (gpointer)ctx->rsp;
6219         default:
6220                 if (reg < 8)
6221                         return _CTX_REG (ctx, rax, reg);
6222                 else if (reg >= 12)
6223                         return _CTX_REG (ctx, r12, reg - 12);
6224                 else
6225                         g_assert_not_reached ();
6226         }
6227 }