mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/appdomain.h>
  24 #include <mono/metadata/debug-helpers.h>
  25 #include <mono/metadata/threads.h>
  26 #include <mono/metadata/profiler-private.h>
  27 #include <mono/metadata/mono-debug.h>
  28 #include <mono/metadata/gc-internal.h>
  29 #include <mono/utils/mono-math.h>
  30 #include <mono/utils/mono-mmap.h>
  31 #include <mono/utils/mono-memory-model.h>
  32 #include <mono/utils/mono-tls.h>
  33 #include <mono/utils/mono-hwcap-x86.h>
  34
  35 #include "trace.h"
  36 #include "ir-emit.h"
  37 #include "mini-amd64.h"
  38 #include "cpu-amd64.h"
  39 #include "debugger-agent.h"
  40 #include "mini-gc.h"
  41
  42 #ifdef HOST_WIN32
  43 static gint jit_tls_offset = -1;
  44 #endif
  45
  46 #ifdef MONO_XEN_OPT
  47 static gboolean optimize_for_xen = TRUE;
  48 #else
  49 #define optimize_for_xen 0
  50 #endif
  51
  52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  53
  54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  55
  56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  57
  58 #ifdef HOST_WIN32
  59 /* Under windows, the calling convention is never stdcall */
  60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  61 #else
  62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  63 #endif
  64
  65 /* This mutex protects architecture specific caches */
  66 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  67 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  68 static CRITICAL_SECTION mini_arch_mutex;
  69
  70 MonoBreakpointInfo
  71 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  72
  73 /* Structure used by the sequence points in AOTed code */
  74 typedef struct {
  75         gpointer ss_trigger_page;
  76         gpointer bp_trigger_page;
  77         gpointer bp_addrs [MONO_ZERO_LEN_ARRAY];
  78 } SeqPointInfo;
  79
  80 /*
  81  * The code generated for sequence points reads from this location, which is
  82  * made read-only when single stepping is enabled.
  83  */
  84 static gpointer ss_trigger_page;
  85
  86 /* Enabled breakpoints read from this trigger page */
  87 static gpointer bp_trigger_page;
  88
  89 /* The size of the breakpoint sequence */
  90 static int breakpoint_size;
  91
  92 /* The size of the breakpoint instruction causing the actual fault */
  93 static int breakpoint_fault_size;
  94
  95 /* The size of the single step instruction causing the actual fault */
  96 static int single_step_fault_size;
  97
  98 #ifdef HOST_WIN32
  99 /* On Win64 always reserve first 32 bytes for first four arguments */
 100 #define ARGS_OFFSET 48
 101 #else
 102 #define ARGS_OFFSET 16
 103 #endif
 104 #define GP_SCRATCH_REG AMD64_R11
 105
 106 /*
 107  * AMD64 register usage:
 108  * - callee saved registers are used for global register allocation
 109  * - %r11 is used for materializing 64 bit constants in opcodes
 110  * - the rest is used for local allocation
 111  */
 112
 113 /*
 114  * Floating point comparison results:
 115  *                  ZF PF CF
 116  * A > B            0  0  0
 117  * A < B            0  0  1
 118  * A = B            1  0  0
 119  * A > B            0  0  0
 120  * UNORDERED        1  1  1
 121  */
 122
 123 const char*
 124 mono_arch_regname (int reg)
 125 {
 126         switch (reg) {
 127         case AMD64_RAX: return "%rax";
 128         case AMD64_RBX: return "%rbx";
 129         case AMD64_RCX: return "%rcx";
 130         case AMD64_RDX: return "%rdx";
 131         case AMD64_RSP: return "%rsp";
 132         case AMD64_RBP: return "%rbp";
 133         case AMD64_RDI: return "%rdi";
 134         case AMD64_RSI: return "%rsi";
 135         case AMD64_R8: return "%r8";
 136         case AMD64_R9: return "%r9";
 137         case AMD64_R10: return "%r10";
 138         case AMD64_R11: return "%r11";
 139         case AMD64_R12: return "%r12";
 140         case AMD64_R13: return "%r13";
 141         case AMD64_R14: return "%r14";
 142         case AMD64_R15: return "%r15";
 143         }
 144         return "unknown";
 145 }
 146
 147 static const char * packed_xmmregs [] = {
 148         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 149         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 150 };
 151
 152 static const char * single_xmmregs [] = {
 153         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 154         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 155 };
 156
 157 const char*
 158 mono_arch_fregname (int reg)
 159 {
 160         if (reg < AMD64_XMM_NREG)
 161                 return single_xmmregs [reg];
 162         else
 163                 return "unknown";
 164 }
 165
 166 const char *
 167 mono_arch_xregname (int reg)
 168 {
 169         if (reg < AMD64_XMM_NREG)
 170                 return packed_xmmregs [reg];
 171         else
 172                 return "unknown";
 173 }
 174
 175 static gboolean
 176 debug_omit_fp (void)
 177 {
 178 #if 0
 179         return mono_debug_count ();
 180 #else
 181         return TRUE;
 182 #endif
 183 }
 184
 185 static inline gboolean
 186 amd64_is_near_call (guint8 *code)
 187 {
 188         /* Skip REX */
 189         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 190                 code += 1;
 191
 192         return code [0] == 0xe8;
 193 }
 194
 195 #ifdef __native_client_codegen__
 196
 197 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 198 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 199 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 200 /* We only want to force bundle alignment for the top level instruction,    */
 201 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 202 static MonoNativeTlsKey nacl_instruction_depth;
 203
 204 static MonoNativeTlsKey nacl_rex_tag;
 205 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 206
 207 void
 208 amd64_nacl_clear_legacy_prefix_tag ()
 209 {
 210         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 211 }
 212
 213 void
 214 amd64_nacl_tag_legacy_prefix (guint8* code)
 215 {
 216         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 217                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 218 }
 219
 220 void
 221 amd64_nacl_tag_rex (guint8* code)
 222 {
 223         mono_native_tls_set_value (nacl_rex_tag, code);
 224 }
 225
 226 guint8*
 227 amd64_nacl_get_legacy_prefix_tag ()
 228 {
 229         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 230 }
 231
 232 guint8*
 233 amd64_nacl_get_rex_tag ()
 234 {
 235         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 236 }
 237
 238 /* Increment the instruction "depth" described above */
 239 void
 240 amd64_nacl_instruction_pre ()
 241 {
 242         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 243         depth++;
 244         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 245 }
 246
 247 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 248 /* alignment if depth == 0 (top level instruction)                          */
 249 /* IN: start, end    pointers to instruction beginning and end              */
 250 /* OUT: start, end   pointers to beginning and end after possible alignment */
 251 /* GLOBALS: nacl_instruction_depth     defined above                        */
 252 void
 253 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 254 {
 255         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 256         depth--;
 257         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 258
 259         g_assert ( depth >= 0 );
 260         if (depth == 0) {
 261                 uintptr_t space_in_block;
 262                 uintptr_t instlen;
 263                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 264                 /* if legacy prefix is present, and if it was emitted before */
 265                 /* the start of the instruction sequence, adjust the start   */
 266                 if (prefix != NULL && prefix < *start) {
 267                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 268                         *start = prefix;
 269                 }
 270                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 271                 instlen = (uintptr_t)(*end - *start);
 272                 /* Only check for instructions which are less than        */
 273                 /* kNaClAlignment. The only instructions that should ever */
 274                 /* be that long are call sequences, which are already     */
 275                 /* padded out to align the return to the next bundle.     */
 276                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 277                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 278                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 279                         const size_t length = (size_t)((*end)-(*start));
 280                         g_assert (length < MAX_NACL_INST_LENGTH);
 281
 282                         memcpy (copy_of_instruction, *start, length);
 283                         *start = mono_arch_nacl_pad (*start, space_in_block);
 284                         memcpy (*start, copy_of_instruction, length);
 285                         *end = *start + length;
 286                 }
 287                 amd64_nacl_clear_legacy_prefix_tag ();
 288                 amd64_nacl_tag_rex (NULL);
 289         }
 290 }
 291
 292 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 293 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 294 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 295 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 296 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 297 /* IN:      code                                                            */
 298 /*             pointer to current instruction stream (in the                */
 299 /*             middle of an instruction, after opcode is emitted)           */
 300 /*          basereg/offset/dreg                                             */
 301 /*             operands of normal membase address                           */
 302 /* OUT:     code                                                            */
 303 /*             pointer to the end of the membase/memindex emit              */
 304 /* GLOBALS: nacl_rex_tag                                                    */
 305 /*             position in instruction stream that rex prefix was emitted   */
 306 /*          nacl_legacy_prefix_tag                                          */
 307 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 308 void
 309 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 310 {
 311         gint8 true_basereg = basereg;
 312
 313         /* Cache these values, they might change  */
 314         /* as new instructions are emitted below. */
 315         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 316         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 317
 318         /* 'basereg' is given masked to 0x7 at this point, so check */
 319         /* the rex prefix to see if this is an extended register.   */
 320         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 321                 true_basereg |= 0x8;
 322         }
 323
 324 #define X86_LEA_OPCODE (0x8D)
 325
 326         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 327                 guint8* old_instruction_start;
 328
 329                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 330                 /* 32-bits of the old base register (new index register)     */
 331                 guint8 buf[32];
 332                 guint8* buf_ptr = buf;
 333                 size_t insert_len;
 334
 335                 g_assert (rex_tag != NULL);
 336
 337                 if (IS_REX(*rex_tag)) {
 338                         /* The old rex.B should be the new rex.X */
 339                         if (*rex_tag & AMD64_REX_B) {
 340                                 *rex_tag |= AMD64_REX_X;
 341                         }
 342                         /* Since our new base is %r15 set rex.B */
 343                         *rex_tag |= AMD64_REX_B;
 344                 } else {
 345                         /* Shift the instruction by one byte  */
 346                         /* so we can insert a rex prefix      */
 347                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 348                         *code += 1;
 349                         /* New rex prefix only needs rex.B for %r15 base */
 350                         *rex_tag = AMD64_REX(AMD64_REX_B);
 351                 }
 352
 353                 if (legacy_prefix_tag) {
 354                         old_instruction_start = legacy_prefix_tag;
 355                 } else {
 356                         old_instruction_start = rex_tag;
 357                 }
 358
 359                 /* Clears the upper 32-bits of the previous base register */
 360                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 361                 insert_len = buf_ptr - buf;
 362
 363                 /* Move the old instruction forward to make */
 364                 /* room for 'mov' stored in 'buf_ptr'       */
 365                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 366                 *code += insert_len;
 367                 memcpy (old_instruction_start, buf, insert_len);
 368
 369                 /* Sandboxed replacement for the normal membase_emit */
 370                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 371
 372         } else {
 373                 /* Normal default behavior, emit membase memory location */
 374                 x86_membase_emit_body (*code, dreg, basereg, offset);
 375         }
 376 }
 377
 378
 379 static inline unsigned char*
 380 amd64_skip_nops (unsigned char* code)
 381 {
 382         guint8 in_nop;
 383         do {
 384                 in_nop = 0;
 385                 if (   code[0] == 0x90) {
 386                         in_nop = 1;
 387                         code += 1;
 388                 }
 389                 if (   code[0] == 0x66 && code[1] == 0x90) {
 390                         in_nop = 1;
 391                         code += 2;
 392                 }
 393                 if (code[0] == 0x0f && code[1] == 0x1f
 394                  && code[2] == 0x00) {
 395                         in_nop = 1;
 396                         code += 3;
 397                 }
 398                 if (code[0] == 0x0f && code[1] == 0x1f
 399                  && code[2] == 0x40 && code[3] == 0x00) {
 400                         in_nop = 1;
 401                         code += 4;
 402                 }
 403                 if (code[0] == 0x0f && code[1] == 0x1f
 404                  && code[2] == 0x44 && code[3] == 0x00
 405                  && code[4] == 0x00) {
 406                         in_nop = 1;
 407                         code += 5;
 408                 }
 409                 if (code[0] == 0x66 && code[1] == 0x0f
 410                  && code[2] == 0x1f && code[3] == 0x44
 411                  && code[4] == 0x00 && code[5] == 0x00) {
 412                         in_nop = 1;
 413                         code += 6;
 414                 }
 415                 if (code[0] == 0x0f && code[1] == 0x1f
 416                  && code[2] == 0x80 && code[3] == 0x00
 417                  && code[4] == 0x00 && code[5] == 0x00
 418                  && code[6] == 0x00) {
 419                         in_nop = 1;
 420                         code += 7;
 421                 }
 422                 if (code[0] == 0x0f && code[1] == 0x1f
 423                  && code[2] == 0x84 && code[3] == 0x00
 424                  && code[4] == 0x00 && code[5] == 0x00
 425                  && code[6] == 0x00 && code[7] == 0x00) {
 426                         in_nop = 1;
 427                         code += 8;
 428                 }
 429         } while ( in_nop );
 430         return code;
 431 }
 432
 433 guint8*
 434 mono_arch_nacl_skip_nops (guint8* code)
 435 {
 436   return amd64_skip_nops(code);
 437 }
 438
 439 #endif /*__native_client_codegen__*/
 440
 441 static inline void
 442 amd64_patch (unsigned char* code, gpointer target)
 443 {
 444         guint8 rex = 0;
 445
 446 #ifdef __native_client_codegen__
 447         code = amd64_skip_nops (code);
 448 #endif
 449 #if defined(__native_client_codegen__) && defined(__native_client__)
 450         if (nacl_is_code_address (code)) {
 451                 /* For tail calls, code is patched after being installed */
 452                 /* but not through the normal "patch callsite" method.   */
 453                 unsigned char buf[kNaClAlignment];
 454                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 455                 int ret;
 456                 memcpy (buf, aligned_code, kNaClAlignment);
 457                 /* Patch a temp buffer of bundle size, */
 458                 /* then install to actual location.    */
 459                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 460                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 461                 g_assert (ret == 0);
 462                 return;
 463         }
 464         target = nacl_modify_patch_target (target);
 465 #endif
 466
 467         /* Skip REX */
 468         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 469                 rex = code [0];
 470                 code += 1;
 471         }
 472
 473         if ((code [0] & 0xf8) == 0xb8) {
 474                 /* amd64_set_reg_template */
 475                 *(guint64*)(code + 1) = (guint64)target;
 476         }
 477         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 478                 /* mov 0(%rip), %dreg */
 479                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 480         }
 481         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 482                 /* call *<OFFSET>(%rip) */
 483                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 484         }
 485         else if (code [0] == 0xe8) {
 486                 /* call <DISP> */
 487                 gint64 disp = (guint8*)target - (guint8*)code;
 488                 g_assert (amd64_is_imm32 (disp));
 489                 x86_patch (code, (unsigned char*)target);
 490         }
 491         else
 492                 x86_patch (code, (unsigned char*)target);
 493 }
 494
 495 void
 496 mono_amd64_patch (unsigned char* code, gpointer target)
 497 {
 498         amd64_patch (code, target);
 499 }
 500
 501 typedef enum {
 502         ArgInIReg,
 503         ArgInFloatSSEReg,
 504         ArgInDoubleSSEReg,
 505         ArgOnStack,
 506         ArgValuetypeInReg,
 507         ArgValuetypeAddrInIReg,
 508         ArgNone /* only in pair_storage */
 509 } ArgStorage;
 510
 511 typedef struct {
 512         gint16 offset;
 513         gint8  reg;
 514         ArgStorage storage;
 515
 516         /* Only if storage == ArgValuetypeInReg */
 517         ArgStorage pair_storage [2];
 518         gint8 pair_regs [2];
 519         int nregs;
 520 } ArgInfo;
 521
 522 typedef struct {
 523         int nargs;
 524         guint32 stack_usage;
 525         guint32 reg_usage;
 526         guint32 freg_usage;
 527         gboolean need_stack_align;
 528         gboolean vtype_retaddr;
 529         /* The index of the vret arg in the argument list */
 530         int vret_arg_index;
 531         ArgInfo ret;
 532         ArgInfo sig_cookie;
 533         ArgInfo args [1];
 534 } CallInfo;
 535
 536 #define DEBUG(a) if (cfg->verbose_level > 1) a
 537
 538 #ifdef HOST_WIN32
 539 #define PARAM_REGS 4
 540
 541 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 542
 543 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 544 #else
 545 #define PARAM_REGS 6
 546
 547 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 548
 549  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 550 #endif
 551
 552 static void inline
 553 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 554 {
 555     ainfo->offset = *stack_size;
 556
 557     if (*gr >= PARAM_REGS) {
 558                 ainfo->storage = ArgOnStack;
 559                 /* Since the same stack slot size is used for all arg */
 560                 /*  types, it needs to be big enough to hold them all */
 561                 (*stack_size) += sizeof(mgreg_t);
 562     }
 563     else {
 564                 ainfo->storage = ArgInIReg;
 565                 ainfo->reg = param_regs [*gr];
 566                 (*gr) ++;
 567     }
 568 }
 569
 570 #ifdef HOST_WIN32
 571 #define FLOAT_PARAM_REGS 4
 572 #else
 573 #define FLOAT_PARAM_REGS 8
 574 #endif
 575
 576 static void inline
 577 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 578 {
 579     ainfo->offset = *stack_size;
 580
 581     if (*gr >= FLOAT_PARAM_REGS) {
 582                 ainfo->storage = ArgOnStack;
 583                 /* Since the same stack slot size is used for both float */
 584                 /*  types, it needs to be big enough to hold them both */
 585                 (*stack_size) += sizeof(mgreg_t);
 586     }
 587     else {
 588                 /* A double register */
 589                 if (is_double)
 590                         ainfo->storage = ArgInDoubleSSEReg;
 591                 else
 592                         ainfo->storage = ArgInFloatSSEReg;
 593                 ainfo->reg = *gr;
 594                 (*gr) += 1;
 595     }
 596 }
 597
 598 typedef enum ArgumentClass {
 599         ARG_CLASS_NO_CLASS,
 600         ARG_CLASS_MEMORY,
 601         ARG_CLASS_INTEGER,
 602         ARG_CLASS_SSE
 603 } ArgumentClass;
 604
 605 static ArgumentClass
 606 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 607 {
 608         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 609         MonoType *ptype;
 610
 611         ptype = mini_type_get_underlying_type (NULL, type);
 612         switch (ptype->type) {
 613         case MONO_TYPE_BOOLEAN:
 614         case MONO_TYPE_CHAR:
 615         case MONO_TYPE_I1:
 616         case MONO_TYPE_U1:
 617         case MONO_TYPE_I2:
 618         case MONO_TYPE_U2:
 619         case MONO_TYPE_I4:
 620         case MONO_TYPE_U4:
 621         case MONO_TYPE_I:
 622         case MONO_TYPE_U:
 623         case MONO_TYPE_STRING:
 624         case MONO_TYPE_OBJECT:
 625         case MONO_TYPE_CLASS:
 626         case MONO_TYPE_SZARRAY:
 627         case MONO_TYPE_PTR:
 628         case MONO_TYPE_FNPTR:
 629         case MONO_TYPE_ARRAY:
 630         case MONO_TYPE_I8:
 631         case MONO_TYPE_U8:
 632                 class2 = ARG_CLASS_INTEGER;
 633                 break;
 634         case MONO_TYPE_R4:
 635         case MONO_TYPE_R8:
 636 #ifdef HOST_WIN32
 637                 class2 = ARG_CLASS_INTEGER;
 638 #else
 639                 class2 = ARG_CLASS_SSE;
 640 #endif
 641                 break;
 642
 643         case MONO_TYPE_TYPEDBYREF:
 644                 g_assert_not_reached ();
 645
 646         case MONO_TYPE_GENERICINST:
 647                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 648                         class2 = ARG_CLASS_INTEGER;
 649                         break;
 650                 }
 651                 /* fall through */
 652         case MONO_TYPE_VALUETYPE: {
 653                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 654                 int i;
 655
 656                 for (i = 0; i < info->num_fields; ++i) {
 657                         class2 = class1;
 658                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 659                 }
 660                 break;
 661         }
 662         default:
 663                 g_assert_not_reached ();
 664         }
 665
 666         /* Merge */
 667         if (class1 == class2)
 668                 ;
 669         else if (class1 == ARG_CLASS_NO_CLASS)
 670                 class1 = class2;
 671         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 672                 class1 = ARG_CLASS_MEMORY;
 673         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 674                 class1 = ARG_CLASS_INTEGER;
 675         else
 676                 class1 = ARG_CLASS_SSE;
 677
 678         return class1;
 679 }
 680 #ifdef __native_client_codegen__
 681
 682 /* Default alignment for Native Client is 32-byte. */
 683 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 684
 685 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 686 /* Check that alignment doesn't cross an alignment boundary.             */
 687 guint8*
 688 mono_arch_nacl_pad(guint8 *code, int pad)
 689 {
 690         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 691
 692         if (pad == 0) return code;
 693         /* assertion: alignment cannot cross a block boundary */
 694         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 695                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 696         while (pad >= kMaxPadding) {
 697                 amd64_padding (code, kMaxPadding);
 698                 pad -= kMaxPadding;
 699         }
 700         if (pad != 0) amd64_padding (code, pad);
 701         return code;
 702 }
 703 #endif
 704
 705 static void
 706 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 707                            gboolean is_return,
 708                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 709 {
 710         guint32 size, quad, nquads, i;
 711         /* Keep track of the size used in each quad so we can */
 712         /* use the right size when copying args/return vars.  */
 713         guint32 quadsize [2] = {8, 8};
 714         ArgumentClass args [2];
 715         MonoMarshalType *info = NULL;
 716         MonoClass *klass;
 717         MonoGenericSharingContext tmp_gsctx;
 718         gboolean pass_on_stack = FALSE;
 719
 720         /*
 721          * The gsctx currently contains no data, it is only used for checking whenever
 722          * open types are allowed, some callers like mono_arch_get_argument_info ()
 723          * don't pass it to us, so work around that.
 724          */
 725         if (!gsctx)
 726                 gsctx = &tmp_gsctx;
 727
 728         klass = mono_class_from_mono_type (type);
 729         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 730 #ifndef HOST_WIN32
 731         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 732                 /* We pass and return vtypes of size 8 in a register */
 733         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 734                 pass_on_stack = TRUE;
 735         }
 736 #else
 737         if (!sig->pinvoke) {
 738                 pass_on_stack = TRUE;
 739         }
 740 #endif
 741
 742         /* If this struct can't be split up naturally into 8-byte */
 743         /* chunks (registers), pass it on the stack.              */
 744         if (sig->pinvoke && !pass_on_stack) {
 745                 guint32 align;
 746                 guint32 field_size;
 747
 748                 info = mono_marshal_load_type_info (klass);
 749                 g_assert(info);
 750                 for (i = 0; i < info->num_fields; ++i) {
 751                         field_size = mono_marshal_type_size (info->fields [i].field->type,
 752                                                            info->fields [i].mspec,
 753                                                            &align, TRUE, klass->unicode);
 754                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
 755                                 pass_on_stack = TRUE;
 756                                 break;
 757                         }
 758                 }
 759         }
 760
 761         if (pass_on_stack) {
 762                 /* Allways pass in memory */
 763                 ainfo->offset = *stack_size;
 764                 *stack_size += ALIGN_TO (size, 8);
 765                 ainfo->storage = ArgOnStack;
 766
 767                 return;
 768         }
 769
 770         /* FIXME: Handle structs smaller than 8 bytes */
 771         //if ((size % 8) != 0)
 772         //      NOT_IMPLEMENTED;
 773
 774         if (size > 8)
 775                 nquads = 2;
 776         else
 777                 nquads = 1;
 778
 779         if (!sig->pinvoke) {
 780                 /* Always pass in 1 or 2 integer registers */
 781                 args [0] = ARG_CLASS_INTEGER;
 782                 args [1] = ARG_CLASS_INTEGER;
 783                 /* Only the simplest cases are supported */
 784                 if (is_return && nquads != 1) {
 785                         args [0] = ARG_CLASS_MEMORY;
 786                         args [1] = ARG_CLASS_MEMORY;
 787                 }
 788         } else {
 789                 /*
 790                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 791                  * The X87 and SSEUP stuff is left out since there are no such types in
 792                  * the CLR.
 793                  */
 794                 info = mono_marshal_load_type_info (klass);
 795                 g_assert (info);
 796
 797 #ifndef HOST_WIN32
 798                 if (info->native_size > 16) {
 799                         ainfo->offset = *stack_size;
 800                         *stack_size += ALIGN_TO (info->native_size, 8);
 801                         ainfo->storage = ArgOnStack;
 802
 803                         return;
 804                 }
 805 #else
 806                 switch (info->native_size) {
 807                 case 1: case 2: case 4: case 8:
 808                         break;
 809                 default:
 810                         if (is_return) {
 811                                 ainfo->storage = ArgOnStack;
 812                                 ainfo->offset = *stack_size;
 813                                 *stack_size += ALIGN_TO (info->native_size, 8);
 814                         }
 815                         else {
 816                                 ainfo->storage = ArgValuetypeAddrInIReg;
 817
 818                                 if (*gr < PARAM_REGS) {
 819                                         ainfo->pair_storage [0] = ArgInIReg;
 820                                         ainfo->pair_regs [0] = param_regs [*gr];
 821                                         (*gr) ++;
 822                                 }
 823                                 else {
 824                                         ainfo->pair_storage [0] = ArgOnStack;
 825                                         ainfo->offset = *stack_size;
 826                                         *stack_size += 8;
 827                                 }
 828                         }
 829
 830                         return;
 831                 }
 832 #endif
 833
 834                 args [0] = ARG_CLASS_NO_CLASS;
 835                 args [1] = ARG_CLASS_NO_CLASS;
 836                 for (quad = 0; quad < nquads; ++quad) {
 837                         int size;
 838                         guint32 align;
 839                         ArgumentClass class1;
 840
 841                         if (info->num_fields == 0)
 842                                 class1 = ARG_CLASS_MEMORY;
 843                         else
 844                                 class1 = ARG_CLASS_NO_CLASS;
 845                         for (i = 0; i < info->num_fields; ++i) {
 846                                 size = mono_marshal_type_size (info->fields [i].field->type,
 847                                                                                            info->fields [i].mspec,
 848                                                                                            &align, TRUE, klass->unicode);
 849                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 850                                         /* Unaligned field */
 851                                         NOT_IMPLEMENTED;
 852                                 }
 853
 854                                 /* Skip fields in other quad */
 855                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 856                                         continue;
 857                                 if ((quad == 1) && (info->fields [i].offset < 8))
 858                                         continue;
 859
 860                                 /* How far into this quad this data extends.*/
 861                                 /* (8 is size of quad) */
 862                                 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
 863
 864                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 865                         }
 866                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 867                         args [quad] = class1;
 868                 }
 869         }
 870
 871         /* Post merger cleanup */
 872         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 873                 args [0] = args [1] = ARG_CLASS_MEMORY;
 874
 875         /* Allocate registers */
 876         {
 877                 int orig_gr = *gr;
 878                 int orig_fr = *fr;
 879
 880                 ainfo->storage = ArgValuetypeInReg;
 881                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 882                 ainfo->nregs = nquads;
 883                 for (quad = 0; quad < nquads; ++quad) {
 884                         switch (args [quad]) {
 885                         case ARG_CLASS_INTEGER:
 886                                 if (*gr >= PARAM_REGS)
 887                                         args [quad] = ARG_CLASS_MEMORY;
 888                                 else {
 889                                         ainfo->pair_storage [quad] = ArgInIReg;
 890                                         if (is_return)
 891                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 892                                         else
 893                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 894                                         (*gr) ++;
 895                                 }
 896                                 break;
 897                         case ARG_CLASS_SSE:
 898                                 if (*fr >= FLOAT_PARAM_REGS)
 899                                         args [quad] = ARG_CLASS_MEMORY;
 900                                 else {
 901                                         if (quadsize[quad] <= 4)
 902                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 903                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 904                                         ainfo->pair_regs [quad] = *fr;
 905                                         (*fr) ++;
 906                                 }
 907                                 break;
 908                         case ARG_CLASS_MEMORY:
 909                                 break;
 910                         default:
 911                                 g_assert_not_reached ();
 912                         }
 913                 }
 914
 915                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 916                         /* Revert possible register assignments */
 917                         *gr = orig_gr;
 918                         *fr = orig_fr;
 919
 920                         ainfo->offset = *stack_size;
 921                         if (sig->pinvoke)
 922                                 *stack_size += ALIGN_TO (info->native_size, 8);
 923                         else
 924                                 *stack_size += nquads * sizeof(mgreg_t);
 925                         ainfo->storage = ArgOnStack;
 926                 }
 927         }
 928 }
 929
 930 /*
 931  * get_call_info:
 932  *
 933  *  Obtain information about a call according to the calling convention.
 934  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 935  * Draft Version 0.23" document for more information.
 936  */
 937 static CallInfo*
 938 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 939 {
 940         guint32 i, gr, fr, pstart;
 941         MonoType *ret_type;
 942         int n = sig->hasthis + sig->param_count;
 943         guint32 stack_size = 0;
 944         CallInfo *cinfo;
 945         gboolean is_pinvoke = sig->pinvoke;
 946
 947         if (mp)
 948                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 949         else
 950                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 951
 952         cinfo->nargs = n;
 953
 954         gr = 0;
 955         fr = 0;
 956
 957         /* return value */
 958         {
 959                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 960                 switch (ret_type->type) {
 961                 case MONO_TYPE_BOOLEAN:
 962                 case MONO_TYPE_I1:
 963                 case MONO_TYPE_U1:
 964                 case MONO_TYPE_I2:
 965                 case MONO_TYPE_U2:
 966                 case MONO_TYPE_CHAR:
 967                 case MONO_TYPE_I4:
 968                 case MONO_TYPE_U4:
 969                 case MONO_TYPE_I:
 970                 case MONO_TYPE_U:
 971                 case MONO_TYPE_PTR:
 972                 case MONO_TYPE_FNPTR:
 973                 case MONO_TYPE_CLASS:
 974                 case MONO_TYPE_OBJECT:
 975                 case MONO_TYPE_SZARRAY:
 976                 case MONO_TYPE_ARRAY:
 977                 case MONO_TYPE_STRING:
 978                         cinfo->ret.storage = ArgInIReg;
 979                         cinfo->ret.reg = AMD64_RAX;
 980                         break;
 981                 case MONO_TYPE_U8:
 982                 case MONO_TYPE_I8:
 983                         cinfo->ret.storage = ArgInIReg;
 984                         cinfo->ret.reg = AMD64_RAX;
 985                         break;
 986                 case MONO_TYPE_R4:
 987                         cinfo->ret.storage = ArgInFloatSSEReg;
 988                         cinfo->ret.reg = AMD64_XMM0;
 989                         break;
 990                 case MONO_TYPE_R8:
 991                         cinfo->ret.storage = ArgInDoubleSSEReg;
 992                         cinfo->ret.reg = AMD64_XMM0;
 993                         break;
 994                 case MONO_TYPE_GENERICINST:
 995                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 996                                 cinfo->ret.storage = ArgInIReg;
 997                                 cinfo->ret.reg = AMD64_RAX;
 998                                 break;
 999                         }
1000                         /* fall through */
1001 #if defined( __native_client_codegen__ )
1002                 case MONO_TYPE_TYPEDBYREF:
1003 #endif
1004                 case MONO_TYPE_VALUETYPE: {
1005                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1006
1007                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1008                         if (cinfo->ret.storage == ArgOnStack) {
1009                                 cinfo->vtype_retaddr = TRUE;
1010                                 /* The caller passes the address where the value is stored */
1011                         }
1012                         break;
1013                 }
1014 #if !defined( __native_client_codegen__ )
1015                 case MONO_TYPE_TYPEDBYREF:
1016                         /* Same as a valuetype with size 24 */
1017                         cinfo->vtype_retaddr = TRUE;
1018                         break;
1019 #endif
1020                 case MONO_TYPE_VOID:
1021                         break;
1022                 default:
1023                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1024                 }
1025         }
1026
1027         pstart = 0;
1028         /*
1029          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1030          * the first argument, allowing 'this' to be always passed in the first arg reg.
1031          * Also do this if the first argument is a reference type, since virtual calls
1032          * are sometimes made using calli without sig->hasthis set, like in the delegate
1033          * invoke wrappers.
1034          */
1035         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1036                 if (sig->hasthis) {
1037                         add_general (&gr, &stack_size, cinfo->args + 0);
1038                 } else {
1039                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1040                         pstart = 1;
1041                 }
1042                 add_general (&gr, &stack_size, &cinfo->ret);
1043                 cinfo->vret_arg_index = 1;
1044         } else {
1045                 /* this */
1046                 if (sig->hasthis)
1047                         add_general (&gr, &stack_size, cinfo->args + 0);
1048
1049                 if (cinfo->vtype_retaddr)
1050                         add_general (&gr, &stack_size, &cinfo->ret);
1051         }
1052
1053         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1054                 gr = PARAM_REGS;
1055                 fr = FLOAT_PARAM_REGS;
1056
1057                 /* Emit the signature cookie just before the implicit arguments */
1058                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1059         }
1060
1061         for (i = pstart; i < sig->param_count; ++i) {
1062                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1063                 MonoType *ptype;
1064
1065 #ifdef HOST_WIN32
1066                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1067                 if (gr > fr)
1068                         fr = gr;
1069                 else if (fr > gr)
1070                         gr = fr;
1071 #endif
1072
1073                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1074                         /* We allways pass the sig cookie on the stack for simplicity */
1075                         /*
1076                          * Prevent implicit arguments + the sig cookie from being passed
1077                          * in registers.
1078                          */
1079                         gr = PARAM_REGS;
1080                         fr = FLOAT_PARAM_REGS;
1081
1082                         /* Emit the signature cookie just before the implicit arguments */
1083                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1084                 }
1085
1086                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1087                 switch (ptype->type) {
1088                 case MONO_TYPE_BOOLEAN:
1089                 case MONO_TYPE_I1:
1090                 case MONO_TYPE_U1:
1091                         add_general (&gr, &stack_size, ainfo);
1092                         break;
1093                 case MONO_TYPE_I2:
1094                 case MONO_TYPE_U2:
1095                 case MONO_TYPE_CHAR:
1096                         add_general (&gr, &stack_size, ainfo);
1097                         break;
1098                 case MONO_TYPE_I4:
1099                 case MONO_TYPE_U4:
1100                         add_general (&gr, &stack_size, ainfo);
1101                         break;
1102                 case MONO_TYPE_I:
1103                 case MONO_TYPE_U:
1104                 case MONO_TYPE_PTR:
1105                 case MONO_TYPE_FNPTR:
1106                 case MONO_TYPE_CLASS:
1107                 case MONO_TYPE_OBJECT:
1108                 case MONO_TYPE_STRING:
1109                 case MONO_TYPE_SZARRAY:
1110                 case MONO_TYPE_ARRAY:
1111                         add_general (&gr, &stack_size, ainfo);
1112                         break;
1113                 case MONO_TYPE_GENERICINST:
1114                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1115                                 add_general (&gr, &stack_size, ainfo);
1116                                 break;
1117                         }
1118                         /* fall through */
1119                 case MONO_TYPE_VALUETYPE:
1120                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1121                         break;
1122                 case MONO_TYPE_TYPEDBYREF:
1123 #if defined( HOST_WIN32 ) || defined( __native_client_codegen__ )
1124                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1125 #else
1126                         stack_size += sizeof (MonoTypedRef);
1127                         ainfo->storage = ArgOnStack;
1128 #endif
1129                         break;
1130                 case MONO_TYPE_U8:
1131                 case MONO_TYPE_I8:
1132                         add_general (&gr, &stack_size, ainfo);
1133                         break;
1134                 case MONO_TYPE_R4:
1135                         add_float (&fr, &stack_size, ainfo, FALSE);
1136                         break;
1137                 case MONO_TYPE_R8:
1138                         add_float (&fr, &stack_size, ainfo, TRUE);
1139                         break;
1140                 default:
1141                         g_assert_not_reached ();
1142                 }
1143         }
1144
1145         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1146                 gr = PARAM_REGS;
1147                 fr = FLOAT_PARAM_REGS;
1148
1149                 /* Emit the signature cookie just before the implicit arguments */
1150                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1151         }
1152
1153 #ifdef HOST_WIN32
1154         // There always is 32 bytes reserved on the stack when calling on Winx64
1155         stack_size += 0x20;
1156 #endif
1157
1158 #ifndef MONO_AMD64_NO_PUSHES
1159         if (stack_size & 0x8) {
1160                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1161                 cinfo->need_stack_align = TRUE;
1162                 stack_size += 8;
1163         }
1164 #endif
1165
1166         cinfo->stack_usage = stack_size;
1167         cinfo->reg_usage = gr;
1168         cinfo->freg_usage = fr;
1169         return cinfo;
1170 }
1171
1172 /*
1173  * mono_arch_get_argument_info:
1174  * @csig:  a method signature
1175  * @param_count: the number of parameters to consider
1176  * @arg_info: an array to store the result infos
1177  *
1178  * Gathers information on parameters such as size, alignment and
1179  * padding. arg_info should be large enought to hold param_count + 1 entries.
1180  *
1181  * Returns the size of the argument area on the stack.
1182  */
1183 int
1184 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1185 {
1186         int k;
1187         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1188         guint32 args_size = cinfo->stack_usage;
1189
1190         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1191         if (csig->hasthis) {
1192                 arg_info [0].offset = 0;
1193         }
1194
1195         for (k = 0; k < param_count; k++) {
1196                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1197                 /* FIXME: */
1198                 arg_info [k + 1].size = 0;
1199         }
1200
1201         g_free (cinfo);
1202
1203         return args_size;
1204 }
1205
1206 gboolean
1207 mono_arch_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1208 {
1209         CallInfo *c1, *c2;
1210         gboolean res;
1211         MonoType *callee_ret;
1212
1213         c1 = get_call_info (NULL, NULL, caller_sig);
1214         c2 = get_call_info (NULL, NULL, callee_sig);
1215         res = c1->stack_usage >= c2->stack_usage;
1216         callee_ret = callee_sig->ret;
1217         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1218                 /* An address on the callee's stack is passed as the first argument */
1219                 res = FALSE;
1220
1221         g_free (c1);
1222         g_free (c2);
1223
1224         return res;
1225 }
1226
1227 /*
1228  * Initialize the cpu to execute managed code.
1229  */
1230 void
1231 mono_arch_cpu_init (void)
1232 {
1233 #ifndef _MSC_VER
1234         guint16 fpcw;
1235
1236         /* spec compliance requires running with double precision */
1237         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1238         fpcw &= ~X86_FPCW_PRECC_MASK;
1239         fpcw |= X86_FPCW_PREC_DOUBLE;
1240         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1241         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1242 #else
1243         /* TODO: This is crashing on Win64 right now.
1244         * _control87 (_PC_53, MCW_PC);
1245         */
1246 #endif
1247 }
1248
1249 /*
1250  * Initialize architecture specific code.
1251  */
1252 void
1253 mono_arch_init (void)
1254 {
1255         int flags;
1256
1257         InitializeCriticalSection (&mini_arch_mutex);
1258 #if defined(__native_client_codegen__)
1259         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1260         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1261         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1262         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1263 #endif
1264
1265 #ifdef MONO_ARCH_NOMAP32BIT
1266         flags = MONO_MMAP_READ;
1267         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1268         breakpoint_size = 13;
1269         breakpoint_fault_size = 3;
1270 #else
1271         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1272         /* amd64_mov_reg_mem () */
1273         breakpoint_size = 8;
1274         breakpoint_fault_size = 8;
1275 #endif
1276
1277         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1278         single_step_fault_size = 4;
1279
1280         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1281         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1282         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1283
1284         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1285         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1286         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1287 }
1288
1289 /*
1290  * Cleanup architecture specific code.
1291  */
1292 void
1293 mono_arch_cleanup (void)
1294 {
1295         DeleteCriticalSection (&mini_arch_mutex);
1296 #if defined(__native_client_codegen__)
1297         mono_native_tls_free (nacl_instruction_depth);
1298         mono_native_tls_free (nacl_rex_tag);
1299         mono_native_tls_free (nacl_legacy_prefix_tag);
1300 #endif
1301 }
1302
1303 /*
1304  * This function returns the optimizations supported on this cpu.
1305  */
1306 guint32
1307 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1308 {
1309         guint32 opts = 0;
1310
1311         *exclude_mask = 0;
1312
1313         if (mono_hwcap_x86_has_cmov) {
1314                 opts |= MONO_OPT_CMOV;
1315
1316                 if (mono_hwcap_x86_has_fcmov)
1317                         opts |= MONO_OPT_FCMOV;
1318                 else
1319                         *exclude_mask |= MONO_OPT_FCMOV;
1320         } else {
1321                 *exclude_mask |= MONO_OPT_CMOV;
1322         }
1323
1324         return opts;
1325 }
1326
1327 /*
1328  * This function test for all SSE functions supported.
1329  *
1330  * Returns a bitmask corresponding to all supported versions.
1331  *
1332  */
1333 guint32
1334 mono_arch_cpu_enumerate_simd_versions (void)
1335 {
1336         guint32 sse_opts = 0;
1337
1338         if (mono_hwcap_x86_has_sse1)
1339                 sse_opts |= SIMD_VERSION_SSE1;
1340
1341         if (mono_hwcap_x86_has_sse2)
1342                 sse_opts |= SIMD_VERSION_SSE2;
1343
1344         if (mono_hwcap_x86_has_sse3)
1345                 sse_opts |= SIMD_VERSION_SSE3;
1346
1347         if (mono_hwcap_x86_has_ssse3)
1348                 sse_opts |= SIMD_VERSION_SSSE3;
1349
1350         if (mono_hwcap_x86_has_sse41)
1351                 sse_opts |= SIMD_VERSION_SSE41;
1352
1353         if (mono_hwcap_x86_has_sse42)
1354                 sse_opts |= SIMD_VERSION_SSE42;
1355
1356         if (mono_hwcap_x86_has_sse4a)
1357                 sse_opts |= SIMD_VERSION_SSE4a;
1358
1359         return sse_opts;
1360 }
1361
1362 #ifndef DISABLE_JIT
1363
1364 GList *
1365 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1366 {
1367         GList *vars = NULL;
1368         int i;
1369
1370         for (i = 0; i < cfg->num_varinfo; i++) {
1371                 MonoInst *ins = cfg->varinfo [i];
1372                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1373
1374                 /* unused vars */
1375                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1376                         continue;
1377
1378                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1379                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1380                         continue;
1381
1382                 if (mono_is_regsize_var (ins->inst_vtype)) {
1383                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1384                         g_assert (i == vmv->idx);
1385                         vars = g_list_prepend (vars, vmv);
1386                 }
1387         }
1388
1389         vars = mono_varlist_sort (cfg, vars, 0);
1390
1391         return vars;
1392 }
1393
1394 /**
1395  * mono_arch_compute_omit_fp:
1396  *
1397  *   Determine whenever the frame pointer can be eliminated.
1398  */
1399 static void
1400 mono_arch_compute_omit_fp (MonoCompile *cfg)
1401 {
1402         MonoMethodSignature *sig;
1403         MonoMethodHeader *header;
1404         int i, locals_size;
1405         CallInfo *cinfo;
1406
1407         if (cfg->arch.omit_fp_computed)
1408                 return;
1409
1410         header = cfg->header;
1411
1412         sig = mono_method_signature (cfg->method);
1413
1414         if (!cfg->arch.cinfo)
1415                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1416         cinfo = cfg->arch.cinfo;
1417
1418         /*
1419          * FIXME: Remove some of the restrictions.
1420          */
1421         cfg->arch.omit_fp = TRUE;
1422         cfg->arch.omit_fp_computed = TRUE;
1423
1424 #ifdef __native_client_codegen__
1425         /* NaCl modules may not change the value of RBP, so it cannot be */
1426         /* used as a normal register, but it can be used as a frame pointer*/
1427         cfg->disable_omit_fp = TRUE;
1428         cfg->arch.omit_fp = FALSE;
1429 #endif
1430
1431         if (cfg->disable_omit_fp)
1432                 cfg->arch.omit_fp = FALSE;
1433
1434         if (!debug_omit_fp ())
1435                 cfg->arch.omit_fp = FALSE;
1436         /*
1437         if (cfg->method->save_lmf)
1438                 cfg->arch.omit_fp = FALSE;
1439         */
1440         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1441                 cfg->arch.omit_fp = FALSE;
1442         if (header->num_clauses)
1443                 cfg->arch.omit_fp = FALSE;
1444         if (cfg->param_area)
1445                 cfg->arch.omit_fp = FALSE;
1446         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1447                 cfg->arch.omit_fp = FALSE;
1448         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1449                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1450                 cfg->arch.omit_fp = FALSE;
1451         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1452                 ArgInfo *ainfo = &cinfo->args [i];
1453
1454                 if (ainfo->storage == ArgOnStack) {
1455                         /*
1456                          * The stack offset can only be determined when the frame
1457                          * size is known.
1458                          */
1459                         cfg->arch.omit_fp = FALSE;
1460                 }
1461         }
1462
1463         locals_size = 0;
1464         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1465                 MonoInst *ins = cfg->varinfo [i];
1466                 int ialign;
1467
1468                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1469         }
1470 }
1471
1472 GList *
1473 mono_arch_get_global_int_regs (MonoCompile *cfg)
1474 {
1475         GList *regs = NULL;
1476
1477         mono_arch_compute_omit_fp (cfg);
1478
1479         if (cfg->globalra) {
1480                 if (cfg->arch.omit_fp)
1481                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1482
1483                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1484                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1485                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1486                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1487 #ifndef __native_client_codegen__
1488                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1489 #endif
1490
1491                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1492                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1493                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1494                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1495                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1496                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1497                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1498                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1499         } else {
1500                 if (cfg->arch.omit_fp)
1501                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1502
1503                 /* We use the callee saved registers for global allocation */
1504                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1505                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1506                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1507                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1508 #ifndef __native_client_codegen__
1509                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1510 #endif
1511 #ifdef HOST_WIN32
1512                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1513                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1514 #endif
1515         }
1516
1517         return regs;
1518 }
1519
1520 GList*
1521 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1522 {
1523         GList *regs = NULL;
1524         int i;
1525
1526         /* All XMM registers */
1527         for (i = 0; i < 16; ++i)
1528                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1529
1530         return regs;
1531 }
1532
1533 GList*
1534 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1535 {
1536         static GList *r = NULL;
1537
1538         if (r == NULL) {
1539                 GList *regs = NULL;
1540
1541                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1542                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1543                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1544                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1545                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1546 #ifndef __native_client_codegen__
1547                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1548 #endif
1549
1550                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1551                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1552                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1553                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1554                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1555                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1556                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1557                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1558
1559                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1560         }
1561
1562         return r;
1563 }
1564
1565 GList*
1566 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1567 {
1568         int i;
1569         static GList *r = NULL;
1570
1571         if (r == NULL) {
1572                 GList *regs = NULL;
1573
1574                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1575                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1576
1577                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1578         }
1579
1580         return r;
1581 }
1582
1583 /*
1584  * mono_arch_regalloc_cost:
1585  *
1586  *  Return the cost, in number of memory references, of the action of
1587  * allocating the variable VMV into a register during global register
1588  * allocation.
1589  */
1590 guint32
1591 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1592 {
1593         MonoInst *ins = cfg->varinfo [vmv->idx];
1594
1595         if (cfg->method->save_lmf)
1596                 /* The register is already saved */
1597                 /* substract 1 for the invisible store in the prolog */
1598                 return (ins->opcode == OP_ARG) ? 0 : 1;
1599         else
1600                 /* push+pop */
1601                 return (ins->opcode == OP_ARG) ? 1 : 2;
1602 }
1603
1604 /*
1605  * mono_arch_fill_argument_info:
1606  *
1607  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1608  * of the method.
1609  */
1610 void
1611 mono_arch_fill_argument_info (MonoCompile *cfg)
1612 {
1613         MonoType *sig_ret;
1614         MonoMethodSignature *sig;
1615         MonoMethodHeader *header;
1616         MonoInst *ins;
1617         int i;
1618         CallInfo *cinfo;
1619
1620         header = cfg->header;
1621
1622         sig = mono_method_signature (cfg->method);
1623
1624         cinfo = cfg->arch.cinfo;
1625         sig_ret = sig->ret;
1626         /*
1627          * Contrary to mono_arch_allocate_vars (), the information should describe
1628          * where the arguments are at the beginning of the method, not where they can be
1629          * accessed during the execution of the method. The later makes no sense for the
1630          * global register allocator, since a variable can be in more than one location.
1631          */
1632         if (sig_ret->type != MONO_TYPE_VOID) {
1633                 switch (cinfo->ret.storage) {
1634                 case ArgInIReg:
1635                 case ArgInFloatSSEReg:
1636                 case ArgInDoubleSSEReg:
1637                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1638                                 cfg->vret_addr->opcode = OP_REGVAR;
1639                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1640                         }
1641                         else {
1642                                 cfg->ret->opcode = OP_REGVAR;
1643                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1644                         }
1645                         break;
1646                 case ArgValuetypeInReg:
1647                         cfg->ret->opcode = OP_REGOFFSET;
1648                         cfg->ret->inst_basereg = -1;
1649                         cfg->ret->inst_offset = -1;
1650                         break;
1651                 default:
1652                         g_assert_not_reached ();
1653                 }
1654         }
1655
1656         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1657                 ArgInfo *ainfo = &cinfo->args [i];
1658                 MonoType *arg_type;
1659
1660                 ins = cfg->args [i];
1661
1662                 if (sig->hasthis && (i == 0))
1663                         arg_type = &mono_defaults.object_class->byval_arg;
1664                 else
1665                         arg_type = sig->params [i - sig->hasthis];
1666
1667                 switch (ainfo->storage) {
1668                 case ArgInIReg:
1669                 case ArgInFloatSSEReg:
1670                 case ArgInDoubleSSEReg:
1671                         ins->opcode = OP_REGVAR;
1672                         ins->inst_c0 = ainfo->reg;
1673                         break;
1674                 case ArgOnStack:
1675                         ins->opcode = OP_REGOFFSET;
1676                         ins->inst_basereg = -1;
1677                         ins->inst_offset = -1;
1678                         break;
1679                 case ArgValuetypeInReg:
1680                         /* Dummy */
1681                         ins->opcode = OP_NOP;
1682                         break;
1683                 default:
1684                         g_assert_not_reached ();
1685                 }
1686         }
1687 }
1688
1689 void
1690 mono_arch_allocate_vars (MonoCompile *cfg)
1691 {
1692         MonoType *sig_ret;
1693         MonoMethodSignature *sig;
1694         MonoMethodHeader *header;
1695         MonoInst *ins;
1696         int i, offset;
1697         guint32 locals_stack_size, locals_stack_align;
1698         gint32 *offsets;
1699         CallInfo *cinfo;
1700
1701         header = cfg->header;
1702
1703         sig = mono_method_signature (cfg->method);
1704
1705         cinfo = cfg->arch.cinfo;
1706         sig_ret = sig->ret;
1707
1708         mono_arch_compute_omit_fp (cfg);
1709
1710         /*
1711          * We use the ABI calling conventions for managed code as well.
1712          * Exception: valuetypes are only sometimes passed or returned in registers.
1713          */
1714
1715         /*
1716          * The stack looks like this:
1717          * <incoming arguments passed on the stack>
1718          * <return value>
1719          * <lmf/caller saved registers>
1720          * <locals>
1721          * <spill area>
1722          * <localloc area>  -> grows dynamically
1723          * <params area>
1724          */
1725
1726         if (cfg->arch.omit_fp) {
1727                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1728                 cfg->frame_reg = AMD64_RSP;
1729                 offset = 0;
1730         } else {
1731                 /* Locals are allocated backwards from %fp */
1732                 cfg->frame_reg = AMD64_RBP;
1733                 offset = 0;
1734         }
1735
1736         if (cfg->method->save_lmf) {
1737                 /* The LMF var is allocated normally */
1738         } else {
1739                 if (cfg->arch.omit_fp)
1740                         cfg->arch.reg_save_area_offset = offset;
1741                 /* Reserve space for callee saved registers */
1742                 for (i = 0; i < AMD64_NREG; ++i)
1743                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1744                                 offset += sizeof(mgreg_t);
1745                         }
1746                 if (!cfg->arch.omit_fp)
1747                         cfg->arch.reg_save_area_offset = -offset;
1748         }
1749
1750         if (sig_ret->type != MONO_TYPE_VOID) {
1751                 switch (cinfo->ret.storage) {
1752                 case ArgInIReg:
1753                 case ArgInFloatSSEReg:
1754                 case ArgInDoubleSSEReg:
1755                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1756                                 if (cfg->globalra) {
1757                                         cfg->vret_addr->opcode = OP_REGVAR;
1758                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1759                                 } else {
1760                                         /* The register is volatile */
1761                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1762                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1763                                         if (cfg->arch.omit_fp) {
1764                                                 cfg->vret_addr->inst_offset = offset;
1765                                                 offset += 8;
1766                                         } else {
1767                                                 offset += 8;
1768                                                 cfg->vret_addr->inst_offset = -offset;
1769                                         }
1770                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1771                                                 printf ("vret_addr =");
1772                                                 mono_print_ins (cfg->vret_addr);
1773                                         }
1774                                 }
1775                         }
1776                         else {
1777                                 cfg->ret->opcode = OP_REGVAR;
1778                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1779                         }
1780                         break;
1781                 case ArgValuetypeInReg:
1782                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1783                         cfg->ret->opcode = OP_REGOFFSET;
1784                         cfg->ret->inst_basereg = cfg->frame_reg;
1785                         if (cfg->arch.omit_fp) {
1786                                 cfg->ret->inst_offset = offset;
1787                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1788                         } else {
1789                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1790                                 cfg->ret->inst_offset = - offset;
1791                         }
1792                         break;
1793                 default:
1794                         g_assert_not_reached ();
1795                 }
1796                 if (!cfg->globalra)
1797                         cfg->ret->dreg = cfg->ret->inst_c0;
1798         }
1799
1800         /* Allocate locals */
1801         if (!cfg->globalra) {
1802                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1803                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1804                         char *mname = mono_method_full_name (cfg->method, TRUE);
1805                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1806                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1807                         g_free (mname);
1808                         return;
1809                 }
1810
1811                 if (locals_stack_align) {
1812                         offset += (locals_stack_align - 1);
1813                         offset &= ~(locals_stack_align - 1);
1814                 }
1815                 if (cfg->arch.omit_fp) {
1816                         cfg->locals_min_stack_offset = offset;
1817                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1818                 } else {
1819                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1820                         cfg->locals_max_stack_offset = - offset;
1821                 }
1822
1823                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1824                         if (offsets [i] != -1) {
1825                                 MonoInst *ins = cfg->varinfo [i];
1826                                 ins->opcode = OP_REGOFFSET;
1827                                 ins->inst_basereg = cfg->frame_reg;
1828                                 if (cfg->arch.omit_fp)
1829                                         ins->inst_offset = (offset + offsets [i]);
1830                                 else
1831                                         ins->inst_offset = - (offset + offsets [i]);
1832                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1833                         }
1834                 }
1835                 offset += locals_stack_size;
1836         }
1837
1838         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1839                 g_assert (!cfg->arch.omit_fp);
1840                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1841                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1842         }
1843
1844         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1845                 ins = cfg->args [i];
1846                 if (ins->opcode != OP_REGVAR) {
1847                         ArgInfo *ainfo = &cinfo->args [i];
1848                         gboolean inreg = TRUE;
1849                         MonoType *arg_type;
1850
1851                         if (sig->hasthis && (i == 0))
1852                                 arg_type = &mono_defaults.object_class->byval_arg;
1853                         else
1854                                 arg_type = sig->params [i - sig->hasthis];
1855
1856                         if (cfg->globalra) {
1857                                 /* The new allocator needs info about the original locations of the arguments */
1858                                 switch (ainfo->storage) {
1859                                 case ArgInIReg:
1860                                 case ArgInFloatSSEReg:
1861                                 case ArgInDoubleSSEReg:
1862                                         ins->opcode = OP_REGVAR;
1863                                         ins->inst_c0 = ainfo->reg;
1864                                         break;
1865                                 case ArgOnStack:
1866                                         g_assert (!cfg->arch.omit_fp);
1867                                         ins->opcode = OP_REGOFFSET;
1868                                         ins->inst_basereg = cfg->frame_reg;
1869                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1870                                         break;
1871                                 case ArgValuetypeInReg:
1872                                         ins->opcode = OP_REGOFFSET;
1873                                         ins->inst_basereg = cfg->frame_reg;
1874                                         /* These arguments are saved to the stack in the prolog */
1875                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1876                                         if (cfg->arch.omit_fp) {
1877                                                 ins->inst_offset = offset;
1878                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1879                                         } else {
1880                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1881                                                 ins->inst_offset = - offset;
1882                                         }
1883                                         break;
1884                                 default:
1885                                         g_assert_not_reached ();
1886                                 }
1887
1888                                 continue;
1889                         }
1890
1891                         /* FIXME: Allocate volatile arguments to registers */
1892                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1893                                 inreg = FALSE;
1894
1895                         /*
1896                          * Under AMD64, all registers used to pass arguments to functions
1897                          * are volatile across calls.
1898                          * FIXME: Optimize this.
1899                          */
1900                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1901                                 inreg = FALSE;
1902
1903                         ins->opcode = OP_REGOFFSET;
1904
1905                         switch (ainfo->storage) {
1906                         case ArgInIReg:
1907                         case ArgInFloatSSEReg:
1908                         case ArgInDoubleSSEReg:
1909                                 if (inreg) {
1910                                         ins->opcode = OP_REGVAR;
1911                                         ins->dreg = ainfo->reg;
1912                                 }
1913                                 break;
1914                         case ArgOnStack:
1915                                 g_assert (!cfg->arch.omit_fp);
1916                                 ins->opcode = OP_REGOFFSET;
1917                                 ins->inst_basereg = cfg->frame_reg;
1918                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1919                                 break;
1920                         case ArgValuetypeInReg:
1921                                 break;
1922                         case ArgValuetypeAddrInIReg: {
1923                                 MonoInst *indir;
1924                                 g_assert (!cfg->arch.omit_fp);
1925
1926                                 MONO_INST_NEW (cfg, indir, 0);
1927                                 indir->opcode = OP_REGOFFSET;
1928                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1929                                         indir->inst_basereg = cfg->frame_reg;
1930                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1931                                         offset += (sizeof (gpointer));
1932                                         indir->inst_offset = - offset;
1933                                 }
1934                                 else {
1935                                         indir->inst_basereg = cfg->frame_reg;
1936                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1937                                 }
1938
1939                                 ins->opcode = OP_VTARG_ADDR;
1940                                 ins->inst_left = indir;
1941
1942                                 break;
1943                         }
1944                         default:
1945                                 NOT_IMPLEMENTED;
1946                         }
1947
1948                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1949                                 ins->opcode = OP_REGOFFSET;
1950                                 ins->inst_basereg = cfg->frame_reg;
1951                                 /* These arguments are saved to the stack in the prolog */
1952                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1953                                 if (cfg->arch.omit_fp) {
1954                                         ins->inst_offset = offset;
1955                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1956                                         // Arguments are yet supported by the stack map creation code
1957                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1958                                 } else {
1959                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1960                                         ins->inst_offset = - offset;
1961                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1962                                 }
1963                         }
1964                 }
1965         }
1966
1967         cfg->stack_offset = offset;
1968 }
1969
1970 void
1971 mono_arch_create_vars (MonoCompile *cfg)
1972 {
1973         MonoMethodSignature *sig;
1974         CallInfo *cinfo;
1975
1976         sig = mono_method_signature (cfg->method);
1977
1978         if (!cfg->arch.cinfo)
1979                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1980         cinfo = cfg->arch.cinfo;
1981
1982         if (cinfo->ret.storage == ArgValuetypeInReg)
1983                 cfg->ret_var_is_local = TRUE;
1984
1985         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1986                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1987                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1988                         printf ("vret_addr = ");
1989                         mono_print_ins (cfg->vret_addr);
1990                 }
1991         }
1992
1993         if (cfg->gen_seq_points) {
1994                 MonoInst *ins;
1995
1996                 if (cfg->compile_aot) {
1997                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1998                         ins->flags |= MONO_INST_VOLATILE;
1999                         cfg->arch.seq_point_info_var = ins;
2000                 }
2001
2002             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2003                 ins->flags |= MONO_INST_VOLATILE;
2004                 cfg->arch.ss_trigger_page_var = ins;
2005         }
2006
2007 #ifdef MONO_AMD64_NO_PUSHES
2008         /*
2009          * When this is set, we pass arguments on the stack by moves, and by allocating
2010          * a bigger stack frame, instead of pushes.
2011          * Pushes complicate exception handling because the arguments on the stack have
2012          * to be popped each time a frame is unwound. They also make fp elimination
2013          * impossible.
2014          * FIXME: This doesn't work inside filter/finally clauses, since those execute
2015          * on a new frame which doesn't include a param area.
2016          */
2017         cfg->arch.no_pushes = TRUE;
2018 #endif
2019
2020         if (cfg->method->save_lmf)
2021                 cfg->create_lmf_var = TRUE;
2022
2023 #if !defined(HOST_WIN32)
2024         if (cfg->method->save_lmf) {
2025                 cfg->lmf_ir = TRUE;
2026                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2027                         cfg->lmf_ir_mono_lmf = TRUE;
2028         }
2029 #endif
2030
2031 #ifndef MONO_AMD64_NO_PUSHES
2032         cfg->arch_eh_jit_info = 1;
2033 #endif
2034 }
2035
2036 static void
2037 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2038 {
2039         MonoInst *ins;
2040
2041         switch (storage) {
2042         case ArgInIReg:
2043                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2044                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2045                 ins->sreg1 = tree->dreg;
2046                 MONO_ADD_INS (cfg->cbb, ins);
2047                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2048                 break;
2049         case ArgInFloatSSEReg:
2050                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2051                 ins->dreg = mono_alloc_freg (cfg);
2052                 ins->sreg1 = tree->dreg;
2053                 MONO_ADD_INS (cfg->cbb, ins);
2054
2055                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2056                 break;
2057         case ArgInDoubleSSEReg:
2058                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2059                 ins->dreg = mono_alloc_freg (cfg);
2060                 ins->sreg1 = tree->dreg;
2061                 MONO_ADD_INS (cfg->cbb, ins);
2062
2063                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2064
2065                 break;
2066         default:
2067                 g_assert_not_reached ();
2068         }
2069 }
2070
2071 static int
2072 arg_storage_to_load_membase (ArgStorage storage)
2073 {
2074         switch (storage) {
2075         case ArgInIReg:
2076 #if defined(__mono_ilp32__)
2077                 return OP_LOADI8_MEMBASE;
2078 #else
2079                 return OP_LOAD_MEMBASE;
2080 #endif
2081         case ArgInDoubleSSEReg:
2082                 return OP_LOADR8_MEMBASE;
2083         case ArgInFloatSSEReg:
2084                 return OP_LOADR4_MEMBASE;
2085         default:
2086                 g_assert_not_reached ();
2087         }
2088
2089         return -1;
2090 }
2091
2092 static void
2093 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2094 {
2095         MonoInst *arg;
2096         MonoMethodSignature *tmp_sig;
2097         int sig_reg;
2098
2099         if (call->tail_call)
2100                 NOT_IMPLEMENTED;
2101
2102         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2103
2104         /*
2105          * mono_ArgIterator_Setup assumes the signature cookie is
2106          * passed first and all the arguments which were before it are
2107          * passed on the stack after the signature. So compensate by
2108          * passing a different signature.
2109          */
2110         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2111         tmp_sig->param_count -= call->signature->sentinelpos;
2112         tmp_sig->sentinelpos = 0;
2113         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2114
2115         sig_reg = mono_alloc_ireg (cfg);
2116         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2117
2118         if (cfg->arch.no_pushes) {
2119                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2120         } else {
2121                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2122                 arg->sreg1 = sig_reg;
2123                 MONO_ADD_INS (cfg->cbb, arg);
2124         }
2125 }
2126
2127 static inline LLVMArgStorage
2128 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2129 {
2130         switch (storage) {
2131         case ArgInIReg:
2132                 return LLVMArgInIReg;
2133         case ArgNone:
2134                 return LLVMArgNone;
2135         default:
2136                 g_assert_not_reached ();
2137                 return LLVMArgNone;
2138         }
2139 }
2140
2141 #ifdef ENABLE_LLVM
2142 LLVMCallInfo*
2143 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2144 {
2145         int i, n;
2146         CallInfo *cinfo;
2147         ArgInfo *ainfo;
2148         int j;
2149         LLVMCallInfo *linfo;
2150         MonoType *t, *sig_ret;
2151
2152         n = sig->param_count + sig->hasthis;
2153         sig_ret = sig->ret;
2154         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2155
2156         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2157
2158         /*
2159          * LLVM always uses the native ABI while we use our own ABI, the
2160          * only difference is the handling of vtypes:
2161          * - we only pass/receive them in registers in some cases, and only
2162          *   in 1 or 2 integer registers.
2163          */
2164         if (cinfo->ret.storage == ArgValuetypeInReg) {
2165                 if (sig->pinvoke) {
2166                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2167                         cfg->disable_llvm = TRUE;
2168                         return linfo;
2169                 }
2170
2171                 linfo->ret.storage = LLVMArgVtypeInReg;
2172                 for (j = 0; j < 2; ++j)
2173                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2174         }
2175
2176         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2177                 /* Vtype returned using a hidden argument */
2178                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2179                 linfo->vret_arg_index = cinfo->vret_arg_index;
2180         }
2181
2182         for (i = 0; i < n; ++i) {
2183                 ainfo = cinfo->args + i;
2184
2185                 if (i >= sig->hasthis)
2186                         t = sig->params [i - sig->hasthis];
2187                 else
2188                         t = &mono_defaults.int_class->byval_arg;
2189
2190                 linfo->args [i].storage = LLVMArgNone;
2191
2192                 switch (ainfo->storage) {
2193                 case ArgInIReg:
2194                         linfo->args [i].storage = LLVMArgInIReg;
2195                         break;
2196                 case ArgInDoubleSSEReg:
2197                 case ArgInFloatSSEReg:
2198                         linfo->args [i].storage = LLVMArgInFPReg;
2199                         break;
2200                 case ArgOnStack:
2201                         if (MONO_TYPE_ISSTRUCT (t)) {
2202                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2203                         } else {
2204                                 linfo->args [i].storage = LLVMArgInIReg;
2205                                 if (!t->byref) {
2206                                         if (t->type == MONO_TYPE_R4)
2207                                                 linfo->args [i].storage = LLVMArgInFPReg;
2208                                         else if (t->type == MONO_TYPE_R8)
2209                                                 linfo->args [i].storage = LLVMArgInFPReg;
2210                                 }
2211                         }
2212                         break;
2213                 case ArgValuetypeInReg:
2214                         if (sig->pinvoke) {
2215                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2216                                 cfg->disable_llvm = TRUE;
2217                                 return linfo;
2218                         }
2219
2220                         linfo->args [i].storage = LLVMArgVtypeInReg;
2221                         for (j = 0; j < 2; ++j)
2222                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2223                         break;
2224                 default:
2225                         cfg->exception_message = g_strdup ("ainfo->storage");
2226                         cfg->disable_llvm = TRUE;
2227                         break;
2228                 }
2229         }
2230
2231         return linfo;
2232 }
2233 #endif
2234
2235 void
2236 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2237 {
2238         MonoInst *arg, *in;
2239         MonoMethodSignature *sig;
2240         MonoType *sig_ret;
2241         int i, n, stack_size;
2242         CallInfo *cinfo;
2243         ArgInfo *ainfo;
2244
2245         stack_size = 0;
2246
2247         sig = call->signature;
2248         n = sig->param_count + sig->hasthis;
2249
2250         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2251
2252         sig_ret = sig->ret;
2253
2254         if (COMPILE_LLVM (cfg)) {
2255                 /* We shouldn't be called in the llvm case */
2256                 cfg->disable_llvm = TRUE;
2257                 return;
2258         }
2259
2260         if (cinfo->need_stack_align) {
2261                 if (!cfg->arch.no_pushes)
2262                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2263         }
2264
2265         /*
2266          * Emit all arguments which are passed on the stack to prevent register
2267          * allocation problems.
2268          */
2269         if (cfg->arch.no_pushes) {
2270                 for (i = 0; i < n; ++i) {
2271                         MonoType *t;
2272                         ainfo = cinfo->args + i;
2273
2274                         in = call->args [i];
2275
2276                         if (sig->hasthis && i == 0)
2277                                 t = &mono_defaults.object_class->byval_arg;
2278                         else
2279                                 t = sig->params [i - sig->hasthis];
2280
2281                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2282                                 if (!t->byref) {
2283                                         if (t->type == MONO_TYPE_R4)
2284                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2285                                         else if (t->type == MONO_TYPE_R8)
2286                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2287                                         else
2288                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2289                                 } else {
2290                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2291                                 }
2292                                 if (cfg->compute_gc_maps) {
2293                                         MonoInst *def;
2294
2295                                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2296                                 }
2297                         }
2298                 }
2299         }
2300
2301         /*
2302          * Emit all parameters passed in registers in non-reverse order for better readability
2303          * and to help the optimization in emit_prolog ().
2304          */
2305         for (i = 0; i < n; ++i) {
2306                 ainfo = cinfo->args + i;
2307
2308                 in = call->args [i];
2309
2310                 if (ainfo->storage == ArgInIReg)
2311                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2312         }
2313
2314         for (i = n - 1; i >= 0; --i) {
2315                 ainfo = cinfo->args + i;
2316
2317                 in = call->args [i];
2318
2319                 switch (ainfo->storage) {
2320                 case ArgInIReg:
2321                         /* Already done */
2322                         break;
2323                 case ArgInFloatSSEReg:
2324                 case ArgInDoubleSSEReg:
2325                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2326                         break;
2327                 case ArgOnStack:
2328                 case ArgValuetypeInReg:
2329                 case ArgValuetypeAddrInIReg:
2330                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2331                                 MonoInst *call_inst = (MonoInst*)call;
2332                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2333                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2334                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2335                                 guint32 align;
2336                                 guint32 size;
2337
2338                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2339                                         size = sizeof (MonoTypedRef);
2340                                         align = sizeof (gpointer);
2341                                 }
2342                                 else {
2343                                         if (sig->pinvoke)
2344                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2345                                         else {
2346                                                 /*
2347                                                  * Other backends use mono_type_stack_size (), but that
2348                                                  * aligns the size to 8, which is larger than the size of
2349                                                  * the source, leading to reads of invalid memory if the
2350                                                  * source is at the end of address space.
2351                                                  */
2352                                                 size = mono_class_value_size (in->klass, &align);
2353                                         }
2354                                 }
2355                                 g_assert (in->klass);
2356
2357                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2358                                         /* Avoid asserts in emit_memcpy () */
2359                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2360                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2361                                         /* Continue normally */
2362                                 }
2363
2364                                 if (size > 0) {
2365                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2366                                         arg->sreg1 = in->dreg;
2367                                         arg->klass = in->klass;
2368                                         arg->backend.size = size;
2369                                         arg->inst_p0 = call;
2370                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2371                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2372
2373                                         MONO_ADD_INS (cfg->cbb, arg);
2374                                 }
2375                         } else {
2376                                 if (cfg->arch.no_pushes) {
2377                                         /* Already done */
2378                                 } else {
2379                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2380                                         arg->sreg1 = in->dreg;
2381                                         if (!sig->params [i - sig->hasthis]->byref) {
2382                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2383                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2384                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2385                                                         arg->inst_destbasereg = X86_ESP;
2386                                                         arg->inst_offset = 0;
2387                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2388                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2389                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2390                                                         arg->inst_destbasereg = X86_ESP;
2391                                                         arg->inst_offset = 0;
2392                                                 }
2393                                         }
2394                                         MONO_ADD_INS (cfg->cbb, arg);
2395                                 }
2396                         }
2397                         break;
2398                 default:
2399                         g_assert_not_reached ();
2400                 }
2401
2402                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2403                         /* Emit the signature cookie just before the implicit arguments */
2404                         emit_sig_cookie (cfg, call, cinfo);
2405         }
2406
2407         /* Handle the case where there are no implicit arguments */
2408         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2409                 emit_sig_cookie (cfg, call, cinfo);
2410
2411         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2412                 MonoInst *vtarg;
2413
2414                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2415                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2416                                 /*
2417                                  * Tell the JIT to use a more efficient calling convention: call using
2418                                  * OP_CALL, compute the result location after the call, and save the
2419                                  * result there.
2420                                  */
2421                                 call->vret_in_reg = TRUE;
2422                                 /*
2423                                  * Nullify the instruction computing the vret addr to enable
2424                                  * future optimizations.
2425                                  */
2426                                 if (call->vret_var)
2427                                         NULLIFY_INS (call->vret_var);
2428                         } else {
2429                                 if (call->tail_call)
2430                                         NOT_IMPLEMENTED;
2431                                 /*
2432                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2433                                  * the stack. Push the address here, so the call instruction can
2434                                  * access it.
2435                                  */
2436                                 if (!cfg->arch.vret_addr_loc) {
2437                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2438                                         /* Prevent it from being register allocated or optimized away */
2439                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2440                                 }
2441
2442                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2443                         }
2444                 }
2445                 else {
2446                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2447                         vtarg->sreg1 = call->vret_var->dreg;
2448                         vtarg->dreg = mono_alloc_preg (cfg);
2449                         MONO_ADD_INS (cfg->cbb, vtarg);
2450
2451                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2452                 }
2453         }
2454
2455 #ifdef HOST_WIN32
2456         if (call->inst.opcode != OP_TAILCALL) {
2457                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2458         }
2459 #endif
2460
2461         if (cfg->method->save_lmf) {
2462                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2463                 MONO_ADD_INS (cfg->cbb, arg);
2464         }
2465
2466         call->stack_usage = cinfo->stack_usage;
2467 }
2468
2469 void
2470 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2471 {
2472         MonoInst *arg;
2473         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2474         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2475         int size = ins->backend.size;
2476
2477         if (ainfo->storage == ArgValuetypeInReg) {
2478                 MonoInst *load;
2479                 int part;
2480
2481                 for (part = 0; part < 2; ++part) {
2482                         if (ainfo->pair_storage [part] == ArgNone)
2483                                 continue;
2484
2485                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2486                         load->inst_basereg = src->dreg;
2487                         load->inst_offset = part * sizeof(mgreg_t);
2488
2489                         switch (ainfo->pair_storage [part]) {
2490                         case ArgInIReg:
2491                                 load->dreg = mono_alloc_ireg (cfg);
2492                                 break;
2493                         case ArgInDoubleSSEReg:
2494                         case ArgInFloatSSEReg:
2495                                 load->dreg = mono_alloc_freg (cfg);
2496                                 break;
2497                         default:
2498                                 g_assert_not_reached ();
2499                         }
2500                         MONO_ADD_INS (cfg->cbb, load);
2501
2502                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2503                 }
2504         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2505                 MonoInst *vtaddr, *load;
2506                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2507
2508                 g_assert (!cfg->arch.no_pushes);
2509
2510                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2511                 cfg->has_indirection = TRUE;
2512                 load->inst_p0 = vtaddr;
2513                 vtaddr->flags |= MONO_INST_INDIRECT;
2514                 load->type = STACK_MP;
2515                 load->klass = vtaddr->klass;
2516                 load->dreg = mono_alloc_ireg (cfg);
2517                 MONO_ADD_INS (cfg->cbb, load);
2518                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2519
2520                 if (ainfo->pair_storage [0] == ArgInIReg) {
2521                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2522                         arg->dreg = mono_alloc_ireg (cfg);
2523                         arg->sreg1 = load->dreg;
2524                         arg->inst_imm = 0;
2525                         MONO_ADD_INS (cfg->cbb, arg);
2526                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2527                 } else {
2528                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2529                         arg->sreg1 = load->dreg;
2530                         MONO_ADD_INS (cfg->cbb, arg);
2531                 }
2532         } else {
2533                 if (size == 8) {
2534                         if (cfg->arch.no_pushes) {
2535                                 int dreg = mono_alloc_ireg (cfg);
2536
2537                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2538                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2539                         } else {
2540                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2541                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2542                                 arg->inst_basereg = src->dreg;
2543                                 arg->inst_offset = 0;
2544                                 MONO_ADD_INS (cfg->cbb, arg);
2545                         }
2546                 } else if (size <= 40) {
2547                         if (cfg->arch.no_pushes) {
2548                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2549                         } else {
2550                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2551                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2552                         }
2553                 } else {
2554                         if (cfg->arch.no_pushes) {
2555                                 // FIXME: Code growth
2556                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2557                         } else {
2558                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2559                                 arg->inst_basereg = src->dreg;
2560                                 arg->inst_offset = 0;
2561                                 arg->inst_imm = size;
2562                                 MONO_ADD_INS (cfg->cbb, arg);
2563                         }
2564                 }
2565
2566                 if (cfg->compute_gc_maps) {
2567                         MonoInst *def;
2568                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2569                 }
2570         }
2571 }
2572
2573 void
2574 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2575 {
2576         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2577
2578         if (ret->type == MONO_TYPE_R4) {
2579                 if (COMPILE_LLVM (cfg))
2580                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2581                 else
2582                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2583                 return;
2584         } else if (ret->type == MONO_TYPE_R8) {
2585                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2586                 return;
2587         }
2588
2589         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2590 }
2591
2592 #endif /* DISABLE_JIT */
2593
2594 #define EMIT_COND_BRANCH(ins,cond,sign) \
2595         if (ins->inst_true_bb->native_offset) { \
2596                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2597         } else { \
2598                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2599                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2600             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2601                         x86_branch8 (code, cond, 0, sign); \
2602                 else \
2603                         x86_branch32 (code, cond, 0, sign); \
2604 }
2605
2606 typedef struct {
2607         MonoMethodSignature *sig;
2608         CallInfo *cinfo;
2609 } ArchDynCallInfo;
2610
2611 typedef struct {
2612         mgreg_t regs [PARAM_REGS];
2613         mgreg_t res;
2614         guint8 *ret;
2615 } DynCallArgs;
2616
2617 static gboolean
2618 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2619 {
2620         int i;
2621
2622 #ifdef HOST_WIN32
2623         return FALSE;
2624 #endif
2625
2626         switch (cinfo->ret.storage) {
2627         case ArgNone:
2628         case ArgInIReg:
2629                 break;
2630         case ArgValuetypeInReg: {
2631                 ArgInfo *ainfo = &cinfo->ret;
2632
2633                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2634                         return FALSE;
2635                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2636                         return FALSE;
2637                 break;
2638         }
2639         default:
2640                 return FALSE;
2641         }
2642
2643         for (i = 0; i < cinfo->nargs; ++i) {
2644                 ArgInfo *ainfo = &cinfo->args [i];
2645                 switch (ainfo->storage) {
2646                 case ArgInIReg:
2647                         break;
2648                 case ArgValuetypeInReg:
2649                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2650                                 return FALSE;
2651                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2652                                 return FALSE;
2653                         break;
2654                 default:
2655                         return FALSE;
2656                 }
2657         }
2658
2659         return TRUE;
2660 }
2661
2662 /*
2663  * mono_arch_dyn_call_prepare:
2664  *
2665  *   Return a pointer to an arch-specific structure which contains information
2666  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2667  * supported for SIG.
2668  * This function is equivalent to ffi_prep_cif in libffi.
2669  */
2670 MonoDynCallInfo*
2671 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2672 {
2673         ArchDynCallInfo *info;
2674         CallInfo *cinfo;
2675
2676         cinfo = get_call_info (NULL, NULL, sig);
2677
2678         if (!dyn_call_supported (sig, cinfo)) {
2679                 g_free (cinfo);
2680                 return NULL;
2681         }
2682
2683         info = g_new0 (ArchDynCallInfo, 1);
2684         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2685         info->sig = sig;
2686         info->cinfo = cinfo;
2687
2688         return (MonoDynCallInfo*)info;
2689 }
2690
2691 /*
2692  * mono_arch_dyn_call_free:
2693  *
2694  *   Free a MonoDynCallInfo structure.
2695  */
2696 void
2697 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2698 {
2699         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2700
2701         g_free (ainfo->cinfo);
2702         g_free (ainfo);
2703 }
2704
2705 #if !defined(__native_client__)
2706 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2707 #define GREG_TO_PTR(greg) (gpointer)(greg)
2708 #else
2709 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2710 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2711 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2712 #endif
2713
2714 /*
2715  * mono_arch_get_start_dyn_call:
2716  *
2717  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2718  * store the result into BUF.
2719  * ARGS should be an array of pointers pointing to the arguments.
2720  * RET should point to a memory buffer large enought to hold the result of the
2721  * call.
2722  * This function should be as fast as possible, any work which does not depend
2723  * on the actual values of the arguments should be done in
2724  * mono_arch_dyn_call_prepare ().
2725  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2726  * libffi.
2727  */
2728 void
2729 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2730 {
2731         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2732         DynCallArgs *p = (DynCallArgs*)buf;
2733         int arg_index, greg, i, pindex;
2734         MonoMethodSignature *sig = dinfo->sig;
2735
2736         g_assert (buf_len >= sizeof (DynCallArgs));
2737
2738         p->res = 0;
2739         p->ret = ret;
2740
2741         arg_index = 0;
2742         greg = 0;
2743         pindex = 0;
2744
2745         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2746                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2747                 if (!sig->hasthis)
2748                         pindex = 1;
2749         }
2750
2751         if (dinfo->cinfo->vtype_retaddr)
2752                 p->regs [greg ++] = PTR_TO_GREG(ret);
2753
2754         for (i = pindex; i < sig->param_count; i++) {
2755                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2756                 gpointer *arg = args [arg_index ++];
2757
2758                 if (t->byref) {
2759                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2760                         continue;
2761                 }
2762
2763                 switch (t->type) {
2764                 case MONO_TYPE_STRING:
2765                 case MONO_TYPE_CLASS:
2766                 case MONO_TYPE_ARRAY:
2767                 case MONO_TYPE_SZARRAY:
2768                 case MONO_TYPE_OBJECT:
2769                 case MONO_TYPE_PTR:
2770                 case MONO_TYPE_I:
2771                 case MONO_TYPE_U:
2772 #if !defined(__mono_ilp32__)
2773                 case MONO_TYPE_I8:
2774                 case MONO_TYPE_U8:
2775 #endif
2776                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2777                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2778                         break;
2779 #if defined(__mono_ilp32__)
2780                 case MONO_TYPE_I8:
2781                 case MONO_TYPE_U8:
2782                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2783                         p->regs [greg ++] = *(guint64*)(arg);
2784                         break;
2785 #endif
2786                 case MONO_TYPE_BOOLEAN:
2787                 case MONO_TYPE_U1:
2788                         p->regs [greg ++] = *(guint8*)(arg);
2789                         break;
2790                 case MONO_TYPE_I1:
2791                         p->regs [greg ++] = *(gint8*)(arg);
2792                         break;
2793                 case MONO_TYPE_I2:
2794                         p->regs [greg ++] = *(gint16*)(arg);
2795                         break;
2796                 case MONO_TYPE_U2:
2797                 case MONO_TYPE_CHAR:
2798                         p->regs [greg ++] = *(guint16*)(arg);
2799                         break;
2800                 case MONO_TYPE_I4:
2801                         p->regs [greg ++] = *(gint32*)(arg);
2802                         break;
2803                 case MONO_TYPE_U4:
2804                         p->regs [greg ++] = *(guint32*)(arg);
2805                         break;
2806                 case MONO_TYPE_GENERICINST:
2807                     if (MONO_TYPE_IS_REFERENCE (t)) {
2808                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2809                                 break;
2810                         } else {
2811                                 /* Fall through */
2812                         }
2813                 case MONO_TYPE_VALUETYPE: {
2814                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2815
2816                         g_assert (ainfo->storage == ArgValuetypeInReg);
2817                         if (ainfo->pair_storage [0] != ArgNone) {
2818                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2819                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2820                         }
2821                         if (ainfo->pair_storage [1] != ArgNone) {
2822                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2823                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2824                         }
2825                         break;
2826                 }
2827                 default:
2828                         g_assert_not_reached ();
2829                 }
2830         }
2831
2832         g_assert (greg <= PARAM_REGS);
2833 }
2834
2835 /*
2836  * mono_arch_finish_dyn_call:
2837  *
2838  *   Store the result of a dyn call into the return value buffer passed to
2839  * start_dyn_call ().
2840  * This function should be as fast as possible, any work which does not depend
2841  * on the actual values of the arguments should be done in
2842  * mono_arch_dyn_call_prepare ().
2843  */
2844 void
2845 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2846 {
2847         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2848         MonoMethodSignature *sig = dinfo->sig;
2849         guint8 *ret = ((DynCallArgs*)buf)->ret;
2850         mgreg_t res = ((DynCallArgs*)buf)->res;
2851         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2852
2853         switch (sig_ret->type) {
2854         case MONO_TYPE_VOID:
2855                 *(gpointer*)ret = NULL;
2856                 break;
2857         case MONO_TYPE_STRING:
2858         case MONO_TYPE_CLASS:
2859         case MONO_TYPE_ARRAY:
2860         case MONO_TYPE_SZARRAY:
2861         case MONO_TYPE_OBJECT:
2862         case MONO_TYPE_I:
2863         case MONO_TYPE_U:
2864         case MONO_TYPE_PTR:
2865                 *(gpointer*)ret = GREG_TO_PTR(res);
2866                 break;
2867         case MONO_TYPE_I1:
2868                 *(gint8*)ret = res;
2869                 break;
2870         case MONO_TYPE_U1:
2871         case MONO_TYPE_BOOLEAN:
2872                 *(guint8*)ret = res;
2873                 break;
2874         case MONO_TYPE_I2:
2875                 *(gint16*)ret = res;
2876                 break;
2877         case MONO_TYPE_U2:
2878         case MONO_TYPE_CHAR:
2879                 *(guint16*)ret = res;
2880                 break;
2881         case MONO_TYPE_I4:
2882                 *(gint32*)ret = res;
2883                 break;
2884         case MONO_TYPE_U4:
2885                 *(guint32*)ret = res;
2886                 break;
2887         case MONO_TYPE_I8:
2888                 *(gint64*)ret = res;
2889                 break;
2890         case MONO_TYPE_U8:
2891                 *(guint64*)ret = res;
2892                 break;
2893         case MONO_TYPE_GENERICINST:
2894                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2895                         *(gpointer*)ret = GREG_TO_PTR(res);
2896                         break;
2897                 } else {
2898                         /* Fall through */
2899                 }
2900         case MONO_TYPE_VALUETYPE:
2901                 if (dinfo->cinfo->vtype_retaddr) {
2902                         /* Nothing to do */
2903                 } else {
2904                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2905
2906                         g_assert (ainfo->storage == ArgValuetypeInReg);
2907
2908                         if (ainfo->pair_storage [0] != ArgNone) {
2909                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2910                                 ((mgreg_t*)ret)[0] = res;
2911                         }
2912
2913                         g_assert (ainfo->pair_storage [1] == ArgNone);
2914                 }
2915                 break;
2916         default:
2917                 g_assert_not_reached ();
2918         }
2919 }
2920
2921 /* emit an exception if condition is fail */
2922 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2923         do {                                                        \
2924                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2925                 if (tins == NULL) {                                                                             \
2926                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2927                                         MONO_PATCH_INFO_EXC, exc_name);  \
2928                         x86_branch32 (code, cond, 0, signed);               \
2929                 } else {        \
2930                         EMIT_COND_BRANCH (tins, cond, signed);  \
2931                 }                       \
2932         } while (0);
2933
2934 #define EMIT_FPCOMPARE(code) do { \
2935         amd64_fcompp (code); \
2936         amd64_fnstsw (code); \
2937 } while (0);
2938
2939 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2940     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2941         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2942         amd64_ ##op (code); \
2943         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2944         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2945 } while (0);
2946
2947 static guint8*
2948 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2949 {
2950         gboolean no_patch = FALSE;
2951
2952         /*
2953          * FIXME: Add support for thunks
2954          */
2955         {
2956                 gboolean near_call = FALSE;
2957
2958                 /*
2959                  * Indirect calls are expensive so try to make a near call if possible.
2960                  * The caller memory is allocated by the code manager so it is
2961                  * guaranteed to be at a 32 bit offset.
2962                  */
2963
2964                 if (patch_type != MONO_PATCH_INFO_ABS) {
2965                         /* The target is in memory allocated using the code manager */
2966                         near_call = TRUE;
2967
2968                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2969                                 if (((MonoMethod*)data)->klass->image->aot_module)
2970                                         /* The callee might be an AOT method */
2971                                         near_call = FALSE;
2972                                 if (((MonoMethod*)data)->dynamic)
2973                                         /* The target is in malloc-ed memory */
2974                                         near_call = FALSE;
2975                         }
2976
2977                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2978                                 /*
2979                                  * The call might go directly to a native function without
2980                                  * the wrapper.
2981                                  */
2982                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2983                                 if (mi) {
2984                                         gconstpointer target = mono_icall_get_wrapper (mi);
2985                                         if ((((guint64)target) >> 32) != 0)
2986                                                 near_call = FALSE;
2987                                 }
2988                         }
2989                 }
2990                 else {
2991                         MonoJumpInfo *jinfo = NULL;
2992
2993                         if (cfg->abs_patches)
2994                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2995                         if (jinfo) {
2996                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2997                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2998                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2999                                                 near_call = TRUE;
3000                                         no_patch = TRUE;
3001                                 } else {
3002                                         /*
3003                                          * This is not really an optimization, but required because the
3004                                          * generic class init trampolines use R11 to pass the vtable.
3005                                          */
3006                                         near_call = TRUE;
3007                                 }
3008                         } else {
3009                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3010                                 if (info) {
3011                                         if (info->func == info->wrapper) {
3012                                                 /* No wrapper */
3013                                                 if ((((guint64)info->func) >> 32) == 0)
3014                                                         near_call = TRUE;
3015                                         }
3016                                         else {
3017                                                 /* See the comment in mono_codegen () */
3018                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3019                                                         near_call = TRUE;
3020                                         }
3021                                 }
3022                                 else if ((((guint64)data) >> 32) == 0) {
3023                                         near_call = TRUE;
3024                                         no_patch = TRUE;
3025                                 }
3026                         }
3027                 }
3028
3029                 if (cfg->method->dynamic)
3030                         /* These methods are allocated using malloc */
3031                         near_call = FALSE;
3032
3033 #ifdef MONO_ARCH_NOMAP32BIT
3034                 near_call = FALSE;
3035 #endif
3036 #if defined(__native_client__)
3037                 /* Always use near_call == TRUE for Native Client */
3038                 near_call = TRUE;
3039 #endif
3040                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3041                 if (optimize_for_xen)
3042                         near_call = FALSE;
3043
3044                 if (cfg->compile_aot) {
3045                         near_call = TRUE;
3046                         no_patch = TRUE;
3047                 }
3048
3049                 if (near_call) {
3050                         /*
3051                          * Align the call displacement to an address divisible by 4 so it does
3052                          * not span cache lines. This is required for code patching to work on SMP
3053                          * systems.
3054                          */
3055                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3056                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3057                                 amd64_padding (code, pad_size);
3058                         }
3059                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3060                         amd64_call_code (code, 0);
3061                 }
3062                 else {
3063                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3064                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3065                         amd64_call_reg (code, GP_SCRATCH_REG);
3066                 }
3067         }
3068
3069         return code;
3070 }
3071
3072 static inline guint8*
3073 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3074 {
3075 #ifdef HOST_WIN32
3076         if (win64_adjust_stack)
3077                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3078 #endif
3079         code = emit_call_body (cfg, code, patch_type, data);
3080 #ifdef HOST_WIN32
3081         if (win64_adjust_stack)
3082                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3083 #endif
3084
3085         return code;
3086 }
3087
3088 static inline int
3089 store_membase_imm_to_store_membase_reg (int opcode)
3090 {
3091         switch (opcode) {
3092         case OP_STORE_MEMBASE_IMM:
3093                 return OP_STORE_MEMBASE_REG;
3094         case OP_STOREI4_MEMBASE_IMM:
3095                 return OP_STOREI4_MEMBASE_REG;
3096         case OP_STOREI8_MEMBASE_IMM:
3097                 return OP_STOREI8_MEMBASE_REG;
3098         }
3099
3100         return -1;
3101 }
3102
3103 #ifndef DISABLE_JIT
3104
3105 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3106
3107 /*
3108  * mono_arch_peephole_pass_1:
3109  *
3110  *   Perform peephole opts which should/can be performed before local regalloc
3111  */
3112 void
3113 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3114 {
3115         MonoInst *ins, *n;
3116
3117         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3118                 MonoInst *last_ins = ins->prev;
3119
3120                 switch (ins->opcode) {
3121                 case OP_ADD_IMM:
3122                 case OP_IADD_IMM:
3123                 case OP_LADD_IMM:
3124                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3125                                 /*
3126                                  * X86_LEA is like ADD, but doesn't have the
3127                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3128                                  * its operand to 64 bit.
3129                                  */
3130                                 ins->opcode = OP_X86_LEA_MEMBASE;
3131                                 ins->inst_basereg = ins->sreg1;
3132                         }
3133                         break;
3134                 case OP_LXOR:
3135                 case OP_IXOR:
3136                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3137                                 MonoInst *ins2;
3138
3139                                 /*
3140                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3141                                  * the latter has length 2-3 instead of 6 (reverse constant
3142                                  * propagation). These instruction sequences are very common
3143                                  * in the initlocals bblock.
3144                                  */
3145                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3146                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3147                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3148                                                 ins2->sreg1 = ins->dreg;
3149                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3150                                                 /* Continue */
3151                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3152                                                 NULLIFY_INS (ins2);
3153                                                 /* Continue */
3154                                         } else {
3155                                                 break;
3156                                         }
3157                                 }
3158                         }
3159                         break;
3160                 case OP_COMPARE_IMM:
3161                 case OP_LCOMPARE_IMM:
3162                         /* OP_COMPARE_IMM (reg, 0)
3163                          * -->
3164                          * OP_AMD64_TEST_NULL (reg)
3165                          */
3166                         if (!ins->inst_imm)
3167                                 ins->opcode = OP_AMD64_TEST_NULL;
3168                         break;
3169                 case OP_ICOMPARE_IMM:
3170                         if (!ins->inst_imm)
3171                                 ins->opcode = OP_X86_TEST_NULL;
3172                         break;
3173                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3174                         /*
3175                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3176                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3177                          * -->
3178                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3179                          * OP_COMPARE_IMM reg, imm
3180                          *
3181                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3182                          */
3183                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3184                             ins->inst_basereg == last_ins->inst_destbasereg &&
3185                             ins->inst_offset == last_ins->inst_offset) {
3186                                         ins->opcode = OP_ICOMPARE_IMM;
3187                                         ins->sreg1 = last_ins->sreg1;
3188
3189                                         /* check if we can remove cmp reg,0 with test null */
3190                                         if (!ins->inst_imm)
3191                                                 ins->opcode = OP_X86_TEST_NULL;
3192                                 }
3193
3194                         break;
3195                 }
3196
3197                 mono_peephole_ins (bb, ins);
3198         }
3199 }
3200
3201 void
3202 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3203 {
3204         MonoInst *ins, *n;
3205
3206         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3207                 switch (ins->opcode) {
3208                 case OP_ICONST:
3209                 case OP_I8CONST: {
3210                         /* reg = 0 -> XOR (reg, reg) */
3211                         /* XOR sets cflags on x86, so we cant do it always */
3212                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3213                                 ins->opcode = OP_LXOR;
3214                                 ins->sreg1 = ins->dreg;
3215                                 ins->sreg2 = ins->dreg;
3216                                 /* Fall through */
3217                         } else {
3218                                 break;
3219                         }
3220                 }
3221                 case OP_LXOR:
3222                         /*
3223                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3224                          * 0 result into 64 bits.
3225                          */
3226                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3227                                 ins->opcode = OP_IXOR;
3228                         }
3229                         /* Fall through */
3230                 case OP_IXOR:
3231                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3232                                 MonoInst *ins2;
3233
3234                                 /*
3235                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3236                                  * the latter has length 2-3 instead of 6 (reverse constant
3237                                  * propagation). These instruction sequences are very common
3238                                  * in the initlocals bblock.
3239                                  */
3240                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3241                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3242                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3243                                                 ins2->sreg1 = ins->dreg;
3244                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3245                                                 /* Continue */
3246                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3247                                                 NULLIFY_INS (ins2);
3248                                                 /* Continue */
3249                                         } else {
3250                                                 break;
3251                                         }
3252                                 }
3253                         }
3254                         break;
3255                 case OP_IADD_IMM:
3256                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3257                                 ins->opcode = OP_X86_INC_REG;
3258                         break;
3259                 case OP_ISUB_IMM:
3260                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3261                                 ins->opcode = OP_X86_DEC_REG;
3262                         break;
3263                 }
3264
3265                 mono_peephole_ins (bb, ins);
3266         }
3267 }
3268
3269 #define NEW_INS(cfg,ins,dest,op) do {   \
3270                 MONO_INST_NEW ((cfg), (dest), (op)); \
3271         (dest)->cil_code = (ins)->cil_code; \
3272         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3273         } while (0)
3274
3275 /*
3276  * mono_arch_lowering_pass:
3277  *
3278  *  Converts complex opcodes into simpler ones so that each IR instruction
3279  * corresponds to one machine instruction.
3280  */
3281 void
3282 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3283 {
3284         MonoInst *ins, *n, *temp;
3285
3286         /*
3287          * FIXME: Need to add more instructions, but the current machine
3288          * description can't model some parts of the composite instructions like
3289          * cdq.
3290          */
3291         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3292                 switch (ins->opcode) {
3293                 case OP_DIV_IMM:
3294                 case OP_REM_IMM:
3295                 case OP_IDIV_IMM:
3296                 case OP_IDIV_UN_IMM:
3297                 case OP_IREM_UN_IMM:
3298                         mono_decompose_op_imm (cfg, bb, ins);
3299                         break;
3300                 case OP_IREM_IMM:
3301                         /* Keep the opcode if we can implement it efficiently */
3302                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
3303                                 mono_decompose_op_imm (cfg, bb, ins);
3304                         break;
3305                 case OP_COMPARE_IMM:
3306                 case OP_LCOMPARE_IMM:
3307                         if (!amd64_is_imm32 (ins->inst_imm)) {
3308                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3309                                 temp->inst_c0 = ins->inst_imm;
3310                                 temp->dreg = mono_alloc_ireg (cfg);
3311                                 ins->opcode = OP_COMPARE;
3312                                 ins->sreg2 = temp->dreg;
3313                         }
3314                         break;
3315 #ifndef __mono_ilp32__
3316                 case OP_LOAD_MEMBASE:
3317 #endif
3318                 case OP_LOADI8_MEMBASE:
3319 #ifndef __native_client_codegen__
3320                 /*  Don't generate memindex opcodes (to simplify */
3321                 /*  read sandboxing) */
3322                         if (!amd64_is_imm32 (ins->inst_offset)) {
3323                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3324                                 temp->inst_c0 = ins->inst_offset;
3325                                 temp->dreg = mono_alloc_ireg (cfg);
3326                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3327                                 ins->inst_indexreg = temp->dreg;
3328                         }
3329 #endif
3330                         break;
3331 #ifndef __mono_ilp32__
3332                 case OP_STORE_MEMBASE_IMM:
3333 #endif
3334                 case OP_STOREI8_MEMBASE_IMM:
3335                         if (!amd64_is_imm32 (ins->inst_imm)) {
3336                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3337                                 temp->inst_c0 = ins->inst_imm;
3338                                 temp->dreg = mono_alloc_ireg (cfg);
3339                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3340                                 ins->sreg1 = temp->dreg;
3341                         }
3342                         break;
3343 #ifdef MONO_ARCH_SIMD_INTRINSICS
3344                 case OP_EXPAND_I1: {
3345                                 int temp_reg1 = mono_alloc_ireg (cfg);
3346                                 int temp_reg2 = mono_alloc_ireg (cfg);
3347                                 int original_reg = ins->sreg1;
3348
3349                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3350                                 temp->sreg1 = original_reg;
3351                                 temp->dreg = temp_reg1;
3352
3353                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3354                                 temp->sreg1 = temp_reg1;
3355                                 temp->dreg = temp_reg2;
3356                                 temp->inst_imm = 8;
3357
3358                                 NEW_INS (cfg, ins, temp, OP_LOR);
3359                                 temp->sreg1 = temp->dreg = temp_reg2;
3360                                 temp->sreg2 = temp_reg1;
3361
3362                                 ins->opcode = OP_EXPAND_I2;
3363                                 ins->sreg1 = temp_reg2;
3364                         }
3365                         break;
3366 #endif
3367                 default:
3368                         break;
3369                 }
3370         }
3371
3372         bb->max_vreg = cfg->next_vreg;
3373 }
3374
3375 static const int
3376 branch_cc_table [] = {
3377         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3378         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3379         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3380 };
3381
3382 /* Maps CMP_... constants to X86_CC_... constants */
3383 static const int
3384 cc_table [] = {
3385         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3386         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3387 };
3388
3389 static const int
3390 cc_signed_table [] = {
3391         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3392         FALSE, FALSE, FALSE, FALSE
3393 };
3394
3395 /*#include "cprop.c"*/
3396
3397 static unsigned char*
3398 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3399 {
3400         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3401
3402         if (size == 1)
3403                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3404         else if (size == 2)
3405                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3406         return code;
3407 }
3408
3409 static unsigned char*
3410 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3411 {
3412         int sreg = tree->sreg1;
3413         int need_touch = FALSE;
3414
3415 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3416         if (!tree->flags & MONO_INST_INIT)
3417                 need_touch = TRUE;
3418 #endif
3419
3420         if (need_touch) {
3421                 guint8* br[5];
3422
3423                 /*
3424                  * Under Windows:
3425                  * If requested stack size is larger than one page,
3426                  * perform stack-touch operation
3427                  */
3428                 /*
3429                  * Generate stack probe code.
3430                  * Under Windows, it is necessary to allocate one page at a time,
3431                  * "touching" stack after each successful sub-allocation. This is
3432                  * because of the way stack growth is implemented - there is a
3433                  * guard page before the lowest stack page that is currently commited.
3434                  * Stack normally grows sequentially so OS traps access to the
3435                  * guard page and commits more pages when needed.
3436                  */
3437                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3438                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3439
3440                 br[2] = code; /* loop */
3441                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3442                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3443                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3444                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3445                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3446                 amd64_patch (br[3], br[2]);
3447                 amd64_test_reg_reg (code, sreg, sreg);
3448                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3449                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3450
3451                 br[1] = code; x86_jump8 (code, 0);
3452
3453                 amd64_patch (br[0], code);
3454                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3455                 amd64_patch (br[1], code);
3456                 amd64_patch (br[4], code);
3457         }
3458         else
3459                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3460
3461         if (tree->flags & MONO_INST_INIT) {
3462                 int offset = 0;
3463                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3464                         amd64_push_reg (code, AMD64_RAX);
3465                         offset += 8;
3466                 }
3467                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3468                         amd64_push_reg (code, AMD64_RCX);
3469                         offset += 8;
3470                 }
3471                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3472                         amd64_push_reg (code, AMD64_RDI);
3473                         offset += 8;
3474                 }
3475
3476                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3477                 if (sreg != AMD64_RCX)
3478                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3479                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3480
3481                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3482                 if (cfg->param_area && cfg->arch.no_pushes)
3483                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3484                 amd64_cld (code);
3485 #if defined(__default_codegen__)
3486                 amd64_prefix (code, X86_REP_PREFIX);
3487                 amd64_stosl (code);
3488 #elif defined(__native_client_codegen__)
3489                 /* NaCl stos pseudo-instruction */
3490                 amd64_codegen_pre(code);
3491                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3492                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3493                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3494                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3495                 amd64_prefix (code, X86_REP_PREFIX);
3496                 amd64_stosl (code);
3497                 amd64_codegen_post(code);
3498 #endif /* __native_client_codegen__ */
3499
3500                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3501                         amd64_pop_reg (code, AMD64_RDI);
3502                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3503                         amd64_pop_reg (code, AMD64_RCX);
3504                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3505                         amd64_pop_reg (code, AMD64_RAX);
3506         }
3507         return code;
3508 }
3509
3510 static guint8*
3511 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3512 {
3513         CallInfo *cinfo;
3514         guint32 quad;
3515
3516         /* Move return value to the target register */
3517         /* FIXME: do this in the local reg allocator */
3518         switch (ins->opcode) {
3519         case OP_CALL:
3520         case OP_CALL_REG:
3521         case OP_CALL_MEMBASE:
3522         case OP_LCALL:
3523         case OP_LCALL_REG:
3524         case OP_LCALL_MEMBASE:
3525                 g_assert (ins->dreg == AMD64_RAX);
3526                 break;
3527         case OP_FCALL:
3528         case OP_FCALL_REG:
3529         case OP_FCALL_MEMBASE:
3530                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3531                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3532                 }
3533                 else {
3534                         if (ins->dreg != AMD64_XMM0)
3535                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3536                 }
3537                 break;
3538         case OP_VCALL:
3539         case OP_VCALL_REG:
3540         case OP_VCALL_MEMBASE:
3541         case OP_VCALL2:
3542         case OP_VCALL2_REG:
3543         case OP_VCALL2_MEMBASE:
3544                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3545                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3546                         MonoInst *loc = cfg->arch.vret_addr_loc;
3547
3548                         /* Load the destination address */
3549                         g_assert (loc->opcode == OP_REGOFFSET);
3550                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3551
3552                         for (quad = 0; quad < 2; quad ++) {
3553                                 switch (cinfo->ret.pair_storage [quad]) {
3554                                 case ArgInIReg:
3555                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3556                                         break;
3557                                 case ArgInFloatSSEReg:
3558                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3559                                         break;
3560                                 case ArgInDoubleSSEReg:
3561                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3562                                         break;
3563                                 case ArgNone:
3564                                         break;
3565                                 default:
3566                                         NOT_IMPLEMENTED;
3567                                 }
3568                         }
3569                 }
3570                 break;
3571         }
3572
3573         return code;
3574 }
3575
3576 #endif /* DISABLE_JIT */
3577
3578 #ifdef __APPLE__
3579 static int tls_gs_offset;
3580 #endif
3581
3582 gboolean
3583 mono_amd64_have_tls_get (void)
3584 {
3585 #ifdef __APPLE__
3586         static gboolean have_tls_get = FALSE;
3587         static gboolean inited = FALSE;
3588         guint8 *ins;
3589
3590         if (inited)
3591                 return have_tls_get;
3592
3593         ins = (guint8*)pthread_getspecific;
3594
3595         /*
3596          * We're looking for these two instructions:
3597          *
3598          * mov    %gs:[offset](,%rdi,8),%rax
3599          * retq
3600          */
3601         have_tls_get = ins [0] == 0x65 &&
3602                        ins [1] == 0x48 &&
3603                        ins [2] == 0x8b &&
3604                        ins [3] == 0x04 &&
3605                        ins [4] == 0xfd &&
3606                        ins [6] == 0x00 &&
3607                        ins [7] == 0x00 &&
3608                        ins [8] == 0x00 &&
3609                        ins [9] == 0xc3;
3610
3611         inited = TRUE;
3612
3613         tls_gs_offset = ins[5];
3614
3615         return have_tls_get;
3616 #else
3617         return TRUE;
3618 #endif
3619 }
3620
3621 int
3622 mono_amd64_get_tls_gs_offset (void)
3623 {
3624 #ifdef TARGET_OSX
3625         return tls_gs_offset;
3626 #else
3627         g_assert_not_reached ();
3628         return -1;
3629 #endif
3630 }
3631
3632 /*
3633  * mono_amd64_emit_tls_get:
3634  * @code: buffer to store code to
3635  * @dreg: hard register where to place the result
3636  * @tls_offset: offset info
3637  *
3638  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3639  * the dreg register the item in the thread local storage identified
3640  * by tls_offset.
3641  *
3642  * Returns: a pointer to the end of the stored code
3643  */
3644 guint8*
3645 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3646 {
3647 #ifdef HOST_WIN32
3648         g_assert (tls_offset < 64);
3649         x86_prefix (code, X86_GS_PREFIX);
3650         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3651 #elif defined(__APPLE__)
3652         x86_prefix (code, X86_GS_PREFIX);
3653         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3654 #else
3655         if (optimize_for_xen) {
3656                 x86_prefix (code, X86_FS_PREFIX);
3657                 amd64_mov_reg_mem (code, dreg, 0, 8);
3658                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3659         } else {
3660                 x86_prefix (code, X86_FS_PREFIX);
3661                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3662         }
3663 #endif
3664         return code;
3665 }
3666
3667 static guint8*
3668 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3669 {
3670         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3671 #ifdef TARGET_OSX
3672         if (dreg != offset_reg)
3673                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3674         amd64_prefix (code, X86_GS_PREFIX);
3675         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3676 #elif defined(__linux__)
3677         int tmpreg = -1;
3678
3679         if (dreg == offset_reg) {
3680                 /* Use a temporary reg by saving it to the redzone */
3681                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3682                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3683                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3684                 offset_reg = tmpreg;
3685         }
3686         x86_prefix (code, X86_FS_PREFIX);
3687         amd64_mov_reg_mem (code, dreg, 0, 8);
3688         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3689         if (tmpreg != -1)
3690                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3691 #else
3692         g_assert_not_reached ();
3693 #endif
3694         return code;
3695 }
3696
3697 static guint8*
3698 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3699 {
3700 #ifdef HOST_WIN32
3701         g_assert_not_reached ();
3702 #elif defined(__APPLE__)
3703         x86_prefix (code, X86_GS_PREFIX);
3704         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3705 #else
3706         g_assert (!optimize_for_xen);
3707         x86_prefix (code, X86_FS_PREFIX);
3708         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3709 #endif
3710         return code;
3711 }
3712
3713 static guint8*
3714 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3715 {
3716         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3717 #ifdef HOST_WIN32
3718         g_assert_not_reached ();
3719 #elif defined(__APPLE__)
3720         x86_prefix (code, X86_GS_PREFIX);
3721         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3722 #else
3723         x86_prefix (code, X86_FS_PREFIX);
3724         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3725 #endif
3726         return code;
3727 }
3728
3729  /*
3730  * mono_arch_translate_tls_offset:
3731  *
3732  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3733  */
3734 int
3735 mono_arch_translate_tls_offset (int offset)
3736 {
3737 #ifdef __APPLE__
3738         return tls_gs_offset + (offset * 8);
3739 #else
3740         return offset;
3741 #endif
3742 }
3743
3744 /*
3745  * emit_setup_lmf:
3746  *
3747  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3748  */
3749 static guint8*
3750 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3751 {
3752         int i;
3753
3754         /*
3755          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3756          */
3757         /*
3758          * sp is saved right before calls but we need to save it here too so
3759          * async stack walks would work.
3760          */
3761         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3762         /* Skip method (only needed for trampoline LMF frames) */
3763         /* Save callee saved regs */
3764         for (i = 0; i < MONO_MAX_IREGS; ++i) {
3765                 int offset;
3766
3767                 switch (i) {
3768                 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
3769                 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
3770                 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
3771                 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
3772                 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
3773 #ifndef __native_client_codegen__
3774                 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
3775 #endif
3776 #ifdef HOST_WIN32
3777                 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
3778                 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
3779 #endif
3780                 default:
3781                         offset = -1;
3782                         break;
3783                 }
3784
3785                 if (offset != -1) {
3786                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
3787                         if ((cfg->arch.omit_fp || (i != AMD64_RBP)) && cfa_offset != -1)
3788                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
3789                 }
3790         }
3791
3792         /* These can't contain refs */
3793         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3794 #ifdef HOST_WIN32
3795         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3796 #endif
3797         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3798         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3799
3800         /* These are handled automatically by the stack marking code */
3801         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), SLOT_NOREF);
3802         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3803         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), SLOT_NOREF);
3804         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), SLOT_NOREF);
3805         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), SLOT_NOREF);
3806         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), SLOT_NOREF);
3807 #ifdef HOST_WIN32
3808         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), SLOT_NOREF);
3809         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), SLOT_NOREF);
3810 #endif
3811
3812         return code;
3813 }
3814
3815 #ifdef HOST_WIN32
3816 /*
3817  * emit_push_lmf:
3818  *
3819  *   Emit code to push an LMF structure on the LMF stack.
3820  */
3821 static guint8*
3822 emit_push_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, gboolean *args_clobbered)
3823 {
3824         if (jit_tls_offset != -1) {
3825                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, jit_tls_offset);
3826                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
3827         } else {
3828                 /*
3829                  * The call might clobber argument registers, but they are already
3830                  * saved to the stack/global regs.
3831                  */
3832                 if (args_clobbered)
3833                         *args_clobbered = TRUE;
3834                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3835                                                   (gpointer)"mono_get_lmf_addr", TRUE);
3836         }
3837
3838         /* Save lmf_addr */
3839         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3840         /* Save previous_lmf */
3841         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
3842         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3843         /* Set new lmf */
3844         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3845         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
3846
3847         return code;
3848 }
3849 #endif
3850
3851 #ifdef HOST_WIN32
3852 /*
3853  * emit_pop_lmf:
3854  *
3855  *   Emit code to pop an LMF structure from the LMF stack.
3856  */
3857 static guint8*
3858 emit_pop_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
3859 {
3860         /* Restore previous lmf */
3861         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3862         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3863         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
3864
3865         return code;
3866 }
3867 #endif
3868
3869 #define REAL_PRINT_REG(text,reg) \
3870 mono_assert (reg >= 0); \
3871 amd64_push_reg (code, AMD64_RAX); \
3872 amd64_push_reg (code, AMD64_RDX); \
3873 amd64_push_reg (code, AMD64_RCX); \
3874 amd64_push_reg (code, reg); \
3875 amd64_push_imm (code, reg); \
3876 amd64_push_imm (code, text " %d %p\n"); \
3877 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3878 amd64_call_reg (code, AMD64_RAX); \
3879 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3880 amd64_pop_reg (code, AMD64_RCX); \
3881 amd64_pop_reg (code, AMD64_RDX); \
3882 amd64_pop_reg (code, AMD64_RAX);
3883
3884 /* benchmark and set based on cpu */
3885 #define LOOP_ALIGNMENT 8
3886 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3887
3888 #ifndef DISABLE_JIT
3889 void
3890 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3891 {
3892         MonoInst *ins;
3893         MonoCallInst *call;
3894         guint offset;
3895         guint8 *code = cfg->native_code + cfg->code_len;
3896         MonoInst *last_ins = NULL;
3897         guint last_offset = 0;
3898         int max_len;
3899
3900         /* Fix max_offset estimate for each successor bb */
3901         if (cfg->opt & MONO_OPT_BRANCH) {
3902                 int current_offset = cfg->code_len;
3903                 MonoBasicBlock *current_bb;
3904                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3905                         current_bb->max_offset = current_offset;
3906                         current_offset += current_bb->max_length;
3907                 }
3908         }
3909
3910         if (cfg->opt & MONO_OPT_LOOP) {
3911                 int pad, align = LOOP_ALIGNMENT;
3912                 /* set alignment depending on cpu */
3913                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3914                         pad = align - pad;
3915                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3916                         amd64_padding (code, pad);
3917                         cfg->code_len += pad;
3918                         bb->native_offset = cfg->code_len;
3919                 }
3920         }
3921
3922 #if defined(__native_client_codegen__)
3923         /* For Native Client, all indirect call/jump targets must be */
3924         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3925         /* indirectly as well.                                       */
3926         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3927                                       (bb->flags & BB_EXCEPTION_HANDLER);
3928
3929         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3930                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3931                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3932                 cfg->code_len += pad;
3933                 bb->native_offset = cfg->code_len;
3934         }
3935 #endif  /*__native_client_codegen__*/
3936
3937         if (cfg->verbose_level > 2)
3938                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3939
3940         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3941                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3942                 g_assert (!cfg->compile_aot);
3943
3944                 cov->data [bb->dfn].cil_code = bb->cil_code;
3945                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3946                 /* this is not thread save, but good enough */
3947                 amd64_inc_membase (code, AMD64_R11, 0);
3948         }
3949
3950         offset = code - cfg->native_code;
3951
3952         mono_debug_open_block (cfg, bb, offset);
3953
3954     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3955                 x86_breakpoint (code);
3956
3957         MONO_BB_FOR_EACH_INS (bb, ins) {
3958                 offset = code - cfg->native_code;
3959
3960                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3961
3962 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3963
3964                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3965                         cfg->code_size *= 2;
3966                         cfg->native_code = mono_realloc_native_code(cfg);
3967                         code = cfg->native_code + offset;
3968                         cfg->stat_code_reallocs++;
3969                 }
3970
3971                 if (cfg->debug_info)
3972                         mono_debug_record_line_number (cfg, ins, offset);
3973
3974                 switch (ins->opcode) {
3975                 case OP_BIGMUL:
3976                         amd64_mul_reg (code, ins->sreg2, TRUE);
3977                         break;
3978                 case OP_BIGMUL_UN:
3979                         amd64_mul_reg (code, ins->sreg2, FALSE);
3980                         break;
3981                 case OP_X86_SETEQ_MEMBASE:
3982                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3983                         break;
3984                 case OP_STOREI1_MEMBASE_IMM:
3985                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3986                         break;
3987                 case OP_STOREI2_MEMBASE_IMM:
3988                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3989                         break;
3990                 case OP_STOREI4_MEMBASE_IMM:
3991                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3992                         break;
3993                 case OP_STOREI1_MEMBASE_REG:
3994                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3995                         break;
3996                 case OP_STOREI2_MEMBASE_REG:
3997                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3998                         break;
3999                 /* In AMD64 NaCl, pointers are 4 bytes, */
4000                 /*  so STORE_* != STOREI8_*. Likewise below. */
4001                 case OP_STORE_MEMBASE_REG:
4002                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4003                         break;
4004                 case OP_STOREI8_MEMBASE_REG:
4005                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4006                         break;
4007                 case OP_STOREI4_MEMBASE_REG:
4008                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4009                         break;
4010                 case OP_STORE_MEMBASE_IMM:
4011 #ifndef __native_client_codegen__
4012                         /* In NaCl, this could be a PCONST type, which could */
4013                         /* mean a pointer type was copied directly into the  */
4014                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4015                         /* the value would be 0x00000000FFFFFFFF which is    */
4016                         /* not proper for an imm32 unless you cast it.       */
4017                         g_assert (amd64_is_imm32 (ins->inst_imm));
4018 #endif
4019                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4020                         break;
4021                 case OP_STOREI8_MEMBASE_IMM:
4022                         g_assert (amd64_is_imm32 (ins->inst_imm));
4023                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4024                         break;
4025                 case OP_LOAD_MEM:
4026 #ifdef __mono_ilp32__
4027                         /* In ILP32, pointers are 4 bytes, so separate these */
4028                         /* cases, use literal 8 below where we really want 8 */
4029                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4030                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4031                         break;
4032 #endif
4033                 case OP_LOADI8_MEM:
4034                         // FIXME: Decompose this earlier
4035                         if (amd64_is_imm32 (ins->inst_imm))
4036                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4037                         else {
4038                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4039                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4040                         }
4041                         break;
4042                 case OP_LOADI4_MEM:
4043                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4044                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4045                         break;
4046                 case OP_LOADU4_MEM:
4047                         // FIXME: Decompose this earlier
4048                         if (amd64_is_imm32 (ins->inst_imm))
4049                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4050                         else {
4051                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4052                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4053                         }
4054                         break;
4055                 case OP_LOADU1_MEM:
4056                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4057                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4058                         break;
4059                 case OP_LOADU2_MEM:
4060                         /* For NaCl, pointers are 4 bytes, so separate these */
4061                         /* cases, use literal 8 below where we really want 8 */
4062                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4063                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4064                         break;
4065                 case OP_LOAD_MEMBASE:
4066                         g_assert (amd64_is_imm32 (ins->inst_offset));
4067                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4068                         break;
4069                 case OP_LOADI8_MEMBASE:
4070                         /* Use literal 8 instead of sizeof pointer or */
4071                         /* register, we really want 8 for this opcode */
4072                         g_assert (amd64_is_imm32 (ins->inst_offset));
4073                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4074                         break;
4075                 case OP_LOADI4_MEMBASE:
4076                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4077                         break;
4078                 case OP_LOADU4_MEMBASE:
4079                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4080                         break;
4081                 case OP_LOADU1_MEMBASE:
4082                         /* The cpu zero extends the result into 64 bits */
4083                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4084                         break;
4085                 case OP_LOADI1_MEMBASE:
4086                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4087                         break;
4088                 case OP_LOADU2_MEMBASE:
4089                         /* The cpu zero extends the result into 64 bits */
4090                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4091                         break;
4092                 case OP_LOADI2_MEMBASE:
4093                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4094                         break;
4095                 case OP_AMD64_LOADI8_MEMINDEX:
4096                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4097                         break;
4098                 case OP_LCONV_TO_I1:
4099                 case OP_ICONV_TO_I1:
4100                 case OP_SEXT_I1:
4101                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4102                         break;
4103                 case OP_LCONV_TO_I2:
4104                 case OP_ICONV_TO_I2:
4105                 case OP_SEXT_I2:
4106                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4107                         break;
4108                 case OP_LCONV_TO_U1:
4109                 case OP_ICONV_TO_U1:
4110                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4111                         break;
4112                 case OP_LCONV_TO_U2:
4113                 case OP_ICONV_TO_U2:
4114                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4115                         break;
4116                 case OP_ZEXT_I4:
4117                         /* Clean out the upper word */
4118                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4119                         break;
4120                 case OP_SEXT_I4:
4121                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4122                         break;
4123                 case OP_COMPARE:
4124                 case OP_LCOMPARE:
4125                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4126                         break;
4127                 case OP_COMPARE_IMM:
4128 #if defined(__mono_ilp32__)
4129                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4130                         g_assert (amd64_is_imm32 (ins->inst_imm));
4131                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4132                         break;
4133 #endif
4134                 case OP_LCOMPARE_IMM:
4135                         g_assert (amd64_is_imm32 (ins->inst_imm));
4136                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4137                         break;
4138                 case OP_X86_COMPARE_REG_MEMBASE:
4139                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4140                         break;
4141                 case OP_X86_TEST_NULL:
4142                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4143                         break;
4144                 case OP_AMD64_TEST_NULL:
4145                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4146                         break;
4147
4148                 case OP_X86_ADD_REG_MEMBASE:
4149                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4150                         break;
4151                 case OP_X86_SUB_REG_MEMBASE:
4152                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4153                         break;
4154                 case OP_X86_AND_REG_MEMBASE:
4155                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4156                         break;
4157                 case OP_X86_OR_REG_MEMBASE:
4158                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4159                         break;
4160                 case OP_X86_XOR_REG_MEMBASE:
4161                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4162                         break;
4163
4164                 case OP_X86_ADD_MEMBASE_IMM:
4165                         /* FIXME: Make a 64 version too */
4166                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4167                         break;
4168                 case OP_X86_SUB_MEMBASE_IMM:
4169                         g_assert (amd64_is_imm32 (ins->inst_imm));
4170                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4171                         break;
4172                 case OP_X86_AND_MEMBASE_IMM:
4173                         g_assert (amd64_is_imm32 (ins->inst_imm));
4174                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4175                         break;
4176                 case OP_X86_OR_MEMBASE_IMM:
4177                         g_assert (amd64_is_imm32 (ins->inst_imm));
4178                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4179                         break;
4180                 case OP_X86_XOR_MEMBASE_IMM:
4181                         g_assert (amd64_is_imm32 (ins->inst_imm));
4182                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4183                         break;
4184                 case OP_X86_ADD_MEMBASE_REG:
4185                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4186                         break;
4187                 case OP_X86_SUB_MEMBASE_REG:
4188                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4189                         break;
4190                 case OP_X86_AND_MEMBASE_REG:
4191                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4192                         break;
4193                 case OP_X86_OR_MEMBASE_REG:
4194                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4195                         break;
4196                 case OP_X86_XOR_MEMBASE_REG:
4197                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4198                         break;
4199                 case OP_X86_INC_MEMBASE:
4200                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4201                         break;
4202                 case OP_X86_INC_REG:
4203                         amd64_inc_reg_size (code, ins->dreg, 4);
4204                         break;
4205                 case OP_X86_DEC_MEMBASE:
4206                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4207                         break;
4208                 case OP_X86_DEC_REG:
4209                         amd64_dec_reg_size (code, ins->dreg, 4);
4210                         break;
4211                 case OP_X86_MUL_REG_MEMBASE:
4212                 case OP_X86_MUL_MEMBASE_REG:
4213                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4214                         break;
4215                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4216                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4217                         break;
4218                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4219                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4220                         break;
4221                 case OP_AMD64_COMPARE_MEMBASE_REG:
4222                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4223                         break;
4224                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4225                         g_assert (amd64_is_imm32 (ins->inst_imm));
4226                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4227                         break;
4228                 case OP_X86_COMPARE_MEMBASE8_IMM:
4229                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4230                         break;
4231                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4232                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4233                         break;
4234                 case OP_AMD64_COMPARE_REG_MEMBASE:
4235                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4236                         break;
4237
4238                 case OP_AMD64_ADD_REG_MEMBASE:
4239                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4240                         break;
4241                 case OP_AMD64_SUB_REG_MEMBASE:
4242                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4243                         break;
4244                 case OP_AMD64_AND_REG_MEMBASE:
4245                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4246                         break;
4247                 case OP_AMD64_OR_REG_MEMBASE:
4248                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4249                         break;
4250                 case OP_AMD64_XOR_REG_MEMBASE:
4251                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4252                         break;
4253
4254                 case OP_AMD64_ADD_MEMBASE_REG:
4255                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4256                         break;
4257                 case OP_AMD64_SUB_MEMBASE_REG:
4258                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4259                         break;
4260                 case OP_AMD64_AND_MEMBASE_REG:
4261                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4262                         break;
4263                 case OP_AMD64_OR_MEMBASE_REG:
4264                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4265                         break;
4266                 case OP_AMD64_XOR_MEMBASE_REG:
4267                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4268                         break;
4269
4270                 case OP_AMD64_ADD_MEMBASE_IMM:
4271                         g_assert (amd64_is_imm32 (ins->inst_imm));
4272                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4273                         break;
4274                 case OP_AMD64_SUB_MEMBASE_IMM:
4275                         g_assert (amd64_is_imm32 (ins->inst_imm));
4276                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4277                         break;
4278                 case OP_AMD64_AND_MEMBASE_IMM:
4279                         g_assert (amd64_is_imm32 (ins->inst_imm));
4280                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4281                         break;
4282                 case OP_AMD64_OR_MEMBASE_IMM:
4283                         g_assert (amd64_is_imm32 (ins->inst_imm));
4284                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4285                         break;
4286                 case OP_AMD64_XOR_MEMBASE_IMM:
4287                         g_assert (amd64_is_imm32 (ins->inst_imm));
4288                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4289                         break;
4290
4291                 case OP_BREAK:
4292                         amd64_breakpoint (code);
4293                         break;
4294                 case OP_RELAXED_NOP:
4295                         x86_prefix (code, X86_REP_PREFIX);
4296                         x86_nop (code);
4297                         break;
4298                 case OP_HARD_NOP:
4299                         x86_nop (code);
4300                         break;
4301                 case OP_NOP:
4302                 case OP_DUMMY_USE:
4303                 case OP_DUMMY_STORE:
4304                 case OP_NOT_REACHED:
4305                 case OP_NOT_NULL:
4306                         break;
4307                 case OP_SEQ_POINT: {
4308                         int i;
4309
4310                         /*
4311                          * Read from the single stepping trigger page. This will cause a
4312                          * SIGSEGV when single stepping is enabled.
4313                          * We do this _before_ the breakpoint, so single stepping after
4314                          * a breakpoint is hit will step to the next IL offset.
4315                          */
4316                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4317                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4318
4319                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4320                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4321                         }
4322
4323                         /*
4324                          * This is the address which is saved in seq points,
4325                          */
4326                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4327
4328                         if (cfg->compile_aot) {
4329                                 guint32 offset = code - cfg->native_code;
4330                                 guint32 val;
4331                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4332
4333                                 /* Load info var */
4334                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4335                                 val = ((offset) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4336                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4337                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4338                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4339                         } else {
4340                                 /*
4341                                  * A placeholder for a possible breakpoint inserted by
4342                                  * mono_arch_set_breakpoint ().
4343                                  */
4344                                 for (i = 0; i < breakpoint_size; ++i)
4345                                         x86_nop (code);
4346                         }
4347                         /*
4348                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4349                          * to another IL offset.
4350                          */
4351                         x86_nop (code);
4352                         break;
4353                 }
4354                 case OP_ADDCC:
4355                 case OP_LADDCC:
4356                 case OP_LADD:
4357                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4358                         break;
4359                 case OP_ADC:
4360                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4361                         break;
4362                 case OP_ADD_IMM:
4363                 case OP_LADD_IMM:
4364                         g_assert (amd64_is_imm32 (ins->inst_imm));
4365                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4366                         break;
4367                 case OP_ADC_IMM:
4368                         g_assert (amd64_is_imm32 (ins->inst_imm));
4369                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4370                         break;
4371                 case OP_SUBCC:
4372                 case OP_LSUBCC:
4373                 case OP_LSUB:
4374                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4375                         break;
4376                 case OP_SBB:
4377                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4378                         break;
4379                 case OP_SUB_IMM:
4380                 case OP_LSUB_IMM:
4381                         g_assert (amd64_is_imm32 (ins->inst_imm));
4382                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4383                         break;
4384                 case OP_SBB_IMM:
4385                         g_assert (amd64_is_imm32 (ins->inst_imm));
4386                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4387                         break;
4388                 case OP_LAND:
4389                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4390                         break;
4391                 case OP_AND_IMM:
4392                 case OP_LAND_IMM:
4393                         g_assert (amd64_is_imm32 (ins->inst_imm));
4394                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4395                         break;
4396                 case OP_LMUL:
4397                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4398                         break;
4399                 case OP_MUL_IMM:
4400                 case OP_LMUL_IMM:
4401                 case OP_IMUL_IMM: {
4402                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4403
4404                         switch (ins->inst_imm) {
4405                         case 2:
4406                                 /* MOV r1, r2 */
4407                                 /* ADD r1, r1 */
4408                                 if (ins->dreg != ins->sreg1)
4409                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4410                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4411                                 break;
4412                         case 3:
4413                                 /* LEA r1, [r2 + r2*2] */
4414                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4415                                 break;
4416                         case 5:
4417                                 /* LEA r1, [r2 + r2*4] */
4418                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4419                                 break;
4420                         case 6:
4421                                 /* LEA r1, [r2 + r2*2] */
4422                                 /* ADD r1, r1          */
4423                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4424                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4425                                 break;
4426                         case 9:
4427                                 /* LEA r1, [r2 + r2*8] */
4428                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4429                                 break;
4430                         case 10:
4431                                 /* LEA r1, [r2 + r2*4] */
4432                                 /* ADD r1, r1          */
4433                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4434                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4435                                 break;
4436                         case 12:
4437                                 /* LEA r1, [r2 + r2*2] */
4438                                 /* SHL r1, 2           */
4439                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4440                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4441                                 break;
4442                         case 25:
4443                                 /* LEA r1, [r2 + r2*4] */
4444                                 /* LEA r1, [r1 + r1*4] */
4445                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4446                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4447                                 break;
4448                         case 100:
4449                                 /* LEA r1, [r2 + r2*4] */
4450                                 /* SHL r1, 2           */
4451                                 /* LEA r1, [r1 + r1*4] */
4452                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4453                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4454                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4455                                 break;
4456                         default:
4457                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4458                                 break;
4459                         }
4460                         break;
4461                 }
4462                 case OP_LDIV:
4463                 case OP_LREM:
4464 #if defined( __native_client_codegen__ )
4465                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4466                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4467 #endif
4468                         /* Regalloc magic makes the div/rem cases the same */
4469                         if (ins->sreg2 == AMD64_RDX) {
4470                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4471                                 amd64_cdq (code);
4472                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4473                         } else {
4474                                 amd64_cdq (code);
4475                                 amd64_div_reg (code, ins->sreg2, TRUE);
4476                         }
4477                         break;
4478                 case OP_LDIV_UN:
4479                 case OP_LREM_UN:
4480 #if defined( __native_client_codegen__ )
4481                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4482                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4483 #endif
4484                         if (ins->sreg2 == AMD64_RDX) {
4485                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4486                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4487                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4488                         } else {
4489                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4490                                 amd64_div_reg (code, ins->sreg2, FALSE);
4491                         }
4492                         break;
4493                 case OP_IDIV:
4494                 case OP_IREM:
4495 #if defined( __native_client_codegen__ )
4496                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4497                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4498 #endif
4499                         if (ins->sreg2 == AMD64_RDX) {
4500                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4501                                 amd64_cdq_size (code, 4);
4502                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4503                         } else {
4504                                 amd64_cdq_size (code, 4);
4505                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4506                         }
4507                         break;
4508                 case OP_IDIV_UN:
4509                 case OP_IREM_UN:
4510 #if defined( __native_client_codegen__ )
4511                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4512                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4513 #endif
4514                         if (ins->sreg2 == AMD64_RDX) {
4515                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4516                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4517                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4518                         } else {
4519                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4520                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4521                         }
4522                         break;
4523                 case OP_IREM_IMM: {
4524                         int power = mono_is_power_of_two (ins->inst_imm);
4525
4526                         g_assert (ins->sreg1 == X86_EAX);
4527                         g_assert (ins->dreg == X86_EAX);
4528                         g_assert (power >= 0);
4529
4530                         if (power == 0) {
4531                                 amd64_mov_reg_imm (code, ins->dreg, 0);
4532                                 break;
4533                         }
4534
4535                         /* Based on gcc code */
4536
4537                         /* Add compensation for negative dividents */
4538                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
4539                         if (power > 1)
4540                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
4541                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
4542                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
4543                         /* Compute remainder */
4544                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
4545                         /* Remove compensation */
4546                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
4547                         break;
4548                 }
4549                 case OP_LMUL_OVF:
4550                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4551                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4552                         break;
4553                 case OP_LOR:
4554                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4555                         break;
4556                 case OP_OR_IMM:
4557                 case OP_LOR_IMM:
4558                         g_assert (amd64_is_imm32 (ins->inst_imm));
4559                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4560                         break;
4561                 case OP_LXOR:
4562                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4563                         break;
4564                 case OP_XOR_IMM:
4565                 case OP_LXOR_IMM:
4566                         g_assert (amd64_is_imm32 (ins->inst_imm));
4567                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4568                         break;
4569                 case OP_LSHL:
4570                         g_assert (ins->sreg2 == AMD64_RCX);
4571                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4572                         break;
4573                 case OP_LSHR:
4574                         g_assert (ins->sreg2 == AMD64_RCX);
4575                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4576                         break;
4577                 case OP_SHR_IMM:
4578                         g_assert (amd64_is_imm32 (ins->inst_imm));
4579                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4580                         break;
4581                 case OP_LSHR_IMM:
4582                         g_assert (amd64_is_imm32 (ins->inst_imm));
4583                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4584                         break;
4585                 case OP_SHR_UN_IMM:
4586                         g_assert (amd64_is_imm32 (ins->inst_imm));
4587                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4588                         break;
4589                 case OP_LSHR_UN_IMM:
4590                         g_assert (amd64_is_imm32 (ins->inst_imm));
4591                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4592                         break;
4593                 case OP_LSHR_UN:
4594                         g_assert (ins->sreg2 == AMD64_RCX);
4595                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4596                         break;
4597                 case OP_SHL_IMM:
4598                         g_assert (amd64_is_imm32 (ins->inst_imm));
4599                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4600                         break;
4601                 case OP_LSHL_IMM:
4602                         g_assert (amd64_is_imm32 (ins->inst_imm));
4603                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4604                         break;
4605
4606                 case OP_IADDCC:
4607                 case OP_IADD:
4608                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4609                         break;
4610                 case OP_IADC:
4611                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4612                         break;
4613                 case OP_IADD_IMM:
4614                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4615                         break;
4616                 case OP_IADC_IMM:
4617                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4618                         break;
4619                 case OP_ISUBCC:
4620                 case OP_ISUB:
4621                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4622                         break;
4623                 case OP_ISBB:
4624                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4625                         break;
4626                 case OP_ISUB_IMM:
4627                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4628                         break;
4629                 case OP_ISBB_IMM:
4630                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4631                         break;
4632                 case OP_IAND:
4633                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4634                         break;
4635                 case OP_IAND_IMM:
4636                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4637                         break;
4638                 case OP_IOR:
4639                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4640                         break;
4641                 case OP_IOR_IMM:
4642                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4643                         break;
4644                 case OP_IXOR:
4645                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4646                         break;
4647                 case OP_IXOR_IMM:
4648                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4649                         break;
4650                 case OP_INEG:
4651                         amd64_neg_reg_size (code, ins->sreg1, 4);
4652                         break;
4653                 case OP_INOT:
4654                         amd64_not_reg_size (code, ins->sreg1, 4);
4655                         break;
4656                 case OP_ISHL:
4657                         g_assert (ins->sreg2 == AMD64_RCX);
4658                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4659                         break;
4660                 case OP_ISHR:
4661                         g_assert (ins->sreg2 == AMD64_RCX);
4662                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4663                         break;
4664                 case OP_ISHR_IMM:
4665                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4666                         break;
4667                 case OP_ISHR_UN_IMM:
4668                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4669                         break;
4670                 case OP_ISHR_UN:
4671                         g_assert (ins->sreg2 == AMD64_RCX);
4672                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4673                         break;
4674                 case OP_ISHL_IMM:
4675                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4676                         break;
4677                 case OP_IMUL:
4678                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4679                         break;
4680                 case OP_IMUL_OVF:
4681                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4682                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4683                         break;
4684                 case OP_IMUL_OVF_UN:
4685                 case OP_LMUL_OVF_UN: {
4686                         /* the mul operation and the exception check should most likely be split */
4687                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4688                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4689                         /*g_assert (ins->sreg2 == X86_EAX);
4690                         g_assert (ins->dreg == X86_EAX);*/
4691                         if (ins->sreg2 == X86_EAX) {
4692                                 non_eax_reg = ins->sreg1;
4693                         } else if (ins->sreg1 == X86_EAX) {
4694                                 non_eax_reg = ins->sreg2;
4695                         } else {
4696                                 /* no need to save since we're going to store to it anyway */
4697                                 if (ins->dreg != X86_EAX) {
4698                                         saved_eax = TRUE;
4699                                         amd64_push_reg (code, X86_EAX);
4700                                 }
4701                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4702                                 non_eax_reg = ins->sreg2;
4703                         }
4704                         if (ins->dreg == X86_EDX) {
4705                                 if (!saved_eax) {
4706                                         saved_eax = TRUE;
4707                                         amd64_push_reg (code, X86_EAX);
4708                                 }
4709                         } else {
4710                                 saved_edx = TRUE;
4711                                 amd64_push_reg (code, X86_EDX);
4712                         }
4713                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4714                         /* save before the check since pop and mov don't change the flags */
4715                         if (ins->dreg != X86_EAX)
4716                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4717                         if (saved_edx)
4718                                 amd64_pop_reg (code, X86_EDX);
4719                         if (saved_eax)
4720                                 amd64_pop_reg (code, X86_EAX);
4721                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4722                         break;
4723                 }
4724                 case OP_ICOMPARE:
4725                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4726                         break;
4727                 case OP_ICOMPARE_IMM:
4728                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4729                         break;
4730                 case OP_IBEQ:
4731                 case OP_IBLT:
4732                 case OP_IBGT:
4733                 case OP_IBGE:
4734                 case OP_IBLE:
4735                 case OP_LBEQ:
4736                 case OP_LBLT:
4737                 case OP_LBGT:
4738                 case OP_LBGE:
4739                 case OP_LBLE:
4740                 case OP_IBNE_UN:
4741                 case OP_IBLT_UN:
4742                 case OP_IBGT_UN:
4743                 case OP_IBGE_UN:
4744                 case OP_IBLE_UN:
4745                 case OP_LBNE_UN:
4746                 case OP_LBLT_UN:
4747                 case OP_LBGT_UN:
4748                 case OP_LBGE_UN:
4749                 case OP_LBLE_UN:
4750                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4751                         break;
4752
4753                 case OP_CMOV_IEQ:
4754                 case OP_CMOV_IGE:
4755                 case OP_CMOV_IGT:
4756                 case OP_CMOV_ILE:
4757                 case OP_CMOV_ILT:
4758                 case OP_CMOV_INE_UN:
4759                 case OP_CMOV_IGE_UN:
4760                 case OP_CMOV_IGT_UN:
4761                 case OP_CMOV_ILE_UN:
4762                 case OP_CMOV_ILT_UN:
4763                 case OP_CMOV_LEQ:
4764                 case OP_CMOV_LGE:
4765                 case OP_CMOV_LGT:
4766                 case OP_CMOV_LLE:
4767                 case OP_CMOV_LLT:
4768                 case OP_CMOV_LNE_UN:
4769                 case OP_CMOV_LGE_UN:
4770                 case OP_CMOV_LGT_UN:
4771                 case OP_CMOV_LLE_UN:
4772                 case OP_CMOV_LLT_UN:
4773                         g_assert (ins->dreg == ins->sreg1);
4774                         /* This needs to operate on 64 bit values */
4775                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4776                         break;
4777
4778                 case OP_LNOT:
4779                         amd64_not_reg (code, ins->sreg1);
4780                         break;
4781                 case OP_LNEG:
4782                         amd64_neg_reg (code, ins->sreg1);
4783                         break;
4784
4785                 case OP_ICONST:
4786                 case OP_I8CONST:
4787                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4788                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4789                         else
4790                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4791                         break;
4792                 case OP_AOTCONST:
4793                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4794                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4795                         break;
4796                 case OP_JUMP_TABLE:
4797                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4798                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4799                         break;
4800                 case OP_MOVE:
4801                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4802                         break;
4803                 case OP_AMD64_SET_XMMREG_R4: {
4804                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4805                         break;
4806                 }
4807                 case OP_AMD64_SET_XMMREG_R8: {
4808                         if (ins->dreg != ins->sreg1)
4809                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4810                         break;
4811                 }
4812                 case OP_TAILCALL: {
4813                         MonoCallInst *call = (MonoCallInst*)ins;
4814                         int i, save_area_offset;
4815
4816                         /* FIXME: no tracing support... */
4817                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4818                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, TRUE);
4819
4820                         g_assert (!cfg->method->save_lmf);
4821
4822                         /* Restore callee saved registers */
4823                         save_area_offset = cfg->arch.reg_save_area_offset;
4824                         for (i = 0; i < AMD64_NREG; ++i)
4825                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4826                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4827                                         save_area_offset += 8;
4828                                 }
4829
4830                         if (cfg->arch.omit_fp) {
4831                                 if (cfg->arch.stack_alloc_size)
4832                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4833                                 // FIXME:
4834                                 if (call->stack_usage)
4835                                         NOT_IMPLEMENTED;
4836                         } else {
4837                                 /* Copy arguments on the stack to our argument area */
4838                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4839                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4840                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4841                                 }
4842
4843                                 amd64_leave (code);
4844                         }
4845
4846                         offset = code - cfg->native_code;
4847                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4848                         if (cfg->compile_aot)
4849                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4850                         else
4851                                 amd64_set_reg_template (code, AMD64_R11);
4852                         amd64_jump_reg (code, AMD64_R11);
4853                         ins->flags |= MONO_INST_GC_CALLSITE;
4854                         ins->backend.pc_offset = code - cfg->native_code;
4855                         break;
4856                 }
4857                 case OP_CHECK_THIS:
4858                         /* ensure ins->sreg1 is not NULL */
4859                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4860                         break;
4861                 case OP_ARGLIST: {
4862                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4863                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4864                         break;
4865                 }
4866                 case OP_CALL:
4867                 case OP_FCALL:
4868                 case OP_LCALL:
4869                 case OP_VCALL:
4870                 case OP_VCALL2:
4871                 case OP_VOIDCALL:
4872                         call = (MonoCallInst*)ins;
4873                         /*
4874                          * The AMD64 ABI forces callers to know about varargs.
4875                          */
4876                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4877                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4878                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4879                                 /*
4880                                  * Since the unmanaged calling convention doesn't contain a
4881                                  * 'vararg' entry, we have to treat every pinvoke call as a
4882                                  * potential vararg call.
4883                                  */
4884                                 guint32 nregs, i;
4885                                 nregs = 0;
4886                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4887                                         if (call->used_fregs & (1 << i))
4888                                                 nregs ++;
4889                                 if (!nregs)
4890                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4891                                 else
4892                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4893                         }
4894
4895                         if (ins->flags & MONO_INST_HAS_METHOD)
4896                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4897                         else
4898                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4899                         ins->flags |= MONO_INST_GC_CALLSITE;
4900                         ins->backend.pc_offset = code - cfg->native_code;
4901                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4902                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4903                         code = emit_move_return_value (cfg, ins, code);
4904                         break;
4905                 case OP_FCALL_REG:
4906                 case OP_LCALL_REG:
4907                 case OP_VCALL_REG:
4908                 case OP_VCALL2_REG:
4909                 case OP_VOIDCALL_REG:
4910                 case OP_CALL_REG:
4911                         call = (MonoCallInst*)ins;
4912
4913                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4914                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4915                                 ins->sreg1 = AMD64_R11;
4916                         }
4917
4918                         /*
4919                          * The AMD64 ABI forces callers to know about varargs.
4920                          */
4921                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4922                                 if (ins->sreg1 == AMD64_RAX) {
4923                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4924                                         ins->sreg1 = AMD64_R11;
4925                                 }
4926                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4927                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4928                                 /*
4929                                  * Since the unmanaged calling convention doesn't contain a
4930                                  * 'vararg' entry, we have to treat every pinvoke call as a
4931                                  * potential vararg call.
4932                                  */
4933                                 guint32 nregs, i;
4934                                 nregs = 0;
4935                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4936                                         if (call->used_fregs & (1 << i))
4937                                                 nregs ++;
4938                                 if (ins->sreg1 == AMD64_RAX) {
4939                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4940                                         ins->sreg1 = AMD64_R11;
4941                                 }
4942                                 if (!nregs)
4943                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4944                                 else
4945                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4946                         }
4947
4948                         amd64_call_reg (code, ins->sreg1);
4949                         ins->flags |= MONO_INST_GC_CALLSITE;
4950                         ins->backend.pc_offset = code - cfg->native_code;
4951                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4952                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4953                         code = emit_move_return_value (cfg, ins, code);
4954                         break;
4955                 case OP_FCALL_MEMBASE:
4956                 case OP_LCALL_MEMBASE:
4957                 case OP_VCALL_MEMBASE:
4958                 case OP_VCALL2_MEMBASE:
4959                 case OP_VOIDCALL_MEMBASE:
4960                 case OP_CALL_MEMBASE:
4961                         call = (MonoCallInst*)ins;
4962
4963                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4964                         ins->flags |= MONO_INST_GC_CALLSITE;
4965                         ins->backend.pc_offset = code - cfg->native_code;
4966                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4967                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4968                         code = emit_move_return_value (cfg, ins, code);
4969                         break;
4970                 case OP_DYN_CALL: {
4971                         int i;
4972                         MonoInst *var = cfg->dyn_call_var;
4973
4974                         g_assert (var->opcode == OP_REGOFFSET);
4975
4976                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4977                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4978                         /* r10 = ftn */
4979                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4980
4981                         /* Save args buffer */
4982                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4983
4984                         /* Set argument registers */
4985                         for (i = 0; i < PARAM_REGS; ++i)
4986                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4987
4988                         /* Make the call */
4989                         amd64_call_reg (code, AMD64_R10);
4990
4991                         ins->flags |= MONO_INST_GC_CALLSITE;
4992                         ins->backend.pc_offset = code - cfg->native_code;
4993
4994                         /* Save result */
4995                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4996                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4997                         break;
4998                 }
4999                 case OP_AMD64_SAVE_SP_TO_LMF: {
5000                         MonoInst *lmf_var = cfg->lmf_var;
5001                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5002                         break;
5003                 }
5004                 case OP_X86_PUSH:
5005                         g_assert (!cfg->arch.no_pushes);
5006                         amd64_push_reg (code, ins->sreg1);
5007                         break;
5008                 case OP_X86_PUSH_IMM:
5009                         g_assert (!cfg->arch.no_pushes);
5010                         g_assert (amd64_is_imm32 (ins->inst_imm));
5011                         amd64_push_imm (code, ins->inst_imm);
5012                         break;
5013                 case OP_X86_PUSH_MEMBASE:
5014                         g_assert (!cfg->arch.no_pushes);
5015                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5016                         break;
5017                 case OP_X86_PUSH_OBJ: {
5018                         int size = ALIGN_TO (ins->inst_imm, 8);
5019
5020                         g_assert (!cfg->arch.no_pushes);
5021
5022                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5023                         amd64_push_reg (code, AMD64_RDI);
5024                         amd64_push_reg (code, AMD64_RSI);
5025                         amd64_push_reg (code, AMD64_RCX);
5026                         if (ins->inst_offset)
5027                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5028                         else
5029                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5030                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5031                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5032                         amd64_cld (code);
5033                         amd64_prefix (code, X86_REP_PREFIX);
5034                         amd64_movsd (code);
5035                         amd64_pop_reg (code, AMD64_RCX);
5036                         amd64_pop_reg (code, AMD64_RSI);
5037                         amd64_pop_reg (code, AMD64_RDI);
5038                         break;
5039                 }
5040                 case OP_X86_LEA:
5041                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5042                         break;
5043                 case OP_X86_LEA_MEMBASE:
5044                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5045                         break;
5046                 case OP_X86_XCHG:
5047                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5048                         break;
5049                 case OP_LOCALLOC:
5050                         /* keep alignment */
5051                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5052                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5053                         code = mono_emit_stack_alloc (cfg, code, ins);
5054                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5055                         if (cfg->param_area && cfg->arch.no_pushes)
5056                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5057                         break;
5058                 case OP_LOCALLOC_IMM: {
5059                         guint32 size = ins->inst_imm;
5060                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5061
5062                         if (ins->flags & MONO_INST_INIT) {
5063                                 if (size < 64) {
5064                                         int i;
5065
5066                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5067                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5068
5069                                         for (i = 0; i < size; i += 8)
5070                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5071                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5072                                 } else {
5073                                         amd64_mov_reg_imm (code, ins->dreg, size);
5074                                         ins->sreg1 = ins->dreg;
5075
5076                                         code = mono_emit_stack_alloc (cfg, code, ins);
5077                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5078                                 }
5079                         } else {
5080                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5081                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5082                         }
5083                         if (cfg->param_area && cfg->arch.no_pushes)
5084                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5085                         break;
5086                 }
5087                 case OP_THROW: {
5088                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5089                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5090                                              (gpointer)"mono_arch_throw_exception", FALSE);
5091                         ins->flags |= MONO_INST_GC_CALLSITE;
5092                         ins->backend.pc_offset = code - cfg->native_code;
5093                         break;
5094                 }
5095                 case OP_RETHROW: {
5096                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5097                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5098                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5099                         ins->flags |= MONO_INST_GC_CALLSITE;
5100                         ins->backend.pc_offset = code - cfg->native_code;
5101                         break;
5102                 }
5103                 case OP_CALL_HANDLER:
5104                         /* Align stack */
5105                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5106                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5107                         amd64_call_imm (code, 0);
5108                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5109                         /* Restore stack alignment */
5110                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5111                         break;
5112                 case OP_START_HANDLER: {
5113                         /* Even though we're saving RSP, use sizeof */
5114                         /* gpointer because spvar is of type IntPtr */
5115                         /* see: mono_create_spvar_for_region */
5116                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5117                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5118
5119                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5120                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5121                                 cfg->param_area && cfg->arch.no_pushes) {
5122                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5123                         }
5124                         break;
5125                 }
5126                 case OP_ENDFINALLY: {
5127                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5128                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5129                         amd64_ret (code);
5130                         break;
5131                 }
5132                 case OP_ENDFILTER: {
5133                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5134                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5135                         /* The local allocator will put the result into RAX */
5136                         amd64_ret (code);
5137                         break;
5138                 }
5139
5140                 case OP_LABEL:
5141                         ins->inst_c0 = code - cfg->native_code;
5142                         break;
5143                 case OP_BR:
5144                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5145                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5146                         //break;
5147                                 if (ins->inst_target_bb->native_offset) {
5148                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5149                                 } else {
5150                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5151                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5152                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5153                                                 x86_jump8 (code, 0);
5154                                         else
5155                                                 x86_jump32 (code, 0);
5156                         }
5157                         break;
5158                 case OP_BR_REG:
5159                         amd64_jump_reg (code, ins->sreg1);
5160                         break;
5161                 case OP_ICNEQ:
5162                 case OP_ICGE:
5163                 case OP_ICLE:
5164                 case OP_ICGE_UN:
5165                 case OP_ICLE_UN:
5166
5167                 case OP_CEQ:
5168                 case OP_LCEQ:
5169                 case OP_ICEQ:
5170                 case OP_CLT:
5171                 case OP_LCLT:
5172                 case OP_ICLT:
5173                 case OP_CGT:
5174                 case OP_ICGT:
5175                 case OP_LCGT:
5176                 case OP_CLT_UN:
5177                 case OP_LCLT_UN:
5178                 case OP_ICLT_UN:
5179                 case OP_CGT_UN:
5180                 case OP_LCGT_UN:
5181                 case OP_ICGT_UN:
5182                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5183                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5184                         break;
5185                 case OP_COND_EXC_EQ:
5186                 case OP_COND_EXC_NE_UN:
5187                 case OP_COND_EXC_LT:
5188                 case OP_COND_EXC_LT_UN:
5189                 case OP_COND_EXC_GT:
5190                 case OP_COND_EXC_GT_UN:
5191                 case OP_COND_EXC_GE:
5192                 case OP_COND_EXC_GE_UN:
5193                 case OP_COND_EXC_LE:
5194                 case OP_COND_EXC_LE_UN:
5195                 case OP_COND_EXC_IEQ:
5196                 case OP_COND_EXC_INE_UN:
5197                 case OP_COND_EXC_ILT:
5198                 case OP_COND_EXC_ILT_UN:
5199                 case OP_COND_EXC_IGT:
5200                 case OP_COND_EXC_IGT_UN:
5201                 case OP_COND_EXC_IGE:
5202                 case OP_COND_EXC_IGE_UN:
5203                 case OP_COND_EXC_ILE:
5204                 case OP_COND_EXC_ILE_UN:
5205                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5206                         break;
5207                 case OP_COND_EXC_OV:
5208                 case OP_COND_EXC_NO:
5209                 case OP_COND_EXC_C:
5210                 case OP_COND_EXC_NC:
5211                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5212                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5213                         break;
5214                 case OP_COND_EXC_IOV:
5215                 case OP_COND_EXC_INO:
5216                 case OP_COND_EXC_IC:
5217                 case OP_COND_EXC_INC:
5218                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5219                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5220                         break;
5221
5222                 /* floating point opcodes */
5223                 case OP_R8CONST: {
5224                         double d = *(double *)ins->inst_p0;
5225
5226                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5227                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5228                         }
5229                         else {
5230                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5231                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5232                         }
5233                         break;
5234                 }
5235                 case OP_R4CONST: {
5236                         float f = *(float *)ins->inst_p0;
5237
5238                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5239                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5240                         }
5241                         else {
5242                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5243                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5244                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5245                         }
5246                         break;
5247                 }
5248                 case OP_STORER8_MEMBASE_REG:
5249                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5250                         break;
5251                 case OP_LOADR8_MEMBASE:
5252                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5253                         break;
5254                 case OP_STORER4_MEMBASE_REG:
5255                         /* This requires a double->single conversion */
5256                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5257                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5258                         break;
5259                 case OP_LOADR4_MEMBASE:
5260                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5261                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5262                         break;
5263                 case OP_ICONV_TO_R4: /* FIXME: change precision */
5264                 case OP_ICONV_TO_R8:
5265                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5266                         break;
5267                 case OP_LCONV_TO_R4: /* FIXME: change precision */
5268                 case OP_LCONV_TO_R8:
5269                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5270                         break;
5271                 case OP_FCONV_TO_R4:
5272                         /* FIXME: nothing to do ?? */
5273                         break;
5274                 case OP_FCONV_TO_I1:
5275                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5276                         break;
5277                 case OP_FCONV_TO_U1:
5278                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5279                         break;
5280                 case OP_FCONV_TO_I2:
5281                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5282                         break;
5283                 case OP_FCONV_TO_U2:
5284                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5285                         break;
5286                 case OP_FCONV_TO_U4:
5287                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5288                         break;
5289                 case OP_FCONV_TO_I4:
5290                 case OP_FCONV_TO_I:
5291                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5292                         break;
5293                 case OP_FCONV_TO_I8:
5294                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5295                         break;
5296                 case OP_LCONV_TO_R_UN: {
5297                         guint8 *br [2];
5298
5299                         /* Based on gcc code */
5300                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5301                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5302
5303                         /* Positive case */
5304                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5305                         br [1] = code; x86_jump8 (code, 0);
5306                         amd64_patch (br [0], code);
5307
5308                         /* Negative case */
5309                         /* Save to the red zone */
5310                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5311                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5312                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5313                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5314                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5315                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5316                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5317                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5318                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5319                         /* Restore */
5320                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5321                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5322                         amd64_patch (br [1], code);
5323                         break;
5324                 }
5325                 case OP_LCONV_TO_OVF_U4:
5326                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5327                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5328                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5329                         break;
5330                 case OP_LCONV_TO_OVF_I4_UN:
5331                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5332                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5333                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5334                         break;
5335                 case OP_FMOVE:
5336                         if (ins->dreg != ins->sreg1)
5337                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5338                         break;
5339                 case OP_FADD:
5340                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5341                         break;
5342                 case OP_FSUB:
5343                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5344                         break;
5345                 case OP_FMUL:
5346                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5347                         break;
5348                 case OP_FDIV:
5349                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5350                         break;
5351                 case OP_FNEG: {
5352                         static double r8_0 = -0.0;
5353
5354                         g_assert (ins->sreg1 == ins->dreg);
5355
5356                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5357                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5358                         break;
5359                 }
5360                 case OP_SIN:
5361                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5362                         break;
5363                 case OP_COS:
5364                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5365                         break;
5366                 case OP_ABS: {
5367                         static guint64 d = 0x7fffffffffffffffUL;
5368
5369                         g_assert (ins->sreg1 == ins->dreg);
5370
5371                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5372                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5373                         break;
5374                 }
5375                 case OP_SQRT:
5376                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5377                         break;
5378                 case OP_IMIN:
5379                         g_assert (cfg->opt & MONO_OPT_CMOV);
5380                         g_assert (ins->dreg == ins->sreg1);
5381                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5382                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5383                         break;
5384                 case OP_IMIN_UN:
5385                         g_assert (cfg->opt & MONO_OPT_CMOV);
5386                         g_assert (ins->dreg == ins->sreg1);
5387                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5388                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5389                         break;
5390                 case OP_IMAX:
5391                         g_assert (cfg->opt & MONO_OPT_CMOV);
5392                         g_assert (ins->dreg == ins->sreg1);
5393                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5394                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5395                         break;
5396                 case OP_IMAX_UN:
5397                         g_assert (cfg->opt & MONO_OPT_CMOV);
5398                         g_assert (ins->dreg == ins->sreg1);
5399                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5400                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5401                         break;
5402                 case OP_LMIN:
5403                         g_assert (cfg->opt & MONO_OPT_CMOV);
5404                         g_assert (ins->dreg == ins->sreg1);
5405                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5406                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5407                         break;
5408                 case OP_LMIN_UN:
5409                         g_assert (cfg->opt & MONO_OPT_CMOV);
5410                         g_assert (ins->dreg == ins->sreg1);
5411                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5412                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5413                         break;
5414                 case OP_LMAX:
5415                         g_assert (cfg->opt & MONO_OPT_CMOV);
5416                         g_assert (ins->dreg == ins->sreg1);
5417                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5418                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5419                         break;
5420                 case OP_LMAX_UN:
5421                         g_assert (cfg->opt & MONO_OPT_CMOV);
5422                         g_assert (ins->dreg == ins->sreg1);
5423                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5424                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5425                         break;
5426                 case OP_X86_FPOP:
5427                         break;
5428                 case OP_FCOMPARE:
5429                         /*
5430                          * The two arguments are swapped because the fbranch instructions
5431                          * depend on this for the non-sse case to work.
5432                          */
5433                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5434                         break;
5435                 case OP_FCNEQ:
5436                 case OP_FCEQ: {
5437                         /* zeroing the register at the start results in
5438                          * shorter and faster code (we can also remove the widening op)
5439                          */
5440                         guchar *unordered_check;
5441                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5442                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5443                         unordered_check = code;
5444                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5445
5446                         if (ins->opcode == OP_FCEQ) {
5447                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5448                                 amd64_patch (unordered_check, code);
5449                         } else {
5450                                 guchar *jump_to_end;
5451                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5452                                 jump_to_end = code;
5453                                 x86_jump8 (code, 0);
5454                                 amd64_patch (unordered_check, code);
5455                                 amd64_inc_reg (code, ins->dreg);
5456                                 amd64_patch (jump_to_end, code);
5457                         }
5458                         break;
5459                 }
5460                 case OP_FCLT:
5461                 case OP_FCLT_UN:
5462                         /* zeroing the register at the start results in
5463                          * shorter and faster code (we can also remove the widening op)
5464                          */
5465                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5466                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5467                         if (ins->opcode == OP_FCLT_UN) {
5468                                 guchar *unordered_check = code;
5469                                 guchar *jump_to_end;
5470                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5471                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5472                                 jump_to_end = code;
5473                                 x86_jump8 (code, 0);
5474                                 amd64_patch (unordered_check, code);
5475                                 amd64_inc_reg (code, ins->dreg);
5476                                 amd64_patch (jump_to_end, code);
5477                         } else {
5478                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5479                         }
5480                         break;
5481                 case OP_FCLE: {
5482                         guchar *unordered_check;
5483                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5484                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5485                         unordered_check = code;
5486                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5487                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5488                         amd64_patch (unordered_check, code);
5489                         break;
5490                 }
5491                 case OP_FCGT:
5492                 case OP_FCGT_UN: {
5493                         /* zeroing the register at the start results in
5494                          * shorter and faster code (we can also remove the widening op)
5495                          */
5496                         guchar *unordered_check;
5497                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5498                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5499                         if (ins->opcode == OP_FCGT) {
5500                                 unordered_check = code;
5501                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5502                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5503                                 amd64_patch (unordered_check, code);
5504                         } else {
5505                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5506                         }
5507                         break;
5508                 }
5509                 case OP_FCGE: {
5510                         guchar *unordered_check;
5511                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5512                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5513                         unordered_check = code;
5514                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5515                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5516                         amd64_patch (unordered_check, code);
5517                         break;
5518                 }
5519
5520                 case OP_FCLT_MEMBASE:
5521                 case OP_FCGT_MEMBASE:
5522                 case OP_FCLT_UN_MEMBASE:
5523                 case OP_FCGT_UN_MEMBASE:
5524                 case OP_FCEQ_MEMBASE: {
5525                         guchar *unordered_check, *jump_to_end;
5526                         int x86_cond;
5527
5528                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5529                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5530
5531                         switch (ins->opcode) {
5532                         case OP_FCEQ_MEMBASE:
5533                                 x86_cond = X86_CC_EQ;
5534                                 break;
5535                         case OP_FCLT_MEMBASE:
5536                         case OP_FCLT_UN_MEMBASE:
5537                                 x86_cond = X86_CC_LT;
5538                                 break;
5539                         case OP_FCGT_MEMBASE:
5540                         case OP_FCGT_UN_MEMBASE:
5541                                 x86_cond = X86_CC_GT;
5542                                 break;
5543                         default:
5544                                 g_assert_not_reached ();
5545                         }
5546
5547                         unordered_check = code;
5548                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5549                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5550
5551                         switch (ins->opcode) {
5552                         case OP_FCEQ_MEMBASE:
5553                         case OP_FCLT_MEMBASE:
5554                         case OP_FCGT_MEMBASE:
5555                                 amd64_patch (unordered_check, code);
5556                                 break;
5557                         case OP_FCLT_UN_MEMBASE:
5558                         case OP_FCGT_UN_MEMBASE:
5559                                 jump_to_end = code;
5560                                 x86_jump8 (code, 0);
5561                                 amd64_patch (unordered_check, code);
5562                                 amd64_inc_reg (code, ins->dreg);
5563                                 amd64_patch (jump_to_end, code);
5564                                 break;
5565                         default:
5566                                 break;
5567                         }
5568                         break;
5569                 }
5570                 case OP_FBEQ: {
5571                         guchar *jump = code;
5572                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5573                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5574                         amd64_patch (jump, code);
5575                         break;
5576                 }
5577                 case OP_FBNE_UN:
5578                         /* Branch if C013 != 100 */
5579                         /* branch if !ZF or (PF|CF) */
5580                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5581                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5582                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5583                         break;
5584                 case OP_FBLT:
5585                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5586                         break;
5587                 case OP_FBLT_UN:
5588                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5589                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5590                         break;
5591                 case OP_FBGT:
5592                 case OP_FBGT_UN:
5593                         if (ins->opcode == OP_FBGT) {
5594                                 guchar *br1;
5595
5596                                 /* skip branch if C1=1 */
5597                                 br1 = code;
5598                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5599                                 /* branch if (C0 | C3) = 1 */
5600                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5601                                 amd64_patch (br1, code);
5602                                 break;
5603                         } else {
5604                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5605                         }
5606                         break;
5607                 case OP_FBGE: {
5608                         /* Branch if C013 == 100 or 001 */
5609                         guchar *br1;
5610
5611                         /* skip branch if C1=1 */
5612                         br1 = code;
5613                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5614                         /* branch if (C0 | C3) = 1 */
5615                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5616                         amd64_patch (br1, code);
5617                         break;
5618                 }
5619                 case OP_FBGE_UN:
5620                         /* Branch if C013 == 000 */
5621                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5622                         break;
5623                 case OP_FBLE: {
5624                         /* Branch if C013=000 or 100 */
5625                         guchar *br1;
5626
5627                         /* skip branch if C1=1 */
5628                         br1 = code;
5629                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5630                         /* branch if C0=0 */
5631                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5632                         amd64_patch (br1, code);
5633                         break;
5634                 }
5635                 case OP_FBLE_UN:
5636                         /* Branch if C013 != 001 */
5637                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5638                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5639                         break;
5640                 case OP_CKFINITE:
5641                         /* Transfer value to the fp stack */
5642                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5643                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5644                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5645
5646                         amd64_push_reg (code, AMD64_RAX);
5647                         amd64_fxam (code);
5648                         amd64_fnstsw (code);
5649                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5650                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5651                         amd64_pop_reg (code, AMD64_RAX);
5652                         amd64_fstp (code, 0);
5653                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5654                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5655                         break;
5656                 case OP_TLS_GET: {
5657                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5658                         break;
5659                 }
5660                 case OP_TLS_GET_REG:
5661                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5662                         break;
5663                 case OP_TLS_SET: {
5664                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5665                         break;
5666                 }
5667                 case OP_TLS_SET_REG: {
5668                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5669                         break;
5670                 }
5671                 case OP_MEMORY_BARRIER: {
5672                         switch (ins->backend.memory_barrier_kind) {
5673                         case StoreLoadBarrier:
5674                         case FullBarrier:
5675                                 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5676                                 x86_prefix (code, X86_LOCK_PREFIX);
5677                                 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5678                                 break;
5679                         }
5680                         break;
5681                 }
5682                 case OP_ATOMIC_ADD_I4:
5683                 case OP_ATOMIC_ADD_I8: {
5684                         int dreg = ins->dreg;
5685                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5686
5687                         if (dreg == ins->inst_basereg)
5688                                 dreg = AMD64_R11;
5689
5690                         if (dreg != ins->sreg2)
5691                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5692
5693                         x86_prefix (code, X86_LOCK_PREFIX);
5694                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5695
5696                         if (dreg != ins->dreg)
5697                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5698
5699                         break;
5700                 }
5701                 case OP_ATOMIC_ADD_NEW_I4:
5702                 case OP_ATOMIC_ADD_NEW_I8: {
5703                         int dreg = ins->dreg;
5704                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
5705
5706                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5707                                 dreg = AMD64_R11;
5708
5709                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5710                         amd64_prefix (code, X86_LOCK_PREFIX);
5711                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5712                         /* dreg contains the old value, add with sreg2 value */
5713                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5714
5715                         if (ins->dreg != dreg)
5716                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5717
5718                         break;
5719                 }
5720                 case OP_ATOMIC_EXCHANGE_I4:
5721                 case OP_ATOMIC_EXCHANGE_I8: {
5722                         guchar *br[2];
5723                         int sreg2 = ins->sreg2;
5724                         int breg = ins->inst_basereg;
5725                         guint32 size;
5726                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5727
5728                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5729                                 size = 8;
5730                         else
5731                                 size = 4;
5732
5733                         /*
5734                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5735                          * an explanation of how this works.
5736                          */
5737
5738                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5739                          * hack to overcome limits in x86 reg allocator
5740                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5741                          */
5742                         g_assert (ins->dreg == AMD64_RAX);
5743
5744                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5745                                 /* Highly unlikely, but possible */
5746                                 need_push = TRUE;
5747
5748                         /* The pushes invalidate rsp */
5749                         if ((breg == AMD64_RAX) || need_push) {
5750                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5751                                 breg = AMD64_R11;
5752                         }
5753
5754                         /* We need the EAX reg for the comparand */
5755                         if (ins->sreg2 == AMD64_RAX) {
5756                                 if (breg != AMD64_R11) {
5757                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5758                                         sreg2 = AMD64_R11;
5759                                 } else {
5760                                         g_assert (need_push);
5761                                         amd64_push_reg (code, AMD64_RDX);
5762                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5763                                         sreg2 = AMD64_RDX;
5764                                         rdx_pushed = TRUE;
5765                                 }
5766                         }
5767
5768                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5769
5770                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5771                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5772                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5773                         amd64_patch (br [1], br [0]);
5774
5775                         if (rdx_pushed)
5776                                 amd64_pop_reg (code, AMD64_RDX);
5777
5778                         break;
5779                 }
5780                 case OP_ATOMIC_CAS_I4:
5781                 case OP_ATOMIC_CAS_I8: {
5782                         guint32 size;
5783
5784                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5785                                 size = 8;
5786                         else
5787                                 size = 4;
5788
5789                         /*
5790                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5791                          * an explanation of how this works.
5792                          */
5793                         g_assert (ins->sreg3 == AMD64_RAX);
5794                         g_assert (ins->sreg1 != AMD64_RAX);
5795                         g_assert (ins->sreg1 != ins->sreg2);
5796
5797                         amd64_prefix (code, X86_LOCK_PREFIX);
5798                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5799
5800                         if (ins->dreg != AMD64_RAX)
5801                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5802                         break;
5803                 }
5804                 case OP_CARD_TABLE_WBARRIER: {
5805                         int ptr = ins->sreg1;
5806                         int value = ins->sreg2;
5807                         guchar *br = 0;
5808                         int nursery_shift, card_table_shift;
5809                         gpointer card_table_mask;
5810                         size_t nursery_size;
5811
5812                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5813                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5814                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5815
5816                         /*If either point to the stack we can simply avoid the WB. This happens due to
5817                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5818                          */
5819                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5820                                 continue;
5821
5822                         /*
5823                          * We need one register we can clobber, we choose EDX and make sreg1
5824                          * fixed EAX to work around limitations in the local register allocator.
5825                          * sreg2 might get allocated to EDX, but that is not a problem since
5826                          * we use it before clobbering EDX.
5827                          */
5828                         g_assert (ins->sreg1 == AMD64_RAX);
5829
5830                         /*
5831                          * This is the code we produce:
5832                          *
5833                          *   edx = value
5834                          *   edx >>= nursery_shift
5835                          *   cmp edx, (nursery_start >> nursery_shift)
5836                          *   jne done
5837                          *   edx = ptr
5838                          *   edx >>= card_table_shift
5839                          *   edx += cardtable
5840                          *   [edx] = 1
5841                          * done:
5842                          */
5843
5844                         if (mono_gc_card_table_nursery_check ()) {
5845                                 if (value != AMD64_RDX)
5846                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5847                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5848                                 if (shifted_nursery_start >> 31) {
5849                                         /*
5850                                          * The value we need to compare against is 64 bits, so we need
5851                                          * another spare register.  We use RBX, which we save and
5852                                          * restore.
5853                                          */
5854                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5855                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5856                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5857                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5858                                 } else {
5859                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5860                                 }
5861                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5862                         }
5863                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5864                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5865                         if (card_table_mask)
5866                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5867
5868                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5869                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5870
5871                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5872
5873                         if (mono_gc_card_table_nursery_check ())
5874                                 x86_patch (br, code);
5875                         break;
5876                 }
5877 #ifdef MONO_ARCH_SIMD_INTRINSICS
5878                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5879                 case OP_ADDPS:
5880                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5881                         break;
5882                 case OP_DIVPS:
5883                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5884                         break;
5885                 case OP_MULPS:
5886                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5887                         break;
5888                 case OP_SUBPS:
5889                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5890                         break;
5891                 case OP_MAXPS:
5892                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5893                         break;
5894                 case OP_MINPS:
5895                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5896                         break;
5897                 case OP_COMPPS:
5898                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5899                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5900                         break;
5901                 case OP_ANDPS:
5902                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904                 case OP_ANDNPS:
5905                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5906                         break;
5907                 case OP_ORPS:
5908                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910                 case OP_XORPS:
5911                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5912                         break;
5913                 case OP_SQRTPS:
5914                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5915                         break;
5916                 case OP_RSQRTPS:
5917                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5918                         break;
5919                 case OP_RCPPS:
5920                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5921                         break;
5922                 case OP_ADDSUBPS:
5923                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5924                         break;
5925                 case OP_HADDPS:
5926                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5927                         break;
5928                 case OP_HSUBPS:
5929                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5930                         break;
5931                 case OP_DUPPS_HIGH:
5932                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5933                         break;
5934                 case OP_DUPPS_LOW:
5935                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5936                         break;
5937
5938                 case OP_PSHUFLEW_HIGH:
5939                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5940                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5941                         break;
5942                 case OP_PSHUFLEW_LOW:
5943                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5944                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5945                         break;
5946                 case OP_PSHUFLED:
5947                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5948                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5949                         break;
5950                 case OP_SHUFPS:
5951                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5952                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5953                         break;
5954                 case OP_SHUFPD:
5955                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5956                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5957                         break;
5958
5959                 case OP_ADDPD:
5960                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5961                         break;
5962                 case OP_DIVPD:
5963                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5964                         break;
5965                 case OP_MULPD:
5966                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5967                         break;
5968                 case OP_SUBPD:
5969                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5970                         break;
5971                 case OP_MAXPD:
5972                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5973                         break;
5974                 case OP_MINPD:
5975                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5976                         break;
5977                 case OP_COMPPD:
5978                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5979                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5980                         break;
5981                 case OP_ANDPD:
5982                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984                 case OP_ANDNPD:
5985                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5986                         break;
5987                 case OP_ORPD:
5988                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5989                         break;
5990                 case OP_XORPD:
5991                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5992                         break;
5993                 case OP_SQRTPD:
5994                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5995                         break;
5996                 case OP_ADDSUBPD:
5997                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5998                         break;
5999                 case OP_HADDPD:
6000                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_HSUBPD:
6003                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005                 case OP_DUPPD:
6006                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6007                         break;
6008
6009                 case OP_EXTRACT_MASK:
6010                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6011                         break;
6012
6013                 case OP_PAND:
6014                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6015                         break;
6016                 case OP_POR:
6017                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6018                         break;
6019                 case OP_PXOR:
6020                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6021                         break;
6022
6023                 case OP_PADDB:
6024                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6025                         break;
6026                 case OP_PADDW:
6027                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6028                         break;
6029                 case OP_PADDD:
6030                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_PADDQ:
6033                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035
6036                 case OP_PSUBB:
6037                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6038                         break;
6039                 case OP_PSUBW:
6040                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6041                         break;
6042                 case OP_PSUBD:
6043                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6044                         break;
6045                 case OP_PSUBQ:
6046                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6047                         break;
6048
6049                 case OP_PMAXB_UN:
6050                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6051                         break;
6052                 case OP_PMAXW_UN:
6053                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6054                         break;
6055                 case OP_PMAXD_UN:
6056                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6057                         break;
6058
6059                 case OP_PMAXB:
6060                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062                 case OP_PMAXW:
6063                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6064                         break;
6065                 case OP_PMAXD:
6066                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6067                         break;
6068
6069                 case OP_PAVGB_UN:
6070                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6071                         break;
6072                 case OP_PAVGW_UN:
6073                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6074                         break;
6075
6076                 case OP_PMINB_UN:
6077                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079                 case OP_PMINW_UN:
6080                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082                 case OP_PMIND_UN:
6083                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6084                         break;
6085
6086                 case OP_PMINB:
6087                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089                 case OP_PMINW:
6090                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_PMIND:
6093                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095
6096                 case OP_PCMPEQB:
6097                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099                 case OP_PCMPEQW:
6100                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102                 case OP_PCMPEQD:
6103                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_PCMPEQQ:
6106                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108
6109                 case OP_PCMPGTB:
6110                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_PCMPGTW:
6113                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_PCMPGTD:
6116                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118                 case OP_PCMPGTQ:
6119                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121
6122                 case OP_PSUM_ABS_DIFF:
6123                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6124                         break;
6125
6126                 case OP_UNPACK_LOWB:
6127                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129                 case OP_UNPACK_LOWW:
6130                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6131                         break;
6132                 case OP_UNPACK_LOWD:
6133                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6134                         break;
6135                 case OP_UNPACK_LOWQ:
6136                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6137                         break;
6138                 case OP_UNPACK_LOWPS:
6139                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6140                         break;
6141                 case OP_UNPACK_LOWPD:
6142                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6143                         break;
6144
6145                 case OP_UNPACK_HIGHB:
6146                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148                 case OP_UNPACK_HIGHW:
6149                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6150                         break;
6151                 case OP_UNPACK_HIGHD:
6152                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6153                         break;
6154                 case OP_UNPACK_HIGHQ:
6155                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6156                         break;
6157                 case OP_UNPACK_HIGHPS:
6158                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6159                         break;
6160                 case OP_UNPACK_HIGHPD:
6161                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6162                         break;
6163
6164                 case OP_PACKW:
6165                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6166                         break;
6167                 case OP_PACKD:
6168                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6169                         break;
6170                 case OP_PACKW_UN:
6171                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6172                         break;
6173                 case OP_PACKD_UN:
6174                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6175                         break;
6176
6177                 case OP_PADDB_SAT_UN:
6178                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6179                         break;
6180                 case OP_PSUBB_SAT_UN:
6181                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6182                         break;
6183                 case OP_PADDW_SAT_UN:
6184                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6185                         break;
6186                 case OP_PSUBW_SAT_UN:
6187                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6188                         break;
6189
6190                 case OP_PADDB_SAT:
6191                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6192                         break;
6193                 case OP_PSUBB_SAT:
6194                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6195                         break;
6196                 case OP_PADDW_SAT:
6197                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6198                         break;
6199                 case OP_PSUBW_SAT:
6200                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6201                         break;
6202
6203                 case OP_PMULW:
6204                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6205                         break;
6206                 case OP_PMULD:
6207                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6208                         break;
6209                 case OP_PMULQ:
6210                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6211                         break;
6212                 case OP_PMULW_HIGH_UN:
6213                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6214                         break;
6215                 case OP_PMULW_HIGH:
6216                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6217                         break;
6218
6219                 case OP_PSHRW:
6220                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6221                         break;
6222                 case OP_PSHRW_REG:
6223                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6224                         break;
6225
6226                 case OP_PSARW:
6227                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6228                         break;
6229                 case OP_PSARW_REG:
6230                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6231                         break;
6232
6233                 case OP_PSHLW:
6234                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6235                         break;
6236                 case OP_PSHLW_REG:
6237                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6238                         break;
6239
6240                 case OP_PSHRD:
6241                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6242                         break;
6243                 case OP_PSHRD_REG:
6244                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6245                         break;
6246
6247                 case OP_PSARD:
6248                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6249                         break;
6250                 case OP_PSARD_REG:
6251                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6252                         break;
6253
6254                 case OP_PSHLD:
6255                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6256                         break;
6257                 case OP_PSHLD_REG:
6258                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6259                         break;
6260
6261                 case OP_PSHRQ:
6262                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6263                         break;
6264                 case OP_PSHRQ_REG:
6265                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6266                         break;
6267
6268                 /*TODO: This is appart of the sse spec but not added
6269                 case OP_PSARQ:
6270                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6271                         break;
6272                 case OP_PSARQ_REG:
6273                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6274                         break;
6275                 */
6276
6277                 case OP_PSHLQ:
6278                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6279                         break;
6280                 case OP_PSHLQ_REG:
6281                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6282                         break;
6283                 case OP_CVTDQ2PD:
6284                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6285                         break;
6286                 case OP_CVTDQ2PS:
6287                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6288                         break;
6289                 case OP_CVTPD2DQ:
6290                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6291                         break;
6292                 case OP_CVTPD2PS:
6293                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6294                         break;
6295                 case OP_CVTPS2DQ:
6296                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6297                         break;
6298                 case OP_CVTPS2PD:
6299                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6300                         break;
6301                 case OP_CVTTPD2DQ:
6302                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6303                         break;
6304                 case OP_CVTTPS2DQ:
6305                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6306                         break;
6307
6308                 case OP_ICONV_TO_X:
6309                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6310                         break;
6311                 case OP_EXTRACT_I4:
6312                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6313                         break;
6314                 case OP_EXTRACT_I8:
6315                         if (ins->inst_c0) {
6316                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6317                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6318                         } else {
6319                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6320                         }
6321                         break;
6322                 case OP_EXTRACT_I1:
6323                 case OP_EXTRACT_U1:
6324                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6325                         if (ins->inst_c0)
6326                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6327                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6328                         break;
6329                 case OP_EXTRACT_I2:
6330                 case OP_EXTRACT_U2:
6331                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6332                         if (ins->inst_c0)
6333                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6334                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6335                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6336                         break;
6337                 case OP_EXTRACT_R8:
6338                         if (ins->inst_c0)
6339                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6340                         else
6341                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6342                         break;
6343                 case OP_INSERT_I2:
6344                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6345                         break;
6346                 case OP_EXTRACTX_U2:
6347                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6348                         break;
6349                 case OP_INSERTX_U1_SLOW:
6350                         /*sreg1 is the extracted ireg (scratch)
6351                         /sreg2 is the to be inserted ireg (scratch)
6352                         /dreg is the xreg to receive the value*/
6353
6354                         /*clear the bits from the extracted word*/
6355                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6356                         /*shift the value to insert if needed*/
6357                         if (ins->inst_c0 & 1)
6358                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6359                         /*join them together*/
6360                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6361                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6362                         break;
6363                 case OP_INSERTX_I4_SLOW:
6364                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6365                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6366                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6367                         break;
6368                 case OP_INSERTX_I8_SLOW:
6369                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6370                         if (ins->inst_c0)
6371                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6372                         else
6373                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6374                         break;
6375
6376                 case OP_INSERTX_R4_SLOW:
6377                         switch (ins->inst_c0) {
6378                         case 0:
6379                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6380                                 break;
6381                         case 1:
6382                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6383                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6384                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6385                                 break;
6386                         case 2:
6387                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6388                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6389                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6390                                 break;
6391                         case 3:
6392                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6393                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6394                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6395                                 break;
6396                         }
6397                         break;
6398                 case OP_INSERTX_R8_SLOW:
6399                         if (ins->inst_c0)
6400                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6401                         else
6402                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6403                         break;
6404                 case OP_STOREX_MEMBASE_REG:
6405                 case OP_STOREX_MEMBASE:
6406                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6407                         break;
6408                 case OP_LOADX_MEMBASE:
6409                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6410                         break;
6411                 case OP_LOADX_ALIGNED_MEMBASE:
6412                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6413                         break;
6414                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6415                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6416                         break;
6417                 case OP_STOREX_NTA_MEMBASE_REG:
6418                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6419                         break;
6420                 case OP_PREFETCH_MEMBASE:
6421                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6422                         break;
6423
6424                 case OP_XMOVE:
6425                         /*FIXME the peephole pass should have killed this*/
6426                         if (ins->dreg != ins->sreg1)
6427                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6428                         break;
6429                 case OP_XZERO:
6430                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6431                         break;
6432                 case OP_ICONV_TO_R8_RAW:
6433                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6434                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6435                         break;
6436
6437                 case OP_FCONV_TO_R8_X:
6438                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6439                         break;
6440
6441                 case OP_XCONV_R8_TO_I4:
6442                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6443                         switch (ins->backend.source_opcode) {
6444                         case OP_FCONV_TO_I1:
6445                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6446                                 break;
6447                         case OP_FCONV_TO_U1:
6448                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6449                                 break;
6450                         case OP_FCONV_TO_I2:
6451                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6452                                 break;
6453                         case OP_FCONV_TO_U2:
6454                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6455                                 break;
6456                         }
6457                         break;
6458
6459                 case OP_EXPAND_I2:
6460                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6461                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6462                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6463                         break;
6464                 case OP_EXPAND_I4:
6465                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6466                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6467                         break;
6468                 case OP_EXPAND_I8:
6469                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6470                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6471                         break;
6472                 case OP_EXPAND_R4:
6473                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6474                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6475                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6476                         break;
6477                 case OP_EXPAND_R8:
6478                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6479                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6480                         break;
6481 #endif
6482                 case OP_LIVERANGE_START: {
6483                         if (cfg->verbose_level > 1)
6484                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6485                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6486                         break;
6487                 }
6488                 case OP_LIVERANGE_END: {
6489                         if (cfg->verbose_level > 1)
6490                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6491                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6492                         break;
6493                 }
6494                 case OP_NACL_GC_SAFE_POINT: {
6495 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6496                         if (cfg->compile_aot)
6497                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6498                         else {
6499                                 guint8 *br [1];
6500
6501                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6502                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6503                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6504                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6505                                 amd64_patch (br[0], code);
6506                         }
6507 #endif
6508                         break;
6509                 }
6510                 case OP_GC_LIVENESS_DEF:
6511                 case OP_GC_LIVENESS_USE:
6512                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6513                         ins->backend.pc_offset = code - cfg->native_code;
6514                         break;
6515                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6516                         ins->backend.pc_offset = code - cfg->native_code;
6517                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6518                         break;
6519                 default:
6520                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6521                         g_assert_not_reached ();
6522                 }
6523
6524                 if ((code - cfg->native_code - offset) > max_len) {
6525 #if !defined(__native_client_codegen__)
6526                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6527                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6528                         g_assert_not_reached ();
6529 #endif
6530                 }
6531
6532                 last_ins = ins;
6533                 last_offset = offset;
6534         }
6535
6536         cfg->code_len = code - cfg->native_code;
6537 }
6538
6539 #endif /* DISABLE_JIT */
6540
6541 void
6542 mono_arch_register_lowlevel_calls (void)
6543 {
6544         /* The signature doesn't matter */
6545         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6546 }
6547
6548 void
6549 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6550 {
6551         MonoJumpInfo *patch_info;
6552         gboolean compile_aot = !run_cctors;
6553
6554         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6555                 unsigned char *ip = patch_info->ip.i + code;
6556                 unsigned char *target;
6557
6558                 if (compile_aot) {
6559                         switch (patch_info->type) {
6560                         case MONO_PATCH_INFO_BB:
6561                         case MONO_PATCH_INFO_LABEL:
6562                                 break;
6563                         default:
6564                                 /* No need to patch these */
6565                                 continue;
6566                         }
6567                 }
6568
6569                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6570
6571                 switch (patch_info->type) {
6572                 case MONO_PATCH_INFO_NONE:
6573                         continue;
6574                 case MONO_PATCH_INFO_METHOD_REL:
6575                 case MONO_PATCH_INFO_R8:
6576                 case MONO_PATCH_INFO_R4:
6577                         g_assert_not_reached ();
6578                         continue;
6579                 case MONO_PATCH_INFO_BB:
6580                         break;
6581                 default:
6582                         break;
6583                 }
6584
6585                 /*
6586                  * Debug code to help track down problems where the target of a near call is
6587                  * is not valid.
6588                  */
6589                 if (amd64_is_near_call (ip)) {
6590                         gint64 disp = (guint8*)target - (guint8*)ip;
6591
6592                         if (!amd64_is_imm32 (disp)) {
6593                                 printf ("TYPE: %d\n", patch_info->type);
6594                                 switch (patch_info->type) {
6595                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6596                                         printf ("V: %s\n", patch_info->data.name);
6597                                         break;
6598                                 case MONO_PATCH_INFO_METHOD_JUMP:
6599                                 case MONO_PATCH_INFO_METHOD:
6600                                         printf ("V: %s\n", patch_info->data.method->name);
6601                                         break;
6602                                 default:
6603                                         break;
6604                                 }
6605                         }
6606                 }
6607
6608                 amd64_patch (ip, (gpointer)target);
6609         }
6610 }
6611
6612 #ifndef DISABLE_JIT
6613
6614 static int
6615 get_max_epilog_size (MonoCompile *cfg)
6616 {
6617         int max_epilog_size = 16;
6618
6619         if (cfg->method->save_lmf)
6620                 max_epilog_size += 256;
6621
6622         if (mono_jit_trace_calls != NULL)
6623                 max_epilog_size += 50;
6624
6625         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6626                 max_epilog_size += 50;
6627
6628         max_epilog_size += (AMD64_NREG * 2);
6629
6630         return max_epilog_size;
6631 }
6632
6633 /*
6634  * This macro is used for testing whenever the unwinder works correctly at every point
6635  * where an async exception can happen.
6636  */
6637 /* This will generate a SIGSEGV at the given point in the code */
6638 #define async_exc_point(code) do { \
6639     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6640          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6641              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6642          cfg->arch.async_point_count ++; \
6643     } \
6644 } while (0)
6645
6646 guint8 *
6647 mono_arch_emit_prolog (MonoCompile *cfg)
6648 {
6649         MonoMethod *method = cfg->method;
6650         MonoBasicBlock *bb;
6651         MonoMethodSignature *sig;
6652         MonoInst *ins;
6653         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6654         guint8 *code;
6655         CallInfo *cinfo;
6656         MonoInst *lmf_var = cfg->lmf_var;
6657         gboolean args_clobbered = FALSE;
6658         gboolean trace = FALSE;
6659 #ifdef __native_client_codegen__
6660         guint alignment_check;
6661 #endif
6662
6663         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
6664
6665 #if defined(__default_codegen__)
6666         code = cfg->native_code = g_malloc (cfg->code_size);
6667 #elif defined(__native_client_codegen__)
6668         /* native_code_alloc is not 32-byte aligned, native_code is. */
6669         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6670
6671         /* Align native_code to next nearest kNaclAlignment byte. */
6672         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6673         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6674
6675         code = cfg->native_code;
6676
6677         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6678         g_assert (alignment_check == 0);
6679 #endif
6680
6681         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6682                 trace = TRUE;
6683
6684         /* Amount of stack space allocated by register saving code */
6685         pos = 0;
6686
6687         /* Offset between RSP and the CFA */
6688         cfa_offset = 0;
6689
6690         /*
6691          * The prolog consists of the following parts:
6692          * FP present:
6693          * - push rbp, mov rbp, rsp
6694          * - save callee saved regs using pushes
6695          * - allocate frame
6696          * - save rgctx if needed
6697          * - save lmf if needed
6698          * FP not present:
6699          * - allocate frame
6700          * - save rgctx if needed
6701          * - save lmf if needed
6702          * - save callee saved regs using moves
6703          */
6704
6705         // CFA = sp + 8
6706         cfa_offset = 8;
6707         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6708         // IP saved at CFA - 8
6709         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6710         async_exc_point (code);
6711         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6712
6713         if (!cfg->arch.omit_fp) {
6714                 amd64_push_reg (code, AMD64_RBP);
6715                 cfa_offset += 8;
6716                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6717                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6718                 async_exc_point (code);
6719 #ifdef HOST_WIN32
6720                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6721 #endif
6722                 /* These are handled automatically by the stack marking code */
6723                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6724
6725                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6726                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6727                 async_exc_point (code);
6728 #ifdef HOST_WIN32
6729                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6730 #endif
6731         }
6732
6733         /* The param area is always at offset 0 from sp */
6734         /* This needs to be allocated here, since it has to come after the spill area */
6735         if (cfg->arch.no_pushes && cfg->param_area) {
6736                 if (cfg->arch.omit_fp)
6737                         // FIXME:
6738                         g_assert_not_reached ();
6739                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6740         }
6741
6742         if (cfg->arch.omit_fp) {
6743                 /*
6744                  * On enter, the stack is misaligned by the pushing of the return
6745                  * address. It is either made aligned by the pushing of %rbp, or by
6746                  * this.
6747                  */
6748                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6749                 if ((alloc_size % 16) == 0) {
6750                         alloc_size += 8;
6751                         /* Mark the padding slot as NOREF */
6752                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6753                 }
6754         } else {
6755                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6756                 if (cfg->stack_offset != alloc_size) {
6757                         /* Mark the padding slot as NOREF */
6758                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6759                 }
6760                 cfg->arch.sp_fp_offset = alloc_size;
6761                 alloc_size -= pos;
6762         }
6763
6764         cfg->arch.stack_alloc_size = alloc_size;
6765
6766         /* Allocate stack frame */
6767         if (alloc_size) {
6768                 /* See mono_emit_stack_alloc */
6769 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6770                 guint32 remaining_size = alloc_size;
6771                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6772                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6773                 guint32 offset = code - cfg->native_code;
6774                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6775                         while (required_code_size >= (cfg->code_size - offset))
6776                                 cfg->code_size *= 2;
6777                         cfg->native_code = mono_realloc_native_code (cfg);
6778                         code = cfg->native_code + offset;
6779                         cfg->stat_code_reallocs++;
6780                 }
6781
6782                 while (remaining_size >= 0x1000) {
6783                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6784                         if (cfg->arch.omit_fp) {
6785                                 cfa_offset += 0x1000;
6786                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6787                         }
6788                         async_exc_point (code);
6789 #ifdef HOST_WIN32
6790                         if (cfg->arch.omit_fp)
6791                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6792 #endif
6793
6794                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6795                         remaining_size -= 0x1000;
6796                 }
6797                 if (remaining_size) {
6798                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6799                         if (cfg->arch.omit_fp) {
6800                                 cfa_offset += remaining_size;
6801                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6802                                 async_exc_point (code);
6803                         }
6804 #ifdef HOST_WIN32
6805                         if (cfg->arch.omit_fp)
6806                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6807 #endif
6808                 }
6809 #else
6810                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6811                 if (cfg->arch.omit_fp) {
6812                         cfa_offset += alloc_size;
6813                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6814                         async_exc_point (code);
6815                 }
6816 #endif
6817         }
6818
6819         /* Stack alignment check */
6820 #if 0
6821         {
6822                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6823                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6824                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6825                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6826                 amd64_breakpoint (code);
6827         }
6828 #endif
6829
6830 #ifndef TARGET_WIN32
6831         if (mini_get_debug_options ()->init_stacks) {
6832                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6833
6834                 /* Save registers to the red zone */
6835                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6836                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6837
6838                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6839                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6840                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6841
6842                 amd64_cld (code);
6843 #if defined(__default_codegen__)
6844                 amd64_prefix (code, X86_REP_PREFIX);
6845                 amd64_stosl (code);
6846 #elif defined(__native_client_codegen__)
6847                 /* NaCl stos pseudo-instruction */
6848                 amd64_codegen_pre (code);
6849                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6850                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6851                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6852                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6853                 amd64_prefix (code, X86_REP_PREFIX);
6854                 amd64_stosl (code);
6855                 amd64_codegen_post (code);
6856 #endif /* __native_client_codegen__ */
6857
6858                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6859                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6860         }
6861 #endif
6862
6863         /* Save LMF */
6864         if (method->save_lmf) {
6865                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6866         }
6867
6868         /* Save callee saved registers */
6869         if (!method->save_lmf) {
6870                 gint32 save_area_offset;
6871
6872                 if (cfg->arch.omit_fp) {
6873                         save_area_offset = cfg->arch.reg_save_area_offset;
6874                         /* Save caller saved registers after sp is adjusted */
6875                         /* The registers are saved at the bottom of the frame */
6876                         /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6877                 } else {
6878                         /* The registers are saved just below the saved rbp */
6879                         save_area_offset = cfg->arch.reg_save_area_offset;
6880                 }
6881
6882                 for (i = 0; i < AMD64_NREG; ++i)
6883                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6884                                 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6885
6886                                 if (cfg->arch.omit_fp) {
6887                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6888                                         /* These are handled automatically by the stack marking code */
6889                                         mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6890                                 } else {
6891                                         mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6892                                         // FIXME: GC
6893                                 }
6894
6895                                 save_area_offset += 8;
6896                                 async_exc_point (code);
6897                         }
6898         }
6899
6900         /* store runtime generic context */
6901         if (cfg->rgctx_var) {
6902                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6903                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6904
6905                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6906
6907                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6908                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6909         }
6910
6911         /* compute max_length in order to use short forward jumps */
6912         max_epilog_size = get_max_epilog_size (cfg);
6913         if (cfg->opt & MONO_OPT_BRANCH) {
6914                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6915                         MonoInst *ins;
6916                         int max_length = 0;
6917
6918                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6919                                 max_length += 6;
6920                         /* max alignment for loops */
6921                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6922                                 max_length += LOOP_ALIGNMENT;
6923 #ifdef __native_client_codegen__
6924                         /* max alignment for native client */
6925                         max_length += kNaClAlignment;
6926 #endif
6927
6928                         MONO_BB_FOR_EACH_INS (bb, ins) {
6929 #ifdef __native_client_codegen__
6930                                 {
6931                                         int space_in_block = kNaClAlignment -
6932                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6933                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6934                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6935                                                 max_length += space_in_block;
6936                                         }
6937                                 }
6938 #endif  /*__native_client_codegen__*/
6939                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6940                         }
6941
6942                         /* Take prolog and epilog instrumentation into account */
6943                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6944                                 max_length += max_epilog_size;
6945
6946                         bb->max_length = max_length;
6947                 }
6948         }
6949
6950         sig = mono_method_signature (method);
6951         pos = 0;
6952
6953         cinfo = cfg->arch.cinfo;
6954
6955         if (sig->ret->type != MONO_TYPE_VOID) {
6956                 /* Save volatile arguments to the stack */
6957                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6958                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6959         }
6960
6961         /* Keep this in sync with emit_load_volatile_arguments */
6962         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6963                 ArgInfo *ainfo = cinfo->args + i;
6964                 gint32 stack_offset;
6965                 MonoType *arg_type;
6966
6967                 ins = cfg->args [i];
6968
6969                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6970                         /* Unused arguments */
6971                         continue;
6972
6973                 if (sig->hasthis && (i == 0))
6974                         arg_type = &mono_defaults.object_class->byval_arg;
6975                 else
6976                         arg_type = sig->params [i - sig->hasthis];
6977
6978                 stack_offset = ainfo->offset + ARGS_OFFSET;
6979
6980                 if (cfg->globalra) {
6981                         /* All the other moves are done by the register allocator */
6982                         switch (ainfo->storage) {
6983                         case ArgInFloatSSEReg:
6984                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6985                                 break;
6986                         case ArgValuetypeInReg:
6987                                 for (quad = 0; quad < 2; quad ++) {
6988                                         switch (ainfo->pair_storage [quad]) {
6989                                         case ArgInIReg:
6990                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6991                                                 break;
6992                                         case ArgInFloatSSEReg:
6993                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6994                                                 break;
6995                                         case ArgInDoubleSSEReg:
6996                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6997                                                 break;
6998                                         case ArgNone:
6999                                                 break;
7000                                         default:
7001                                                 g_assert_not_reached ();
7002                                         }
7003                                 }
7004                                 break;
7005                         default:
7006                                 break;
7007                         }
7008
7009                         continue;
7010                 }
7011
7012                 /* Save volatile arguments to the stack */
7013                 if (ins->opcode != OP_REGVAR) {
7014                         switch (ainfo->storage) {
7015                         case ArgInIReg: {
7016                                 guint32 size = 8;
7017
7018                                 /* FIXME: I1 etc */
7019                                 /*
7020                                 if (stack_offset & 0x1)
7021                                         size = 1;
7022                                 else if (stack_offset & 0x2)
7023                                         size = 2;
7024                                 else if (stack_offset & 0x4)
7025                                         size = 4;
7026                                 else
7027                                         size = 8;
7028                                 */
7029                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7030
7031                                 /*
7032                                  * Save the original location of 'this',
7033                                  * get_generic_info_from_stack_frame () needs this to properly look up
7034                                  * the argument value during the handling of async exceptions.
7035                                  */
7036                                 if (ins == cfg->args [0]) {
7037                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7038                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7039                                 }
7040                                 break;
7041                         }
7042                         case ArgInFloatSSEReg:
7043                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7044                                 break;
7045                         case ArgInDoubleSSEReg:
7046                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7047                                 break;
7048                         case ArgValuetypeInReg:
7049                                 for (quad = 0; quad < 2; quad ++) {
7050                                         switch (ainfo->pair_storage [quad]) {
7051                                         case ArgInIReg:
7052                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7053                                                 break;
7054                                         case ArgInFloatSSEReg:
7055                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7056                                                 break;
7057                                         case ArgInDoubleSSEReg:
7058                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7059                                                 break;
7060                                         case ArgNone:
7061                                                 break;
7062                                         default:
7063                                                 g_assert_not_reached ();
7064                                         }
7065                                 }
7066                                 break;
7067                         case ArgValuetypeAddrInIReg:
7068                                 if (ainfo->pair_storage [0] == ArgInIReg)
7069                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7070                                 break;
7071                         default:
7072                                 break;
7073                         }
7074                 } else {
7075                         /* Argument allocated to (non-volatile) register */
7076                         switch (ainfo->storage) {
7077                         case ArgInIReg:
7078                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7079                                 break;
7080                         case ArgOnStack:
7081                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7082                                 break;
7083                         default:
7084                                 g_assert_not_reached ();
7085                         }
7086
7087                         if (ins == cfg->args [0]) {
7088                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7089                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7090                         }
7091                 }
7092         }
7093
7094 #ifdef HOST_WIN32
7095         if (method->save_lmf) {
7096                 code = emit_push_lmf (cfg, code, lmf_var->inst_offset, &args_clobbered);
7097         }
7098 #else
7099         args_clobbered = TRUE;
7100 #endif
7101
7102         if (trace) {
7103                 args_clobbered = TRUE;
7104                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7105         }
7106
7107         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7108                 args_clobbered = TRUE;
7109
7110         /*
7111          * Optimize the common case of the first bblock making a call with the same
7112          * arguments as the method. This works because the arguments are still in their
7113          * original argument registers.
7114          * FIXME: Generalize this
7115          */
7116         if (!args_clobbered) {
7117                 MonoBasicBlock *first_bb = cfg->bb_entry;
7118                 MonoInst *next;
7119
7120                 next = mono_bb_first_ins (first_bb);
7121                 if (!next && first_bb->next_bb) {
7122                         first_bb = first_bb->next_bb;
7123                         next = mono_bb_first_ins (first_bb);
7124                 }
7125
7126                 if (first_bb->in_count > 1)
7127                         next = NULL;
7128
7129                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7130                         ArgInfo *ainfo = cinfo->args + i;
7131                         gboolean match = FALSE;
7132
7133                         ins = cfg->args [i];
7134                         if (ins->opcode != OP_REGVAR) {
7135                                 switch (ainfo->storage) {
7136                                 case ArgInIReg: {
7137                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7138                                                 if (next->dreg == ainfo->reg) {
7139                                                         NULLIFY_INS (next);
7140                                                         match = TRUE;
7141                                                 } else {
7142                                                         next->opcode = OP_MOVE;
7143                                                         next->sreg1 = ainfo->reg;
7144                                                         /* Only continue if the instruction doesn't change argument regs */
7145                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7146                                                                 match = TRUE;
7147                                                 }
7148                                         }
7149                                         break;
7150                                 }
7151                                 default:
7152                                         break;
7153                                 }
7154                         } else {
7155                                 /* Argument allocated to (non-volatile) register */
7156                                 switch (ainfo->storage) {
7157                                 case ArgInIReg:
7158                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7159                                                 NULLIFY_INS (next);
7160                                                 match = TRUE;
7161                                         }
7162                                         break;
7163                                 default:
7164                                         break;
7165                                 }
7166                         }
7167
7168                         if (match) {
7169                                 next = next->next;
7170                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7171                                 if (!next)
7172                                         break;
7173                         }
7174                 }
7175         }
7176
7177         if (cfg->gen_seq_points) {
7178                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7179
7180                 /* Initialize seq_point_info_var */
7181                 if (cfg->compile_aot) {
7182                         /* Initialize the variable from a GOT slot */
7183                         /* Same as OP_AOTCONST */
7184                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7185                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7186                         g_assert (info_var->opcode == OP_REGOFFSET);
7187                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7188                 }
7189
7190                 /* Initialize ss_trigger_page_var */
7191                 ins = cfg->arch.ss_trigger_page_var;
7192
7193                 g_assert (ins->opcode == OP_REGOFFSET);
7194
7195                 if (cfg->compile_aot) {
7196                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7197                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7198                 } else {
7199                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7200                 }
7201                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7202         }
7203
7204         cfg->code_len = code - cfg->native_code;
7205
7206         g_assert (cfg->code_len < cfg->code_size);
7207
7208         return code;
7209 }
7210
7211 void
7212 mono_arch_emit_epilog (MonoCompile *cfg)
7213 {
7214         MonoMethod *method = cfg->method;
7215         int quad, pos, i;
7216         guint8 *code;
7217         int max_epilog_size;
7218         CallInfo *cinfo;
7219         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7220
7221         max_epilog_size = get_max_epilog_size (cfg);
7222
7223         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7224                 cfg->code_size *= 2;
7225                 cfg->native_code = mono_realloc_native_code (cfg);
7226                 cfg->stat_code_reallocs++;
7227         }
7228
7229         code = cfg->native_code + cfg->code_len;
7230
7231         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7232                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7233
7234         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7235         pos = 0;
7236
7237         if (method->save_lmf) {
7238 #ifdef HOST_WIN32
7239                 code = emit_pop_lmf (cfg, code, lmf_offset);
7240 #endif
7241
7242                 /* check if we need to restore protection of the stack after a stack overflow */
7243                 if (mono_get_jit_tls_offset () != -1) {
7244                         guint8 *patch;
7245                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7246                         /* we load the value in a separate instruction: this mechanism may be
7247                          * used later as a safer way to do thread interruption
7248                          */
7249                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7250                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7251                         patch = code;
7252                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7253                         /* note that the call trampoline will preserve eax/edx */
7254                         x86_call_reg (code, X86_ECX);
7255                         x86_patch (patch, code);
7256                 } else {
7257                         /* FIXME: maybe save the jit tls in the prolog */
7258                 }
7259
7260                 /* Restore caller saved regs */
7261                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7262                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7263                 }
7264                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
7265                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
7266                 }
7267                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
7268                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
7269                 }
7270                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
7271                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
7272                 }
7273                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
7274                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
7275                 }
7276                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
7277 #if defined(__default_codegen__)
7278                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
7279 #elif defined(__native_client_codegen__)
7280                         g_assert_not_reached();
7281 #endif
7282                 }
7283 #ifdef HOST_WIN32
7284                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
7285                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
7286                 }
7287                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
7288                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
7289                 }
7290 #endif
7291         } else {
7292                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7293
7294                 for (i = 0; i < AMD64_NREG; ++i)
7295                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7296                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7297                                 save_area_offset += 8;
7298                         }
7299         }
7300
7301         /* Load returned vtypes into registers if needed */
7302         cinfo = cfg->arch.cinfo;
7303         if (cinfo->ret.storage == ArgValuetypeInReg) {
7304                 ArgInfo *ainfo = &cinfo->ret;
7305                 MonoInst *inst = cfg->ret;
7306
7307                 for (quad = 0; quad < 2; quad ++) {
7308                         switch (ainfo->pair_storage [quad]) {
7309                         case ArgInIReg:
7310                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7311                                 break;
7312                         case ArgInFloatSSEReg:
7313                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7314                                 break;
7315                         case ArgInDoubleSSEReg:
7316                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7317                                 break;
7318                         case ArgNone:
7319                                 break;
7320                         default:
7321                                 g_assert_not_reached ();
7322                         }
7323                 }
7324         }
7325
7326         if (cfg->arch.omit_fp) {
7327                 if (cfg->arch.stack_alloc_size)
7328                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7329         } else {
7330                 amd64_leave (code);
7331         }
7332         async_exc_point (code);
7333         amd64_ret (code);
7334
7335         cfg->code_len = code - cfg->native_code;
7336
7337         g_assert (cfg->code_len < cfg->code_size);
7338 }
7339
7340 void
7341 mono_arch_emit_exceptions (MonoCompile *cfg)
7342 {
7343         MonoJumpInfo *patch_info;
7344         int nthrows, i;
7345         guint8 *code;
7346         MonoClass *exc_classes [16];
7347         guint8 *exc_throw_start [16], *exc_throw_end [16];
7348         guint32 code_size = 0;
7349
7350         /* Compute needed space */
7351         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7352                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7353                         code_size += 40;
7354                 if (patch_info->type == MONO_PATCH_INFO_R8)
7355                         code_size += 8 + 15; /* sizeof (double) + alignment */
7356                 if (patch_info->type == MONO_PATCH_INFO_R4)
7357                         code_size += 4 + 15; /* sizeof (float) + alignment */
7358                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7359                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7360         }
7361
7362 #ifdef __native_client_codegen__
7363         /* Give us extra room on Native Client.  This could be   */
7364         /* more carefully calculated, but bundle alignment makes */
7365         /* it much trickier, so *2 like other places is good.    */
7366         code_size *= 2;
7367 #endif
7368
7369         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7370                 cfg->code_size *= 2;
7371                 cfg->native_code = mono_realloc_native_code (cfg);
7372                 cfg->stat_code_reallocs++;
7373         }
7374
7375         code = cfg->native_code + cfg->code_len;
7376
7377         /* add code to raise exceptions */
7378         nthrows = 0;
7379         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7380                 switch (patch_info->type) {
7381                 case MONO_PATCH_INFO_EXC: {
7382                         MonoClass *exc_class;
7383                         guint8 *buf, *buf2;
7384                         guint32 throw_ip;
7385
7386                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7387
7388                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7389                         g_assert (exc_class);
7390                         throw_ip = patch_info->ip.i;
7391
7392                         //x86_breakpoint (code);
7393                         /* Find a throw sequence for the same exception class */
7394                         for (i = 0; i < nthrows; ++i)
7395                                 if (exc_classes [i] == exc_class)
7396                                         break;
7397                         if (i < nthrows) {
7398                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7399                                 x86_jump_code (code, exc_throw_start [i]);
7400                                 patch_info->type = MONO_PATCH_INFO_NONE;
7401                         }
7402                         else {
7403                                 buf = code;
7404                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7405                                 buf2 = code;
7406
7407                                 if (nthrows < 16) {
7408                                         exc_classes [nthrows] = exc_class;
7409                                         exc_throw_start [nthrows] = code;
7410                                 }
7411                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7412
7413                                 patch_info->type = MONO_PATCH_INFO_NONE;
7414
7415                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7416
7417                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7418                                 while (buf < buf2)
7419                                         x86_nop (buf);
7420
7421                                 if (nthrows < 16) {
7422                                         exc_throw_end [nthrows] = code;
7423                                         nthrows ++;
7424                                 }
7425                         }
7426                         break;
7427                 }
7428                 default:
7429                         /* do nothing */
7430                         break;
7431                 }
7432                 g_assert(code < cfg->native_code + cfg->code_size);
7433         }
7434
7435         /* Handle relocations with RIP relative addressing */
7436         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7437                 gboolean remove = FALSE;
7438                 guint8 *orig_code = code;
7439
7440                 switch (patch_info->type) {
7441                 case MONO_PATCH_INFO_R8:
7442                 case MONO_PATCH_INFO_R4: {
7443                         guint8 *pos, *patch_pos;
7444                         guint32 target_pos;
7445
7446                         /* The SSE opcodes require a 16 byte alignment */
7447 #if defined(__default_codegen__)
7448                         code = (guint8*)ALIGN_TO (code, 16);
7449 #elif defined(__native_client_codegen__)
7450                         {
7451                                 /* Pad this out with HLT instructions  */
7452                                 /* or we can get garbage bytes emitted */
7453                                 /* which will fail validation          */
7454                                 guint8 *aligned_code;
7455                                 /* extra align to make room for  */
7456                                 /* mov/push below                      */
7457                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7458                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7459                                 /* The technique of hiding data in an  */
7460                                 /* instruction has a problem here: we  */
7461                                 /* need the data aligned to a 16-byte  */
7462                                 /* boundary but the instruction cannot */
7463                                 /* cross the bundle boundary. so only  */
7464                                 /* odd multiples of 16 can be used     */
7465                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7466                                         aligned_code += 16;
7467                                 }
7468                                 while (code < aligned_code) {
7469                                         *(code++) = 0xf4; /* hlt */
7470                                 }
7471                         }
7472 #endif
7473
7474                         pos = cfg->native_code + patch_info->ip.i;
7475                         if (IS_REX (pos [1])) {
7476                                 patch_pos = pos + 5;
7477                                 target_pos = code - pos - 9;
7478                         }
7479                         else {
7480                                 patch_pos = pos + 4;
7481                                 target_pos = code - pos - 8;
7482                         }
7483
7484                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7485 #ifdef __native_client_codegen__
7486                                 /* Hide 64-bit data in a         */
7487                                 /* "mov imm64, r11" instruction. */
7488                                 /* write it before the start of  */
7489                                 /* the data*/
7490                                 *(code-2) = 0x49; /* prefix      */
7491                                 *(code-1) = 0xbb; /* mov X, %r11 */
7492 #endif
7493                                 *(double*)code = *(double*)patch_info->data.target;
7494                                 code += sizeof (double);
7495                         } else {
7496 #ifdef __native_client_codegen__
7497                                 /* Hide 32-bit data in a        */
7498                                 /* "push imm32" instruction.    */
7499                                 *(code-1) = 0x68; /* push */
7500 #endif
7501                                 *(float*)code = *(float*)patch_info->data.target;
7502                                 code += sizeof (float);
7503                         }
7504
7505                         *(guint32*)(patch_pos) = target_pos;
7506
7507                         remove = TRUE;
7508                         break;
7509                 }
7510                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7511                         guint8 *pos;
7512
7513                         if (cfg->compile_aot)
7514                                 continue;
7515
7516                         /*loading is faster against aligned addresses.*/
7517                         code = (guint8*)ALIGN_TO (code, 8);
7518                         memset (orig_code, 0, code - orig_code);
7519
7520                         pos = cfg->native_code + patch_info->ip.i;
7521
7522                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7523                         if (IS_REX (pos [1]))
7524                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7525                         else
7526                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7527
7528                         *(gpointer*)code = (gpointer)patch_info->data.target;
7529                         code += sizeof (gpointer);
7530
7531                         remove = TRUE;
7532                         break;
7533                 }
7534                 default:
7535                         break;
7536                 }
7537
7538                 if (remove) {
7539                         if (patch_info == cfg->patch_info)
7540                                 cfg->patch_info = patch_info->next;
7541                         else {
7542                                 MonoJumpInfo *tmp;
7543
7544                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7545                                         ;
7546                                 tmp->next = patch_info->next;
7547                         }
7548                 }
7549                 g_assert (code < cfg->native_code + cfg->code_size);
7550         }
7551
7552         cfg->code_len = code - cfg->native_code;
7553
7554         g_assert (cfg->code_len < cfg->code_size);
7555
7556 }
7557
7558 #endif /* DISABLE_JIT */
7559
7560 void*
7561 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7562 {
7563         guchar *code = p;
7564         CallInfo *cinfo = NULL;
7565         MonoMethodSignature *sig;
7566         MonoInst *inst;
7567         int i, n, stack_area = 0;
7568
7569         /* Keep this in sync with mono_arch_get_argument_info */
7570
7571         if (enable_arguments) {
7572                 /* Allocate a new area on the stack and save arguments there */
7573                 sig = mono_method_signature (cfg->method);
7574
7575                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7576
7577                 n = sig->param_count + sig->hasthis;
7578
7579                 stack_area = ALIGN_TO (n * 8, 16);
7580
7581                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7582
7583                 for (i = 0; i < n; ++i) {
7584                         inst = cfg->args [i];
7585
7586                         if (inst->opcode == OP_REGVAR)
7587                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7588                         else {
7589                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7590                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7591                         }
7592                 }
7593         }
7594
7595         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7596         amd64_set_reg_template (code, AMD64_ARG_REG1);
7597         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7598         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7599
7600         if (enable_arguments)
7601                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7602
7603         return code;
7604 }
7605
7606 enum {
7607         SAVE_NONE,
7608         SAVE_STRUCT,
7609         SAVE_EAX,
7610         SAVE_EAX_EDX,
7611         SAVE_XMM
7612 };
7613
7614 void*
7615 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7616 {
7617         guchar *code = p;
7618         int save_mode = SAVE_NONE;
7619         MonoMethod *method = cfg->method;
7620         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
7621         int i;
7622
7623         switch (ret_type->type) {
7624         case MONO_TYPE_VOID:
7625                 /* special case string .ctor icall */
7626                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7627                         save_mode = SAVE_EAX;
7628                 else
7629                         save_mode = SAVE_NONE;
7630                 break;
7631         case MONO_TYPE_I8:
7632         case MONO_TYPE_U8:
7633                 save_mode = SAVE_EAX;
7634                 break;
7635         case MONO_TYPE_R4:
7636         case MONO_TYPE_R8:
7637                 save_mode = SAVE_XMM;
7638                 break;
7639         case MONO_TYPE_GENERICINST:
7640                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7641                         save_mode = SAVE_EAX;
7642                         break;
7643                 }
7644                 /* Fall through */
7645         case MONO_TYPE_VALUETYPE:
7646                 save_mode = SAVE_STRUCT;
7647                 break;
7648         default:
7649                 save_mode = SAVE_EAX;
7650                 break;
7651         }
7652
7653         /* Save the result and copy it into the proper argument register */
7654         switch (save_mode) {
7655         case SAVE_EAX:
7656                 amd64_push_reg (code, AMD64_RAX);
7657                 /* Align stack */
7658                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7659                 if (enable_arguments)
7660                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7661                 break;
7662         case SAVE_STRUCT:
7663                 /* FIXME: */
7664                 if (enable_arguments)
7665                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7666                 break;
7667         case SAVE_XMM:
7668                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7669                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7670                 /* Align stack */
7671                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7672                 /*
7673                  * The result is already in the proper argument register so no copying
7674                  * needed.
7675                  */
7676                 break;
7677         case SAVE_NONE:
7678                 break;
7679         default:
7680                 g_assert_not_reached ();
7681         }
7682
7683         /* Set %al since this is a varargs call */
7684         if (save_mode == SAVE_XMM)
7685                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7686         else
7687                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7688
7689         if (preserve_argument_registers) {
7690                 for (i = 0; i < PARAM_REGS; ++i)
7691                         amd64_push_reg (code, param_regs [i]);
7692         }
7693
7694         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7695         amd64_set_reg_template (code, AMD64_ARG_REG1);
7696         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7697
7698         if (preserve_argument_registers) {
7699                 for (i = PARAM_REGS - 1; i >= 0; --i)
7700                         amd64_pop_reg (code, param_regs [i]);
7701         }
7702
7703         /* Restore result */
7704         switch (save_mode) {
7705         case SAVE_EAX:
7706                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7707                 amd64_pop_reg (code, AMD64_RAX);
7708                 break;
7709         case SAVE_STRUCT:
7710                 /* FIXME: */
7711                 break;
7712         case SAVE_XMM:
7713                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7714                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7715                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7716                 break;
7717         case SAVE_NONE:
7718                 break;
7719         default:
7720                 g_assert_not_reached ();
7721         }
7722
7723         return code;
7724 }
7725
7726 void
7727 mono_arch_flush_icache (guint8 *code, gint size)
7728 {
7729         /* Not needed */
7730 }
7731
7732 void
7733 mono_arch_flush_register_windows (void)
7734 {
7735 }
7736
7737 gboolean
7738 mono_arch_is_inst_imm (gint64 imm)
7739 {
7740         return amd64_is_imm32 (imm);
7741 }
7742
7743 /*
7744  * Determine whenever the trap whose info is in SIGINFO is caused by
7745  * integer overflow.
7746  */
7747 gboolean
7748 mono_arch_is_int_overflow (void *sigctx, void *info)
7749 {
7750         MonoContext ctx;
7751         guint8* rip;
7752         int reg;
7753         gint64 value;
7754
7755         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7756
7757         rip = (guint8*)ctx.rip;
7758
7759         if (IS_REX (rip [0])) {
7760                 reg = amd64_rex_b (rip [0]);
7761                 rip ++;
7762         }
7763         else
7764                 reg = 0;
7765
7766         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7767                 /* idiv REG */
7768                 reg += x86_modrm_rm (rip [1]);
7769
7770                 switch (reg) {
7771                 case AMD64_RAX:
7772                         value = ctx.rax;
7773                         break;
7774                 case AMD64_RBX:
7775                         value = ctx.rbx;
7776                         break;
7777                 case AMD64_RCX:
7778                         value = ctx.rcx;
7779                         break;
7780                 case AMD64_RDX:
7781                         value = ctx.rdx;
7782                         break;
7783                 case AMD64_RBP:
7784                         value = ctx.rbp;
7785                         break;
7786                 case AMD64_RSP:
7787                         value = ctx.rsp;
7788                         break;
7789                 case AMD64_RSI:
7790                         value = ctx.rsi;
7791                         break;
7792                 case AMD64_RDI:
7793                         value = ctx.rdi;
7794                         break;
7795                 case AMD64_R12:
7796                         value = ctx.r12;
7797                         break;
7798                 case AMD64_R13:
7799                         value = ctx.r13;
7800                         break;
7801                 case AMD64_R14:
7802                         value = ctx.r14;
7803                         break;
7804                 case AMD64_R15:
7805                         value = ctx.r15;
7806                         break;
7807                 default:
7808                         g_assert_not_reached ();
7809                         reg = -1;
7810                 }
7811
7812                 if (value == -1)
7813                         return TRUE;
7814         }
7815
7816         return FALSE;
7817 }
7818
7819 guint32
7820 mono_arch_get_patch_offset (guint8 *code)
7821 {
7822         return 3;
7823 }
7824
7825 /**
7826  * mono_breakpoint_clean_code:
7827  *
7828  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7829  * breakpoints in the original code, they are removed in the copy.
7830  *
7831  * Returns TRUE if no sw breakpoint was present.
7832  */
7833 gboolean
7834 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7835 {
7836         int i;
7837         gboolean can_write = TRUE;
7838         /*
7839          * If method_start is non-NULL we need to perform bound checks, since we access memory
7840          * at code - offset we could go before the start of the method and end up in a different
7841          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7842          * instead.
7843          */
7844         if (!method_start || code - offset >= method_start) {
7845                 memcpy (buf, code - offset, size);
7846         } else {
7847                 int diff = code - method_start;
7848                 memset (buf, 0, size);
7849                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7850         }
7851         code -= offset;
7852         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7853                 int idx = mono_breakpoint_info_index [i];
7854                 guint8 *ptr;
7855                 if (idx < 1)
7856                         continue;
7857                 ptr = mono_breakpoint_info [idx].address;
7858                 if (ptr >= code && ptr < code + size) {
7859                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7860                         can_write = FALSE;
7861                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7862                         buf [ptr - code] = saved_byte;
7863                 }
7864         }
7865         return can_write;
7866 }
7867
7868 #if defined(__native_client_codegen__)
7869 /* For membase calls, we want the base register. for Native Client,  */
7870 /* all indirect calls have the following sequence with the given sizes: */
7871 /* mov %eXX,%eXX                                [2-3]   */
7872 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7873 /* and $0xffffffffffffffe0,%r11d                [4]     */
7874 /* add %r15,%r11                                [3]     */
7875 /* callq *%r11                                  [3]     */
7876
7877
7878 /* Determine if code points to a NaCl call-through-register sequence, */
7879 /* (i.e., the last 3 instructions listed above) */
7880 int
7881 is_nacl_call_reg_sequence(guint8* code)
7882 {
7883         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7884                                "\x4d\x03\xdf"     /* add */
7885                                "\x41\xff\xd3";   /* call */
7886         return memcmp(code, sequence, 10) == 0;
7887 }
7888
7889 /* Determine if code points to the first opcode of the mov membase component */
7890 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7891 /* (there could be a REX prefix before the opcode but it is ignored) */
7892 static int
7893 is_nacl_indirect_call_membase_sequence(guint8* code)
7894 {
7895                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7896         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7897                /* and that src reg = dest reg */
7898                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7899                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7900                IS_REX(code[2]) &&
7901                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7902                /* and has dst of r11 and base of r15 */
7903                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7904                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7905 }
7906 #endif /* __native_client_codegen__ */
7907
7908 int
7909 mono_arch_get_this_arg_reg (guint8 *code)
7910 {
7911         return AMD64_ARG_REG1;
7912 }
7913
7914 gpointer
7915 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7916 {
7917         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7918 }
7919
7920 #define MAX_ARCH_DELEGATE_PARAMS 10
7921
7922 static gpointer
7923 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7924 {
7925         guint8 *code, *start;
7926         int i;
7927
7928         if (has_target) {
7929                 start = code = mono_global_codeman_reserve (64);
7930
7931                 /* Replace the this argument with the target */
7932                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7933                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7934                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7935
7936                 g_assert ((code - start) < 64);
7937         } else {
7938                 start = code = mono_global_codeman_reserve (64);
7939
7940                 if (param_count == 0) {
7941                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7942                 } else {
7943                         /* We have to shift the arguments left */
7944                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7945                         for (i = 0; i < param_count; ++i) {
7946 #ifdef HOST_WIN32
7947                                 if (i < 3)
7948                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7949                                 else
7950                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7951 #else
7952                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7953 #endif
7954                         }
7955
7956                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7957                 }
7958                 g_assert ((code - start) < 64);
7959         }
7960
7961         nacl_global_codeman_validate(&start, 64, &code);
7962
7963         mono_debug_add_delegate_trampoline (start, code - start);
7964
7965         if (code_len)
7966                 *code_len = code - start;
7967
7968
7969         if (mono_jit_map_is_enabled ()) {
7970                 char *buff;
7971                 if (has_target)
7972                         buff = (char*)"delegate_invoke_has_target";
7973                 else
7974                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7975                 mono_emit_jit_tramp (start, code - start, buff);
7976                 if (!has_target)
7977                         g_free (buff);
7978         }
7979
7980         return start;
7981 }
7982
7983 /*
7984  * mono_arch_get_delegate_invoke_impls:
7985  *
7986  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7987  * trampolines.
7988  */
7989 GSList*
7990 mono_arch_get_delegate_invoke_impls (void)
7991 {
7992         GSList *res = NULL;
7993         guint8 *code;
7994         guint32 code_len;
7995         int i;
7996         char *tramp_name;
7997
7998         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7999         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
8000
8001         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
8002                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
8003                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
8004                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
8005                 g_free (tramp_name);
8006         }
8007
8008         return res;
8009 }
8010
8011 gpointer
8012 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8013 {
8014         guint8 *code, *start;
8015         int i;
8016
8017         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8018                 return NULL;
8019
8020         /* FIXME: Support more cases */
8021         if (MONO_TYPE_ISSTRUCT (sig->ret))
8022                 return NULL;
8023
8024         if (has_target) {
8025                 static guint8* cached = NULL;
8026
8027                 if (cached)
8028                         return cached;
8029
8030                 if (mono_aot_only)
8031                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8032                 else
8033                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
8034
8035                 mono_memory_barrier ();
8036
8037                 cached = start;
8038         } else {
8039                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8040                 for (i = 0; i < sig->param_count; ++i)
8041                         if (!mono_is_regsize_var (sig->params [i]))
8042                                 return NULL;
8043                 if (sig->param_count > 4)
8044                         return NULL;
8045
8046                 code = cache [sig->param_count];
8047                 if (code)
8048                         return code;
8049
8050                 if (mono_aot_only) {
8051                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8052                         start = mono_aot_get_trampoline (name);
8053                         g_free (name);
8054                 } else {
8055                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8056                 }
8057
8058                 mono_memory_barrier ();
8059
8060                 cache [sig->param_count] = start;
8061         }
8062
8063         return start;
8064 }
8065 void
8066 mono_arch_finish_init (void)
8067 {
8068 #ifdef HOST_WIN32
8069         /*
8070          * We need to init this multiple times, since when we are first called, the key might not
8071          * be initialized yet.
8072          */
8073         jit_tls_offset = mono_get_jit_tls_key ();
8074
8075         /* Only 64 tls entries can be accessed using inline code */
8076         if (jit_tls_offset >= 64)
8077                 jit_tls_offset = -1;
8078 #else
8079 #ifdef MONO_XEN_OPT
8080         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8081 #endif
8082 #endif
8083 }
8084
8085 void
8086 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8087 {
8088 }
8089
8090 #ifdef MONO_ARCH_HAVE_IMT
8091
8092 #if defined(__default_codegen__)
8093 #define CMP_SIZE (6 + 1)
8094 #define CMP_REG_REG_SIZE (4 + 1)
8095 #define BR_SMALL_SIZE 2
8096 #define BR_LARGE_SIZE 6
8097 #define MOV_REG_IMM_SIZE 10
8098 #define MOV_REG_IMM_32BIT_SIZE 6
8099 #define JUMP_REG_SIZE (2 + 1)
8100 #elif defined(__native_client_codegen__)
8101 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8102 #define CMP_SIZE ((6 + 1) * 2 - 1)
8103 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8104 #define BR_SMALL_SIZE (2 * 2 - 1)
8105 #define BR_LARGE_SIZE (6 * 2 - 1)
8106 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8107 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8108 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8109 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8110 /* Jump membase's size is large and unpredictable    */
8111 /* in native client, just pad it out a whole bundle. */
8112 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8113 #endif
8114
8115 static int
8116 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8117 {
8118         int i, distance = 0;
8119         for (i = start; i < target; ++i)
8120                 distance += imt_entries [i]->chunk_size;
8121         return distance;
8122 }
8123
8124 /*
8125  * LOCKING: called with the domain lock held
8126  */
8127 gpointer
8128 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8129         gpointer fail_tramp)
8130 {
8131         int i;
8132         int size = 0;
8133         guint8 *code, *start;
8134         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8135
8136         for (i = 0; i < count; ++i) {
8137                 MonoIMTCheckItem *item = imt_entries [i];
8138                 if (item->is_equals) {
8139                         if (item->check_target_idx) {
8140                                 if (!item->compare_done) {
8141                                         if (amd64_is_imm32 (item->key))
8142                                                 item->chunk_size += CMP_SIZE;
8143                                         else
8144                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8145                                 }
8146                                 if (item->has_target_code) {
8147                                         item->chunk_size += MOV_REG_IMM_SIZE;
8148                                 } else {
8149                                         if (vtable_is_32bit)
8150                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8151                                         else
8152                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8153 #ifdef __native_client_codegen__
8154                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8155 #endif
8156                                 }
8157                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8158                         } else {
8159                                 if (fail_tramp) {
8160                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8161                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8162                                 } else {
8163                                         if (vtable_is_32bit)
8164                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8165                                         else
8166                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8167                                         item->chunk_size += JUMP_REG_SIZE;
8168                                         /* with assert below:
8169                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8170                                          */
8171 #ifdef __native_client_codegen__
8172                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8173 #endif
8174                                 }
8175                         }
8176                 } else {
8177                         if (amd64_is_imm32 (item->key))
8178                                 item->chunk_size += CMP_SIZE;
8179                         else
8180                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8181                         item->chunk_size += BR_LARGE_SIZE;
8182                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8183                 }
8184                 size += item->chunk_size;
8185         }
8186 #if defined(__native_client__) && defined(__native_client_codegen__)
8187         /* In Native Client, we don't re-use thunks, allocate from the */
8188         /* normal code manager paths. */
8189         code = mono_domain_code_reserve (domain, size);
8190 #else
8191         if (fail_tramp)
8192                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8193         else
8194                 code = mono_domain_code_reserve (domain, size);
8195 #endif
8196         start = code;
8197         for (i = 0; i < count; ++i) {
8198                 MonoIMTCheckItem *item = imt_entries [i];
8199                 item->code_target = code;
8200                 if (item->is_equals) {
8201                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8202
8203                         if (item->check_target_idx || fail_case) {
8204                                 if (!item->compare_done || fail_case) {
8205                                         if (amd64_is_imm32 (item->key))
8206                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8207                                         else {
8208                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8209                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8210                                         }
8211                                 }
8212                                 item->jmp_code = code;
8213                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8214                                 if (item->has_target_code) {
8215                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8216                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8217                                 } else {
8218                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8219                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8220                                 }
8221
8222                                 if (fail_case) {
8223                                         amd64_patch (item->jmp_code, code);
8224                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8225                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8226                                         item->jmp_code = NULL;
8227                                 }
8228                         } else {
8229                                 /* enable the commented code to assert on wrong method */
8230 #if 0
8231                                 if (amd64_is_imm32 (item->key))
8232                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8233                                 else {
8234                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8235                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8236                                 }
8237                                 item->jmp_code = code;
8238                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8239                                 /* See the comment below about R10 */
8240                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8241                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8242                                 amd64_patch (item->jmp_code, code);
8243                                 amd64_breakpoint (code);
8244                                 item->jmp_code = NULL;
8245 #else
8246                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8247                                    needs to be preserved.  R10 needs
8248                                    to be preserved for calls which
8249                                    require a runtime generic context,
8250                                    but interface calls don't. */
8251                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8252                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8253 #endif
8254                         }
8255                 } else {
8256                         if (amd64_is_imm32 (item->key))
8257                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8258                         else {
8259                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8260                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8261                         }
8262                         item->jmp_code = code;
8263                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8264                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8265                         else
8266                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8267                 }
8268                 g_assert (code - item->code_target <= item->chunk_size);
8269         }
8270         /* patch the branches to get to the target items */
8271         for (i = 0; i < count; ++i) {
8272                 MonoIMTCheckItem *item = imt_entries [i];
8273                 if (item->jmp_code) {
8274                         if (item->check_target_idx) {
8275                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8276                         }
8277                 }
8278         }
8279
8280         if (!fail_tramp)
8281                 mono_stats.imt_thunks_size += code - start;
8282         g_assert (code - start <= size);
8283
8284         nacl_domain_code_validate(domain, &start, size, &code);
8285
8286         return start;
8287 }
8288
8289 MonoMethod*
8290 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8291 {
8292         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8293 }
8294 #endif
8295
8296 MonoVTable*
8297 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8298 {
8299         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8300 }
8301
8302 GSList*
8303 mono_arch_get_cie_program (void)
8304 {
8305         GSList *l = NULL;
8306
8307         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8308         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8309
8310         return l;
8311 }
8312
8313 MonoInst*
8314 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8315 {
8316         MonoInst *ins = NULL;
8317         int opcode = 0;
8318
8319         if (cmethod->klass == mono_defaults.math_class) {
8320                 if (strcmp (cmethod->name, "Sin") == 0) {
8321                         opcode = OP_SIN;
8322                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8323                         opcode = OP_COS;
8324                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8325                         opcode = OP_SQRT;
8326                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8327                         opcode = OP_ABS;
8328                 }
8329
8330                 if (opcode) {
8331                         MONO_INST_NEW (cfg, ins, opcode);
8332                         ins->type = STACK_R8;
8333                         ins->dreg = mono_alloc_freg (cfg);
8334                         ins->sreg1 = args [0]->dreg;
8335                         MONO_ADD_INS (cfg->cbb, ins);
8336                 }
8337
8338                 opcode = 0;
8339                 if (cfg->opt & MONO_OPT_CMOV) {
8340                         if (strcmp (cmethod->name, "Min") == 0) {
8341                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8342                                         opcode = OP_IMIN;
8343                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8344                                         opcode = OP_IMIN_UN;
8345                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8346                                         opcode = OP_LMIN;
8347                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8348                                         opcode = OP_LMIN_UN;
8349                         } else if (strcmp (cmethod->name, "Max") == 0) {
8350                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8351                                         opcode = OP_IMAX;
8352                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8353                                         opcode = OP_IMAX_UN;
8354                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8355                                         opcode = OP_LMAX;
8356                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8357                                         opcode = OP_LMAX_UN;
8358                         }
8359                 }
8360
8361                 if (opcode) {
8362                         MONO_INST_NEW (cfg, ins, opcode);
8363                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8364                         ins->dreg = mono_alloc_ireg (cfg);
8365                         ins->sreg1 = args [0]->dreg;
8366                         ins->sreg2 = args [1]->dreg;
8367                         MONO_ADD_INS (cfg->cbb, ins);
8368                 }
8369
8370 #if 0
8371                 /* OP_FREM is not IEEE compatible */
8372                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8373                         MONO_INST_NEW (cfg, ins, OP_FREM);
8374                         ins->inst_i0 = args [0];
8375                         ins->inst_i1 = args [1];
8376                 }
8377 #endif
8378         }
8379
8380         /*
8381          * Can't implement CompareExchange methods this way since they have
8382          * three arguments.
8383          */
8384
8385         return ins;
8386 }
8387
8388 gboolean
8389 mono_arch_print_tree (MonoInst *tree, int arity)
8390 {
8391         return 0;
8392 }
8393
8394 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8395
8396 mgreg_t
8397 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8398 {
8399         switch (reg) {
8400         case AMD64_RCX: return ctx->rcx;
8401         case AMD64_RDX: return ctx->rdx;
8402         case AMD64_RBX: return ctx->rbx;
8403         case AMD64_RBP: return ctx->rbp;
8404         case AMD64_RSP: return ctx->rsp;
8405         default:
8406                 return _CTX_REG (ctx, rax, reg);
8407         }
8408 }
8409
8410 void
8411 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8412 {
8413         switch (reg) {
8414         case AMD64_RCX:
8415                 ctx->rcx = val;
8416                 break;
8417         case AMD64_RDX:
8418                 ctx->rdx = val;
8419                 break;
8420         case AMD64_RBX:
8421                 ctx->rbx = val;
8422                 break;
8423         case AMD64_RBP:
8424                 ctx->rbp = val;
8425                 break;
8426         case AMD64_RSP:
8427                 ctx->rsp = val;
8428                 break;
8429         default:
8430                 _CTX_REG (ctx, rax, reg) = val;
8431         }
8432 }
8433
8434 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8435 gpointer
8436 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8437 {
8438         int offset;
8439         gpointer *sp, old_value;
8440         char *bp;
8441         const unsigned char *handler;
8442
8443         /*Decode the first instruction to figure out where did we store the spvar*/
8444         /*Our jit MUST generate the following:
8445          mov    %rsp, ?(%rbp)
8446
8447          Which is encoded as: REX.W 0x89 mod_rm
8448          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8449                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8450                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8451
8452         FIXME can we generate frameless methods on this case?
8453
8454         */
8455         handler = clause->handler_start;
8456
8457         /*REX.W*/
8458         if (*handler != 0x48)
8459                 return NULL;
8460         ++handler;
8461
8462         /*mov r, r/m */
8463         if (*handler != 0x89)
8464                 return NULL;
8465         ++handler;
8466
8467         if (*handler == 0x65)
8468                 offset = *(signed char*)(handler + 1);
8469         else if (*handler == 0xA5)
8470                 offset = *(int*)(handler + 1);
8471         else
8472                 return NULL;
8473
8474         /*Load the spvar*/
8475         bp = MONO_CONTEXT_GET_BP (ctx);
8476         sp = *(gpointer*)(bp + offset);
8477
8478         old_value = *sp;
8479         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8480                 return old_value;
8481
8482         *sp = new_value;
8483
8484         return old_value;
8485 }
8486
8487 /*
8488  * mono_arch_emit_load_aotconst:
8489  *
8490  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8491  * TARGET from the mscorlib GOT in full-aot code.
8492  * On AMD64, the result is placed into R11.
8493  */
8494 guint8*
8495 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8496 {
8497         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8498         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8499
8500         return code;
8501 }
8502
8503 /*
8504  * mono_arch_get_trampolines:
8505  *
8506  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8507  * for AOT.
8508  */
8509 GSList *
8510 mono_arch_get_trampolines (gboolean aot)
8511 {
8512         return mono_amd64_get_exception_trampolines (aot);
8513 }
8514
8515 /* Soft Debug support */
8516 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8517
8518 /*
8519  * mono_arch_set_breakpoint:
8520  *
8521  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8522  * The location should contain code emitted by OP_SEQ_POINT.
8523  */
8524 void
8525 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8526 {
8527         guint8 *code = ip;
8528         guint8 *orig_code = code;
8529
8530         if (ji->from_aot) {
8531                 guint32 native_offset = ip - (guint8*)ji->code_start;
8532                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8533
8534                 g_assert (info->bp_addrs [native_offset] == 0);
8535                 info->bp_addrs [native_offset] = bp_trigger_page;
8536         } else {
8537                 /*
8538                  * In production, we will use int3 (has to fix the size in the md
8539                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8540                  * instead.
8541                  */
8542                 g_assert (code [0] == 0x90);
8543                 if (breakpoint_size == 8) {
8544                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8545                 } else {
8546                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8547                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8548                 }
8549
8550                 g_assert (code - orig_code == breakpoint_size);
8551         }
8552 }
8553
8554 /*
8555  * mono_arch_clear_breakpoint:
8556  *
8557  *   Clear the breakpoint at IP.
8558  */
8559 void
8560 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8561 {
8562         guint8 *code = ip;
8563         int i;
8564
8565         if (ji->from_aot) {
8566                 guint32 native_offset = ip - (guint8*)ji->code_start;
8567                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8568
8569                 g_assert (info->bp_addrs [native_offset] == 0);
8570                 info->bp_addrs [native_offset] = info;
8571         } else {
8572                 for (i = 0; i < breakpoint_size; ++i)
8573                         x86_nop (code);
8574         }
8575 }
8576
8577 gboolean
8578 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8579 {
8580 #ifdef HOST_WIN32
8581         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8582         return FALSE;
8583 #else
8584         siginfo_t* sinfo = (siginfo_t*) info;
8585         /* Sometimes the address is off by 4 */
8586         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8587                 return TRUE;
8588         else
8589                 return FALSE;
8590 #endif
8591 }
8592
8593 /*
8594  * mono_arch_skip_breakpoint:
8595  *
8596  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8597  * we resume, the instruction is not executed again.
8598  */
8599 void
8600 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8601 {
8602         if (ji->from_aot) {
8603                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8604                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8605         } else {
8606                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8607         }
8608 }
8609
8610 /*
8611  * mono_arch_start_single_stepping:
8612  *
8613  *   Start single stepping.
8614  */
8615 void
8616 mono_arch_start_single_stepping (void)
8617 {
8618         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8619 }
8620
8621 /*
8622  * mono_arch_stop_single_stepping:
8623  *
8624  *   Stop single stepping.
8625  */
8626 void
8627 mono_arch_stop_single_stepping (void)
8628 {
8629         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8630 }
8631
8632 /*
8633  * mono_arch_is_single_step_event:
8634  *
8635  *   Return whenever the machine state in SIGCTX corresponds to a single
8636  * step event.
8637  */
8638 gboolean
8639 mono_arch_is_single_step_event (void *info, void *sigctx)
8640 {
8641 #ifdef HOST_WIN32
8642         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8643         return FALSE;
8644 #else
8645         siginfo_t* sinfo = (siginfo_t*) info;
8646         /* Sometimes the address is off by 4 */
8647         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8648                 return TRUE;
8649         else
8650                 return FALSE;
8651 #endif
8652 }
8653
8654 /*
8655  * mono_arch_skip_single_step:
8656  *
8657  *   Modify CTX so the ip is placed after the single step trigger instruction,
8658  * we resume, the instruction is not executed again.
8659  */
8660 void
8661 mono_arch_skip_single_step (MonoContext *ctx)
8662 {
8663         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8664 }
8665
8666 /*
8667  * mono_arch_create_seq_point_info:
8668  *
8669  *   Return a pointer to a data structure which is used by the sequence
8670  * point implementation in AOTed code.
8671  */
8672 gpointer
8673 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8674 {
8675         SeqPointInfo *info;
8676         MonoJitInfo *ji;
8677         int i;
8678
8679         // FIXME: Add a free function
8680
8681         mono_domain_lock (domain);
8682         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8683                                                                 code);
8684         mono_domain_unlock (domain);
8685
8686         if (!info) {
8687                 ji = mono_jit_info_table_find (domain, (char*)code);
8688                 g_assert (ji);
8689
8690                 // FIXME: Optimize the size
8691                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8692
8693                 info->ss_trigger_page = ss_trigger_page;
8694                 info->bp_trigger_page = bp_trigger_page;
8695                 /* Initialize to a valid address */
8696                 for (i = 0; i < ji->code_size; ++i)
8697                         info->bp_addrs [i] = info;
8698
8699                 mono_domain_lock (domain);
8700                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8701                                                          code, info);
8702                 mono_domain_unlock (domain);
8703         }
8704
8705         return info;
8706 }
8707
8708 void
8709 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8710 {
8711         ext->lmf.previous_lmf = prev_lmf;
8712         /* Mark that this is a MonoLMFExt */
8713         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8714         ext->lmf.rsp = (gssize)ext;
8715 }
8716
8717 #endif