mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 /*
  69  * The code generated for sequence points reads from this location, which is
  70  * made read-only when single stepping is enabled.
  71  */
  72 static gpointer ss_trigger_page;
  73
  74 /* Enabled breakpoints read from this trigger page */
  75 static gpointer bp_trigger_page;
  76
  77 /* The size of the breakpoint sequence */
  78 static int breakpoint_size;
  79
  80 /* The size of the breakpoint instruction causing the actual fault */
  81 static int breakpoint_fault_size;
  82
  83 /* The size of the single step instruction causing the actual fault */
  84 static int single_step_fault_size;
  85
  86 /* The single step trampoline */
  87 static gpointer ss_trampoline;
  88
  89 /* Offset between fp and the first argument in the callee */
  90 #define ARGS_OFFSET 16
  91 #define GP_SCRATCH_REG AMD64_R11
  92
  93 /*
  94  * AMD64 register usage:
  95  * - callee saved registers are used for global register allocation
  96  * - %r11 is used for materializing 64 bit constants in opcodes
  97  * - the rest is used for local allocation
  98  */
  99
 100 /*
 101  * Floating point comparison results:
 102  *                  ZF PF CF
 103  * A > B            0  0  0
 104  * A < B            0  0  1
 105  * A = B            1  0  0
 106  * A > B            0  0  0
 107  * UNORDERED        1  1  1
 108  */
 109
 110 const char*
 111 mono_arch_regname (int reg)
 112 {
 113         switch (reg) {
 114         case AMD64_RAX: return "%rax";
 115         case AMD64_RBX: return "%rbx";
 116         case AMD64_RCX: return "%rcx";
 117         case AMD64_RDX: return "%rdx";
 118         case AMD64_RSP: return "%rsp";
 119         case AMD64_RBP: return "%rbp";
 120         case AMD64_RDI: return "%rdi";
 121         case AMD64_RSI: return "%rsi";
 122         case AMD64_R8: return "%r8";
 123         case AMD64_R9: return "%r9";
 124         case AMD64_R10: return "%r10";
 125         case AMD64_R11: return "%r11";
 126         case AMD64_R12: return "%r12";
 127         case AMD64_R13: return "%r13";
 128         case AMD64_R14: return "%r14";
 129         case AMD64_R15: return "%r15";
 130         }
 131         return "unknown";
 132 }
 133
 134 static const char * packed_xmmregs [] = {
 135         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 136         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 137 };
 138
 139 static const char * single_xmmregs [] = {
 140         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 141         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 142 };
 143
 144 const char*
 145 mono_arch_fregname (int reg)
 146 {
 147         if (reg < AMD64_XMM_NREG)
 148                 return single_xmmregs [reg];
 149         else
 150                 return "unknown";
 151 }
 152
 153 const char *
 154 mono_arch_xregname (int reg)
 155 {
 156         if (reg < AMD64_XMM_NREG)
 157                 return packed_xmmregs [reg];
 158         else
 159                 return "unknown";
 160 }
 161
 162 static gboolean
 163 debug_omit_fp (void)
 164 {
 165 #if 0
 166         return mono_debug_count ();
 167 #else
 168         return TRUE;
 169 #endif
 170 }
 171
 172 static inline gboolean
 173 amd64_is_near_call (guint8 *code)
 174 {
 175         /* Skip REX */
 176         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 177                 code += 1;
 178
 179         return code [0] == 0xe8;
 180 }
 181
 182 #ifdef __native_client_codegen__
 183
 184 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 185 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 186 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 187 /* We only want to force bundle alignment for the top level instruction,    */
 188 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 189 static MonoNativeTlsKey nacl_instruction_depth;
 190
 191 static MonoNativeTlsKey nacl_rex_tag;
 192 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 193
 194 void
 195 amd64_nacl_clear_legacy_prefix_tag ()
 196 {
 197         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 198 }
 199
 200 void
 201 amd64_nacl_tag_legacy_prefix (guint8* code)
 202 {
 203         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 204                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 205 }
 206
 207 void
 208 amd64_nacl_tag_rex (guint8* code)
 209 {
 210         mono_native_tls_set_value (nacl_rex_tag, code);
 211 }
 212
 213 guint8*
 214 amd64_nacl_get_legacy_prefix_tag ()
 215 {
 216         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 217 }
 218
 219 guint8*
 220 amd64_nacl_get_rex_tag ()
 221 {
 222         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 223 }
 224
 225 /* Increment the instruction "depth" described above */
 226 void
 227 amd64_nacl_instruction_pre ()
 228 {
 229         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 230         depth++;
 231         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 232 }
 233
 234 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 235 /* alignment if depth == 0 (top level instruction)                          */
 236 /* IN: start, end    pointers to instruction beginning and end              */
 237 /* OUT: start, end   pointers to beginning and end after possible alignment */
 238 /* GLOBALS: nacl_instruction_depth     defined above                        */
 239 void
 240 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 241 {
 242         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 243         depth--;
 244         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 245
 246         g_assert ( depth >= 0 );
 247         if (depth == 0) {
 248                 uintptr_t space_in_block;
 249                 uintptr_t instlen;
 250                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 251                 /* if legacy prefix is present, and if it was emitted before */
 252                 /* the start of the instruction sequence, adjust the start   */
 253                 if (prefix != NULL && prefix < *start) {
 254                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 255                         *start = prefix;
 256                 }
 257                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 258                 instlen = (uintptr_t)(*end - *start);
 259                 /* Only check for instructions which are less than        */
 260                 /* kNaClAlignment. The only instructions that should ever */
 261                 /* be that long are call sequences, which are already     */
 262                 /* padded out to align the return to the next bundle.     */
 263                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 264                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 265                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 266                         const size_t length = (size_t)((*end)-(*start));
 267                         g_assert (length < MAX_NACL_INST_LENGTH);
 268
 269                         memcpy (copy_of_instruction, *start, length);
 270                         *start = mono_arch_nacl_pad (*start, space_in_block);
 271                         memcpy (*start, copy_of_instruction, length);
 272                         *end = *start + length;
 273                 }
 274                 amd64_nacl_clear_legacy_prefix_tag ();
 275                 amd64_nacl_tag_rex (NULL);
 276         }
 277 }
 278
 279 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 280 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 281 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 282 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 283 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 284 /* IN:      code                                                            */
 285 /*             pointer to current instruction stream (in the                */
 286 /*             middle of an instruction, after opcode is emitted)           */
 287 /*          basereg/offset/dreg                                             */
 288 /*             operands of normal membase address                           */
 289 /* OUT:     code                                                            */
 290 /*             pointer to the end of the membase/memindex emit              */
 291 /* GLOBALS: nacl_rex_tag                                                    */
 292 /*             position in instruction stream that rex prefix was emitted   */
 293 /*          nacl_legacy_prefix_tag                                          */
 294 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 295 void
 296 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 297 {
 298         gint8 true_basereg = basereg;
 299
 300         /* Cache these values, they might change  */
 301         /* as new instructions are emitted below. */
 302         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 303         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 304
 305         /* 'basereg' is given masked to 0x7 at this point, so check */
 306         /* the rex prefix to see if this is an extended register.   */
 307         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 308                 true_basereg |= 0x8;
 309         }
 310
 311 #define X86_LEA_OPCODE (0x8D)
 312
 313         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 314                 guint8* old_instruction_start;
 315
 316                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 317                 /* 32-bits of the old base register (new index register)     */
 318                 guint8 buf[32];
 319                 guint8* buf_ptr = buf;
 320                 size_t insert_len;
 321
 322                 g_assert (rex_tag != NULL);
 323
 324                 if (IS_REX(*rex_tag)) {
 325                         /* The old rex.B should be the new rex.X */
 326                         if (*rex_tag & AMD64_REX_B) {
 327                                 *rex_tag |= AMD64_REX_X;
 328                         }
 329                         /* Since our new base is %r15 set rex.B */
 330                         *rex_tag |= AMD64_REX_B;
 331                 } else {
 332                         /* Shift the instruction by one byte  */
 333                         /* so we can insert a rex prefix      */
 334                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 335                         *code += 1;
 336                         /* New rex prefix only needs rex.B for %r15 base */
 337                         *rex_tag = AMD64_REX(AMD64_REX_B);
 338                 }
 339
 340                 if (legacy_prefix_tag) {
 341                         old_instruction_start = legacy_prefix_tag;
 342                 } else {
 343                         old_instruction_start = rex_tag;
 344                 }
 345
 346                 /* Clears the upper 32-bits of the previous base register */
 347                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 348                 insert_len = buf_ptr - buf;
 349
 350                 /* Move the old instruction forward to make */
 351                 /* room for 'mov' stored in 'buf_ptr'       */
 352                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 353                 *code += insert_len;
 354                 memcpy (old_instruction_start, buf, insert_len);
 355
 356                 /* Sandboxed replacement for the normal membase_emit */
 357                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 358
 359         } else {
 360                 /* Normal default behavior, emit membase memory location */
 361                 x86_membase_emit_body (*code, dreg, basereg, offset);
 362         }
 363 }
 364
 365
 366 static inline unsigned char*
 367 amd64_skip_nops (unsigned char* code)
 368 {
 369         guint8 in_nop;
 370         do {
 371                 in_nop = 0;
 372                 if (   code[0] == 0x90) {
 373                         in_nop = 1;
 374                         code += 1;
 375                 }
 376                 if (   code[0] == 0x66 && code[1] == 0x90) {
 377                         in_nop = 1;
 378                         code += 2;
 379                 }
 380                 if (code[0] == 0x0f && code[1] == 0x1f
 381                  && code[2] == 0x00) {
 382                         in_nop = 1;
 383                         code += 3;
 384                 }
 385                 if (code[0] == 0x0f && code[1] == 0x1f
 386                  && code[2] == 0x40 && code[3] == 0x00) {
 387                         in_nop = 1;
 388                         code += 4;
 389                 }
 390                 if (code[0] == 0x0f && code[1] == 0x1f
 391                  && code[2] == 0x44 && code[3] == 0x00
 392                  && code[4] == 0x00) {
 393                         in_nop = 1;
 394                         code += 5;
 395                 }
 396                 if (code[0] == 0x66 && code[1] == 0x0f
 397                  && code[2] == 0x1f && code[3] == 0x44
 398                  && code[4] == 0x00 && code[5] == 0x00) {
 399                         in_nop = 1;
 400                         code += 6;
 401                 }
 402                 if (code[0] == 0x0f && code[1] == 0x1f
 403                  && code[2] == 0x80 && code[3] == 0x00
 404                  && code[4] == 0x00 && code[5] == 0x00
 405                  && code[6] == 0x00) {
 406                         in_nop = 1;
 407                         code += 7;
 408                 }
 409                 if (code[0] == 0x0f && code[1] == 0x1f
 410                  && code[2] == 0x84 && code[3] == 0x00
 411                  && code[4] == 0x00 && code[5] == 0x00
 412                  && code[6] == 0x00 && code[7] == 0x00) {
 413                         in_nop = 1;
 414                         code += 8;
 415                 }
 416         } while ( in_nop );
 417         return code;
 418 }
 419
 420 guint8*
 421 mono_arch_nacl_skip_nops (guint8* code)
 422 {
 423   return amd64_skip_nops(code);
 424 }
 425
 426 #endif /*__native_client_codegen__*/
 427
 428 static inline void
 429 amd64_patch (unsigned char* code, gpointer target)
 430 {
 431         guint8 rex = 0;
 432
 433 #ifdef __native_client_codegen__
 434         code = amd64_skip_nops (code);
 435 #endif
 436 #if defined(__native_client_codegen__) && defined(__native_client__)
 437         if (nacl_is_code_address (code)) {
 438                 /* For tail calls, code is patched after being installed */
 439                 /* but not through the normal "patch callsite" method.   */
 440                 unsigned char buf[kNaClAlignment];
 441                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 442                 int ret;
 443                 memcpy (buf, aligned_code, kNaClAlignment);
 444                 /* Patch a temp buffer of bundle size, */
 445                 /* then install to actual location.    */
 446                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 447                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 448                 g_assert (ret == 0);
 449                 return;
 450         }
 451         target = nacl_modify_patch_target (target);
 452 #endif
 453
 454         /* Skip REX */
 455         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 456                 rex = code [0];
 457                 code += 1;
 458         }
 459
 460         if ((code [0] & 0xf8) == 0xb8) {
 461                 /* amd64_set_reg_template */
 462                 *(guint64*)(code + 1) = (guint64)target;
 463         }
 464         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 465                 /* mov 0(%rip), %dreg */
 466                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 467         }
 468         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 469                 /* call *<OFFSET>(%rip) */
 470                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 471         }
 472         else if (code [0] == 0xe8) {
 473                 /* call <DISP> */
 474                 gint64 disp = (guint8*)target - (guint8*)code;
 475                 g_assert (amd64_is_imm32 (disp));
 476                 x86_patch (code, (unsigned char*)target);
 477         }
 478         else
 479                 x86_patch (code, (unsigned char*)target);
 480 }
 481
 482 void
 483 mono_amd64_patch (unsigned char* code, gpointer target)
 484 {
 485         amd64_patch (code, target);
 486 }
 487
 488 typedef enum {
 489         ArgInIReg,
 490         ArgInFloatSSEReg,
 491         ArgInDoubleSSEReg,
 492         ArgOnStack,
 493         ArgValuetypeInReg,
 494         ArgValuetypeAddrInIReg,
 495         ArgNone /* only in pair_storage */
 496 } ArgStorage;
 497
 498 typedef struct {
 499         gint16 offset;
 500         gint8  reg;
 501         ArgStorage storage;
 502
 503         /* Only if storage == ArgValuetypeInReg */
 504         ArgStorage pair_storage [2];
 505         gint8 pair_regs [2];
 506         /* The size of each pair */
 507         int pair_size [2];
 508         int nregs;
 509 } ArgInfo;
 510
 511 typedef struct {
 512         int nargs;
 513         guint32 stack_usage;
 514         guint32 reg_usage;
 515         guint32 freg_usage;
 516         gboolean need_stack_align;
 517         gboolean vtype_retaddr;
 518         /* The index of the vret arg in the argument list */
 519         int vret_arg_index;
 520         ArgInfo ret;
 521         ArgInfo sig_cookie;
 522         ArgInfo args [1];
 523 } CallInfo;
 524
 525 #define DEBUG(a) if (cfg->verbose_level > 1) a
 526
 527 #ifdef TARGET_WIN32
 528 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 529
 530 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 531 #else
 532 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 533
 534  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 535 #endif
 536
 537 static void inline
 538 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 539 {
 540     ainfo->offset = *stack_size;
 541
 542     if (*gr >= PARAM_REGS) {
 543                 ainfo->storage = ArgOnStack;
 544                 /* Since the same stack slot size is used for all arg */
 545                 /*  types, it needs to be big enough to hold them all */
 546                 (*stack_size) += sizeof(mgreg_t);
 547     }
 548     else {
 549                 ainfo->storage = ArgInIReg;
 550                 ainfo->reg = param_regs [*gr];
 551                 (*gr) ++;
 552     }
 553 }
 554
 555 #ifdef TARGET_WIN32
 556 #define FLOAT_PARAM_REGS 4
 557 #else
 558 #define FLOAT_PARAM_REGS 8
 559 #endif
 560
 561 static void inline
 562 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 563 {
 564     ainfo->offset = *stack_size;
 565
 566     if (*gr >= FLOAT_PARAM_REGS) {
 567                 ainfo->storage = ArgOnStack;
 568                 /* Since the same stack slot size is used for both float */
 569                 /*  types, it needs to be big enough to hold them both */
 570                 (*stack_size) += sizeof(mgreg_t);
 571     }
 572     else {
 573                 /* A double register */
 574                 if (is_double)
 575                         ainfo->storage = ArgInDoubleSSEReg;
 576                 else
 577                         ainfo->storage = ArgInFloatSSEReg;
 578                 ainfo->reg = *gr;
 579                 (*gr) += 1;
 580     }
 581 }
 582
 583 typedef enum ArgumentClass {
 584         ARG_CLASS_NO_CLASS,
 585         ARG_CLASS_MEMORY,
 586         ARG_CLASS_INTEGER,
 587         ARG_CLASS_SSE
 588 } ArgumentClass;
 589
 590 static ArgumentClass
 591 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 592 {
 593         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 594         MonoType *ptype;
 595
 596         ptype = mini_get_underlying_type (type);
 597         switch (ptype->type) {
 598         case MONO_TYPE_I1:
 599         case MONO_TYPE_U1:
 600         case MONO_TYPE_I2:
 601         case MONO_TYPE_U2:
 602         case MONO_TYPE_I4:
 603         case MONO_TYPE_U4:
 604         case MONO_TYPE_I:
 605         case MONO_TYPE_U:
 606         case MONO_TYPE_STRING:
 607         case MONO_TYPE_OBJECT:
 608         case MONO_TYPE_CLASS:
 609         case MONO_TYPE_SZARRAY:
 610         case MONO_TYPE_PTR:
 611         case MONO_TYPE_FNPTR:
 612         case MONO_TYPE_ARRAY:
 613         case MONO_TYPE_I8:
 614         case MONO_TYPE_U8:
 615                 class2 = ARG_CLASS_INTEGER;
 616                 break;
 617         case MONO_TYPE_R4:
 618         case MONO_TYPE_R8:
 619 #ifdef TARGET_WIN32
 620                 class2 = ARG_CLASS_INTEGER;
 621 #else
 622                 class2 = ARG_CLASS_SSE;
 623 #endif
 624                 break;
 625
 626         case MONO_TYPE_TYPEDBYREF:
 627                 g_assert_not_reached ();
 628
 629         case MONO_TYPE_GENERICINST:
 630                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 631                         class2 = ARG_CLASS_INTEGER;
 632                         break;
 633                 }
 634                 /* fall through */
 635         case MONO_TYPE_VALUETYPE: {
 636                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 637                 int i;
 638
 639                 for (i = 0; i < info->num_fields; ++i) {
 640                         class2 = class1;
 641                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 642                 }
 643                 break;
 644         }
 645         default:
 646                 g_assert_not_reached ();
 647         }
 648
 649         /* Merge */
 650         if (class1 == class2)
 651                 ;
 652         else if (class1 == ARG_CLASS_NO_CLASS)
 653                 class1 = class2;
 654         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 655                 class1 = ARG_CLASS_MEMORY;
 656         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 657                 class1 = ARG_CLASS_INTEGER;
 658         else
 659                 class1 = ARG_CLASS_SSE;
 660
 661         return class1;
 662 }
 663 #ifdef __native_client_codegen__
 664
 665 /* Default alignment for Native Client is 32-byte. */
 666 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 667
 668 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 669 /* Check that alignment doesn't cross an alignment boundary.             */
 670 guint8*
 671 mono_arch_nacl_pad(guint8 *code, int pad)
 672 {
 673         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 674
 675         if (pad == 0) return code;
 676         /* assertion: alignment cannot cross a block boundary */
 677         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 678                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 679         while (pad >= kMaxPadding) {
 680                 amd64_padding (code, kMaxPadding);
 681                 pad -= kMaxPadding;
 682         }
 683         if (pad != 0) amd64_padding (code, pad);
 684         return code;
 685 }
 686 #endif
 687
 688 static int
 689 count_fields_nested (MonoClass *klass)
 690 {
 691         MonoMarshalType *info;
 692         int i, count;
 693
 694         info = mono_marshal_load_type_info (klass);
 695         g_assert(info);
 696         count = 0;
 697         for (i = 0; i < info->num_fields; ++i) {
 698                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 699                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 700                 else
 701                         count ++;
 702         }
 703         return count;
 704 }
 705
 706 static int
 707 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 708 {
 709         MonoMarshalType *info;
 710         int i;
 711
 712         info = mono_marshal_load_type_info (klass);
 713         g_assert(info);
 714         for (i = 0; i < info->num_fields; ++i) {
 715                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 716                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 717                 } else {
 718                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 719                         fields [index].offset += offset;
 720                         index ++;
 721                 }
 722         }
 723         return index;
 724 }
 725
 726 static void
 727 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 728                            gboolean is_return,
 729                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 730 {
 731         guint32 size, quad, nquads, i, nfields;
 732         /* Keep track of the size used in each quad so we can */
 733         /* use the right size when copying args/return vars.  */
 734         guint32 quadsize [2] = {8, 8};
 735         ArgumentClass args [2];
 736         MonoMarshalType *info = NULL;
 737         MonoMarshalField *fields = NULL;
 738         MonoClass *klass;
 739         gboolean pass_on_stack = FALSE;
 740
 741         klass = mono_class_from_mono_type (type);
 742         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 743 #ifndef TARGET_WIN32
 744         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 745                 /* We pass and return vtypes of size 8 in a register */
 746         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 747                 pass_on_stack = TRUE;
 748         }
 749 #else
 750         if (!sig->pinvoke) {
 751                 pass_on_stack = TRUE;
 752         }
 753 #endif
 754
 755         /* If this struct can't be split up naturally into 8-byte */
 756         /* chunks (registers), pass it on the stack.              */
 757         if (sig->pinvoke && !pass_on_stack) {
 758                 guint32 align;
 759                 guint32 field_size;
 760
 761                 info = mono_marshal_load_type_info (klass);
 762                 g_assert (info);
 763
 764                 /*
 765                  * Collect field information recursively to be able to
 766                  * handle nested structures.
 767                  */
 768                 nfields = count_fields_nested (klass);
 769                 fields = g_new0 (MonoMarshalField, nfields);
 770                 collect_field_info_nested (klass, fields, 0, 0);
 771
 772                 for (i = 0; i < nfields; ++i) {
 773                         field_size = mono_marshal_type_size (fields [i].field->type,
 774                                                            fields [i].mspec,
 775                                                            &align, TRUE, klass->unicode);
 776                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 777                                 pass_on_stack = TRUE;
 778                                 break;
 779                         }
 780                 }
 781         }
 782
 783 #ifndef TARGET_WIN32
 784         if (size == 0) {
 785                 ainfo->storage = ArgValuetypeInReg;
 786                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 787                 return;
 788         }
 789 #endif
 790
 791         if (pass_on_stack) {
 792                 /* Allways pass in memory */
 793                 ainfo->offset = *stack_size;
 794                 *stack_size += ALIGN_TO (size, 8);
 795                 ainfo->storage = ArgOnStack;
 796
 797                 g_free (fields);
 798                 return;
 799         }
 800
 801         /* FIXME: Handle structs smaller than 8 bytes */
 802         //if ((size % 8) != 0)
 803         //      NOT_IMPLEMENTED;
 804
 805         if (size > 8)
 806                 nquads = 2;
 807         else
 808                 nquads = 1;
 809
 810         if (!sig->pinvoke) {
 811                 int n = mono_class_value_size (klass, NULL);
 812
 813                 quadsize [0] = n >= 8 ? 8 : n;
 814                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 815
 816                 /* Always pass in 1 or 2 integer registers */
 817                 args [0] = ARG_CLASS_INTEGER;
 818                 args [1] = ARG_CLASS_INTEGER;
 819                 /* Only the simplest cases are supported */
 820                 if (is_return && nquads != 1) {
 821                         args [0] = ARG_CLASS_MEMORY;
 822                         args [1] = ARG_CLASS_MEMORY;
 823                 }
 824         } else {
 825                 /*
 826                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 827                  * The X87 and SSEUP stuff is left out since there are no such types in
 828                  * the CLR.
 829                  */
 830                 g_assert (info);
 831
 832                 if (!fields) {
 833                         ainfo->storage = ArgValuetypeInReg;
 834                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 835                         return;
 836                 }
 837
 838 #ifndef TARGET_WIN32
 839                 if (info->native_size > 16) {
 840                         ainfo->offset = *stack_size;
 841                         *stack_size += ALIGN_TO (info->native_size, 8);
 842                         ainfo->storage = ArgOnStack;
 843
 844                         g_free (fields);
 845                         return;
 846                 }
 847 #else
 848                 switch (info->native_size) {
 849                 case 1: case 2: case 4: case 8:
 850                         break;
 851                 default:
 852                         if (is_return) {
 853                                 ainfo->storage = ArgOnStack;
 854                                 ainfo->offset = *stack_size;
 855                                 *stack_size += ALIGN_TO (info->native_size, 8);
 856                         }
 857                         else {
 858                                 ainfo->storage = ArgValuetypeAddrInIReg;
 859
 860                                 if (*gr < PARAM_REGS) {
 861                                         ainfo->pair_storage [0] = ArgInIReg;
 862                                         ainfo->pair_regs [0] = param_regs [*gr];
 863                                         (*gr) ++;
 864                                 }
 865                                 else {
 866                                         ainfo->pair_storage [0] = ArgOnStack;
 867                                         ainfo->offset = *stack_size;
 868                                         *stack_size += 8;
 869                                 }
 870                         }
 871
 872                         g_free (fields);
 873                         return;
 874                 }
 875 #endif
 876
 877                 args [0] = ARG_CLASS_NO_CLASS;
 878                 args [1] = ARG_CLASS_NO_CLASS;
 879                 for (quad = 0; quad < nquads; ++quad) {
 880                         int size;
 881                         guint32 align;
 882                         ArgumentClass class1;
 883
 884                         if (nfields == 0)
 885                                 class1 = ARG_CLASS_MEMORY;
 886                         else
 887                                 class1 = ARG_CLASS_NO_CLASS;
 888                         for (i = 0; i < nfields; ++i) {
 889                                 size = mono_marshal_type_size (fields [i].field->type,
 890                                                                                            fields [i].mspec,
 891                                                                                            &align, TRUE, klass->unicode);
 892                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 893                                         /* Unaligned field */
 894                                         NOT_IMPLEMENTED;
 895                                 }
 896
 897                                 /* Skip fields in other quad */
 898                                 if ((quad == 0) && (fields [i].offset >= 8))
 899                                         continue;
 900                                 if ((quad == 1) && (fields [i].offset < 8))
 901                                         continue;
 902
 903                                 /* How far into this quad this data extends.*/
 904                                 /* (8 is size of quad) */
 905                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 906
 907                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 908                         }
 909                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 910                         args [quad] = class1;
 911                 }
 912         }
 913
 914         g_free (fields);
 915
 916         /* Post merger cleanup */
 917         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 918                 args [0] = args [1] = ARG_CLASS_MEMORY;
 919
 920         /* Allocate registers */
 921         {
 922                 int orig_gr = *gr;
 923                 int orig_fr = *fr;
 924
 925                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 926                         quadsize [0] ++;
 927                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 928                         quadsize [1] ++;
 929
 930                 ainfo->storage = ArgValuetypeInReg;
 931                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 932                 g_assert (quadsize [0] <= 8);
 933                 g_assert (quadsize [1] <= 8);
 934                 ainfo->pair_size [0] = quadsize [0];
 935                 ainfo->pair_size [1] = quadsize [1];
 936                 ainfo->nregs = nquads;
 937                 for (quad = 0; quad < nquads; ++quad) {
 938                         switch (args [quad]) {
 939                         case ARG_CLASS_INTEGER:
 940                                 if (*gr >= PARAM_REGS)
 941                                         args [quad] = ARG_CLASS_MEMORY;
 942                                 else {
 943                                         ainfo->pair_storage [quad] = ArgInIReg;
 944                                         if (is_return)
 945                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 946                                         else
 947                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 948                                         (*gr) ++;
 949                                 }
 950                                 break;
 951                         case ARG_CLASS_SSE:
 952                                 if (*fr >= FLOAT_PARAM_REGS)
 953                                         args [quad] = ARG_CLASS_MEMORY;
 954                                 else {
 955                                         if (quadsize[quad] <= 4)
 956                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 957                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 958                                         ainfo->pair_regs [quad] = *fr;
 959                                         (*fr) ++;
 960                                 }
 961                                 break;
 962                         case ARG_CLASS_MEMORY:
 963                                 break;
 964                         default:
 965                                 g_assert_not_reached ();
 966                         }
 967                 }
 968
 969                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 970                         /* Revert possible register assignments */
 971                         *gr = orig_gr;
 972                         *fr = orig_fr;
 973
 974                         ainfo->offset = *stack_size;
 975                         if (sig->pinvoke)
 976                                 *stack_size += ALIGN_TO (info->native_size, 8);
 977                         else
 978                                 *stack_size += nquads * sizeof(mgreg_t);
 979                         ainfo->storage = ArgOnStack;
 980                 }
 981         }
 982 }
 983
 984 /*
 985  * get_call_info:
 986  *
 987  *  Obtain information about a call according to the calling convention.
 988  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 989  * Draft Version 0.23" document for more information.
 990  */
 991 static CallInfo*
 992 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 993 {
 994         guint32 i, gr, fr, pstart;
 995         MonoType *ret_type;
 996         int n = sig->hasthis + sig->param_count;
 997         guint32 stack_size = 0;
 998         CallInfo *cinfo;
 999         gboolean is_pinvoke = sig->pinvoke;
1000
1001         if (mp)
1002                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1003         else
1004                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1005
1006         cinfo->nargs = n;
1007
1008         gr = 0;
1009         fr = 0;
1010
1011 #ifdef TARGET_WIN32
1012         /* Reserve space where the callee can save the argument registers */
1013         stack_size = 4 * sizeof (mgreg_t);
1014 #endif
1015
1016         /* return value */
1017         ret_type = mini_get_underlying_type (sig->ret);
1018         switch (ret_type->type) {
1019         case MONO_TYPE_I1:
1020         case MONO_TYPE_U1:
1021         case MONO_TYPE_I2:
1022         case MONO_TYPE_U2:
1023         case MONO_TYPE_I4:
1024         case MONO_TYPE_U4:
1025         case MONO_TYPE_I:
1026         case MONO_TYPE_U:
1027         case MONO_TYPE_PTR:
1028         case MONO_TYPE_FNPTR:
1029         case MONO_TYPE_CLASS:
1030         case MONO_TYPE_OBJECT:
1031         case MONO_TYPE_SZARRAY:
1032         case MONO_TYPE_ARRAY:
1033         case MONO_TYPE_STRING:
1034                 cinfo->ret.storage = ArgInIReg;
1035                 cinfo->ret.reg = AMD64_RAX;
1036                 break;
1037         case MONO_TYPE_U8:
1038         case MONO_TYPE_I8:
1039                 cinfo->ret.storage = ArgInIReg;
1040                 cinfo->ret.reg = AMD64_RAX;
1041                 break;
1042         case MONO_TYPE_R4:
1043                 cinfo->ret.storage = ArgInFloatSSEReg;
1044                 cinfo->ret.reg = AMD64_XMM0;
1045                 break;
1046         case MONO_TYPE_R8:
1047                 cinfo->ret.storage = ArgInDoubleSSEReg;
1048                 cinfo->ret.reg = AMD64_XMM0;
1049                 break;
1050         case MONO_TYPE_GENERICINST:
1051                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1052                         cinfo->ret.storage = ArgInIReg;
1053                         cinfo->ret.reg = AMD64_RAX;
1054                         break;
1055                 }
1056                 /* fall through */
1057 #if defined( __native_client_codegen__ )
1058         case MONO_TYPE_TYPEDBYREF:
1059 #endif
1060         case MONO_TYPE_VALUETYPE: {
1061                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1062
1063                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1064                 if (cinfo->ret.storage == ArgOnStack) {
1065                         cinfo->vtype_retaddr = TRUE;
1066                         /* The caller passes the address where the value is stored */
1067                 }
1068                 break;
1069         }
1070 #if !defined( __native_client_codegen__ )
1071         case MONO_TYPE_TYPEDBYREF:
1072                 /* Same as a valuetype with size 24 */
1073                 cinfo->vtype_retaddr = TRUE;
1074                 break;
1075 #endif
1076         case MONO_TYPE_VOID:
1077                 break;
1078         default:
1079                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1080         }
1081
1082         pstart = 0;
1083         /*
1084          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1085          * the first argument, allowing 'this' to be always passed in the first arg reg.
1086          * Also do this if the first argument is a reference type, since virtual calls
1087          * are sometimes made using calli without sig->hasthis set, like in the delegate
1088          * invoke wrappers.
1089          */
1090         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1091                 if (sig->hasthis) {
1092                         add_general (&gr, &stack_size, cinfo->args + 0);
1093                 } else {
1094                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1095                         pstart = 1;
1096                 }
1097                 add_general (&gr, &stack_size, &cinfo->ret);
1098                 cinfo->vret_arg_index = 1;
1099         } else {
1100                 /* this */
1101                 if (sig->hasthis)
1102                         add_general (&gr, &stack_size, cinfo->args + 0);
1103
1104                 if (cinfo->vtype_retaddr)
1105                         add_general (&gr, &stack_size, &cinfo->ret);
1106         }
1107
1108         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1109                 gr = PARAM_REGS;
1110                 fr = FLOAT_PARAM_REGS;
1111
1112                 /* Emit the signature cookie just before the implicit arguments */
1113                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1114         }
1115
1116         for (i = pstart; i < sig->param_count; ++i) {
1117                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1118                 MonoType *ptype;
1119
1120 #ifdef TARGET_WIN32
1121                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1122                 if (gr > fr)
1123                         fr = gr;
1124                 else if (fr > gr)
1125                         gr = fr;
1126 #endif
1127
1128                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1129                         /* We allways pass the sig cookie on the stack for simplicity */
1130                         /*
1131                          * Prevent implicit arguments + the sig cookie from being passed
1132                          * in registers.
1133                          */
1134                         gr = PARAM_REGS;
1135                         fr = FLOAT_PARAM_REGS;
1136
1137                         /* Emit the signature cookie just before the implicit arguments */
1138                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1139                 }
1140
1141                 ptype = mini_get_underlying_type (sig->params [i]);
1142                 switch (ptype->type) {
1143                 case MONO_TYPE_I1:
1144                 case MONO_TYPE_U1:
1145                         add_general (&gr, &stack_size, ainfo);
1146                         break;
1147                 case MONO_TYPE_I2:
1148                 case MONO_TYPE_U2:
1149                         add_general (&gr, &stack_size, ainfo);
1150                         break;
1151                 case MONO_TYPE_I4:
1152                 case MONO_TYPE_U4:
1153                         add_general (&gr, &stack_size, ainfo);
1154                         break;
1155                 case MONO_TYPE_I:
1156                 case MONO_TYPE_U:
1157                 case MONO_TYPE_PTR:
1158                 case MONO_TYPE_FNPTR:
1159                 case MONO_TYPE_CLASS:
1160                 case MONO_TYPE_OBJECT:
1161                 case MONO_TYPE_STRING:
1162                 case MONO_TYPE_SZARRAY:
1163                 case MONO_TYPE_ARRAY:
1164                         add_general (&gr, &stack_size, ainfo);
1165                         break;
1166                 case MONO_TYPE_GENERICINST:
1167                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1168                                 add_general (&gr, &stack_size, ainfo);
1169                                 break;
1170                         }
1171                         /* fall through */
1172                 case MONO_TYPE_VALUETYPE:
1173                 case MONO_TYPE_TYPEDBYREF:
1174                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1175                         break;
1176                 case MONO_TYPE_U8:
1177
1178                 case MONO_TYPE_I8:
1179                         add_general (&gr, &stack_size, ainfo);
1180                         break;
1181                 case MONO_TYPE_R4:
1182                         add_float (&fr, &stack_size, ainfo, FALSE);
1183                         break;
1184                 case MONO_TYPE_R8:
1185                         add_float (&fr, &stack_size, ainfo, TRUE);
1186                         break;
1187                 default:
1188                         g_assert_not_reached ();
1189                 }
1190         }
1191
1192         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1193                 gr = PARAM_REGS;
1194                 fr = FLOAT_PARAM_REGS;
1195
1196                 /* Emit the signature cookie just before the implicit arguments */
1197                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1198         }
1199
1200         cinfo->stack_usage = stack_size;
1201         cinfo->reg_usage = gr;
1202         cinfo->freg_usage = fr;
1203         return cinfo;
1204 }
1205
1206 /*
1207  * mono_arch_get_argument_info:
1208  * @csig:  a method signature
1209  * @param_count: the number of parameters to consider
1210  * @arg_info: an array to store the result infos
1211  *
1212  * Gathers information on parameters such as size, alignment and
1213  * padding. arg_info should be large enought to hold param_count + 1 entries.
1214  *
1215  * Returns the size of the argument area on the stack.
1216  */
1217 int
1218 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1219 {
1220         int k;
1221         CallInfo *cinfo = get_call_info (NULL, csig);
1222         guint32 args_size = cinfo->stack_usage;
1223
1224         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1225         if (csig->hasthis) {
1226                 arg_info [0].offset = 0;
1227         }
1228
1229         for (k = 0; k < param_count; k++) {
1230                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1231                 /* FIXME: */
1232                 arg_info [k + 1].size = 0;
1233         }
1234
1235         g_free (cinfo);
1236
1237         return args_size;
1238 }
1239
1240 gboolean
1241 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1242 {
1243         CallInfo *c1, *c2;
1244         gboolean res;
1245         MonoType *callee_ret;
1246
1247         c1 = get_call_info (NULL, caller_sig);
1248         c2 = get_call_info (NULL, callee_sig);
1249         res = c1->stack_usage >= c2->stack_usage;
1250         callee_ret = mini_get_underlying_type (callee_sig->ret);
1251         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1252                 /* An address on the callee's stack is passed as the first argument */
1253                 res = FALSE;
1254
1255         g_free (c1);
1256         g_free (c2);
1257
1258         return res;
1259 }
1260
1261 /*
1262  * Initialize the cpu to execute managed code.
1263  */
1264 void
1265 mono_arch_cpu_init (void)
1266 {
1267 #ifndef _MSC_VER
1268         guint16 fpcw;
1269
1270         /* spec compliance requires running with double precision */
1271         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1272         fpcw &= ~X86_FPCW_PRECC_MASK;
1273         fpcw |= X86_FPCW_PREC_DOUBLE;
1274         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1275         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1276 #else
1277         /* TODO: This is crashing on Win64 right now.
1278         * _control87 (_PC_53, MCW_PC);
1279         */
1280 #endif
1281 }
1282
1283 /*
1284  * Initialize architecture specific code.
1285  */
1286 void
1287 mono_arch_init (void)
1288 {
1289         int flags;
1290
1291         mono_mutex_init_recursive (&mini_arch_mutex);
1292 #if defined(__native_client_codegen__)
1293         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1294         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1295         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1296         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1297 #endif
1298
1299 #ifdef MONO_ARCH_NOMAP32BIT
1300         flags = MONO_MMAP_READ;
1301         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1302         breakpoint_size = 13;
1303         breakpoint_fault_size = 3;
1304 #else
1305         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1306         /* amd64_mov_reg_mem () */
1307         breakpoint_size = 8;
1308         breakpoint_fault_size = 8;
1309 #endif
1310
1311         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1312         single_step_fault_size = 4;
1313
1314         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1315         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1316         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1317
1318         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1319         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1320         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1321         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1322 }
1323
1324 /*
1325  * Cleanup architecture specific code.
1326  */
1327 void
1328 mono_arch_cleanup (void)
1329 {
1330         mono_mutex_destroy (&mini_arch_mutex);
1331 #if defined(__native_client_codegen__)
1332         mono_native_tls_free (nacl_instruction_depth);
1333         mono_native_tls_free (nacl_rex_tag);
1334         mono_native_tls_free (nacl_legacy_prefix_tag);
1335 #endif
1336 }
1337
1338 /*
1339  * This function returns the optimizations supported on this cpu.
1340  */
1341 guint32
1342 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1343 {
1344         guint32 opts = 0;
1345
1346         *exclude_mask = 0;
1347
1348         if (mono_hwcap_x86_has_cmov) {
1349                 opts |= MONO_OPT_CMOV;
1350
1351                 if (mono_hwcap_x86_has_fcmov)
1352                         opts |= MONO_OPT_FCMOV;
1353                 else
1354                         *exclude_mask |= MONO_OPT_FCMOV;
1355         } else {
1356                 *exclude_mask |= MONO_OPT_CMOV;
1357         }
1358
1359         return opts;
1360 }
1361
1362 /*
1363  * This function test for all SSE functions supported.
1364  *
1365  * Returns a bitmask corresponding to all supported versions.
1366  *
1367  */
1368 guint32
1369 mono_arch_cpu_enumerate_simd_versions (void)
1370 {
1371         guint32 sse_opts = 0;
1372
1373         if (mono_hwcap_x86_has_sse1)
1374                 sse_opts |= SIMD_VERSION_SSE1;
1375
1376         if (mono_hwcap_x86_has_sse2)
1377                 sse_opts |= SIMD_VERSION_SSE2;
1378
1379         if (mono_hwcap_x86_has_sse3)
1380                 sse_opts |= SIMD_VERSION_SSE3;
1381
1382         if (mono_hwcap_x86_has_ssse3)
1383                 sse_opts |= SIMD_VERSION_SSSE3;
1384
1385         if (mono_hwcap_x86_has_sse41)
1386                 sse_opts |= SIMD_VERSION_SSE41;
1387
1388         if (mono_hwcap_x86_has_sse42)
1389                 sse_opts |= SIMD_VERSION_SSE42;
1390
1391         if (mono_hwcap_x86_has_sse4a)
1392                 sse_opts |= SIMD_VERSION_SSE4a;
1393
1394         return sse_opts;
1395 }
1396
1397 #ifndef DISABLE_JIT
1398
1399 GList *
1400 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1401 {
1402         GList *vars = NULL;
1403         int i;
1404
1405         for (i = 0; i < cfg->num_varinfo; i++) {
1406                 MonoInst *ins = cfg->varinfo [i];
1407                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1408
1409                 /* unused vars */
1410                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1411                         continue;
1412
1413                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1414                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1415                         continue;
1416
1417                 if (mono_is_regsize_var (ins->inst_vtype)) {
1418                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1419                         g_assert (i == vmv->idx);
1420                         vars = g_list_prepend (vars, vmv);
1421                 }
1422         }
1423
1424         vars = mono_varlist_sort (cfg, vars, 0);
1425
1426         return vars;
1427 }
1428
1429 /**
1430  * mono_arch_compute_omit_fp:
1431  *
1432  *   Determine whenever the frame pointer can be eliminated.
1433  */
1434 static void
1435 mono_arch_compute_omit_fp (MonoCompile *cfg)
1436 {
1437         MonoMethodSignature *sig;
1438         MonoMethodHeader *header;
1439         int i, locals_size;
1440         CallInfo *cinfo;
1441
1442         if (cfg->arch.omit_fp_computed)
1443                 return;
1444
1445         header = cfg->header;
1446
1447         sig = mono_method_signature (cfg->method);
1448
1449         if (!cfg->arch.cinfo)
1450                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1451         cinfo = cfg->arch.cinfo;
1452
1453         /*
1454          * FIXME: Remove some of the restrictions.
1455          */
1456         cfg->arch.omit_fp = TRUE;
1457         cfg->arch.omit_fp_computed = TRUE;
1458
1459 #ifdef __native_client_codegen__
1460         /* NaCl modules may not change the value of RBP, so it cannot be */
1461         /* used as a normal register, but it can be used as a frame pointer*/
1462         cfg->disable_omit_fp = TRUE;
1463         cfg->arch.omit_fp = FALSE;
1464 #endif
1465
1466         if (cfg->disable_omit_fp)
1467                 cfg->arch.omit_fp = FALSE;
1468
1469         if (!debug_omit_fp ())
1470                 cfg->arch.omit_fp = FALSE;
1471         /*
1472         if (cfg->method->save_lmf)
1473                 cfg->arch.omit_fp = FALSE;
1474         */
1475         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1476                 cfg->arch.omit_fp = FALSE;
1477         if (header->num_clauses)
1478                 cfg->arch.omit_fp = FALSE;
1479         if (cfg->param_area)
1480                 cfg->arch.omit_fp = FALSE;
1481         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1482                 cfg->arch.omit_fp = FALSE;
1483         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1484                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1485                 cfg->arch.omit_fp = FALSE;
1486         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1487                 ArgInfo *ainfo = &cinfo->args [i];
1488
1489                 if (ainfo->storage == ArgOnStack) {
1490                         /*
1491                          * The stack offset can only be determined when the frame
1492                          * size is known.
1493                          */
1494                         cfg->arch.omit_fp = FALSE;
1495                 }
1496         }
1497
1498         locals_size = 0;
1499         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1500                 MonoInst *ins = cfg->varinfo [i];
1501                 int ialign;
1502
1503                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1504         }
1505 }
1506
1507 GList *
1508 mono_arch_get_global_int_regs (MonoCompile *cfg)
1509 {
1510         GList *regs = NULL;
1511
1512         mono_arch_compute_omit_fp (cfg);
1513
1514         if (cfg->arch.omit_fp)
1515                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1516
1517         /* We use the callee saved registers for global allocation */
1518         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1519         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1520         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1521         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1522 #ifndef __native_client_codegen__
1523         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1524 #endif
1525 #ifdef TARGET_WIN32
1526         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1527         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1528 #endif
1529
1530         return regs;
1531 }
1532
1533 GList*
1534 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1535 {
1536         GList *regs = NULL;
1537         int i;
1538
1539         /* All XMM registers */
1540         for (i = 0; i < 16; ++i)
1541                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1542
1543         return regs;
1544 }
1545
1546 GList*
1547 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1548 {
1549         static GList *r = NULL;
1550
1551         if (r == NULL) {
1552                 GList *regs = NULL;
1553
1554                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1555                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1556                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1557                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1558                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1559 #ifndef __native_client_codegen__
1560                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1561 #endif
1562
1563                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1564                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1565                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1566                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1567                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1568                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1569                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1570                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1571
1572                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1573         }
1574
1575         return r;
1576 }
1577
1578 GList*
1579 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1580 {
1581         int i;
1582         static GList *r = NULL;
1583
1584         if (r == NULL) {
1585                 GList *regs = NULL;
1586
1587                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1588                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1589
1590                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1591         }
1592
1593         return r;
1594 }
1595
1596 /*
1597  * mono_arch_regalloc_cost:
1598  *
1599  *  Return the cost, in number of memory references, of the action of
1600  * allocating the variable VMV into a register during global register
1601  * allocation.
1602  */
1603 guint32
1604 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1605 {
1606         MonoInst *ins = cfg->varinfo [vmv->idx];
1607
1608         if (cfg->method->save_lmf)
1609                 /* The register is already saved */
1610                 /* substract 1 for the invisible store in the prolog */
1611                 return (ins->opcode == OP_ARG) ? 0 : 1;
1612         else
1613                 /* push+pop */
1614                 return (ins->opcode == OP_ARG) ? 1 : 2;
1615 }
1616
1617 /*
1618  * mono_arch_fill_argument_info:
1619  *
1620  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1621  * of the method.
1622  */
1623 void
1624 mono_arch_fill_argument_info (MonoCompile *cfg)
1625 {
1626         MonoType *sig_ret;
1627         MonoMethodSignature *sig;
1628         MonoInst *ins;
1629         int i;
1630         CallInfo *cinfo;
1631
1632         sig = mono_method_signature (cfg->method);
1633
1634         cinfo = cfg->arch.cinfo;
1635         sig_ret = mini_get_underlying_type (sig->ret);
1636
1637         /*
1638          * Contrary to mono_arch_allocate_vars (), the information should describe
1639          * where the arguments are at the beginning of the method, not where they can be
1640          * accessed during the execution of the method. The later makes no sense for the
1641          * global register allocator, since a variable can be in more than one location.
1642          */
1643         if (sig_ret->type != MONO_TYPE_VOID) {
1644                 switch (cinfo->ret.storage) {
1645                 case ArgInIReg:
1646                 case ArgInFloatSSEReg:
1647                 case ArgInDoubleSSEReg:
1648                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1649                                 cfg->vret_addr->opcode = OP_REGVAR;
1650                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1651                         }
1652                         else {
1653                                 cfg->ret->opcode = OP_REGVAR;
1654                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1655                         }
1656                         break;
1657                 case ArgValuetypeInReg:
1658                         cfg->ret->opcode = OP_REGOFFSET;
1659                         cfg->ret->inst_basereg = -1;
1660                         cfg->ret->inst_offset = -1;
1661                         break;
1662                 default:
1663                         g_assert_not_reached ();
1664                 }
1665         }
1666
1667         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1668                 ArgInfo *ainfo = &cinfo->args [i];
1669
1670                 ins = cfg->args [i];
1671
1672                 switch (ainfo->storage) {
1673                 case ArgInIReg:
1674                 case ArgInFloatSSEReg:
1675                 case ArgInDoubleSSEReg:
1676                         ins->opcode = OP_REGVAR;
1677                         ins->inst_c0 = ainfo->reg;
1678                         break;
1679                 case ArgOnStack:
1680                         ins->opcode = OP_REGOFFSET;
1681                         ins->inst_basereg = -1;
1682                         ins->inst_offset = -1;
1683                         break;
1684                 case ArgValuetypeInReg:
1685                         /* Dummy */
1686                         ins->opcode = OP_NOP;
1687                         break;
1688                 default:
1689                         g_assert_not_reached ();
1690                 }
1691         }
1692 }
1693
1694 void
1695 mono_arch_allocate_vars (MonoCompile *cfg)
1696 {
1697         MonoType *sig_ret;
1698         MonoMethodSignature *sig;
1699         MonoInst *ins;
1700         int i, offset;
1701         guint32 locals_stack_size, locals_stack_align;
1702         gint32 *offsets;
1703         CallInfo *cinfo;
1704
1705         sig = mono_method_signature (cfg->method);
1706
1707         cinfo = cfg->arch.cinfo;
1708         sig_ret = mini_get_underlying_type (sig->ret);
1709
1710         mono_arch_compute_omit_fp (cfg);
1711
1712         /*
1713          * We use the ABI calling conventions for managed code as well.
1714          * Exception: valuetypes are only sometimes passed or returned in registers.
1715          */
1716
1717         /*
1718          * The stack looks like this:
1719          * <incoming arguments passed on the stack>
1720          * <return value>
1721          * <lmf/caller saved registers>
1722          * <locals>
1723          * <spill area>
1724          * <localloc area>  -> grows dynamically
1725          * <params area>
1726          */
1727
1728         if (cfg->arch.omit_fp) {
1729                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1730                 cfg->frame_reg = AMD64_RSP;
1731                 offset = 0;
1732         } else {
1733                 /* Locals are allocated backwards from %fp */
1734                 cfg->frame_reg = AMD64_RBP;
1735                 offset = 0;
1736         }
1737
1738         cfg->arch.saved_iregs = cfg->used_int_regs;
1739         if (cfg->method->save_lmf)
1740                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1741                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1742
1743         if (cfg->arch.omit_fp)
1744                 cfg->arch.reg_save_area_offset = offset;
1745         /* Reserve space for callee saved registers */
1746         for (i = 0; i < AMD64_NREG; ++i)
1747                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1748                         offset += sizeof(mgreg_t);
1749                 }
1750         if (!cfg->arch.omit_fp)
1751                 cfg->arch.reg_save_area_offset = -offset;
1752
1753         if (sig_ret->type != MONO_TYPE_VOID) {
1754                 switch (cinfo->ret.storage) {
1755                 case ArgInIReg:
1756                 case ArgInFloatSSEReg:
1757                 case ArgInDoubleSSEReg:
1758                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1759                                 /* The register is volatile */
1760                                 cfg->vret_addr->opcode = OP_REGOFFSET;
1761                                 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1762                                 if (cfg->arch.omit_fp) {
1763                                         cfg->vret_addr->inst_offset = offset;
1764                                         offset += 8;
1765                                 } else {
1766                                         offset += 8;
1767                                         cfg->vret_addr->inst_offset = -offset;
1768                                 }
1769                                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1770                                         printf ("vret_addr =");
1771                                         mono_print_ins (cfg->vret_addr);
1772                                 }
1773                         }
1774                         else {
1775                                 cfg->ret->opcode = OP_REGVAR;
1776                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1777                         }
1778                         break;
1779                 case ArgValuetypeInReg:
1780                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1781                         cfg->ret->opcode = OP_REGOFFSET;
1782                         cfg->ret->inst_basereg = cfg->frame_reg;
1783                         if (cfg->arch.omit_fp) {
1784                                 cfg->ret->inst_offset = offset;
1785                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1786                         } else {
1787                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1788                                 cfg->ret->inst_offset = - offset;
1789                         }
1790                         break;
1791                 default:
1792                         g_assert_not_reached ();
1793                 }
1794                 cfg->ret->dreg = cfg->ret->inst_c0;
1795         }
1796
1797         /* Allocate locals */
1798         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1799         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1800                 char *mname = mono_method_full_name (cfg->method, TRUE);
1801                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1802                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1803                 g_free (mname);
1804                 return;
1805         }
1806
1807         if (locals_stack_align) {
1808                 offset += (locals_stack_align - 1);
1809                 offset &= ~(locals_stack_align - 1);
1810         }
1811         if (cfg->arch.omit_fp) {
1812                 cfg->locals_min_stack_offset = offset;
1813                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1814         } else {
1815                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1816                 cfg->locals_max_stack_offset = - offset;
1817         }
1818
1819         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1820                 if (offsets [i] != -1) {
1821                         MonoInst *ins = cfg->varinfo [i];
1822                         ins->opcode = OP_REGOFFSET;
1823                         ins->inst_basereg = cfg->frame_reg;
1824                         if (cfg->arch.omit_fp)
1825                                 ins->inst_offset = (offset + offsets [i]);
1826                         else
1827                                 ins->inst_offset = - (offset + offsets [i]);
1828                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1829                 }
1830         }
1831         offset += locals_stack_size;
1832
1833         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1834                 g_assert (!cfg->arch.omit_fp);
1835                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1836                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1837         }
1838
1839         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1840                 ins = cfg->args [i];
1841                 if (ins->opcode != OP_REGVAR) {
1842                         ArgInfo *ainfo = &cinfo->args [i];
1843                         gboolean inreg = TRUE;
1844
1845                         /* FIXME: Allocate volatile arguments to registers */
1846                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1847                                 inreg = FALSE;
1848
1849                         /*
1850                          * Under AMD64, all registers used to pass arguments to functions
1851                          * are volatile across calls.
1852                          * FIXME: Optimize this.
1853                          */
1854                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1855                                 inreg = FALSE;
1856
1857                         ins->opcode = OP_REGOFFSET;
1858
1859                         switch (ainfo->storage) {
1860                         case ArgInIReg:
1861                         case ArgInFloatSSEReg:
1862                         case ArgInDoubleSSEReg:
1863                                 if (inreg) {
1864                                         ins->opcode = OP_REGVAR;
1865                                         ins->dreg = ainfo->reg;
1866                                 }
1867                                 break;
1868                         case ArgOnStack:
1869                                 g_assert (!cfg->arch.omit_fp);
1870                                 ins->opcode = OP_REGOFFSET;
1871                                 ins->inst_basereg = cfg->frame_reg;
1872                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1873                                 break;
1874                         case ArgValuetypeInReg:
1875                                 break;
1876                         case ArgValuetypeAddrInIReg: {
1877                                 MonoInst *indir;
1878                                 g_assert (!cfg->arch.omit_fp);
1879
1880                                 MONO_INST_NEW (cfg, indir, 0);
1881                                 indir->opcode = OP_REGOFFSET;
1882                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1883                                         indir->inst_basereg = cfg->frame_reg;
1884                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1885                                         offset += (sizeof (gpointer));
1886                                         indir->inst_offset = - offset;
1887                                 }
1888                                 else {
1889                                         indir->inst_basereg = cfg->frame_reg;
1890                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1891                                 }
1892
1893                                 ins->opcode = OP_VTARG_ADDR;
1894                                 ins->inst_left = indir;
1895
1896                                 break;
1897                         }
1898                         default:
1899                                 NOT_IMPLEMENTED;
1900                         }
1901
1902                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1903                                 ins->opcode = OP_REGOFFSET;
1904                                 ins->inst_basereg = cfg->frame_reg;
1905                                 /* These arguments are saved to the stack in the prolog */
1906                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1907                                 if (cfg->arch.omit_fp) {
1908                                         ins->inst_offset = offset;
1909                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1910                                         // Arguments are yet supported by the stack map creation code
1911                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1912                                 } else {
1913                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1914                                         ins->inst_offset = - offset;
1915                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1916                                 }
1917                         }
1918                 }
1919         }
1920
1921         cfg->stack_offset = offset;
1922 }
1923
1924 void
1925 mono_arch_create_vars (MonoCompile *cfg)
1926 {
1927         MonoMethodSignature *sig;
1928         CallInfo *cinfo;
1929         MonoType *sig_ret;
1930
1931         sig = mono_method_signature (cfg->method);
1932
1933         if (!cfg->arch.cinfo)
1934                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1935         cinfo = cfg->arch.cinfo;
1936
1937         if (cinfo->ret.storage == ArgValuetypeInReg)
1938                 cfg->ret_var_is_local = TRUE;
1939
1940         sig_ret = mini_get_underlying_type (sig->ret);
1941         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1942                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1943                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1944                         printf ("vret_addr = ");
1945                         mono_print_ins (cfg->vret_addr);
1946                 }
1947         }
1948
1949         if (cfg->gen_sdb_seq_points) {
1950                 MonoInst *ins;
1951
1952                 if (cfg->compile_aot) {
1953                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1954                         ins->flags |= MONO_INST_VOLATILE;
1955                         cfg->arch.seq_point_info_var = ins;
1956
1957                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1958                         ins->flags |= MONO_INST_VOLATILE;
1959                         cfg->arch.ss_tramp_var = ins;
1960                 }
1961
1962             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1963                 ins->flags |= MONO_INST_VOLATILE;
1964                 cfg->arch.ss_trigger_page_var = ins;
1965         }
1966
1967         if (cfg->method->save_lmf)
1968                 cfg->create_lmf_var = TRUE;
1969
1970         if (cfg->method->save_lmf) {
1971                 cfg->lmf_ir = TRUE;
1972 #if !defined(TARGET_WIN32)
1973                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1974                         cfg->lmf_ir_mono_lmf = TRUE;
1975 #endif
1976         }
1977 }
1978
1979 static void
1980 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1981 {
1982         MonoInst *ins;
1983
1984         switch (storage) {
1985         case ArgInIReg:
1986                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1987                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1988                 ins->sreg1 = tree->dreg;
1989                 MONO_ADD_INS (cfg->cbb, ins);
1990                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1991                 break;
1992         case ArgInFloatSSEReg:
1993                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1994                 ins->dreg = mono_alloc_freg (cfg);
1995                 ins->sreg1 = tree->dreg;
1996                 MONO_ADD_INS (cfg->cbb, ins);
1997
1998                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1999                 break;
2000         case ArgInDoubleSSEReg:
2001                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2002                 ins->dreg = mono_alloc_freg (cfg);
2003                 ins->sreg1 = tree->dreg;
2004                 MONO_ADD_INS (cfg->cbb, ins);
2005
2006                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2007
2008                 break;
2009         default:
2010                 g_assert_not_reached ();
2011         }
2012 }
2013
2014 static int
2015 arg_storage_to_load_membase (ArgStorage storage)
2016 {
2017         switch (storage) {
2018         case ArgInIReg:
2019 #if defined(__mono_ilp32__)
2020                 return OP_LOADI8_MEMBASE;
2021 #else
2022                 return OP_LOAD_MEMBASE;
2023 #endif
2024         case ArgInDoubleSSEReg:
2025                 return OP_LOADR8_MEMBASE;
2026         case ArgInFloatSSEReg:
2027                 return OP_LOADR4_MEMBASE;
2028         default:
2029                 g_assert_not_reached ();
2030         }
2031
2032         return -1;
2033 }
2034
2035 static void
2036 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2037 {
2038         MonoMethodSignature *tmp_sig;
2039         int sig_reg;
2040
2041         if (call->tail_call)
2042                 NOT_IMPLEMENTED;
2043
2044         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2045
2046         /*
2047          * mono_ArgIterator_Setup assumes the signature cookie is
2048          * passed first and all the arguments which were before it are
2049          * passed on the stack after the signature. So compensate by
2050          * passing a different signature.
2051          */
2052         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2053         tmp_sig->param_count -= call->signature->sentinelpos;
2054         tmp_sig->sentinelpos = 0;
2055         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2056
2057         sig_reg = mono_alloc_ireg (cfg);
2058         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2059
2060         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2061 }
2062
2063 #ifdef ENABLE_LLVM
2064 static inline LLVMArgStorage
2065 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2066 {
2067         switch (storage) {
2068         case ArgInIReg:
2069                 return LLVMArgInIReg;
2070         case ArgNone:
2071                 return LLVMArgNone;
2072         default:
2073                 g_assert_not_reached ();
2074                 return LLVMArgNone;
2075         }
2076 }
2077
2078 LLVMCallInfo*
2079 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2080 {
2081         int i, n;
2082         CallInfo *cinfo;
2083         ArgInfo *ainfo;
2084         int j;
2085         LLVMCallInfo *linfo;
2086         MonoType *t, *sig_ret;
2087
2088         n = sig->param_count + sig->hasthis;
2089         sig_ret = mini_get_underlying_type (sig->ret);
2090
2091         cinfo = get_call_info (cfg->mempool, sig);
2092
2093         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2094
2095         /*
2096          * LLVM always uses the native ABI while we use our own ABI, the
2097          * only difference is the handling of vtypes:
2098          * - we only pass/receive them in registers in some cases, and only
2099          *   in 1 or 2 integer registers.
2100          */
2101         if (cinfo->ret.storage == ArgValuetypeInReg) {
2102                 if (sig->pinvoke) {
2103                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2104                         cfg->disable_llvm = TRUE;
2105                         return linfo;
2106                 }
2107
2108                 linfo->ret.storage = LLVMArgVtypeInReg;
2109                 for (j = 0; j < 2; ++j)
2110                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2111         }
2112
2113         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2114                 /* Vtype returned using a hidden argument */
2115                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2116                 linfo->vret_arg_index = cinfo->vret_arg_index;
2117         }
2118
2119         for (i = 0; i < n; ++i) {
2120                 ainfo = cinfo->args + i;
2121
2122                 if (i >= sig->hasthis)
2123                         t = sig->params [i - sig->hasthis];
2124                 else
2125                         t = &mono_defaults.int_class->byval_arg;
2126
2127                 linfo->args [i].storage = LLVMArgNone;
2128
2129                 switch (ainfo->storage) {
2130                 case ArgInIReg:
2131                         linfo->args [i].storage = LLVMArgInIReg;
2132                         break;
2133                 case ArgInDoubleSSEReg:
2134                 case ArgInFloatSSEReg:
2135                         linfo->args [i].storage = LLVMArgInFPReg;
2136                         break;
2137                 case ArgOnStack:
2138                         if (MONO_TYPE_ISSTRUCT (t)) {
2139                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2140                         } else {
2141                                 linfo->args [i].storage = LLVMArgInIReg;
2142                                 if (!t->byref) {
2143                                         if (t->type == MONO_TYPE_R4)
2144                                                 linfo->args [i].storage = LLVMArgInFPReg;
2145                                         else if (t->type == MONO_TYPE_R8)
2146                                                 linfo->args [i].storage = LLVMArgInFPReg;
2147                                 }
2148                         }
2149                         break;
2150                 case ArgValuetypeInReg:
2151                         if (sig->pinvoke) {
2152                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2153                                 cfg->disable_llvm = TRUE;
2154                                 return linfo;
2155                         }
2156
2157                         linfo->args [i].storage = LLVMArgVtypeInReg;
2158                         for (j = 0; j < 2; ++j)
2159                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2160                         break;
2161                 default:
2162                         cfg->exception_message = g_strdup ("ainfo->storage");
2163                         cfg->disable_llvm = TRUE;
2164                         break;
2165                 }
2166         }
2167
2168         return linfo;
2169 }
2170 #endif
2171
2172 void
2173 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2174 {
2175         MonoInst *arg, *in;
2176         MonoMethodSignature *sig;
2177         MonoType *sig_ret;
2178         int i, n;
2179         CallInfo *cinfo;
2180         ArgInfo *ainfo;
2181
2182         sig = call->signature;
2183         n = sig->param_count + sig->hasthis;
2184
2185         cinfo = get_call_info (cfg->mempool, sig);
2186
2187         sig_ret = sig->ret;
2188
2189         if (COMPILE_LLVM (cfg)) {
2190                 /* We shouldn't be called in the llvm case */
2191                 cfg->disable_llvm = TRUE;
2192                 return;
2193         }
2194
2195         /*
2196          * Emit all arguments which are passed on the stack to prevent register
2197          * allocation problems.
2198          */
2199         for (i = 0; i < n; ++i) {
2200                 MonoType *t;
2201                 ainfo = cinfo->args + i;
2202
2203                 in = call->args [i];
2204
2205                 if (sig->hasthis && i == 0)
2206                         t = &mono_defaults.object_class->byval_arg;
2207                 else
2208                         t = sig->params [i - sig->hasthis];
2209
2210                 t = mini_get_underlying_type (t);
2211                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2212                         if (!t->byref) {
2213                                 if (t->type == MONO_TYPE_R4)
2214                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2215                                 else if (t->type == MONO_TYPE_R8)
2216                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2217                                 else
2218                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2219                         } else {
2220                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2221                         }
2222                         if (cfg->compute_gc_maps) {
2223                                 MonoInst *def;
2224
2225                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2226                         }
2227                 }
2228         }
2229
2230         /*
2231          * Emit all parameters passed in registers in non-reverse order for better readability
2232          * and to help the optimization in emit_prolog ().
2233          */
2234         for (i = 0; i < n; ++i) {
2235                 ainfo = cinfo->args + i;
2236
2237                 in = call->args [i];
2238
2239                 if (ainfo->storage == ArgInIReg)
2240                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2241         }
2242
2243         for (i = n - 1; i >= 0; --i) {
2244                 MonoType *t;
2245
2246                 ainfo = cinfo->args + i;
2247
2248                 in = call->args [i];
2249
2250                 if (sig->hasthis && i == 0)
2251                         t = &mono_defaults.object_class->byval_arg;
2252                 else
2253                         t = sig->params [i - sig->hasthis];
2254                 t = mini_get_underlying_type (t);
2255
2256                 switch (ainfo->storage) {
2257                 case ArgInIReg:
2258                         /* Already done */
2259                         break;
2260                 case ArgInFloatSSEReg:
2261                 case ArgInDoubleSSEReg:
2262                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2263                         break;
2264                 case ArgOnStack:
2265                 case ArgValuetypeInReg:
2266                 case ArgValuetypeAddrInIReg:
2267                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2268                                 MonoInst *call_inst = (MonoInst*)call;
2269                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2270                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2271                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
2272                                 guint32 align;
2273                                 guint32 size;
2274
2275                                 if (t->type == MONO_TYPE_TYPEDBYREF) {
2276                                         size = sizeof (MonoTypedRef);
2277                                         align = sizeof (gpointer);
2278                                 }
2279                                 else {
2280                                         if (sig->pinvoke)
2281                                                 size = mono_type_native_stack_size (t, &align);
2282                                         else {
2283                                                 /*
2284                                                  * Other backends use mono_type_stack_size (), but that
2285                                                  * aligns the size to 8, which is larger than the size of
2286                                                  * the source, leading to reads of invalid memory if the
2287                                                  * source is at the end of address space.
2288                                                  */
2289                                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2290                                         }
2291                                 }
2292                                 g_assert (in->klass);
2293
2294                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2295                                         /* Avoid asserts in emit_memcpy () */
2296                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2297                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2298                                         /* Continue normally */
2299                                 }
2300
2301                                 if (size > 0) {
2302                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2303                                         arg->sreg1 = in->dreg;
2304                                         arg->klass = mono_class_from_mono_type (t);
2305                                         arg->backend.size = size;
2306                                         arg->inst_p0 = call;
2307                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2308                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2309
2310                                         MONO_ADD_INS (cfg->cbb, arg);
2311                                 }
2312                         }
2313                         break;
2314                 default:
2315                         g_assert_not_reached ();
2316                 }
2317
2318                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2319                         /* Emit the signature cookie just before the implicit arguments */
2320                         emit_sig_cookie (cfg, call, cinfo);
2321         }
2322
2323         /* Handle the case where there are no implicit arguments */
2324         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2325                 emit_sig_cookie (cfg, call, cinfo);
2326
2327         sig_ret = mini_get_underlying_type (sig->ret);
2328         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2329                 MonoInst *vtarg;
2330
2331                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2332                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2333                                 /*
2334                                  * Tell the JIT to use a more efficient calling convention: call using
2335                                  * OP_CALL, compute the result location after the call, and save the
2336                                  * result there.
2337                                  */
2338                                 call->vret_in_reg = TRUE;
2339                                 /*
2340                                  * Nullify the instruction computing the vret addr to enable
2341                                  * future optimizations.
2342                                  */
2343                                 if (call->vret_var)
2344                                         NULLIFY_INS (call->vret_var);
2345                         } else {
2346                                 if (call->tail_call)
2347                                         NOT_IMPLEMENTED;
2348                                 /*
2349                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2350                                  * the stack. Push the address here, so the call instruction can
2351                                  * access it.
2352                                  */
2353                                 if (!cfg->arch.vret_addr_loc) {
2354                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2355                                         /* Prevent it from being register allocated or optimized away */
2356                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2357                                 }
2358
2359                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2360                         }
2361                 }
2362                 else {
2363                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2364                         vtarg->sreg1 = call->vret_var->dreg;
2365                         vtarg->dreg = mono_alloc_preg (cfg);
2366                         MONO_ADD_INS (cfg->cbb, vtarg);
2367
2368                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2369                 }
2370         }
2371
2372         if (cfg->method->save_lmf) {
2373                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2374                 MONO_ADD_INS (cfg->cbb, arg);
2375         }
2376
2377         call->stack_usage = cinfo->stack_usage;
2378 }
2379
2380 void
2381 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2382 {
2383         MonoInst *arg;
2384         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2385         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2386         int size = ins->backend.size;
2387
2388         if (ainfo->storage == ArgValuetypeInReg) {
2389                 MonoInst *load;
2390                 int part;
2391
2392                 for (part = 0; part < 2; ++part) {
2393                         if (ainfo->pair_storage [part] == ArgNone)
2394                                 continue;
2395
2396                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2397                         load->inst_basereg = src->dreg;
2398                         load->inst_offset = part * sizeof(mgreg_t);
2399
2400                         switch (ainfo->pair_storage [part]) {
2401                         case ArgInIReg:
2402                                 load->dreg = mono_alloc_ireg (cfg);
2403                                 break;
2404                         case ArgInDoubleSSEReg:
2405                         case ArgInFloatSSEReg:
2406                                 load->dreg = mono_alloc_freg (cfg);
2407                                 break;
2408                         default:
2409                                 g_assert_not_reached ();
2410                         }
2411                         MONO_ADD_INS (cfg->cbb, load);
2412
2413                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2414                 }
2415         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2416                 MonoInst *vtaddr, *load;
2417                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2418
2419                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2420                 cfg->has_indirection = TRUE;
2421                 load->inst_p0 = vtaddr;
2422                 vtaddr->flags |= MONO_INST_INDIRECT;
2423                 load->type = STACK_MP;
2424                 load->klass = vtaddr->klass;
2425                 load->dreg = mono_alloc_ireg (cfg);
2426                 MONO_ADD_INS (cfg->cbb, load);
2427                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2428
2429                 if (ainfo->pair_storage [0] == ArgInIReg) {
2430                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2431                         arg->dreg = mono_alloc_ireg (cfg);
2432                         arg->sreg1 = load->dreg;
2433                         arg->inst_imm = 0;
2434                         MONO_ADD_INS (cfg->cbb, arg);
2435                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2436                 } else {
2437                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2438                 }
2439         } else {
2440                 if (size == 8) {
2441                         int dreg = mono_alloc_ireg (cfg);
2442
2443                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2444                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2445                 } else if (size <= 40) {
2446                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2447                 } else {
2448                         // FIXME: Code growth
2449                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2450                 }
2451
2452                 if (cfg->compute_gc_maps) {
2453                         MonoInst *def;
2454                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2455                 }
2456         }
2457 }
2458
2459 void
2460 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2461 {
2462         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2463
2464         if (ret->type == MONO_TYPE_R4) {
2465                 if (COMPILE_LLVM (cfg))
2466                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2467                 else
2468                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2469                 return;
2470         } else if (ret->type == MONO_TYPE_R8) {
2471                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2472                 return;
2473         }
2474
2475         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2476 }
2477
2478 #endif /* DISABLE_JIT */
2479
2480 #define EMIT_COND_BRANCH(ins,cond,sign) \
2481         if (ins->inst_true_bb->native_offset) { \
2482                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2483         } else { \
2484                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2485                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2486             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2487                         x86_branch8 (code, cond, 0, sign); \
2488                 else \
2489                         x86_branch32 (code, cond, 0, sign); \
2490 }
2491
2492 typedef struct {
2493         MonoMethodSignature *sig;
2494         CallInfo *cinfo;
2495 } ArchDynCallInfo;
2496
2497 static gboolean
2498 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2499 {
2500         int i;
2501
2502 #ifdef HOST_WIN32
2503         return FALSE;
2504 #endif
2505
2506         switch (cinfo->ret.storage) {
2507         case ArgNone:
2508         case ArgInIReg:
2509                 break;
2510         case ArgValuetypeInReg: {
2511                 ArgInfo *ainfo = &cinfo->ret;
2512
2513                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2514                         return FALSE;
2515                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2516                         return FALSE;
2517                 break;
2518         }
2519         default:
2520                 return FALSE;
2521         }
2522
2523         for (i = 0; i < cinfo->nargs; ++i) {
2524                 ArgInfo *ainfo = &cinfo->args [i];
2525                 switch (ainfo->storage) {
2526                 case ArgInIReg:
2527                         break;
2528                 case ArgValuetypeInReg:
2529                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2530                                 return FALSE;
2531                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2532                                 return FALSE;
2533                         break;
2534                 default:
2535                         return FALSE;
2536                 }
2537         }
2538
2539         return TRUE;
2540 }
2541
2542 /*
2543  * mono_arch_dyn_call_prepare:
2544  *
2545  *   Return a pointer to an arch-specific structure which contains information
2546  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2547  * supported for SIG.
2548  * This function is equivalent to ffi_prep_cif in libffi.
2549  */
2550 MonoDynCallInfo*
2551 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2552 {
2553         ArchDynCallInfo *info;
2554         CallInfo *cinfo;
2555
2556         cinfo = get_call_info (NULL, sig);
2557
2558         if (!dyn_call_supported (sig, cinfo)) {
2559                 g_free (cinfo);
2560                 return NULL;
2561         }
2562
2563         info = g_new0 (ArchDynCallInfo, 1);
2564         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2565         info->sig = sig;
2566         info->cinfo = cinfo;
2567
2568         return (MonoDynCallInfo*)info;
2569 }
2570
2571 /*
2572  * mono_arch_dyn_call_free:
2573  *
2574  *   Free a MonoDynCallInfo structure.
2575  */
2576 void
2577 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2578 {
2579         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2580
2581         g_free (ainfo->cinfo);
2582         g_free (ainfo);
2583 }
2584
2585 #if !defined(__native_client__)
2586 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2587 #define GREG_TO_PTR(greg) (gpointer)(greg)
2588 #else
2589 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2590 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2591 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2592 #endif
2593
2594 /*
2595  * mono_arch_get_start_dyn_call:
2596  *
2597  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2598  * store the result into BUF.
2599  * ARGS should be an array of pointers pointing to the arguments.
2600  * RET should point to a memory buffer large enought to hold the result of the
2601  * call.
2602  * This function should be as fast as possible, any work which does not depend
2603  * on the actual values of the arguments should be done in
2604  * mono_arch_dyn_call_prepare ().
2605  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2606  * libffi.
2607  */
2608 void
2609 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2610 {
2611         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2612         DynCallArgs *p = (DynCallArgs*)buf;
2613         int arg_index, greg, i, pindex;
2614         MonoMethodSignature *sig = dinfo->sig;
2615
2616         g_assert (buf_len >= sizeof (DynCallArgs));
2617
2618         p->res = 0;
2619         p->ret = ret;
2620
2621         arg_index = 0;
2622         greg = 0;
2623         pindex = 0;
2624
2625         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2626                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2627                 if (!sig->hasthis)
2628                         pindex = 1;
2629         }
2630
2631         if (dinfo->cinfo->vtype_retaddr)
2632                 p->regs [greg ++] = PTR_TO_GREG(ret);
2633
2634         for (i = pindex; i < sig->param_count; i++) {
2635                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2636                 gpointer *arg = args [arg_index ++];
2637
2638                 if (t->byref) {
2639                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2640                         continue;
2641                 }
2642
2643                 switch (t->type) {
2644                 case MONO_TYPE_STRING:
2645                 case MONO_TYPE_CLASS:
2646                 case MONO_TYPE_ARRAY:
2647                 case MONO_TYPE_SZARRAY:
2648                 case MONO_TYPE_OBJECT:
2649                 case MONO_TYPE_PTR:
2650                 case MONO_TYPE_I:
2651                 case MONO_TYPE_U:
2652 #if !defined(__mono_ilp32__)
2653                 case MONO_TYPE_I8:
2654                 case MONO_TYPE_U8:
2655 #endif
2656                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2657                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2658                         break;
2659 #if defined(__mono_ilp32__)
2660                 case MONO_TYPE_I8:
2661                 case MONO_TYPE_U8:
2662                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2663                         p->regs [greg ++] = *(guint64*)(arg);
2664                         break;
2665 #endif
2666                 case MONO_TYPE_U1:
2667                         p->regs [greg ++] = *(guint8*)(arg);
2668                         break;
2669                 case MONO_TYPE_I1:
2670                         p->regs [greg ++] = *(gint8*)(arg);
2671                         break;
2672                 case MONO_TYPE_I2:
2673                         p->regs [greg ++] = *(gint16*)(arg);
2674                         break;
2675                 case MONO_TYPE_U2:
2676                         p->regs [greg ++] = *(guint16*)(arg);
2677                         break;
2678                 case MONO_TYPE_I4:
2679                         p->regs [greg ++] = *(gint32*)(arg);
2680                         break;
2681                 case MONO_TYPE_U4:
2682                         p->regs [greg ++] = *(guint32*)(arg);
2683                         break;
2684                 case MONO_TYPE_GENERICINST:
2685                     if (MONO_TYPE_IS_REFERENCE (t)) {
2686                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2687                                 break;
2688                         } else {
2689                                 /* Fall through */
2690                         }
2691                 case MONO_TYPE_VALUETYPE: {
2692                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2693
2694                         g_assert (ainfo->storage == ArgValuetypeInReg);
2695                         if (ainfo->pair_storage [0] != ArgNone) {
2696                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2697                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2698                         }
2699                         if (ainfo->pair_storage [1] != ArgNone) {
2700                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2701                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2702                         }
2703                         break;
2704                 }
2705                 default:
2706                         g_assert_not_reached ();
2707                 }
2708         }
2709
2710         g_assert (greg <= PARAM_REGS);
2711 }
2712
2713 /*
2714  * mono_arch_finish_dyn_call:
2715  *
2716  *   Store the result of a dyn call into the return value buffer passed to
2717  * start_dyn_call ().
2718  * This function should be as fast as possible, any work which does not depend
2719  * on the actual values of the arguments should be done in
2720  * mono_arch_dyn_call_prepare ().
2721  */
2722 void
2723 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2724 {
2725         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2726         MonoMethodSignature *sig = dinfo->sig;
2727         guint8 *ret = ((DynCallArgs*)buf)->ret;
2728         mgreg_t res = ((DynCallArgs*)buf)->res;
2729         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2730
2731         switch (sig_ret->type) {
2732         case MONO_TYPE_VOID:
2733                 *(gpointer*)ret = NULL;
2734                 break;
2735         case MONO_TYPE_STRING:
2736         case MONO_TYPE_CLASS:
2737         case MONO_TYPE_ARRAY:
2738         case MONO_TYPE_SZARRAY:
2739         case MONO_TYPE_OBJECT:
2740         case MONO_TYPE_I:
2741         case MONO_TYPE_U:
2742         case MONO_TYPE_PTR:
2743                 *(gpointer*)ret = GREG_TO_PTR(res);
2744                 break;
2745         case MONO_TYPE_I1:
2746                 *(gint8*)ret = res;
2747                 break;
2748         case MONO_TYPE_U1:
2749                 *(guint8*)ret = res;
2750                 break;
2751         case MONO_TYPE_I2:
2752                 *(gint16*)ret = res;
2753                 break;
2754         case MONO_TYPE_U2:
2755                 *(guint16*)ret = res;
2756                 break;
2757         case MONO_TYPE_I4:
2758                 *(gint32*)ret = res;
2759                 break;
2760         case MONO_TYPE_U4:
2761                 *(guint32*)ret = res;
2762                 break;
2763         case MONO_TYPE_I8:
2764                 *(gint64*)ret = res;
2765                 break;
2766         case MONO_TYPE_U8:
2767                 *(guint64*)ret = res;
2768                 break;
2769         case MONO_TYPE_GENERICINST:
2770                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2771                         *(gpointer*)ret = GREG_TO_PTR(res);
2772                         break;
2773                 } else {
2774                         /* Fall through */
2775                 }
2776         case MONO_TYPE_VALUETYPE:
2777                 if (dinfo->cinfo->vtype_retaddr) {
2778                         /* Nothing to do */
2779                 } else {
2780                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2781
2782                         g_assert (ainfo->storage == ArgValuetypeInReg);
2783
2784                         if (ainfo->pair_storage [0] != ArgNone) {
2785                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2786                                 ((mgreg_t*)ret)[0] = res;
2787                         }
2788
2789                         g_assert (ainfo->pair_storage [1] == ArgNone);
2790                 }
2791                 break;
2792         default:
2793                 g_assert_not_reached ();
2794         }
2795 }
2796
2797 /* emit an exception if condition is fail */
2798 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2799         do {                                                        \
2800                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2801                 if (tins == NULL) {                                                                             \
2802                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2803                                         MONO_PATCH_INFO_EXC, exc_name);  \
2804                         x86_branch32 (code, cond, 0, signed);               \
2805                 } else {        \
2806                         EMIT_COND_BRANCH (tins, cond, signed);  \
2807                 }                       \
2808         } while (0);
2809
2810 #define EMIT_FPCOMPARE(code) do { \
2811         amd64_fcompp (code); \
2812         amd64_fnstsw (code); \
2813 } while (0);
2814
2815 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2816     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2817         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2818         amd64_ ##op (code); \
2819         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2820         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2821 } while (0);
2822
2823 static guint8*
2824 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2825 {
2826         gboolean no_patch = FALSE;
2827
2828         /*
2829          * FIXME: Add support for thunks
2830          */
2831         {
2832                 gboolean near_call = FALSE;
2833
2834                 /*
2835                  * Indirect calls are expensive so try to make a near call if possible.
2836                  * The caller memory is allocated by the code manager so it is
2837                  * guaranteed to be at a 32 bit offset.
2838                  */
2839
2840                 if (patch_type != MONO_PATCH_INFO_ABS) {
2841                         /* The target is in memory allocated using the code manager */
2842                         near_call = TRUE;
2843
2844                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2845                                 if (((MonoMethod*)data)->klass->image->aot_module)
2846                                         /* The callee might be an AOT method */
2847                                         near_call = FALSE;
2848                                 if (((MonoMethod*)data)->dynamic)
2849                                         /* The target is in malloc-ed memory */
2850                                         near_call = FALSE;
2851                         }
2852
2853                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2854                                 /*
2855                                  * The call might go directly to a native function without
2856                                  * the wrapper.
2857                                  */
2858                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2859                                 if (mi) {
2860                                         gconstpointer target = mono_icall_get_wrapper (mi);
2861                                         if ((((guint64)target) >> 32) != 0)
2862                                                 near_call = FALSE;
2863                                 }
2864                         }
2865                 }
2866                 else {
2867                         MonoJumpInfo *jinfo = NULL;
2868
2869                         if (cfg->abs_patches)
2870                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2871                         if (jinfo) {
2872                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2873                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2874                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2875                                                 near_call = TRUE;
2876                                         no_patch = TRUE;
2877                                 } else {
2878                                         /*
2879                                          * This is not really an optimization, but required because the
2880                                          * generic class init trampolines use R11 to pass the vtable.
2881                                          */
2882                                         near_call = TRUE;
2883                                 }
2884                         } else {
2885                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2886                                 if (info) {
2887                                         if (info->func == info->wrapper) {
2888                                                 /* No wrapper */
2889                                                 if ((((guint64)info->func) >> 32) == 0)
2890                                                         near_call = TRUE;
2891                                         }
2892                                         else {
2893                                                 /* See the comment in mono_codegen () */
2894                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2895                                                         near_call = TRUE;
2896                                         }
2897                                 }
2898                                 else if ((((guint64)data) >> 32) == 0) {
2899                                         near_call = TRUE;
2900                                         no_patch = TRUE;
2901                                 }
2902                         }
2903                 }
2904
2905                 if (cfg->method->dynamic)
2906                         /* These methods are allocated using malloc */
2907                         near_call = FALSE;
2908
2909 #ifdef MONO_ARCH_NOMAP32BIT
2910                 near_call = FALSE;
2911 #endif
2912 #if defined(__native_client__)
2913                 /* Always use near_call == TRUE for Native Client */
2914                 near_call = TRUE;
2915 #endif
2916                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2917                 if (optimize_for_xen)
2918                         near_call = FALSE;
2919
2920                 if (cfg->compile_aot) {
2921                         near_call = TRUE;
2922                         no_patch = TRUE;
2923                 }
2924
2925                 if (near_call) {
2926                         /*
2927                          * Align the call displacement to an address divisible by 4 so it does
2928                          * not span cache lines. This is required for code patching to work on SMP
2929                          * systems.
2930                          */
2931                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2932                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2933                                 amd64_padding (code, pad_size);
2934                         }
2935                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2936                         amd64_call_code (code, 0);
2937                 }
2938                 else {
2939                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2940                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2941                         amd64_call_reg (code, GP_SCRATCH_REG);
2942                 }
2943         }
2944
2945         return code;
2946 }
2947
2948 static inline guint8*
2949 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2950 {
2951 #ifdef TARGET_WIN32
2952         if (win64_adjust_stack)
2953                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2954 #endif
2955         code = emit_call_body (cfg, code, patch_type, data);
2956 #ifdef TARGET_WIN32
2957         if (win64_adjust_stack)
2958                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2959 #endif
2960
2961         return code;
2962 }
2963
2964 static inline int
2965 store_membase_imm_to_store_membase_reg (int opcode)
2966 {
2967         switch (opcode) {
2968         case OP_STORE_MEMBASE_IMM:
2969                 return OP_STORE_MEMBASE_REG;
2970         case OP_STOREI4_MEMBASE_IMM:
2971                 return OP_STOREI4_MEMBASE_REG;
2972         case OP_STOREI8_MEMBASE_IMM:
2973                 return OP_STOREI8_MEMBASE_REG;
2974         }
2975
2976         return -1;
2977 }
2978
2979 #ifndef DISABLE_JIT
2980
2981 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2982
2983 /*
2984  * mono_arch_peephole_pass_1:
2985  *
2986  *   Perform peephole opts which should/can be performed before local regalloc
2987  */
2988 void
2989 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2990 {
2991         MonoInst *ins, *n;
2992
2993         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2994                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2995
2996                 switch (ins->opcode) {
2997                 case OP_ADD_IMM:
2998                 case OP_IADD_IMM:
2999                 case OP_LADD_IMM:
3000                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3001                                 /*
3002                                  * X86_LEA is like ADD, but doesn't have the
3003                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3004                                  * its operand to 64 bit.
3005                                  */
3006                                 ins->opcode = OP_X86_LEA_MEMBASE;
3007                                 ins->inst_basereg = ins->sreg1;
3008                         }
3009                         break;
3010                 case OP_LXOR:
3011                 case OP_IXOR:
3012                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3013                                 MonoInst *ins2;
3014
3015                                 /*
3016                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3017                                  * the latter has length 2-3 instead of 6 (reverse constant
3018                                  * propagation). These instruction sequences are very common
3019                                  * in the initlocals bblock.
3020                                  */
3021                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3022                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3023                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3024                                                 ins2->sreg1 = ins->dreg;
3025                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3026                                                 /* Continue */
3027                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3028                                                 NULLIFY_INS (ins2);
3029                                                 /* Continue */
3030                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3031                                                 /* Continue */
3032                                         } else {
3033                                                 break;
3034                                         }
3035                                 }
3036                         }
3037                         break;
3038                 case OP_COMPARE_IMM:
3039                 case OP_LCOMPARE_IMM:
3040                         /* OP_COMPARE_IMM (reg, 0)
3041                          * -->
3042                          * OP_AMD64_TEST_NULL (reg)
3043                          */
3044                         if (!ins->inst_imm)
3045                                 ins->opcode = OP_AMD64_TEST_NULL;
3046                         break;
3047                 case OP_ICOMPARE_IMM:
3048                         if (!ins->inst_imm)
3049                                 ins->opcode = OP_X86_TEST_NULL;
3050                         break;
3051                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3052                         /*
3053                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3054                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3055                          * -->
3056                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3057                          * OP_COMPARE_IMM reg, imm
3058                          *
3059                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3060                          */
3061                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3062                             ins->inst_basereg == last_ins->inst_destbasereg &&
3063                             ins->inst_offset == last_ins->inst_offset) {
3064                                         ins->opcode = OP_ICOMPARE_IMM;
3065                                         ins->sreg1 = last_ins->sreg1;
3066
3067                                         /* check if we can remove cmp reg,0 with test null */
3068                                         if (!ins->inst_imm)
3069                                                 ins->opcode = OP_X86_TEST_NULL;
3070                                 }
3071
3072                         break;
3073                 }
3074
3075                 mono_peephole_ins (bb, ins);
3076         }
3077 }
3078
3079 void
3080 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3081 {
3082         MonoInst *ins, *n;
3083
3084         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3085                 switch (ins->opcode) {
3086                 case OP_ICONST:
3087                 case OP_I8CONST: {
3088                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3089                         /* reg = 0 -> XOR (reg, reg) */
3090                         /* XOR sets cflags on x86, so we cant do it always */
3091                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3092                                 ins->opcode = OP_LXOR;
3093                                 ins->sreg1 = ins->dreg;
3094                                 ins->sreg2 = ins->dreg;
3095                                 /* Fall through */
3096                         } else {
3097                                 break;
3098                         }
3099                 }
3100                 case OP_LXOR:
3101                         /*
3102                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3103                          * 0 result into 64 bits.
3104                          */
3105                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3106                                 ins->opcode = OP_IXOR;
3107                         }
3108                         /* Fall through */
3109                 case OP_IXOR:
3110                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3111                                 MonoInst *ins2;
3112
3113                                 /*
3114                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3115                                  * the latter has length 2-3 instead of 6 (reverse constant
3116                                  * propagation). These instruction sequences are very common
3117                                  * in the initlocals bblock.
3118                                  */
3119                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3120                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3121                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3122                                                 ins2->sreg1 = ins->dreg;
3123                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3124                                                 /* Continue */
3125                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3126                                                 NULLIFY_INS (ins2);
3127                                                 /* Continue */
3128                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3129                                                 /* Continue */
3130                                         } else {
3131                                                 break;
3132                                         }
3133                                 }
3134                         }
3135                         break;
3136                 case OP_IADD_IMM:
3137                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3138                                 ins->opcode = OP_X86_INC_REG;
3139                         break;
3140                 case OP_ISUB_IMM:
3141                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3142                                 ins->opcode = OP_X86_DEC_REG;
3143                         break;
3144                 }
3145
3146                 mono_peephole_ins (bb, ins);
3147         }
3148 }
3149
3150 #define NEW_INS(cfg,ins,dest,op) do {   \
3151                 MONO_INST_NEW ((cfg), (dest), (op)); \
3152         (dest)->cil_code = (ins)->cil_code; \
3153         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3154         } while (0)
3155
3156 /*
3157  * mono_arch_lowering_pass:
3158  *
3159  *  Converts complex opcodes into simpler ones so that each IR instruction
3160  * corresponds to one machine instruction.
3161  */
3162 void
3163 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3164 {
3165         MonoInst *ins, *n, *temp;
3166
3167         /*
3168          * FIXME: Need to add more instructions, but the current machine
3169          * description can't model some parts of the composite instructions like
3170          * cdq.
3171          */
3172         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3173                 switch (ins->opcode) {
3174                 case OP_DIV_IMM:
3175                 case OP_REM_IMM:
3176                 case OP_IDIV_IMM:
3177                 case OP_IDIV_UN_IMM:
3178                 case OP_IREM_UN_IMM:
3179                 case OP_LREM_IMM:
3180                 case OP_IREM_IMM:
3181                         mono_decompose_op_imm (cfg, bb, ins);
3182                         break;
3183                 case OP_COMPARE_IMM:
3184                 case OP_LCOMPARE_IMM:
3185                         if (!amd64_is_imm32 (ins->inst_imm)) {
3186                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3187                                 temp->inst_c0 = ins->inst_imm;
3188                                 temp->dreg = mono_alloc_ireg (cfg);
3189                                 ins->opcode = OP_COMPARE;
3190                                 ins->sreg2 = temp->dreg;
3191                         }
3192                         break;
3193 #ifndef __mono_ilp32__
3194                 case OP_LOAD_MEMBASE:
3195 #endif
3196                 case OP_LOADI8_MEMBASE:
3197 #ifndef __native_client_codegen__
3198                 /*  Don't generate memindex opcodes (to simplify */
3199                 /*  read sandboxing) */
3200                         if (!amd64_is_imm32 (ins->inst_offset)) {
3201                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3202                                 temp->inst_c0 = ins->inst_offset;
3203                                 temp->dreg = mono_alloc_ireg (cfg);
3204                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3205                                 ins->inst_indexreg = temp->dreg;
3206                         }
3207 #endif
3208                         break;
3209 #ifndef __mono_ilp32__
3210                 case OP_STORE_MEMBASE_IMM:
3211 #endif
3212                 case OP_STOREI8_MEMBASE_IMM:
3213                         if (!amd64_is_imm32 (ins->inst_imm)) {
3214                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3215                                 temp->inst_c0 = ins->inst_imm;
3216                                 temp->dreg = mono_alloc_ireg (cfg);
3217                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3218                                 ins->sreg1 = temp->dreg;
3219                         }
3220                         break;
3221 #ifdef MONO_ARCH_SIMD_INTRINSICS
3222                 case OP_EXPAND_I1: {
3223                                 int temp_reg1 = mono_alloc_ireg (cfg);
3224                                 int temp_reg2 = mono_alloc_ireg (cfg);
3225                                 int original_reg = ins->sreg1;
3226
3227                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3228                                 temp->sreg1 = original_reg;
3229                                 temp->dreg = temp_reg1;
3230
3231                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3232                                 temp->sreg1 = temp_reg1;
3233                                 temp->dreg = temp_reg2;
3234                                 temp->inst_imm = 8;
3235
3236                                 NEW_INS (cfg, ins, temp, OP_LOR);
3237                                 temp->sreg1 = temp->dreg = temp_reg2;
3238                                 temp->sreg2 = temp_reg1;
3239
3240                                 ins->opcode = OP_EXPAND_I2;
3241                                 ins->sreg1 = temp_reg2;
3242                         }
3243                         break;
3244 #endif
3245                 default:
3246                         break;
3247                 }
3248         }
3249
3250         bb->max_vreg = cfg->next_vreg;
3251 }
3252
3253 static const int
3254 branch_cc_table [] = {
3255         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3256         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3257         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3258 };
3259
3260 /* Maps CMP_... constants to X86_CC_... constants */
3261 static const int
3262 cc_table [] = {
3263         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3264         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3265 };
3266
3267 static const int
3268 cc_signed_table [] = {
3269         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3270         FALSE, FALSE, FALSE, FALSE
3271 };
3272
3273 /*#include "cprop.c"*/
3274
3275 static unsigned char*
3276 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3277 {
3278         if (size == 8)
3279                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3280         else
3281                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3282
3283         if (size == 1)
3284                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3285         else if (size == 2)
3286                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3287         return code;
3288 }
3289
3290 static unsigned char*
3291 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3292 {
3293         int sreg = tree->sreg1;
3294         int need_touch = FALSE;
3295
3296 #if defined(TARGET_WIN32)
3297         need_touch = TRUE;
3298 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3299         if (!tree->flags & MONO_INST_INIT)
3300                 need_touch = TRUE;
3301 #endif
3302
3303         if (need_touch) {
3304                 guint8* br[5];
3305
3306                 /*
3307                  * Under Windows:
3308                  * If requested stack size is larger than one page,
3309                  * perform stack-touch operation
3310                  */
3311                 /*
3312                  * Generate stack probe code.
3313                  * Under Windows, it is necessary to allocate one page at a time,
3314                  * "touching" stack after each successful sub-allocation. This is
3315                  * because of the way stack growth is implemented - there is a
3316                  * guard page before the lowest stack page that is currently commited.
3317                  * Stack normally grows sequentially so OS traps access to the
3318                  * guard page and commits more pages when needed.
3319                  */
3320                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3321                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3322
3323                 br[2] = code; /* loop */
3324                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3325                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3326                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3327                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3328                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3329                 amd64_patch (br[3], br[2]);
3330                 amd64_test_reg_reg (code, sreg, sreg);
3331                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3332                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3333
3334                 br[1] = code; x86_jump8 (code, 0);
3335
3336                 amd64_patch (br[0], code);
3337                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3338                 amd64_patch (br[1], code);
3339                 amd64_patch (br[4], code);
3340         }
3341         else
3342                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3343
3344         if (tree->flags & MONO_INST_INIT) {
3345                 int offset = 0;
3346                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3347                         amd64_push_reg (code, AMD64_RAX);
3348                         offset += 8;
3349                 }
3350                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3351                         amd64_push_reg (code, AMD64_RCX);
3352                         offset += 8;
3353                 }
3354                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3355                         amd64_push_reg (code, AMD64_RDI);
3356                         offset += 8;
3357                 }
3358
3359                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3360                 if (sreg != AMD64_RCX)
3361                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3362                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3363
3364                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3365                 if (cfg->param_area)
3366                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3367                 amd64_cld (code);
3368 #if defined(__default_codegen__)
3369                 amd64_prefix (code, X86_REP_PREFIX);
3370                 amd64_stosl (code);
3371 #elif defined(__native_client_codegen__)
3372                 /* NaCl stos pseudo-instruction */
3373                 amd64_codegen_pre(code);
3374                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3375                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3376                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3377                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3378                 amd64_prefix (code, X86_REP_PREFIX);
3379                 amd64_stosl (code);
3380                 amd64_codegen_post(code);
3381 #endif /* __native_client_codegen__ */
3382
3383                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3384                         amd64_pop_reg (code, AMD64_RDI);
3385                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3386                         amd64_pop_reg (code, AMD64_RCX);
3387                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3388                         amd64_pop_reg (code, AMD64_RAX);
3389         }
3390         return code;
3391 }
3392
3393 static guint8*
3394 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3395 {
3396         CallInfo *cinfo;
3397         guint32 quad;
3398
3399         /* Move return value to the target register */
3400         /* FIXME: do this in the local reg allocator */
3401         switch (ins->opcode) {
3402         case OP_CALL:
3403         case OP_CALL_REG:
3404         case OP_CALL_MEMBASE:
3405         case OP_LCALL:
3406         case OP_LCALL_REG:
3407         case OP_LCALL_MEMBASE:
3408                 g_assert (ins->dreg == AMD64_RAX);
3409                 break;
3410         case OP_FCALL:
3411         case OP_FCALL_REG:
3412         case OP_FCALL_MEMBASE: {
3413                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3414                 if (rtype->type == MONO_TYPE_R4) {
3415                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3416                 }
3417                 else {
3418                         if (ins->dreg != AMD64_XMM0)
3419                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3420                 }
3421                 break;
3422         }
3423         case OP_RCALL:
3424         case OP_RCALL_REG:
3425         case OP_RCALL_MEMBASE:
3426                 if (ins->dreg != AMD64_XMM0)
3427                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3428                 break;
3429         case OP_VCALL:
3430         case OP_VCALL_REG:
3431         case OP_VCALL_MEMBASE:
3432         case OP_VCALL2:
3433         case OP_VCALL2_REG:
3434         case OP_VCALL2_MEMBASE:
3435                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3436                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3437                         MonoInst *loc = cfg->arch.vret_addr_loc;
3438
3439                         /* Load the destination address */
3440                         g_assert (loc->opcode == OP_REGOFFSET);
3441                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3442
3443                         for (quad = 0; quad < 2; quad ++) {
3444                                 switch (cinfo->ret.pair_storage [quad]) {
3445                                 case ArgInIReg:
3446                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3447                                         break;
3448                                 case ArgInFloatSSEReg:
3449                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3450                                         break;
3451                                 case ArgInDoubleSSEReg:
3452                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3453                                         break;
3454                                 case ArgNone:
3455                                         break;
3456                                 default:
3457                                         NOT_IMPLEMENTED;
3458                                 }
3459                         }
3460                 }
3461                 break;
3462         }
3463
3464         return code;
3465 }
3466
3467 #endif /* DISABLE_JIT */
3468
3469 #ifdef __APPLE__
3470 static int tls_gs_offset;
3471 #endif
3472
3473 gboolean
3474 mono_amd64_have_tls_get (void)
3475 {
3476 #ifdef TARGET_MACH
3477         static gboolean have_tls_get = FALSE;
3478         static gboolean inited = FALSE;
3479
3480         if (inited)
3481                 return have_tls_get;
3482
3483 #if MONO_HAVE_FAST_TLS
3484         guint8 *ins = (guint8*)pthread_getspecific;
3485
3486         /*
3487          * We're looking for these two instructions:
3488          *
3489          * mov    %gs:[offset](,%rdi,8),%rax
3490          * retq
3491          */
3492         have_tls_get = ins [0] == 0x65 &&
3493                        ins [1] == 0x48 &&
3494                        ins [2] == 0x8b &&
3495                        ins [3] == 0x04 &&
3496                        ins [4] == 0xfd &&
3497                        ins [6] == 0x00 &&
3498                        ins [7] == 0x00 &&
3499                        ins [8] == 0x00 &&
3500                        ins [9] == 0xc3;
3501
3502         tls_gs_offset = ins[5];
3503 #endif
3504
3505         inited = TRUE;
3506
3507         return have_tls_get;
3508 #elif defined(TARGET_ANDROID)
3509         return FALSE;
3510 #else
3511         return TRUE;
3512 #endif
3513 }
3514
3515 int
3516 mono_amd64_get_tls_gs_offset (void)
3517 {
3518 #ifdef TARGET_OSX
3519         return tls_gs_offset;
3520 #else
3521         g_assert_not_reached ();
3522         return -1;
3523 #endif
3524 }
3525
3526 /*
3527  * mono_amd64_emit_tls_get:
3528  * @code: buffer to store code to
3529  * @dreg: hard register where to place the result
3530  * @tls_offset: offset info
3531  *
3532  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3533  * the dreg register the item in the thread local storage identified
3534  * by tls_offset.
3535  *
3536  * Returns: a pointer to the end of the stored code
3537  */
3538 guint8*
3539 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3540 {
3541 #ifdef TARGET_WIN32
3542         if (tls_offset < 64) {
3543                 x86_prefix (code, X86_GS_PREFIX);
3544                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3545         } else {
3546                 guint8 *buf [16];
3547
3548                 g_assert (tls_offset < 0x440);
3549                 /* Load TEB->TlsExpansionSlots */
3550                 x86_prefix (code, X86_GS_PREFIX);
3551                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3552                 amd64_test_reg_reg (code, dreg, dreg);
3553                 buf [0] = code;
3554                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3555                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3556                 amd64_patch (buf [0], code);
3557         }
3558 #elif defined(__APPLE__)
3559         x86_prefix (code, X86_GS_PREFIX);
3560         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3561 #else
3562         if (optimize_for_xen) {
3563                 x86_prefix (code, X86_FS_PREFIX);
3564                 amd64_mov_reg_mem (code, dreg, 0, 8);
3565                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3566         } else {
3567                 x86_prefix (code, X86_FS_PREFIX);
3568                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3569         }
3570 #endif
3571         return code;
3572 }
3573
3574 static guint8*
3575 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3576 {
3577         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3578 #ifdef TARGET_OSX
3579         if (dreg != offset_reg)
3580                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3581         amd64_prefix (code, X86_GS_PREFIX);
3582         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3583 #elif defined(__linux__)
3584         int tmpreg = -1;
3585
3586         if (dreg == offset_reg) {
3587                 /* Use a temporary reg by saving it to the redzone */
3588                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3589                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3590                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3591                 offset_reg = tmpreg;
3592         }
3593         x86_prefix (code, X86_FS_PREFIX);
3594         amd64_mov_reg_mem (code, dreg, 0, 8);
3595         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3596         if (tmpreg != -1)
3597                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3598 #else
3599         g_assert_not_reached ();
3600 #endif
3601         return code;
3602 }
3603
3604 static guint8*
3605 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3606 {
3607 #ifdef TARGET_WIN32
3608         g_assert_not_reached ();
3609 #elif defined(__APPLE__)
3610         x86_prefix (code, X86_GS_PREFIX);
3611         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3612 #else
3613         g_assert (!optimize_for_xen);
3614         x86_prefix (code, X86_FS_PREFIX);
3615         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3616 #endif
3617         return code;
3618 }
3619
3620 static guint8*
3621 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3622 {
3623         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3624 #ifdef TARGET_WIN32
3625         g_assert_not_reached ();
3626 #elif defined(__APPLE__)
3627         x86_prefix (code, X86_GS_PREFIX);
3628         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3629 #else
3630         x86_prefix (code, X86_FS_PREFIX);
3631         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3632 #endif
3633         return code;
3634 }
3635
3636  /*
3637  * mono_arch_translate_tls_offset:
3638  *
3639  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3640  */
3641 int
3642 mono_arch_translate_tls_offset (int offset)
3643 {
3644 #ifdef __APPLE__
3645         return tls_gs_offset + (offset * 8);
3646 #else
3647         return offset;
3648 #endif
3649 }
3650
3651 /*
3652  * emit_setup_lmf:
3653  *
3654  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3655  */
3656 static guint8*
3657 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3658 {
3659         /*
3660          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3661          */
3662         /*
3663          * sp is saved right before calls but we need to save it here too so
3664          * async stack walks would work.
3665          */
3666         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3667         /* Save rbp */
3668         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3669         if (cfg->arch.omit_fp && cfa_offset != -1)
3670                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3671
3672         /* These can't contain refs */
3673         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3674         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3675         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3676         /* These are handled automatically by the stack marking code */
3677         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3678
3679         return code;
3680 }
3681
3682 #define REAL_PRINT_REG(text,reg) \
3683 mono_assert (reg >= 0); \
3684 amd64_push_reg (code, AMD64_RAX); \
3685 amd64_push_reg (code, AMD64_RDX); \
3686 amd64_push_reg (code, AMD64_RCX); \
3687 amd64_push_reg (code, reg); \
3688 amd64_push_imm (code, reg); \
3689 amd64_push_imm (code, text " %d %p\n"); \
3690 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3691 amd64_call_reg (code, AMD64_RAX); \
3692 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3693 amd64_pop_reg (code, AMD64_RCX); \
3694 amd64_pop_reg (code, AMD64_RDX); \
3695 amd64_pop_reg (code, AMD64_RAX);
3696
3697 /* benchmark and set based on cpu */
3698 #define LOOP_ALIGNMENT 8
3699 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3700
3701 #ifndef DISABLE_JIT
3702 void
3703 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3704 {
3705         MonoInst *ins;
3706         MonoCallInst *call;
3707         guint offset;
3708         guint8 *code = cfg->native_code + cfg->code_len;
3709         int max_len;
3710
3711         /* Fix max_offset estimate for each successor bb */
3712         if (cfg->opt & MONO_OPT_BRANCH) {
3713                 int current_offset = cfg->code_len;
3714                 MonoBasicBlock *current_bb;
3715                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3716                         current_bb->max_offset = current_offset;
3717                         current_offset += current_bb->max_length;
3718                 }
3719         }
3720
3721         if (cfg->opt & MONO_OPT_LOOP) {
3722                 int pad, align = LOOP_ALIGNMENT;
3723                 /* set alignment depending on cpu */
3724                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3725                         pad = align - pad;
3726                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3727                         amd64_padding (code, pad);
3728                         cfg->code_len += pad;
3729                         bb->native_offset = cfg->code_len;
3730                 }
3731         }
3732
3733 #if defined(__native_client_codegen__)
3734         /* For Native Client, all indirect call/jump targets must be */
3735         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3736         /* indirectly as well.                                       */
3737         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3738                                       (bb->flags & BB_EXCEPTION_HANDLER);
3739
3740         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3741                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3742                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3743                 cfg->code_len += pad;
3744                 bb->native_offset = cfg->code_len;
3745         }
3746 #endif  /*__native_client_codegen__*/
3747
3748         if (cfg->verbose_level > 2)
3749                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3750
3751         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3752                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3753                 g_assert (!cfg->compile_aot);
3754
3755                 cov->data [bb->dfn].cil_code = bb->cil_code;
3756                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3757                 /* this is not thread save, but good enough */
3758                 amd64_inc_membase (code, AMD64_R11, 0);
3759         }
3760
3761         offset = code - cfg->native_code;
3762
3763         mono_debug_open_block (cfg, bb, offset);
3764
3765     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3766                 x86_breakpoint (code);
3767
3768         MONO_BB_FOR_EACH_INS (bb, ins) {
3769                 offset = code - cfg->native_code;
3770
3771                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3772
3773 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3774
3775                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3776                         cfg->code_size *= 2;
3777                         cfg->native_code = mono_realloc_native_code(cfg);
3778                         code = cfg->native_code + offset;
3779                         cfg->stat_code_reallocs++;
3780                 }
3781
3782                 if (cfg->debug_info)
3783                         mono_debug_record_line_number (cfg, ins, offset);
3784
3785                 switch (ins->opcode) {
3786                 case OP_BIGMUL:
3787                         amd64_mul_reg (code, ins->sreg2, TRUE);
3788                         break;
3789                 case OP_BIGMUL_UN:
3790                         amd64_mul_reg (code, ins->sreg2, FALSE);
3791                         break;
3792                 case OP_X86_SETEQ_MEMBASE:
3793                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3794                         break;
3795                 case OP_STOREI1_MEMBASE_IMM:
3796                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3797                         break;
3798                 case OP_STOREI2_MEMBASE_IMM:
3799                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3800                         break;
3801                 case OP_STOREI4_MEMBASE_IMM:
3802                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3803                         break;
3804                 case OP_STOREI1_MEMBASE_REG:
3805                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3806                         break;
3807                 case OP_STOREI2_MEMBASE_REG:
3808                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3809                         break;
3810                 /* In AMD64 NaCl, pointers are 4 bytes, */
3811                 /*  so STORE_* != STOREI8_*. Likewise below. */
3812                 case OP_STORE_MEMBASE_REG:
3813                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3814                         break;
3815                 case OP_STOREI8_MEMBASE_REG:
3816                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3817                         break;
3818                 case OP_STOREI4_MEMBASE_REG:
3819                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3820                         break;
3821                 case OP_STORE_MEMBASE_IMM:
3822 #ifndef __native_client_codegen__
3823                         /* In NaCl, this could be a PCONST type, which could */
3824                         /* mean a pointer type was copied directly into the  */
3825                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3826                         /* the value would be 0x00000000FFFFFFFF which is    */
3827                         /* not proper for an imm32 unless you cast it.       */
3828                         g_assert (amd64_is_imm32 (ins->inst_imm));
3829 #endif
3830                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3831                         break;
3832                 case OP_STOREI8_MEMBASE_IMM:
3833                         g_assert (amd64_is_imm32 (ins->inst_imm));
3834                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3835                         break;
3836                 case OP_LOAD_MEM:
3837 #ifdef __mono_ilp32__
3838                         /* In ILP32, pointers are 4 bytes, so separate these */
3839                         /* cases, use literal 8 below where we really want 8 */
3840                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3841                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3842                         break;
3843 #endif
3844                 case OP_LOADI8_MEM:
3845                         // FIXME: Decompose this earlier
3846                         if (amd64_is_imm32 (ins->inst_imm))
3847                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3848                         else {
3849                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3850                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3851                         }
3852                         break;
3853                 case OP_LOADI4_MEM:
3854                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3855                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3856                         break;
3857                 case OP_LOADU4_MEM:
3858                         // FIXME: Decompose this earlier
3859                         if (amd64_is_imm32 (ins->inst_imm))
3860                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3861                         else {
3862                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3863                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3864                         }
3865                         break;
3866                 case OP_LOADU1_MEM:
3867                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3868                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3869                         break;
3870                 case OP_LOADU2_MEM:
3871                         /* For NaCl, pointers are 4 bytes, so separate these */
3872                         /* cases, use literal 8 below where we really want 8 */
3873                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3874                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3875                         break;
3876                 case OP_LOAD_MEMBASE:
3877                         g_assert (amd64_is_imm32 (ins->inst_offset));
3878                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3879                         break;
3880                 case OP_LOADI8_MEMBASE:
3881                         /* Use literal 8 instead of sizeof pointer or */
3882                         /* register, we really want 8 for this opcode */
3883                         g_assert (amd64_is_imm32 (ins->inst_offset));
3884                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3885                         break;
3886                 case OP_LOADI4_MEMBASE:
3887                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3888                         break;
3889                 case OP_LOADU4_MEMBASE:
3890                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3891                         break;
3892                 case OP_LOADU1_MEMBASE:
3893                         /* The cpu zero extends the result into 64 bits */
3894                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3895                         break;
3896                 case OP_LOADI1_MEMBASE:
3897                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3898                         break;
3899                 case OP_LOADU2_MEMBASE:
3900                         /* The cpu zero extends the result into 64 bits */
3901                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3902                         break;
3903                 case OP_LOADI2_MEMBASE:
3904                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3905                         break;
3906                 case OP_AMD64_LOADI8_MEMINDEX:
3907                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3908                         break;
3909                 case OP_LCONV_TO_I1:
3910                 case OP_ICONV_TO_I1:
3911                 case OP_SEXT_I1:
3912                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3913                         break;
3914                 case OP_LCONV_TO_I2:
3915                 case OP_ICONV_TO_I2:
3916                 case OP_SEXT_I2:
3917                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3918                         break;
3919                 case OP_LCONV_TO_U1:
3920                 case OP_ICONV_TO_U1:
3921                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3922                         break;
3923                 case OP_LCONV_TO_U2:
3924                 case OP_ICONV_TO_U2:
3925                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3926                         break;
3927                 case OP_ZEXT_I4:
3928                         /* Clean out the upper word */
3929                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3930                         break;
3931                 case OP_SEXT_I4:
3932                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3933                         break;
3934                 case OP_COMPARE:
3935                 case OP_LCOMPARE:
3936                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3937                         break;
3938                 case OP_COMPARE_IMM:
3939 #if defined(__mono_ilp32__)
3940                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3941                         g_assert (amd64_is_imm32 (ins->inst_imm));
3942                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3943                         break;
3944 #endif
3945                 case OP_LCOMPARE_IMM:
3946                         g_assert (amd64_is_imm32 (ins->inst_imm));
3947                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3948                         break;
3949                 case OP_X86_COMPARE_REG_MEMBASE:
3950                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3951                         break;
3952                 case OP_X86_TEST_NULL:
3953                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3954                         break;
3955                 case OP_AMD64_TEST_NULL:
3956                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3957                         break;
3958
3959                 case OP_X86_ADD_REG_MEMBASE:
3960                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3961                         break;
3962                 case OP_X86_SUB_REG_MEMBASE:
3963                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3964                         break;
3965                 case OP_X86_AND_REG_MEMBASE:
3966                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3967                         break;
3968                 case OP_X86_OR_REG_MEMBASE:
3969                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3970                         break;
3971                 case OP_X86_XOR_REG_MEMBASE:
3972                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3973                         break;
3974
3975                 case OP_X86_ADD_MEMBASE_IMM:
3976                         /* FIXME: Make a 64 version too */
3977                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3978                         break;
3979                 case OP_X86_SUB_MEMBASE_IMM:
3980                         g_assert (amd64_is_imm32 (ins->inst_imm));
3981                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3982                         break;
3983                 case OP_X86_AND_MEMBASE_IMM:
3984                         g_assert (amd64_is_imm32 (ins->inst_imm));
3985                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3986                         break;
3987                 case OP_X86_OR_MEMBASE_IMM:
3988                         g_assert (amd64_is_imm32 (ins->inst_imm));
3989                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3990                         break;
3991                 case OP_X86_XOR_MEMBASE_IMM:
3992                         g_assert (amd64_is_imm32 (ins->inst_imm));
3993                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3994                         break;
3995                 case OP_X86_ADD_MEMBASE_REG:
3996                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3997                         break;
3998                 case OP_X86_SUB_MEMBASE_REG:
3999                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4000                         break;
4001                 case OP_X86_AND_MEMBASE_REG:
4002                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4003                         break;
4004                 case OP_X86_OR_MEMBASE_REG:
4005                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4006                         break;
4007                 case OP_X86_XOR_MEMBASE_REG:
4008                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4009                         break;
4010                 case OP_X86_INC_MEMBASE:
4011                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4012                         break;
4013                 case OP_X86_INC_REG:
4014                         amd64_inc_reg_size (code, ins->dreg, 4);
4015                         break;
4016                 case OP_X86_DEC_MEMBASE:
4017                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4018                         break;
4019                 case OP_X86_DEC_REG:
4020                         amd64_dec_reg_size (code, ins->dreg, 4);
4021                         break;
4022                 case OP_X86_MUL_REG_MEMBASE:
4023                 case OP_X86_MUL_MEMBASE_REG:
4024                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4025                         break;
4026                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4027                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4028                         break;
4029                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4030                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4031                         break;
4032                 case OP_AMD64_COMPARE_MEMBASE_REG:
4033                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4034                         break;
4035                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4036                         g_assert (amd64_is_imm32 (ins->inst_imm));
4037                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4038                         break;
4039                 case OP_X86_COMPARE_MEMBASE8_IMM:
4040                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4041                         break;
4042                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4043                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4044                         break;
4045                 case OP_AMD64_COMPARE_REG_MEMBASE:
4046                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4047                         break;
4048
4049                 case OP_AMD64_ADD_REG_MEMBASE:
4050                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4051                         break;
4052                 case OP_AMD64_SUB_REG_MEMBASE:
4053                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4054                         break;
4055                 case OP_AMD64_AND_REG_MEMBASE:
4056                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4057                         break;
4058                 case OP_AMD64_OR_REG_MEMBASE:
4059                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4060                         break;
4061                 case OP_AMD64_XOR_REG_MEMBASE:
4062                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4063                         break;
4064
4065                 case OP_AMD64_ADD_MEMBASE_REG:
4066                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4067                         break;
4068                 case OP_AMD64_SUB_MEMBASE_REG:
4069                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4070                         break;
4071                 case OP_AMD64_AND_MEMBASE_REG:
4072                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4073                         break;
4074                 case OP_AMD64_OR_MEMBASE_REG:
4075                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4076                         break;
4077                 case OP_AMD64_XOR_MEMBASE_REG:
4078                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4079                         break;
4080
4081                 case OP_AMD64_ADD_MEMBASE_IMM:
4082                         g_assert (amd64_is_imm32 (ins->inst_imm));
4083                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4084                         break;
4085                 case OP_AMD64_SUB_MEMBASE_IMM:
4086                         g_assert (amd64_is_imm32 (ins->inst_imm));
4087                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4088                         break;
4089                 case OP_AMD64_AND_MEMBASE_IMM:
4090                         g_assert (amd64_is_imm32 (ins->inst_imm));
4091                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4092                         break;
4093                 case OP_AMD64_OR_MEMBASE_IMM:
4094                         g_assert (amd64_is_imm32 (ins->inst_imm));
4095                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4096                         break;
4097                 case OP_AMD64_XOR_MEMBASE_IMM:
4098                         g_assert (amd64_is_imm32 (ins->inst_imm));
4099                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4100                         break;
4101
4102                 case OP_BREAK:
4103                         amd64_breakpoint (code);
4104                         break;
4105                 case OP_RELAXED_NOP:
4106                         x86_prefix (code, X86_REP_PREFIX);
4107                         x86_nop (code);
4108                         break;
4109                 case OP_HARD_NOP:
4110                         x86_nop (code);
4111                         break;
4112                 case OP_NOP:
4113                 case OP_DUMMY_USE:
4114                 case OP_DUMMY_STORE:
4115                 case OP_DUMMY_ICONST:
4116                 case OP_DUMMY_R8CONST:
4117                 case OP_NOT_REACHED:
4118                 case OP_NOT_NULL:
4119                         break;
4120                 case OP_IL_SEQ_POINT:
4121                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4122                         break;
4123                 case OP_SEQ_POINT: {
4124                         int i;
4125
4126                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4127                                 if (cfg->compile_aot) {
4128                                         MonoInst *var = cfg->arch.ss_tramp_var;
4129                                         guint8 *label;
4130
4131                                         /* Load ss_tramp_var */
4132                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4133                                         /* Load the trampoline address */
4134                                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4135                                         /* Call it if it is non-null */
4136                                         amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4137                                         label = code;
4138                                         amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4139                                         amd64_call_reg (code, AMD64_R11);
4140                                         amd64_patch (label, code);
4141                                 } else {
4142                                         /*
4143                                          * Read from the single stepping trigger page. This will cause a
4144                                          * SIGSEGV when single stepping is enabled.
4145                                          * We do this _before_ the breakpoint, so single stepping after
4146                                          * a breakpoint is hit will step to the next IL offset.
4147                                          */
4148                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
4149
4150                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4151                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4152                                 }
4153                         }
4154
4155                         /*
4156                          * This is the address which is saved in seq points,
4157                          */
4158                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4159
4160                         if (cfg->compile_aot) {
4161                                 guint32 offset = code - cfg->native_code;
4162                                 guint32 val;
4163                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4164                                 guint8 *label;
4165
4166                                 /* Load info var */
4167                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4168                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4169                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4170                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4171                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4172                                 label = code;
4173                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4174                                 /* Call the trampoline */
4175                                 amd64_call_reg (code, AMD64_R11);
4176                                 amd64_patch (label, code);
4177                         } else {
4178                                 /*
4179                                  * A placeholder for a possible breakpoint inserted by
4180                                  * mono_arch_set_breakpoint ().
4181                                  */
4182                                 for (i = 0; i < breakpoint_size; ++i)
4183                                         x86_nop (code);
4184                         }
4185                         /*
4186                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4187                          * to another IL offset.
4188                          */
4189                         x86_nop (code);
4190                         break;
4191                 }
4192                 case OP_ADDCC:
4193                 case OP_LADDCC:
4194                 case OP_LADD:
4195                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4196                         break;
4197                 case OP_ADC:
4198                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4199                         break;
4200                 case OP_ADD_IMM:
4201                 case OP_LADD_IMM:
4202                         g_assert (amd64_is_imm32 (ins->inst_imm));
4203                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4204                         break;
4205                 case OP_ADC_IMM:
4206                         g_assert (amd64_is_imm32 (ins->inst_imm));
4207                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4208                         break;
4209                 case OP_SUBCC:
4210                 case OP_LSUBCC:
4211                 case OP_LSUB:
4212                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4213                         break;
4214                 case OP_SBB:
4215                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4216                         break;
4217                 case OP_SUB_IMM:
4218                 case OP_LSUB_IMM:
4219                         g_assert (amd64_is_imm32 (ins->inst_imm));
4220                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4221                         break;
4222                 case OP_SBB_IMM:
4223                         g_assert (amd64_is_imm32 (ins->inst_imm));
4224                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4225                         break;
4226                 case OP_LAND:
4227                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4228                         break;
4229                 case OP_AND_IMM:
4230                 case OP_LAND_IMM:
4231                         g_assert (amd64_is_imm32 (ins->inst_imm));
4232                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4233                         break;
4234                 case OP_LMUL:
4235                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4236                         break;
4237                 case OP_MUL_IMM:
4238                 case OP_LMUL_IMM:
4239                 case OP_IMUL_IMM: {
4240                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4241
4242                         switch (ins->inst_imm) {
4243                         case 2:
4244                                 /* MOV r1, r2 */
4245                                 /* ADD r1, r1 */
4246                                 if (ins->dreg != ins->sreg1)
4247                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4248                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4249                                 break;
4250                         case 3:
4251                                 /* LEA r1, [r2 + r2*2] */
4252                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4253                                 break;
4254                         case 5:
4255                                 /* LEA r1, [r2 + r2*4] */
4256                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4257                                 break;
4258                         case 6:
4259                                 /* LEA r1, [r2 + r2*2] */
4260                                 /* ADD r1, r1          */
4261                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4262                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4263                                 break;
4264                         case 9:
4265                                 /* LEA r1, [r2 + r2*8] */
4266                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4267                                 break;
4268                         case 10:
4269                                 /* LEA r1, [r2 + r2*4] */
4270                                 /* ADD r1, r1          */
4271                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4272                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4273                                 break;
4274                         case 12:
4275                                 /* LEA r1, [r2 + r2*2] */
4276                                 /* SHL r1, 2           */
4277                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4278                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4279                                 break;
4280                         case 25:
4281                                 /* LEA r1, [r2 + r2*4] */
4282                                 /* LEA r1, [r1 + r1*4] */
4283                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4284                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4285                                 break;
4286                         case 100:
4287                                 /* LEA r1, [r2 + r2*4] */
4288                                 /* SHL r1, 2           */
4289                                 /* LEA r1, [r1 + r1*4] */
4290                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4291                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4292                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4293                                 break;
4294                         default:
4295                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4296                                 break;
4297                         }
4298                         break;
4299                 }
4300                 case OP_LDIV:
4301                 case OP_LREM:
4302 #if defined( __native_client_codegen__ )
4303                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4304                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4305 #endif
4306                         /* Regalloc magic makes the div/rem cases the same */
4307                         if (ins->sreg2 == AMD64_RDX) {
4308                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4309                                 amd64_cdq (code);
4310                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4311                         } else {
4312                                 amd64_cdq (code);
4313                                 amd64_div_reg (code, ins->sreg2, TRUE);
4314                         }
4315                         break;
4316                 case OP_LDIV_UN:
4317                 case OP_LREM_UN:
4318 #if defined( __native_client_codegen__ )
4319                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4320                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4321 #endif
4322                         if (ins->sreg2 == AMD64_RDX) {
4323                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4324                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4325                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4326                         } else {
4327                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4328                                 amd64_div_reg (code, ins->sreg2, FALSE);
4329                         }
4330                         break;
4331                 case OP_IDIV:
4332                 case OP_IREM:
4333 #if defined( __native_client_codegen__ )
4334                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4335                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4336 #endif
4337                         if (ins->sreg2 == AMD64_RDX) {
4338                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4339                                 amd64_cdq_size (code, 4);
4340                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4341                         } else {
4342                                 amd64_cdq_size (code, 4);
4343                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4344                         }
4345                         break;
4346                 case OP_IDIV_UN:
4347                 case OP_IREM_UN:
4348 #if defined( __native_client_codegen__ )
4349                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4350                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4351 #endif
4352                         if (ins->sreg2 == AMD64_RDX) {
4353                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4354                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4355                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4356                         } else {
4357                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4358                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4359                         }
4360                         break;
4361                 case OP_LMUL_OVF:
4362                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4363                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4364                         break;
4365                 case OP_LOR:
4366                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4367                         break;
4368                 case OP_OR_IMM:
4369                 case OP_LOR_IMM:
4370                         g_assert (amd64_is_imm32 (ins->inst_imm));
4371                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4372                         break;
4373                 case OP_LXOR:
4374                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4375                         break;
4376                 case OP_XOR_IMM:
4377                 case OP_LXOR_IMM:
4378                         g_assert (amd64_is_imm32 (ins->inst_imm));
4379                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4380                         break;
4381                 case OP_LSHL:
4382                         g_assert (ins->sreg2 == AMD64_RCX);
4383                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4384                         break;
4385                 case OP_LSHR:
4386                         g_assert (ins->sreg2 == AMD64_RCX);
4387                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4388                         break;
4389                 case OP_SHR_IMM:
4390                 case OP_LSHR_IMM:
4391                         g_assert (amd64_is_imm32 (ins->inst_imm));
4392                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4393                         break;
4394                 case OP_SHR_UN_IMM:
4395                         g_assert (amd64_is_imm32 (ins->inst_imm));
4396                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4397                         break;
4398                 case OP_LSHR_UN_IMM:
4399                         g_assert (amd64_is_imm32 (ins->inst_imm));
4400                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4401                         break;
4402                 case OP_LSHR_UN:
4403                         g_assert (ins->sreg2 == AMD64_RCX);
4404                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4405                         break;
4406                 case OP_SHL_IMM:
4407                 case OP_LSHL_IMM:
4408                         g_assert (amd64_is_imm32 (ins->inst_imm));
4409                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4410                         break;
4411
4412                 case OP_IADDCC:
4413                 case OP_IADD:
4414                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4415                         break;
4416                 case OP_IADC:
4417                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4418                         break;
4419                 case OP_IADD_IMM:
4420                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4421                         break;
4422                 case OP_IADC_IMM:
4423                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4424                         break;
4425                 case OP_ISUBCC:
4426                 case OP_ISUB:
4427                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4428                         break;
4429                 case OP_ISBB:
4430                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4431                         break;
4432                 case OP_ISUB_IMM:
4433                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4434                         break;
4435                 case OP_ISBB_IMM:
4436                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4437                         break;
4438                 case OP_IAND:
4439                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4440                         break;
4441                 case OP_IAND_IMM:
4442                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4443                         break;
4444                 case OP_IOR:
4445                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4446                         break;
4447                 case OP_IOR_IMM:
4448                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4449                         break;
4450                 case OP_IXOR:
4451                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4452                         break;
4453                 case OP_IXOR_IMM:
4454                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4455                         break;
4456                 case OP_INEG:
4457                         amd64_neg_reg_size (code, ins->sreg1, 4);
4458                         break;
4459                 case OP_INOT:
4460                         amd64_not_reg_size (code, ins->sreg1, 4);
4461                         break;
4462                 case OP_ISHL:
4463                         g_assert (ins->sreg2 == AMD64_RCX);
4464                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4465                         break;
4466                 case OP_ISHR:
4467                         g_assert (ins->sreg2 == AMD64_RCX);
4468                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4469                         break;
4470                 case OP_ISHR_IMM:
4471                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4472                         break;
4473                 case OP_ISHR_UN_IMM:
4474                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4475                         break;
4476                 case OP_ISHR_UN:
4477                         g_assert (ins->sreg2 == AMD64_RCX);
4478                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4479                         break;
4480                 case OP_ISHL_IMM:
4481                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4482                         break;
4483                 case OP_IMUL:
4484                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4485                         break;
4486                 case OP_IMUL_OVF:
4487                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4488                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4489                         break;
4490                 case OP_IMUL_OVF_UN:
4491                 case OP_LMUL_OVF_UN: {
4492                         /* the mul operation and the exception check should most likely be split */
4493                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4494                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4495                         /*g_assert (ins->sreg2 == X86_EAX);
4496                         g_assert (ins->dreg == X86_EAX);*/
4497                         if (ins->sreg2 == X86_EAX) {
4498                                 non_eax_reg = ins->sreg1;
4499                         } else if (ins->sreg1 == X86_EAX) {
4500                                 non_eax_reg = ins->sreg2;
4501                         } else {
4502                                 /* no need to save since we're going to store to it anyway */
4503                                 if (ins->dreg != X86_EAX) {
4504                                         saved_eax = TRUE;
4505                                         amd64_push_reg (code, X86_EAX);
4506                                 }
4507                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4508                                 non_eax_reg = ins->sreg2;
4509                         }
4510                         if (ins->dreg == X86_EDX) {
4511                                 if (!saved_eax) {
4512                                         saved_eax = TRUE;
4513                                         amd64_push_reg (code, X86_EAX);
4514                                 }
4515                         } else {
4516                                 saved_edx = TRUE;
4517                                 amd64_push_reg (code, X86_EDX);
4518                         }
4519                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4520                         /* save before the check since pop and mov don't change the flags */
4521                         if (ins->dreg != X86_EAX)
4522                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4523                         if (saved_edx)
4524                                 amd64_pop_reg (code, X86_EDX);
4525                         if (saved_eax)
4526                                 amd64_pop_reg (code, X86_EAX);
4527                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4528                         break;
4529                 }
4530                 case OP_ICOMPARE:
4531                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4532                         break;
4533                 case OP_ICOMPARE_IMM:
4534                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4535                         break;
4536                 case OP_IBEQ:
4537                 case OP_IBLT:
4538                 case OP_IBGT:
4539                 case OP_IBGE:
4540                 case OP_IBLE:
4541                 case OP_LBEQ:
4542                 case OP_LBLT:
4543                 case OP_LBGT:
4544                 case OP_LBGE:
4545                 case OP_LBLE:
4546                 case OP_IBNE_UN:
4547                 case OP_IBLT_UN:
4548                 case OP_IBGT_UN:
4549                 case OP_IBGE_UN:
4550                 case OP_IBLE_UN:
4551                 case OP_LBNE_UN:
4552                 case OP_LBLT_UN:
4553                 case OP_LBGT_UN:
4554                 case OP_LBGE_UN:
4555                 case OP_LBLE_UN:
4556                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4557                         break;
4558
4559                 case OP_CMOV_IEQ:
4560                 case OP_CMOV_IGE:
4561                 case OP_CMOV_IGT:
4562                 case OP_CMOV_ILE:
4563                 case OP_CMOV_ILT:
4564                 case OP_CMOV_INE_UN:
4565                 case OP_CMOV_IGE_UN:
4566                 case OP_CMOV_IGT_UN:
4567                 case OP_CMOV_ILE_UN:
4568                 case OP_CMOV_ILT_UN:
4569                 case OP_CMOV_LEQ:
4570                 case OP_CMOV_LGE:
4571                 case OP_CMOV_LGT:
4572                 case OP_CMOV_LLE:
4573                 case OP_CMOV_LLT:
4574                 case OP_CMOV_LNE_UN:
4575                 case OP_CMOV_LGE_UN:
4576                 case OP_CMOV_LGT_UN:
4577                 case OP_CMOV_LLE_UN:
4578                 case OP_CMOV_LLT_UN:
4579                         g_assert (ins->dreg == ins->sreg1);
4580                         /* This needs to operate on 64 bit values */
4581                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4582                         break;
4583
4584                 case OP_LNOT:
4585                         amd64_not_reg (code, ins->sreg1);
4586                         break;
4587                 case OP_LNEG:
4588                         amd64_neg_reg (code, ins->sreg1);
4589                         break;
4590
4591                 case OP_ICONST:
4592                 case OP_I8CONST:
4593                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4594                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4595                         else
4596                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4597                         break;
4598                 case OP_AOTCONST:
4599                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4600                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4601                         break;
4602                 case OP_JUMP_TABLE:
4603                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4604                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4605                         break;
4606                 case OP_MOVE:
4607                         if (ins->dreg != ins->sreg1)
4608                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4609                         break;
4610                 case OP_AMD64_SET_XMMREG_R4: {
4611                         if (cfg->r4fp) {
4612                                 if (ins->dreg != ins->sreg1)
4613                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4614                         } else {
4615                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4616                         }
4617                         break;
4618                 }
4619                 case OP_AMD64_SET_XMMREG_R8: {
4620                         if (ins->dreg != ins->sreg1)
4621                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4622                         break;
4623                 }
4624                 case OP_TAILCALL: {
4625                         MonoCallInst *call = (MonoCallInst*)ins;
4626                         int i, save_area_offset;
4627
4628                         g_assert (!cfg->method->save_lmf);
4629
4630                         /* Restore callee saved registers */
4631                         save_area_offset = cfg->arch.reg_save_area_offset;
4632                         for (i = 0; i < AMD64_NREG; ++i)
4633                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4634                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4635                                         save_area_offset += 8;
4636                                 }
4637
4638                         if (cfg->arch.omit_fp) {
4639                                 if (cfg->arch.stack_alloc_size)
4640                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4641                                 // FIXME:
4642                                 if (call->stack_usage)
4643                                         NOT_IMPLEMENTED;
4644                         } else {
4645                                 /* Copy arguments on the stack to our argument area */
4646                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4647                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4648                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4649                                 }
4650
4651                                 amd64_leave (code);
4652                         }
4653
4654                         offset = code - cfg->native_code;
4655                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4656                         if (cfg->compile_aot)
4657                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4658                         else
4659                                 amd64_set_reg_template (code, AMD64_R11);
4660                         amd64_jump_reg (code, AMD64_R11);
4661                         ins->flags |= MONO_INST_GC_CALLSITE;
4662                         ins->backend.pc_offset = code - cfg->native_code;
4663                         break;
4664                 }
4665                 case OP_CHECK_THIS:
4666                         /* ensure ins->sreg1 is not NULL */
4667                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4668                         break;
4669                 case OP_ARGLIST: {
4670                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4671                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4672                         break;
4673                 }
4674                 case OP_CALL:
4675                 case OP_FCALL:
4676                 case OP_RCALL:
4677                 case OP_LCALL:
4678                 case OP_VCALL:
4679                 case OP_VCALL2:
4680                 case OP_VOIDCALL:
4681                         call = (MonoCallInst*)ins;
4682                         /*
4683                          * The AMD64 ABI forces callers to know about varargs.
4684                          */
4685                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4686                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4687                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4688                                 /*
4689                                  * Since the unmanaged calling convention doesn't contain a
4690                                  * 'vararg' entry, we have to treat every pinvoke call as a
4691                                  * potential vararg call.
4692                                  */
4693                                 guint32 nregs, i;
4694                                 nregs = 0;
4695                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4696                                         if (call->used_fregs & (1 << i))
4697                                                 nregs ++;
4698                                 if (!nregs)
4699                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4700                                 else
4701                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4702                         }
4703
4704                         if (ins->flags & MONO_INST_HAS_METHOD)
4705                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4706                         else
4707                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4708                         ins->flags |= MONO_INST_GC_CALLSITE;
4709                         ins->backend.pc_offset = code - cfg->native_code;
4710                         code = emit_move_return_value (cfg, ins, code);
4711                         break;
4712                 case OP_FCALL_REG:
4713                 case OP_RCALL_REG:
4714                 case OP_LCALL_REG:
4715                 case OP_VCALL_REG:
4716                 case OP_VCALL2_REG:
4717                 case OP_VOIDCALL_REG:
4718                 case OP_CALL_REG:
4719                         call = (MonoCallInst*)ins;
4720
4721                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4722                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4723                                 ins->sreg1 = AMD64_R11;
4724                         }
4725
4726                         /*
4727                          * The AMD64 ABI forces callers to know about varargs.
4728                          */
4729                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4730                                 if (ins->sreg1 == AMD64_RAX) {
4731                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4732                                         ins->sreg1 = AMD64_R11;
4733                                 }
4734                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4735                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4736                                 /*
4737                                  * Since the unmanaged calling convention doesn't contain a
4738                                  * 'vararg' entry, we have to treat every pinvoke call as a
4739                                  * potential vararg call.
4740                                  */
4741                                 guint32 nregs, i;
4742                                 nregs = 0;
4743                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4744                                         if (call->used_fregs & (1 << i))
4745                                                 nregs ++;
4746                                 if (ins->sreg1 == AMD64_RAX) {
4747                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4748                                         ins->sreg1 = AMD64_R11;
4749                                 }
4750                                 if (!nregs)
4751                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4752                                 else
4753                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4754                         }
4755
4756                         amd64_call_reg (code, ins->sreg1);
4757                         ins->flags |= MONO_INST_GC_CALLSITE;
4758                         ins->backend.pc_offset = code - cfg->native_code;
4759                         code = emit_move_return_value (cfg, ins, code);
4760                         break;
4761                 case OP_FCALL_MEMBASE:
4762                 case OP_RCALL_MEMBASE:
4763                 case OP_LCALL_MEMBASE:
4764                 case OP_VCALL_MEMBASE:
4765                 case OP_VCALL2_MEMBASE:
4766                 case OP_VOIDCALL_MEMBASE:
4767                 case OP_CALL_MEMBASE:
4768                         call = (MonoCallInst*)ins;
4769
4770                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4771                         ins->flags |= MONO_INST_GC_CALLSITE;
4772                         ins->backend.pc_offset = code - cfg->native_code;
4773                         code = emit_move_return_value (cfg, ins, code);
4774                         break;
4775                 case OP_DYN_CALL: {
4776                         int i;
4777                         MonoInst *var = cfg->dyn_call_var;
4778
4779                         g_assert (var->opcode == OP_REGOFFSET);
4780
4781                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4782                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4783                         /* r10 = ftn */
4784                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4785
4786                         /* Save args buffer */
4787                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4788
4789                         /* Set argument registers */
4790                         for (i = 0; i < PARAM_REGS; ++i)
4791                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4792
4793                         /* Make the call */
4794                         amd64_call_reg (code, AMD64_R10);
4795
4796                         ins->flags |= MONO_INST_GC_CALLSITE;
4797                         ins->backend.pc_offset = code - cfg->native_code;
4798
4799                         /* Save result */
4800                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4801                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4802                         break;
4803                 }
4804                 case OP_AMD64_SAVE_SP_TO_LMF: {
4805                         MonoInst *lmf_var = cfg->lmf_var;
4806                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4807                         break;
4808                 }
4809                 case OP_X86_PUSH:
4810                         g_assert_not_reached ();
4811                         amd64_push_reg (code, ins->sreg1);
4812                         break;
4813                 case OP_X86_PUSH_IMM:
4814                         g_assert_not_reached ();
4815                         g_assert (amd64_is_imm32 (ins->inst_imm));
4816                         amd64_push_imm (code, ins->inst_imm);
4817                         break;
4818                 case OP_X86_PUSH_MEMBASE:
4819                         g_assert_not_reached ();
4820                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4821                         break;
4822                 case OP_X86_PUSH_OBJ: {
4823                         int size = ALIGN_TO (ins->inst_imm, 8);
4824
4825                         g_assert_not_reached ();
4826
4827                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4828                         amd64_push_reg (code, AMD64_RDI);
4829                         amd64_push_reg (code, AMD64_RSI);
4830                         amd64_push_reg (code, AMD64_RCX);
4831                         if (ins->inst_offset)
4832                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4833                         else
4834                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4835                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4836                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4837                         amd64_cld (code);
4838                         amd64_prefix (code, X86_REP_PREFIX);
4839                         amd64_movsd (code);
4840                         amd64_pop_reg (code, AMD64_RCX);
4841                         amd64_pop_reg (code, AMD64_RSI);
4842                         amd64_pop_reg (code, AMD64_RDI);
4843                         break;
4844                 }
4845                 case OP_GENERIC_CLASS_INIT: {
4846                         static int byte_offset = -1;
4847                         static guint8 bitmask;
4848                         guint8 *jump;
4849
4850                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4851
4852                         if (byte_offset < 0)
4853                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4854
4855                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4856                         jump = code;
4857                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4858
4859                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4860                         ins->flags |= MONO_INST_GC_CALLSITE;
4861                         ins->backend.pc_offset = code - cfg->native_code;
4862
4863                         x86_patch (jump, code);
4864                         break;
4865                 }
4866
4867                 case OP_X86_LEA:
4868                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4869                         break;
4870                 case OP_X86_LEA_MEMBASE:
4871                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4872                         break;
4873                 case OP_X86_XCHG:
4874                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4875                         break;
4876                 case OP_LOCALLOC:
4877                         /* keep alignment */
4878                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4879                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4880                         code = mono_emit_stack_alloc (cfg, code, ins);
4881                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4882                         if (cfg->param_area)
4883                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4884                         break;
4885                 case OP_LOCALLOC_IMM: {
4886                         guint32 size = ins->inst_imm;
4887                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4888
4889                         if (ins->flags & MONO_INST_INIT) {
4890                                 if (size < 64) {
4891                                         int i;
4892
4893                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4894                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4895
4896                                         for (i = 0; i < size; i += 8)
4897                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4898                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4899                                 } else {
4900                                         amd64_mov_reg_imm (code, ins->dreg, size);
4901                                         ins->sreg1 = ins->dreg;
4902
4903                                         code = mono_emit_stack_alloc (cfg, code, ins);
4904                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4905                                 }
4906                         } else {
4907                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4908                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4909                         }
4910                         if (cfg->param_area)
4911                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4912                         break;
4913                 }
4914                 case OP_THROW: {
4915                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4916                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4917                                              (gpointer)"mono_arch_throw_exception", FALSE);
4918                         ins->flags |= MONO_INST_GC_CALLSITE;
4919                         ins->backend.pc_offset = code - cfg->native_code;
4920                         break;
4921                 }
4922                 case OP_RETHROW: {
4923                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4924                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4925                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4926                         ins->flags |= MONO_INST_GC_CALLSITE;
4927                         ins->backend.pc_offset = code - cfg->native_code;
4928                         break;
4929                 }
4930                 case OP_CALL_HANDLER:
4931                         /* Align stack */
4932                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4933                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4934                         amd64_call_imm (code, 0);
4935                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4936                         /* Restore stack alignment */
4937                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4938                         break;
4939                 case OP_START_HANDLER: {
4940                         /* Even though we're saving RSP, use sizeof */
4941                         /* gpointer because spvar is of type IntPtr */
4942                         /* see: mono_create_spvar_for_region */
4943                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4944                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4945
4946                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4947                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4948                                 cfg->param_area) {
4949                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4950                         }
4951                         break;
4952                 }
4953                 case OP_ENDFINALLY: {
4954                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4955                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4956                         amd64_ret (code);
4957                         break;
4958                 }
4959                 case OP_ENDFILTER: {
4960                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4961                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4962                         /* The local allocator will put the result into RAX */
4963                         amd64_ret (code);
4964                         break;
4965                 }
4966                 case OP_GET_EX_OBJ:
4967                         if (ins->dreg != AMD64_RAX)
4968                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4969                         break;
4970                 case OP_LABEL:
4971                         ins->inst_c0 = code - cfg->native_code;
4972                         break;
4973                 case OP_BR:
4974                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4975                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4976                         //break;
4977                                 if (ins->inst_target_bb->native_offset) {
4978                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4979                                 } else {
4980                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4981                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4982                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4983                                                 x86_jump8 (code, 0);
4984                                         else
4985                                                 x86_jump32 (code, 0);
4986                         }
4987                         break;
4988                 case OP_BR_REG:
4989                         amd64_jump_reg (code, ins->sreg1);
4990                         break;
4991                 case OP_ICNEQ:
4992                 case OP_ICGE:
4993                 case OP_ICLE:
4994                 case OP_ICGE_UN:
4995                 case OP_ICLE_UN:
4996
4997                 case OP_CEQ:
4998                 case OP_LCEQ:
4999                 case OP_ICEQ:
5000                 case OP_CLT:
5001                 case OP_LCLT:
5002                 case OP_ICLT:
5003                 case OP_CGT:
5004                 case OP_ICGT:
5005                 case OP_LCGT:
5006                 case OP_CLT_UN:
5007                 case OP_LCLT_UN:
5008                 case OP_ICLT_UN:
5009                 case OP_CGT_UN:
5010                 case OP_LCGT_UN:
5011                 case OP_ICGT_UN:
5012                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5013                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5014                         break;
5015                 case OP_COND_EXC_EQ:
5016                 case OP_COND_EXC_NE_UN:
5017                 case OP_COND_EXC_LT:
5018                 case OP_COND_EXC_LT_UN:
5019                 case OP_COND_EXC_GT:
5020                 case OP_COND_EXC_GT_UN:
5021                 case OP_COND_EXC_GE:
5022                 case OP_COND_EXC_GE_UN:
5023                 case OP_COND_EXC_LE:
5024                 case OP_COND_EXC_LE_UN:
5025                 case OP_COND_EXC_IEQ:
5026                 case OP_COND_EXC_INE_UN:
5027                 case OP_COND_EXC_ILT:
5028                 case OP_COND_EXC_ILT_UN:
5029                 case OP_COND_EXC_IGT:
5030                 case OP_COND_EXC_IGT_UN:
5031                 case OP_COND_EXC_IGE:
5032                 case OP_COND_EXC_IGE_UN:
5033                 case OP_COND_EXC_ILE:
5034                 case OP_COND_EXC_ILE_UN:
5035                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5036                         break;
5037                 case OP_COND_EXC_OV:
5038                 case OP_COND_EXC_NO:
5039                 case OP_COND_EXC_C:
5040                 case OP_COND_EXC_NC:
5041                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5042                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5043                         break;
5044                 case OP_COND_EXC_IOV:
5045                 case OP_COND_EXC_INO:
5046                 case OP_COND_EXC_IC:
5047                 case OP_COND_EXC_INC:
5048                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5049                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5050                         break;
5051
5052                 /* floating point opcodes */
5053                 case OP_R8CONST: {
5054                         double d = *(double *)ins->inst_p0;
5055
5056                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5057                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5058                         }
5059                         else {
5060                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5061                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5062                         }
5063                         break;
5064                 }
5065                 case OP_R4CONST: {
5066                         float f = *(float *)ins->inst_p0;
5067
5068                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5069                                 if (cfg->r4fp)
5070                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5071                                 else
5072                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5073                         }
5074                         else {
5075                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5076                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5077                                 if (!cfg->r4fp)
5078                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5079                         }
5080                         break;
5081                 }
5082                 case OP_STORER8_MEMBASE_REG:
5083                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5084                         break;
5085                 case OP_LOADR8_MEMBASE:
5086                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5087                         break;
5088                 case OP_STORER4_MEMBASE_REG:
5089                         if (cfg->r4fp) {
5090                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5091                         } else {
5092                                 /* This requires a double->single conversion */
5093                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5094                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5095                         }
5096                         break;
5097                 case OP_LOADR4_MEMBASE:
5098                         if (cfg->r4fp) {
5099                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5100                         } else {
5101                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5102                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5103                         }
5104                         break;
5105                 case OP_ICONV_TO_R4:
5106                         if (cfg->r4fp) {
5107                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5108                         } else {
5109                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5110                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5111                         }
5112                         break;
5113                 case OP_ICONV_TO_R8:
5114                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5115                         break;
5116                 case OP_LCONV_TO_R4:
5117                         if (cfg->r4fp) {
5118                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5119                         } else {
5120                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5121                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5122                         }
5123                         break;
5124                 case OP_LCONV_TO_R8:
5125                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5126                         break;
5127                 case OP_FCONV_TO_R4:
5128                         if (cfg->r4fp) {
5129                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5130                         } else {
5131                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5132                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5133                         }
5134                         break;
5135                 case OP_FCONV_TO_I1:
5136                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5137                         break;
5138                 case OP_FCONV_TO_U1:
5139                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5140                         break;
5141                 case OP_FCONV_TO_I2:
5142                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5143                         break;
5144                 case OP_FCONV_TO_U2:
5145                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5146                         break;
5147                 case OP_FCONV_TO_U4:
5148                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5149                         break;
5150                 case OP_FCONV_TO_I4:
5151                 case OP_FCONV_TO_I:
5152                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5153                         break;
5154                 case OP_FCONV_TO_I8:
5155                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5156                         break;
5157
5158                 case OP_RCONV_TO_I1:
5159                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5160                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5161                         break;
5162                 case OP_RCONV_TO_U1:
5163                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5164                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5165                         break;
5166                 case OP_RCONV_TO_I2:
5167                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5168                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5169                         break;
5170                 case OP_RCONV_TO_U2:
5171                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5172                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5173                         break;
5174                 case OP_RCONV_TO_I4:
5175                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5176                         break;
5177                 case OP_RCONV_TO_U4:
5178                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5179                         break;
5180                 case OP_RCONV_TO_I8:
5181                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5182                         break;
5183                 case OP_RCONV_TO_R8:
5184                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5185                         break;
5186                 case OP_RCONV_TO_R4:
5187                         if (ins->dreg != ins->sreg1)
5188                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5189                         break;
5190
5191                 case OP_LCONV_TO_R_UN: {
5192                         guint8 *br [2];
5193
5194                         /* Based on gcc code */
5195                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5196                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5197
5198                         /* Positive case */
5199                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5200                         br [1] = code; x86_jump8 (code, 0);
5201                         amd64_patch (br [0], code);
5202
5203                         /* Negative case */
5204                         /* Save to the red zone */
5205                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5206                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5207                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5208                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5209                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5210                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5211                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5212                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5213                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5214                         /* Restore */
5215                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5216                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5217                         amd64_patch (br [1], code);
5218                         break;
5219                 }
5220                 case OP_LCONV_TO_OVF_U4:
5221                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5222                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5223                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5224                         break;
5225                 case OP_LCONV_TO_OVF_I4_UN:
5226                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5227                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5228                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5229                         break;
5230                 case OP_FMOVE:
5231                         if (ins->dreg != ins->sreg1)
5232                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5233                         break;
5234                 case OP_RMOVE:
5235                         if (ins->dreg != ins->sreg1)
5236                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5237                         break;
5238                 case OP_MOVE_F_TO_I4:
5239                         if (cfg->r4fp) {
5240                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5241                         } else {
5242                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5243                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5244                         }
5245                         break;
5246                 case OP_MOVE_I4_TO_F:
5247                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5248                         if (!cfg->r4fp)
5249                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5250                         break;
5251                 case OP_MOVE_F_TO_I8:
5252                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5253                         break;
5254                 case OP_MOVE_I8_TO_F:
5255                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5256                         break;
5257                 case OP_FADD:
5258                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5259                         break;
5260                 case OP_FSUB:
5261                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5262                         break;
5263                 case OP_FMUL:
5264                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5265                         break;
5266                 case OP_FDIV:
5267                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5268                         break;
5269                 case OP_FNEG: {
5270                         static double r8_0 = -0.0;
5271
5272                         g_assert (ins->sreg1 == ins->dreg);
5273
5274                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5275                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5276                         break;
5277                 }
5278                 case OP_SIN:
5279                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5280                         break;
5281                 case OP_COS:
5282                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5283                         break;
5284                 case OP_ABS: {
5285                         static guint64 d = 0x7fffffffffffffffUL;
5286
5287                         g_assert (ins->sreg1 == ins->dreg);
5288
5289                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5290                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5291                         break;
5292                 }
5293                 case OP_SQRT:
5294                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5295                         break;
5296
5297                 case OP_RADD:
5298                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5299                         break;
5300                 case OP_RSUB:
5301                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5302                         break;
5303                 case OP_RMUL:
5304                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5305                         break;
5306                 case OP_RDIV:
5307                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5308                         break;
5309                 case OP_RNEG: {
5310                         static float r4_0 = -0.0;
5311
5312                         g_assert (ins->sreg1 == ins->dreg);
5313
5314                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5315                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5316                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5317                         break;
5318                 }
5319
5320                 case OP_IMIN:
5321                         g_assert (cfg->opt & MONO_OPT_CMOV);
5322                         g_assert (ins->dreg == ins->sreg1);
5323                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5324                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5325                         break;
5326                 case OP_IMIN_UN:
5327                         g_assert (cfg->opt & MONO_OPT_CMOV);
5328                         g_assert (ins->dreg == ins->sreg1);
5329                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5330                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5331                         break;
5332                 case OP_IMAX:
5333                         g_assert (cfg->opt & MONO_OPT_CMOV);
5334                         g_assert (ins->dreg == ins->sreg1);
5335                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5336                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5337                         break;
5338                 case OP_IMAX_UN:
5339                         g_assert (cfg->opt & MONO_OPT_CMOV);
5340                         g_assert (ins->dreg == ins->sreg1);
5341                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5342                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5343                         break;
5344                 case OP_LMIN:
5345                         g_assert (cfg->opt & MONO_OPT_CMOV);
5346                         g_assert (ins->dreg == ins->sreg1);
5347                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5348                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5349                         break;
5350                 case OP_LMIN_UN:
5351                         g_assert (cfg->opt & MONO_OPT_CMOV);
5352                         g_assert (ins->dreg == ins->sreg1);
5353                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5354                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5355                         break;
5356                 case OP_LMAX:
5357                         g_assert (cfg->opt & MONO_OPT_CMOV);
5358                         g_assert (ins->dreg == ins->sreg1);
5359                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5360                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5361                         break;
5362                 case OP_LMAX_UN:
5363                         g_assert (cfg->opt & MONO_OPT_CMOV);
5364                         g_assert (ins->dreg == ins->sreg1);
5365                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5366                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5367                         break;
5368                 case OP_X86_FPOP:
5369                         break;
5370                 case OP_FCOMPARE:
5371                         /*
5372                          * The two arguments are swapped because the fbranch instructions
5373                          * depend on this for the non-sse case to work.
5374                          */
5375                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5376                         break;
5377                 case OP_RCOMPARE:
5378                         /*
5379                          * FIXME: Get rid of this.
5380                          * The two arguments are swapped because the fbranch instructions
5381                          * depend on this for the non-sse case to work.
5382                          */
5383                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5384                         break;
5385                 case OP_FCNEQ:
5386                 case OP_FCEQ: {
5387                         /* zeroing the register at the start results in
5388                          * shorter and faster code (we can also remove the widening op)
5389                          */
5390                         guchar *unordered_check;
5391
5392                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5393                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5394                         unordered_check = code;
5395                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5396
5397                         if (ins->opcode == OP_FCEQ) {
5398                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5399                                 amd64_patch (unordered_check, code);
5400                         } else {
5401                                 guchar *jump_to_end;
5402                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5403                                 jump_to_end = code;
5404                                 x86_jump8 (code, 0);
5405                                 amd64_patch (unordered_check, code);
5406                                 amd64_inc_reg (code, ins->dreg);
5407                                 amd64_patch (jump_to_end, code);
5408                         }
5409                         break;
5410                 }
5411                 case OP_FCLT:
5412                 case OP_FCLT_UN: {
5413                         /* zeroing the register at the start results in
5414                          * shorter and faster code (we can also remove the widening op)
5415                          */
5416                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5417                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5418                         if (ins->opcode == OP_FCLT_UN) {
5419                                 guchar *unordered_check = code;
5420                                 guchar *jump_to_end;
5421                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5422                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5423                                 jump_to_end = code;
5424                                 x86_jump8 (code, 0);
5425                                 amd64_patch (unordered_check, code);
5426                                 amd64_inc_reg (code, ins->dreg);
5427                                 amd64_patch (jump_to_end, code);
5428                         } else {
5429                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5430                         }
5431                         break;
5432                 }
5433                 case OP_FCLE: {
5434                         guchar *unordered_check;
5435                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5436                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5437                         unordered_check = code;
5438                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5439                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5440                         amd64_patch (unordered_check, code);
5441                         break;
5442                 }
5443                 case OP_FCGT:
5444                 case OP_FCGT_UN: {
5445                         /* zeroing the register at the start results in
5446                          * shorter and faster code (we can also remove the widening op)
5447                          */
5448                         guchar *unordered_check;
5449
5450                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5451                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5452                         if (ins->opcode == OP_FCGT) {
5453                                 unordered_check = code;
5454                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5455                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5456                                 amd64_patch (unordered_check, code);
5457                         } else {
5458                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5459                         }
5460                         break;
5461                 }
5462                 case OP_FCGE: {
5463                         guchar *unordered_check;
5464                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5465                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5466                         unordered_check = code;
5467                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5468                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5469                         amd64_patch (unordered_check, code);
5470                         break;
5471                 }
5472
5473                 case OP_RCEQ:
5474                 case OP_RCGT:
5475                 case OP_RCLT:
5476                 case OP_RCLT_UN:
5477                 case OP_RCGT_UN: {
5478                         int x86_cond;
5479                         gboolean unordered = FALSE;
5480
5481                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5482                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5483
5484                         switch (ins->opcode) {
5485                         case OP_RCEQ:
5486                                 x86_cond = X86_CC_EQ;
5487                                 break;
5488                         case OP_RCGT:
5489                                 x86_cond = X86_CC_LT;
5490                                 break;
5491                         case OP_RCLT:
5492                                 x86_cond = X86_CC_GT;
5493                                 break;
5494                         case OP_RCLT_UN:
5495                                 x86_cond = X86_CC_GT;
5496                                 unordered = TRUE;
5497                                 break;
5498                         case OP_RCGT_UN:
5499                                 x86_cond = X86_CC_LT;
5500                                 unordered = TRUE;
5501                                 break;
5502                         default:
5503                                 g_assert_not_reached ();
5504                                 break;
5505                         }
5506
5507                         if (unordered) {
5508                                 guchar *unordered_check;
5509                                 guchar *jump_to_end;
5510
5511                                 unordered_check = code;
5512                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5513                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5514                                 jump_to_end = code;
5515                                 x86_jump8 (code, 0);
5516                                 amd64_patch (unordered_check, code);
5517                                 amd64_inc_reg (code, ins->dreg);
5518                                 amd64_patch (jump_to_end, code);
5519                         } else {
5520                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5521                         }
5522                         break;
5523                 }
5524                 case OP_FCLT_MEMBASE:
5525                 case OP_FCGT_MEMBASE:
5526                 case OP_FCLT_UN_MEMBASE:
5527                 case OP_FCGT_UN_MEMBASE:
5528                 case OP_FCEQ_MEMBASE: {
5529                         guchar *unordered_check, *jump_to_end;
5530                         int x86_cond;
5531
5532                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5533                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5534
5535                         switch (ins->opcode) {
5536                         case OP_FCEQ_MEMBASE:
5537                                 x86_cond = X86_CC_EQ;
5538                                 break;
5539                         case OP_FCLT_MEMBASE:
5540                         case OP_FCLT_UN_MEMBASE:
5541                                 x86_cond = X86_CC_LT;
5542                                 break;
5543                         case OP_FCGT_MEMBASE:
5544                         case OP_FCGT_UN_MEMBASE:
5545                                 x86_cond = X86_CC_GT;
5546                                 break;
5547                         default:
5548                                 g_assert_not_reached ();
5549                         }
5550
5551                         unordered_check = code;
5552                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5553                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5554
5555                         switch (ins->opcode) {
5556                         case OP_FCEQ_MEMBASE:
5557                         case OP_FCLT_MEMBASE:
5558                         case OP_FCGT_MEMBASE:
5559                                 amd64_patch (unordered_check, code);
5560                                 break;
5561                         case OP_FCLT_UN_MEMBASE:
5562                         case OP_FCGT_UN_MEMBASE:
5563                                 jump_to_end = code;
5564                                 x86_jump8 (code, 0);
5565                                 amd64_patch (unordered_check, code);
5566                                 amd64_inc_reg (code, ins->dreg);
5567                                 amd64_patch (jump_to_end, code);
5568                                 break;
5569                         default:
5570                                 break;
5571                         }
5572                         break;
5573                 }
5574                 case OP_FBEQ: {
5575                         guchar *jump = code;
5576                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5577                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5578                         amd64_patch (jump, code);
5579                         break;
5580                 }
5581                 case OP_FBNE_UN:
5582                         /* Branch if C013 != 100 */
5583                         /* branch if !ZF or (PF|CF) */
5584                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5585                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5586                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5587                         break;
5588                 case OP_FBLT:
5589                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5590                         break;
5591                 case OP_FBLT_UN:
5592                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5593                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5594                         break;
5595                 case OP_FBGT:
5596                 case OP_FBGT_UN:
5597                         if (ins->opcode == OP_FBGT) {
5598                                 guchar *br1;
5599
5600                                 /* skip branch if C1=1 */
5601                                 br1 = code;
5602                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5603                                 /* branch if (C0 | C3) = 1 */
5604                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5605                                 amd64_patch (br1, code);
5606                                 break;
5607                         } else {
5608                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5609                         }
5610                         break;
5611                 case OP_FBGE: {
5612                         /* Branch if C013 == 100 or 001 */
5613                         guchar *br1;
5614
5615                         /* skip branch if C1=1 */
5616                         br1 = code;
5617                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5618                         /* branch if (C0 | C3) = 1 */
5619                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5620                         amd64_patch (br1, code);
5621                         break;
5622                 }
5623                 case OP_FBGE_UN:
5624                         /* Branch if C013 == 000 */
5625                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5626                         break;
5627                 case OP_FBLE: {
5628                         /* Branch if C013=000 or 100 */
5629                         guchar *br1;
5630
5631                         /* skip branch if C1=1 */
5632                         br1 = code;
5633                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5634                         /* branch if C0=0 */
5635                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5636                         amd64_patch (br1, code);
5637                         break;
5638                 }
5639                 case OP_FBLE_UN:
5640                         /* Branch if C013 != 001 */
5641                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5642                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5643                         break;
5644                 case OP_CKFINITE:
5645                         /* Transfer value to the fp stack */
5646                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5647                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5648                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5649
5650                         amd64_push_reg (code, AMD64_RAX);
5651                         amd64_fxam (code);
5652                         amd64_fnstsw (code);
5653                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5654                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5655                         amd64_pop_reg (code, AMD64_RAX);
5656                         amd64_fstp (code, 0);
5657                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5658                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5659                         break;
5660                 case OP_TLS_GET: {
5661                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5662                         break;
5663                 }
5664                 case OP_TLS_GET_REG:
5665                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5666                         break;
5667                 case OP_TLS_SET: {
5668                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5669                         break;
5670                 }
5671                 case OP_TLS_SET_REG: {
5672                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5673                         break;
5674                 }
5675                 case OP_MEMORY_BARRIER: {
5676                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5677                                 x86_mfence (code);
5678                         break;
5679                 }
5680                 case OP_ATOMIC_ADD_I4:
5681                 case OP_ATOMIC_ADD_I8: {
5682                         int dreg = ins->dreg;
5683                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5684
5685                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5686                                 dreg = AMD64_R11;
5687
5688                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5689                         amd64_prefix (code, X86_LOCK_PREFIX);
5690                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5691                         /* dreg contains the old value, add with sreg2 value */
5692                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5693
5694                         if (ins->dreg != dreg)
5695                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5696
5697                         break;
5698                 }
5699                 case OP_ATOMIC_EXCHANGE_I4:
5700                 case OP_ATOMIC_EXCHANGE_I8: {
5701                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5702
5703                         /* LOCK prefix is implied. */
5704                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5705                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5706                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5707                         break;
5708                 }
5709                 case OP_ATOMIC_CAS_I4:
5710                 case OP_ATOMIC_CAS_I8: {
5711                         guint32 size;
5712
5713                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5714                                 size = 8;
5715                         else
5716                                 size = 4;
5717
5718                         /*
5719                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5720                          * an explanation of how this works.
5721                          */
5722                         g_assert (ins->sreg3 == AMD64_RAX);
5723                         g_assert (ins->sreg1 != AMD64_RAX);
5724                         g_assert (ins->sreg1 != ins->sreg2);
5725
5726                         amd64_prefix (code, X86_LOCK_PREFIX);
5727                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5728
5729                         if (ins->dreg != AMD64_RAX)
5730                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5731                         break;
5732                 }
5733                 case OP_ATOMIC_LOAD_I1: {
5734                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5735                         break;
5736                 }
5737                 case OP_ATOMIC_LOAD_U1: {
5738                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5739                         break;
5740                 }
5741                 case OP_ATOMIC_LOAD_I2: {
5742                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5743                         break;
5744                 }
5745                 case OP_ATOMIC_LOAD_U2: {
5746                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5747                         break;
5748                 }
5749                 case OP_ATOMIC_LOAD_I4: {
5750                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5751                         break;
5752                 }
5753                 case OP_ATOMIC_LOAD_U4:
5754                 case OP_ATOMIC_LOAD_I8:
5755                 case OP_ATOMIC_LOAD_U8: {
5756                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5757                         break;
5758                 }
5759                 case OP_ATOMIC_LOAD_R4: {
5760                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5761                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5762                         break;
5763                 }
5764                 case OP_ATOMIC_LOAD_R8: {
5765                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5766                         break;
5767                 }
5768                 case OP_ATOMIC_STORE_I1:
5769                 case OP_ATOMIC_STORE_U1:
5770                 case OP_ATOMIC_STORE_I2:
5771                 case OP_ATOMIC_STORE_U2:
5772                 case OP_ATOMIC_STORE_I4:
5773                 case OP_ATOMIC_STORE_U4:
5774                 case OP_ATOMIC_STORE_I8:
5775                 case OP_ATOMIC_STORE_U8: {
5776                         int size;
5777
5778                         switch (ins->opcode) {
5779                         case OP_ATOMIC_STORE_I1:
5780                         case OP_ATOMIC_STORE_U1:
5781                                 size = 1;
5782                                 break;
5783                         case OP_ATOMIC_STORE_I2:
5784                         case OP_ATOMIC_STORE_U2:
5785                                 size = 2;
5786                                 break;
5787                         case OP_ATOMIC_STORE_I4:
5788                         case OP_ATOMIC_STORE_U4:
5789                                 size = 4;
5790                                 break;
5791                         case OP_ATOMIC_STORE_I8:
5792                         case OP_ATOMIC_STORE_U8:
5793                                 size = 8;
5794                                 break;
5795                         }
5796
5797                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5798
5799                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5800                                 x86_mfence (code);
5801                         break;
5802                 }
5803                 case OP_ATOMIC_STORE_R4: {
5804                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5805                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5806
5807                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5808                                 x86_mfence (code);
5809                         break;
5810                 }
5811                 case OP_ATOMIC_STORE_R8: {
5812                         x86_nop (code);
5813                         x86_nop (code);
5814                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5815                         x86_nop (code);
5816                         x86_nop (code);
5817
5818                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5819                                 x86_mfence (code);
5820                         break;
5821                 }
5822                 case OP_CARD_TABLE_WBARRIER: {
5823                         int ptr = ins->sreg1;
5824                         int value = ins->sreg2;
5825                         guchar *br = 0;
5826                         int nursery_shift, card_table_shift;
5827                         gpointer card_table_mask;
5828                         size_t nursery_size;
5829
5830                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5831                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5832                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5833
5834                         /*If either point to the stack we can simply avoid the WB. This happens due to
5835                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5836                          */
5837                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5838                                 continue;
5839
5840                         /*
5841                          * We need one register we can clobber, we choose EDX and make sreg1
5842                          * fixed EAX to work around limitations in the local register allocator.
5843                          * sreg2 might get allocated to EDX, but that is not a problem since
5844                          * we use it before clobbering EDX.
5845                          */
5846                         g_assert (ins->sreg1 == AMD64_RAX);
5847
5848                         /*
5849                          * This is the code we produce:
5850                          *
5851                          *   edx = value
5852                          *   edx >>= nursery_shift
5853                          *   cmp edx, (nursery_start >> nursery_shift)
5854                          *   jne done
5855                          *   edx = ptr
5856                          *   edx >>= card_table_shift
5857                          *   edx += cardtable
5858                          *   [edx] = 1
5859                          * done:
5860                          */
5861
5862                         if (mono_gc_card_table_nursery_check ()) {
5863                                 if (value != AMD64_RDX)
5864                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5865                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5866                                 if (shifted_nursery_start >> 31) {
5867                                         /*
5868                                          * The value we need to compare against is 64 bits, so we need
5869                                          * another spare register.  We use RBX, which we save and
5870                                          * restore.
5871                                          */
5872                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5873                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5874                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5875                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5876                                 } else {
5877                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5878                                 }
5879                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5880                         }
5881                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5882                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5883                         if (card_table_mask)
5884                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5885
5886                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5887                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5888
5889                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5890
5891                         if (mono_gc_card_table_nursery_check ())
5892                                 x86_patch (br, code);
5893                         break;
5894                 }
5895 #ifdef MONO_ARCH_SIMD_INTRINSICS
5896                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5897                 case OP_ADDPS:
5898                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5899                         break;
5900                 case OP_DIVPS:
5901                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5902                         break;
5903                 case OP_MULPS:
5904                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5905                         break;
5906                 case OP_SUBPS:
5907                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5908                         break;
5909                 case OP_MAXPS:
5910                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5911                         break;
5912                 case OP_MINPS:
5913                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5914                         break;
5915                 case OP_COMPPS:
5916                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5917                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5918                         break;
5919                 case OP_ANDPS:
5920                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5921                         break;
5922                 case OP_ANDNPS:
5923                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5924                         break;
5925                 case OP_ORPS:
5926                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5927                         break;
5928                 case OP_XORPS:
5929                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5930                         break;
5931                 case OP_SQRTPS:
5932                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5933                         break;
5934                 case OP_RSQRTPS:
5935                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5936                         break;
5937                 case OP_RCPPS:
5938                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5939                         break;
5940                 case OP_ADDSUBPS:
5941                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5942                         break;
5943                 case OP_HADDPS:
5944                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5945                         break;
5946                 case OP_HSUBPS:
5947                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5948                         break;
5949                 case OP_DUPPS_HIGH:
5950                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5951                         break;
5952                 case OP_DUPPS_LOW:
5953                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5954                         break;
5955
5956                 case OP_PSHUFLEW_HIGH:
5957                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5958                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5959                         break;
5960                 case OP_PSHUFLEW_LOW:
5961                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5962                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5963                         break;
5964                 case OP_PSHUFLED:
5965                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5966                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5967                         break;
5968                 case OP_SHUFPS:
5969                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5970                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5971                         break;
5972                 case OP_SHUFPD:
5973                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5974                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5975                         break;
5976
5977                 case OP_ADDPD:
5978                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5979                         break;
5980                 case OP_DIVPD:
5981                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5982                         break;
5983                 case OP_MULPD:
5984                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5985                         break;
5986                 case OP_SUBPD:
5987                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5988                         break;
5989                 case OP_MAXPD:
5990                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992                 case OP_MINPD:
5993                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995                 case OP_COMPPD:
5996                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5997                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5998                         break;
5999                 case OP_ANDPD:
6000                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_ANDNPD:
6003                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005                 case OP_ORPD:
6006                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6007                         break;
6008                 case OP_XORPD:
6009                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011                 case OP_SQRTPD:
6012                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6013                         break;
6014                 case OP_ADDSUBPD:
6015                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017                 case OP_HADDPD:
6018                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6019                         break;
6020                 case OP_HSUBPD:
6021                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6022                         break;
6023                 case OP_DUPPD:
6024                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6025                         break;
6026
6027                 case OP_EXTRACT_MASK:
6028                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6029                         break;
6030
6031                 case OP_PAND:
6032                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_POR:
6035                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_PXOR:
6038                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040
6041                 case OP_PADDB:
6042                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044                 case OP_PADDW:
6045                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047                 case OP_PADDD:
6048                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6049                         break;
6050                 case OP_PADDQ:
6051                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6052                         break;
6053
6054                 case OP_PSUBB:
6055                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_PSUBW:
6058                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060                 case OP_PSUBD:
6061                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063                 case OP_PSUBQ:
6064                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6065                         break;
6066
6067                 case OP_PMAXB_UN:
6068                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_PMAXW_UN:
6071                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_PMAXD_UN:
6074                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076
6077                 case OP_PMAXB:
6078                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080                 case OP_PMAXW:
6081                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083                 case OP_PMAXD:
6084                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6085                         break;
6086
6087                 case OP_PAVGB_UN:
6088                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6089                         break;
6090                 case OP_PAVGW_UN:
6091                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093
6094                 case OP_PMINB_UN:
6095                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6096                         break;
6097                 case OP_PMINW_UN:
6098                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6099                         break;
6100                 case OP_PMIND_UN:
6101                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6102                         break;
6103
6104                 case OP_PMINB:
6105                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6106                         break;
6107                 case OP_PMINW:
6108                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6109                         break;
6110                 case OP_PMIND:
6111                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6112                         break;
6113
6114                 case OP_PCMPEQB:
6115                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6116                         break;
6117                 case OP_PCMPEQW:
6118                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6119                         break;
6120                 case OP_PCMPEQD:
6121                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6122                         break;
6123                 case OP_PCMPEQQ:
6124                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6125                         break;
6126
6127                 case OP_PCMPGTB:
6128                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6129                         break;
6130                 case OP_PCMPGTW:
6131                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6132                         break;
6133                 case OP_PCMPGTD:
6134                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6135                         break;
6136                 case OP_PCMPGTQ:
6137                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6138                         break;
6139
6140                 case OP_PSUM_ABS_DIFF:
6141                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6142                         break;
6143
6144                 case OP_UNPACK_LOWB:
6145                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6146                         break;
6147                 case OP_UNPACK_LOWW:
6148                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6149                         break;
6150                 case OP_UNPACK_LOWD:
6151                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6152                         break;
6153                 case OP_UNPACK_LOWQ:
6154                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6155                         break;
6156                 case OP_UNPACK_LOWPS:
6157                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6158                         break;
6159                 case OP_UNPACK_LOWPD:
6160                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6161                         break;
6162
6163                 case OP_UNPACK_HIGHB:
6164                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6165                         break;
6166                 case OP_UNPACK_HIGHW:
6167                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6168                         break;
6169                 case OP_UNPACK_HIGHD:
6170                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6171                         break;
6172                 case OP_UNPACK_HIGHQ:
6173                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6174                         break;
6175                 case OP_UNPACK_HIGHPS:
6176                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6177                         break;
6178                 case OP_UNPACK_HIGHPD:
6179                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6180                         break;
6181
6182                 case OP_PACKW:
6183                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6184                         break;
6185                 case OP_PACKD:
6186                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6187                         break;
6188                 case OP_PACKW_UN:
6189                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6190                         break;
6191                 case OP_PACKD_UN:
6192                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194
6195                 case OP_PADDB_SAT_UN:
6196                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6197                         break;
6198                 case OP_PSUBB_SAT_UN:
6199                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6200                         break;
6201                 case OP_PADDW_SAT_UN:
6202                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6203                         break;
6204                 case OP_PSUBW_SAT_UN:
6205                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6206                         break;
6207
6208                 case OP_PADDB_SAT:
6209                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6210                         break;
6211                 case OP_PSUBB_SAT:
6212                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6213                         break;
6214                 case OP_PADDW_SAT:
6215                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6216                         break;
6217                 case OP_PSUBW_SAT:
6218                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6219                         break;
6220
6221                 case OP_PMULW:
6222                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6223                         break;
6224                 case OP_PMULD:
6225                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6226                         break;
6227                 case OP_PMULQ:
6228                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6229                         break;
6230                 case OP_PMULW_HIGH_UN:
6231                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6232                         break;
6233                 case OP_PMULW_HIGH:
6234                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6235                         break;
6236
6237                 case OP_PSHRW:
6238                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6239                         break;
6240                 case OP_PSHRW_REG:
6241                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6242                         break;
6243
6244                 case OP_PSARW:
6245                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6246                         break;
6247                 case OP_PSARW_REG:
6248                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6249                         break;
6250
6251                 case OP_PSHLW:
6252                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6253                         break;
6254                 case OP_PSHLW_REG:
6255                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6256                         break;
6257
6258                 case OP_PSHRD:
6259                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6260                         break;
6261                 case OP_PSHRD_REG:
6262                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6263                         break;
6264
6265                 case OP_PSARD:
6266                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6267                         break;
6268                 case OP_PSARD_REG:
6269                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6270                         break;
6271
6272                 case OP_PSHLD:
6273                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6274                         break;
6275                 case OP_PSHLD_REG:
6276                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6277                         break;
6278
6279                 case OP_PSHRQ:
6280                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6281                         break;
6282                 case OP_PSHRQ_REG:
6283                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6284                         break;
6285
6286                 /*TODO: This is appart of the sse spec but not added
6287                 case OP_PSARQ:
6288                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6289                         break;
6290                 case OP_PSARQ_REG:
6291                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6292                         break;
6293                 */
6294
6295                 case OP_PSHLQ:
6296                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6297                         break;
6298                 case OP_PSHLQ_REG:
6299                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6300                         break;
6301                 case OP_CVTDQ2PD:
6302                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6303                         break;
6304                 case OP_CVTDQ2PS:
6305                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6306                         break;
6307                 case OP_CVTPD2DQ:
6308                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6309                         break;
6310                 case OP_CVTPD2PS:
6311                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6312                         break;
6313                 case OP_CVTPS2DQ:
6314                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6315                         break;
6316                 case OP_CVTPS2PD:
6317                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6318                         break;
6319                 case OP_CVTTPD2DQ:
6320                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6321                         break;
6322                 case OP_CVTTPS2DQ:
6323                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6324                         break;
6325
6326                 case OP_ICONV_TO_X:
6327                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6328                         break;
6329                 case OP_EXTRACT_I4:
6330                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6331                         break;
6332                 case OP_EXTRACT_I8:
6333                         if (ins->inst_c0) {
6334                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6335                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6336                         } else {
6337                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6338                         }
6339                         break;
6340                 case OP_EXTRACT_I1:
6341                 case OP_EXTRACT_U1:
6342                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6343                         if (ins->inst_c0)
6344                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6345                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6346                         break;
6347                 case OP_EXTRACT_I2:
6348                 case OP_EXTRACT_U2:
6349                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6350                         if (ins->inst_c0)
6351                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6352                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6353                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6354                         break;
6355                 case OP_EXTRACT_R8:
6356                         if (ins->inst_c0)
6357                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6358                         else
6359                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6360                         break;
6361                 case OP_INSERT_I2:
6362                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6363                         break;
6364                 case OP_EXTRACTX_U2:
6365                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6366                         break;
6367                 case OP_INSERTX_U1_SLOW:
6368                         /*sreg1 is the extracted ireg (scratch)
6369                         /sreg2 is the to be inserted ireg (scratch)
6370                         /dreg is the xreg to receive the value*/
6371
6372                         /*clear the bits from the extracted word*/
6373                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6374                         /*shift the value to insert if needed*/
6375                         if (ins->inst_c0 & 1)
6376                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6377                         /*join them together*/
6378                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6379                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6380                         break;
6381                 case OP_INSERTX_I4_SLOW:
6382                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6383                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6384                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6385                         break;
6386                 case OP_INSERTX_I8_SLOW:
6387                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6388                         if (ins->inst_c0)
6389                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6390                         else
6391                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6392                         break;
6393
6394                 case OP_INSERTX_R4_SLOW:
6395                         switch (ins->inst_c0) {
6396                         case 0:
6397                                 if (cfg->r4fp)
6398                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6399                                 else
6400                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6401                                 break;
6402                         case 1:
6403                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6404                                 if (cfg->r4fp)
6405                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6406                                 else
6407                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6408                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6409                                 break;
6410                         case 2:
6411                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6412                                 if (cfg->r4fp)
6413                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6414                                 else
6415                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6416                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6417                                 break;
6418                         case 3:
6419                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6420                                 if (cfg->r4fp)
6421                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6422                                 else
6423                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6424                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6425                                 break;
6426                         }
6427                         break;
6428                 case OP_INSERTX_R8_SLOW:
6429                         if (ins->inst_c0)
6430                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6431                         else
6432                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6433                         break;
6434                 case OP_STOREX_MEMBASE_REG:
6435                 case OP_STOREX_MEMBASE:
6436                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6437                         break;
6438                 case OP_LOADX_MEMBASE:
6439                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6440                         break;
6441                 case OP_LOADX_ALIGNED_MEMBASE:
6442                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6443                         break;
6444                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6445                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6446                         break;
6447                 case OP_STOREX_NTA_MEMBASE_REG:
6448                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6449                         break;
6450                 case OP_PREFETCH_MEMBASE:
6451                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6452                         break;
6453
6454                 case OP_XMOVE:
6455                         /*FIXME the peephole pass should have killed this*/
6456                         if (ins->dreg != ins->sreg1)
6457                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6458                         break;
6459                 case OP_XZERO:
6460                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6461                         break;
6462                 case OP_ICONV_TO_R4_RAW:
6463                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6464                         break;
6465
6466                 case OP_FCONV_TO_R8_X:
6467                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6468                         break;
6469
6470                 case OP_XCONV_R8_TO_I4:
6471                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6472                         switch (ins->backend.source_opcode) {
6473                         case OP_FCONV_TO_I1:
6474                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6475                                 break;
6476                         case OP_FCONV_TO_U1:
6477                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6478                                 break;
6479                         case OP_FCONV_TO_I2:
6480                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6481                                 break;
6482                         case OP_FCONV_TO_U2:
6483                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6484                                 break;
6485                         }
6486                         break;
6487
6488                 case OP_EXPAND_I2:
6489                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6490                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6491                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6492                         break;
6493                 case OP_EXPAND_I4:
6494                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6495                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6496                         break;
6497                 case OP_EXPAND_I8:
6498                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6499                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6500                         break;
6501                 case OP_EXPAND_R4:
6502                         if (cfg->r4fp) {
6503                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6504                         } else {
6505                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6506                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6507                         }
6508                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6509                         break;
6510                 case OP_EXPAND_R8:
6511                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6512                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6513                         break;
6514 #endif
6515                 case OP_LIVERANGE_START: {
6516                         if (cfg->verbose_level > 1)
6517                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6518                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6519                         break;
6520                 }
6521                 case OP_LIVERANGE_END: {
6522                         if (cfg->verbose_level > 1)
6523                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6524                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6525                         break;
6526                 }
6527                 case OP_GC_SAFE_POINT: {
6528                         const char *polling_func = NULL;
6529                         int compare_val = 0;
6530                         guint8 *br [1];
6531
6532 #if defined (USE_COOP_GC)
6533                         polling_func = "mono_threads_state_poll";
6534                         compare_val = 1;
6535 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6536                         polling_func = "mono_nacl_gc";
6537                         compare_val = 0xFFFFFFFF;
6538 #endif
6539                         if (!polling_func)
6540                                 break;
6541
6542                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6543                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6544                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6545                         amd64_patch (br[0], code);
6546                         break;
6547                 }
6548
6549                 case OP_GC_LIVENESS_DEF:
6550                 case OP_GC_LIVENESS_USE:
6551                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6552                         ins->backend.pc_offset = code - cfg->native_code;
6553                         break;
6554                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6555                         ins->backend.pc_offset = code - cfg->native_code;
6556                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6557                         break;
6558                 default:
6559                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6560                         g_assert_not_reached ();
6561                 }
6562
6563                 if ((code - cfg->native_code - offset) > max_len) {
6564 #if !defined(__native_client_codegen__)
6565                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6566                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6567                         g_assert_not_reached ();
6568 #endif
6569                 }
6570         }
6571
6572         cfg->code_len = code - cfg->native_code;
6573 }
6574
6575 #endif /* DISABLE_JIT */
6576
6577 void
6578 mono_arch_register_lowlevel_calls (void)
6579 {
6580         /* The signature doesn't matter */
6581         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6582 }
6583
6584 void
6585 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6586 {
6587         unsigned char *ip = ji->ip.i + code;
6588
6589         /*
6590          * Debug code to help track down problems where the target of a near call is
6591          * is not valid.
6592          */
6593         if (amd64_is_near_call (ip)) {
6594                 gint64 disp = (guint8*)target - (guint8*)ip;
6595
6596                 if (!amd64_is_imm32 (disp)) {
6597                         printf ("TYPE: %d\n", ji->type);
6598                         switch (ji->type) {
6599                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6600                                 printf ("V: %s\n", ji->data.name);
6601                                 break;
6602                         case MONO_PATCH_INFO_METHOD_JUMP:
6603                         case MONO_PATCH_INFO_METHOD:
6604                                 printf ("V: %s\n", ji->data.method->name);
6605                                 break;
6606                         default:
6607                                 break;
6608                         }
6609                 }
6610         }
6611
6612         amd64_patch (ip, (gpointer)target);
6613 }
6614
6615 #ifndef DISABLE_JIT
6616
6617 static int
6618 get_max_epilog_size (MonoCompile *cfg)
6619 {
6620         int max_epilog_size = 16;
6621
6622         if (cfg->method->save_lmf)
6623                 max_epilog_size += 256;
6624
6625         if (mono_jit_trace_calls != NULL)
6626                 max_epilog_size += 50;
6627
6628         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6629                 max_epilog_size += 50;
6630
6631         max_epilog_size += (AMD64_NREG * 2);
6632
6633         return max_epilog_size;
6634 }
6635
6636 /*
6637  * This macro is used for testing whenever the unwinder works correctly at every point
6638  * where an async exception can happen.
6639  */
6640 /* This will generate a SIGSEGV at the given point in the code */
6641 #define async_exc_point(code) do { \
6642     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6643          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6644              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6645          cfg->arch.async_point_count ++; \
6646     } \
6647 } while (0)
6648
6649 guint8 *
6650 mono_arch_emit_prolog (MonoCompile *cfg)
6651 {
6652         MonoMethod *method = cfg->method;
6653         MonoBasicBlock *bb;
6654         MonoMethodSignature *sig;
6655         MonoInst *ins;
6656         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6657         guint8 *code;
6658         CallInfo *cinfo;
6659         MonoInst *lmf_var = cfg->lmf_var;
6660         gboolean args_clobbered = FALSE;
6661         gboolean trace = FALSE;
6662 #ifdef __native_client_codegen__
6663         guint alignment_check;
6664 #endif
6665
6666         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6667
6668 #if defined(__default_codegen__)
6669         code = cfg->native_code = g_malloc (cfg->code_size);
6670 #elif defined(__native_client_codegen__)
6671         /* native_code_alloc is not 32-byte aligned, native_code is. */
6672         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6673
6674         /* Align native_code to next nearest kNaclAlignment byte. */
6675         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6676         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6677
6678         code = cfg->native_code;
6679
6680         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6681         g_assert (alignment_check == 0);
6682 #endif
6683
6684         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6685                 trace = TRUE;
6686
6687         /* Amount of stack space allocated by register saving code */
6688         pos = 0;
6689
6690         /* Offset between RSP and the CFA */
6691         cfa_offset = 0;
6692
6693         /*
6694          * The prolog consists of the following parts:
6695          * FP present:
6696          * - push rbp, mov rbp, rsp
6697          * - save callee saved regs using pushes
6698          * - allocate frame
6699          * - save rgctx if needed
6700          * - save lmf if needed
6701          * FP not present:
6702          * - allocate frame
6703          * - save rgctx if needed
6704          * - save lmf if needed
6705          * - save callee saved regs using moves
6706          */
6707
6708         // CFA = sp + 8
6709         cfa_offset = 8;
6710         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6711         // IP saved at CFA - 8
6712         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6713         async_exc_point (code);
6714         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6715
6716         if (!cfg->arch.omit_fp) {
6717                 amd64_push_reg (code, AMD64_RBP);
6718                 cfa_offset += 8;
6719                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6720                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6721                 async_exc_point (code);
6722 #ifdef TARGET_WIN32
6723                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6724 #endif
6725                 /* These are handled automatically by the stack marking code */
6726                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6727
6728                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6729                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6730                 async_exc_point (code);
6731 #ifdef TARGET_WIN32
6732                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6733 #endif
6734         }
6735
6736         /* The param area is always at offset 0 from sp */
6737         /* This needs to be allocated here, since it has to come after the spill area */
6738         if (cfg->param_area) {
6739                 if (cfg->arch.omit_fp)
6740                         // FIXME:
6741                         g_assert_not_reached ();
6742                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6743         }
6744
6745         if (cfg->arch.omit_fp) {
6746                 /*
6747                  * On enter, the stack is misaligned by the pushing of the return
6748                  * address. It is either made aligned by the pushing of %rbp, or by
6749                  * this.
6750                  */
6751                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6752                 if ((alloc_size % 16) == 0) {
6753                         alloc_size += 8;
6754                         /* Mark the padding slot as NOREF */
6755                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6756                 }
6757         } else {
6758                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6759                 if (cfg->stack_offset != alloc_size) {
6760                         /* Mark the padding slot as NOREF */
6761                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6762                 }
6763                 cfg->arch.sp_fp_offset = alloc_size;
6764                 alloc_size -= pos;
6765         }
6766
6767         cfg->arch.stack_alloc_size = alloc_size;
6768
6769         /* Allocate stack frame */
6770         if (alloc_size) {
6771                 /* See mono_emit_stack_alloc */
6772 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6773                 guint32 remaining_size = alloc_size;
6774                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6775                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6776                 guint32 offset = code - cfg->native_code;
6777                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6778                         while (required_code_size >= (cfg->code_size - offset))
6779                                 cfg->code_size *= 2;
6780                         cfg->native_code = mono_realloc_native_code (cfg);
6781                         code = cfg->native_code + offset;
6782                         cfg->stat_code_reallocs++;
6783                 }
6784
6785                 while (remaining_size >= 0x1000) {
6786                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6787                         if (cfg->arch.omit_fp) {
6788                                 cfa_offset += 0x1000;
6789                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6790                         }
6791                         async_exc_point (code);
6792 #ifdef TARGET_WIN32
6793                         if (cfg->arch.omit_fp)
6794                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6795 #endif
6796
6797                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6798                         remaining_size -= 0x1000;
6799                 }
6800                 if (remaining_size) {
6801                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6802                         if (cfg->arch.omit_fp) {
6803                                 cfa_offset += remaining_size;
6804                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6805                                 async_exc_point (code);
6806                         }
6807 #ifdef TARGET_WIN32
6808                         if (cfg->arch.omit_fp)
6809                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6810 #endif
6811                 }
6812 #else
6813                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6814                 if (cfg->arch.omit_fp) {
6815                         cfa_offset += alloc_size;
6816                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6817                         async_exc_point (code);
6818                 }
6819 #endif
6820         }
6821
6822         /* Stack alignment check */
6823 #if 0
6824         {
6825                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6826                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6827                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6828                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6829                 amd64_breakpoint (code);
6830         }
6831 #endif
6832
6833         if (mini_get_debug_options ()->init_stacks) {
6834                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6835
6836                 /* Save registers to the red zone */
6837                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6838                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6839
6840                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6841                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6842                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6843
6844                 amd64_cld (code);
6845 #if defined(__default_codegen__)
6846                 amd64_prefix (code, X86_REP_PREFIX);
6847                 amd64_stosl (code);
6848 #elif defined(__native_client_codegen__)
6849                 /* NaCl stos pseudo-instruction */
6850                 amd64_codegen_pre (code);
6851                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6852                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6853                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6854                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6855                 amd64_prefix (code, X86_REP_PREFIX);
6856                 amd64_stosl (code);
6857                 amd64_codegen_post (code);
6858 #endif /* __native_client_codegen__ */
6859
6860                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6861                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6862         }
6863
6864         /* Save LMF */
6865         if (method->save_lmf)
6866                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6867
6868         /* Save callee saved registers */
6869         if (cfg->arch.omit_fp) {
6870                 save_area_offset = cfg->arch.reg_save_area_offset;
6871                 /* Save caller saved registers after sp is adjusted */
6872                 /* The registers are saved at the bottom of the frame */
6873                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6874         } else {
6875                 /* The registers are saved just below the saved rbp */
6876                 save_area_offset = cfg->arch.reg_save_area_offset;
6877         }
6878
6879         for (i = 0; i < AMD64_NREG; ++i) {
6880                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6881                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6882
6883                         if (cfg->arch.omit_fp) {
6884                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6885                                 /* These are handled automatically by the stack marking code */
6886                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6887                         } else {
6888                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6889                                 // FIXME: GC
6890                         }
6891
6892                         save_area_offset += 8;
6893                         async_exc_point (code);
6894                 }
6895         }
6896
6897         /* store runtime generic context */
6898         if (cfg->rgctx_var) {
6899                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6900                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6901
6902                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6903
6904                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6905                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6906         }
6907
6908         /* compute max_length in order to use short forward jumps */
6909         max_epilog_size = get_max_epilog_size (cfg);
6910         if (cfg->opt & MONO_OPT_BRANCH) {
6911                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6912                         MonoInst *ins;
6913                         int max_length = 0;
6914
6915                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6916                                 max_length += 6;
6917                         /* max alignment for loops */
6918                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6919                                 max_length += LOOP_ALIGNMENT;
6920 #ifdef __native_client_codegen__
6921                         /* max alignment for native client */
6922                         max_length += kNaClAlignment;
6923 #endif
6924
6925                         MONO_BB_FOR_EACH_INS (bb, ins) {
6926 #ifdef __native_client_codegen__
6927                                 {
6928                                         int space_in_block = kNaClAlignment -
6929                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6930                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6931                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6932                                                 max_length += space_in_block;
6933                                         }
6934                                 }
6935 #endif  /*__native_client_codegen__*/
6936                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6937                         }
6938
6939                         /* Take prolog and epilog instrumentation into account */
6940                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6941                                 max_length += max_epilog_size;
6942
6943                         bb->max_length = max_length;
6944                 }
6945         }
6946
6947         sig = mono_method_signature (method);
6948         pos = 0;
6949
6950         cinfo = cfg->arch.cinfo;
6951
6952         if (sig->ret->type != MONO_TYPE_VOID) {
6953                 /* Save volatile arguments to the stack */
6954                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6955                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6956         }
6957
6958         /* Keep this in sync with emit_load_volatile_arguments */
6959         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6960                 ArgInfo *ainfo = cinfo->args + i;
6961
6962                 ins = cfg->args [i];
6963
6964                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6965                         /* Unused arguments */
6966                         continue;
6967
6968                 /* Save volatile arguments to the stack */
6969                 if (ins->opcode != OP_REGVAR) {
6970                         switch (ainfo->storage) {
6971                         case ArgInIReg: {
6972                                 guint32 size = 8;
6973
6974                                 /* FIXME: I1 etc */
6975                                 /*
6976                                 if (stack_offset & 0x1)
6977                                         size = 1;
6978                                 else if (stack_offset & 0x2)
6979                                         size = 2;
6980                                 else if (stack_offset & 0x4)
6981                                         size = 4;
6982                                 else
6983                                         size = 8;
6984                                 */
6985                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6986
6987                                 /*
6988                                  * Save the original location of 'this',
6989                                  * get_generic_info_from_stack_frame () needs this to properly look up
6990                                  * the argument value during the handling of async exceptions.
6991                                  */
6992                                 if (ins == cfg->args [0]) {
6993                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6994                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6995                                 }
6996                                 break;
6997                         }
6998                         case ArgInFloatSSEReg:
6999                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7000                                 break;
7001                         case ArgInDoubleSSEReg:
7002                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7003                                 break;
7004                         case ArgValuetypeInReg:
7005                                 for (quad = 0; quad < 2; quad ++) {
7006                                         switch (ainfo->pair_storage [quad]) {
7007                                         case ArgInIReg:
7008                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7009                                                 break;
7010                                         case ArgInFloatSSEReg:
7011                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7012                                                 break;
7013                                         case ArgInDoubleSSEReg:
7014                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7015                                                 break;
7016                                         case ArgNone:
7017                                                 break;
7018                                         default:
7019                                                 g_assert_not_reached ();
7020                                         }
7021                                 }
7022                                 break;
7023                         case ArgValuetypeAddrInIReg:
7024                                 if (ainfo->pair_storage [0] == ArgInIReg)
7025                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7026                                 break;
7027                         default:
7028                                 break;
7029                         }
7030                 } else {
7031                         /* Argument allocated to (non-volatile) register */
7032                         switch (ainfo->storage) {
7033                         case ArgInIReg:
7034                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7035                                 break;
7036                         case ArgOnStack:
7037                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7038                                 break;
7039                         default:
7040                                 g_assert_not_reached ();
7041                         }
7042
7043                         if (ins == cfg->args [0]) {
7044                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7045                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7046                         }
7047                 }
7048         }
7049
7050         if (cfg->method->save_lmf)
7051                 args_clobbered = TRUE;
7052
7053         if (trace) {
7054                 args_clobbered = TRUE;
7055                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7056         }
7057
7058         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7059                 args_clobbered = TRUE;
7060
7061         /*
7062          * Optimize the common case of the first bblock making a call with the same
7063          * arguments as the method. This works because the arguments are still in their
7064          * original argument registers.
7065          * FIXME: Generalize this
7066          */
7067         if (!args_clobbered) {
7068                 MonoBasicBlock *first_bb = cfg->bb_entry;
7069                 MonoInst *next;
7070                 int filter = FILTER_IL_SEQ_POINT;
7071
7072                 next = mono_bb_first_inst (first_bb, filter);
7073                 if (!next && first_bb->next_bb) {
7074                         first_bb = first_bb->next_bb;
7075                         next = mono_bb_first_inst (first_bb, filter);
7076                 }
7077
7078                 if (first_bb->in_count > 1)
7079                         next = NULL;
7080
7081                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7082                         ArgInfo *ainfo = cinfo->args + i;
7083                         gboolean match = FALSE;
7084
7085                         ins = cfg->args [i];
7086                         if (ins->opcode != OP_REGVAR) {
7087                                 switch (ainfo->storage) {
7088                                 case ArgInIReg: {
7089                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7090                                                 if (next->dreg == ainfo->reg) {
7091                                                         NULLIFY_INS (next);
7092                                                         match = TRUE;
7093                                                 } else {
7094                                                         next->opcode = OP_MOVE;
7095                                                         next->sreg1 = ainfo->reg;
7096                                                         /* Only continue if the instruction doesn't change argument regs */
7097                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7098                                                                 match = TRUE;
7099                                                 }
7100                                         }
7101                                         break;
7102                                 }
7103                                 default:
7104                                         break;
7105                                 }
7106                         } else {
7107                                 /* Argument allocated to (non-volatile) register */
7108                                 switch (ainfo->storage) {
7109                                 case ArgInIReg:
7110                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7111                                                 NULLIFY_INS (next);
7112                                                 match = TRUE;
7113                                         }
7114                                         break;
7115                                 default:
7116                                         break;
7117                                 }
7118                         }
7119
7120                         if (match) {
7121                                 next = mono_inst_next (next, filter);
7122                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7123                                 if (!next)
7124                                         break;
7125                         }
7126                 }
7127         }
7128
7129         if (cfg->gen_sdb_seq_points) {
7130                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7131
7132                 /* Initialize seq_point_info_var */
7133                 if (cfg->compile_aot) {
7134                         /* Initialize the variable from a GOT slot */
7135                         /* Same as OP_AOTCONST */
7136                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7137                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7138                         g_assert (info_var->opcode == OP_REGOFFSET);
7139                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7140                 }
7141
7142                 if (cfg->compile_aot) {
7143                         /* Initialize ss_tramp_var */
7144                         ins = cfg->arch.ss_tramp_var;
7145                         g_assert (ins->opcode == OP_REGOFFSET);
7146
7147                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7148                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7149                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7150                 } else {
7151                         /* Initialize ss_trigger_page_var */
7152                         ins = cfg->arch.ss_trigger_page_var;
7153
7154                         g_assert (ins->opcode == OP_REGOFFSET);
7155
7156                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7157                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7158                 }
7159         }
7160
7161         cfg->code_len = code - cfg->native_code;
7162
7163         g_assert (cfg->code_len < cfg->code_size);
7164
7165         return code;
7166 }
7167
7168 void
7169 mono_arch_emit_epilog (MonoCompile *cfg)
7170 {
7171         MonoMethod *method = cfg->method;
7172         int quad, i;
7173         guint8 *code;
7174         int max_epilog_size;
7175         CallInfo *cinfo;
7176         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7177         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7178
7179         max_epilog_size = get_max_epilog_size (cfg);
7180
7181         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7182                 cfg->code_size *= 2;
7183                 cfg->native_code = mono_realloc_native_code (cfg);
7184                 cfg->stat_code_reallocs++;
7185         }
7186         code = cfg->native_code + cfg->code_len;
7187
7188         cfg->has_unwind_info_for_epilog = TRUE;
7189
7190         /* Mark the start of the epilog */
7191         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7192
7193         /* Save the uwind state which is needed by the out-of-line code */
7194         mono_emit_unwind_op_remember_state (cfg, code);
7195
7196         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7197                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7198
7199         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7200
7201         if (method->save_lmf) {
7202                 /* check if we need to restore protection of the stack after a stack overflow */
7203                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7204                         guint8 *patch;
7205                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7206                         /* we load the value in a separate instruction: this mechanism may be
7207                          * used later as a safer way to do thread interruption
7208                          */
7209                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7210                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7211                         patch = code;
7212                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7213                         /* note that the call trampoline will preserve eax/edx */
7214                         x86_call_reg (code, X86_ECX);
7215                         x86_patch (patch, code);
7216                 } else {
7217                         /* FIXME: maybe save the jit tls in the prolog */
7218                 }
7219                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7220                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7221                 }
7222         }
7223
7224         /* Restore callee saved regs */
7225         for (i = 0; i < AMD64_NREG; ++i) {
7226                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7227                         /* Restore only used_int_regs, not arch.saved_iregs */
7228                         if (cfg->used_int_regs & (1 << i)) {
7229                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7230                                 mono_emit_unwind_op_same_value (cfg, code, i);
7231                                 async_exc_point (code);
7232                         }
7233                         save_area_offset += 8;
7234                 }
7235         }
7236
7237         /* Load returned vtypes into registers if needed */
7238         cinfo = cfg->arch.cinfo;
7239         if (cinfo->ret.storage == ArgValuetypeInReg) {
7240                 ArgInfo *ainfo = &cinfo->ret;
7241                 MonoInst *inst = cfg->ret;
7242
7243                 for (quad = 0; quad < 2; quad ++) {
7244                         switch (ainfo->pair_storage [quad]) {
7245                         case ArgInIReg:
7246                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7247                                 break;
7248                         case ArgInFloatSSEReg:
7249                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7250                                 break;
7251                         case ArgInDoubleSSEReg:
7252                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7253                                 break;
7254                         case ArgNone:
7255                                 break;
7256                         default:
7257                                 g_assert_not_reached ();
7258                         }
7259                 }
7260         }
7261
7262         if (cfg->arch.omit_fp) {
7263                 if (cfg->arch.stack_alloc_size) {
7264                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7265                 }
7266         } else {
7267                 amd64_leave (code);
7268                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7269         }
7270         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7271         async_exc_point (code);
7272         amd64_ret (code);
7273
7274         /* Restore the unwind state to be the same as before the epilog */
7275         mono_emit_unwind_op_restore_state (cfg, code);
7276
7277         cfg->code_len = code - cfg->native_code;
7278
7279         g_assert (cfg->code_len < cfg->code_size);
7280 }
7281
7282 void
7283 mono_arch_emit_exceptions (MonoCompile *cfg)
7284 {
7285         MonoJumpInfo *patch_info;
7286         int nthrows, i;
7287         guint8 *code;
7288         MonoClass *exc_classes [16];
7289         guint8 *exc_throw_start [16], *exc_throw_end [16];
7290         guint32 code_size = 0;
7291
7292         /* Compute needed space */
7293         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7294                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7295                         code_size += 40;
7296                 if (patch_info->type == MONO_PATCH_INFO_R8)
7297                         code_size += 8 + 15; /* sizeof (double) + alignment */
7298                 if (patch_info->type == MONO_PATCH_INFO_R4)
7299                         code_size += 4 + 15; /* sizeof (float) + alignment */
7300                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7301                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7302         }
7303
7304 #ifdef __native_client_codegen__
7305         /* Give us extra room on Native Client.  This could be   */
7306         /* more carefully calculated, but bundle alignment makes */
7307         /* it much trickier, so *2 like other places is good.    */
7308         code_size *= 2;
7309 #endif
7310
7311         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7312                 cfg->code_size *= 2;
7313                 cfg->native_code = mono_realloc_native_code (cfg);
7314                 cfg->stat_code_reallocs++;
7315         }
7316
7317         code = cfg->native_code + cfg->code_len;
7318
7319         /* add code to raise exceptions */
7320         nthrows = 0;
7321         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7322                 switch (patch_info->type) {
7323                 case MONO_PATCH_INFO_EXC: {
7324                         MonoClass *exc_class;
7325                         guint8 *buf, *buf2;
7326                         guint32 throw_ip;
7327
7328                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7329
7330                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7331                         g_assert (exc_class);
7332                         throw_ip = patch_info->ip.i;
7333
7334                         //x86_breakpoint (code);
7335                         /* Find a throw sequence for the same exception class */
7336                         for (i = 0; i < nthrows; ++i)
7337                                 if (exc_classes [i] == exc_class)
7338                                         break;
7339                         if (i < nthrows) {
7340                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7341                                 x86_jump_code (code, exc_throw_start [i]);
7342                                 patch_info->type = MONO_PATCH_INFO_NONE;
7343                         }
7344                         else {
7345                                 buf = code;
7346                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7347                                 buf2 = code;
7348
7349                                 if (nthrows < 16) {
7350                                         exc_classes [nthrows] = exc_class;
7351                                         exc_throw_start [nthrows] = code;
7352                                 }
7353                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7354
7355                                 patch_info->type = MONO_PATCH_INFO_NONE;
7356
7357                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7358
7359                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7360                                 while (buf < buf2)
7361                                         x86_nop (buf);
7362
7363                                 if (nthrows < 16) {
7364                                         exc_throw_end [nthrows] = code;
7365                                         nthrows ++;
7366                                 }
7367                         }
7368                         break;
7369                 }
7370                 default:
7371                         /* do nothing */
7372                         break;
7373                 }
7374                 g_assert(code < cfg->native_code + cfg->code_size);
7375         }
7376
7377         /* Handle relocations with RIP relative addressing */
7378         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7379                 gboolean remove = FALSE;
7380                 guint8 *orig_code = code;
7381
7382                 switch (patch_info->type) {
7383                 case MONO_PATCH_INFO_R8:
7384                 case MONO_PATCH_INFO_R4: {
7385                         guint8 *pos, *patch_pos;
7386                         guint32 target_pos;
7387
7388                         /* The SSE opcodes require a 16 byte alignment */
7389 #if defined(__default_codegen__)
7390                         code = (guint8*)ALIGN_TO (code, 16);
7391 #elif defined(__native_client_codegen__)
7392                         {
7393                                 /* Pad this out with HLT instructions  */
7394                                 /* or we can get garbage bytes emitted */
7395                                 /* which will fail validation          */
7396                                 guint8 *aligned_code;
7397                                 /* extra align to make room for  */
7398                                 /* mov/push below                      */
7399                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7400                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7401                                 /* The technique of hiding data in an  */
7402                                 /* instruction has a problem here: we  */
7403                                 /* need the data aligned to a 16-byte  */
7404                                 /* boundary but the instruction cannot */
7405                                 /* cross the bundle boundary. so only  */
7406                                 /* odd multiples of 16 can be used     */
7407                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7408                                         aligned_code += 16;
7409                                 }
7410                                 while (code < aligned_code) {
7411                                         *(code++) = 0xf4; /* hlt */
7412                                 }
7413                         }
7414 #endif
7415
7416                         pos = cfg->native_code + patch_info->ip.i;
7417                         if (IS_REX (pos [1])) {
7418                                 patch_pos = pos + 5;
7419                                 target_pos = code - pos - 9;
7420                         }
7421                         else {
7422                                 patch_pos = pos + 4;
7423                                 target_pos = code - pos - 8;
7424                         }
7425
7426                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7427 #ifdef __native_client_codegen__
7428                                 /* Hide 64-bit data in a         */
7429                                 /* "mov imm64, r11" instruction. */
7430                                 /* write it before the start of  */
7431                                 /* the data*/
7432                                 *(code-2) = 0x49; /* prefix      */
7433                                 *(code-1) = 0xbb; /* mov X, %r11 */
7434 #endif
7435                                 *(double*)code = *(double*)patch_info->data.target;
7436                                 code += sizeof (double);
7437                         } else {
7438 #ifdef __native_client_codegen__
7439                                 /* Hide 32-bit data in a        */
7440                                 /* "push imm32" instruction.    */
7441                                 *(code-1) = 0x68; /* push */
7442 #endif
7443                                 *(float*)code = *(float*)patch_info->data.target;
7444                                 code += sizeof (float);
7445                         }
7446
7447                         *(guint32*)(patch_pos) = target_pos;
7448
7449                         remove = TRUE;
7450                         break;
7451                 }
7452                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7453                         guint8 *pos;
7454
7455                         if (cfg->compile_aot)
7456                                 continue;
7457
7458                         /*loading is faster against aligned addresses.*/
7459                         code = (guint8*)ALIGN_TO (code, 8);
7460                         memset (orig_code, 0, code - orig_code);
7461
7462                         pos = cfg->native_code + patch_info->ip.i;
7463
7464                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7465                         if (IS_REX (pos [1]))
7466                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7467                         else
7468                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7469
7470                         *(gpointer*)code = (gpointer)patch_info->data.target;
7471                         code += sizeof (gpointer);
7472
7473                         remove = TRUE;
7474                         break;
7475                 }
7476                 default:
7477                         break;
7478                 }
7479
7480                 if (remove) {
7481                         if (patch_info == cfg->patch_info)
7482                                 cfg->patch_info = patch_info->next;
7483                         else {
7484                                 MonoJumpInfo *tmp;
7485
7486                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7487                                         ;
7488                                 tmp->next = patch_info->next;
7489                         }
7490                 }
7491                 g_assert (code < cfg->native_code + cfg->code_size);
7492         }
7493
7494         cfg->code_len = code - cfg->native_code;
7495
7496         g_assert (cfg->code_len < cfg->code_size);
7497
7498 }
7499
7500 #endif /* DISABLE_JIT */
7501
7502 void*
7503 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7504 {
7505         guchar *code = p;
7506         MonoMethodSignature *sig;
7507         MonoInst *inst;
7508         int i, n, stack_area = 0;
7509
7510         /* Keep this in sync with mono_arch_get_argument_info */
7511
7512         if (enable_arguments) {
7513                 /* Allocate a new area on the stack and save arguments there */
7514                 sig = mono_method_signature (cfg->method);
7515
7516                 n = sig->param_count + sig->hasthis;
7517
7518                 stack_area = ALIGN_TO (n * 8, 16);
7519
7520                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7521
7522                 for (i = 0; i < n; ++i) {
7523                         inst = cfg->args [i];
7524
7525                         if (inst->opcode == OP_REGVAR)
7526                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7527                         else {
7528                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7529                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7530                         }
7531                 }
7532         }
7533
7534         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7535         amd64_set_reg_template (code, AMD64_ARG_REG1);
7536         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7537         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7538
7539         if (enable_arguments)
7540                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7541
7542         return code;
7543 }
7544
7545 enum {
7546         SAVE_NONE,
7547         SAVE_STRUCT,
7548         SAVE_EAX,
7549         SAVE_EAX_EDX,
7550         SAVE_XMM
7551 };
7552
7553 void*
7554 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7555 {
7556         guchar *code = p;
7557         int save_mode = SAVE_NONE;
7558         MonoMethod *method = cfg->method;
7559         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7560         int i;
7561
7562         switch (ret_type->type) {
7563         case MONO_TYPE_VOID:
7564                 /* special case string .ctor icall */
7565                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7566                         save_mode = SAVE_EAX;
7567                 else
7568                         save_mode = SAVE_NONE;
7569                 break;
7570         case MONO_TYPE_I8:
7571         case MONO_TYPE_U8:
7572                 save_mode = SAVE_EAX;
7573                 break;
7574         case MONO_TYPE_R4:
7575         case MONO_TYPE_R8:
7576                 save_mode = SAVE_XMM;
7577                 break;
7578         case MONO_TYPE_GENERICINST:
7579                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7580                         save_mode = SAVE_EAX;
7581                         break;
7582                 }
7583                 /* Fall through */
7584         case MONO_TYPE_VALUETYPE:
7585                 save_mode = SAVE_STRUCT;
7586                 break;
7587         default:
7588                 save_mode = SAVE_EAX;
7589                 break;
7590         }
7591
7592         /* Save the result and copy it into the proper argument register */
7593         switch (save_mode) {
7594         case SAVE_EAX:
7595                 amd64_push_reg (code, AMD64_RAX);
7596                 /* Align stack */
7597                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7598                 if (enable_arguments)
7599                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7600                 break;
7601         case SAVE_STRUCT:
7602                 /* FIXME: */
7603                 if (enable_arguments)
7604                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7605                 break;
7606         case SAVE_XMM:
7607                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7608                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7609                 /* Align stack */
7610                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7611                 /*
7612                  * The result is already in the proper argument register so no copying
7613                  * needed.
7614                  */
7615                 break;
7616         case SAVE_NONE:
7617                 break;
7618         default:
7619                 g_assert_not_reached ();
7620         }
7621
7622         /* Set %al since this is a varargs call */
7623         if (save_mode == SAVE_XMM)
7624                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7625         else
7626                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7627
7628         if (preserve_argument_registers) {
7629                 for (i = 0; i < PARAM_REGS; ++i)
7630                         amd64_push_reg (code, param_regs [i]);
7631         }
7632
7633         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7634         amd64_set_reg_template (code, AMD64_ARG_REG1);
7635         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7636
7637         if (preserve_argument_registers) {
7638                 for (i = PARAM_REGS - 1; i >= 0; --i)
7639                         amd64_pop_reg (code, param_regs [i]);
7640         }
7641
7642         /* Restore result */
7643         switch (save_mode) {
7644         case SAVE_EAX:
7645                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7646                 amd64_pop_reg (code, AMD64_RAX);
7647                 break;
7648         case SAVE_STRUCT:
7649                 /* FIXME: */
7650                 break;
7651         case SAVE_XMM:
7652                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7653                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7654                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7655                 break;
7656         case SAVE_NONE:
7657                 break;
7658         default:
7659                 g_assert_not_reached ();
7660         }
7661
7662         return code;
7663 }
7664
7665 void
7666 mono_arch_flush_icache (guint8 *code, gint size)
7667 {
7668         /* Not needed */
7669 }
7670
7671 void
7672 mono_arch_flush_register_windows (void)
7673 {
7674 }
7675
7676 gboolean
7677 mono_arch_is_inst_imm (gint64 imm)
7678 {
7679         return amd64_is_imm32 (imm);
7680 }
7681
7682 /*
7683  * Determine whenever the trap whose info is in SIGINFO is caused by
7684  * integer overflow.
7685  */
7686 gboolean
7687 mono_arch_is_int_overflow (void *sigctx, void *info)
7688 {
7689         MonoContext ctx;
7690         guint8* rip;
7691         int reg;
7692         gint64 value;
7693
7694         mono_sigctx_to_monoctx (sigctx, &ctx);
7695
7696         rip = (guint8*)ctx.gregs [AMD64_RIP];
7697
7698         if (IS_REX (rip [0])) {
7699                 reg = amd64_rex_b (rip [0]);
7700                 rip ++;
7701         }
7702         else
7703                 reg = 0;
7704
7705         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7706                 /* idiv REG */
7707                 reg += x86_modrm_rm (rip [1]);
7708
7709                 value = ctx.gregs [reg];
7710
7711                 if (value == -1)
7712                         return TRUE;
7713         }
7714
7715         return FALSE;
7716 }
7717
7718 guint32
7719 mono_arch_get_patch_offset (guint8 *code)
7720 {
7721         return 3;
7722 }
7723
7724 /**
7725  * mono_breakpoint_clean_code:
7726  *
7727  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7728  * breakpoints in the original code, they are removed in the copy.
7729  *
7730  * Returns TRUE if no sw breakpoint was present.
7731  */
7732 gboolean
7733 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7734 {
7735         /*
7736          * If method_start is non-NULL we need to perform bound checks, since we access memory
7737          * at code - offset we could go before the start of the method and end up in a different
7738          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7739          * instead.
7740          */
7741         if (!method_start || code - offset >= method_start) {
7742                 memcpy (buf, code - offset, size);
7743         } else {
7744                 int diff = code - method_start;
7745                 memset (buf, 0, size);
7746                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7747         }
7748         return TRUE;
7749 }
7750
7751 #if defined(__native_client_codegen__)
7752 /* For membase calls, we want the base register. for Native Client,  */
7753 /* all indirect calls have the following sequence with the given sizes: */
7754 /* mov %eXX,%eXX                                [2-3]   */
7755 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7756 /* and $0xffffffffffffffe0,%r11d                [4]     */
7757 /* add %r15,%r11                                [3]     */
7758 /* callq *%r11                                  [3]     */
7759
7760
7761 /* Determine if code points to a NaCl call-through-register sequence, */
7762 /* (i.e., the last 3 instructions listed above) */
7763 int
7764 is_nacl_call_reg_sequence(guint8* code)
7765 {
7766         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7767                                "\x4d\x03\xdf"     /* add */
7768                                "\x41\xff\xd3";   /* call */
7769         return memcmp(code, sequence, 10) == 0;
7770 }
7771
7772 /* Determine if code points to the first opcode of the mov membase component */
7773 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7774 /* (there could be a REX prefix before the opcode but it is ignored) */
7775 static int
7776 is_nacl_indirect_call_membase_sequence(guint8* code)
7777 {
7778                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7779         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7780                /* and that src reg = dest reg */
7781                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7782                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7783                IS_REX(code[2]) &&
7784                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7785                /* and has dst of r11 and base of r15 */
7786                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7787                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7788 }
7789 #endif /* __native_client_codegen__ */
7790
7791 int
7792 mono_arch_get_this_arg_reg (guint8 *code)
7793 {
7794         return AMD64_ARG_REG1;
7795 }
7796
7797 gpointer
7798 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7799 {
7800         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7801 }
7802
7803 #define MAX_ARCH_DELEGATE_PARAMS 10
7804
7805 static gpointer
7806 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7807 {
7808         guint8 *code, *start;
7809         GSList *unwind_ops = NULL;
7810         int i;
7811
7812         unwind_ops = mono_arch_get_cie_program ();
7813
7814         if (has_target) {
7815                 start = code = mono_global_codeman_reserve (64);
7816
7817                 /* Replace the this argument with the target */
7818                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7819                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7820                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7821
7822                 g_assert ((code - start) < 64);
7823         } else {
7824                 start = code = mono_global_codeman_reserve (64);
7825
7826                 if (param_count == 0) {
7827                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7828                 } else {
7829                         /* We have to shift the arguments left */
7830                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7831                         for (i = 0; i < param_count; ++i) {
7832 #ifdef TARGET_WIN32
7833                                 if (i < 3)
7834                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7835                                 else
7836                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7837 #else
7838                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7839 #endif
7840                         }
7841
7842                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7843                 }
7844                 g_assert ((code - start) < 64);
7845         }
7846
7847         nacl_global_codeman_validate (&start, 64, &code);
7848         mono_arch_flush_icache (start, code - start);
7849
7850         if (has_target) {
7851                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7852         } else {
7853                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7854                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7855                 g_free (name);
7856         }
7857
7858         if (mono_jit_map_is_enabled ()) {
7859                 char *buff;
7860                 if (has_target)
7861                         buff = (char*)"delegate_invoke_has_target";
7862                 else
7863                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7864                 mono_emit_jit_tramp (start, code - start, buff);
7865                 if (!has_target)
7866                         g_free (buff);
7867         }
7868         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7869
7870         return start;
7871 }
7872
7873 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7874
7875 static gpointer
7876 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7877 {
7878         guint8 *code, *start;
7879         int size = 20;
7880         char *tramp_name;
7881         GSList *unwind_ops;
7882
7883         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7884                 return NULL;
7885
7886         start = code = mono_global_codeman_reserve (size);
7887
7888         unwind_ops = mono_arch_get_cie_program ();
7889
7890         /* Replace the this argument with the target */
7891         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7892         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7893
7894         if (load_imt_reg) {
7895                 /* Load the IMT reg */
7896                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7897         }
7898
7899         /* Load the vtable */
7900         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7901         amd64_jump_membase (code, AMD64_RAX, offset);
7902         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7903
7904         if (load_imt_reg)
7905                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
7906         else
7907                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
7908         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7909         g_free (tramp_name);
7910
7911         return start;
7912 }
7913
7914 /*
7915  * mono_arch_get_delegate_invoke_impls:
7916  *
7917  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7918  * trampolines.
7919  */
7920 GSList*
7921 mono_arch_get_delegate_invoke_impls (void)
7922 {
7923         GSList *res = NULL;
7924         MonoTrampInfo *info;
7925         int i;
7926
7927         get_delegate_invoke_impl (&info, TRUE, 0);
7928         res = g_slist_prepend (res, info);
7929
7930         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7931                 get_delegate_invoke_impl (&info, FALSE, i);
7932                 res = g_slist_prepend (res, info);
7933         }
7934
7935         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7936                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7937                 res = g_slist_prepend (res, info);
7938
7939                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7940                 res = g_slist_prepend (res, info);
7941         }
7942
7943         return res;
7944 }
7945
7946 gpointer
7947 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7948 {
7949         guint8 *code, *start;
7950         int i;
7951
7952         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7953                 return NULL;
7954
7955         /* FIXME: Support more cases */
7956         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7957                 return NULL;
7958
7959         if (has_target) {
7960                 static guint8* cached = NULL;
7961
7962                 if (cached)
7963                         return cached;
7964
7965                 if (mono_aot_only) {
7966                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7967                 } else {
7968                         MonoTrampInfo *info;
7969                         start = get_delegate_invoke_impl (&info, TRUE, 0);
7970                         mono_tramp_info_register (info, NULL);
7971                 }
7972
7973                 mono_memory_barrier ();
7974
7975                 cached = start;
7976         } else {
7977                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7978                 for (i = 0; i < sig->param_count; ++i)
7979                         if (!mono_is_regsize_var (sig->params [i]))
7980                                 return NULL;
7981                 if (sig->param_count > 4)
7982                         return NULL;
7983
7984                 code = cache [sig->param_count];
7985                 if (code)
7986                         return code;
7987
7988                 if (mono_aot_only) {
7989                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7990                         start = mono_aot_get_trampoline (name);
7991                         g_free (name);
7992                 } else {
7993                         MonoTrampInfo *info;
7994                         start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7995                         mono_tramp_info_register (info, NULL);
7996                 }
7997
7998                 mono_memory_barrier ();
7999
8000                 cache [sig->param_count] = start;
8001         }
8002
8003         return start;
8004 }
8005
8006 gpointer
8007 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8008 {
8009         MonoTrampInfo *info;
8010         gpointer code;
8011
8012         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8013         if (code)
8014                 mono_tramp_info_register (info, NULL);
8015         return code;
8016 }
8017
8018 void
8019 mono_arch_finish_init (void)
8020 {
8021 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8022         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8023 #endif
8024 }
8025
8026 void
8027 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8028 {
8029 }
8030
8031 #if defined(__default_codegen__)
8032 #define CMP_SIZE (6 + 1)
8033 #define CMP_REG_REG_SIZE (4 + 1)
8034 #define BR_SMALL_SIZE 2
8035 #define BR_LARGE_SIZE 6
8036 #define MOV_REG_IMM_SIZE 10
8037 #define MOV_REG_IMM_32BIT_SIZE 6
8038 #define JUMP_REG_SIZE (2 + 1)
8039 #elif defined(__native_client_codegen__)
8040 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8041 #define CMP_SIZE ((6 + 1) * 2 - 1)
8042 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8043 #define BR_SMALL_SIZE (2 * 2 - 1)
8044 #define BR_LARGE_SIZE (6 * 2 - 1)
8045 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8046 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8047 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8048 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8049 /* Jump membase's size is large and unpredictable    */
8050 /* in native client, just pad it out a whole bundle. */
8051 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8052 #endif
8053
8054 static int
8055 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8056 {
8057         int i, distance = 0;
8058         for (i = start; i < target; ++i)
8059                 distance += imt_entries [i]->chunk_size;
8060         return distance;
8061 }
8062
8063 /*
8064  * LOCKING: called with the domain lock held
8065  */
8066 gpointer
8067 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8068         gpointer fail_tramp)
8069 {
8070         int i;
8071         int size = 0;
8072         guint8 *code, *start;
8073         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8074         GSList *unwind_ops;
8075
8076         for (i = 0; i < count; ++i) {
8077                 MonoIMTCheckItem *item = imt_entries [i];
8078                 if (item->is_equals) {
8079                         if (item->check_target_idx) {
8080                                 if (!item->compare_done) {
8081                                         if (amd64_is_imm32 (item->key))
8082                                                 item->chunk_size += CMP_SIZE;
8083                                         else
8084                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8085                                 }
8086                                 if (item->has_target_code) {
8087                                         item->chunk_size += MOV_REG_IMM_SIZE;
8088                                 } else {
8089                                         if (vtable_is_32bit)
8090                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8091                                         else
8092                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8093 #ifdef __native_client_codegen__
8094                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8095 #endif
8096                                 }
8097                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8098                         } else {
8099                                 if (fail_tramp) {
8100                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8101                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8102                                 } else {
8103                                         if (vtable_is_32bit)
8104                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8105                                         else
8106                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8107                                         item->chunk_size += JUMP_REG_SIZE;
8108                                         /* with assert below:
8109                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8110                                          */
8111 #ifdef __native_client_codegen__
8112                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8113 #endif
8114                                 }
8115                         }
8116                 } else {
8117                         if (amd64_is_imm32 (item->key))
8118                                 item->chunk_size += CMP_SIZE;
8119                         else
8120                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8121                         item->chunk_size += BR_LARGE_SIZE;
8122                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8123                 }
8124                 size += item->chunk_size;
8125         }
8126 #if defined(__native_client__) && defined(__native_client_codegen__)
8127         /* In Native Client, we don't re-use thunks, allocate from the */
8128         /* normal code manager paths. */
8129         code = mono_domain_code_reserve (domain, size);
8130 #else
8131         if (fail_tramp)
8132                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8133         else
8134                 code = mono_domain_code_reserve (domain, size);
8135 #endif
8136         start = code;
8137
8138         unwind_ops = mono_arch_get_cie_program ();
8139
8140         for (i = 0; i < count; ++i) {
8141                 MonoIMTCheckItem *item = imt_entries [i];
8142                 item->code_target = code;
8143                 if (item->is_equals) {
8144                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8145
8146                         if (item->check_target_idx || fail_case) {
8147                                 if (!item->compare_done || fail_case) {
8148                                         if (amd64_is_imm32 (item->key))
8149                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8150                                         else {
8151                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8152                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8153                                         }
8154                                 }
8155                                 item->jmp_code = code;
8156                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8157                                 if (item->has_target_code) {
8158                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8159                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8160                                 } else {
8161                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8162                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8163                                 }
8164
8165                                 if (fail_case) {
8166                                         amd64_patch (item->jmp_code, code);
8167                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8168                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8169                                         item->jmp_code = NULL;
8170                                 }
8171                         } else {
8172                                 /* enable the commented code to assert on wrong method */
8173 #if 0
8174                                 if (amd64_is_imm32 (item->key))
8175                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8176                                 else {
8177                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8178                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8179                                 }
8180                                 item->jmp_code = code;
8181                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8182                                 /* See the comment below about R10 */
8183                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8184                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8185                                 amd64_patch (item->jmp_code, code);
8186                                 amd64_breakpoint (code);
8187                                 item->jmp_code = NULL;
8188 #else
8189                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8190                                    needs to be preserved.  R10 needs
8191                                    to be preserved for calls which
8192                                    require a runtime generic context,
8193                                    but interface calls don't. */
8194                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8195                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8196 #endif
8197                         }
8198                 } else {
8199                         if (amd64_is_imm32 (item->key))
8200                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8201                         else {
8202                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8203                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8204                         }
8205                         item->jmp_code = code;
8206                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8207                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8208                         else
8209                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8210                 }
8211                 g_assert (code - item->code_target <= item->chunk_size);
8212         }
8213         /* patch the branches to get to the target items */
8214         for (i = 0; i < count; ++i) {
8215                 MonoIMTCheckItem *item = imt_entries [i];
8216                 if (item->jmp_code) {
8217                         if (item->check_target_idx) {
8218                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8219                         }
8220                 }
8221         }
8222
8223         if (!fail_tramp)
8224                 mono_stats.imt_thunks_size += code - start;
8225         g_assert (code - start <= size);
8226
8227         nacl_domain_code_validate(domain, &start, size, &code);
8228         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8229
8230         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8231
8232         return start;
8233 }
8234
8235 MonoMethod*
8236 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8237 {
8238         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8239 }
8240
8241 MonoVTable*
8242 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8243 {
8244         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8245 }
8246
8247 GSList*
8248 mono_arch_get_cie_program (void)
8249 {
8250         GSList *l = NULL;
8251
8252         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8253         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8254
8255         return l;
8256 }
8257
8258 #ifndef DISABLE_JIT
8259
8260 MonoInst*
8261 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8262 {
8263         MonoInst *ins = NULL;
8264         int opcode = 0;
8265
8266         if (cmethod->klass == mono_defaults.math_class) {
8267                 if (strcmp (cmethod->name, "Sin") == 0) {
8268                         opcode = OP_SIN;
8269                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8270                         opcode = OP_COS;
8271                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8272                         opcode = OP_SQRT;
8273                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8274                         opcode = OP_ABS;
8275                 }
8276
8277                 if (opcode && fsig->param_count == 1) {
8278                         MONO_INST_NEW (cfg, ins, opcode);
8279                         ins->type = STACK_R8;
8280                         ins->dreg = mono_alloc_freg (cfg);
8281                         ins->sreg1 = args [0]->dreg;
8282                         MONO_ADD_INS (cfg->cbb, ins);
8283                 }
8284
8285                 opcode = 0;
8286                 if (cfg->opt & MONO_OPT_CMOV) {
8287                         if (strcmp (cmethod->name, "Min") == 0) {
8288                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8289                                         opcode = OP_IMIN;
8290                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8291                                         opcode = OP_IMIN_UN;
8292                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8293                                         opcode = OP_LMIN;
8294                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8295                                         opcode = OP_LMIN_UN;
8296                         } else if (strcmp (cmethod->name, "Max") == 0) {
8297                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8298                                         opcode = OP_IMAX;
8299                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8300                                         opcode = OP_IMAX_UN;
8301                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8302                                         opcode = OP_LMAX;
8303                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8304                                         opcode = OP_LMAX_UN;
8305                         }
8306                 }
8307
8308                 if (opcode && fsig->param_count == 2) {
8309                         MONO_INST_NEW (cfg, ins, opcode);
8310                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8311                         ins->dreg = mono_alloc_ireg (cfg);
8312                         ins->sreg1 = args [0]->dreg;
8313                         ins->sreg2 = args [1]->dreg;
8314                         MONO_ADD_INS (cfg->cbb, ins);
8315                 }
8316
8317 #if 0
8318                 /* OP_FREM is not IEEE compatible */
8319                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8320                         MONO_INST_NEW (cfg, ins, OP_FREM);
8321                         ins->inst_i0 = args [0];
8322                         ins->inst_i1 = args [1];
8323                 }
8324 #endif
8325         }
8326
8327         return ins;
8328 }
8329 #endif
8330
8331 gboolean
8332 mono_arch_print_tree (MonoInst *tree, int arity)
8333 {
8334         return 0;
8335 }
8336
8337 mgreg_t
8338 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8339 {
8340         return ctx->gregs [reg];
8341 }
8342
8343 void
8344 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8345 {
8346         ctx->gregs [reg] = val;
8347 }
8348
8349 gpointer
8350 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8351 {
8352         gpointer *sp, old_value;
8353         char *bp;
8354
8355         /*Load the spvar*/
8356         bp = MONO_CONTEXT_GET_BP (ctx);
8357         sp = *(gpointer*)(bp + clause->exvar_offset);
8358
8359         old_value = *sp;
8360         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8361                 return old_value;
8362
8363         *sp = new_value;
8364
8365         return old_value;
8366 }
8367
8368 /*
8369  * mono_arch_emit_load_aotconst:
8370  *
8371  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8372  * TARGET from the mscorlib GOT in full-aot code.
8373  * On AMD64, the result is placed into R11.
8374  */
8375 guint8*
8376 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8377 {
8378         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8379         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8380
8381         return code;
8382 }
8383
8384 /*
8385  * mono_arch_get_trampolines:
8386  *
8387  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8388  * for AOT.
8389  */
8390 GSList *
8391 mono_arch_get_trampolines (gboolean aot)
8392 {
8393         return mono_amd64_get_exception_trampolines (aot);
8394 }
8395
8396 /* Soft Debug support */
8397 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8398
8399 /*
8400  * mono_arch_set_breakpoint:
8401  *
8402  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8403  * The location should contain code emitted by OP_SEQ_POINT.
8404  */
8405 void
8406 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8407 {
8408         guint8 *code = ip;
8409         guint8 *orig_code = code;
8410
8411         if (ji->from_aot) {
8412                 guint32 native_offset = ip - (guint8*)ji->code_start;
8413                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8414
8415                 g_assert (info->bp_addrs [native_offset] == 0);
8416                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8417         } else {
8418                 /*
8419                  * In production, we will use int3 (has to fix the size in the md
8420                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8421                  * instead.
8422                  */
8423                 g_assert (code [0] == 0x90);
8424                 if (breakpoint_size == 8) {
8425                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8426                 } else {
8427                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8428                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8429                 }
8430
8431                 g_assert (code - orig_code == breakpoint_size);
8432         }
8433 }
8434
8435 /*
8436  * mono_arch_clear_breakpoint:
8437  *
8438  *   Clear the breakpoint at IP.
8439  */
8440 void
8441 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8442 {
8443         guint8 *code = ip;
8444         int i;
8445
8446         if (ji->from_aot) {
8447                 guint32 native_offset = ip - (guint8*)ji->code_start;
8448                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8449
8450                 info->bp_addrs [native_offset] = NULL;
8451         } else {
8452                 for (i = 0; i < breakpoint_size; ++i)
8453                         x86_nop (code);
8454         }
8455 }
8456
8457 gboolean
8458 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8459 {
8460 #ifdef HOST_WIN32
8461         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8462         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8463                 return TRUE;
8464         else
8465                 return FALSE;
8466 #else
8467         siginfo_t* sinfo = (siginfo_t*) info;
8468         /* Sometimes the address is off by 4 */
8469         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8470                 return TRUE;
8471         else
8472                 return FALSE;
8473 #endif
8474 }
8475
8476 /*
8477  * mono_arch_skip_breakpoint:
8478  *
8479  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8480  * we resume, the instruction is not executed again.
8481  */
8482 void
8483 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8484 {
8485         if (ji->from_aot) {
8486                 /* The breakpoint instruction is a call */
8487         } else {
8488                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8489         }
8490 }
8491
8492 /*
8493  * mono_arch_start_single_stepping:
8494  *
8495  *   Start single stepping.
8496  */
8497 void
8498 mono_arch_start_single_stepping (void)
8499 {
8500         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8501         ss_trampoline = mini_get_single_step_trampoline ();
8502 }
8503
8504 /*
8505  * mono_arch_stop_single_stepping:
8506  *
8507  *   Stop single stepping.
8508  */
8509 void
8510 mono_arch_stop_single_stepping (void)
8511 {
8512         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8513         ss_trampoline = NULL;
8514 }
8515
8516 /*
8517  * mono_arch_is_single_step_event:
8518  *
8519  *   Return whenever the machine state in SIGCTX corresponds to a single
8520  * step event.
8521  */
8522 gboolean
8523 mono_arch_is_single_step_event (void *info, void *sigctx)
8524 {
8525 #ifdef HOST_WIN32
8526         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8527         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8528                 return TRUE;
8529         else
8530                 return FALSE;
8531 #else
8532         siginfo_t* sinfo = (siginfo_t*) info;
8533         /* Sometimes the address is off by 4 */
8534         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8535                 return TRUE;
8536         else
8537                 return FALSE;
8538 #endif
8539 }
8540
8541 /*
8542  * mono_arch_skip_single_step:
8543  *
8544  *   Modify CTX so the ip is placed after the single step trigger instruction,
8545  * we resume, the instruction is not executed again.
8546  */
8547 void
8548 mono_arch_skip_single_step (MonoContext *ctx)
8549 {
8550         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8551 }
8552
8553 /*
8554  * mono_arch_create_seq_point_info:
8555  *
8556  *   Return a pointer to a data structure which is used by the sequence
8557  * point implementation in AOTed code.
8558  */
8559 gpointer
8560 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8561 {
8562         SeqPointInfo *info;
8563         MonoJitInfo *ji;
8564
8565         // FIXME: Add a free function
8566
8567         mono_domain_lock (domain);
8568         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8569                                                                 code);
8570         mono_domain_unlock (domain);
8571
8572         if (!info) {
8573                 ji = mono_jit_info_table_find (domain, (char*)code);
8574                 g_assert (ji);
8575
8576                 // FIXME: Optimize the size
8577                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8578
8579                 info->ss_tramp_addr = &ss_trampoline;
8580
8581                 mono_domain_lock (domain);
8582                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8583                                                          code, info);
8584                 mono_domain_unlock (domain);
8585         }
8586
8587         return info;
8588 }
8589
8590 void
8591 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8592 {
8593         ext->lmf.previous_lmf = prev_lmf;
8594         /* Mark that this is a MonoLMFExt */
8595         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8596         ext->lmf.rsp = (gssize)ext;
8597 }
8598
8599 #endif
8600
8601 gboolean
8602 mono_arch_opcode_supported (int opcode)
8603 {
8604         switch (opcode) {
8605         case OP_ATOMIC_ADD_I4:
8606         case OP_ATOMIC_ADD_I8:
8607         case OP_ATOMIC_EXCHANGE_I4:
8608         case OP_ATOMIC_EXCHANGE_I8:
8609         case OP_ATOMIC_CAS_I4:
8610         case OP_ATOMIC_CAS_I8:
8611         case OP_ATOMIC_LOAD_I1:
8612         case OP_ATOMIC_LOAD_I2:
8613         case OP_ATOMIC_LOAD_I4:
8614         case OP_ATOMIC_LOAD_I8:
8615         case OP_ATOMIC_LOAD_U1:
8616         case OP_ATOMIC_LOAD_U2:
8617         case OP_ATOMIC_LOAD_U4:
8618         case OP_ATOMIC_LOAD_U8:
8619         case OP_ATOMIC_LOAD_R4:
8620         case OP_ATOMIC_LOAD_R8:
8621         case OP_ATOMIC_STORE_I1:
8622         case OP_ATOMIC_STORE_I2:
8623         case OP_ATOMIC_STORE_I4:
8624         case OP_ATOMIC_STORE_I8:
8625         case OP_ATOMIC_STORE_U1:
8626         case OP_ATOMIC_STORE_U2:
8627         case OP_ATOMIC_STORE_U4:
8628         case OP_ATOMIC_STORE_U8:
8629         case OP_ATOMIC_STORE_R4:
8630         case OP_ATOMIC_STORE_R8:
8631                 return TRUE;
8632         default:
8633                 return FALSE;
8634         }
8635 }