mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 /* The single step trampoline */
  69 static gpointer ss_trampoline;
  70
  71 /* The breakpoint trampoline */
  72 static gpointer bp_trampoline;
  73
  74 /* Offset between fp and the first argument in the callee */
  75 #define ARGS_OFFSET 16
  76 #define GP_SCRATCH_REG AMD64_R11
  77
  78 /*
  79  * AMD64 register usage:
  80  * - callee saved registers are used for global register allocation
  81  * - %r11 is used for materializing 64 bit constants in opcodes
  82  * - the rest is used for local allocation
  83  */
  84
  85 /*
  86  * Floating point comparison results:
  87  *                  ZF PF CF
  88  * A > B            0  0  0
  89  * A < B            0  0  1
  90  * A = B            1  0  0
  91  * A > B            0  0  0
  92  * UNORDERED        1  1  1
  93  */
  94
  95 const char*
  96 mono_arch_regname (int reg)
  97 {
  98         switch (reg) {
  99         case AMD64_RAX: return "%rax";
 100         case AMD64_RBX: return "%rbx";
 101         case AMD64_RCX: return "%rcx";
 102         case AMD64_RDX: return "%rdx";
 103         case AMD64_RSP: return "%rsp";
 104         case AMD64_RBP: return "%rbp";
 105         case AMD64_RDI: return "%rdi";
 106         case AMD64_RSI: return "%rsi";
 107         case AMD64_R8: return "%r8";
 108         case AMD64_R9: return "%r9";
 109         case AMD64_R10: return "%r10";
 110         case AMD64_R11: return "%r11";
 111         case AMD64_R12: return "%r12";
 112         case AMD64_R13: return "%r13";
 113         case AMD64_R14: return "%r14";
 114         case AMD64_R15: return "%r15";
 115         }
 116         return "unknown";
 117 }
 118
 119 static const char * packed_xmmregs [] = {
 120         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 121         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 122 };
 123
 124 static const char * single_xmmregs [] = {
 125         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 126         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 127 };
 128
 129 const char*
 130 mono_arch_fregname (int reg)
 131 {
 132         if (reg < AMD64_XMM_NREG)
 133                 return single_xmmregs [reg];
 134         else
 135                 return "unknown";
 136 }
 137
 138 const char *
 139 mono_arch_xregname (int reg)
 140 {
 141         if (reg < AMD64_XMM_NREG)
 142                 return packed_xmmregs [reg];
 143         else
 144                 return "unknown";
 145 }
 146
 147 static gboolean
 148 debug_omit_fp (void)
 149 {
 150 #if 0
 151         return mono_debug_count ();
 152 #else
 153         return TRUE;
 154 #endif
 155 }
 156
 157 static inline gboolean
 158 amd64_is_near_call (guint8 *code)
 159 {
 160         /* Skip REX */
 161         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 162                 code += 1;
 163
 164         return code [0] == 0xe8;
 165 }
 166
 167 static inline gboolean
 168 amd64_use_imm32 (gint64 val)
 169 {
 170         if (mini_get_debug_options()->single_imm_size)
 171                 return FALSE;
 172
 173         return amd64_is_imm32 (val);
 174 }
 175
 176 #ifdef __native_client_codegen__
 177
 178 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 179 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 180 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 181 /* We only want to force bundle alignment for the top level instruction,    */
 182 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 183 static MonoNativeTlsKey nacl_instruction_depth;
 184
 185 static MonoNativeTlsKey nacl_rex_tag;
 186 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 187
 188 void
 189 amd64_nacl_clear_legacy_prefix_tag ()
 190 {
 191         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 192 }
 193
 194 void
 195 amd64_nacl_tag_legacy_prefix (guint8* code)
 196 {
 197         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 198                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 199 }
 200
 201 void
 202 amd64_nacl_tag_rex (guint8* code)
 203 {
 204         mono_native_tls_set_value (nacl_rex_tag, code);
 205 }
 206
 207 guint8*
 208 amd64_nacl_get_legacy_prefix_tag ()
 209 {
 210         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 211 }
 212
 213 guint8*
 214 amd64_nacl_get_rex_tag ()
 215 {
 216         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 217 }
 218
 219 /* Increment the instruction "depth" described above */
 220 void
 221 amd64_nacl_instruction_pre ()
 222 {
 223         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 224         depth++;
 225         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 226 }
 227
 228 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 229 /* alignment if depth == 0 (top level instruction)                          */
 230 /* IN: start, end    pointers to instruction beginning and end              */
 231 /* OUT: start, end   pointers to beginning and end after possible alignment */
 232 /* GLOBALS: nacl_instruction_depth     defined above                        */
 233 void
 234 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 235 {
 236         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 237         depth--;
 238         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 239
 240         g_assert ( depth >= 0 );
 241         if (depth == 0) {
 242                 uintptr_t space_in_block;
 243                 uintptr_t instlen;
 244                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 245                 /* if legacy prefix is present, and if it was emitted before */
 246                 /* the start of the instruction sequence, adjust the start   */
 247                 if (prefix != NULL && prefix < *start) {
 248                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 249                         *start = prefix;
 250                 }
 251                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 252                 instlen = (uintptr_t)(*end - *start);
 253                 /* Only check for instructions which are less than        */
 254                 /* kNaClAlignment. The only instructions that should ever */
 255                 /* be that long are call sequences, which are already     */
 256                 /* padded out to align the return to the next bundle.     */
 257                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 258                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 259                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 260                         const size_t length = (size_t)((*end)-(*start));
 261                         g_assert (length < MAX_NACL_INST_LENGTH);
 262
 263                         memcpy (copy_of_instruction, *start, length);
 264                         *start = mono_arch_nacl_pad (*start, space_in_block);
 265                         memcpy (*start, copy_of_instruction, length);
 266                         *end = *start + length;
 267                 }
 268                 amd64_nacl_clear_legacy_prefix_tag ();
 269                 amd64_nacl_tag_rex (NULL);
 270         }
 271 }
 272
 273 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 274 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 275 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 276 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 277 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 278 /* IN:      code                                                            */
 279 /*             pointer to current instruction stream (in the                */
 280 /*             middle of an instruction, after opcode is emitted)           */
 281 /*          basereg/offset/dreg                                             */
 282 /*             operands of normal membase address                           */
 283 /* OUT:     code                                                            */
 284 /*             pointer to the end of the membase/memindex emit              */
 285 /* GLOBALS: nacl_rex_tag                                                    */
 286 /*             position in instruction stream that rex prefix was emitted   */
 287 /*          nacl_legacy_prefix_tag                                          */
 288 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 289 void
 290 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 291 {
 292         gint8 true_basereg = basereg;
 293
 294         /* Cache these values, they might change  */
 295         /* as new instructions are emitted below. */
 296         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 297         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 298
 299         /* 'basereg' is given masked to 0x7 at this point, so check */
 300         /* the rex prefix to see if this is an extended register.   */
 301         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 302                 true_basereg |= 0x8;
 303         }
 304
 305 #define X86_LEA_OPCODE (0x8D)
 306
 307         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 308                 guint8* old_instruction_start;
 309
 310                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 311                 /* 32-bits of the old base register (new index register)     */
 312                 guint8 buf[32];
 313                 guint8* buf_ptr = buf;
 314                 size_t insert_len;
 315
 316                 g_assert (rex_tag != NULL);
 317
 318                 if (IS_REX(*rex_tag)) {
 319                         /* The old rex.B should be the new rex.X */
 320                         if (*rex_tag & AMD64_REX_B) {
 321                                 *rex_tag |= AMD64_REX_X;
 322                         }
 323                         /* Since our new base is %r15 set rex.B */
 324                         *rex_tag |= AMD64_REX_B;
 325                 } else {
 326                         /* Shift the instruction by one byte  */
 327                         /* so we can insert a rex prefix      */
 328                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 329                         *code += 1;
 330                         /* New rex prefix only needs rex.B for %r15 base */
 331                         *rex_tag = AMD64_REX(AMD64_REX_B);
 332                 }
 333
 334                 if (legacy_prefix_tag) {
 335                         old_instruction_start = legacy_prefix_tag;
 336                 } else {
 337                         old_instruction_start = rex_tag;
 338                 }
 339
 340                 /* Clears the upper 32-bits of the previous base register */
 341                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 342                 insert_len = buf_ptr - buf;
 343
 344                 /* Move the old instruction forward to make */
 345                 /* room for 'mov' stored in 'buf_ptr'       */
 346                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 347                 *code += insert_len;
 348                 memcpy (old_instruction_start, buf, insert_len);
 349
 350                 /* Sandboxed replacement for the normal membase_emit */
 351                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 352
 353         } else {
 354                 /* Normal default behavior, emit membase memory location */
 355                 x86_membase_emit_body (*code, dreg, basereg, offset);
 356         }
 357 }
 358
 359
 360 static inline unsigned char*
 361 amd64_skip_nops (unsigned char* code)
 362 {
 363         guint8 in_nop;
 364         do {
 365                 in_nop = 0;
 366                 if (   code[0] == 0x90) {
 367                         in_nop = 1;
 368                         code += 1;
 369                 }
 370                 if (   code[0] == 0x66 && code[1] == 0x90) {
 371                         in_nop = 1;
 372                         code += 2;
 373                 }
 374                 if (code[0] == 0x0f && code[1] == 0x1f
 375                  && code[2] == 0x00) {
 376                         in_nop = 1;
 377                         code += 3;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x40 && code[3] == 0x00) {
 381                         in_nop = 1;
 382                         code += 4;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x44 && code[3] == 0x00
 386                  && code[4] == 0x00) {
 387                         in_nop = 1;
 388                         code += 5;
 389                 }
 390                 if (code[0] == 0x66 && code[1] == 0x0f
 391                  && code[2] == 0x1f && code[3] == 0x44
 392                  && code[4] == 0x00 && code[5] == 0x00) {
 393                         in_nop = 1;
 394                         code += 6;
 395                 }
 396                 if (code[0] == 0x0f && code[1] == 0x1f
 397                  && code[2] == 0x80 && code[3] == 0x00
 398                  && code[4] == 0x00 && code[5] == 0x00
 399                  && code[6] == 0x00) {
 400                         in_nop = 1;
 401                         code += 7;
 402                 }
 403                 if (code[0] == 0x0f && code[1] == 0x1f
 404                  && code[2] == 0x84 && code[3] == 0x00
 405                  && code[4] == 0x00 && code[5] == 0x00
 406                  && code[6] == 0x00 && code[7] == 0x00) {
 407                         in_nop = 1;
 408                         code += 8;
 409                 }
 410         } while ( in_nop );
 411         return code;
 412 }
 413
 414 guint8*
 415 mono_arch_nacl_skip_nops (guint8* code)
 416 {
 417   return amd64_skip_nops(code);
 418 }
 419
 420 #endif /*__native_client_codegen__*/
 421
 422 static inline void
 423 amd64_patch (unsigned char* code, gpointer target)
 424 {
 425         guint8 rex = 0;
 426
 427 #ifdef __native_client_codegen__
 428         code = amd64_skip_nops (code);
 429 #endif
 430 #if defined(__native_client_codegen__) && defined(__native_client__)
 431         if (nacl_is_code_address (code)) {
 432                 /* For tail calls, code is patched after being installed */
 433                 /* but not through the normal "patch callsite" method.   */
 434                 unsigned char buf[kNaClAlignment];
 435                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 436                 int ret;
 437                 memcpy (buf, aligned_code, kNaClAlignment);
 438                 /* Patch a temp buffer of bundle size, */
 439                 /* then install to actual location.    */
 440                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 441                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 442                 g_assert (ret == 0);
 443                 return;
 444         }
 445         target = nacl_modify_patch_target (target);
 446 #endif
 447
 448         /* Skip REX */
 449         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 450                 rex = code [0];
 451                 code += 1;
 452         }
 453
 454         if ((code [0] & 0xf8) == 0xb8) {
 455                 /* amd64_set_reg_template */
 456                 *(guint64*)(code + 1) = (guint64)target;
 457         }
 458         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 459                 /* mov 0(%rip), %dreg */
 460                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 461         }
 462         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 463                 /* call *<OFFSET>(%rip) */
 464                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 465         }
 466         else if (code [0] == 0xe8) {
 467                 /* call <DISP> */
 468                 gint64 disp = (guint8*)target - (guint8*)code;
 469                 g_assert (amd64_is_imm32 (disp));
 470                 x86_patch (code, (unsigned char*)target);
 471         }
 472         else
 473                 x86_patch (code, (unsigned char*)target);
 474 }
 475
 476 void
 477 mono_amd64_patch (unsigned char* code, gpointer target)
 478 {
 479         amd64_patch (code, target);
 480 }
 481
 482 typedef enum {
 483         ArgInIReg,
 484         ArgInFloatSSEReg,
 485         ArgInDoubleSSEReg,
 486         ArgOnStack,
 487         ArgValuetypeInReg,
 488         ArgValuetypeAddrInIReg,
 489         /* gsharedvt argument passed by addr */
 490         ArgGSharedVtInReg,
 491         ArgGSharedVtOnStack,
 492         ArgNone /* only in pair_storage */
 493 } ArgStorage;
 494
 495 typedef struct {
 496         gint16 offset;
 497         gint8  reg;
 498         ArgStorage storage;
 499
 500         /* Only if storage == ArgValuetypeInReg */
 501         ArgStorage pair_storage [2];
 502         gint8 pair_regs [2];
 503         /* The size of each pair */
 504         int pair_size [2];
 505         int nregs;
 506 } ArgInfo;
 507
 508 typedef struct {
 509         int nargs;
 510         guint32 stack_usage;
 511         guint32 reg_usage;
 512         guint32 freg_usage;
 513         gboolean need_stack_align;
 514         /* The index of the vret arg in the argument list */
 515         int vret_arg_index;
 516         ArgInfo ret;
 517         ArgInfo sig_cookie;
 518         ArgInfo args [1];
 519 } CallInfo;
 520
 521 #define DEBUG(a) if (cfg->verbose_level > 1) a
 522
 523 #ifdef TARGET_WIN32
 524 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 525
 526 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 527 #else
 528 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 529
 530  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 531 #endif
 532
 533 static void inline
 534 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 535 {
 536     ainfo->offset = *stack_size;
 537
 538     if (*gr >= PARAM_REGS) {
 539                 ainfo->storage = ArgOnStack;
 540                 /* Since the same stack slot size is used for all arg */
 541                 /*  types, it needs to be big enough to hold them all */
 542                 (*stack_size) += sizeof(mgreg_t);
 543     }
 544     else {
 545                 ainfo->storage = ArgInIReg;
 546                 ainfo->reg = param_regs [*gr];
 547                 (*gr) ++;
 548     }
 549 }
 550
 551 #ifdef TARGET_WIN32
 552 #define FLOAT_PARAM_REGS 4
 553 #else
 554 #define FLOAT_PARAM_REGS 8
 555 #endif
 556
 557 static void inline
 558 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 559 {
 560     ainfo->offset = *stack_size;
 561
 562     if (*gr >= FLOAT_PARAM_REGS) {
 563                 ainfo->storage = ArgOnStack;
 564                 /* Since the same stack slot size is used for both float */
 565                 /*  types, it needs to be big enough to hold them both */
 566                 (*stack_size) += sizeof(mgreg_t);
 567     }
 568     else {
 569                 /* A double register */
 570                 if (is_double)
 571                         ainfo->storage = ArgInDoubleSSEReg;
 572                 else
 573                         ainfo->storage = ArgInFloatSSEReg;
 574                 ainfo->reg = *gr;
 575                 (*gr) += 1;
 576     }
 577 }
 578
 579 typedef enum ArgumentClass {
 580         ARG_CLASS_NO_CLASS,
 581         ARG_CLASS_MEMORY,
 582         ARG_CLASS_INTEGER,
 583         ARG_CLASS_SSE
 584 } ArgumentClass;
 585
 586 static ArgumentClass
 587 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 588 {
 589         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 590         MonoType *ptype;
 591
 592         ptype = mini_get_underlying_type (type);
 593         switch (ptype->type) {
 594         case MONO_TYPE_I1:
 595         case MONO_TYPE_U1:
 596         case MONO_TYPE_I2:
 597         case MONO_TYPE_U2:
 598         case MONO_TYPE_I4:
 599         case MONO_TYPE_U4:
 600         case MONO_TYPE_I:
 601         case MONO_TYPE_U:
 602         case MONO_TYPE_STRING:
 603         case MONO_TYPE_OBJECT:
 604         case MONO_TYPE_CLASS:
 605         case MONO_TYPE_SZARRAY:
 606         case MONO_TYPE_PTR:
 607         case MONO_TYPE_FNPTR:
 608         case MONO_TYPE_ARRAY:
 609         case MONO_TYPE_I8:
 610         case MONO_TYPE_U8:
 611                 class2 = ARG_CLASS_INTEGER;
 612                 break;
 613         case MONO_TYPE_R4:
 614         case MONO_TYPE_R8:
 615 #ifdef TARGET_WIN32
 616                 class2 = ARG_CLASS_INTEGER;
 617 #else
 618                 class2 = ARG_CLASS_SSE;
 619 #endif
 620                 break;
 621
 622         case MONO_TYPE_TYPEDBYREF:
 623                 g_assert_not_reached ();
 624
 625         case MONO_TYPE_GENERICINST:
 626                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 627                         class2 = ARG_CLASS_INTEGER;
 628                         break;
 629                 }
 630                 /* fall through */
 631         case MONO_TYPE_VALUETYPE: {
 632                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 633                 int i;
 634
 635                 for (i = 0; i < info->num_fields; ++i) {
 636                         class2 = class1;
 637                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 638                 }
 639                 break;
 640         }
 641         default:
 642                 g_assert_not_reached ();
 643         }
 644
 645         /* Merge */
 646         if (class1 == class2)
 647                 ;
 648         else if (class1 == ARG_CLASS_NO_CLASS)
 649                 class1 = class2;
 650         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 651                 class1 = ARG_CLASS_MEMORY;
 652         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 653                 class1 = ARG_CLASS_INTEGER;
 654         else
 655                 class1 = ARG_CLASS_SSE;
 656
 657         return class1;
 658 }
 659 #ifdef __native_client_codegen__
 660
 661 /* Default alignment for Native Client is 32-byte. */
 662 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 663
 664 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 665 /* Check that alignment doesn't cross an alignment boundary.             */
 666 guint8*
 667 mono_arch_nacl_pad(guint8 *code, int pad)
 668 {
 669         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 670
 671         if (pad == 0) return code;
 672         /* assertion: alignment cannot cross a block boundary */
 673         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 674                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 675         while (pad >= kMaxPadding) {
 676                 amd64_padding (code, kMaxPadding);
 677                 pad -= kMaxPadding;
 678         }
 679         if (pad != 0) amd64_padding (code, pad);
 680         return code;
 681 }
 682 #endif
 683
 684 static int
 685 count_fields_nested (MonoClass *klass)
 686 {
 687         MonoMarshalType *info;
 688         int i, count;
 689
 690         info = mono_marshal_load_type_info (klass);
 691         g_assert(info);
 692         count = 0;
 693         for (i = 0; i < info->num_fields; ++i) {
 694                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 695                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 696                 else
 697                         count ++;
 698         }
 699         return count;
 700 }
 701
 702 static int
 703 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 704 {
 705         MonoMarshalType *info;
 706         int i;
 707
 708         info = mono_marshal_load_type_info (klass);
 709         g_assert(info);
 710         for (i = 0; i < info->num_fields; ++i) {
 711                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 712                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 713                 } else {
 714                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 715                         fields [index].offset += offset;
 716                         index ++;
 717                 }
 718         }
 719         return index;
 720 }
 721
 722 #ifdef TARGET_WIN32
 723 static void
 724 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 725                                          gboolean is_return,
 726                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 727 {
 728         guint32 size, i, nfields;
 729         guint32 argsize = 8;
 730         ArgumentClass arg_class;
 731         MonoMarshalType *info = NULL;
 732         MonoMarshalField *fields = NULL;
 733         MonoClass *klass;
 734         gboolean pass_on_stack = FALSE;
 735
 736         klass = mono_class_from_mono_type (type);
 737         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 738         if (!sig->pinvoke)
 739                 pass_on_stack = TRUE;
 740
 741         /* If this struct can't be split up naturally into 8-byte */
 742         /* chunks (registers), pass it on the stack.              */
 743         if (sig->pinvoke && !pass_on_stack) {
 744                 guint32 align;
 745                 guint32 field_size;
 746
 747                 info = mono_marshal_load_type_info (klass);
 748                 g_assert (info);
 749
 750                 /*
 751                  * Collect field information recursively to be able to
 752                  * handle nested structures.
 753                  */
 754                 nfields = count_fields_nested (klass);
 755                 fields = g_new0 (MonoMarshalField, nfields);
 756                 collect_field_info_nested (klass, fields, 0, 0);
 757
 758                 for (i = 0; i < nfields; ++i) {
 759                         field_size = mono_marshal_type_size (fields [i].field->type,
 760                                                            fields [i].mspec,
 761                                                            &align, TRUE, klass->unicode);
 762                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 763                                 pass_on_stack = TRUE;
 764                                 break;
 765                         }
 766                 }
 767         }
 768
 769         if (pass_on_stack) {
 770                 /* Allways pass in memory */
 771                 ainfo->offset = *stack_size;
 772                 *stack_size += ALIGN_TO (size, 8);
 773                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 774
 775                 g_free (fields);
 776                 return;
 777         }
 778
 779         if (!sig->pinvoke) {
 780                 int n = mono_class_value_size (klass, NULL);
 781
 782                 argsize = n;
 783
 784                 if (n > 8)
 785                         arg_class = ARG_CLASS_MEMORY;
 786                 else
 787                         /* Always pass in 1 integer register */
 788                         arg_class = ARG_CLASS_INTEGER;
 789         } else {
 790                 g_assert (info);
 791
 792                 if (!fields) {
 793                         ainfo->storage = ArgValuetypeInReg;
 794                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 795                         return;
 796                 }
 797
 798                 switch (info->native_size) {
 799                 case 1: case 2: case 4: case 8:
 800                         break;
 801                 default:
 802                         if (is_return) {
 803                                 ainfo->storage = ArgValuetypeAddrInIReg;
 804                                 ainfo->offset = *stack_size;
 805                                 *stack_size += ALIGN_TO (info->native_size, 8);
 806                         }
 807                         else {
 808                                 ainfo->storage = ArgValuetypeAddrInIReg;
 809
 810                                 if (*gr < PARAM_REGS) {
 811                                         ainfo->pair_storage [0] = ArgInIReg;
 812                                         ainfo->pair_regs [0] = param_regs [*gr];
 813                                         (*gr) ++;
 814                                 }
 815                                 else {
 816                                         ainfo->pair_storage [0] = ArgOnStack;
 817                                         ainfo->offset = *stack_size;
 818                                         *stack_size += 8;
 819                                 }
 820                         }
 821
 822                         g_free (fields);
 823                         return;
 824                 }
 825
 826                 int size;
 827                 guint32 align;
 828                 ArgumentClass class1;
 829
 830                 if (nfields == 0)
 831                         class1 = ARG_CLASS_MEMORY;
 832                 else
 833                         class1 = ARG_CLASS_NO_CLASS;
 834                 for (i = 0; i < nfields; ++i) {
 835                         size = mono_marshal_type_size (fields [i].field->type,
 836                                                                                    fields [i].mspec,
 837                                                                                    &align, TRUE, klass->unicode);
 838                         /* How far into this quad this data extends.*/
 839                         /* (8 is size of quad) */
 840                         argsize = fields [i].offset + size;
 841
 842                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 843                 }
 844                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 845                 arg_class = class1;
 846         }
 847
 848         g_free (fields);
 849
 850         /* Allocate registers */
 851         {
 852                 int orig_gr = *gr;
 853                 int orig_fr = *fr;
 854
 855                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 856                         argsize ++;
 857
 858                 ainfo->storage = ArgValuetypeInReg;
 859                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 860                 ainfo->pair_size [0] = argsize;
 861                 ainfo->pair_size [1] = 0;
 862                 ainfo->nregs = 1;
 863                 switch (arg_class) {
 864                 case ARG_CLASS_INTEGER:
 865                         if (*gr >= PARAM_REGS)
 866                                 arg_class = ARG_CLASS_MEMORY;
 867                         else {
 868                                 ainfo->pair_storage [0] = ArgInIReg;
 869                                 if (is_return)
 870                                         ainfo->pair_regs [0] = return_regs [*gr];
 871                                 else
 872                                         ainfo->pair_regs [0] = param_regs [*gr];
 873                                 (*gr) ++;
 874                         }
 875                         break;
 876                 case ARG_CLASS_SSE:
 877                         if (*fr >= FLOAT_PARAM_REGS)
 878                                 arg_class = ARG_CLASS_MEMORY;
 879                         else {
 880                                 if (argsize <= 4)
 881                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 882                                 else
 883                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 884                                 ainfo->pair_regs [0] = *fr;
 885                                 (*fr) ++;
 886                         }
 887                         break;
 888                 case ARG_CLASS_MEMORY:
 889                         break;
 890                 default:
 891                         g_assert_not_reached ();
 892                 }
 893
 894                 if (arg_class == ARG_CLASS_MEMORY) {
 895                         /* Revert possible register assignments */
 896                         *gr = orig_gr;
 897                         *fr = orig_fr;
 898
 899                         ainfo->offset = *stack_size;
 900                         *stack_size += sizeof (mgreg_t);
 901                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 902                 }
 903         }
 904 }
 905 #endif /* TARGET_WIN32 */
 906
 907 static void
 908 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 909                            gboolean is_return,
 910                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 911 {
 912 #ifdef TARGET_WIN32
 913         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 914 #else
 915         guint32 size, quad, nquads, i, nfields;
 916         /* Keep track of the size used in each quad so we can */
 917         /* use the right size when copying args/return vars.  */
 918         guint32 quadsize [2] = {8, 8};
 919         ArgumentClass args [2];
 920         MonoMarshalType *info = NULL;
 921         MonoMarshalField *fields = NULL;
 922         MonoClass *klass;
 923         gboolean pass_on_stack = FALSE;
 924
 925         klass = mono_class_from_mono_type (type);
 926         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 927         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 928                 /* We pass and return vtypes of size 8 in a register */
 929         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 930                 pass_on_stack = TRUE;
 931         }
 932
 933         /* If this struct can't be split up naturally into 8-byte */
 934         /* chunks (registers), pass it on the stack.              */
 935         if (sig->pinvoke && !pass_on_stack) {
 936                 guint32 align;
 937                 guint32 field_size;
 938
 939                 info = mono_marshal_load_type_info (klass);
 940                 g_assert (info);
 941
 942                 /*
 943                  * Collect field information recursively to be able to
 944                  * handle nested structures.
 945                  */
 946                 nfields = count_fields_nested (klass);
 947                 fields = g_new0 (MonoMarshalField, nfields);
 948                 collect_field_info_nested (klass, fields, 0, 0);
 949
 950                 for (i = 0; i < nfields; ++i) {
 951                         field_size = mono_marshal_type_size (fields [i].field->type,
 952                                                            fields [i].mspec,
 953                                                            &align, TRUE, klass->unicode);
 954                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 955                                 pass_on_stack = TRUE;
 956                                 break;
 957                         }
 958                 }
 959         }
 960
 961         if (size == 0) {
 962                 ainfo->storage = ArgValuetypeInReg;
 963                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 964                 return;
 965         }
 966
 967         if (pass_on_stack) {
 968                 /* Allways pass in memory */
 969                 ainfo->offset = *stack_size;
 970                 *stack_size += ALIGN_TO (size, 8);
 971                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 972
 973                 g_free (fields);
 974                 return;
 975         }
 976
 977         if (size > 8)
 978                 nquads = 2;
 979         else
 980                 nquads = 1;
 981
 982         if (!sig->pinvoke) {
 983                 int n = mono_class_value_size (klass, NULL);
 984
 985                 quadsize [0] = n >= 8 ? 8 : n;
 986                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 987
 988                 /* Always pass in 1 or 2 integer registers */
 989                 args [0] = ARG_CLASS_INTEGER;
 990                 args [1] = ARG_CLASS_INTEGER;
 991                 /* Only the simplest cases are supported */
 992                 if (is_return && nquads != 1) {
 993                         args [0] = ARG_CLASS_MEMORY;
 994                         args [1] = ARG_CLASS_MEMORY;
 995                 }
 996         } else {
 997                 /*
 998                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 999                  * The X87 and SSEUP stuff is left out since there are no such types in
1000                  * the CLR.
1001                  */
1002                 g_assert (info);
1003
1004                 if (!fields) {
1005                         ainfo->storage = ArgValuetypeInReg;
1006                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1007                         return;
1008                 }
1009
1010                 if (info->native_size > 16) {
1011                         ainfo->offset = *stack_size;
1012                         *stack_size += ALIGN_TO (info->native_size, 8);
1013                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1014
1015                         g_free (fields);
1016                         return;
1017                 }
1018
1019                 args [0] = ARG_CLASS_NO_CLASS;
1020                 args [1] = ARG_CLASS_NO_CLASS;
1021                 for (quad = 0; quad < nquads; ++quad) {
1022                         int size;
1023                         guint32 align;
1024                         ArgumentClass class1;
1025
1026                         if (nfields == 0)
1027                                 class1 = ARG_CLASS_MEMORY;
1028                         else
1029                                 class1 = ARG_CLASS_NO_CLASS;
1030                         for (i = 0; i < nfields; ++i) {
1031                                 size = mono_marshal_type_size (fields [i].field->type,
1032                                                                                            fields [i].mspec,
1033                                                                                            &align, TRUE, klass->unicode);
1034                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
1035                                         /* Unaligned field */
1036                                         NOT_IMPLEMENTED;
1037                                 }
1038
1039                                 /* Skip fields in other quad */
1040                                 if ((quad == 0) && (fields [i].offset >= 8))
1041                                         continue;
1042                                 if ((quad == 1) && (fields [i].offset < 8))
1043                                         continue;
1044
1045                                 /* How far into this quad this data extends.*/
1046                                 /* (8 is size of quad) */
1047                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
1048
1049                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
1050                         }
1051                         g_assert (class1 != ARG_CLASS_NO_CLASS);
1052                         args [quad] = class1;
1053                 }
1054         }
1055
1056         g_free (fields);
1057
1058         /* Post merger cleanup */
1059         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
1060                 args [0] = args [1] = ARG_CLASS_MEMORY;
1061
1062         /* Allocate registers */
1063         {
1064                 int orig_gr = *gr;
1065                 int orig_fr = *fr;
1066
1067                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
1068                         quadsize [0] ++;
1069                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1070                         quadsize [1] ++;
1071
1072                 ainfo->storage = ArgValuetypeInReg;
1073                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1074                 g_assert (quadsize [0] <= 8);
1075                 g_assert (quadsize [1] <= 8);
1076                 ainfo->pair_size [0] = quadsize [0];
1077                 ainfo->pair_size [1] = quadsize [1];
1078                 ainfo->nregs = nquads;
1079                 for (quad = 0; quad < nquads; ++quad) {
1080                         switch (args [quad]) {
1081                         case ARG_CLASS_INTEGER:
1082                                 if (*gr >= PARAM_REGS)
1083                                         args [quad] = ARG_CLASS_MEMORY;
1084                                 else {
1085                                         ainfo->pair_storage [quad] = ArgInIReg;
1086                                         if (is_return)
1087                                                 ainfo->pair_regs [quad] = return_regs [*gr];
1088                                         else
1089                                                 ainfo->pair_regs [quad] = param_regs [*gr];
1090                                         (*gr) ++;
1091                                 }
1092                                 break;
1093                         case ARG_CLASS_SSE:
1094                                 if (*fr >= FLOAT_PARAM_REGS)
1095                                         args [quad] = ARG_CLASS_MEMORY;
1096                                 else {
1097                                         if (quadsize[quad] <= 4)
1098                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
1099                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
1100                                         ainfo->pair_regs [quad] = *fr;
1101                                         (*fr) ++;
1102                                 }
1103                                 break;
1104                         case ARG_CLASS_MEMORY:
1105                                 break;
1106                         default:
1107                                 g_assert_not_reached ();
1108                         }
1109                 }
1110
1111                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
1112                         /* Revert possible register assignments */
1113                         *gr = orig_gr;
1114                         *fr = orig_fr;
1115
1116                         ainfo->offset = *stack_size;
1117                         if (sig->pinvoke)
1118                                 *stack_size += ALIGN_TO (info->native_size, 8);
1119                         else
1120                                 *stack_size += nquads * sizeof(mgreg_t);
1121                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1122                 }
1123         }
1124 #endif /* !TARGET_WIN32 */
1125 }
1126
1127 /*
1128  * get_call_info:
1129  *
1130  *  Obtain information about a call according to the calling convention.
1131  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1132  * Draft Version 0.23" document for more information.
1133  */
1134 static CallInfo*
1135 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1136 {
1137         guint32 i, gr, fr, pstart;
1138         MonoType *ret_type;
1139         int n = sig->hasthis + sig->param_count;
1140         guint32 stack_size = 0;
1141         CallInfo *cinfo;
1142         gboolean is_pinvoke = sig->pinvoke;
1143
1144         if (mp)
1145                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1146         else
1147                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1148
1149         cinfo->nargs = n;
1150
1151         gr = 0;
1152         fr = 0;
1153
1154 #ifdef TARGET_WIN32
1155         /* Reserve space where the callee can save the argument registers */
1156         stack_size = 4 * sizeof (mgreg_t);
1157 #endif
1158
1159         /* return value */
1160         ret_type = mini_get_underlying_type (sig->ret);
1161         switch (ret_type->type) {
1162         case MONO_TYPE_I1:
1163         case MONO_TYPE_U1:
1164         case MONO_TYPE_I2:
1165         case MONO_TYPE_U2:
1166         case MONO_TYPE_I4:
1167         case MONO_TYPE_U4:
1168         case MONO_TYPE_I:
1169         case MONO_TYPE_U:
1170         case MONO_TYPE_PTR:
1171         case MONO_TYPE_FNPTR:
1172         case MONO_TYPE_CLASS:
1173         case MONO_TYPE_OBJECT:
1174         case MONO_TYPE_SZARRAY:
1175         case MONO_TYPE_ARRAY:
1176         case MONO_TYPE_STRING:
1177                 cinfo->ret.storage = ArgInIReg;
1178                 cinfo->ret.reg = AMD64_RAX;
1179                 break;
1180         case MONO_TYPE_U8:
1181         case MONO_TYPE_I8:
1182                 cinfo->ret.storage = ArgInIReg;
1183                 cinfo->ret.reg = AMD64_RAX;
1184                 break;
1185         case MONO_TYPE_R4:
1186                 cinfo->ret.storage = ArgInFloatSSEReg;
1187                 cinfo->ret.reg = AMD64_XMM0;
1188                 break;
1189         case MONO_TYPE_R8:
1190                 cinfo->ret.storage = ArgInDoubleSSEReg;
1191                 cinfo->ret.reg = AMD64_XMM0;
1192                 break;
1193         case MONO_TYPE_GENERICINST:
1194                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1195                         cinfo->ret.storage = ArgInIReg;
1196                         cinfo->ret.reg = AMD64_RAX;
1197                         break;
1198                 }
1199                 if (mini_is_gsharedvt_type (ret_type)) {
1200                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1201                         break;
1202                 }
1203                 /* fall through */
1204         case MONO_TYPE_VALUETYPE:
1205         case MONO_TYPE_TYPEDBYREF: {
1206                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1207
1208                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1209                 g_assert (cinfo->ret.storage != ArgInIReg);
1210                 break;
1211         }
1212         case MONO_TYPE_VAR:
1213         case MONO_TYPE_MVAR:
1214                 g_assert (mini_is_gsharedvt_type (ret_type));
1215                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1216                 break;
1217         case MONO_TYPE_VOID:
1218                 break;
1219         default:
1220                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1221         }
1222
1223         pstart = 0;
1224         /*
1225          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1226          * the first argument, allowing 'this' to be always passed in the first arg reg.
1227          * Also do this if the first argument is a reference type, since virtual calls
1228          * are sometimes made using calli without sig->hasthis set, like in the delegate
1229          * invoke wrappers.
1230          */
1231         if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1232                 if (sig->hasthis) {
1233                         add_general (&gr, &stack_size, cinfo->args + 0);
1234                 } else {
1235                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1236                         pstart = 1;
1237                 }
1238                 add_general (&gr, &stack_size, &cinfo->ret);
1239                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1240                 cinfo->vret_arg_index = 1;
1241         } else {
1242                 /* this */
1243                 if (sig->hasthis)
1244                         add_general (&gr, &stack_size, cinfo->args + 0);
1245
1246                 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1247                         add_general (&gr, &stack_size, &cinfo->ret);
1248                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1249                 }
1250         }
1251
1252         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1253                 gr = PARAM_REGS;
1254                 fr = FLOAT_PARAM_REGS;
1255
1256                 /* Emit the signature cookie just before the implicit arguments */
1257                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1258         }
1259
1260         for (i = pstart; i < sig->param_count; ++i) {
1261                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1262                 MonoType *ptype;
1263
1264 #ifdef TARGET_WIN32
1265                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1266                 if (gr > fr)
1267                         fr = gr;
1268                 else if (fr > gr)
1269                         gr = fr;
1270 #endif
1271
1272                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1273                         /* We allways pass the sig cookie on the stack for simplicity */
1274                         /*
1275                          * Prevent implicit arguments + the sig cookie from being passed
1276                          * in registers.
1277                          */
1278                         gr = PARAM_REGS;
1279                         fr = FLOAT_PARAM_REGS;
1280
1281                         /* Emit the signature cookie just before the implicit arguments */
1282                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1283                 }
1284
1285                 ptype = mini_get_underlying_type (sig->params [i]);
1286                 switch (ptype->type) {
1287                 case MONO_TYPE_I1:
1288                 case MONO_TYPE_U1:
1289                         add_general (&gr, &stack_size, ainfo);
1290                         break;
1291                 case MONO_TYPE_I2:
1292                 case MONO_TYPE_U2:
1293                         add_general (&gr, &stack_size, ainfo);
1294                         break;
1295                 case MONO_TYPE_I4:
1296                 case MONO_TYPE_U4:
1297                         add_general (&gr, &stack_size, ainfo);
1298                         break;
1299                 case MONO_TYPE_I:
1300                 case MONO_TYPE_U:
1301                 case MONO_TYPE_PTR:
1302                 case MONO_TYPE_FNPTR:
1303                 case MONO_TYPE_CLASS:
1304                 case MONO_TYPE_OBJECT:
1305                 case MONO_TYPE_STRING:
1306                 case MONO_TYPE_SZARRAY:
1307                 case MONO_TYPE_ARRAY:
1308                         add_general (&gr, &stack_size, ainfo);
1309                         break;
1310                 case MONO_TYPE_GENERICINST:
1311                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1312                                 add_general (&gr, &stack_size, ainfo);
1313                                 break;
1314                         }
1315                         if (mini_is_gsharedvt_type (ptype)) {
1316                                 /* gsharedvt arguments are passed by ref */
1317                                 add_general (&gr, &stack_size, ainfo);
1318                                 if (ainfo->storage == ArgInIReg)
1319                                         ainfo->storage = ArgGSharedVtInReg;
1320                                 else
1321                                         ainfo->storage = ArgGSharedVtOnStack;
1322                                 break;
1323                         }
1324                         /* fall through */
1325                 case MONO_TYPE_VALUETYPE:
1326                 case MONO_TYPE_TYPEDBYREF:
1327                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1328                         break;
1329                 case MONO_TYPE_U8:
1330
1331                 case MONO_TYPE_I8:
1332                         add_general (&gr, &stack_size, ainfo);
1333                         break;
1334                 case MONO_TYPE_R4:
1335                         add_float (&fr, &stack_size, ainfo, FALSE);
1336                         break;
1337                 case MONO_TYPE_R8:
1338                         add_float (&fr, &stack_size, ainfo, TRUE);
1339                         break;
1340                 case MONO_TYPE_VAR:
1341                 case MONO_TYPE_MVAR:
1342                         /* gsharedvt arguments are passed by ref */
1343                         g_assert (mini_is_gsharedvt_type (ptype));
1344                         add_general (&gr, &stack_size, ainfo);
1345                         if (ainfo->storage == ArgInIReg)
1346                                 ainfo->storage = ArgGSharedVtInReg;
1347                         else
1348                                 ainfo->storage = ArgGSharedVtOnStack;
1349                         break;
1350                 default:
1351                         g_assert_not_reached ();
1352                 }
1353         }
1354
1355         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1356                 gr = PARAM_REGS;
1357                 fr = FLOAT_PARAM_REGS;
1358
1359                 /* Emit the signature cookie just before the implicit arguments */
1360                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1361         }
1362
1363         cinfo->stack_usage = stack_size;
1364         cinfo->reg_usage = gr;
1365         cinfo->freg_usage = fr;
1366         return cinfo;
1367 }
1368
1369 /*
1370  * mono_arch_get_argument_info:
1371  * @csig:  a method signature
1372  * @param_count: the number of parameters to consider
1373  * @arg_info: an array to store the result infos
1374  *
1375  * Gathers information on parameters such as size, alignment and
1376  * padding. arg_info should be large enought to hold param_count + 1 entries.
1377  *
1378  * Returns the size of the argument area on the stack.
1379  */
1380 int
1381 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1382 {
1383         int k;
1384         CallInfo *cinfo = get_call_info (NULL, csig);
1385         guint32 args_size = cinfo->stack_usage;
1386
1387         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1388         if (csig->hasthis) {
1389                 arg_info [0].offset = 0;
1390         }
1391
1392         for (k = 0; k < param_count; k++) {
1393                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1394                 /* FIXME: */
1395                 arg_info [k + 1].size = 0;
1396         }
1397
1398         g_free (cinfo);
1399
1400         return args_size;
1401 }
1402
1403 gboolean
1404 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1405 {
1406         CallInfo *c1, *c2;
1407         gboolean res;
1408         MonoType *callee_ret;
1409
1410         c1 = get_call_info (NULL, caller_sig);
1411         c2 = get_call_info (NULL, callee_sig);
1412         res = c1->stack_usage >= c2->stack_usage;
1413         callee_ret = mini_get_underlying_type (callee_sig->ret);
1414         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1415                 /* An address on the callee's stack is passed as the first argument */
1416                 res = FALSE;
1417
1418         g_free (c1);
1419         g_free (c2);
1420
1421         return res;
1422 }
1423
1424 /*
1425  * Initialize the cpu to execute managed code.
1426  */
1427 void
1428 mono_arch_cpu_init (void)
1429 {
1430 #ifndef _MSC_VER
1431         guint16 fpcw;
1432
1433         /* spec compliance requires running with double precision */
1434         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1435         fpcw &= ~X86_FPCW_PRECC_MASK;
1436         fpcw |= X86_FPCW_PREC_DOUBLE;
1437         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1438         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1439 #else
1440         /* TODO: This is crashing on Win64 right now.
1441         * _control87 (_PC_53, MCW_PC);
1442         */
1443 #endif
1444 }
1445
1446 /*
1447  * Initialize architecture specific code.
1448  */
1449 void
1450 mono_arch_init (void)
1451 {
1452         mono_mutex_init_recursive (&mini_arch_mutex);
1453 #if defined(__native_client_codegen__)
1454         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1455         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1456         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1457         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1458 #endif
1459
1460         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1461         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1462         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1463         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1464
1465         if (!mono_aot_only)
1466                 bp_trampoline = mini_get_breakpoint_trampoline ();
1467 }
1468
1469 /*
1470  * Cleanup architecture specific code.
1471  */
1472 void
1473 mono_arch_cleanup (void)
1474 {
1475         mono_mutex_destroy (&mini_arch_mutex);
1476 #if defined(__native_client_codegen__)
1477         mono_native_tls_free (nacl_instruction_depth);
1478         mono_native_tls_free (nacl_rex_tag);
1479         mono_native_tls_free (nacl_legacy_prefix_tag);
1480 #endif
1481 }
1482
1483 /*
1484  * This function returns the optimizations supported on this cpu.
1485  */
1486 guint32
1487 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1488 {
1489         guint32 opts = 0;
1490
1491         *exclude_mask = 0;
1492
1493         if (mono_hwcap_x86_has_cmov) {
1494                 opts |= MONO_OPT_CMOV;
1495
1496                 if (mono_hwcap_x86_has_fcmov)
1497                         opts |= MONO_OPT_FCMOV;
1498                 else
1499                         *exclude_mask |= MONO_OPT_FCMOV;
1500         } else {
1501                 *exclude_mask |= MONO_OPT_CMOV;
1502         }
1503
1504         return opts;
1505 }
1506
1507 /*
1508  * This function test for all SSE functions supported.
1509  *
1510  * Returns a bitmask corresponding to all supported versions.
1511  *
1512  */
1513 guint32
1514 mono_arch_cpu_enumerate_simd_versions (void)
1515 {
1516         guint32 sse_opts = 0;
1517
1518         if (mono_hwcap_x86_has_sse1)
1519                 sse_opts |= SIMD_VERSION_SSE1;
1520
1521         if (mono_hwcap_x86_has_sse2)
1522                 sse_opts |= SIMD_VERSION_SSE2;
1523
1524         if (mono_hwcap_x86_has_sse3)
1525                 sse_opts |= SIMD_VERSION_SSE3;
1526
1527         if (mono_hwcap_x86_has_ssse3)
1528                 sse_opts |= SIMD_VERSION_SSSE3;
1529
1530         if (mono_hwcap_x86_has_sse41)
1531                 sse_opts |= SIMD_VERSION_SSE41;
1532
1533         if (mono_hwcap_x86_has_sse42)
1534                 sse_opts |= SIMD_VERSION_SSE42;
1535
1536         if (mono_hwcap_x86_has_sse4a)
1537                 sse_opts |= SIMD_VERSION_SSE4a;
1538
1539         return sse_opts;
1540 }
1541
1542 #ifndef DISABLE_JIT
1543
1544 GList *
1545 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1546 {
1547         GList *vars = NULL;
1548         int i;
1549
1550         for (i = 0; i < cfg->num_varinfo; i++) {
1551                 MonoInst *ins = cfg->varinfo [i];
1552                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1553
1554                 /* unused vars */
1555                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1556                         continue;
1557
1558                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1559                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1560                         continue;
1561
1562                 if (mono_is_regsize_var (ins->inst_vtype)) {
1563                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1564                         g_assert (i == vmv->idx);
1565                         vars = g_list_prepend (vars, vmv);
1566                 }
1567         }
1568
1569         vars = mono_varlist_sort (cfg, vars, 0);
1570
1571         return vars;
1572 }
1573
1574 /**
1575  * mono_arch_compute_omit_fp:
1576  *
1577  *   Determine whenever the frame pointer can be eliminated.
1578  */
1579 static void
1580 mono_arch_compute_omit_fp (MonoCompile *cfg)
1581 {
1582         MonoMethodSignature *sig;
1583         MonoMethodHeader *header;
1584         int i, locals_size;
1585         CallInfo *cinfo;
1586
1587         if (cfg->arch.omit_fp_computed)
1588                 return;
1589
1590         header = cfg->header;
1591
1592         sig = mono_method_signature (cfg->method);
1593
1594         if (!cfg->arch.cinfo)
1595                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1596         cinfo = cfg->arch.cinfo;
1597
1598         /*
1599          * FIXME: Remove some of the restrictions.
1600          */
1601         cfg->arch.omit_fp = TRUE;
1602         cfg->arch.omit_fp_computed = TRUE;
1603
1604 #ifdef __native_client_codegen__
1605         /* NaCl modules may not change the value of RBP, so it cannot be */
1606         /* used as a normal register, but it can be used as a frame pointer*/
1607         cfg->disable_omit_fp = TRUE;
1608         cfg->arch.omit_fp = FALSE;
1609 #endif
1610
1611         if (cfg->disable_omit_fp)
1612                 cfg->arch.omit_fp = FALSE;
1613
1614         if (!debug_omit_fp ())
1615                 cfg->arch.omit_fp = FALSE;
1616         /*
1617         if (cfg->method->save_lmf)
1618                 cfg->arch.omit_fp = FALSE;
1619         */
1620         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1621                 cfg->arch.omit_fp = FALSE;
1622         if (header->num_clauses)
1623                 cfg->arch.omit_fp = FALSE;
1624         if (cfg->param_area)
1625                 cfg->arch.omit_fp = FALSE;
1626         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1627                 cfg->arch.omit_fp = FALSE;
1628         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1629                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1630                 cfg->arch.omit_fp = FALSE;
1631         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1632                 ArgInfo *ainfo = &cinfo->args [i];
1633
1634                 if (ainfo->storage == ArgOnStack) {
1635                         /*
1636                          * The stack offset can only be determined when the frame
1637                          * size is known.
1638                          */
1639                         cfg->arch.omit_fp = FALSE;
1640                 }
1641         }
1642
1643         locals_size = 0;
1644         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1645                 MonoInst *ins = cfg->varinfo [i];
1646                 int ialign;
1647
1648                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1649         }
1650 }
1651
1652 GList *
1653 mono_arch_get_global_int_regs (MonoCompile *cfg)
1654 {
1655         GList *regs = NULL;
1656
1657         mono_arch_compute_omit_fp (cfg);
1658
1659         if (cfg->arch.omit_fp)
1660                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1661
1662         /* We use the callee saved registers for global allocation */
1663         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1664         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1665         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1666         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1667 #ifndef __native_client_codegen__
1668         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1669 #endif
1670 #ifdef TARGET_WIN32
1671         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1672         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1673 #endif
1674
1675         return regs;
1676 }
1677
1678 GList*
1679 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1680 {
1681         GList *regs = NULL;
1682         int i;
1683
1684         /* All XMM registers */
1685         for (i = 0; i < 16; ++i)
1686                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1687
1688         return regs;
1689 }
1690
1691 GList*
1692 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1693 {
1694         static GList *r = NULL;
1695
1696         if (r == NULL) {
1697                 GList *regs = NULL;
1698
1699                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1700                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1701                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1702                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1703                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1704 #ifndef __native_client_codegen__
1705                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1706 #endif
1707
1708                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1709                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1710                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1711                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1712                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1713                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1714                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1715                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1716
1717                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1718         }
1719
1720         return r;
1721 }
1722
1723 GList*
1724 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1725 {
1726         int i;
1727         static GList *r = NULL;
1728
1729         if (r == NULL) {
1730                 GList *regs = NULL;
1731
1732                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1733                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1734
1735                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1736         }
1737
1738         return r;
1739 }
1740
1741 /*
1742  * mono_arch_regalloc_cost:
1743  *
1744  *  Return the cost, in number of memory references, of the action of
1745  * allocating the variable VMV into a register during global register
1746  * allocation.
1747  */
1748 guint32
1749 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1750 {
1751         MonoInst *ins = cfg->varinfo [vmv->idx];
1752
1753         if (cfg->method->save_lmf)
1754                 /* The register is already saved */
1755                 /* substract 1 for the invisible store in the prolog */
1756                 return (ins->opcode == OP_ARG) ? 0 : 1;
1757         else
1758                 /* push+pop */
1759                 return (ins->opcode == OP_ARG) ? 1 : 2;
1760 }
1761
1762 /*
1763  * mono_arch_fill_argument_info:
1764  *
1765  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1766  * of the method.
1767  */
1768 void
1769 mono_arch_fill_argument_info (MonoCompile *cfg)
1770 {
1771         MonoType *sig_ret;
1772         MonoMethodSignature *sig;
1773         MonoInst *ins;
1774         int i;
1775         CallInfo *cinfo;
1776
1777         sig = mono_method_signature (cfg->method);
1778
1779         cinfo = cfg->arch.cinfo;
1780         sig_ret = mini_get_underlying_type (sig->ret);
1781
1782         /*
1783          * Contrary to mono_arch_allocate_vars (), the information should describe
1784          * where the arguments are at the beginning of the method, not where they can be
1785          * accessed during the execution of the method. The later makes no sense for the
1786          * global register allocator, since a variable can be in more than one location.
1787          */
1788         switch (cinfo->ret.storage) {
1789         case ArgInIReg:
1790         case ArgInFloatSSEReg:
1791         case ArgInDoubleSSEReg:
1792                 cfg->ret->opcode = OP_REGVAR;
1793                 cfg->ret->inst_c0 = cinfo->ret.reg;
1794                 break;
1795         case ArgValuetypeInReg:
1796                 cfg->ret->opcode = OP_REGOFFSET;
1797                 cfg->ret->inst_basereg = -1;
1798                 cfg->ret->inst_offset = -1;
1799                 break;
1800         case ArgNone:
1801                 break;
1802         default:
1803                 g_assert_not_reached ();
1804         }
1805
1806         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1807                 ArgInfo *ainfo = &cinfo->args [i];
1808
1809                 ins = cfg->args [i];
1810
1811                 switch (ainfo->storage) {
1812                 case ArgInIReg:
1813                 case ArgInFloatSSEReg:
1814                 case ArgInDoubleSSEReg:
1815                         ins->opcode = OP_REGVAR;
1816                         ins->inst_c0 = ainfo->reg;
1817                         break;
1818                 case ArgOnStack:
1819                         ins->opcode = OP_REGOFFSET;
1820                         ins->inst_basereg = -1;
1821                         ins->inst_offset = -1;
1822                         break;
1823                 case ArgValuetypeInReg:
1824                         /* Dummy */
1825                         ins->opcode = OP_NOP;
1826                         break;
1827                 default:
1828                         g_assert_not_reached ();
1829                 }
1830         }
1831 }
1832
1833 void
1834 mono_arch_allocate_vars (MonoCompile *cfg)
1835 {
1836         MonoType *sig_ret;
1837         MonoMethodSignature *sig;
1838         MonoInst *ins;
1839         int i, offset;
1840         guint32 locals_stack_size, locals_stack_align;
1841         gint32 *offsets;
1842         CallInfo *cinfo;
1843
1844         sig = mono_method_signature (cfg->method);
1845
1846         cinfo = cfg->arch.cinfo;
1847         sig_ret = mini_get_underlying_type (sig->ret);
1848
1849         mono_arch_compute_omit_fp (cfg);
1850
1851         /*
1852          * We use the ABI calling conventions for managed code as well.
1853          * Exception: valuetypes are only sometimes passed or returned in registers.
1854          */
1855
1856         /*
1857          * The stack looks like this:
1858          * <incoming arguments passed on the stack>
1859          * <return value>
1860          * <lmf/caller saved registers>
1861          * <locals>
1862          * <spill area>
1863          * <localloc area>  -> grows dynamically
1864          * <params area>
1865          */
1866
1867         if (cfg->arch.omit_fp) {
1868                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1869                 cfg->frame_reg = AMD64_RSP;
1870                 offset = 0;
1871         } else {
1872                 /* Locals are allocated backwards from %fp */
1873                 cfg->frame_reg = AMD64_RBP;
1874                 offset = 0;
1875         }
1876
1877         cfg->arch.saved_iregs = cfg->used_int_regs;
1878         if (cfg->method->save_lmf)
1879                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1880                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1881
1882         if (cfg->arch.omit_fp)
1883                 cfg->arch.reg_save_area_offset = offset;
1884         /* Reserve space for callee saved registers */
1885         for (i = 0; i < AMD64_NREG; ++i)
1886                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1887                         offset += sizeof(mgreg_t);
1888                 }
1889         if (!cfg->arch.omit_fp)
1890                 cfg->arch.reg_save_area_offset = -offset;
1891
1892         if (sig_ret->type != MONO_TYPE_VOID) {
1893                 switch (cinfo->ret.storage) {
1894                 case ArgInIReg:
1895                 case ArgInFloatSSEReg:
1896                 case ArgInDoubleSSEReg:
1897                         cfg->ret->opcode = OP_REGVAR;
1898                         cfg->ret->inst_c0 = cinfo->ret.reg;
1899                         break;
1900                 case ArgValuetypeAddrInIReg:
1901                         /* The register is volatile */
1902                         cfg->vret_addr->opcode = OP_REGOFFSET;
1903                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1904                         if (cfg->arch.omit_fp) {
1905                                 cfg->vret_addr->inst_offset = offset;
1906                                 offset += 8;
1907                         } else {
1908                                 offset += 8;
1909                                 cfg->vret_addr->inst_offset = -offset;
1910                         }
1911                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1912                                 printf ("vret_addr =");
1913                                 mono_print_ins (cfg->vret_addr);
1914                         }
1915                         break;
1916                 case ArgValuetypeInReg:
1917                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1918                         cfg->ret->opcode = OP_REGOFFSET;
1919                         cfg->ret->inst_basereg = cfg->frame_reg;
1920                         if (cfg->arch.omit_fp) {
1921                                 cfg->ret->inst_offset = offset;
1922                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1923                         } else {
1924                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1925                                 cfg->ret->inst_offset = - offset;
1926                         }
1927                         break;
1928                 default:
1929                         g_assert_not_reached ();
1930                 }
1931                 cfg->ret->dreg = cfg->ret->inst_c0;
1932         }
1933
1934         /* Allocate locals */
1935         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1936         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1937                 char *mname = mono_method_full_name (cfg->method, TRUE);
1938                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1939                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1940                 g_free (mname);
1941                 return;
1942         }
1943
1944         if (locals_stack_align) {
1945                 offset += (locals_stack_align - 1);
1946                 offset &= ~(locals_stack_align - 1);
1947         }
1948         if (cfg->arch.omit_fp) {
1949                 cfg->locals_min_stack_offset = offset;
1950                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1951         } else {
1952                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1953                 cfg->locals_max_stack_offset = - offset;
1954         }
1955
1956         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1957                 if (offsets [i] != -1) {
1958                         MonoInst *ins = cfg->varinfo [i];
1959                         ins->opcode = OP_REGOFFSET;
1960                         ins->inst_basereg = cfg->frame_reg;
1961                         if (cfg->arch.omit_fp)
1962                                 ins->inst_offset = (offset + offsets [i]);
1963                         else
1964                                 ins->inst_offset = - (offset + offsets [i]);
1965                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1966                 }
1967         }
1968         offset += locals_stack_size;
1969
1970         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1971                 g_assert (!cfg->arch.omit_fp);
1972                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1973                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1974         }
1975
1976         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1977                 ins = cfg->args [i];
1978                 if (ins->opcode != OP_REGVAR) {
1979                         ArgInfo *ainfo = &cinfo->args [i];
1980                         gboolean inreg = TRUE;
1981
1982                         /* FIXME: Allocate volatile arguments to registers */
1983                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1984                                 inreg = FALSE;
1985
1986                         /*
1987                          * Under AMD64, all registers used to pass arguments to functions
1988                          * are volatile across calls.
1989                          * FIXME: Optimize this.
1990                          */
1991                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1992                                 inreg = FALSE;
1993
1994                         ins->opcode = OP_REGOFFSET;
1995
1996                         switch (ainfo->storage) {
1997                         case ArgInIReg:
1998                         case ArgInFloatSSEReg:
1999                         case ArgInDoubleSSEReg:
2000                         case ArgGSharedVtInReg:
2001                                 if (inreg) {
2002                                         ins->opcode = OP_REGVAR;
2003                                         ins->dreg = ainfo->reg;
2004                                 }
2005                                 break;
2006                         case ArgOnStack:
2007                         case ArgGSharedVtOnStack:
2008                                 g_assert (!cfg->arch.omit_fp);
2009                                 ins->opcode = OP_REGOFFSET;
2010                                 ins->inst_basereg = cfg->frame_reg;
2011                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
2012                                 break;
2013                         case ArgValuetypeInReg:
2014                                 break;
2015                         case ArgValuetypeAddrInIReg: {
2016                                 MonoInst *indir;
2017                                 g_assert (!cfg->arch.omit_fp);
2018
2019                                 MONO_INST_NEW (cfg, indir, 0);
2020                                 indir->opcode = OP_REGOFFSET;
2021                                 if (ainfo->pair_storage [0] == ArgInIReg) {
2022                                         indir->inst_basereg = cfg->frame_reg;
2023                                         offset = ALIGN_TO (offset, sizeof (gpointer));
2024                                         offset += (sizeof (gpointer));
2025                                         indir->inst_offset = - offset;
2026                                 }
2027                                 else {
2028                                         indir->inst_basereg = cfg->frame_reg;
2029                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
2030                                 }
2031
2032                                 ins->opcode = OP_VTARG_ADDR;
2033                                 ins->inst_left = indir;
2034
2035                                 break;
2036                         }
2037                         default:
2038                                 NOT_IMPLEMENTED;
2039                         }
2040
2041                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
2042                                 ins->opcode = OP_REGOFFSET;
2043                                 ins->inst_basereg = cfg->frame_reg;
2044                                 /* These arguments are saved to the stack in the prolog */
2045                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
2046                                 if (cfg->arch.omit_fp) {
2047                                         ins->inst_offset = offset;
2048                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2049                                         // Arguments are yet supported by the stack map creation code
2050                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2051                                 } else {
2052                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2053                                         ins->inst_offset = - offset;
2054                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2055                                 }
2056                         }
2057                 }
2058         }
2059
2060         cfg->stack_offset = offset;
2061 }
2062
2063 void
2064 mono_arch_create_vars (MonoCompile *cfg)
2065 {
2066         MonoMethodSignature *sig;
2067         CallInfo *cinfo;
2068         MonoType *sig_ret;
2069
2070         sig = mono_method_signature (cfg->method);
2071
2072         if (!cfg->arch.cinfo)
2073                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2074         cinfo = cfg->arch.cinfo;
2075
2076         if (cinfo->ret.storage == ArgValuetypeInReg)
2077                 cfg->ret_var_is_local = TRUE;
2078
2079         sig_ret = mini_get_underlying_type (sig->ret);
2080         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2081                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2082                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2083                         printf ("vret_addr = ");
2084                         mono_print_ins (cfg->vret_addr);
2085                 }
2086         }
2087
2088         if (cfg->gen_sdb_seq_points) {
2089                 MonoInst *ins;
2090
2091                 if (cfg->compile_aot) {
2092                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2093                         ins->flags |= MONO_INST_VOLATILE;
2094                         cfg->arch.seq_point_info_var = ins;
2095                 }
2096                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2097                 ins->flags |= MONO_INST_VOLATILE;
2098                 cfg->arch.ss_tramp_var = ins;
2099
2100                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2101                 ins->flags |= MONO_INST_VOLATILE;
2102                 cfg->arch.bp_tramp_var = ins;
2103         }
2104
2105         if (cfg->method->save_lmf)
2106                 cfg->create_lmf_var = TRUE;
2107
2108         if (cfg->method->save_lmf) {
2109                 cfg->lmf_ir = TRUE;
2110 #if !defined(TARGET_WIN32)
2111                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2112                         cfg->lmf_ir_mono_lmf = TRUE;
2113 #endif
2114         }
2115 }
2116
2117 static void
2118 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2119 {
2120         MonoInst *ins;
2121
2122         switch (storage) {
2123         case ArgInIReg:
2124                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2125                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2126                 ins->sreg1 = tree->dreg;
2127                 MONO_ADD_INS (cfg->cbb, ins);
2128                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2129                 break;
2130         case ArgInFloatSSEReg:
2131                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2132                 ins->dreg = mono_alloc_freg (cfg);
2133                 ins->sreg1 = tree->dreg;
2134                 MONO_ADD_INS (cfg->cbb, ins);
2135
2136                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2137                 break;
2138         case ArgInDoubleSSEReg:
2139                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2140                 ins->dreg = mono_alloc_freg (cfg);
2141                 ins->sreg1 = tree->dreg;
2142                 MONO_ADD_INS (cfg->cbb, ins);
2143
2144                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2145
2146                 break;
2147         default:
2148                 g_assert_not_reached ();
2149         }
2150 }
2151
2152 static int
2153 arg_storage_to_load_membase (ArgStorage storage)
2154 {
2155         switch (storage) {
2156         case ArgInIReg:
2157 #if defined(__mono_ilp32__)
2158                 return OP_LOADI8_MEMBASE;
2159 #else
2160                 return OP_LOAD_MEMBASE;
2161 #endif
2162         case ArgInDoubleSSEReg:
2163                 return OP_LOADR8_MEMBASE;
2164         case ArgInFloatSSEReg:
2165                 return OP_LOADR4_MEMBASE;
2166         default:
2167                 g_assert_not_reached ();
2168         }
2169
2170         return -1;
2171 }
2172
2173 static void
2174 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2175 {
2176         MonoMethodSignature *tmp_sig;
2177         int sig_reg;
2178
2179         if (call->tail_call)
2180                 NOT_IMPLEMENTED;
2181
2182         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2183
2184         /*
2185          * mono_ArgIterator_Setup assumes the signature cookie is
2186          * passed first and all the arguments which were before it are
2187          * passed on the stack after the signature. So compensate by
2188          * passing a different signature.
2189          */
2190         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2191         tmp_sig->param_count -= call->signature->sentinelpos;
2192         tmp_sig->sentinelpos = 0;
2193         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2194
2195         sig_reg = mono_alloc_ireg (cfg);
2196         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2197
2198         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2199 }
2200
2201 #ifdef ENABLE_LLVM
2202 static inline LLVMArgStorage
2203 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2204 {
2205         switch (storage) {
2206         case ArgInIReg:
2207                 return LLVMArgInIReg;
2208         case ArgNone:
2209                 return LLVMArgNone;
2210         case ArgGSharedVtInReg:
2211         case ArgGSharedVtOnStack:
2212                 return LLVMArgGSharedVt;
2213         default:
2214                 g_assert_not_reached ();
2215                 return LLVMArgNone;
2216         }
2217 }
2218
2219 LLVMCallInfo*
2220 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2221 {
2222         int i, n;
2223         CallInfo *cinfo;
2224         ArgInfo *ainfo;
2225         int j;
2226         LLVMCallInfo *linfo;
2227         MonoType *t, *sig_ret;
2228
2229         n = sig->param_count + sig->hasthis;
2230         sig_ret = mini_get_underlying_type (sig->ret);
2231
2232         cinfo = get_call_info (cfg->mempool, sig);
2233
2234         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2235
2236         /*
2237          * LLVM always uses the native ABI while we use our own ABI, the
2238          * only difference is the handling of vtypes:
2239          * - we only pass/receive them in registers in some cases, and only
2240          *   in 1 or 2 integer registers.
2241          */
2242         switch (cinfo->ret.storage) {
2243         case ArgNone:
2244                 linfo->ret.storage = LLVMArgNone;
2245                 break;
2246         case ArgInIReg:
2247         case ArgInFloatSSEReg:
2248         case ArgInDoubleSSEReg:
2249                 linfo->ret.storage = LLVMArgNormal;
2250                 break;
2251         case ArgValuetypeInReg:
2252                 if (sig->pinvoke) {
2253                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2254                         cfg->disable_llvm = TRUE;
2255                         return linfo;
2256                 }
2257
2258                 linfo->ret.storage = LLVMArgVtypeInReg;
2259                 for (j = 0; j < 2; ++j)
2260                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2261                 break;
2262         case ArgValuetypeAddrInIReg:
2263                 /* Vtype returned using a hidden argument */
2264                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2265                 linfo->vret_arg_index = cinfo->vret_arg_index;
2266                 break;
2267         default:
2268                 g_assert_not_reached ();
2269                 break;
2270         }
2271
2272         for (i = 0; i < n; ++i) {
2273                 ainfo = cinfo->args + i;
2274
2275                 if (i >= sig->hasthis)
2276                         t = sig->params [i - sig->hasthis];
2277                 else
2278                         t = &mono_defaults.int_class->byval_arg;
2279
2280                 linfo->args [i].storage = LLVMArgNone;
2281
2282                 switch (ainfo->storage) {
2283                 case ArgInIReg:
2284                         linfo->args [i].storage = LLVMArgInIReg;
2285                         break;
2286                 case ArgInDoubleSSEReg:
2287                 case ArgInFloatSSEReg:
2288                         linfo->args [i].storage = LLVMArgInFPReg;
2289                         break;
2290                 case ArgOnStack:
2291                         if (MONO_TYPE_ISSTRUCT (t)) {
2292                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2293                         } else {
2294                                 linfo->args [i].storage = LLVMArgInIReg;
2295                                 if (!t->byref) {
2296                                         if (t->type == MONO_TYPE_R4)
2297                                                 linfo->args [i].storage = LLVMArgInFPReg;
2298                                         else if (t->type == MONO_TYPE_R8)
2299                                                 linfo->args [i].storage = LLVMArgInFPReg;
2300                                 }
2301                         }
2302                         break;
2303                 case ArgValuetypeInReg:
2304                         if (sig->pinvoke) {
2305                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2306                                 cfg->disable_llvm = TRUE;
2307                                 return linfo;
2308                         }
2309
2310                         linfo->args [i].storage = LLVMArgVtypeInReg;
2311                         for (j = 0; j < 2; ++j)
2312                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2313                         break;
2314                 case ArgGSharedVtInReg:
2315                 case ArgGSharedVtOnStack:
2316                         linfo->args [i].storage = LLVMArgGSharedVt;
2317                         break;
2318                 default:
2319                         cfg->exception_message = g_strdup ("ainfo->storage");
2320                         cfg->disable_llvm = TRUE;
2321                         break;
2322                 }
2323         }
2324
2325         return linfo;
2326 }
2327 #endif
2328
2329 void
2330 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2331 {
2332         MonoInst *arg, *in;
2333         MonoMethodSignature *sig;
2334         MonoType *sig_ret;
2335         int i, n;
2336         CallInfo *cinfo;
2337         ArgInfo *ainfo;
2338
2339         sig = call->signature;
2340         n = sig->param_count + sig->hasthis;
2341
2342         cinfo = get_call_info (cfg->mempool, sig);
2343
2344         sig_ret = sig->ret;
2345
2346         if (COMPILE_LLVM (cfg)) {
2347                 /* We shouldn't be called in the llvm case */
2348                 cfg->disable_llvm = TRUE;
2349                 return;
2350         }
2351
2352         /*
2353          * Emit all arguments which are passed on the stack to prevent register
2354          * allocation problems.
2355          */
2356         for (i = 0; i < n; ++i) {
2357                 MonoType *t;
2358                 ainfo = cinfo->args + i;
2359
2360                 in = call->args [i];
2361
2362                 if (sig->hasthis && i == 0)
2363                         t = &mono_defaults.object_class->byval_arg;
2364                 else
2365                         t = sig->params [i - sig->hasthis];
2366
2367                 t = mini_get_underlying_type (t);
2368                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2369                         if (!t->byref) {
2370                                 if (t->type == MONO_TYPE_R4)
2371                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2372                                 else if (t->type == MONO_TYPE_R8)
2373                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2374                                 else
2375                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2376                         } else {
2377                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2378                         }
2379                         if (cfg->compute_gc_maps) {
2380                                 MonoInst *def;
2381
2382                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2383                         }
2384                 }
2385         }
2386
2387         /*
2388          * Emit all parameters passed in registers in non-reverse order for better readability
2389          * and to help the optimization in emit_prolog ().
2390          */
2391         for (i = 0; i < n; ++i) {
2392                 ainfo = cinfo->args + i;
2393
2394                 in = call->args [i];
2395
2396                 if (ainfo->storage == ArgInIReg)
2397                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2398         }
2399
2400         for (i = n - 1; i >= 0; --i) {
2401                 MonoType *t;
2402
2403                 ainfo = cinfo->args + i;
2404
2405                 in = call->args [i];
2406
2407                 if (sig->hasthis && i == 0)
2408                         t = &mono_defaults.object_class->byval_arg;
2409                 else
2410                         t = sig->params [i - sig->hasthis];
2411                 t = mini_get_underlying_type (t);
2412
2413                 switch (ainfo->storage) {
2414                 case ArgInIReg:
2415                         /* Already done */
2416                         break;
2417                 case ArgInFloatSSEReg:
2418                 case ArgInDoubleSSEReg:
2419                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2420                         break;
2421                 case ArgOnStack:
2422                 case ArgValuetypeInReg:
2423                 case ArgValuetypeAddrInIReg:
2424                 case ArgGSharedVtInReg:
2425                 case ArgGSharedVtOnStack: {
2426                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2427                                 /* Already emitted above */
2428                                 break;
2429                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2430                                 MonoInst *call_inst = (MonoInst*)call;
2431                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2432                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2433                                 break;
2434                         }
2435
2436                         guint32 align;
2437                         guint32 size;
2438
2439                         if (sig->pinvoke)
2440                                 size = mono_type_native_stack_size (t, &align);
2441                         else {
2442                                 /*
2443                                  * Other backends use mono_type_stack_size (), but that
2444                                  * aligns the size to 8, which is larger than the size of
2445                                  * the source, leading to reads of invalid memory if the
2446                                  * source is at the end of address space.
2447                                  */
2448                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2449                         }
2450
2451                         if (size >= 10000) {
2452                                 /* Avoid asserts in emit_memcpy () */
2453                                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2454                                 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2455                                 /* Continue normally */
2456                         }
2457
2458                         if (size > 0) {
2459                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2460                                 arg->sreg1 = in->dreg;
2461                                 arg->klass = mono_class_from_mono_type (t);
2462                                 arg->backend.size = size;
2463                                 arg->inst_p0 = call;
2464                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2465                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2466
2467                                 MONO_ADD_INS (cfg->cbb, arg);
2468                         }
2469                         break;
2470                 }
2471                 default:
2472                         g_assert_not_reached ();
2473                 }
2474
2475                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2476                         /* Emit the signature cookie just before the implicit arguments */
2477                         emit_sig_cookie (cfg, call, cinfo);
2478         }
2479
2480         /* Handle the case where there are no implicit arguments */
2481         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2482                 emit_sig_cookie (cfg, call, cinfo);
2483
2484         switch (cinfo->ret.storage) {
2485         case ArgValuetypeInReg:
2486                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2487                         /*
2488                          * Tell the JIT to use a more efficient calling convention: call using
2489                          * OP_CALL, compute the result location after the call, and save the
2490                          * result there.
2491                          */
2492                         call->vret_in_reg = TRUE;
2493                         /*
2494                          * Nullify the instruction computing the vret addr to enable
2495                          * future optimizations.
2496                          */
2497                         if (call->vret_var)
2498                                 NULLIFY_INS (call->vret_var);
2499                 } else {
2500                         if (call->tail_call)
2501                                 NOT_IMPLEMENTED;
2502                         /*
2503                          * The valuetype is in RAX:RDX after the call, need to be copied to
2504                          * the stack. Push the address here, so the call instruction can
2505                          * access it.
2506                          */
2507                         if (!cfg->arch.vret_addr_loc) {
2508                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2509                                 /* Prevent it from being register allocated or optimized away */
2510                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2511                         }
2512
2513                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2514                 }
2515                 break;
2516         case ArgValuetypeAddrInIReg: {
2517                 MonoInst *vtarg;
2518                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2519                 vtarg->sreg1 = call->vret_var->dreg;
2520                 vtarg->dreg = mono_alloc_preg (cfg);
2521                 MONO_ADD_INS (cfg->cbb, vtarg);
2522
2523                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2524                 break;
2525         }
2526         default:
2527                 break;
2528         }
2529
2530         if (cfg->method->save_lmf) {
2531                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2532                 MONO_ADD_INS (cfg->cbb, arg);
2533         }
2534
2535         call->stack_usage = cinfo->stack_usage;
2536 }
2537
2538 void
2539 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2540 {
2541         MonoInst *arg;
2542         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2543         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2544         int size = ins->backend.size;
2545
2546         switch (ainfo->storage) {
2547         case ArgValuetypeInReg: {
2548                 MonoInst *load;
2549                 int part;
2550
2551                 for (part = 0; part < 2; ++part) {
2552                         if (ainfo->pair_storage [part] == ArgNone)
2553                                 continue;
2554
2555                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2556                         load->inst_basereg = src->dreg;
2557                         load->inst_offset = part * sizeof(mgreg_t);
2558
2559                         switch (ainfo->pair_storage [part]) {
2560                         case ArgInIReg:
2561                                 load->dreg = mono_alloc_ireg (cfg);
2562                                 break;
2563                         case ArgInDoubleSSEReg:
2564                         case ArgInFloatSSEReg:
2565                                 load->dreg = mono_alloc_freg (cfg);
2566                                 break;
2567                         default:
2568                                 g_assert_not_reached ();
2569                         }
2570                         MONO_ADD_INS (cfg->cbb, load);
2571
2572                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2573                 }
2574                 break;
2575         }
2576         case ArgValuetypeAddrInIReg: {
2577                 MonoInst *vtaddr, *load;
2578                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2579
2580                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2581                 cfg->has_indirection = TRUE;
2582                 load->inst_p0 = vtaddr;
2583                 vtaddr->flags |= MONO_INST_INDIRECT;
2584                 load->type = STACK_MP;
2585                 load->klass = vtaddr->klass;
2586                 load->dreg = mono_alloc_ireg (cfg);
2587                 MONO_ADD_INS (cfg->cbb, load);
2588                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2589
2590                 if (ainfo->pair_storage [0] == ArgInIReg) {
2591                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2592                         arg->dreg = mono_alloc_ireg (cfg);
2593                         arg->sreg1 = load->dreg;
2594                         arg->inst_imm = 0;
2595                         MONO_ADD_INS (cfg->cbb, arg);
2596                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2597                 } else {
2598                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2599                 }
2600                 break;
2601         }
2602         case ArgGSharedVtInReg:
2603                 /* Pass by addr */
2604                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2605                 break;
2606         case ArgGSharedVtOnStack:
2607                 g_assert_not_reached ();
2608                 break;
2609         default:
2610                 if (size == 8) {
2611                         int dreg = mono_alloc_ireg (cfg);
2612
2613                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2614                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2615                 } else if (size <= 40) {
2616                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2617                 } else {
2618                         // FIXME: Code growth
2619                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2620                 }
2621
2622                 if (cfg->compute_gc_maps) {
2623                         MonoInst *def;
2624                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2625                 }
2626         }
2627 }
2628
2629 void
2630 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2631 {
2632         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2633
2634         if (ret->type == MONO_TYPE_R4) {
2635                 if (COMPILE_LLVM (cfg))
2636                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2637                 else
2638                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2639                 return;
2640         } else if (ret->type == MONO_TYPE_R8) {
2641                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2642                 return;
2643         }
2644
2645         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2646 }
2647
2648 #endif /* DISABLE_JIT */
2649
2650 #define EMIT_COND_BRANCH(ins,cond,sign) \
2651         if (ins->inst_true_bb->native_offset) { \
2652                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2653         } else { \
2654                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2655                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2656             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2657                         x86_branch8 (code, cond, 0, sign); \
2658                 else \
2659                         x86_branch32 (code, cond, 0, sign); \
2660 }
2661
2662 typedef struct {
2663         MonoMethodSignature *sig;
2664         CallInfo *cinfo;
2665 } ArchDynCallInfo;
2666
2667 static gboolean
2668 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2669 {
2670         int i;
2671
2672 #ifdef HOST_WIN32
2673         return FALSE;
2674 #endif
2675
2676         switch (cinfo->ret.storage) {
2677         case ArgNone:
2678         case ArgInIReg:
2679                 break;
2680         case ArgValuetypeInReg: {
2681                 ArgInfo *ainfo = &cinfo->ret;
2682
2683                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2684                         return FALSE;
2685                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2686                         return FALSE;
2687                 break;
2688         }
2689         default:
2690                 return FALSE;
2691         }
2692
2693         for (i = 0; i < cinfo->nargs; ++i) {
2694                 ArgInfo *ainfo = &cinfo->args [i];
2695                 switch (ainfo->storage) {
2696                 case ArgInIReg:
2697                         break;
2698                 case ArgValuetypeInReg:
2699                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2700                                 return FALSE;
2701                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2702                                 return FALSE;
2703                         break;
2704                 default:
2705                         return FALSE;
2706                 }
2707         }
2708
2709         return TRUE;
2710 }
2711
2712 /*
2713  * mono_arch_dyn_call_prepare:
2714  *
2715  *   Return a pointer to an arch-specific structure which contains information
2716  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2717  * supported for SIG.
2718  * This function is equivalent to ffi_prep_cif in libffi.
2719  */
2720 MonoDynCallInfo*
2721 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2722 {
2723         ArchDynCallInfo *info;
2724         CallInfo *cinfo;
2725
2726         cinfo = get_call_info (NULL, sig);
2727
2728         if (!dyn_call_supported (sig, cinfo)) {
2729                 g_free (cinfo);
2730                 return NULL;
2731         }
2732
2733         info = g_new0 (ArchDynCallInfo, 1);
2734         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2735         info->sig = sig;
2736         info->cinfo = cinfo;
2737
2738         return (MonoDynCallInfo*)info;
2739 }
2740
2741 /*
2742  * mono_arch_dyn_call_free:
2743  *
2744  *   Free a MonoDynCallInfo structure.
2745  */
2746 void
2747 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2748 {
2749         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2750
2751         g_free (ainfo->cinfo);
2752         g_free (ainfo);
2753 }
2754
2755 #if !defined(__native_client__)
2756 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2757 #define GREG_TO_PTR(greg) (gpointer)(greg)
2758 #else
2759 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2760 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2761 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2762 #endif
2763
2764 /*
2765  * mono_arch_get_start_dyn_call:
2766  *
2767  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2768  * store the result into BUF.
2769  * ARGS should be an array of pointers pointing to the arguments.
2770  * RET should point to a memory buffer large enought to hold the result of the
2771  * call.
2772  * This function should be as fast as possible, any work which does not depend
2773  * on the actual values of the arguments should be done in
2774  * mono_arch_dyn_call_prepare ().
2775  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2776  * libffi.
2777  */
2778 void
2779 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2780 {
2781         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2782         DynCallArgs *p = (DynCallArgs*)buf;
2783         int arg_index, greg, i, pindex;
2784         MonoMethodSignature *sig = dinfo->sig;
2785
2786         g_assert (buf_len >= sizeof (DynCallArgs));
2787
2788         p->res = 0;
2789         p->ret = ret;
2790
2791         arg_index = 0;
2792         greg = 0;
2793         pindex = 0;
2794
2795         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2796                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2797                 if (!sig->hasthis)
2798                         pindex = 1;
2799         }
2800
2801         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg)
2802                 p->regs [greg ++] = PTR_TO_GREG(ret);
2803
2804         for (i = pindex; i < sig->param_count; i++) {
2805                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2806                 gpointer *arg = args [arg_index ++];
2807
2808                 if (t->byref) {
2809                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2810                         continue;
2811                 }
2812
2813                 switch (t->type) {
2814                 case MONO_TYPE_STRING:
2815                 case MONO_TYPE_CLASS:
2816                 case MONO_TYPE_ARRAY:
2817                 case MONO_TYPE_SZARRAY:
2818                 case MONO_TYPE_OBJECT:
2819                 case MONO_TYPE_PTR:
2820                 case MONO_TYPE_I:
2821                 case MONO_TYPE_U:
2822 #if !defined(__mono_ilp32__)
2823                 case MONO_TYPE_I8:
2824                 case MONO_TYPE_U8:
2825 #endif
2826                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2827                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2828                         break;
2829 #if defined(__mono_ilp32__)
2830                 case MONO_TYPE_I8:
2831                 case MONO_TYPE_U8:
2832                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2833                         p->regs [greg ++] = *(guint64*)(arg);
2834                         break;
2835 #endif
2836                 case MONO_TYPE_U1:
2837                         p->regs [greg ++] = *(guint8*)(arg);
2838                         break;
2839                 case MONO_TYPE_I1:
2840                         p->regs [greg ++] = *(gint8*)(arg);
2841                         break;
2842                 case MONO_TYPE_I2:
2843                         p->regs [greg ++] = *(gint16*)(arg);
2844                         break;
2845                 case MONO_TYPE_U2:
2846                         p->regs [greg ++] = *(guint16*)(arg);
2847                         break;
2848                 case MONO_TYPE_I4:
2849                         p->regs [greg ++] = *(gint32*)(arg);
2850                         break;
2851                 case MONO_TYPE_U4:
2852                         p->regs [greg ++] = *(guint32*)(arg);
2853                         break;
2854                 case MONO_TYPE_GENERICINST:
2855                     if (MONO_TYPE_IS_REFERENCE (t)) {
2856                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2857                                 break;
2858                         } else {
2859                                 /* Fall through */
2860                         }
2861                 case MONO_TYPE_VALUETYPE: {
2862                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2863
2864                         g_assert (ainfo->storage == ArgValuetypeInReg);
2865                         if (ainfo->pair_storage [0] != ArgNone) {
2866                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2867                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2868                         }
2869                         if (ainfo->pair_storage [1] != ArgNone) {
2870                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2871                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2872                         }
2873                         break;
2874                 }
2875                 default:
2876                         g_assert_not_reached ();
2877                 }
2878         }
2879
2880         g_assert (greg <= PARAM_REGS);
2881 }
2882
2883 /*
2884  * mono_arch_finish_dyn_call:
2885  *
2886  *   Store the result of a dyn call into the return value buffer passed to
2887  * start_dyn_call ().
2888  * This function should be as fast as possible, any work which does not depend
2889  * on the actual values of the arguments should be done in
2890  * mono_arch_dyn_call_prepare ().
2891  */
2892 void
2893 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2894 {
2895         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2896         MonoMethodSignature *sig = dinfo->sig;
2897         guint8 *ret = ((DynCallArgs*)buf)->ret;
2898         mgreg_t res = ((DynCallArgs*)buf)->res;
2899         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2900
2901         switch (sig_ret->type) {
2902         case MONO_TYPE_VOID:
2903                 *(gpointer*)ret = NULL;
2904                 break;
2905         case MONO_TYPE_STRING:
2906         case MONO_TYPE_CLASS:
2907         case MONO_TYPE_ARRAY:
2908         case MONO_TYPE_SZARRAY:
2909         case MONO_TYPE_OBJECT:
2910         case MONO_TYPE_I:
2911         case MONO_TYPE_U:
2912         case MONO_TYPE_PTR:
2913                 *(gpointer*)ret = GREG_TO_PTR(res);
2914                 break;
2915         case MONO_TYPE_I1:
2916                 *(gint8*)ret = res;
2917                 break;
2918         case MONO_TYPE_U1:
2919                 *(guint8*)ret = res;
2920                 break;
2921         case MONO_TYPE_I2:
2922                 *(gint16*)ret = res;
2923                 break;
2924         case MONO_TYPE_U2:
2925                 *(guint16*)ret = res;
2926                 break;
2927         case MONO_TYPE_I4:
2928                 *(gint32*)ret = res;
2929                 break;
2930         case MONO_TYPE_U4:
2931                 *(guint32*)ret = res;
2932                 break;
2933         case MONO_TYPE_I8:
2934                 *(gint64*)ret = res;
2935                 break;
2936         case MONO_TYPE_U8:
2937                 *(guint64*)ret = res;
2938                 break;
2939         case MONO_TYPE_GENERICINST:
2940                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2941                         *(gpointer*)ret = GREG_TO_PTR(res);
2942                         break;
2943                 } else {
2944                         /* Fall through */
2945                 }
2946         case MONO_TYPE_VALUETYPE:
2947                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2948                         /* Nothing to do */
2949                 } else {
2950                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2951
2952                         g_assert (ainfo->storage == ArgValuetypeInReg);
2953
2954                         if (ainfo->pair_storage [0] != ArgNone) {
2955                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2956                                 ((mgreg_t*)ret)[0] = res;
2957                         }
2958
2959                         g_assert (ainfo->pair_storage [1] == ArgNone);
2960                 }
2961                 break;
2962         default:
2963                 g_assert_not_reached ();
2964         }
2965 }
2966
2967 /* emit an exception if condition is fail */
2968 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2969         do {                                                        \
2970                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2971                 if (tins == NULL) {                                                                             \
2972                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2973                                         MONO_PATCH_INFO_EXC, exc_name);  \
2974                         x86_branch32 (code, cond, 0, signed);               \
2975                 } else {        \
2976                         EMIT_COND_BRANCH (tins, cond, signed);  \
2977                 }                       \
2978         } while (0);
2979
2980 #define EMIT_FPCOMPARE(code) do { \
2981         amd64_fcompp (code); \
2982         amd64_fnstsw (code); \
2983 } while (0);
2984
2985 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2986     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2987         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2988         amd64_ ##op (code); \
2989         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2990         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2991 } while (0);
2992
2993 static guint8*
2994 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2995 {
2996         gboolean no_patch = FALSE;
2997
2998         /*
2999          * FIXME: Add support for thunks
3000          */
3001         {
3002                 gboolean near_call = FALSE;
3003
3004                 /*
3005                  * Indirect calls are expensive so try to make a near call if possible.
3006                  * The caller memory is allocated by the code manager so it is
3007                  * guaranteed to be at a 32 bit offset.
3008                  */
3009
3010                 if (patch_type != MONO_PATCH_INFO_ABS) {
3011                         /* The target is in memory allocated using the code manager */
3012                         near_call = TRUE;
3013
3014                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3015                                 if (((MonoMethod*)data)->klass->image->aot_module)
3016                                         /* The callee might be an AOT method */
3017                                         near_call = FALSE;
3018                                 if (((MonoMethod*)data)->dynamic)
3019                                         /* The target is in malloc-ed memory */
3020                                         near_call = FALSE;
3021                         }
3022
3023                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3024                                 /*
3025                                  * The call might go directly to a native function without
3026                                  * the wrapper.
3027                                  */
3028                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
3029                                 if (mi) {
3030                                         gconstpointer target = mono_icall_get_wrapper (mi);
3031                                         if ((((guint64)target) >> 32) != 0)
3032                                                 near_call = FALSE;
3033                                 }
3034                         }
3035                 }
3036                 else {
3037                         MonoJumpInfo *jinfo = NULL;
3038
3039                         if (cfg->abs_patches)
3040                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
3041                         if (jinfo) {
3042                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3043                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3044                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3045                                                 near_call = TRUE;
3046                                         no_patch = TRUE;
3047                                 } else {
3048                                         /*
3049                                          * This is not really an optimization, but required because the
3050                                          * generic class init trampolines use R11 to pass the vtable.
3051                                          */
3052                                         near_call = TRUE;
3053                                 }
3054                         } else {
3055                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3056                                 if (info) {
3057                                         if (info->func == info->wrapper) {
3058                                                 /* No wrapper */
3059                                                 if ((((guint64)info->func) >> 32) == 0)
3060                                                         near_call = TRUE;
3061                                         }
3062                                         else {
3063                                                 /* See the comment in mono_codegen () */
3064                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3065                                                         near_call = TRUE;
3066                                         }
3067                                 }
3068                                 else if ((((guint64)data) >> 32) == 0) {
3069                                         near_call = TRUE;
3070                                         no_patch = TRUE;
3071                                 }
3072                         }
3073                 }
3074
3075                 if (cfg->method->dynamic)
3076                         /* These methods are allocated using malloc */
3077                         near_call = FALSE;
3078
3079 #ifdef MONO_ARCH_NOMAP32BIT
3080                 near_call = FALSE;
3081 #endif
3082 #if defined(__native_client__)
3083                 /* Always use near_call == TRUE for Native Client */
3084                 near_call = TRUE;
3085 #endif
3086                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3087                 if (optimize_for_xen)
3088                         near_call = FALSE;
3089
3090                 if (cfg->compile_aot) {
3091                         near_call = TRUE;
3092                         no_patch = TRUE;
3093                 }
3094
3095                 if (near_call) {
3096                         /*
3097                          * Align the call displacement to an address divisible by 4 so it does
3098                          * not span cache lines. This is required for code patching to work on SMP
3099                          * systems.
3100                          */
3101                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3102                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3103                                 amd64_padding (code, pad_size);
3104                         }
3105                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3106                         amd64_call_code (code, 0);
3107                 }
3108                 else {
3109                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3110                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3111                         amd64_call_reg (code, GP_SCRATCH_REG);
3112                 }
3113         }
3114
3115         return code;
3116 }
3117
3118 static inline guint8*
3119 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3120 {
3121 #ifdef TARGET_WIN32
3122         if (win64_adjust_stack)
3123                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3124 #endif
3125         code = emit_call_body (cfg, code, patch_type, data);
3126 #ifdef TARGET_WIN32
3127         if (win64_adjust_stack)
3128                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3129 #endif
3130
3131         return code;
3132 }
3133
3134 static inline int
3135 store_membase_imm_to_store_membase_reg (int opcode)
3136 {
3137         switch (opcode) {
3138         case OP_STORE_MEMBASE_IMM:
3139                 return OP_STORE_MEMBASE_REG;
3140         case OP_STOREI4_MEMBASE_IMM:
3141                 return OP_STOREI4_MEMBASE_REG;
3142         case OP_STOREI8_MEMBASE_IMM:
3143                 return OP_STOREI8_MEMBASE_REG;
3144         }
3145
3146         return -1;
3147 }
3148
3149 #ifndef DISABLE_JIT
3150
3151 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3152
3153 /*
3154  * mono_arch_peephole_pass_1:
3155  *
3156  *   Perform peephole opts which should/can be performed before local regalloc
3157  */
3158 void
3159 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3160 {
3161         MonoInst *ins, *n;
3162
3163         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3164                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3165
3166                 switch (ins->opcode) {
3167                 case OP_ADD_IMM:
3168                 case OP_IADD_IMM:
3169                 case OP_LADD_IMM:
3170                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3171                                 /*
3172                                  * X86_LEA is like ADD, but doesn't have the
3173                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3174                                  * its operand to 64 bit.
3175                                  */
3176                                 ins->opcode = OP_X86_LEA_MEMBASE;
3177                                 ins->inst_basereg = ins->sreg1;
3178                         }
3179                         break;
3180                 case OP_LXOR:
3181                 case OP_IXOR:
3182                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3183                                 MonoInst *ins2;
3184
3185                                 /*
3186                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3187                                  * the latter has length 2-3 instead of 6 (reverse constant
3188                                  * propagation). These instruction sequences are very common
3189                                  * in the initlocals bblock.
3190                                  */
3191                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3192                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3193                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3194                                                 ins2->sreg1 = ins->dreg;
3195                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3196                                                 /* Continue */
3197                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3198                                                 NULLIFY_INS (ins2);
3199                                                 /* Continue */
3200                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3201                                                 /* Continue */
3202                                         } else {
3203                                                 break;
3204                                         }
3205                                 }
3206                         }
3207                         break;
3208                 case OP_COMPARE_IMM:
3209                 case OP_LCOMPARE_IMM:
3210                         /* OP_COMPARE_IMM (reg, 0)
3211                          * -->
3212                          * OP_AMD64_TEST_NULL (reg)
3213                          */
3214                         if (!ins->inst_imm)
3215                                 ins->opcode = OP_AMD64_TEST_NULL;
3216                         break;
3217                 case OP_ICOMPARE_IMM:
3218                         if (!ins->inst_imm)
3219                                 ins->opcode = OP_X86_TEST_NULL;
3220                         break;
3221                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3222                         /*
3223                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3224                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3225                          * -->
3226                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3227                          * OP_COMPARE_IMM reg, imm
3228                          *
3229                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3230                          */
3231                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3232                             ins->inst_basereg == last_ins->inst_destbasereg &&
3233                             ins->inst_offset == last_ins->inst_offset) {
3234                                         ins->opcode = OP_ICOMPARE_IMM;
3235                                         ins->sreg1 = last_ins->sreg1;
3236
3237                                         /* check if we can remove cmp reg,0 with test null */
3238                                         if (!ins->inst_imm)
3239                                                 ins->opcode = OP_X86_TEST_NULL;
3240                                 }
3241
3242                         break;
3243                 }
3244
3245                 mono_peephole_ins (bb, ins);
3246         }
3247 }
3248
3249 void
3250 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3251 {
3252         MonoInst *ins, *n;
3253
3254         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3255                 switch (ins->opcode) {
3256                 case OP_ICONST:
3257                 case OP_I8CONST: {
3258                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3259                         /* reg = 0 -> XOR (reg, reg) */
3260                         /* XOR sets cflags on x86, so we cant do it always */
3261                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3262                                 ins->opcode = OP_LXOR;
3263                                 ins->sreg1 = ins->dreg;
3264                                 ins->sreg2 = ins->dreg;
3265                                 /* Fall through */
3266                         } else {
3267                                 break;
3268                         }
3269                 }
3270                 case OP_LXOR:
3271                         /*
3272                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3273                          * 0 result into 64 bits.
3274                          */
3275                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3276                                 ins->opcode = OP_IXOR;
3277                         }
3278                         /* Fall through */
3279                 case OP_IXOR:
3280                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3281                                 MonoInst *ins2;
3282
3283                                 /*
3284                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3285                                  * the latter has length 2-3 instead of 6 (reverse constant
3286                                  * propagation). These instruction sequences are very common
3287                                  * in the initlocals bblock.
3288                                  */
3289                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3290                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3291                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3292                                                 ins2->sreg1 = ins->dreg;
3293                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3294                                                 /* Continue */
3295                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3296                                                 NULLIFY_INS (ins2);
3297                                                 /* Continue */
3298                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3299                                                 /* Continue */
3300                                         } else {
3301                                                 break;
3302                                         }
3303                                 }
3304                         }
3305                         break;
3306                 case OP_IADD_IMM:
3307                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3308                                 ins->opcode = OP_X86_INC_REG;
3309                         break;
3310                 case OP_ISUB_IMM:
3311                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3312                                 ins->opcode = OP_X86_DEC_REG;
3313                         break;
3314                 }
3315
3316                 mono_peephole_ins (bb, ins);
3317         }
3318 }
3319
3320 #define NEW_INS(cfg,ins,dest,op) do {   \
3321                 MONO_INST_NEW ((cfg), (dest), (op)); \
3322         (dest)->cil_code = (ins)->cil_code; \
3323         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3324         } while (0)
3325
3326 /*
3327  * mono_arch_lowering_pass:
3328  *
3329  *  Converts complex opcodes into simpler ones so that each IR instruction
3330  * corresponds to one machine instruction.
3331  */
3332 void
3333 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3334 {
3335         MonoInst *ins, *n, *temp;
3336
3337         /*
3338          * FIXME: Need to add more instructions, but the current machine
3339          * description can't model some parts of the composite instructions like
3340          * cdq.
3341          */
3342         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3343                 switch (ins->opcode) {
3344                 case OP_DIV_IMM:
3345                 case OP_REM_IMM:
3346                 case OP_IDIV_IMM:
3347                 case OP_IDIV_UN_IMM:
3348                 case OP_IREM_UN_IMM:
3349                 case OP_LREM_IMM:
3350                 case OP_IREM_IMM:
3351                         mono_decompose_op_imm (cfg, bb, ins);
3352                         break;
3353                 case OP_COMPARE_IMM:
3354                 case OP_LCOMPARE_IMM:
3355                         if (!amd64_use_imm32 (ins->inst_imm)) {
3356                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3357                                 temp->inst_c0 = ins->inst_imm;
3358                                 temp->dreg = mono_alloc_ireg (cfg);
3359                                 ins->opcode = OP_COMPARE;
3360                                 ins->sreg2 = temp->dreg;
3361                         }
3362                         break;
3363 #ifndef __mono_ilp32__
3364                 case OP_LOAD_MEMBASE:
3365 #endif
3366                 case OP_LOADI8_MEMBASE:
3367 #ifndef __native_client_codegen__
3368                 /*  Don't generate memindex opcodes (to simplify */
3369                 /*  read sandboxing) */
3370                         if (!amd64_use_imm32 (ins->inst_offset)) {
3371                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3372                                 temp->inst_c0 = ins->inst_offset;
3373                                 temp->dreg = mono_alloc_ireg (cfg);
3374                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3375                                 ins->inst_indexreg = temp->dreg;
3376                         }
3377 #endif
3378                         break;
3379 #ifndef __mono_ilp32__
3380                 case OP_STORE_MEMBASE_IMM:
3381 #endif
3382                 case OP_STOREI8_MEMBASE_IMM:
3383                         if (!amd64_use_imm32 (ins->inst_imm)) {
3384                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3385                                 temp->inst_c0 = ins->inst_imm;
3386                                 temp->dreg = mono_alloc_ireg (cfg);
3387                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3388                                 ins->sreg1 = temp->dreg;
3389                         }
3390                         break;
3391 #ifdef MONO_ARCH_SIMD_INTRINSICS
3392                 case OP_EXPAND_I1: {
3393                                 int temp_reg1 = mono_alloc_ireg (cfg);
3394                                 int temp_reg2 = mono_alloc_ireg (cfg);
3395                                 int original_reg = ins->sreg1;
3396
3397                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3398                                 temp->sreg1 = original_reg;
3399                                 temp->dreg = temp_reg1;
3400
3401                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3402                                 temp->sreg1 = temp_reg1;
3403                                 temp->dreg = temp_reg2;
3404                                 temp->inst_imm = 8;
3405
3406                                 NEW_INS (cfg, ins, temp, OP_LOR);
3407                                 temp->sreg1 = temp->dreg = temp_reg2;
3408                                 temp->sreg2 = temp_reg1;
3409
3410                                 ins->opcode = OP_EXPAND_I2;
3411                                 ins->sreg1 = temp_reg2;
3412                         }
3413                         break;
3414 #endif
3415                 default:
3416                         break;
3417                 }
3418         }
3419
3420         bb->max_vreg = cfg->next_vreg;
3421 }
3422
3423 static const int
3424 branch_cc_table [] = {
3425         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3426         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3427         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3428 };
3429
3430 /* Maps CMP_... constants to X86_CC_... constants */
3431 static const int
3432 cc_table [] = {
3433         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3434         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3435 };
3436
3437 static const int
3438 cc_signed_table [] = {
3439         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3440         FALSE, FALSE, FALSE, FALSE
3441 };
3442
3443 /*#include "cprop.c"*/
3444
3445 static unsigned char*
3446 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3447 {
3448         if (size == 8)
3449                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3450         else
3451                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3452
3453         if (size == 1)
3454                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3455         else if (size == 2)
3456                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3457         return code;
3458 }
3459
3460 static unsigned char*
3461 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3462 {
3463         int sreg = tree->sreg1;
3464         int need_touch = FALSE;
3465
3466 #if defined(TARGET_WIN32)
3467         need_touch = TRUE;
3468 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3469         if (!tree->flags & MONO_INST_INIT)
3470                 need_touch = TRUE;
3471 #endif
3472
3473         if (need_touch) {
3474                 guint8* br[5];
3475
3476                 /*
3477                  * Under Windows:
3478                  * If requested stack size is larger than one page,
3479                  * perform stack-touch operation
3480                  */
3481                 /*
3482                  * Generate stack probe code.
3483                  * Under Windows, it is necessary to allocate one page at a time,
3484                  * "touching" stack after each successful sub-allocation. This is
3485                  * because of the way stack growth is implemented - there is a
3486                  * guard page before the lowest stack page that is currently commited.
3487                  * Stack normally grows sequentially so OS traps access to the
3488                  * guard page and commits more pages when needed.
3489                  */
3490                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3491                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3492
3493                 br[2] = code; /* loop */
3494                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3495                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3496                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3497                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3498                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3499                 amd64_patch (br[3], br[2]);
3500                 amd64_test_reg_reg (code, sreg, sreg);
3501                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3502                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3503
3504                 br[1] = code; x86_jump8 (code, 0);
3505
3506                 amd64_patch (br[0], code);
3507                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3508                 amd64_patch (br[1], code);
3509                 amd64_patch (br[4], code);
3510         }
3511         else
3512                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3513
3514         if (tree->flags & MONO_INST_INIT) {
3515                 int offset = 0;
3516                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3517                         amd64_push_reg (code, AMD64_RAX);
3518                         offset += 8;
3519                 }
3520                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3521                         amd64_push_reg (code, AMD64_RCX);
3522                         offset += 8;
3523                 }
3524                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3525                         amd64_push_reg (code, AMD64_RDI);
3526                         offset += 8;
3527                 }
3528
3529                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3530                 if (sreg != AMD64_RCX)
3531                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3532                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3533
3534                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3535                 if (cfg->param_area)
3536                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3537                 amd64_cld (code);
3538 #if defined(__default_codegen__)
3539                 amd64_prefix (code, X86_REP_PREFIX);
3540                 amd64_stosl (code);
3541 #elif defined(__native_client_codegen__)
3542                 /* NaCl stos pseudo-instruction */
3543                 amd64_codegen_pre(code);
3544                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3545                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3546                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3547                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3548                 amd64_prefix (code, X86_REP_PREFIX);
3549                 amd64_stosl (code);
3550                 amd64_codegen_post(code);
3551 #endif /* __native_client_codegen__ */
3552
3553                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3554                         amd64_pop_reg (code, AMD64_RDI);
3555                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3556                         amd64_pop_reg (code, AMD64_RCX);
3557                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3558                         amd64_pop_reg (code, AMD64_RAX);
3559         }
3560         return code;
3561 }
3562
3563 static guint8*
3564 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3565 {
3566         CallInfo *cinfo;
3567         guint32 quad;
3568
3569         /* Move return value to the target register */
3570         /* FIXME: do this in the local reg allocator */
3571         switch (ins->opcode) {
3572         case OP_CALL:
3573         case OP_CALL_REG:
3574         case OP_CALL_MEMBASE:
3575         case OP_LCALL:
3576         case OP_LCALL_REG:
3577         case OP_LCALL_MEMBASE:
3578                 g_assert (ins->dreg == AMD64_RAX);
3579                 break;
3580         case OP_FCALL:
3581         case OP_FCALL_REG:
3582         case OP_FCALL_MEMBASE: {
3583                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3584                 if (rtype->type == MONO_TYPE_R4) {
3585                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3586                 }
3587                 else {
3588                         if (ins->dreg != AMD64_XMM0)
3589                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3590                 }
3591                 break;
3592         }
3593         case OP_RCALL:
3594         case OP_RCALL_REG:
3595         case OP_RCALL_MEMBASE:
3596                 if (ins->dreg != AMD64_XMM0)
3597                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3598                 break;
3599         case OP_VCALL:
3600         case OP_VCALL_REG:
3601         case OP_VCALL_MEMBASE:
3602         case OP_VCALL2:
3603         case OP_VCALL2_REG:
3604         case OP_VCALL2_MEMBASE:
3605                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3606                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3607                         MonoInst *loc = cfg->arch.vret_addr_loc;
3608
3609                         /* Load the destination address */
3610                         g_assert (loc->opcode == OP_REGOFFSET);
3611                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3612
3613                         for (quad = 0; quad < 2; quad ++) {
3614                                 switch (cinfo->ret.pair_storage [quad]) {
3615                                 case ArgInIReg:
3616                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3617                                         break;
3618                                 case ArgInFloatSSEReg:
3619                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3620                                         break;
3621                                 case ArgInDoubleSSEReg:
3622                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3623                                         break;
3624                                 case ArgNone:
3625                                         break;
3626                                 default:
3627                                         NOT_IMPLEMENTED;
3628                                 }
3629                         }
3630                 }
3631                 break;
3632         }
3633
3634         return code;
3635 }
3636
3637 #endif /* DISABLE_JIT */
3638
3639 #ifdef __APPLE__
3640 static int tls_gs_offset;
3641 #endif
3642
3643 gboolean
3644 mono_amd64_have_tls_get (void)
3645 {
3646 #ifdef TARGET_MACH
3647         static gboolean have_tls_get = FALSE;
3648         static gboolean inited = FALSE;
3649
3650         if (inited)
3651                 return have_tls_get;
3652
3653 #if MONO_HAVE_FAST_TLS
3654         guint8 *ins = (guint8*)pthread_getspecific;
3655
3656         /*
3657          * We're looking for these two instructions:
3658          *
3659          * mov    %gs:[offset](,%rdi,8),%rax
3660          * retq
3661          */
3662         have_tls_get = ins [0] == 0x65 &&
3663                        ins [1] == 0x48 &&
3664                        ins [2] == 0x8b &&
3665                        ins [3] == 0x04 &&
3666                        ins [4] == 0xfd &&
3667                        ins [6] == 0x00 &&
3668                        ins [7] == 0x00 &&
3669                        ins [8] == 0x00 &&
3670                        ins [9] == 0xc3;
3671
3672         tls_gs_offset = ins[5];
3673
3674         /*
3675          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3676          * For that version we're looking for these instructions:
3677          *
3678          * pushq  %rbp
3679          * movq   %rsp, %rbp
3680          * mov    %gs:[offset](,%rdi,8),%rax
3681          * popq   %rbp
3682          * retq
3683          */
3684         if (!have_tls_get) {
3685                 have_tls_get = ins [0] == 0x55 &&
3686                                ins [1] == 0x48 &&
3687                                ins [2] == 0x89 &&
3688                                ins [3] == 0xe5 &&
3689                                ins [4] == 0x65 &&
3690                                ins [5] == 0x48 &&
3691                                ins [6] == 0x8b &&
3692                                ins [7] == 0x04 &&
3693                                ins [8] == 0xfd &&
3694                                ins [10] == 0x00 &&
3695                                ins [11] == 0x00 &&
3696                                ins [12] == 0x00 &&
3697                                ins [13] == 0x5d &&
3698                                ins [14] == 0xc3;
3699
3700                 tls_gs_offset = ins[9];
3701         }
3702 #endif
3703
3704         inited = TRUE;
3705
3706         return have_tls_get;
3707 #elif defined(TARGET_ANDROID)
3708         return FALSE;
3709 #else
3710         return TRUE;
3711 #endif
3712 }
3713
3714 int
3715 mono_amd64_get_tls_gs_offset (void)
3716 {
3717 #ifdef TARGET_OSX
3718         return tls_gs_offset;
3719 #else
3720         g_assert_not_reached ();
3721         return -1;
3722 #endif
3723 }
3724
3725 /*
3726  * mono_amd64_emit_tls_get:
3727  * @code: buffer to store code to
3728  * @dreg: hard register where to place the result
3729  * @tls_offset: offset info
3730  *
3731  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3732  * the dreg register the item in the thread local storage identified
3733  * by tls_offset.
3734  *
3735  * Returns: a pointer to the end of the stored code
3736  */
3737 guint8*
3738 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3739 {
3740 #ifdef TARGET_WIN32
3741         if (tls_offset < 64) {
3742                 x86_prefix (code, X86_GS_PREFIX);
3743                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3744         } else {
3745                 guint8 *buf [16];
3746
3747                 g_assert (tls_offset < 0x440);
3748                 /* Load TEB->TlsExpansionSlots */
3749                 x86_prefix (code, X86_GS_PREFIX);
3750                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3751                 amd64_test_reg_reg (code, dreg, dreg);
3752                 buf [0] = code;
3753                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3754                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3755                 amd64_patch (buf [0], code);
3756         }
3757 #elif defined(__APPLE__)
3758         x86_prefix (code, X86_GS_PREFIX);
3759         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3760 #else
3761         if (optimize_for_xen) {
3762                 x86_prefix (code, X86_FS_PREFIX);
3763                 amd64_mov_reg_mem (code, dreg, 0, 8);
3764                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3765         } else {
3766                 x86_prefix (code, X86_FS_PREFIX);
3767                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3768         }
3769 #endif
3770         return code;
3771 }
3772
3773 static guint8*
3774 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3775 {
3776         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3777 #ifdef TARGET_OSX
3778         if (dreg != offset_reg)
3779                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3780         amd64_prefix (code, X86_GS_PREFIX);
3781         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3782 #elif defined(__linux__)
3783         int tmpreg = -1;
3784
3785         if (dreg == offset_reg) {
3786                 /* Use a temporary reg by saving it to the redzone */
3787                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3788                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3789                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3790                 offset_reg = tmpreg;
3791         }
3792         x86_prefix (code, X86_FS_PREFIX);
3793         amd64_mov_reg_mem (code, dreg, 0, 8);
3794         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3795         if (tmpreg != -1)
3796                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3797 #else
3798         g_assert_not_reached ();
3799 #endif
3800         return code;
3801 }
3802
3803 static guint8*
3804 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3805 {
3806 #ifdef TARGET_WIN32
3807         g_assert_not_reached ();
3808 #elif defined(__APPLE__)
3809         x86_prefix (code, X86_GS_PREFIX);
3810         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3811 #else
3812         g_assert (!optimize_for_xen);
3813         x86_prefix (code, X86_FS_PREFIX);
3814         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3815 #endif
3816         return code;
3817 }
3818
3819 static guint8*
3820 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3821 {
3822         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3823 #ifdef TARGET_WIN32
3824         g_assert_not_reached ();
3825 #elif defined(__APPLE__)
3826         x86_prefix (code, X86_GS_PREFIX);
3827         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3828 #else
3829         x86_prefix (code, X86_FS_PREFIX);
3830         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3831 #endif
3832         return code;
3833 }
3834
3835  /*
3836  * mono_arch_translate_tls_offset:
3837  *
3838  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3839  */
3840 int
3841 mono_arch_translate_tls_offset (int offset)
3842 {
3843 #ifdef __APPLE__
3844         return tls_gs_offset + (offset * 8);
3845 #else
3846         return offset;
3847 #endif
3848 }
3849
3850 /*
3851  * emit_setup_lmf:
3852  *
3853  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3854  */
3855 static guint8*
3856 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3857 {
3858         /*
3859          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3860          */
3861         /*
3862          * sp is saved right before calls but we need to save it here too so
3863          * async stack walks would work.
3864          */
3865         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3866         /* Save rbp */
3867         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3868         if (cfg->arch.omit_fp && cfa_offset != -1)
3869                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3870
3871         /* These can't contain refs */
3872         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3873         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3874         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3875         /* These are handled automatically by the stack marking code */
3876         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3877
3878         return code;
3879 }
3880
3881 #define REAL_PRINT_REG(text,reg) \
3882 mono_assert (reg >= 0); \
3883 amd64_push_reg (code, AMD64_RAX); \
3884 amd64_push_reg (code, AMD64_RDX); \
3885 amd64_push_reg (code, AMD64_RCX); \
3886 amd64_push_reg (code, reg); \
3887 amd64_push_imm (code, reg); \
3888 amd64_push_imm (code, text " %d %p\n"); \
3889 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3890 amd64_call_reg (code, AMD64_RAX); \
3891 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3892 amd64_pop_reg (code, AMD64_RCX); \
3893 amd64_pop_reg (code, AMD64_RDX); \
3894 amd64_pop_reg (code, AMD64_RAX);
3895
3896 /* benchmark and set based on cpu */
3897 #define LOOP_ALIGNMENT 8
3898 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3899
3900 #ifndef DISABLE_JIT
3901 void
3902 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3903 {
3904         MonoInst *ins;
3905         MonoCallInst *call;
3906         guint offset;
3907         guint8 *code = cfg->native_code + cfg->code_len;
3908         int max_len;
3909
3910         /* Fix max_offset estimate for each successor bb */
3911         if (cfg->opt & MONO_OPT_BRANCH) {
3912                 int current_offset = cfg->code_len;
3913                 MonoBasicBlock *current_bb;
3914                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3915                         current_bb->max_offset = current_offset;
3916                         current_offset += current_bb->max_length;
3917                 }
3918         }
3919
3920         if (cfg->opt & MONO_OPT_LOOP) {
3921                 int pad, align = LOOP_ALIGNMENT;
3922                 /* set alignment depending on cpu */
3923                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3924                         pad = align - pad;
3925                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3926                         amd64_padding (code, pad);
3927                         cfg->code_len += pad;
3928                         bb->native_offset = cfg->code_len;
3929                 }
3930         }
3931
3932 #if defined(__native_client_codegen__)
3933         /* For Native Client, all indirect call/jump targets must be */
3934         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3935         /* indirectly as well.                                       */
3936         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3937                                       (bb->flags & BB_EXCEPTION_HANDLER);
3938
3939         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3940                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3941                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3942                 cfg->code_len += pad;
3943                 bb->native_offset = cfg->code_len;
3944         }
3945 #endif  /*__native_client_codegen__*/
3946
3947         if (cfg->verbose_level > 2)
3948                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3949
3950         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3951                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3952                 g_assert (!cfg->compile_aot);
3953
3954                 cov->data [bb->dfn].cil_code = bb->cil_code;
3955                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3956                 /* this is not thread save, but good enough */
3957                 amd64_inc_membase (code, AMD64_R11, 0);
3958         }
3959
3960         offset = code - cfg->native_code;
3961
3962         mono_debug_open_block (cfg, bb, offset);
3963
3964     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3965                 x86_breakpoint (code);
3966
3967         MONO_BB_FOR_EACH_INS (bb, ins) {
3968                 offset = code - cfg->native_code;
3969
3970                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3971
3972 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3973
3974                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3975                         cfg->code_size *= 2;
3976                         cfg->native_code = mono_realloc_native_code(cfg);
3977                         code = cfg->native_code + offset;
3978                         cfg->stat_code_reallocs++;
3979                 }
3980
3981                 if (cfg->debug_info)
3982                         mono_debug_record_line_number (cfg, ins, offset);
3983
3984                 switch (ins->opcode) {
3985                 case OP_BIGMUL:
3986                         amd64_mul_reg (code, ins->sreg2, TRUE);
3987                         break;
3988                 case OP_BIGMUL_UN:
3989                         amd64_mul_reg (code, ins->sreg2, FALSE);
3990                         break;
3991                 case OP_X86_SETEQ_MEMBASE:
3992                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3993                         break;
3994                 case OP_STOREI1_MEMBASE_IMM:
3995                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3996                         break;
3997                 case OP_STOREI2_MEMBASE_IMM:
3998                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3999                         break;
4000                 case OP_STOREI4_MEMBASE_IMM:
4001                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
4002                         break;
4003                 case OP_STOREI1_MEMBASE_REG:
4004                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
4005                         break;
4006                 case OP_STOREI2_MEMBASE_REG:
4007                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4008                         break;
4009                 /* In AMD64 NaCl, pointers are 4 bytes, */
4010                 /*  so STORE_* != STOREI8_*. Likewise below. */
4011                 case OP_STORE_MEMBASE_REG:
4012                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4013                         break;
4014                 case OP_STOREI8_MEMBASE_REG:
4015                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4016                         break;
4017                 case OP_STOREI4_MEMBASE_REG:
4018                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4019                         break;
4020                 case OP_STORE_MEMBASE_IMM:
4021 #ifndef __native_client_codegen__
4022                         /* In NaCl, this could be a PCONST type, which could */
4023                         /* mean a pointer type was copied directly into the  */
4024                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4025                         /* the value would be 0x00000000FFFFFFFF which is    */
4026                         /* not proper for an imm32 unless you cast it.       */
4027                         g_assert (amd64_is_imm32 (ins->inst_imm));
4028 #endif
4029                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4030                         break;
4031                 case OP_STOREI8_MEMBASE_IMM:
4032                         g_assert (amd64_is_imm32 (ins->inst_imm));
4033                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4034                         break;
4035                 case OP_LOAD_MEM:
4036 #ifdef __mono_ilp32__
4037                         /* In ILP32, pointers are 4 bytes, so separate these */
4038                         /* cases, use literal 8 below where we really want 8 */
4039                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4040                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4041                         break;
4042 #endif
4043                 case OP_LOADI8_MEM:
4044                         // FIXME: Decompose this earlier
4045                         if (amd64_use_imm32 (ins->inst_imm))
4046                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4047                         else {
4048                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4049                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4050                         }
4051                         break;
4052                 case OP_LOADI4_MEM:
4053                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4054                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4055                         break;
4056                 case OP_LOADU4_MEM:
4057                         // FIXME: Decompose this earlier
4058                         if (amd64_use_imm32 (ins->inst_imm))
4059                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4060                         else {
4061                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4062                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4063                         }
4064                         break;
4065                 case OP_LOADU1_MEM:
4066                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4067                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4068                         break;
4069                 case OP_LOADU2_MEM:
4070                         /* For NaCl, pointers are 4 bytes, so separate these */
4071                         /* cases, use literal 8 below where we really want 8 */
4072                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4073                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4074                         break;
4075                 case OP_LOAD_MEMBASE:
4076                         g_assert (amd64_is_imm32 (ins->inst_offset));
4077                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4078                         break;
4079                 case OP_LOADI8_MEMBASE:
4080                         /* Use literal 8 instead of sizeof pointer or */
4081                         /* register, we really want 8 for this opcode */
4082                         g_assert (amd64_is_imm32 (ins->inst_offset));
4083                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4084                         break;
4085                 case OP_LOADI4_MEMBASE:
4086                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4087                         break;
4088                 case OP_LOADU4_MEMBASE:
4089                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4090                         break;
4091                 case OP_LOADU1_MEMBASE:
4092                         /* The cpu zero extends the result into 64 bits */
4093                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4094                         break;
4095                 case OP_LOADI1_MEMBASE:
4096                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4097                         break;
4098                 case OP_LOADU2_MEMBASE:
4099                         /* The cpu zero extends the result into 64 bits */
4100                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4101                         break;
4102                 case OP_LOADI2_MEMBASE:
4103                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4104                         break;
4105                 case OP_AMD64_LOADI8_MEMINDEX:
4106                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4107                         break;
4108                 case OP_LCONV_TO_I1:
4109                 case OP_ICONV_TO_I1:
4110                 case OP_SEXT_I1:
4111                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4112                         break;
4113                 case OP_LCONV_TO_I2:
4114                 case OP_ICONV_TO_I2:
4115                 case OP_SEXT_I2:
4116                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4117                         break;
4118                 case OP_LCONV_TO_U1:
4119                 case OP_ICONV_TO_U1:
4120                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4121                         break;
4122                 case OP_LCONV_TO_U2:
4123                 case OP_ICONV_TO_U2:
4124                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4125                         break;
4126                 case OP_ZEXT_I4:
4127                         /* Clean out the upper word */
4128                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4129                         break;
4130                 case OP_SEXT_I4:
4131                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4132                         break;
4133                 case OP_COMPARE:
4134                 case OP_LCOMPARE:
4135                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4136                         break;
4137                 case OP_COMPARE_IMM:
4138 #if defined(__mono_ilp32__)
4139                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4140                         g_assert (amd64_is_imm32 (ins->inst_imm));
4141                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4142                         break;
4143 #endif
4144                 case OP_LCOMPARE_IMM:
4145                         g_assert (amd64_is_imm32 (ins->inst_imm));
4146                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4147                         break;
4148                 case OP_X86_COMPARE_REG_MEMBASE:
4149                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4150                         break;
4151                 case OP_X86_TEST_NULL:
4152                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4153                         break;
4154                 case OP_AMD64_TEST_NULL:
4155                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4156                         break;
4157
4158                 case OP_X86_ADD_REG_MEMBASE:
4159                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4160                         break;
4161                 case OP_X86_SUB_REG_MEMBASE:
4162                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4163                         break;
4164                 case OP_X86_AND_REG_MEMBASE:
4165                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4166                         break;
4167                 case OP_X86_OR_REG_MEMBASE:
4168                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4169                         break;
4170                 case OP_X86_XOR_REG_MEMBASE:
4171                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4172                         break;
4173
4174                 case OP_X86_ADD_MEMBASE_IMM:
4175                         /* FIXME: Make a 64 version too */
4176                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4177                         break;
4178                 case OP_X86_SUB_MEMBASE_IMM:
4179                         g_assert (amd64_is_imm32 (ins->inst_imm));
4180                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4181                         break;
4182                 case OP_X86_AND_MEMBASE_IMM:
4183                         g_assert (amd64_is_imm32 (ins->inst_imm));
4184                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4185                         break;
4186                 case OP_X86_OR_MEMBASE_IMM:
4187                         g_assert (amd64_is_imm32 (ins->inst_imm));
4188                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4189                         break;
4190                 case OP_X86_XOR_MEMBASE_IMM:
4191                         g_assert (amd64_is_imm32 (ins->inst_imm));
4192                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4193                         break;
4194                 case OP_X86_ADD_MEMBASE_REG:
4195                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4196                         break;
4197                 case OP_X86_SUB_MEMBASE_REG:
4198                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4199                         break;
4200                 case OP_X86_AND_MEMBASE_REG:
4201                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4202                         break;
4203                 case OP_X86_OR_MEMBASE_REG:
4204                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4205                         break;
4206                 case OP_X86_XOR_MEMBASE_REG:
4207                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4208                         break;
4209                 case OP_X86_INC_MEMBASE:
4210                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4211                         break;
4212                 case OP_X86_INC_REG:
4213                         amd64_inc_reg_size (code, ins->dreg, 4);
4214                         break;
4215                 case OP_X86_DEC_MEMBASE:
4216                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4217                         break;
4218                 case OP_X86_DEC_REG:
4219                         amd64_dec_reg_size (code, ins->dreg, 4);
4220                         break;
4221                 case OP_X86_MUL_REG_MEMBASE:
4222                 case OP_X86_MUL_MEMBASE_REG:
4223                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4224                         break;
4225                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4226                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4227                         break;
4228                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4229                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4230                         break;
4231                 case OP_AMD64_COMPARE_MEMBASE_REG:
4232                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4233                         break;
4234                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4235                         g_assert (amd64_is_imm32 (ins->inst_imm));
4236                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4237                         break;
4238                 case OP_X86_COMPARE_MEMBASE8_IMM:
4239                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4240                         break;
4241                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4242                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4243                         break;
4244                 case OP_AMD64_COMPARE_REG_MEMBASE:
4245                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4246                         break;
4247
4248                 case OP_AMD64_ADD_REG_MEMBASE:
4249                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4250                         break;
4251                 case OP_AMD64_SUB_REG_MEMBASE:
4252                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4253                         break;
4254                 case OP_AMD64_AND_REG_MEMBASE:
4255                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4256                         break;
4257                 case OP_AMD64_OR_REG_MEMBASE:
4258                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4259                         break;
4260                 case OP_AMD64_XOR_REG_MEMBASE:
4261                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4262                         break;
4263
4264                 case OP_AMD64_ADD_MEMBASE_REG:
4265                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4266                         break;
4267                 case OP_AMD64_SUB_MEMBASE_REG:
4268                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4269                         break;
4270                 case OP_AMD64_AND_MEMBASE_REG:
4271                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4272                         break;
4273                 case OP_AMD64_OR_MEMBASE_REG:
4274                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4275                         break;
4276                 case OP_AMD64_XOR_MEMBASE_REG:
4277                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4278                         break;
4279
4280                 case OP_AMD64_ADD_MEMBASE_IMM:
4281                         g_assert (amd64_is_imm32 (ins->inst_imm));
4282                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4283                         break;
4284                 case OP_AMD64_SUB_MEMBASE_IMM:
4285                         g_assert (amd64_is_imm32 (ins->inst_imm));
4286                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4287                         break;
4288                 case OP_AMD64_AND_MEMBASE_IMM:
4289                         g_assert (amd64_is_imm32 (ins->inst_imm));
4290                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4291                         break;
4292                 case OP_AMD64_OR_MEMBASE_IMM:
4293                         g_assert (amd64_is_imm32 (ins->inst_imm));
4294                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4295                         break;
4296                 case OP_AMD64_XOR_MEMBASE_IMM:
4297                         g_assert (amd64_is_imm32 (ins->inst_imm));
4298                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4299                         break;
4300
4301                 case OP_BREAK:
4302                         amd64_breakpoint (code);
4303                         break;
4304                 case OP_RELAXED_NOP:
4305                         x86_prefix (code, X86_REP_PREFIX);
4306                         x86_nop (code);
4307                         break;
4308                 case OP_HARD_NOP:
4309                         x86_nop (code);
4310                         break;
4311                 case OP_NOP:
4312                 case OP_DUMMY_USE:
4313                 case OP_DUMMY_STORE:
4314                 case OP_DUMMY_ICONST:
4315                 case OP_DUMMY_R8CONST:
4316                 case OP_NOT_REACHED:
4317                 case OP_NOT_NULL:
4318                         break;
4319                 case OP_IL_SEQ_POINT:
4320                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4321                         break;
4322                 case OP_SEQ_POINT: {
4323                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4324                                 MonoInst *var = cfg->arch.ss_tramp_var;
4325                                 guint8 *label;
4326
4327                                 /* Load ss_tramp_var */
4328                                 /* This is equal to &ss_trampoline */
4329                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4330                                 /* Load the trampoline address */
4331                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4332                                 /* Call it if it is non-null */
4333                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4334                                 label = code;
4335                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4336                                 amd64_call_reg (code, AMD64_R11);
4337                                 amd64_patch (label, code);
4338                         }
4339
4340                         /*
4341                          * This is the address which is saved in seq points,
4342                          */
4343                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4344
4345                         if (cfg->compile_aot) {
4346                                 guint32 offset = code - cfg->native_code;
4347                                 guint32 val;
4348                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4349                                 guint8 *label;
4350
4351                                 /* Load info var */
4352                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4353                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4354                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4355                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4356                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4357                                 label = code;
4358                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4359                                 /* Call the trampoline */
4360                                 amd64_call_reg (code, AMD64_R11);
4361                                 amd64_patch (label, code);
4362                         } else {
4363                                 MonoInst *var = cfg->arch.bp_tramp_var;
4364                                 guint8 *label;
4365
4366                                 /*
4367                                  * Emit a test+branch against a constant, the constant will be overwritten
4368                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4369                                  */
4370                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4371                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4372                                 label = code;
4373                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4374
4375                                 g_assert (var);
4376                                 g_assert (var->opcode == OP_REGOFFSET);
4377                                 /* Load bp_tramp_var */
4378                                 /* This is equal to &bp_trampoline */
4379                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4380                                 /* Call the trampoline */
4381                                 amd64_call_membase (code, AMD64_R11, 0);
4382                                 amd64_patch (label, code);
4383                         }
4384                         /*
4385                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4386                          * to another IL offset.
4387                          */
4388                         x86_nop (code);
4389                         break;
4390                 }
4391                 case OP_ADDCC:
4392                 case OP_LADDCC:
4393                 case OP_LADD:
4394                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4395                         break;
4396                 case OP_ADC:
4397                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4398                         break;
4399                 case OP_ADD_IMM:
4400                 case OP_LADD_IMM:
4401                         g_assert (amd64_is_imm32 (ins->inst_imm));
4402                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4403                         break;
4404                 case OP_ADC_IMM:
4405                         g_assert (amd64_is_imm32 (ins->inst_imm));
4406                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4407                         break;
4408                 case OP_SUBCC:
4409                 case OP_LSUBCC:
4410                 case OP_LSUB:
4411                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4412                         break;
4413                 case OP_SBB:
4414                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4415                         break;
4416                 case OP_SUB_IMM:
4417                 case OP_LSUB_IMM:
4418                         g_assert (amd64_is_imm32 (ins->inst_imm));
4419                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4420                         break;
4421                 case OP_SBB_IMM:
4422                         g_assert (amd64_is_imm32 (ins->inst_imm));
4423                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4424                         break;
4425                 case OP_LAND:
4426                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4427                         break;
4428                 case OP_AND_IMM:
4429                 case OP_LAND_IMM:
4430                         g_assert (amd64_is_imm32 (ins->inst_imm));
4431                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4432                         break;
4433                 case OP_LMUL:
4434                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4435                         break;
4436                 case OP_MUL_IMM:
4437                 case OP_LMUL_IMM:
4438                 case OP_IMUL_IMM: {
4439                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4440
4441                         switch (ins->inst_imm) {
4442                         case 2:
4443                                 /* MOV r1, r2 */
4444                                 /* ADD r1, r1 */
4445                                 if (ins->dreg != ins->sreg1)
4446                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4447                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4448                                 break;
4449                         case 3:
4450                                 /* LEA r1, [r2 + r2*2] */
4451                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4452                                 break;
4453                         case 5:
4454                                 /* LEA r1, [r2 + r2*4] */
4455                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4456                                 break;
4457                         case 6:
4458                                 /* LEA r1, [r2 + r2*2] */
4459                                 /* ADD r1, r1          */
4460                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4461                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4462                                 break;
4463                         case 9:
4464                                 /* LEA r1, [r2 + r2*8] */
4465                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4466                                 break;
4467                         case 10:
4468                                 /* LEA r1, [r2 + r2*4] */
4469                                 /* ADD r1, r1          */
4470                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4471                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4472                                 break;
4473                         case 12:
4474                                 /* LEA r1, [r2 + r2*2] */
4475                                 /* SHL r1, 2           */
4476                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4477                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4478                                 break;
4479                         case 25:
4480                                 /* LEA r1, [r2 + r2*4] */
4481                                 /* LEA r1, [r1 + r1*4] */
4482                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4483                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4484                                 break;
4485                         case 100:
4486                                 /* LEA r1, [r2 + r2*4] */
4487                                 /* SHL r1, 2           */
4488                                 /* LEA r1, [r1 + r1*4] */
4489                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4490                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4491                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4492                                 break;
4493                         default:
4494                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4495                                 break;
4496                         }
4497                         break;
4498                 }
4499                 case OP_LDIV:
4500                 case OP_LREM:
4501 #if defined( __native_client_codegen__ )
4502                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4503                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4504 #endif
4505                         /* Regalloc magic makes the div/rem cases the same */
4506                         if (ins->sreg2 == AMD64_RDX) {
4507                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4508                                 amd64_cdq (code);
4509                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4510                         } else {
4511                                 amd64_cdq (code);
4512                                 amd64_div_reg (code, ins->sreg2, TRUE);
4513                         }
4514                         break;
4515                 case OP_LDIV_UN:
4516                 case OP_LREM_UN:
4517 #if defined( __native_client_codegen__ )
4518                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4519                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4520 #endif
4521                         if (ins->sreg2 == AMD64_RDX) {
4522                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4523                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4524                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4525                         } else {
4526                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4527                                 amd64_div_reg (code, ins->sreg2, FALSE);
4528                         }
4529                         break;
4530                 case OP_IDIV:
4531                 case OP_IREM:
4532 #if defined( __native_client_codegen__ )
4533                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4534                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4535 #endif
4536                         if (ins->sreg2 == AMD64_RDX) {
4537                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4538                                 amd64_cdq_size (code, 4);
4539                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4540                         } else {
4541                                 amd64_cdq_size (code, 4);
4542                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4543                         }
4544                         break;
4545                 case OP_IDIV_UN:
4546                 case OP_IREM_UN:
4547 #if defined( __native_client_codegen__ )
4548                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4549                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4550 #endif
4551                         if (ins->sreg2 == AMD64_RDX) {
4552                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4553                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4554                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4555                         } else {
4556                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4557                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4558                         }
4559                         break;
4560                 case OP_LMUL_OVF:
4561                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4562                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4563                         break;
4564                 case OP_LOR:
4565                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4566                         break;
4567                 case OP_OR_IMM:
4568                 case OP_LOR_IMM:
4569                         g_assert (amd64_is_imm32 (ins->inst_imm));
4570                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4571                         break;
4572                 case OP_LXOR:
4573                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4574                         break;
4575                 case OP_XOR_IMM:
4576                 case OP_LXOR_IMM:
4577                         g_assert (amd64_is_imm32 (ins->inst_imm));
4578                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4579                         break;
4580                 case OP_LSHL:
4581                         g_assert (ins->sreg2 == AMD64_RCX);
4582                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4583                         break;
4584                 case OP_LSHR:
4585                         g_assert (ins->sreg2 == AMD64_RCX);
4586                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4587                         break;
4588                 case OP_SHR_IMM:
4589                 case OP_LSHR_IMM:
4590                         g_assert (amd64_is_imm32 (ins->inst_imm));
4591                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4592                         break;
4593                 case OP_SHR_UN_IMM:
4594                         g_assert (amd64_is_imm32 (ins->inst_imm));
4595                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4596                         break;
4597                 case OP_LSHR_UN_IMM:
4598                         g_assert (amd64_is_imm32 (ins->inst_imm));
4599                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4600                         break;
4601                 case OP_LSHR_UN:
4602                         g_assert (ins->sreg2 == AMD64_RCX);
4603                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4604                         break;
4605                 case OP_SHL_IMM:
4606                 case OP_LSHL_IMM:
4607                         g_assert (amd64_is_imm32 (ins->inst_imm));
4608                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4609                         break;
4610
4611                 case OP_IADDCC:
4612                 case OP_IADD:
4613                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4614                         break;
4615                 case OP_IADC:
4616                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4617                         break;
4618                 case OP_IADD_IMM:
4619                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4620                         break;
4621                 case OP_IADC_IMM:
4622                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4623                         break;
4624                 case OP_ISUBCC:
4625                 case OP_ISUB:
4626                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4627                         break;
4628                 case OP_ISBB:
4629                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4630                         break;
4631                 case OP_ISUB_IMM:
4632                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4633                         break;
4634                 case OP_ISBB_IMM:
4635                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4636                         break;
4637                 case OP_IAND:
4638                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4639                         break;
4640                 case OP_IAND_IMM:
4641                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4642                         break;
4643                 case OP_IOR:
4644                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4645                         break;
4646                 case OP_IOR_IMM:
4647                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4648                         break;
4649                 case OP_IXOR:
4650                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4651                         break;
4652                 case OP_IXOR_IMM:
4653                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4654                         break;
4655                 case OP_INEG:
4656                         amd64_neg_reg_size (code, ins->sreg1, 4);
4657                         break;
4658                 case OP_INOT:
4659                         amd64_not_reg_size (code, ins->sreg1, 4);
4660                         break;
4661                 case OP_ISHL:
4662                         g_assert (ins->sreg2 == AMD64_RCX);
4663                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4664                         break;
4665                 case OP_ISHR:
4666                         g_assert (ins->sreg2 == AMD64_RCX);
4667                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4668                         break;
4669                 case OP_ISHR_IMM:
4670                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4671                         break;
4672                 case OP_ISHR_UN_IMM:
4673                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4674                         break;
4675                 case OP_ISHR_UN:
4676                         g_assert (ins->sreg2 == AMD64_RCX);
4677                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4678                         break;
4679                 case OP_ISHL_IMM:
4680                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4681                         break;
4682                 case OP_IMUL:
4683                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4684                         break;
4685                 case OP_IMUL_OVF:
4686                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4687                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4688                         break;
4689                 case OP_IMUL_OVF_UN:
4690                 case OP_LMUL_OVF_UN: {
4691                         /* the mul operation and the exception check should most likely be split */
4692                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4693                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4694                         /*g_assert (ins->sreg2 == X86_EAX);
4695                         g_assert (ins->dreg == X86_EAX);*/
4696                         if (ins->sreg2 == X86_EAX) {
4697                                 non_eax_reg = ins->sreg1;
4698                         } else if (ins->sreg1 == X86_EAX) {
4699                                 non_eax_reg = ins->sreg2;
4700                         } else {
4701                                 /* no need to save since we're going to store to it anyway */
4702                                 if (ins->dreg != X86_EAX) {
4703                                         saved_eax = TRUE;
4704                                         amd64_push_reg (code, X86_EAX);
4705                                 }
4706                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4707                                 non_eax_reg = ins->sreg2;
4708                         }
4709                         if (ins->dreg == X86_EDX) {
4710                                 if (!saved_eax) {
4711                                         saved_eax = TRUE;
4712                                         amd64_push_reg (code, X86_EAX);
4713                                 }
4714                         } else {
4715                                 saved_edx = TRUE;
4716                                 amd64_push_reg (code, X86_EDX);
4717                         }
4718                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4719                         /* save before the check since pop and mov don't change the flags */
4720                         if (ins->dreg != X86_EAX)
4721                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4722                         if (saved_edx)
4723                                 amd64_pop_reg (code, X86_EDX);
4724                         if (saved_eax)
4725                                 amd64_pop_reg (code, X86_EAX);
4726                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4727                         break;
4728                 }
4729                 case OP_ICOMPARE:
4730                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4731                         break;
4732                 case OP_ICOMPARE_IMM:
4733                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4734                         break;
4735                 case OP_IBEQ:
4736                 case OP_IBLT:
4737                 case OP_IBGT:
4738                 case OP_IBGE:
4739                 case OP_IBLE:
4740                 case OP_LBEQ:
4741                 case OP_LBLT:
4742                 case OP_LBGT:
4743                 case OP_LBGE:
4744                 case OP_LBLE:
4745                 case OP_IBNE_UN:
4746                 case OP_IBLT_UN:
4747                 case OP_IBGT_UN:
4748                 case OP_IBGE_UN:
4749                 case OP_IBLE_UN:
4750                 case OP_LBNE_UN:
4751                 case OP_LBLT_UN:
4752                 case OP_LBGT_UN:
4753                 case OP_LBGE_UN:
4754                 case OP_LBLE_UN:
4755                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4756                         break;
4757
4758                 case OP_CMOV_IEQ:
4759                 case OP_CMOV_IGE:
4760                 case OP_CMOV_IGT:
4761                 case OP_CMOV_ILE:
4762                 case OP_CMOV_ILT:
4763                 case OP_CMOV_INE_UN:
4764                 case OP_CMOV_IGE_UN:
4765                 case OP_CMOV_IGT_UN:
4766                 case OP_CMOV_ILE_UN:
4767                 case OP_CMOV_ILT_UN:
4768                 case OP_CMOV_LEQ:
4769                 case OP_CMOV_LGE:
4770                 case OP_CMOV_LGT:
4771                 case OP_CMOV_LLE:
4772                 case OP_CMOV_LLT:
4773                 case OP_CMOV_LNE_UN:
4774                 case OP_CMOV_LGE_UN:
4775                 case OP_CMOV_LGT_UN:
4776                 case OP_CMOV_LLE_UN:
4777                 case OP_CMOV_LLT_UN:
4778                         g_assert (ins->dreg == ins->sreg1);
4779                         /* This needs to operate on 64 bit values */
4780                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4781                         break;
4782
4783                 case OP_LNOT:
4784                         amd64_not_reg (code, ins->sreg1);
4785                         break;
4786                 case OP_LNEG:
4787                         amd64_neg_reg (code, ins->sreg1);
4788                         break;
4789
4790                 case OP_ICONST:
4791                 case OP_I8CONST:
4792                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4793                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4794                         else
4795                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4796                         break;
4797                 case OP_AOTCONST:
4798                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4799                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4800                         break;
4801                 case OP_JUMP_TABLE:
4802                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4803                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4804                         break;
4805                 case OP_MOVE:
4806                         if (ins->dreg != ins->sreg1)
4807                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4808                         break;
4809                 case OP_AMD64_SET_XMMREG_R4: {
4810                         if (cfg->r4fp) {
4811                                 if (ins->dreg != ins->sreg1)
4812                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4813                         } else {
4814                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4815                         }
4816                         break;
4817                 }
4818                 case OP_AMD64_SET_XMMREG_R8: {
4819                         if (ins->dreg != ins->sreg1)
4820                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4821                         break;
4822                 }
4823                 case OP_TAILCALL: {
4824                         MonoCallInst *call = (MonoCallInst*)ins;
4825                         int i, save_area_offset;
4826
4827                         g_assert (!cfg->method->save_lmf);
4828
4829                         /* Restore callee saved registers */
4830                         save_area_offset = cfg->arch.reg_save_area_offset;
4831                         for (i = 0; i < AMD64_NREG; ++i)
4832                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4833                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4834                                         save_area_offset += 8;
4835                                 }
4836
4837                         if (cfg->arch.omit_fp) {
4838                                 if (cfg->arch.stack_alloc_size)
4839                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4840                                 // FIXME:
4841                                 if (call->stack_usage)
4842                                         NOT_IMPLEMENTED;
4843                         } else {
4844                                 /* Copy arguments on the stack to our argument area */
4845                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4846                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4847                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4848                                 }
4849
4850                                 amd64_leave (code);
4851                         }
4852
4853                         offset = code - cfg->native_code;
4854                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4855                         if (cfg->compile_aot)
4856                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4857                         else
4858                                 amd64_set_reg_template (code, AMD64_R11);
4859                         amd64_jump_reg (code, AMD64_R11);
4860                         ins->flags |= MONO_INST_GC_CALLSITE;
4861                         ins->backend.pc_offset = code - cfg->native_code;
4862                         break;
4863                 }
4864                 case OP_CHECK_THIS:
4865                         /* ensure ins->sreg1 is not NULL */
4866                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4867                         break;
4868                 case OP_ARGLIST: {
4869                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4870                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4871                         break;
4872                 }
4873                 case OP_CALL:
4874                 case OP_FCALL:
4875                 case OP_RCALL:
4876                 case OP_LCALL:
4877                 case OP_VCALL:
4878                 case OP_VCALL2:
4879                 case OP_VOIDCALL:
4880                         call = (MonoCallInst*)ins;
4881                         /*
4882                          * The AMD64 ABI forces callers to know about varargs.
4883                          */
4884                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4885                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4886                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4887                                 /*
4888                                  * Since the unmanaged calling convention doesn't contain a
4889                                  * 'vararg' entry, we have to treat every pinvoke call as a
4890                                  * potential vararg call.
4891                                  */
4892                                 guint32 nregs, i;
4893                                 nregs = 0;
4894                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4895                                         if (call->used_fregs & (1 << i))
4896                                                 nregs ++;
4897                                 if (!nregs)
4898                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4899                                 else
4900                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4901                         }
4902
4903                         if (ins->flags & MONO_INST_HAS_METHOD)
4904                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4905                         else
4906                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4907                         ins->flags |= MONO_INST_GC_CALLSITE;
4908                         ins->backend.pc_offset = code - cfg->native_code;
4909                         code = emit_move_return_value (cfg, ins, code);
4910                         break;
4911                 case OP_FCALL_REG:
4912                 case OP_RCALL_REG:
4913                 case OP_LCALL_REG:
4914                 case OP_VCALL_REG:
4915                 case OP_VCALL2_REG:
4916                 case OP_VOIDCALL_REG:
4917                 case OP_CALL_REG:
4918                         call = (MonoCallInst*)ins;
4919
4920                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4921                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4922                                 ins->sreg1 = AMD64_R11;
4923                         }
4924
4925                         /*
4926                          * The AMD64 ABI forces callers to know about varargs.
4927                          */
4928                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4929                                 if (ins->sreg1 == AMD64_RAX) {
4930                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4931                                         ins->sreg1 = AMD64_R11;
4932                                 }
4933                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4934                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4935                                 /*
4936                                  * Since the unmanaged calling convention doesn't contain a
4937                                  * 'vararg' entry, we have to treat every pinvoke call as a
4938                                  * potential vararg call.
4939                                  */
4940                                 guint32 nregs, i;
4941                                 nregs = 0;
4942                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4943                                         if (call->used_fregs & (1 << i))
4944                                                 nregs ++;
4945                                 if (ins->sreg1 == AMD64_RAX) {
4946                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4947                                         ins->sreg1 = AMD64_R11;
4948                                 }
4949                                 if (!nregs)
4950                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4951                                 else
4952                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4953                         }
4954
4955                         amd64_call_reg (code, ins->sreg1);
4956                         ins->flags |= MONO_INST_GC_CALLSITE;
4957                         ins->backend.pc_offset = code - cfg->native_code;
4958                         code = emit_move_return_value (cfg, ins, code);
4959                         break;
4960                 case OP_FCALL_MEMBASE:
4961                 case OP_RCALL_MEMBASE:
4962                 case OP_LCALL_MEMBASE:
4963                 case OP_VCALL_MEMBASE:
4964                 case OP_VCALL2_MEMBASE:
4965                 case OP_VOIDCALL_MEMBASE:
4966                 case OP_CALL_MEMBASE:
4967                         call = (MonoCallInst*)ins;
4968
4969                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4970                         ins->flags |= MONO_INST_GC_CALLSITE;
4971                         ins->backend.pc_offset = code - cfg->native_code;
4972                         code = emit_move_return_value (cfg, ins, code);
4973                         break;
4974                 case OP_DYN_CALL: {
4975                         int i;
4976                         MonoInst *var = cfg->dyn_call_var;
4977
4978                         g_assert (var->opcode == OP_REGOFFSET);
4979
4980                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4981                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4982                         /* r10 = ftn */
4983                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4984
4985                         /* Save args buffer */
4986                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4987
4988                         /* Set argument registers */
4989                         for (i = 0; i < PARAM_REGS; ++i)
4990                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4991
4992                         /* Make the call */
4993                         amd64_call_reg (code, AMD64_R10);
4994
4995                         ins->flags |= MONO_INST_GC_CALLSITE;
4996                         ins->backend.pc_offset = code - cfg->native_code;
4997
4998                         /* Save result */
4999                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5000                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5001                         break;
5002                 }
5003                 case OP_AMD64_SAVE_SP_TO_LMF: {
5004                         MonoInst *lmf_var = cfg->lmf_var;
5005                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5006                         break;
5007                 }
5008                 case OP_X86_PUSH:
5009                         g_assert_not_reached ();
5010                         amd64_push_reg (code, ins->sreg1);
5011                         break;
5012                 case OP_X86_PUSH_IMM:
5013                         g_assert_not_reached ();
5014                         g_assert (amd64_is_imm32 (ins->inst_imm));
5015                         amd64_push_imm (code, ins->inst_imm);
5016                         break;
5017                 case OP_X86_PUSH_MEMBASE:
5018                         g_assert_not_reached ();
5019                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5020                         break;
5021                 case OP_X86_PUSH_OBJ: {
5022                         int size = ALIGN_TO (ins->inst_imm, 8);
5023
5024                         g_assert_not_reached ();
5025
5026                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5027                         amd64_push_reg (code, AMD64_RDI);
5028                         amd64_push_reg (code, AMD64_RSI);
5029                         amd64_push_reg (code, AMD64_RCX);
5030                         if (ins->inst_offset)
5031                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5032                         else
5033                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5034                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5035                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5036                         amd64_cld (code);
5037                         amd64_prefix (code, X86_REP_PREFIX);
5038                         amd64_movsd (code);
5039                         amd64_pop_reg (code, AMD64_RCX);
5040                         amd64_pop_reg (code, AMD64_RSI);
5041                         amd64_pop_reg (code, AMD64_RDI);
5042                         break;
5043                 }
5044                 case OP_GENERIC_CLASS_INIT: {
5045                         static int byte_offset = -1;
5046                         static guint8 bitmask;
5047                         guint8 *jump;
5048
5049                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
5050
5051                         if (byte_offset < 0)
5052                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5053
5054                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
5055                         jump = code;
5056                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
5057
5058                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5059                         ins->flags |= MONO_INST_GC_CALLSITE;
5060                         ins->backend.pc_offset = code - cfg->native_code;
5061
5062                         x86_patch (jump, code);
5063                         break;
5064                 }
5065
5066                 case OP_X86_LEA:
5067                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5068                         break;
5069                 case OP_X86_LEA_MEMBASE:
5070                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5071                         break;
5072                 case OP_X86_XCHG:
5073                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5074                         break;
5075                 case OP_LOCALLOC:
5076                         /* keep alignment */
5077                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5078                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5079                         code = mono_emit_stack_alloc (cfg, code, ins);
5080                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5081                         if (cfg->param_area)
5082                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5083                         break;
5084                 case OP_LOCALLOC_IMM: {
5085                         guint32 size = ins->inst_imm;
5086                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5087
5088                         if (ins->flags & MONO_INST_INIT) {
5089                                 if (size < 64) {
5090                                         int i;
5091
5092                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5093                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5094
5095                                         for (i = 0; i < size; i += 8)
5096                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5097                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5098                                 } else {
5099                                         amd64_mov_reg_imm (code, ins->dreg, size);
5100                                         ins->sreg1 = ins->dreg;
5101
5102                                         code = mono_emit_stack_alloc (cfg, code, ins);
5103                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5104                                 }
5105                         } else {
5106                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5107                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5108                         }
5109                         if (cfg->param_area)
5110                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5111                         break;
5112                 }
5113                 case OP_THROW: {
5114                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5115                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5116                                              (gpointer)"mono_arch_throw_exception", FALSE);
5117                         ins->flags |= MONO_INST_GC_CALLSITE;
5118                         ins->backend.pc_offset = code - cfg->native_code;
5119                         break;
5120                 }
5121                 case OP_RETHROW: {
5122                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5123                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5124                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5125                         ins->flags |= MONO_INST_GC_CALLSITE;
5126                         ins->backend.pc_offset = code - cfg->native_code;
5127                         break;
5128                 }
5129                 case OP_CALL_HANDLER:
5130                         /* Align stack */
5131                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5132                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5133                         amd64_call_imm (code, 0);
5134                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5135                         /* Restore stack alignment */
5136                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5137                         break;
5138                 case OP_START_HANDLER: {
5139                         /* Even though we're saving RSP, use sizeof */
5140                         /* gpointer because spvar is of type IntPtr */
5141                         /* see: mono_create_spvar_for_region */
5142                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5143                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5144
5145                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5146                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5147                                 cfg->param_area) {
5148                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5149                         }
5150                         break;
5151                 }
5152                 case OP_ENDFINALLY: {
5153                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5154                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5155                         amd64_ret (code);
5156                         break;
5157                 }
5158                 case OP_ENDFILTER: {
5159                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5160                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5161                         /* The local allocator will put the result into RAX */
5162                         amd64_ret (code);
5163                         break;
5164                 }
5165                 case OP_GET_EX_OBJ:
5166                         if (ins->dreg != AMD64_RAX)
5167                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5168                         break;
5169                 case OP_LABEL:
5170                         ins->inst_c0 = code - cfg->native_code;
5171                         break;
5172                 case OP_BR:
5173                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5174                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5175                         //break;
5176                                 if (ins->inst_target_bb->native_offset) {
5177                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5178                                 } else {
5179                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5180                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5181                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5182                                                 x86_jump8 (code, 0);
5183                                         else
5184                                                 x86_jump32 (code, 0);
5185                         }
5186                         break;
5187                 case OP_BR_REG:
5188                         amd64_jump_reg (code, ins->sreg1);
5189                         break;
5190                 case OP_ICNEQ:
5191                 case OP_ICGE:
5192                 case OP_ICLE:
5193                 case OP_ICGE_UN:
5194                 case OP_ICLE_UN:
5195
5196                 case OP_CEQ:
5197                 case OP_LCEQ:
5198                 case OP_ICEQ:
5199                 case OP_CLT:
5200                 case OP_LCLT:
5201                 case OP_ICLT:
5202                 case OP_CGT:
5203                 case OP_ICGT:
5204                 case OP_LCGT:
5205                 case OP_CLT_UN:
5206                 case OP_LCLT_UN:
5207                 case OP_ICLT_UN:
5208                 case OP_CGT_UN:
5209                 case OP_LCGT_UN:
5210                 case OP_ICGT_UN:
5211                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5212                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5213                         break;
5214                 case OP_COND_EXC_EQ:
5215                 case OP_COND_EXC_NE_UN:
5216                 case OP_COND_EXC_LT:
5217                 case OP_COND_EXC_LT_UN:
5218                 case OP_COND_EXC_GT:
5219                 case OP_COND_EXC_GT_UN:
5220                 case OP_COND_EXC_GE:
5221                 case OP_COND_EXC_GE_UN:
5222                 case OP_COND_EXC_LE:
5223                 case OP_COND_EXC_LE_UN:
5224                 case OP_COND_EXC_IEQ:
5225                 case OP_COND_EXC_INE_UN:
5226                 case OP_COND_EXC_ILT:
5227                 case OP_COND_EXC_ILT_UN:
5228                 case OP_COND_EXC_IGT:
5229                 case OP_COND_EXC_IGT_UN:
5230                 case OP_COND_EXC_IGE:
5231                 case OP_COND_EXC_IGE_UN:
5232                 case OP_COND_EXC_ILE:
5233                 case OP_COND_EXC_ILE_UN:
5234                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5235                         break;
5236                 case OP_COND_EXC_OV:
5237                 case OP_COND_EXC_NO:
5238                 case OP_COND_EXC_C:
5239                 case OP_COND_EXC_NC:
5240                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5241                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5242                         break;
5243                 case OP_COND_EXC_IOV:
5244                 case OP_COND_EXC_INO:
5245                 case OP_COND_EXC_IC:
5246                 case OP_COND_EXC_INC:
5247                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5248                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5249                         break;
5250
5251                 /* floating point opcodes */
5252                 case OP_R8CONST: {
5253                         double d = *(double *)ins->inst_p0;
5254
5255                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5256                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5257                         }
5258                         else {
5259                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5260                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5261                         }
5262                         break;
5263                 }
5264                 case OP_R4CONST: {
5265                         float f = *(float *)ins->inst_p0;
5266
5267                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5268                                 if (cfg->r4fp)
5269                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5270                                 else
5271                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5272                         }
5273                         else {
5274                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5275                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5276                                 if (!cfg->r4fp)
5277                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5278                         }
5279                         break;
5280                 }
5281                 case OP_STORER8_MEMBASE_REG:
5282                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5283                         break;
5284                 case OP_LOADR8_MEMBASE:
5285                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5286                         break;
5287                 case OP_STORER4_MEMBASE_REG:
5288                         if (cfg->r4fp) {
5289                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5290                         } else {
5291                                 /* This requires a double->single conversion */
5292                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5293                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5294                         }
5295                         break;
5296                 case OP_LOADR4_MEMBASE:
5297                         if (cfg->r4fp) {
5298                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5299                         } else {
5300                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5301                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5302                         }
5303                         break;
5304                 case OP_ICONV_TO_R4:
5305                         if (cfg->r4fp) {
5306                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5307                         } else {
5308                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5309                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5310                         }
5311                         break;
5312                 case OP_ICONV_TO_R8:
5313                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5314                         break;
5315                 case OP_LCONV_TO_R4:
5316                         if (cfg->r4fp) {
5317                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5318                         } else {
5319                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5320                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5321                         }
5322                         break;
5323                 case OP_LCONV_TO_R8:
5324                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5325                         break;
5326                 case OP_FCONV_TO_R4:
5327                         if (cfg->r4fp) {
5328                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5329                         } else {
5330                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5331                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5332                         }
5333                         break;
5334                 case OP_FCONV_TO_I1:
5335                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5336                         break;
5337                 case OP_FCONV_TO_U1:
5338                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5339                         break;
5340                 case OP_FCONV_TO_I2:
5341                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5342                         break;
5343                 case OP_FCONV_TO_U2:
5344                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5345                         break;
5346                 case OP_FCONV_TO_U4:
5347                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5348                         break;
5349                 case OP_FCONV_TO_I4:
5350                 case OP_FCONV_TO_I:
5351                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5352                         break;
5353                 case OP_FCONV_TO_I8:
5354                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5355                         break;
5356
5357                 case OP_RCONV_TO_I1:
5358                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5359                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5360                         break;
5361                 case OP_RCONV_TO_U1:
5362                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5363                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5364                         break;
5365                 case OP_RCONV_TO_I2:
5366                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5367                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5368                         break;
5369                 case OP_RCONV_TO_U2:
5370                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5371                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5372                         break;
5373                 case OP_RCONV_TO_I4:
5374                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5375                         break;
5376                 case OP_RCONV_TO_U4:
5377                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5378                         break;
5379                 case OP_RCONV_TO_I8:
5380                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5381                         break;
5382                 case OP_RCONV_TO_R8:
5383                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5384                         break;
5385                 case OP_RCONV_TO_R4:
5386                         if (ins->dreg != ins->sreg1)
5387                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5388                         break;
5389
5390                 case OP_LCONV_TO_R_UN: {
5391                         guint8 *br [2];
5392
5393                         /* Based on gcc code */
5394                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5395                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5396
5397                         /* Positive case */
5398                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5399                         br [1] = code; x86_jump8 (code, 0);
5400                         amd64_patch (br [0], code);
5401
5402                         /* Negative case */
5403                         /* Save to the red zone */
5404                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5405                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5406                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5407                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5408                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5409                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5410                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5411                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5412                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5413                         /* Restore */
5414                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5415                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5416                         amd64_patch (br [1], code);
5417                         break;
5418                 }
5419                 case OP_LCONV_TO_OVF_U4:
5420                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5421                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5422                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5423                         break;
5424                 case OP_LCONV_TO_OVF_I4_UN:
5425                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5426                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5427                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5428                         break;
5429                 case OP_FMOVE:
5430                         if (ins->dreg != ins->sreg1)
5431                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5432                         break;
5433                 case OP_RMOVE:
5434                         if (ins->dreg != ins->sreg1)
5435                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5436                         break;
5437                 case OP_MOVE_F_TO_I4:
5438                         if (cfg->r4fp) {
5439                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5440                         } else {
5441                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5442                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5443                         }
5444                         break;
5445                 case OP_MOVE_I4_TO_F:
5446                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5447                         if (!cfg->r4fp)
5448                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5449                         break;
5450                 case OP_MOVE_F_TO_I8:
5451                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5452                         break;
5453                 case OP_MOVE_I8_TO_F:
5454                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5455                         break;
5456                 case OP_FADD:
5457                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5458                         break;
5459                 case OP_FSUB:
5460                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5461                         break;
5462                 case OP_FMUL:
5463                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5464                         break;
5465                 case OP_FDIV:
5466                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5467                         break;
5468                 case OP_FNEG: {
5469                         static double r8_0 = -0.0;
5470
5471                         g_assert (ins->sreg1 == ins->dreg);
5472
5473                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5474                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5475                         break;
5476                 }
5477                 case OP_SIN:
5478                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5479                         break;
5480                 case OP_COS:
5481                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5482                         break;
5483                 case OP_ABS: {
5484                         static guint64 d = 0x7fffffffffffffffUL;
5485
5486                         g_assert (ins->sreg1 == ins->dreg);
5487
5488                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5489                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5490                         break;
5491                 }
5492                 case OP_SQRT:
5493                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5494                         break;
5495
5496                 case OP_RADD:
5497                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5498                         break;
5499                 case OP_RSUB:
5500                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5501                         break;
5502                 case OP_RMUL:
5503                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5504                         break;
5505                 case OP_RDIV:
5506                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5507                         break;
5508                 case OP_RNEG: {
5509                         static float r4_0 = -0.0;
5510
5511                         g_assert (ins->sreg1 == ins->dreg);
5512
5513                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5514                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5515                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5516                         break;
5517                 }
5518
5519                 case OP_IMIN:
5520                         g_assert (cfg->opt & MONO_OPT_CMOV);
5521                         g_assert (ins->dreg == ins->sreg1);
5522                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5523                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5524                         break;
5525                 case OP_IMIN_UN:
5526                         g_assert (cfg->opt & MONO_OPT_CMOV);
5527                         g_assert (ins->dreg == ins->sreg1);
5528                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5529                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5530                         break;
5531                 case OP_IMAX:
5532                         g_assert (cfg->opt & MONO_OPT_CMOV);
5533                         g_assert (ins->dreg == ins->sreg1);
5534                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5535                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5536                         break;
5537                 case OP_IMAX_UN:
5538                         g_assert (cfg->opt & MONO_OPT_CMOV);
5539                         g_assert (ins->dreg == ins->sreg1);
5540                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5541                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5542                         break;
5543                 case OP_LMIN:
5544                         g_assert (cfg->opt & MONO_OPT_CMOV);
5545                         g_assert (ins->dreg == ins->sreg1);
5546                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5547                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5548                         break;
5549                 case OP_LMIN_UN:
5550                         g_assert (cfg->opt & MONO_OPT_CMOV);
5551                         g_assert (ins->dreg == ins->sreg1);
5552                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5553                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5554                         break;
5555                 case OP_LMAX:
5556                         g_assert (cfg->opt & MONO_OPT_CMOV);
5557                         g_assert (ins->dreg == ins->sreg1);
5558                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5559                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5560                         break;
5561                 case OP_LMAX_UN:
5562                         g_assert (cfg->opt & MONO_OPT_CMOV);
5563                         g_assert (ins->dreg == ins->sreg1);
5564                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5565                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5566                         break;
5567                 case OP_X86_FPOP:
5568                         break;
5569                 case OP_FCOMPARE:
5570                         /*
5571                          * The two arguments are swapped because the fbranch instructions
5572                          * depend on this for the non-sse case to work.
5573                          */
5574                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5575                         break;
5576                 case OP_RCOMPARE:
5577                         /*
5578                          * FIXME: Get rid of this.
5579                          * The two arguments are swapped because the fbranch instructions
5580                          * depend on this for the non-sse case to work.
5581                          */
5582                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5583                         break;
5584                 case OP_FCNEQ:
5585                 case OP_FCEQ: {
5586                         /* zeroing the register at the start results in
5587                          * shorter and faster code (we can also remove the widening op)
5588                          */
5589                         guchar *unordered_check;
5590
5591                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5592                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5593                         unordered_check = code;
5594                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5595
5596                         if (ins->opcode == OP_FCEQ) {
5597                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5598                                 amd64_patch (unordered_check, code);
5599                         } else {
5600                                 guchar *jump_to_end;
5601                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5602                                 jump_to_end = code;
5603                                 x86_jump8 (code, 0);
5604                                 amd64_patch (unordered_check, code);
5605                                 amd64_inc_reg (code, ins->dreg);
5606                                 amd64_patch (jump_to_end, code);
5607                         }
5608                         break;
5609                 }
5610                 case OP_FCLT:
5611                 case OP_FCLT_UN: {
5612                         /* zeroing the register at the start results in
5613                          * shorter and faster code (we can also remove the widening op)
5614                          */
5615                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5616                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5617                         if (ins->opcode == OP_FCLT_UN) {
5618                                 guchar *unordered_check = code;
5619                                 guchar *jump_to_end;
5620                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5621                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5622                                 jump_to_end = code;
5623                                 x86_jump8 (code, 0);
5624                                 amd64_patch (unordered_check, code);
5625                                 amd64_inc_reg (code, ins->dreg);
5626                                 amd64_patch (jump_to_end, code);
5627                         } else {
5628                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5629                         }
5630                         break;
5631                 }
5632                 case OP_FCLE: {
5633                         guchar *unordered_check;
5634                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5635                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5636                         unordered_check = code;
5637                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5638                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5639                         amd64_patch (unordered_check, code);
5640                         break;
5641                 }
5642                 case OP_FCGT:
5643                 case OP_FCGT_UN: {
5644                         /* zeroing the register at the start results in
5645                          * shorter and faster code (we can also remove the widening op)
5646                          */
5647                         guchar *unordered_check;
5648
5649                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5650                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5651                         if (ins->opcode == OP_FCGT) {
5652                                 unordered_check = code;
5653                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5654                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5655                                 amd64_patch (unordered_check, code);
5656                         } else {
5657                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5658                         }
5659                         break;
5660                 }
5661                 case OP_FCGE: {
5662                         guchar *unordered_check;
5663                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5664                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5665                         unordered_check = code;
5666                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5667                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5668                         amd64_patch (unordered_check, code);
5669                         break;
5670                 }
5671
5672                 case OP_RCEQ:
5673                 case OP_RCGT:
5674                 case OP_RCLT:
5675                 case OP_RCLT_UN:
5676                 case OP_RCGT_UN: {
5677                         int x86_cond;
5678                         gboolean unordered = FALSE;
5679
5680                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5681                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5682
5683                         switch (ins->opcode) {
5684                         case OP_RCEQ:
5685                                 x86_cond = X86_CC_EQ;
5686                                 break;
5687                         case OP_RCGT:
5688                                 x86_cond = X86_CC_LT;
5689                                 break;
5690                         case OP_RCLT:
5691                                 x86_cond = X86_CC_GT;
5692                                 break;
5693                         case OP_RCLT_UN:
5694                                 x86_cond = X86_CC_GT;
5695                                 unordered = TRUE;
5696                                 break;
5697                         case OP_RCGT_UN:
5698                                 x86_cond = X86_CC_LT;
5699                                 unordered = TRUE;
5700                                 break;
5701                         default:
5702                                 g_assert_not_reached ();
5703                                 break;
5704                         }
5705
5706                         if (unordered) {
5707                                 guchar *unordered_check;
5708                                 guchar *jump_to_end;
5709
5710                                 unordered_check = code;
5711                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5712                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5713                                 jump_to_end = code;
5714                                 x86_jump8 (code, 0);
5715                                 amd64_patch (unordered_check, code);
5716                                 amd64_inc_reg (code, ins->dreg);
5717                                 amd64_patch (jump_to_end, code);
5718                         } else {
5719                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5720                         }
5721                         break;
5722                 }
5723                 case OP_FCLT_MEMBASE:
5724                 case OP_FCGT_MEMBASE:
5725                 case OP_FCLT_UN_MEMBASE:
5726                 case OP_FCGT_UN_MEMBASE:
5727                 case OP_FCEQ_MEMBASE: {
5728                         guchar *unordered_check, *jump_to_end;
5729                         int x86_cond;
5730
5731                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5732                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5733
5734                         switch (ins->opcode) {
5735                         case OP_FCEQ_MEMBASE:
5736                                 x86_cond = X86_CC_EQ;
5737                                 break;
5738                         case OP_FCLT_MEMBASE:
5739                         case OP_FCLT_UN_MEMBASE:
5740                                 x86_cond = X86_CC_LT;
5741                                 break;
5742                         case OP_FCGT_MEMBASE:
5743                         case OP_FCGT_UN_MEMBASE:
5744                                 x86_cond = X86_CC_GT;
5745                                 break;
5746                         default:
5747                                 g_assert_not_reached ();
5748                         }
5749
5750                         unordered_check = code;
5751                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5752                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5753
5754                         switch (ins->opcode) {
5755                         case OP_FCEQ_MEMBASE:
5756                         case OP_FCLT_MEMBASE:
5757                         case OP_FCGT_MEMBASE:
5758                                 amd64_patch (unordered_check, code);
5759                                 break;
5760                         case OP_FCLT_UN_MEMBASE:
5761                         case OP_FCGT_UN_MEMBASE:
5762                                 jump_to_end = code;
5763                                 x86_jump8 (code, 0);
5764                                 amd64_patch (unordered_check, code);
5765                                 amd64_inc_reg (code, ins->dreg);
5766                                 amd64_patch (jump_to_end, code);
5767                                 break;
5768                         default:
5769                                 break;
5770                         }
5771                         break;
5772                 }
5773                 case OP_FBEQ: {
5774                         guchar *jump = code;
5775                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5776                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5777                         amd64_patch (jump, code);
5778                         break;
5779                 }
5780                 case OP_FBNE_UN:
5781                         /* Branch if C013 != 100 */
5782                         /* branch if !ZF or (PF|CF) */
5783                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5784                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5785                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5786                         break;
5787                 case OP_FBLT:
5788                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5789                         break;
5790                 case OP_FBLT_UN:
5791                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5792                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5793                         break;
5794                 case OP_FBGT:
5795                 case OP_FBGT_UN:
5796                         if (ins->opcode == OP_FBGT) {
5797                                 guchar *br1;
5798
5799                                 /* skip branch if C1=1 */
5800                                 br1 = code;
5801                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5802                                 /* branch if (C0 | C3) = 1 */
5803                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5804                                 amd64_patch (br1, code);
5805                                 break;
5806                         } else {
5807                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5808                         }
5809                         break;
5810                 case OP_FBGE: {
5811                         /* Branch if C013 == 100 or 001 */
5812                         guchar *br1;
5813
5814                         /* skip branch if C1=1 */
5815                         br1 = code;
5816                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5817                         /* branch if (C0 | C3) = 1 */
5818                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5819                         amd64_patch (br1, code);
5820                         break;
5821                 }
5822                 case OP_FBGE_UN:
5823                         /* Branch if C013 == 000 */
5824                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5825                         break;
5826                 case OP_FBLE: {
5827                         /* Branch if C013=000 or 100 */
5828                         guchar *br1;
5829
5830                         /* skip branch if C1=1 */
5831                         br1 = code;
5832                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5833                         /* branch if C0=0 */
5834                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5835                         amd64_patch (br1, code);
5836                         break;
5837                 }
5838                 case OP_FBLE_UN:
5839                         /* Branch if C013 != 001 */
5840                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5841                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5842                         break;
5843                 case OP_CKFINITE:
5844                         /* Transfer value to the fp stack */
5845                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5846                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5847                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5848
5849                         amd64_push_reg (code, AMD64_RAX);
5850                         amd64_fxam (code);
5851                         amd64_fnstsw (code);
5852                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5853                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5854                         amd64_pop_reg (code, AMD64_RAX);
5855                         amd64_fstp (code, 0);
5856                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5857                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5858                         break;
5859                 case OP_TLS_GET: {
5860                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5861                         break;
5862                 }
5863                 case OP_TLS_GET_REG:
5864                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5865                         break;
5866                 case OP_TLS_SET: {
5867                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5868                         break;
5869                 }
5870                 case OP_TLS_SET_REG: {
5871                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5872                         break;
5873                 }
5874                 case OP_MEMORY_BARRIER: {
5875                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5876                                 x86_mfence (code);
5877                         break;
5878                 }
5879                 case OP_ATOMIC_ADD_I4:
5880                 case OP_ATOMIC_ADD_I8: {
5881                         int dreg = ins->dreg;
5882                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5883
5884                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5885                                 dreg = AMD64_R11;
5886
5887                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5888                         amd64_prefix (code, X86_LOCK_PREFIX);
5889                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5890                         /* dreg contains the old value, add with sreg2 value */
5891                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5892
5893                         if (ins->dreg != dreg)
5894                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5895
5896                         break;
5897                 }
5898                 case OP_ATOMIC_EXCHANGE_I4:
5899                 case OP_ATOMIC_EXCHANGE_I8: {
5900                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5901
5902                         /* LOCK prefix is implied. */
5903                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5904                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5905                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5906                         break;
5907                 }
5908                 case OP_ATOMIC_CAS_I4:
5909                 case OP_ATOMIC_CAS_I8: {
5910                         guint32 size;
5911
5912                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5913                                 size = 8;
5914                         else
5915                                 size = 4;
5916
5917                         /*
5918                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5919                          * an explanation of how this works.
5920                          */
5921                         g_assert (ins->sreg3 == AMD64_RAX);
5922                         g_assert (ins->sreg1 != AMD64_RAX);
5923                         g_assert (ins->sreg1 != ins->sreg2);
5924
5925                         amd64_prefix (code, X86_LOCK_PREFIX);
5926                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5927
5928                         if (ins->dreg != AMD64_RAX)
5929                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5930                         break;
5931                 }
5932                 case OP_ATOMIC_LOAD_I1: {
5933                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5934                         break;
5935                 }
5936                 case OP_ATOMIC_LOAD_U1: {
5937                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5938                         break;
5939                 }
5940                 case OP_ATOMIC_LOAD_I2: {
5941                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5942                         break;
5943                 }
5944                 case OP_ATOMIC_LOAD_U2: {
5945                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5946                         break;
5947                 }
5948                 case OP_ATOMIC_LOAD_I4: {
5949                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5950                         break;
5951                 }
5952                 case OP_ATOMIC_LOAD_U4:
5953                 case OP_ATOMIC_LOAD_I8:
5954                 case OP_ATOMIC_LOAD_U8: {
5955                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5956                         break;
5957                 }
5958                 case OP_ATOMIC_LOAD_R4: {
5959                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5960                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5961                         break;
5962                 }
5963                 case OP_ATOMIC_LOAD_R8: {
5964                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5965                         break;
5966                 }
5967                 case OP_ATOMIC_STORE_I1:
5968                 case OP_ATOMIC_STORE_U1:
5969                 case OP_ATOMIC_STORE_I2:
5970                 case OP_ATOMIC_STORE_U2:
5971                 case OP_ATOMIC_STORE_I4:
5972                 case OP_ATOMIC_STORE_U4:
5973                 case OP_ATOMIC_STORE_I8:
5974                 case OP_ATOMIC_STORE_U8: {
5975                         int size;
5976
5977                         switch (ins->opcode) {
5978                         case OP_ATOMIC_STORE_I1:
5979                         case OP_ATOMIC_STORE_U1:
5980                                 size = 1;
5981                                 break;
5982                         case OP_ATOMIC_STORE_I2:
5983                         case OP_ATOMIC_STORE_U2:
5984                                 size = 2;
5985                                 break;
5986                         case OP_ATOMIC_STORE_I4:
5987                         case OP_ATOMIC_STORE_U4:
5988                                 size = 4;
5989                                 break;
5990                         case OP_ATOMIC_STORE_I8:
5991                         case OP_ATOMIC_STORE_U8:
5992                                 size = 8;
5993                                 break;
5994                         }
5995
5996                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5997
5998                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5999                                 x86_mfence (code);
6000                         break;
6001                 }
6002                 case OP_ATOMIC_STORE_R4: {
6003                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6004                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6005
6006                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6007                                 x86_mfence (code);
6008                         break;
6009                 }
6010                 case OP_ATOMIC_STORE_R8: {
6011                         x86_nop (code);
6012                         x86_nop (code);
6013                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
6014                         x86_nop (code);
6015                         x86_nop (code);
6016
6017                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6018                                 x86_mfence (code);
6019                         break;
6020                 }
6021                 case OP_CARD_TABLE_WBARRIER: {
6022                         int ptr = ins->sreg1;
6023                         int value = ins->sreg2;
6024                         guchar *br = 0;
6025                         int nursery_shift, card_table_shift;
6026                         gpointer card_table_mask;
6027                         size_t nursery_size;
6028
6029                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
6030                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
6031                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
6032
6033                         /*If either point to the stack we can simply avoid the WB. This happens due to
6034                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6035                          */
6036                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
6037                                 continue;
6038
6039                         /*
6040                          * We need one register we can clobber, we choose EDX and make sreg1
6041                          * fixed EAX to work around limitations in the local register allocator.
6042                          * sreg2 might get allocated to EDX, but that is not a problem since
6043                          * we use it before clobbering EDX.
6044                          */
6045                         g_assert (ins->sreg1 == AMD64_RAX);
6046
6047                         /*
6048                          * This is the code we produce:
6049                          *
6050                          *   edx = value
6051                          *   edx >>= nursery_shift
6052                          *   cmp edx, (nursery_start >> nursery_shift)
6053                          *   jne done
6054                          *   edx = ptr
6055                          *   edx >>= card_table_shift
6056                          *   edx += cardtable
6057                          *   [edx] = 1
6058                          * done:
6059                          */
6060
6061                         if (mono_gc_card_table_nursery_check ()) {
6062                                 if (value != AMD64_RDX)
6063                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
6064                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
6065                                 if (shifted_nursery_start >> 31) {
6066                                         /*
6067                                          * The value we need to compare against is 64 bits, so we need
6068                                          * another spare register.  We use RBX, which we save and
6069                                          * restore.
6070                                          */
6071                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
6072                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
6073                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
6074                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
6075                                 } else {
6076                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
6077                                 }
6078                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
6079                         }
6080                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
6081                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
6082                         if (card_table_mask)
6083                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
6084
6085                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6086                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
6087
6088                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
6089
6090                         if (mono_gc_card_table_nursery_check ())
6091                                 x86_patch (br, code);
6092                         break;
6093                 }
6094 #ifdef MONO_ARCH_SIMD_INTRINSICS
6095                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6096                 case OP_ADDPS:
6097                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099                 case OP_DIVPS:
6100                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102                 case OP_MULPS:
6103                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_SUBPS:
6106                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108                 case OP_MAXPS:
6109                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
6110                         break;
6111                 case OP_MINPS:
6112                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114                 case OP_COMPPS:
6115                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6116                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6117                         break;
6118                 case OP_ANDPS:
6119                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121                 case OP_ANDNPS:
6122                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6123                         break;
6124                 case OP_ORPS:
6125                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6126                         break;
6127                 case OP_XORPS:
6128                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6129                         break;
6130                 case OP_SQRTPS:
6131                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6132                         break;
6133                 case OP_RSQRTPS:
6134                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6135                         break;
6136                 case OP_RCPPS:
6137                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6138                         break;
6139                 case OP_ADDSUBPS:
6140                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6141                         break;
6142                 case OP_HADDPS:
6143                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6144                         break;
6145                 case OP_HSUBPS:
6146                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148                 case OP_DUPPS_HIGH:
6149                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6150                         break;
6151                 case OP_DUPPS_LOW:
6152                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6153                         break;
6154
6155                 case OP_PSHUFLEW_HIGH:
6156                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6157                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6158                         break;
6159                 case OP_PSHUFLEW_LOW:
6160                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6161                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6162                         break;
6163                 case OP_PSHUFLED:
6164                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6165                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6166                         break;
6167                 case OP_SHUFPS:
6168                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6169                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6170                         break;
6171                 case OP_SHUFPD:
6172                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6173                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6174                         break;
6175
6176                 case OP_ADDPD:
6177                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6178                         break;
6179                 case OP_DIVPD:
6180                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6181                         break;
6182                 case OP_MULPD:
6183                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6184                         break;
6185                 case OP_SUBPD:
6186                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6187                         break;
6188                 case OP_MAXPD:
6189                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6190                         break;
6191                 case OP_MINPD:
6192                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194                 case OP_COMPPD:
6195                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6196                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6197                         break;
6198                 case OP_ANDPD:
6199                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6200                         break;
6201                 case OP_ANDNPD:
6202                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6203                         break;
6204                 case OP_ORPD:
6205                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6206                         break;
6207                 case OP_XORPD:
6208                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6209                         break;
6210                 case OP_SQRTPD:
6211                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6212                         break;
6213                 case OP_ADDSUBPD:
6214                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6215                         break;
6216                 case OP_HADDPD:
6217                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6218                         break;
6219                 case OP_HSUBPD:
6220                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6221                         break;
6222                 case OP_DUPPD:
6223                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6224                         break;
6225
6226                 case OP_EXTRACT_MASK:
6227                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6228                         break;
6229
6230                 case OP_PAND:
6231                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6232                         break;
6233                 case OP_POR:
6234                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6235                         break;
6236                 case OP_PXOR:
6237                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6238                         break;
6239
6240                 case OP_PADDB:
6241                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6242                         break;
6243                 case OP_PADDW:
6244                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6245                         break;
6246                 case OP_PADDD:
6247                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6248                         break;
6249                 case OP_PADDQ:
6250                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6251                         break;
6252
6253                 case OP_PSUBB:
6254                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6255                         break;
6256                 case OP_PSUBW:
6257                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6258                         break;
6259                 case OP_PSUBD:
6260                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6261                         break;
6262                 case OP_PSUBQ:
6263                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6264                         break;
6265
6266                 case OP_PMAXB_UN:
6267                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6268                         break;
6269                 case OP_PMAXW_UN:
6270                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6271                         break;
6272                 case OP_PMAXD_UN:
6273                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6274                         break;
6275
6276                 case OP_PMAXB:
6277                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6278                         break;
6279                 case OP_PMAXW:
6280                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6281                         break;
6282                 case OP_PMAXD:
6283                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6284                         break;
6285
6286                 case OP_PAVGB_UN:
6287                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6288                         break;
6289                 case OP_PAVGW_UN:
6290                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6291                         break;
6292
6293                 case OP_PMINB_UN:
6294                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6295                         break;
6296                 case OP_PMINW_UN:
6297                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6298                         break;
6299                 case OP_PMIND_UN:
6300                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6301                         break;
6302
6303                 case OP_PMINB:
6304                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6305                         break;
6306                 case OP_PMINW:
6307                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6308                         break;
6309                 case OP_PMIND:
6310                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6311                         break;
6312
6313                 case OP_PCMPEQB:
6314                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6315                         break;
6316                 case OP_PCMPEQW:
6317                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6318                         break;
6319                 case OP_PCMPEQD:
6320                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6321                         break;
6322                 case OP_PCMPEQQ:
6323                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6324                         break;
6325
6326                 case OP_PCMPGTB:
6327                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6328                         break;
6329                 case OP_PCMPGTW:
6330                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6331                         break;
6332                 case OP_PCMPGTD:
6333                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6334                         break;
6335                 case OP_PCMPGTQ:
6336                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6337                         break;
6338
6339                 case OP_PSUM_ABS_DIFF:
6340                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6341                         break;
6342
6343                 case OP_UNPACK_LOWB:
6344                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6345                         break;
6346                 case OP_UNPACK_LOWW:
6347                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6348                         break;
6349                 case OP_UNPACK_LOWD:
6350                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6351                         break;
6352                 case OP_UNPACK_LOWQ:
6353                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6354                         break;
6355                 case OP_UNPACK_LOWPS:
6356                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6357                         break;
6358                 case OP_UNPACK_LOWPD:
6359                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6360                         break;
6361
6362                 case OP_UNPACK_HIGHB:
6363                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6364                         break;
6365                 case OP_UNPACK_HIGHW:
6366                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6367                         break;
6368                 case OP_UNPACK_HIGHD:
6369                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6370                         break;
6371                 case OP_UNPACK_HIGHQ:
6372                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6373                         break;
6374                 case OP_UNPACK_HIGHPS:
6375                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6376                         break;
6377                 case OP_UNPACK_HIGHPD:
6378                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6379                         break;
6380
6381                 case OP_PACKW:
6382                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6383                         break;
6384                 case OP_PACKD:
6385                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6386                         break;
6387                 case OP_PACKW_UN:
6388                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6389                         break;
6390                 case OP_PACKD_UN:
6391                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6392                         break;
6393
6394                 case OP_PADDB_SAT_UN:
6395                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6396                         break;
6397                 case OP_PSUBB_SAT_UN:
6398                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6399                         break;
6400                 case OP_PADDW_SAT_UN:
6401                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6402                         break;
6403                 case OP_PSUBW_SAT_UN:
6404                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6405                         break;
6406
6407                 case OP_PADDB_SAT:
6408                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6409                         break;
6410                 case OP_PSUBB_SAT:
6411                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6412                         break;
6413                 case OP_PADDW_SAT:
6414                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6415                         break;
6416                 case OP_PSUBW_SAT:
6417                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6418                         break;
6419
6420                 case OP_PMULW:
6421                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6422                         break;
6423                 case OP_PMULD:
6424                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6425                         break;
6426                 case OP_PMULQ:
6427                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6428                         break;
6429                 case OP_PMULW_HIGH_UN:
6430                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6431                         break;
6432                 case OP_PMULW_HIGH:
6433                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6434                         break;
6435
6436                 case OP_PSHRW:
6437                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6438                         break;
6439                 case OP_PSHRW_REG:
6440                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6441                         break;
6442
6443                 case OP_PSARW:
6444                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6445                         break;
6446                 case OP_PSARW_REG:
6447                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6448                         break;
6449
6450                 case OP_PSHLW:
6451                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6452                         break;
6453                 case OP_PSHLW_REG:
6454                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6455                         break;
6456
6457                 case OP_PSHRD:
6458                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6459                         break;
6460                 case OP_PSHRD_REG:
6461                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6462                         break;
6463
6464                 case OP_PSARD:
6465                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6466                         break;
6467                 case OP_PSARD_REG:
6468                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6469                         break;
6470
6471                 case OP_PSHLD:
6472                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6473                         break;
6474                 case OP_PSHLD_REG:
6475                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6476                         break;
6477
6478                 case OP_PSHRQ:
6479                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6480                         break;
6481                 case OP_PSHRQ_REG:
6482                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6483                         break;
6484
6485                 /*TODO: This is appart of the sse spec but not added
6486                 case OP_PSARQ:
6487                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6488                         break;
6489                 case OP_PSARQ_REG:
6490                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6491                         break;
6492                 */
6493
6494                 case OP_PSHLQ:
6495                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6496                         break;
6497                 case OP_PSHLQ_REG:
6498                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6499                         break;
6500                 case OP_CVTDQ2PD:
6501                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6502                         break;
6503                 case OP_CVTDQ2PS:
6504                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6505                         break;
6506                 case OP_CVTPD2DQ:
6507                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6508                         break;
6509                 case OP_CVTPD2PS:
6510                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6511                         break;
6512                 case OP_CVTPS2DQ:
6513                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6514                         break;
6515                 case OP_CVTPS2PD:
6516                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6517                         break;
6518                 case OP_CVTTPD2DQ:
6519                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6520                         break;
6521                 case OP_CVTTPS2DQ:
6522                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6523                         break;
6524
6525                 case OP_ICONV_TO_X:
6526                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6527                         break;
6528                 case OP_EXTRACT_I4:
6529                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6530                         break;
6531                 case OP_EXTRACT_I8:
6532                         if (ins->inst_c0) {
6533                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6534                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6535                         } else {
6536                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6537                         }
6538                         break;
6539                 case OP_EXTRACT_I1:
6540                 case OP_EXTRACT_U1:
6541                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6542                         if (ins->inst_c0)
6543                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6544                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6545                         break;
6546                 case OP_EXTRACT_I2:
6547                 case OP_EXTRACT_U2:
6548                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6549                         if (ins->inst_c0)
6550                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6551                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6552                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6553                         break;
6554                 case OP_EXTRACT_R8:
6555                         if (ins->inst_c0)
6556                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6557                         else
6558                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6559                         break;
6560                 case OP_INSERT_I2:
6561                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6562                         break;
6563                 case OP_EXTRACTX_U2:
6564                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6565                         break;
6566                 case OP_INSERTX_U1_SLOW:
6567                         /*sreg1 is the extracted ireg (scratch)
6568                         /sreg2 is the to be inserted ireg (scratch)
6569                         /dreg is the xreg to receive the value*/
6570
6571                         /*clear the bits from the extracted word*/
6572                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6573                         /*shift the value to insert if needed*/
6574                         if (ins->inst_c0 & 1)
6575                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6576                         /*join them together*/
6577                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6578                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6579                         break;
6580                 case OP_INSERTX_I4_SLOW:
6581                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6582                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6583                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6584                         break;
6585                 case OP_INSERTX_I8_SLOW:
6586                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6587                         if (ins->inst_c0)
6588                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6589                         else
6590                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6591                         break;
6592
6593                 case OP_INSERTX_R4_SLOW:
6594                         switch (ins->inst_c0) {
6595                         case 0:
6596                                 if (cfg->r4fp)
6597                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6598                                 else
6599                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6600                                 break;
6601                         case 1:
6602                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6603                                 if (cfg->r4fp)
6604                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6605                                 else
6606                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6607                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6608                                 break;
6609                         case 2:
6610                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6611                                 if (cfg->r4fp)
6612                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6613                                 else
6614                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6615                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6616                                 break;
6617                         case 3:
6618                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6619                                 if (cfg->r4fp)
6620                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6621                                 else
6622                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6623                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6624                                 break;
6625                         }
6626                         break;
6627                 case OP_INSERTX_R8_SLOW:
6628                         if (ins->inst_c0)
6629                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6630                         else
6631                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6632                         break;
6633                 case OP_STOREX_MEMBASE_REG:
6634                 case OP_STOREX_MEMBASE:
6635                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6636                         break;
6637                 case OP_LOADX_MEMBASE:
6638                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6639                         break;
6640                 case OP_LOADX_ALIGNED_MEMBASE:
6641                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6642                         break;
6643                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6644                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6645                         break;
6646                 case OP_STOREX_NTA_MEMBASE_REG:
6647                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6648                         break;
6649                 case OP_PREFETCH_MEMBASE:
6650                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6651                         break;
6652
6653                 case OP_XMOVE:
6654                         /*FIXME the peephole pass should have killed this*/
6655                         if (ins->dreg != ins->sreg1)
6656                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6657                         break;
6658                 case OP_XZERO:
6659                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6660                         break;
6661                 case OP_ICONV_TO_R4_RAW:
6662                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6663                         break;
6664
6665                 case OP_FCONV_TO_R8_X:
6666                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6667                         break;
6668
6669                 case OP_XCONV_R8_TO_I4:
6670                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6671                         switch (ins->backend.source_opcode) {
6672                         case OP_FCONV_TO_I1:
6673                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6674                                 break;
6675                         case OP_FCONV_TO_U1:
6676                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6677                                 break;
6678                         case OP_FCONV_TO_I2:
6679                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6680                                 break;
6681                         case OP_FCONV_TO_U2:
6682                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6683                                 break;
6684                         }
6685                         break;
6686
6687                 case OP_EXPAND_I2:
6688                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6689                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6690                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6691                         break;
6692                 case OP_EXPAND_I4:
6693                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6694                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6695                         break;
6696                 case OP_EXPAND_I8:
6697                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6698                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6699                         break;
6700                 case OP_EXPAND_R4:
6701                         if (cfg->r4fp) {
6702                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6703                         } else {
6704                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6705                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6706                         }
6707                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6708                         break;
6709                 case OP_EXPAND_R8:
6710                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6711                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6712                         break;
6713 #endif
6714                 case OP_LIVERANGE_START: {
6715                         if (cfg->verbose_level > 1)
6716                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6717                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6718                         break;
6719                 }
6720                 case OP_LIVERANGE_END: {
6721                         if (cfg->verbose_level > 1)
6722                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6723                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6724                         break;
6725                 }
6726                 case OP_GC_SAFE_POINT: {
6727                         const char *polling_func = NULL;
6728                         int compare_val = 0;
6729                         guint8 *br [1];
6730
6731 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6732                         polling_func = "mono_nacl_gc";
6733                         compare_val = 0xFFFFFFFF;
6734 #else
6735                         g_assert (mono_threads_is_coop_enabled ());
6736                         polling_func = "mono_threads_state_poll";
6737                         compare_val = 1;
6738 #endif
6739
6740                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6741                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6742                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6743                         amd64_patch (br[0], code);
6744                         break;
6745                 }
6746
6747                 case OP_GC_LIVENESS_DEF:
6748                 case OP_GC_LIVENESS_USE:
6749                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6750                         ins->backend.pc_offset = code - cfg->native_code;
6751                         break;
6752                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6753                         ins->backend.pc_offset = code - cfg->native_code;
6754                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6755                         break;
6756                 default:
6757                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6758                         g_assert_not_reached ();
6759                 }
6760
6761                 if ((code - cfg->native_code - offset) > max_len) {
6762 #if !defined(__native_client_codegen__)
6763                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6764                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6765                         g_assert_not_reached ();
6766 #endif
6767                 }
6768         }
6769
6770         cfg->code_len = code - cfg->native_code;
6771 }
6772
6773 #endif /* DISABLE_JIT */
6774
6775 void
6776 mono_arch_register_lowlevel_calls (void)
6777 {
6778         /* The signature doesn't matter */
6779         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6780 }
6781
6782 void
6783 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6784 {
6785         unsigned char *ip = ji->ip.i + code;
6786
6787         /*
6788          * Debug code to help track down problems where the target of a near call is
6789          * is not valid.
6790          */
6791         if (amd64_is_near_call (ip)) {
6792                 gint64 disp = (guint8*)target - (guint8*)ip;
6793
6794                 if (!amd64_is_imm32 (disp)) {
6795                         printf ("TYPE: %d\n", ji->type);
6796                         switch (ji->type) {
6797                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6798                                 printf ("V: %s\n", ji->data.name);
6799                                 break;
6800                         case MONO_PATCH_INFO_METHOD_JUMP:
6801                         case MONO_PATCH_INFO_METHOD:
6802                                 printf ("V: %s\n", ji->data.method->name);
6803                                 break;
6804                         default:
6805                                 break;
6806                         }
6807                 }
6808         }
6809
6810         amd64_patch (ip, (gpointer)target);
6811 }
6812
6813 #ifndef DISABLE_JIT
6814
6815 static int
6816 get_max_epilog_size (MonoCompile *cfg)
6817 {
6818         int max_epilog_size = 16;
6819
6820         if (cfg->method->save_lmf)
6821                 max_epilog_size += 256;
6822
6823         if (mono_jit_trace_calls != NULL)
6824                 max_epilog_size += 50;
6825
6826         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6827                 max_epilog_size += 50;
6828
6829         max_epilog_size += (AMD64_NREG * 2);
6830
6831         return max_epilog_size;
6832 }
6833
6834 /*
6835  * This macro is used for testing whenever the unwinder works correctly at every point
6836  * where an async exception can happen.
6837  */
6838 /* This will generate a SIGSEGV at the given point in the code */
6839 #define async_exc_point(code) do { \
6840     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6841          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6842              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6843          cfg->arch.async_point_count ++; \
6844     } \
6845 } while (0)
6846
6847 guint8 *
6848 mono_arch_emit_prolog (MonoCompile *cfg)
6849 {
6850         MonoMethod *method = cfg->method;
6851         MonoBasicBlock *bb;
6852         MonoMethodSignature *sig;
6853         MonoInst *ins;
6854         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6855         guint8 *code;
6856         CallInfo *cinfo;
6857         MonoInst *lmf_var = cfg->lmf_var;
6858         gboolean args_clobbered = FALSE;
6859         gboolean trace = FALSE;
6860 #ifdef __native_client_codegen__
6861         guint alignment_check;
6862 #endif
6863
6864         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6865
6866 #if defined(__default_codegen__)
6867         code = cfg->native_code = g_malloc (cfg->code_size);
6868 #elif defined(__native_client_codegen__)
6869         /* native_code_alloc is not 32-byte aligned, native_code is. */
6870         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6871
6872         /* Align native_code to next nearest kNaclAlignment byte. */
6873         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6874         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6875
6876         code = cfg->native_code;
6877
6878         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6879         g_assert (alignment_check == 0);
6880 #endif
6881
6882         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6883                 trace = TRUE;
6884
6885         /* Amount of stack space allocated by register saving code */
6886         pos = 0;
6887
6888         /* Offset between RSP and the CFA */
6889         cfa_offset = 0;
6890
6891         /*
6892          * The prolog consists of the following parts:
6893          * FP present:
6894          * - push rbp, mov rbp, rsp
6895          * - save callee saved regs using pushes
6896          * - allocate frame
6897          * - save rgctx if needed
6898          * - save lmf if needed
6899          * FP not present:
6900          * - allocate frame
6901          * - save rgctx if needed
6902          * - save lmf if needed
6903          * - save callee saved regs using moves
6904          */
6905
6906         // CFA = sp + 8
6907         cfa_offset = 8;
6908         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6909         // IP saved at CFA - 8
6910         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6911         async_exc_point (code);
6912         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6913
6914         if (!cfg->arch.omit_fp) {
6915                 amd64_push_reg (code, AMD64_RBP);
6916                 cfa_offset += 8;
6917                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6918                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6919                 async_exc_point (code);
6920 #ifdef TARGET_WIN32
6921                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6922 #endif
6923                 /* These are handled automatically by the stack marking code */
6924                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6925
6926                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6927                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6928                 async_exc_point (code);
6929 #ifdef TARGET_WIN32
6930                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6931 #endif
6932         }
6933
6934         /* The param area is always at offset 0 from sp */
6935         /* This needs to be allocated here, since it has to come after the spill area */
6936         if (cfg->param_area) {
6937                 if (cfg->arch.omit_fp)
6938                         // FIXME:
6939                         g_assert_not_reached ();
6940                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6941         }
6942
6943         if (cfg->arch.omit_fp) {
6944                 /*
6945                  * On enter, the stack is misaligned by the pushing of the return
6946                  * address. It is either made aligned by the pushing of %rbp, or by
6947                  * this.
6948                  */
6949                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6950                 if ((alloc_size % 16) == 0) {
6951                         alloc_size += 8;
6952                         /* Mark the padding slot as NOREF */
6953                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6954                 }
6955         } else {
6956                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6957                 if (cfg->stack_offset != alloc_size) {
6958                         /* Mark the padding slot as NOREF */
6959                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6960                 }
6961                 cfg->arch.sp_fp_offset = alloc_size;
6962                 alloc_size -= pos;
6963         }
6964
6965         cfg->arch.stack_alloc_size = alloc_size;
6966
6967         /* Allocate stack frame */
6968         if (alloc_size) {
6969                 /* See mono_emit_stack_alloc */
6970 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6971                 guint32 remaining_size = alloc_size;
6972                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6973                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6974                 guint32 offset = code - cfg->native_code;
6975                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6976                         while (required_code_size >= (cfg->code_size - offset))
6977                                 cfg->code_size *= 2;
6978                         cfg->native_code = mono_realloc_native_code (cfg);
6979                         code = cfg->native_code + offset;
6980                         cfg->stat_code_reallocs++;
6981                 }
6982
6983                 while (remaining_size >= 0x1000) {
6984                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6985                         if (cfg->arch.omit_fp) {
6986                                 cfa_offset += 0x1000;
6987                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6988                         }
6989                         async_exc_point (code);
6990 #ifdef TARGET_WIN32
6991                         if (cfg->arch.omit_fp)
6992                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6993 #endif
6994
6995                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6996                         remaining_size -= 0x1000;
6997                 }
6998                 if (remaining_size) {
6999                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
7000                         if (cfg->arch.omit_fp) {
7001                                 cfa_offset += remaining_size;
7002                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7003                                 async_exc_point (code);
7004                         }
7005 #ifdef TARGET_WIN32
7006                         if (cfg->arch.omit_fp)
7007                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7008 #endif
7009                 }
7010 #else
7011                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
7012                 if (cfg->arch.omit_fp) {
7013                         cfa_offset += alloc_size;
7014                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7015                         async_exc_point (code);
7016                 }
7017 #endif
7018         }
7019
7020         /* Stack alignment check */
7021 #if 0
7022         {
7023                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
7024                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
7025                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
7026                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
7027                 amd64_breakpoint (code);
7028         }
7029 #endif
7030
7031         if (mini_get_debug_options ()->init_stacks) {
7032                 /* Fill the stack frame with a dummy value to force deterministic behavior */
7033
7034                 /* Save registers to the red zone */
7035                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
7036                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
7037
7038                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
7039                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
7040                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
7041
7042                 amd64_cld (code);
7043 #if defined(__default_codegen__)
7044                 amd64_prefix (code, X86_REP_PREFIX);
7045                 amd64_stosl (code);
7046 #elif defined(__native_client_codegen__)
7047                 /* NaCl stos pseudo-instruction */
7048                 amd64_codegen_pre (code);
7049                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
7050                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
7051                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7052                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
7053                 amd64_prefix (code, X86_REP_PREFIX);
7054                 amd64_stosl (code);
7055                 amd64_codegen_post (code);
7056 #endif /* __native_client_codegen__ */
7057
7058                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
7059                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
7060         }
7061
7062         /* Save LMF */
7063         if (method->save_lmf)
7064                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
7065
7066         /* Save callee saved registers */
7067         if (cfg->arch.omit_fp) {
7068                 save_area_offset = cfg->arch.reg_save_area_offset;
7069                 /* Save caller saved registers after sp is adjusted */
7070                 /* The registers are saved at the bottom of the frame */
7071                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7072         } else {
7073                 /* The registers are saved just below the saved rbp */
7074                 save_area_offset = cfg->arch.reg_save_area_offset;
7075         }
7076
7077         for (i = 0; i < AMD64_NREG; ++i) {
7078                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7079                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
7080
7081                         if (cfg->arch.omit_fp) {
7082                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
7083                                 /* These are handled automatically by the stack marking code */
7084                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
7085                         } else {
7086                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
7087                                 // FIXME: GC
7088                         }
7089
7090                         save_area_offset += 8;
7091                         async_exc_point (code);
7092                 }
7093         }
7094
7095         /* store runtime generic context */
7096         if (cfg->rgctx_var) {
7097                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
7098                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
7099
7100                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7101
7102                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7103                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7104         }
7105
7106         /* compute max_length in order to use short forward jumps */
7107         max_epilog_size = get_max_epilog_size (cfg);
7108         if (cfg->opt & MONO_OPT_BRANCH) {
7109                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
7110                         MonoInst *ins;
7111                         int max_length = 0;
7112
7113                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
7114                                 max_length += 6;
7115                         /* max alignment for loops */
7116                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7117                                 max_length += LOOP_ALIGNMENT;
7118 #ifdef __native_client_codegen__
7119                         /* max alignment for native client */
7120                         max_length += kNaClAlignment;
7121 #endif
7122
7123                         MONO_BB_FOR_EACH_INS (bb, ins) {
7124 #ifdef __native_client_codegen__
7125                                 {
7126                                         int space_in_block = kNaClAlignment -
7127                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7128                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7129                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
7130                                                 max_length += space_in_block;
7131                                         }
7132                                 }
7133 #endif  /*__native_client_codegen__*/
7134                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7135                         }
7136
7137                         /* Take prolog and epilog instrumentation into account */
7138                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7139                                 max_length += max_epilog_size;
7140
7141                         bb->max_length = max_length;
7142                 }
7143         }
7144
7145         sig = mono_method_signature (method);
7146         pos = 0;
7147
7148         cinfo = cfg->arch.cinfo;
7149
7150         if (sig->ret->type != MONO_TYPE_VOID) {
7151                 /* Save volatile arguments to the stack */
7152                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7153                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7154         }
7155
7156         /* Keep this in sync with emit_load_volatile_arguments */
7157         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7158                 ArgInfo *ainfo = cinfo->args + i;
7159
7160                 ins = cfg->args [i];
7161
7162                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7163                         /* Unused arguments */
7164                         continue;
7165
7166                 /* Save volatile arguments to the stack */
7167                 if (ins->opcode != OP_REGVAR) {
7168                         switch (ainfo->storage) {
7169                         case ArgInIReg: {
7170                                 guint32 size = 8;
7171
7172                                 /* FIXME: I1 etc */
7173                                 /*
7174                                 if (stack_offset & 0x1)
7175                                         size = 1;
7176                                 else if (stack_offset & 0x2)
7177                                         size = 2;
7178                                 else if (stack_offset & 0x4)
7179                                         size = 4;
7180                                 else
7181                                         size = 8;
7182                                 */
7183                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7184
7185                                 /*
7186                                  * Save the original location of 'this',
7187                                  * get_generic_info_from_stack_frame () needs this to properly look up
7188                                  * the argument value during the handling of async exceptions.
7189                                  */
7190                                 if (ins == cfg->args [0]) {
7191                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7192                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7193                                 }
7194                                 break;
7195                         }
7196                         case ArgInFloatSSEReg:
7197                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7198                                 break;
7199                         case ArgInDoubleSSEReg:
7200                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7201                                 break;
7202                         case ArgValuetypeInReg:
7203                                 for (quad = 0; quad < 2; quad ++) {
7204                                         switch (ainfo->pair_storage [quad]) {
7205                                         case ArgInIReg:
7206                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7207                                                 break;
7208                                         case ArgInFloatSSEReg:
7209                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7210                                                 break;
7211                                         case ArgInDoubleSSEReg:
7212                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7213                                                 break;
7214                                         case ArgNone:
7215                                                 break;
7216                                         default:
7217                                                 g_assert_not_reached ();
7218                                         }
7219                                 }
7220                                 break;
7221                         case ArgValuetypeAddrInIReg:
7222                                 if (ainfo->pair_storage [0] == ArgInIReg)
7223                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7224                                 break;
7225                         default:
7226                                 break;
7227                         }
7228                 } else {
7229                         /* Argument allocated to (non-volatile) register */
7230                         switch (ainfo->storage) {
7231                         case ArgInIReg:
7232                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7233                                 break;
7234                         case ArgOnStack:
7235                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7236                                 break;
7237                         default:
7238                                 g_assert_not_reached ();
7239                         }
7240
7241                         if (ins == cfg->args [0]) {
7242                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7243                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7244                         }
7245                 }
7246         }
7247
7248         if (cfg->method->save_lmf)
7249                 args_clobbered = TRUE;
7250
7251         if (trace) {
7252                 args_clobbered = TRUE;
7253                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7254         }
7255
7256         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7257                 args_clobbered = TRUE;
7258
7259         /*
7260          * Optimize the common case of the first bblock making a call with the same
7261          * arguments as the method. This works because the arguments are still in their
7262          * original argument registers.
7263          * FIXME: Generalize this
7264          */
7265         if (!args_clobbered) {
7266                 MonoBasicBlock *first_bb = cfg->bb_entry;
7267                 MonoInst *next;
7268                 int filter = FILTER_IL_SEQ_POINT;
7269
7270                 next = mono_bb_first_inst (first_bb, filter);
7271                 if (!next && first_bb->next_bb) {
7272                         first_bb = first_bb->next_bb;
7273                         next = mono_bb_first_inst (first_bb, filter);
7274                 }
7275
7276                 if (first_bb->in_count > 1)
7277                         next = NULL;
7278
7279                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7280                         ArgInfo *ainfo = cinfo->args + i;
7281                         gboolean match = FALSE;
7282
7283                         ins = cfg->args [i];
7284                         if (ins->opcode != OP_REGVAR) {
7285                                 switch (ainfo->storage) {
7286                                 case ArgInIReg: {
7287                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7288                                                 if (next->dreg == ainfo->reg) {
7289                                                         NULLIFY_INS (next);
7290                                                         match = TRUE;
7291                                                 } else {
7292                                                         next->opcode = OP_MOVE;
7293                                                         next->sreg1 = ainfo->reg;
7294                                                         /* Only continue if the instruction doesn't change argument regs */
7295                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7296                                                                 match = TRUE;
7297                                                 }
7298                                         }
7299                                         break;
7300                                 }
7301                                 default:
7302                                         break;
7303                                 }
7304                         } else {
7305                                 /* Argument allocated to (non-volatile) register */
7306                                 switch (ainfo->storage) {
7307                                 case ArgInIReg:
7308                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7309                                                 NULLIFY_INS (next);
7310                                                 match = TRUE;
7311                                         }
7312                                         break;
7313                                 default:
7314                                         break;
7315                                 }
7316                         }
7317
7318                         if (match) {
7319                                 next = mono_inst_next (next, filter);
7320                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7321                                 if (!next)
7322                                         break;
7323                         }
7324                 }
7325         }
7326
7327         if (cfg->gen_sdb_seq_points) {
7328                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7329
7330                 /* Initialize seq_point_info_var */
7331                 if (cfg->compile_aot) {
7332                         /* Initialize the variable from a GOT slot */
7333                         /* Same as OP_AOTCONST */
7334                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7335                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7336                         g_assert (info_var->opcode == OP_REGOFFSET);
7337                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7338                 }
7339
7340                 if (cfg->compile_aot) {
7341                         /* Initialize ss_tramp_var */
7342                         ins = cfg->arch.ss_tramp_var;
7343                         g_assert (ins->opcode == OP_REGOFFSET);
7344
7345                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7346                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7347                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7348                 } else {
7349                         /* Initialize ss_tramp_var */
7350                         ins = cfg->arch.ss_tramp_var;
7351                         g_assert (ins->opcode == OP_REGOFFSET);
7352
7353                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7354                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7355
7356                         /* Initialize bp_tramp_var */
7357                         ins = cfg->arch.bp_tramp_var;
7358                         g_assert (ins->opcode == OP_REGOFFSET);
7359
7360                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7361                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7362                 }
7363         }
7364
7365         cfg->code_len = code - cfg->native_code;
7366
7367         g_assert (cfg->code_len < cfg->code_size);
7368
7369         return code;
7370 }
7371
7372 void
7373 mono_arch_emit_epilog (MonoCompile *cfg)
7374 {
7375         MonoMethod *method = cfg->method;
7376         int quad, i;
7377         guint8 *code;
7378         int max_epilog_size;
7379         CallInfo *cinfo;
7380         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7381         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7382
7383         max_epilog_size = get_max_epilog_size (cfg);
7384
7385         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7386                 cfg->code_size *= 2;
7387                 cfg->native_code = mono_realloc_native_code (cfg);
7388                 cfg->stat_code_reallocs++;
7389         }
7390         code = cfg->native_code + cfg->code_len;
7391
7392         cfg->has_unwind_info_for_epilog = TRUE;
7393
7394         /* Mark the start of the epilog */
7395         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7396
7397         /* Save the uwind state which is needed by the out-of-line code */
7398         mono_emit_unwind_op_remember_state (cfg, code);
7399
7400         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7401                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7402
7403         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7404
7405         if (method->save_lmf) {
7406                 /* check if we need to restore protection of the stack after a stack overflow */
7407                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7408                         guint8 *patch;
7409                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7410                         /* we load the value in a separate instruction: this mechanism may be
7411                          * used later as a safer way to do thread interruption
7412                          */
7413                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7414                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7415                         patch = code;
7416                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7417                         /* note that the call trampoline will preserve eax/edx */
7418                         x86_call_reg (code, X86_ECX);
7419                         x86_patch (patch, code);
7420                 } else {
7421                         /* FIXME: maybe save the jit tls in the prolog */
7422                 }
7423                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7424                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7425                 }
7426         }
7427
7428         /* Restore callee saved regs */
7429         for (i = 0; i < AMD64_NREG; ++i) {
7430                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7431                         /* Restore only used_int_regs, not arch.saved_iregs */
7432                         if (cfg->used_int_regs & (1 << i)) {
7433                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7434                                 mono_emit_unwind_op_same_value (cfg, code, i);
7435                                 async_exc_point (code);
7436                         }
7437                         save_area_offset += 8;
7438                 }
7439         }
7440
7441         /* Load returned vtypes into registers if needed */
7442         cinfo = cfg->arch.cinfo;
7443         if (cinfo->ret.storage == ArgValuetypeInReg) {
7444                 ArgInfo *ainfo = &cinfo->ret;
7445                 MonoInst *inst = cfg->ret;
7446
7447                 for (quad = 0; quad < 2; quad ++) {
7448                         switch (ainfo->pair_storage [quad]) {
7449                         case ArgInIReg:
7450                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7451                                 break;
7452                         case ArgInFloatSSEReg:
7453                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7454                                 break;
7455                         case ArgInDoubleSSEReg:
7456                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7457                                 break;
7458                         case ArgNone:
7459                                 break;
7460                         default:
7461                                 g_assert_not_reached ();
7462                         }
7463                 }
7464         }
7465
7466         if (cfg->arch.omit_fp) {
7467                 if (cfg->arch.stack_alloc_size) {
7468                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7469                 }
7470         } else {
7471                 amd64_leave (code);
7472                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7473         }
7474         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7475         async_exc_point (code);
7476         amd64_ret (code);
7477
7478         /* Restore the unwind state to be the same as before the epilog */
7479         mono_emit_unwind_op_restore_state (cfg, code);
7480
7481         cfg->code_len = code - cfg->native_code;
7482
7483         g_assert (cfg->code_len < cfg->code_size);
7484 }
7485
7486 void
7487 mono_arch_emit_exceptions (MonoCompile *cfg)
7488 {
7489         MonoJumpInfo *patch_info;
7490         int nthrows, i;
7491         guint8 *code;
7492         MonoClass *exc_classes [16];
7493         guint8 *exc_throw_start [16], *exc_throw_end [16];
7494         guint32 code_size = 0;
7495
7496         /* Compute needed space */
7497         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7498                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7499                         code_size += 40;
7500                 if (patch_info->type == MONO_PATCH_INFO_R8)
7501                         code_size += 8 + 15; /* sizeof (double) + alignment */
7502                 if (patch_info->type == MONO_PATCH_INFO_R4)
7503                         code_size += 4 + 15; /* sizeof (float) + alignment */
7504                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7505                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7506         }
7507
7508 #ifdef __native_client_codegen__
7509         /* Give us extra room on Native Client.  This could be   */
7510         /* more carefully calculated, but bundle alignment makes */
7511         /* it much trickier, so *2 like other places is good.    */
7512         code_size *= 2;
7513 #endif
7514
7515         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7516                 cfg->code_size *= 2;
7517                 cfg->native_code = mono_realloc_native_code (cfg);
7518                 cfg->stat_code_reallocs++;
7519         }
7520
7521         code = cfg->native_code + cfg->code_len;
7522
7523         /* add code to raise exceptions */
7524         nthrows = 0;
7525         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7526                 switch (patch_info->type) {
7527                 case MONO_PATCH_INFO_EXC: {
7528                         MonoClass *exc_class;
7529                         guint8 *buf, *buf2;
7530                         guint32 throw_ip;
7531
7532                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7533
7534                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7535                         g_assert (exc_class);
7536                         throw_ip = patch_info->ip.i;
7537
7538                         //x86_breakpoint (code);
7539                         /* Find a throw sequence for the same exception class */
7540                         for (i = 0; i < nthrows; ++i)
7541                                 if (exc_classes [i] == exc_class)
7542                                         break;
7543                         if (i < nthrows) {
7544                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7545                                 x86_jump_code (code, exc_throw_start [i]);
7546                                 patch_info->type = MONO_PATCH_INFO_NONE;
7547                         }
7548                         else {
7549                                 buf = code;
7550                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7551                                 buf2 = code;
7552
7553                                 if (nthrows < 16) {
7554                                         exc_classes [nthrows] = exc_class;
7555                                         exc_throw_start [nthrows] = code;
7556                                 }
7557                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7558
7559                                 patch_info->type = MONO_PATCH_INFO_NONE;
7560
7561                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7562
7563                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7564                                 while (buf < buf2)
7565                                         x86_nop (buf);
7566
7567                                 if (nthrows < 16) {
7568                                         exc_throw_end [nthrows] = code;
7569                                         nthrows ++;
7570                                 }
7571                         }
7572                         break;
7573                 }
7574                 default:
7575                         /* do nothing */
7576                         break;
7577                 }
7578                 g_assert(code < cfg->native_code + cfg->code_size);
7579         }
7580
7581         /* Handle relocations with RIP relative addressing */
7582         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7583                 gboolean remove = FALSE;
7584                 guint8 *orig_code = code;
7585
7586                 switch (patch_info->type) {
7587                 case MONO_PATCH_INFO_R8:
7588                 case MONO_PATCH_INFO_R4: {
7589                         guint8 *pos, *patch_pos;
7590                         guint32 target_pos;
7591
7592                         /* The SSE opcodes require a 16 byte alignment */
7593 #if defined(__default_codegen__)
7594                         code = (guint8*)ALIGN_TO (code, 16);
7595 #elif defined(__native_client_codegen__)
7596                         {
7597                                 /* Pad this out with HLT instructions  */
7598                                 /* or we can get garbage bytes emitted */
7599                                 /* which will fail validation          */
7600                                 guint8 *aligned_code;
7601                                 /* extra align to make room for  */
7602                                 /* mov/push below                      */
7603                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7604                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7605                                 /* The technique of hiding data in an  */
7606                                 /* instruction has a problem here: we  */
7607                                 /* need the data aligned to a 16-byte  */
7608                                 /* boundary but the instruction cannot */
7609                                 /* cross the bundle boundary. so only  */
7610                                 /* odd multiples of 16 can be used     */
7611                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7612                                         aligned_code += 16;
7613                                 }
7614                                 while (code < aligned_code) {
7615                                         *(code++) = 0xf4; /* hlt */
7616                                 }
7617                         }
7618 #endif
7619
7620                         pos = cfg->native_code + patch_info->ip.i;
7621                         if (IS_REX (pos [1])) {
7622                                 patch_pos = pos + 5;
7623                                 target_pos = code - pos - 9;
7624                         }
7625                         else {
7626                                 patch_pos = pos + 4;
7627                                 target_pos = code - pos - 8;
7628                         }
7629
7630                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7631 #ifdef __native_client_codegen__
7632                                 /* Hide 64-bit data in a         */
7633                                 /* "mov imm64, r11" instruction. */
7634                                 /* write it before the start of  */
7635                                 /* the data*/
7636                                 *(code-2) = 0x49; /* prefix      */
7637                                 *(code-1) = 0xbb; /* mov X, %r11 */
7638 #endif
7639                                 *(double*)code = *(double*)patch_info->data.target;
7640                                 code += sizeof (double);
7641                         } else {
7642 #ifdef __native_client_codegen__
7643                                 /* Hide 32-bit data in a        */
7644                                 /* "push imm32" instruction.    */
7645                                 *(code-1) = 0x68; /* push */
7646 #endif
7647                                 *(float*)code = *(float*)patch_info->data.target;
7648                                 code += sizeof (float);
7649                         }
7650
7651                         *(guint32*)(patch_pos) = target_pos;
7652
7653                         remove = TRUE;
7654                         break;
7655                 }
7656                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7657                         guint8 *pos;
7658
7659                         if (cfg->compile_aot)
7660                                 continue;
7661
7662                         /*loading is faster against aligned addresses.*/
7663                         code = (guint8*)ALIGN_TO (code, 8);
7664                         memset (orig_code, 0, code - orig_code);
7665
7666                         pos = cfg->native_code + patch_info->ip.i;
7667
7668                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7669                         if (IS_REX (pos [1]))
7670                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7671                         else
7672                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7673
7674                         *(gpointer*)code = (gpointer)patch_info->data.target;
7675                         code += sizeof (gpointer);
7676
7677                         remove = TRUE;
7678                         break;
7679                 }
7680                 default:
7681                         break;
7682                 }
7683
7684                 if (remove) {
7685                         if (patch_info == cfg->patch_info)
7686                                 cfg->patch_info = patch_info->next;
7687                         else {
7688                                 MonoJumpInfo *tmp;
7689
7690                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7691                                         ;
7692                                 tmp->next = patch_info->next;
7693                         }
7694                 }
7695                 g_assert (code < cfg->native_code + cfg->code_size);
7696         }
7697
7698         cfg->code_len = code - cfg->native_code;
7699
7700         g_assert (cfg->code_len < cfg->code_size);
7701
7702 }
7703
7704 #endif /* DISABLE_JIT */
7705
7706 void*
7707 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7708 {
7709         guchar *code = p;
7710         MonoMethodSignature *sig;
7711         MonoInst *inst;
7712         int i, n, stack_area = 0;
7713
7714         /* Keep this in sync with mono_arch_get_argument_info */
7715
7716         if (enable_arguments) {
7717                 /* Allocate a new area on the stack and save arguments there */
7718                 sig = mono_method_signature (cfg->method);
7719
7720                 n = sig->param_count + sig->hasthis;
7721
7722                 stack_area = ALIGN_TO (n * 8, 16);
7723
7724                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7725
7726                 for (i = 0; i < n; ++i) {
7727                         inst = cfg->args [i];
7728
7729                         if (inst->opcode == OP_REGVAR)
7730                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7731                         else {
7732                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7733                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7734                         }
7735                 }
7736         }
7737
7738         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7739         amd64_set_reg_template (code, AMD64_ARG_REG1);
7740         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7741         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7742
7743         if (enable_arguments)
7744                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7745
7746         return code;
7747 }
7748
7749 enum {
7750         SAVE_NONE,
7751         SAVE_STRUCT,
7752         SAVE_EAX,
7753         SAVE_EAX_EDX,
7754         SAVE_XMM
7755 };
7756
7757 void*
7758 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7759 {
7760         guchar *code = p;
7761         int save_mode = SAVE_NONE;
7762         MonoMethod *method = cfg->method;
7763         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7764         int i;
7765
7766         switch (ret_type->type) {
7767         case MONO_TYPE_VOID:
7768                 /* special case string .ctor icall */
7769                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7770                         save_mode = SAVE_EAX;
7771                 else
7772                         save_mode = SAVE_NONE;
7773                 break;
7774         case MONO_TYPE_I8:
7775         case MONO_TYPE_U8:
7776                 save_mode = SAVE_EAX;
7777                 break;
7778         case MONO_TYPE_R4:
7779         case MONO_TYPE_R8:
7780                 save_mode = SAVE_XMM;
7781                 break;
7782         case MONO_TYPE_GENERICINST:
7783                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7784                         save_mode = SAVE_EAX;
7785                         break;
7786                 }
7787                 /* Fall through */
7788         case MONO_TYPE_VALUETYPE:
7789                 save_mode = SAVE_STRUCT;
7790                 break;
7791         default:
7792                 save_mode = SAVE_EAX;
7793                 break;
7794         }
7795
7796         /* Save the result and copy it into the proper argument register */
7797         switch (save_mode) {
7798         case SAVE_EAX:
7799                 amd64_push_reg (code, AMD64_RAX);
7800                 /* Align stack */
7801                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7802                 if (enable_arguments)
7803                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7804                 break;
7805         case SAVE_STRUCT:
7806                 /* FIXME: */
7807                 if (enable_arguments)
7808                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7809                 break;
7810         case SAVE_XMM:
7811                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7812                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7813                 /* Align stack */
7814                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7815                 /*
7816                  * The result is already in the proper argument register so no copying
7817                  * needed.
7818                  */
7819                 break;
7820         case SAVE_NONE:
7821                 break;
7822         default:
7823                 g_assert_not_reached ();
7824         }
7825
7826         /* Set %al since this is a varargs call */
7827         if (save_mode == SAVE_XMM)
7828                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7829         else
7830                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7831
7832         if (preserve_argument_registers) {
7833                 for (i = 0; i < PARAM_REGS; ++i)
7834                         amd64_push_reg (code, param_regs [i]);
7835         }
7836
7837         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7838         amd64_set_reg_template (code, AMD64_ARG_REG1);
7839         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7840
7841         if (preserve_argument_registers) {
7842                 for (i = PARAM_REGS - 1; i >= 0; --i)
7843                         amd64_pop_reg (code, param_regs [i]);
7844         }
7845
7846         /* Restore result */
7847         switch (save_mode) {
7848         case SAVE_EAX:
7849                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7850                 amd64_pop_reg (code, AMD64_RAX);
7851                 break;
7852         case SAVE_STRUCT:
7853                 /* FIXME: */
7854                 break;
7855         case SAVE_XMM:
7856                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7857                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7858                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7859                 break;
7860         case SAVE_NONE:
7861                 break;
7862         default:
7863                 g_assert_not_reached ();
7864         }
7865
7866         return code;
7867 }
7868
7869 void
7870 mono_arch_flush_icache (guint8 *code, gint size)
7871 {
7872         /* Not needed */
7873 }
7874
7875 void
7876 mono_arch_flush_register_windows (void)
7877 {
7878 }
7879
7880 gboolean
7881 mono_arch_is_inst_imm (gint64 imm)
7882 {
7883         return amd64_use_imm32 (imm);
7884 }
7885
7886 /*
7887  * Determine whenever the trap whose info is in SIGINFO is caused by
7888  * integer overflow.
7889  */
7890 gboolean
7891 mono_arch_is_int_overflow (void *sigctx, void *info)
7892 {
7893         MonoContext ctx;
7894         guint8* rip;
7895         int reg;
7896         gint64 value;
7897
7898         mono_sigctx_to_monoctx (sigctx, &ctx);
7899
7900         rip = (guint8*)ctx.gregs [AMD64_RIP];
7901
7902         if (IS_REX (rip [0])) {
7903                 reg = amd64_rex_b (rip [0]);
7904                 rip ++;
7905         }
7906         else
7907                 reg = 0;
7908
7909         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7910                 /* idiv REG */
7911                 reg += x86_modrm_rm (rip [1]);
7912
7913                 value = ctx.gregs [reg];
7914
7915                 if (value == -1)
7916                         return TRUE;
7917         }
7918
7919         return FALSE;
7920 }
7921
7922 guint32
7923 mono_arch_get_patch_offset (guint8 *code)
7924 {
7925         return 3;
7926 }
7927
7928 /**
7929  * mono_breakpoint_clean_code:
7930  *
7931  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7932  * breakpoints in the original code, they are removed in the copy.
7933  *
7934  * Returns TRUE if no sw breakpoint was present.
7935  */
7936 gboolean
7937 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7938 {
7939         /*
7940          * If method_start is non-NULL we need to perform bound checks, since we access memory
7941          * at code - offset we could go before the start of the method and end up in a different
7942          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7943          * instead.
7944          */
7945         if (!method_start || code - offset >= method_start) {
7946                 memcpy (buf, code - offset, size);
7947         } else {
7948                 int diff = code - method_start;
7949                 memset (buf, 0, size);
7950                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7951         }
7952         return TRUE;
7953 }
7954
7955 #if defined(__native_client_codegen__)
7956 /* For membase calls, we want the base register. for Native Client,  */
7957 /* all indirect calls have the following sequence with the given sizes: */
7958 /* mov %eXX,%eXX                                [2-3]   */
7959 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7960 /* and $0xffffffffffffffe0,%r11d                [4]     */
7961 /* add %r15,%r11                                [3]     */
7962 /* callq *%r11                                  [3]     */
7963
7964
7965 /* Determine if code points to a NaCl call-through-register sequence, */
7966 /* (i.e., the last 3 instructions listed above) */
7967 int
7968 is_nacl_call_reg_sequence(guint8* code)
7969 {
7970         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7971                                "\x4d\x03\xdf"     /* add */
7972                                "\x41\xff\xd3";   /* call */
7973         return memcmp(code, sequence, 10) == 0;
7974 }
7975
7976 /* Determine if code points to the first opcode of the mov membase component */
7977 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7978 /* (there could be a REX prefix before the opcode but it is ignored) */
7979 static int
7980 is_nacl_indirect_call_membase_sequence(guint8* code)
7981 {
7982                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7983         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7984                /* and that src reg = dest reg */
7985                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7986                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7987                IS_REX(code[2]) &&
7988                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7989                /* and has dst of r11 and base of r15 */
7990                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7991                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7992 }
7993 #endif /* __native_client_codegen__ */
7994
7995 int
7996 mono_arch_get_this_arg_reg (guint8 *code)
7997 {
7998         return AMD64_ARG_REG1;
7999 }
8000
8001 gpointer
8002 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
8003 {
8004         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
8005 }
8006
8007 #define MAX_ARCH_DELEGATE_PARAMS 10
8008
8009 static gpointer
8010 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
8011 {
8012         guint8 *code, *start;
8013         GSList *unwind_ops = NULL;
8014         int i;
8015
8016         unwind_ops = mono_arch_get_cie_program ();
8017
8018         if (has_target) {
8019                 start = code = mono_global_codeman_reserve (64);
8020
8021                 /* Replace the this argument with the target */
8022                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8023                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8024                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8025
8026                 g_assert ((code - start) < 64);
8027         } else {
8028                 start = code = mono_global_codeman_reserve (64);
8029
8030                 if (param_count == 0) {
8031                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8032                 } else {
8033                         /* We have to shift the arguments left */
8034                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8035                         for (i = 0; i < param_count; ++i) {
8036 #ifdef TARGET_WIN32
8037                                 if (i < 3)
8038                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8039                                 else
8040                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
8041 #else
8042                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8043 #endif
8044                         }
8045
8046                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8047                 }
8048                 g_assert ((code - start) < 64);
8049         }
8050
8051         nacl_global_codeman_validate (&start, 64, &code);
8052         mono_arch_flush_icache (start, code - start);
8053
8054         if (has_target) {
8055                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8056         } else {
8057                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
8058                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
8059                 g_free (name);
8060         }
8061
8062         if (mono_jit_map_is_enabled ()) {
8063                 char *buff;
8064                 if (has_target)
8065                         buff = (char*)"delegate_invoke_has_target";
8066                 else
8067                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8068                 mono_emit_jit_tramp (start, code - start, buff);
8069                 if (!has_target)
8070                         g_free (buff);
8071         }
8072         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8073
8074         return start;
8075 }
8076
8077 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8078
8079 static gpointer
8080 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
8081 {
8082         guint8 *code, *start;
8083         int size = 20;
8084         char *tramp_name;
8085         GSList *unwind_ops;
8086
8087         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
8088                 return NULL;
8089
8090         start = code = mono_global_codeman_reserve (size);
8091
8092         unwind_ops = mono_arch_get_cie_program ();
8093
8094         /* Replace the this argument with the target */
8095         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8096         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8097
8098         if (load_imt_reg) {
8099                 /* Load the IMT reg */
8100                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8101         }
8102
8103         /* Load the vtable */
8104         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8105         amd64_jump_membase (code, AMD64_RAX, offset);
8106         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8107
8108         if (load_imt_reg)
8109                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
8110         else
8111                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
8112         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
8113         g_free (tramp_name);
8114
8115         return start;
8116 }
8117
8118 /*
8119  * mono_arch_get_delegate_invoke_impls:
8120  *
8121  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8122  * trampolines.
8123  */
8124 GSList*
8125 mono_arch_get_delegate_invoke_impls (void)
8126 {
8127         GSList *res = NULL;
8128         MonoTrampInfo *info;
8129         int i;
8130
8131         get_delegate_invoke_impl (&info, TRUE, 0);
8132         res = g_slist_prepend (res, info);
8133
8134         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8135                 get_delegate_invoke_impl (&info, FALSE, i);
8136                 res = g_slist_prepend (res, info);
8137         }
8138
8139         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8140                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8141                 res = g_slist_prepend (res, info);
8142
8143                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8144                 res = g_slist_prepend (res, info);
8145         }
8146
8147         return res;
8148 }
8149
8150 gpointer
8151 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8152 {
8153         guint8 *code, *start;
8154         int i;
8155
8156         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8157                 return NULL;
8158
8159         /* FIXME: Support more cases */
8160         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8161                 return NULL;
8162
8163         if (has_target) {
8164                 static guint8* cached = NULL;
8165
8166                 if (cached)
8167                         return cached;
8168
8169                 if (mono_aot_only) {
8170                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8171                 } else {
8172                         MonoTrampInfo *info;
8173                         start = get_delegate_invoke_impl (&info, TRUE, 0);
8174                         mono_tramp_info_register (info, NULL);
8175                 }
8176
8177                 mono_memory_barrier ();
8178
8179                 cached = start;
8180         } else {
8181                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8182                 for (i = 0; i < sig->param_count; ++i)
8183                         if (!mono_is_regsize_var (sig->params [i]))
8184                                 return NULL;
8185                 if (sig->param_count > 4)
8186                         return NULL;
8187
8188                 code = cache [sig->param_count];
8189                 if (code)
8190                         return code;
8191
8192                 if (mono_aot_only) {
8193                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8194                         start = mono_aot_get_trampoline (name);
8195                         g_free (name);
8196                 } else {
8197                         MonoTrampInfo *info;
8198                         start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8199                         mono_tramp_info_register (info, NULL);
8200                 }
8201
8202                 mono_memory_barrier ();
8203
8204                 cache [sig->param_count] = start;
8205         }
8206
8207         return start;
8208 }
8209
8210 gpointer
8211 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8212 {
8213         MonoTrampInfo *info;
8214         gpointer code;
8215
8216         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8217         if (code)
8218                 mono_tramp_info_register (info, NULL);
8219         return code;
8220 }
8221
8222 void
8223 mono_arch_finish_init (void)
8224 {
8225 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8226         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8227 #endif
8228 }
8229
8230 void
8231 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8232 {
8233 }
8234
8235 #if defined(__default_codegen__)
8236 #define CMP_SIZE (6 + 1)
8237 #define CMP_REG_REG_SIZE (4 + 1)
8238 #define BR_SMALL_SIZE 2
8239 #define BR_LARGE_SIZE 6
8240 #define MOV_REG_IMM_SIZE 10
8241 #define MOV_REG_IMM_32BIT_SIZE 6
8242 #define JUMP_REG_SIZE (2 + 1)
8243 #elif defined(__native_client_codegen__)
8244 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8245 #define CMP_SIZE ((6 + 1) * 2 - 1)
8246 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8247 #define BR_SMALL_SIZE (2 * 2 - 1)
8248 #define BR_LARGE_SIZE (6 * 2 - 1)
8249 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8250 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8251 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8252 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8253 /* Jump membase's size is large and unpredictable    */
8254 /* in native client, just pad it out a whole bundle. */
8255 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8256 #endif
8257
8258 static int
8259 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8260 {
8261         int i, distance = 0;
8262         for (i = start; i < target; ++i)
8263                 distance += imt_entries [i]->chunk_size;
8264         return distance;
8265 }
8266
8267 /*
8268  * LOCKING: called with the domain lock held
8269  */
8270 gpointer
8271 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8272         gpointer fail_tramp)
8273 {
8274         int i;
8275         int size = 0;
8276         guint8 *code, *start;
8277         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8278         GSList *unwind_ops;
8279
8280         for (i = 0; i < count; ++i) {
8281                 MonoIMTCheckItem *item = imt_entries [i];
8282                 if (item->is_equals) {
8283                         if (item->check_target_idx) {
8284                                 if (!item->compare_done) {
8285                                         if (amd64_use_imm32 ((gint64)item->key))
8286                                                 item->chunk_size += CMP_SIZE;
8287                                         else
8288                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8289                                 }
8290                                 if (item->has_target_code) {
8291                                         item->chunk_size += MOV_REG_IMM_SIZE;
8292                                 } else {
8293                                         if (vtable_is_32bit)
8294                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8295                                         else
8296                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8297 #ifdef __native_client_codegen__
8298                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8299 #endif
8300                                 }
8301                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8302                         } else {
8303                                 if (fail_tramp) {
8304                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8305                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8306                                 } else {
8307                                         if (vtable_is_32bit)
8308                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8309                                         else
8310                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8311                                         item->chunk_size += JUMP_REG_SIZE;
8312                                         /* with assert below:
8313                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8314                                          */
8315 #ifdef __native_client_codegen__
8316                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8317 #endif
8318                                 }
8319                         }
8320                 } else {
8321                         if (amd64_use_imm32 ((gint64)item->key))
8322                                 item->chunk_size += CMP_SIZE;
8323                         else
8324                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8325                         item->chunk_size += BR_LARGE_SIZE;
8326                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8327                 }
8328                 size += item->chunk_size;
8329         }
8330 #if defined(__native_client__) && defined(__native_client_codegen__)
8331         /* In Native Client, we don't re-use thunks, allocate from the */
8332         /* normal code manager paths. */
8333         code = mono_domain_code_reserve (domain, size);
8334 #else
8335         if (fail_tramp)
8336                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8337         else
8338                 code = mono_domain_code_reserve (domain, size);
8339 #endif
8340         start = code;
8341
8342         unwind_ops = mono_arch_get_cie_program ();
8343
8344         for (i = 0; i < count; ++i) {
8345                 MonoIMTCheckItem *item = imt_entries [i];
8346                 item->code_target = code;
8347                 if (item->is_equals) {
8348                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8349
8350                         if (item->check_target_idx || fail_case) {
8351                                 if (!item->compare_done || fail_case) {
8352                                         if (amd64_use_imm32 ((gint64)item->key))
8353                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8354                                         else {
8355                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8356                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8357                                         }
8358                                 }
8359                                 item->jmp_code = code;
8360                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8361                                 if (item->has_target_code) {
8362                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8363                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8364                                 } else {
8365                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8366                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8367                                 }
8368
8369                                 if (fail_case) {
8370                                         amd64_patch (item->jmp_code, code);
8371                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8372                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8373                                         item->jmp_code = NULL;
8374                                 }
8375                         } else {
8376                                 /* enable the commented code to assert on wrong method */
8377 #if 0
8378                                 if (amd64_is_imm32 (item->key))
8379                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8380                                 else {
8381                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8382                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8383                                 }
8384                                 item->jmp_code = code;
8385                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8386                                 /* See the comment below about R10 */
8387                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8388                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8389                                 amd64_patch (item->jmp_code, code);
8390                                 amd64_breakpoint (code);
8391                                 item->jmp_code = NULL;
8392 #else
8393                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8394                                    needs to be preserved.  R10 needs
8395                                    to be preserved for calls which
8396                                    require a runtime generic context,
8397                                    but interface calls don't. */
8398                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8399                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8400 #endif
8401                         }
8402                 } else {
8403                         if (amd64_use_imm32 ((gint64)item->key))
8404                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8405                         else {
8406                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8407                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8408                         }
8409                         item->jmp_code = code;
8410                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8411                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8412                         else
8413                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8414                 }
8415                 g_assert (code - item->code_target <= item->chunk_size);
8416         }
8417         /* patch the branches to get to the target items */
8418         for (i = 0; i < count; ++i) {
8419                 MonoIMTCheckItem *item = imt_entries [i];
8420                 if (item->jmp_code) {
8421                         if (item->check_target_idx) {
8422                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8423                         }
8424                 }
8425         }
8426
8427         if (!fail_tramp)
8428                 mono_stats.imt_thunks_size += code - start;
8429         g_assert (code - start <= size);
8430
8431         nacl_domain_code_validate(domain, &start, size, &code);
8432         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8433
8434         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8435
8436         return start;
8437 }
8438
8439 MonoMethod*
8440 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8441 {
8442         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8443 }
8444
8445 MonoVTable*
8446 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8447 {
8448         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8449 }
8450
8451 GSList*
8452 mono_arch_get_cie_program (void)
8453 {
8454         GSList *l = NULL;
8455
8456         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8457         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8458
8459         return l;
8460 }
8461
8462 #ifndef DISABLE_JIT
8463
8464 MonoInst*
8465 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8466 {
8467         MonoInst *ins = NULL;
8468         int opcode = 0;
8469
8470         if (cmethod->klass == mono_defaults.math_class) {
8471                 if (strcmp (cmethod->name, "Sin") == 0) {
8472                         opcode = OP_SIN;
8473                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8474                         opcode = OP_COS;
8475                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8476                         opcode = OP_SQRT;
8477                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8478                         opcode = OP_ABS;
8479                 }
8480
8481                 if (opcode && fsig->param_count == 1) {
8482                         MONO_INST_NEW (cfg, ins, opcode);
8483                         ins->type = STACK_R8;
8484                         ins->dreg = mono_alloc_freg (cfg);
8485                         ins->sreg1 = args [0]->dreg;
8486                         MONO_ADD_INS (cfg->cbb, ins);
8487                 }
8488
8489                 opcode = 0;
8490                 if (cfg->opt & MONO_OPT_CMOV) {
8491                         if (strcmp (cmethod->name, "Min") == 0) {
8492                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8493                                         opcode = OP_IMIN;
8494                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8495                                         opcode = OP_IMIN_UN;
8496                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8497                                         opcode = OP_LMIN;
8498                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8499                                         opcode = OP_LMIN_UN;
8500                         } else if (strcmp (cmethod->name, "Max") == 0) {
8501                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8502                                         opcode = OP_IMAX;
8503                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8504                                         opcode = OP_IMAX_UN;
8505                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8506                                         opcode = OP_LMAX;
8507                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8508                                         opcode = OP_LMAX_UN;
8509                         }
8510                 }
8511
8512                 if (opcode && fsig->param_count == 2) {
8513                         MONO_INST_NEW (cfg, ins, opcode);
8514                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8515                         ins->dreg = mono_alloc_ireg (cfg);
8516                         ins->sreg1 = args [0]->dreg;
8517                         ins->sreg2 = args [1]->dreg;
8518                         MONO_ADD_INS (cfg->cbb, ins);
8519                 }
8520
8521 #if 0
8522                 /* OP_FREM is not IEEE compatible */
8523                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8524                         MONO_INST_NEW (cfg, ins, OP_FREM);
8525                         ins->inst_i0 = args [0];
8526                         ins->inst_i1 = args [1];
8527                 }
8528 #endif
8529         }
8530
8531         return ins;
8532 }
8533 #endif
8534
8535 gboolean
8536 mono_arch_print_tree (MonoInst *tree, int arity)
8537 {
8538         return 0;
8539 }
8540
8541 mgreg_t
8542 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8543 {
8544         return ctx->gregs [reg];
8545 }
8546
8547 void
8548 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8549 {
8550         ctx->gregs [reg] = val;
8551 }
8552
8553 gpointer
8554 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8555 {
8556         gpointer *sp, old_value;
8557         char *bp;
8558
8559         /*Load the spvar*/
8560         bp = MONO_CONTEXT_GET_BP (ctx);
8561         sp = *(gpointer*)(bp + clause->exvar_offset);
8562
8563         old_value = *sp;
8564         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8565                 return old_value;
8566
8567         *sp = new_value;
8568
8569         return old_value;
8570 }
8571
8572 /*
8573  * mono_arch_emit_load_aotconst:
8574  *
8575  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8576  * TARGET from the mscorlib GOT in full-aot code.
8577  * On AMD64, the result is placed into R11.
8578  */
8579 guint8*
8580 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8581 {
8582         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8583         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8584
8585         return code;
8586 }
8587
8588 /*
8589  * mono_arch_get_trampolines:
8590  *
8591  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8592  * for AOT.
8593  */
8594 GSList *
8595 mono_arch_get_trampolines (gboolean aot)
8596 {
8597         return mono_amd64_get_exception_trampolines (aot);
8598 }
8599
8600 /* Soft Debug support */
8601 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8602
8603 /*
8604  * mono_arch_set_breakpoint:
8605  *
8606  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8607  * The location should contain code emitted by OP_SEQ_POINT.
8608  */
8609 void
8610 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8611 {
8612         guint8 *code = ip;
8613
8614         if (ji->from_aot) {
8615                 guint32 native_offset = ip - (guint8*)ji->code_start;
8616                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8617
8618                 g_assert (info->bp_addrs [native_offset] == 0);
8619                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8620         } else {
8621                 /* ip points to a mov r11, 0 */
8622                 g_assert (code [0] == 0x41);
8623                 g_assert (code [1] == 0xbb);
8624                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8625         }
8626 }
8627
8628 /*
8629  * mono_arch_clear_breakpoint:
8630  *
8631  *   Clear the breakpoint at IP.
8632  */
8633 void
8634 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8635 {
8636         guint8 *code = ip;
8637
8638         if (ji->from_aot) {
8639                 guint32 native_offset = ip - (guint8*)ji->code_start;
8640                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8641
8642                 info->bp_addrs [native_offset] = NULL;
8643         } else {
8644                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8645         }
8646 }
8647
8648 gboolean
8649 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8650 {
8651         /* We use soft breakpoints on amd64 */
8652         return FALSE;
8653 }
8654
8655 /*
8656  * mono_arch_skip_breakpoint:
8657  *
8658  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8659  * we resume, the instruction is not executed again.
8660  */
8661 void
8662 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8663 {
8664         g_assert_not_reached ();
8665 }
8666
8667 /*
8668  * mono_arch_start_single_stepping:
8669  *
8670  *   Start single stepping.
8671  */
8672 void
8673 mono_arch_start_single_stepping (void)
8674 {
8675         ss_trampoline = mini_get_single_step_trampoline ();
8676 }
8677
8678 /*
8679  * mono_arch_stop_single_stepping:
8680  *
8681  *   Stop single stepping.
8682  */
8683 void
8684 mono_arch_stop_single_stepping (void)
8685 {
8686         ss_trampoline = NULL;
8687 }
8688
8689 /*
8690  * mono_arch_is_single_step_event:
8691  *
8692  *   Return whenever the machine state in SIGCTX corresponds to a single
8693  * step event.
8694  */
8695 gboolean
8696 mono_arch_is_single_step_event (void *info, void *sigctx)
8697 {
8698         /* We use soft breakpoints on amd64 */
8699         return FALSE;
8700 }
8701
8702 /*
8703  * mono_arch_skip_single_step:
8704  *
8705  *   Modify CTX so the ip is placed after the single step trigger instruction,
8706  * we resume, the instruction is not executed again.
8707  */
8708 void
8709 mono_arch_skip_single_step (MonoContext *ctx)
8710 {
8711         g_assert_not_reached ();
8712 }
8713
8714 /*
8715  * mono_arch_create_seq_point_info:
8716  *
8717  *   Return a pointer to a data structure which is used by the sequence
8718  * point implementation in AOTed code.
8719  */
8720 gpointer
8721 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8722 {
8723         SeqPointInfo *info;
8724         MonoJitInfo *ji;
8725
8726         // FIXME: Add a free function
8727
8728         mono_domain_lock (domain);
8729         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8730                                                                 code);
8731         mono_domain_unlock (domain);
8732
8733         if (!info) {
8734                 ji = mono_jit_info_table_find (domain, (char*)code);
8735                 g_assert (ji);
8736
8737                 // FIXME: Optimize the size
8738                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8739
8740                 info->ss_tramp_addr = &ss_trampoline;
8741
8742                 mono_domain_lock (domain);
8743                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8744                                                          code, info);
8745                 mono_domain_unlock (domain);
8746         }
8747
8748         return info;
8749 }
8750
8751 void
8752 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8753 {
8754         ext->lmf.previous_lmf = prev_lmf;
8755         /* Mark that this is a MonoLMFExt */
8756         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8757         ext->lmf.rsp = (gssize)ext;
8758 }
8759
8760 #endif
8761
8762 gboolean
8763 mono_arch_opcode_supported (int opcode)
8764 {
8765         switch (opcode) {
8766         case OP_ATOMIC_ADD_I4:
8767         case OP_ATOMIC_ADD_I8:
8768         case OP_ATOMIC_EXCHANGE_I4:
8769         case OP_ATOMIC_EXCHANGE_I8:
8770         case OP_ATOMIC_CAS_I4:
8771         case OP_ATOMIC_CAS_I8:
8772         case OP_ATOMIC_LOAD_I1:
8773         case OP_ATOMIC_LOAD_I2:
8774         case OP_ATOMIC_LOAD_I4:
8775         case OP_ATOMIC_LOAD_I8:
8776         case OP_ATOMIC_LOAD_U1:
8777         case OP_ATOMIC_LOAD_U2:
8778         case OP_ATOMIC_LOAD_U4:
8779         case OP_ATOMIC_LOAD_U8:
8780         case OP_ATOMIC_LOAD_R4:
8781         case OP_ATOMIC_LOAD_R8:
8782         case OP_ATOMIC_STORE_I1:
8783         case OP_ATOMIC_STORE_I2:
8784         case OP_ATOMIC_STORE_I4:
8785         case OP_ATOMIC_STORE_I8:
8786         case OP_ATOMIC_STORE_U1:
8787         case OP_ATOMIC_STORE_U2:
8788         case OP_ATOMIC_STORE_U4:
8789         case OP_ATOMIC_STORE_U8:
8790         case OP_ATOMIC_STORE_R4:
8791         case OP_ATOMIC_STORE_R8:
8792                 return TRUE;
8793         default:
8794                 return FALSE;
8795         }
8796 }
8797
8798 #if defined(ENABLE_GSHAREDVT)
8799
8800 #include "../../../mono-extensions/mono/mini/mini-amd64-gsharedvt.c"
8801
8802 #endif /* !MONOTOUCH */