mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 /*
  72  * The code generated for sequence points reads from this location, which is
  73  * made read-only when single stepping is enabled.
  74  */
  75 static gpointer ss_trigger_page;
  76
  77 /* Enabled breakpoints read from this trigger page */
  78 static gpointer bp_trigger_page;
  79
  80 /* The size of the breakpoint sequence */
  81 static int breakpoint_size;
  82
  83 /* The size of the breakpoint instruction causing the actual fault */
  84 static int breakpoint_fault_size;
  85
  86 /* The size of the single step instruction causing the actual fault */
  87 static int single_step_fault_size;
  88
  89 /* The single step trampoline */
  90 static gpointer ss_trampoline;
  91
  92 /* Offset between fp and the first argument in the callee */
  93 #define ARGS_OFFSET 16
  94 #define GP_SCRATCH_REG AMD64_R11
  95
  96 /*
  97  * AMD64 register usage:
  98  * - callee saved registers are used for global register allocation
  99  * - %r11 is used for materializing 64 bit constants in opcodes
 100  * - the rest is used for local allocation
 101  */
 102
 103 /*
 104  * Floating point comparison results:
 105  *                  ZF PF CF
 106  * A > B            0  0  0
 107  * A < B            0  0  1
 108  * A = B            1  0  0
 109  * A > B            0  0  0
 110  * UNORDERED        1  1  1
 111  */
 112
 113 const char*
 114 mono_arch_regname (int reg)
 115 {
 116         switch (reg) {
 117         case AMD64_RAX: return "%rax";
 118         case AMD64_RBX: return "%rbx";
 119         case AMD64_RCX: return "%rcx";
 120         case AMD64_RDX: return "%rdx";
 121         case AMD64_RSP: return "%rsp";
 122         case AMD64_RBP: return "%rbp";
 123         case AMD64_RDI: return "%rdi";
 124         case AMD64_RSI: return "%rsi";
 125         case AMD64_R8: return "%r8";
 126         case AMD64_R9: return "%r9";
 127         case AMD64_R10: return "%r10";
 128         case AMD64_R11: return "%r11";
 129         case AMD64_R12: return "%r12";
 130         case AMD64_R13: return "%r13";
 131         case AMD64_R14: return "%r14";
 132         case AMD64_R15: return "%r15";
 133         }
 134         return "unknown";
 135 }
 136
 137 static const char * packed_xmmregs [] = {
 138         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 139         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 140 };
 141
 142 static const char * single_xmmregs [] = {
 143         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 144         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 145 };
 146
 147 const char*
 148 mono_arch_fregname (int reg)
 149 {
 150         if (reg < AMD64_XMM_NREG)
 151                 return single_xmmregs [reg];
 152         else
 153                 return "unknown";
 154 }
 155
 156 const char *
 157 mono_arch_xregname (int reg)
 158 {
 159         if (reg < AMD64_XMM_NREG)
 160                 return packed_xmmregs [reg];
 161         else
 162                 return "unknown";
 163 }
 164
 165 static gboolean
 166 debug_omit_fp (void)
 167 {
 168 #if 0
 169         return mono_debug_count ();
 170 #else
 171         return TRUE;
 172 #endif
 173 }
 174
 175 static inline gboolean
 176 amd64_is_near_call (guint8 *code)
 177 {
 178         /* Skip REX */
 179         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 180                 code += 1;
 181
 182         return code [0] == 0xe8;
 183 }
 184
 185 #ifdef __native_client_codegen__
 186
 187 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 188 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 189 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 190 /* We only want to force bundle alignment for the top level instruction,    */
 191 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 192 static MonoNativeTlsKey nacl_instruction_depth;
 193
 194 static MonoNativeTlsKey nacl_rex_tag;
 195 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 196
 197 void
 198 amd64_nacl_clear_legacy_prefix_tag ()
 199 {
 200         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 201 }
 202
 203 void
 204 amd64_nacl_tag_legacy_prefix (guint8* code)
 205 {
 206         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 207                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 208 }
 209
 210 void
 211 amd64_nacl_tag_rex (guint8* code)
 212 {
 213         mono_native_tls_set_value (nacl_rex_tag, code);
 214 }
 215
 216 guint8*
 217 amd64_nacl_get_legacy_prefix_tag ()
 218 {
 219         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 220 }
 221
 222 guint8*
 223 amd64_nacl_get_rex_tag ()
 224 {
 225         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 226 }
 227
 228 /* Increment the instruction "depth" described above */
 229 void
 230 amd64_nacl_instruction_pre ()
 231 {
 232         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 233         depth++;
 234         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 235 }
 236
 237 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 238 /* alignment if depth == 0 (top level instruction)                          */
 239 /* IN: start, end    pointers to instruction beginning and end              */
 240 /* OUT: start, end   pointers to beginning and end after possible alignment */
 241 /* GLOBALS: nacl_instruction_depth     defined above                        */
 242 void
 243 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 244 {
 245         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 246         depth--;
 247         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 248
 249         g_assert ( depth >= 0 );
 250         if (depth == 0) {
 251                 uintptr_t space_in_block;
 252                 uintptr_t instlen;
 253                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 254                 /* if legacy prefix is present, and if it was emitted before */
 255                 /* the start of the instruction sequence, adjust the start   */
 256                 if (prefix != NULL && prefix < *start) {
 257                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 258                         *start = prefix;
 259                 }
 260                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 261                 instlen = (uintptr_t)(*end - *start);
 262                 /* Only check for instructions which are less than        */
 263                 /* kNaClAlignment. The only instructions that should ever */
 264                 /* be that long are call sequences, which are already     */
 265                 /* padded out to align the return to the next bundle.     */
 266                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 267                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 268                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 269                         const size_t length = (size_t)((*end)-(*start));
 270                         g_assert (length < MAX_NACL_INST_LENGTH);
 271
 272                         memcpy (copy_of_instruction, *start, length);
 273                         *start = mono_arch_nacl_pad (*start, space_in_block);
 274                         memcpy (*start, copy_of_instruction, length);
 275                         *end = *start + length;
 276                 }
 277                 amd64_nacl_clear_legacy_prefix_tag ();
 278                 amd64_nacl_tag_rex (NULL);
 279         }
 280 }
 281
 282 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 283 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 284 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 285 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 286 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 287 /* IN:      code                                                            */
 288 /*             pointer to current instruction stream (in the                */
 289 /*             middle of an instruction, after opcode is emitted)           */
 290 /*          basereg/offset/dreg                                             */
 291 /*             operands of normal membase address                           */
 292 /* OUT:     code                                                            */
 293 /*             pointer to the end of the membase/memindex emit              */
 294 /* GLOBALS: nacl_rex_tag                                                    */
 295 /*             position in instruction stream that rex prefix was emitted   */
 296 /*          nacl_legacy_prefix_tag                                          */
 297 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 298 void
 299 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 300 {
 301         gint8 true_basereg = basereg;
 302
 303         /* Cache these values, they might change  */
 304         /* as new instructions are emitted below. */
 305         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 306         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 307
 308         /* 'basereg' is given masked to 0x7 at this point, so check */
 309         /* the rex prefix to see if this is an extended register.   */
 310         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 311                 true_basereg |= 0x8;
 312         }
 313
 314 #define X86_LEA_OPCODE (0x8D)
 315
 316         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 317                 guint8* old_instruction_start;
 318
 319                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 320                 /* 32-bits of the old base register (new index register)     */
 321                 guint8 buf[32];
 322                 guint8* buf_ptr = buf;
 323                 size_t insert_len;
 324
 325                 g_assert (rex_tag != NULL);
 326
 327                 if (IS_REX(*rex_tag)) {
 328                         /* The old rex.B should be the new rex.X */
 329                         if (*rex_tag & AMD64_REX_B) {
 330                                 *rex_tag |= AMD64_REX_X;
 331                         }
 332                         /* Since our new base is %r15 set rex.B */
 333                         *rex_tag |= AMD64_REX_B;
 334                 } else {
 335                         /* Shift the instruction by one byte  */
 336                         /* so we can insert a rex prefix      */
 337                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 338                         *code += 1;
 339                         /* New rex prefix only needs rex.B for %r15 base */
 340                         *rex_tag = AMD64_REX(AMD64_REX_B);
 341                 }
 342
 343                 if (legacy_prefix_tag) {
 344                         old_instruction_start = legacy_prefix_tag;
 345                 } else {
 346                         old_instruction_start = rex_tag;
 347                 }
 348
 349                 /* Clears the upper 32-bits of the previous base register */
 350                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 351                 insert_len = buf_ptr - buf;
 352
 353                 /* Move the old instruction forward to make */
 354                 /* room for 'mov' stored in 'buf_ptr'       */
 355                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 356                 *code += insert_len;
 357                 memcpy (old_instruction_start, buf, insert_len);
 358
 359                 /* Sandboxed replacement for the normal membase_emit */
 360                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 361
 362         } else {
 363                 /* Normal default behavior, emit membase memory location */
 364                 x86_membase_emit_body (*code, dreg, basereg, offset);
 365         }
 366 }
 367
 368
 369 static inline unsigned char*
 370 amd64_skip_nops (unsigned char* code)
 371 {
 372         guint8 in_nop;
 373         do {
 374                 in_nop = 0;
 375                 if (   code[0] == 0x90) {
 376                         in_nop = 1;
 377                         code += 1;
 378                 }
 379                 if (   code[0] == 0x66 && code[1] == 0x90) {
 380                         in_nop = 1;
 381                         code += 2;
 382                 }
 383                 if (code[0] == 0x0f && code[1] == 0x1f
 384                  && code[2] == 0x00) {
 385                         in_nop = 1;
 386                         code += 3;
 387                 }
 388                 if (code[0] == 0x0f && code[1] == 0x1f
 389                  && code[2] == 0x40 && code[3] == 0x00) {
 390                         in_nop = 1;
 391                         code += 4;
 392                 }
 393                 if (code[0] == 0x0f && code[1] == 0x1f
 394                  && code[2] == 0x44 && code[3] == 0x00
 395                  && code[4] == 0x00) {
 396                         in_nop = 1;
 397                         code += 5;
 398                 }
 399                 if (code[0] == 0x66 && code[1] == 0x0f
 400                  && code[2] == 0x1f && code[3] == 0x44
 401                  && code[4] == 0x00 && code[5] == 0x00) {
 402                         in_nop = 1;
 403                         code += 6;
 404                 }
 405                 if (code[0] == 0x0f && code[1] == 0x1f
 406                  && code[2] == 0x80 && code[3] == 0x00
 407                  && code[4] == 0x00 && code[5] == 0x00
 408                  && code[6] == 0x00) {
 409                         in_nop = 1;
 410                         code += 7;
 411                 }
 412                 if (code[0] == 0x0f && code[1] == 0x1f
 413                  && code[2] == 0x84 && code[3] == 0x00
 414                  && code[4] == 0x00 && code[5] == 0x00
 415                  && code[6] == 0x00 && code[7] == 0x00) {
 416                         in_nop = 1;
 417                         code += 8;
 418                 }
 419         } while ( in_nop );
 420         return code;
 421 }
 422
 423 guint8*
 424 mono_arch_nacl_skip_nops (guint8* code)
 425 {
 426   return amd64_skip_nops(code);
 427 }
 428
 429 #endif /*__native_client_codegen__*/
 430
 431 static inline void
 432 amd64_patch (unsigned char* code, gpointer target)
 433 {
 434         guint8 rex = 0;
 435
 436 #ifdef __native_client_codegen__
 437         code = amd64_skip_nops (code);
 438 #endif
 439 #if defined(__native_client_codegen__) && defined(__native_client__)
 440         if (nacl_is_code_address (code)) {
 441                 /* For tail calls, code is patched after being installed */
 442                 /* but not through the normal "patch callsite" method.   */
 443                 unsigned char buf[kNaClAlignment];
 444                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 445                 int ret;
 446                 memcpy (buf, aligned_code, kNaClAlignment);
 447                 /* Patch a temp buffer of bundle size, */
 448                 /* then install to actual location.    */
 449                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 450                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 451                 g_assert (ret == 0);
 452                 return;
 453         }
 454         target = nacl_modify_patch_target (target);
 455 #endif
 456
 457         /* Skip REX */
 458         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 459                 rex = code [0];
 460                 code += 1;
 461         }
 462
 463         if ((code [0] & 0xf8) == 0xb8) {
 464                 /* amd64_set_reg_template */
 465                 *(guint64*)(code + 1) = (guint64)target;
 466         }
 467         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 468                 /* mov 0(%rip), %dreg */
 469                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 470         }
 471         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 472                 /* call *<OFFSET>(%rip) */
 473                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 474         }
 475         else if (code [0] == 0xe8) {
 476                 /* call <DISP> */
 477                 gint64 disp = (guint8*)target - (guint8*)code;
 478                 g_assert (amd64_is_imm32 (disp));
 479                 x86_patch (code, (unsigned char*)target);
 480         }
 481         else
 482                 x86_patch (code, (unsigned char*)target);
 483 }
 484
 485 void
 486 mono_amd64_patch (unsigned char* code, gpointer target)
 487 {
 488         amd64_patch (code, target);
 489 }
 490
 491 typedef enum {
 492         ArgInIReg,
 493         ArgInFloatSSEReg,
 494         ArgInDoubleSSEReg,
 495         ArgOnStack,
 496         ArgValuetypeInReg,
 497         ArgValuetypeAddrInIReg,
 498         ArgNone /* only in pair_storage */
 499 } ArgStorage;
 500
 501 typedef struct {
 502         gint16 offset;
 503         gint8  reg;
 504         ArgStorage storage;
 505
 506         /* Only if storage == ArgValuetypeInReg */
 507         ArgStorage pair_storage [2];
 508         gint8 pair_regs [2];
 509         /* The size of each pair */
 510         int pair_size [2];
 511         int nregs;
 512 } ArgInfo;
 513
 514 typedef struct {
 515         int nargs;
 516         guint32 stack_usage;
 517         guint32 reg_usage;
 518         guint32 freg_usage;
 519         gboolean need_stack_align;
 520         gboolean vtype_retaddr;
 521         /* The index of the vret arg in the argument list */
 522         int vret_arg_index;
 523         ArgInfo ret;
 524         ArgInfo sig_cookie;
 525         ArgInfo args [1];
 526 } CallInfo;
 527
 528 #define DEBUG(a) if (cfg->verbose_level > 1) a
 529
 530 #ifdef TARGET_WIN32
 531 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 532
 533 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #else
 535 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 536
 537  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 538 #endif
 539
 540 static void inline
 541 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 542 {
 543     ainfo->offset = *stack_size;
 544
 545     if (*gr >= PARAM_REGS) {
 546                 ainfo->storage = ArgOnStack;
 547                 /* Since the same stack slot size is used for all arg */
 548                 /*  types, it needs to be big enough to hold them all */
 549                 (*stack_size) += sizeof(mgreg_t);
 550     }
 551     else {
 552                 ainfo->storage = ArgInIReg;
 553                 ainfo->reg = param_regs [*gr];
 554                 (*gr) ++;
 555     }
 556 }
 557
 558 #ifdef TARGET_WIN32
 559 #define FLOAT_PARAM_REGS 4
 560 #else
 561 #define FLOAT_PARAM_REGS 8
 562 #endif
 563
 564 static void inline
 565 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 566 {
 567     ainfo->offset = *stack_size;
 568
 569     if (*gr >= FLOAT_PARAM_REGS) {
 570                 ainfo->storage = ArgOnStack;
 571                 /* Since the same stack slot size is used for both float */
 572                 /*  types, it needs to be big enough to hold them both */
 573                 (*stack_size) += sizeof(mgreg_t);
 574     }
 575     else {
 576                 /* A double register */
 577                 if (is_double)
 578                         ainfo->storage = ArgInDoubleSSEReg;
 579                 else
 580                         ainfo->storage = ArgInFloatSSEReg;
 581                 ainfo->reg = *gr;
 582                 (*gr) += 1;
 583     }
 584 }
 585
 586 typedef enum ArgumentClass {
 587         ARG_CLASS_NO_CLASS,
 588         ARG_CLASS_MEMORY,
 589         ARG_CLASS_INTEGER,
 590         ARG_CLASS_SSE
 591 } ArgumentClass;
 592
 593 static ArgumentClass
 594 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 595 {
 596         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 597         MonoType *ptype;
 598
 599         ptype = mini_type_get_underlying_type (gsctx, type);
 600         switch (ptype->type) {
 601         case MONO_TYPE_I1:
 602         case MONO_TYPE_U1:
 603         case MONO_TYPE_I2:
 604         case MONO_TYPE_U2:
 605         case MONO_TYPE_I4:
 606         case MONO_TYPE_U4:
 607         case MONO_TYPE_I:
 608         case MONO_TYPE_U:
 609         case MONO_TYPE_STRING:
 610         case MONO_TYPE_OBJECT:
 611         case MONO_TYPE_CLASS:
 612         case MONO_TYPE_SZARRAY:
 613         case MONO_TYPE_PTR:
 614         case MONO_TYPE_FNPTR:
 615         case MONO_TYPE_ARRAY:
 616         case MONO_TYPE_I8:
 617         case MONO_TYPE_U8:
 618                 class2 = ARG_CLASS_INTEGER;
 619                 break;
 620         case MONO_TYPE_R4:
 621         case MONO_TYPE_R8:
 622 #ifdef TARGET_WIN32
 623                 class2 = ARG_CLASS_INTEGER;
 624 #else
 625                 class2 = ARG_CLASS_SSE;
 626 #endif
 627                 break;
 628
 629         case MONO_TYPE_TYPEDBYREF:
 630                 g_assert_not_reached ();
 631
 632         case MONO_TYPE_GENERICINST:
 633                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 634                         class2 = ARG_CLASS_INTEGER;
 635                         break;
 636                 }
 637                 /* fall through */
 638         case MONO_TYPE_VALUETYPE: {
 639                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 640                 int i;
 641
 642                 for (i = 0; i < info->num_fields; ++i) {
 643                         class2 = class1;
 644                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 645                 }
 646                 break;
 647         }
 648         default:
 649                 g_assert_not_reached ();
 650         }
 651
 652         /* Merge */
 653         if (class1 == class2)
 654                 ;
 655         else if (class1 == ARG_CLASS_NO_CLASS)
 656                 class1 = class2;
 657         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 658                 class1 = ARG_CLASS_MEMORY;
 659         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 660                 class1 = ARG_CLASS_INTEGER;
 661         else
 662                 class1 = ARG_CLASS_SSE;
 663
 664         return class1;
 665 }
 666 #ifdef __native_client_codegen__
 667
 668 /* Default alignment for Native Client is 32-byte. */
 669 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 670
 671 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 672 /* Check that alignment doesn't cross an alignment boundary.             */
 673 guint8*
 674 mono_arch_nacl_pad(guint8 *code, int pad)
 675 {
 676         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 677
 678         if (pad == 0) return code;
 679         /* assertion: alignment cannot cross a block boundary */
 680         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 681                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 682         while (pad >= kMaxPadding) {
 683                 amd64_padding (code, kMaxPadding);
 684                 pad -= kMaxPadding;
 685         }
 686         if (pad != 0) amd64_padding (code, pad);
 687         return code;
 688 }
 689 #endif
 690
 691 static int
 692 count_fields_nested (MonoClass *klass)
 693 {
 694         MonoMarshalType *info;
 695         int i, count;
 696
 697         info = mono_marshal_load_type_info (klass);
 698         g_assert(info);
 699         count = 0;
 700         for (i = 0; i < info->num_fields; ++i) {
 701                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 702                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 703                 else
 704                         count ++;
 705         }
 706         return count;
 707 }
 708
 709 static int
 710 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 711 {
 712         MonoMarshalType *info;
 713         int i;
 714
 715         info = mono_marshal_load_type_info (klass);
 716         g_assert(info);
 717         for (i = 0; i < info->num_fields; ++i) {
 718                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 719                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 720                 } else {
 721                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 722                         fields [index].offset += offset;
 723                         index ++;
 724                 }
 725         }
 726         return index;
 727 }
 728
 729 static void
 730 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 731                            gboolean is_return,
 732                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 733 {
 734         guint32 size, quad, nquads, i, nfields;
 735         /* Keep track of the size used in each quad so we can */
 736         /* use the right size when copying args/return vars.  */
 737         guint32 quadsize [2] = {8, 8};
 738         ArgumentClass args [2];
 739         MonoMarshalType *info = NULL;
 740         MonoMarshalField *fields = NULL;
 741         MonoClass *klass;
 742         MonoGenericSharingContext tmp_gsctx;
 743         gboolean pass_on_stack = FALSE;
 744
 745         /*
 746          * The gsctx currently contains no data, it is only used for checking whenever
 747          * open types are allowed, some callers like mono_arch_get_argument_info ()
 748          * don't pass it to us, so work around that.
 749          */
 750         if (!gsctx)
 751                 gsctx = &tmp_gsctx;
 752
 753         klass = mono_class_from_mono_type (type);
 754         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 755 #ifndef TARGET_WIN32
 756         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 757                 /* We pass and return vtypes of size 8 in a register */
 758         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 759                 pass_on_stack = TRUE;
 760         }
 761 #else
 762         if (!sig->pinvoke) {
 763                 pass_on_stack = TRUE;
 764         }
 765 #endif
 766
 767         /* If this struct can't be split up naturally into 8-byte */
 768         /* chunks (registers), pass it on the stack.              */
 769         if (sig->pinvoke && !pass_on_stack) {
 770                 guint32 align;
 771                 guint32 field_size;
 772
 773                 info = mono_marshal_load_type_info (klass);
 774                 g_assert (info);
 775
 776                 /*
 777                  * Collect field information recursively to be able to
 778                  * handle nested structures.
 779                  */
 780                 nfields = count_fields_nested (klass);
 781                 fields = g_new0 (MonoMarshalField, nfields);
 782                 collect_field_info_nested (klass, fields, 0, 0);
 783
 784                 for (i = 0; i < nfields; ++i) {
 785                         field_size = mono_marshal_type_size (fields [i].field->type,
 786                                                            fields [i].mspec,
 787                                                            &align, TRUE, klass->unicode);
 788                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 789                                 pass_on_stack = TRUE;
 790                                 break;
 791                         }
 792                 }
 793         }
 794
 795         if (pass_on_stack) {
 796                 /* Allways pass in memory */
 797                 ainfo->offset = *stack_size;
 798                 *stack_size += ALIGN_TO (size, 8);
 799                 ainfo->storage = ArgOnStack;
 800
 801                 g_free (fields);
 802                 return;
 803         }
 804
 805         /* FIXME: Handle structs smaller than 8 bytes */
 806         //if ((size % 8) != 0)
 807         //      NOT_IMPLEMENTED;
 808
 809         if (size > 8)
 810                 nquads = 2;
 811         else
 812                 nquads = 1;
 813
 814         if (!sig->pinvoke) {
 815                 int n = mono_class_value_size (klass, NULL);
 816
 817                 quadsize [0] = n >= 8 ? 8 : n;
 818                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 819
 820                 /* Always pass in 1 or 2 integer registers */
 821                 args [0] = ARG_CLASS_INTEGER;
 822                 args [1] = ARG_CLASS_INTEGER;
 823                 /* Only the simplest cases are supported */
 824                 if (is_return && nquads != 1) {
 825                         args [0] = ARG_CLASS_MEMORY;
 826                         args [1] = ARG_CLASS_MEMORY;
 827                 }
 828         } else {
 829                 /*
 830                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 831                  * The X87 and SSEUP stuff is left out since there are no such types in
 832                  * the CLR.
 833                  */
 834                 g_assert (info);
 835                 g_assert (fields);
 836
 837 #ifndef TARGET_WIN32
 838                 if (info->native_size > 16) {
 839                         ainfo->offset = *stack_size;
 840                         *stack_size += ALIGN_TO (info->native_size, 8);
 841                         ainfo->storage = ArgOnStack;
 842
 843                         g_free (fields);
 844                         return;
 845                 }
 846 #else
 847                 switch (info->native_size) {
 848                 case 1: case 2: case 4: case 8:
 849                         break;
 850                 default:
 851                         if (is_return) {
 852                                 ainfo->storage = ArgOnStack;
 853                                 ainfo->offset = *stack_size;
 854                                 *stack_size += ALIGN_TO (info->native_size, 8);
 855                         }
 856                         else {
 857                                 ainfo->storage = ArgValuetypeAddrInIReg;
 858
 859                                 if (*gr < PARAM_REGS) {
 860                                         ainfo->pair_storage [0] = ArgInIReg;
 861                                         ainfo->pair_regs [0] = param_regs [*gr];
 862                                         (*gr) ++;
 863                                 }
 864                                 else {
 865                                         ainfo->pair_storage [0] = ArgOnStack;
 866                                         ainfo->offset = *stack_size;
 867                                         *stack_size += 8;
 868                                 }
 869                         }
 870
 871                         g_free (fields);
 872                         return;
 873                 }
 874 #endif
 875
 876                 args [0] = ARG_CLASS_NO_CLASS;
 877                 args [1] = ARG_CLASS_NO_CLASS;
 878                 for (quad = 0; quad < nquads; ++quad) {
 879                         int size;
 880                         guint32 align;
 881                         ArgumentClass class1;
 882
 883                         if (nfields == 0)
 884                                 class1 = ARG_CLASS_MEMORY;
 885                         else
 886                                 class1 = ARG_CLASS_NO_CLASS;
 887                         for (i = 0; i < nfields; ++i) {
 888                                 size = mono_marshal_type_size (fields [i].field->type,
 889                                                                                            fields [i].mspec,
 890                                                                                            &align, TRUE, klass->unicode);
 891                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 892                                         /* Unaligned field */
 893                                         NOT_IMPLEMENTED;
 894                                 }
 895
 896                                 /* Skip fields in other quad */
 897                                 if ((quad == 0) && (fields [i].offset >= 8))
 898                                         continue;
 899                                 if ((quad == 1) && (fields [i].offset < 8))
 900                                         continue;
 901
 902                                 /* How far into this quad this data extends.*/
 903                                 /* (8 is size of quad) */
 904                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 905
 906                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 907                         }
 908                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 909                         args [quad] = class1;
 910                 }
 911         }
 912
 913         g_free (fields);
 914
 915         /* Post merger cleanup */
 916         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 917                 args [0] = args [1] = ARG_CLASS_MEMORY;
 918
 919         /* Allocate registers */
 920         {
 921                 int orig_gr = *gr;
 922                 int orig_fr = *fr;
 923
 924                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 925                         quadsize [0] ++;
 926                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 927                         quadsize [1] ++;
 928
 929                 ainfo->storage = ArgValuetypeInReg;
 930                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 931                 g_assert (quadsize [0] <= 8);
 932                 g_assert (quadsize [1] <= 8);
 933                 ainfo->pair_size [0] = quadsize [0];
 934                 ainfo->pair_size [1] = quadsize [1];
 935                 ainfo->nregs = nquads;
 936                 for (quad = 0; quad < nquads; ++quad) {
 937                         switch (args [quad]) {
 938                         case ARG_CLASS_INTEGER:
 939                                 if (*gr >= PARAM_REGS)
 940                                         args [quad] = ARG_CLASS_MEMORY;
 941                                 else {
 942                                         ainfo->pair_storage [quad] = ArgInIReg;
 943                                         if (is_return)
 944                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 945                                         else
 946                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 947                                         (*gr) ++;
 948                                 }
 949                                 break;
 950                         case ARG_CLASS_SSE:
 951                                 if (*fr >= FLOAT_PARAM_REGS)
 952                                         args [quad] = ARG_CLASS_MEMORY;
 953                                 else {
 954                                         if (quadsize[quad] <= 4)
 955                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 956                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 957                                         ainfo->pair_regs [quad] = *fr;
 958                                         (*fr) ++;
 959                                 }
 960                                 break;
 961                         case ARG_CLASS_MEMORY:
 962                                 break;
 963                         default:
 964                                 g_assert_not_reached ();
 965                         }
 966                 }
 967
 968                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 969                         /* Revert possible register assignments */
 970                         *gr = orig_gr;
 971                         *fr = orig_fr;
 972
 973                         ainfo->offset = *stack_size;
 974                         if (sig->pinvoke)
 975                                 *stack_size += ALIGN_TO (info->native_size, 8);
 976                         else
 977                                 *stack_size += nquads * sizeof(mgreg_t);
 978                         ainfo->storage = ArgOnStack;
 979                 }
 980         }
 981 }
 982
 983 /*
 984  * get_call_info:
 985  *
 986  *  Obtain information about a call according to the calling convention.
 987  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 988  * Draft Version 0.23" document for more information.
 989  */
 990 static CallInfo*
 991 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 992 {
 993         guint32 i, gr, fr, pstart;
 994         MonoType *ret_type;
 995         int n = sig->hasthis + sig->param_count;
 996         guint32 stack_size = 0;
 997         CallInfo *cinfo;
 998         gboolean is_pinvoke = sig->pinvoke;
 999
1000         if (mp)
1001                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002         else
1003                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1004
1005         cinfo->nargs = n;
1006
1007         gr = 0;
1008         fr = 0;
1009
1010 #ifdef TARGET_WIN32
1011         /* Reserve space where the callee can save the argument registers */
1012         stack_size = 4 * sizeof (mgreg_t);
1013 #endif
1014
1015         /* return value */
1016         ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1017         switch (ret_type->type) {
1018         case MONO_TYPE_I1:
1019         case MONO_TYPE_U1:
1020         case MONO_TYPE_I2:
1021         case MONO_TYPE_U2:
1022         case MONO_TYPE_I4:
1023         case MONO_TYPE_U4:
1024         case MONO_TYPE_I:
1025         case MONO_TYPE_U:
1026         case MONO_TYPE_PTR:
1027         case MONO_TYPE_FNPTR:
1028         case MONO_TYPE_CLASS:
1029         case MONO_TYPE_OBJECT:
1030         case MONO_TYPE_SZARRAY:
1031         case MONO_TYPE_ARRAY:
1032         case MONO_TYPE_STRING:
1033                 cinfo->ret.storage = ArgInIReg;
1034                 cinfo->ret.reg = AMD64_RAX;
1035                 break;
1036         case MONO_TYPE_U8:
1037         case MONO_TYPE_I8:
1038                 cinfo->ret.storage = ArgInIReg;
1039                 cinfo->ret.reg = AMD64_RAX;
1040                 break;
1041         case MONO_TYPE_R4:
1042                 cinfo->ret.storage = ArgInFloatSSEReg;
1043                 cinfo->ret.reg = AMD64_XMM0;
1044                 break;
1045         case MONO_TYPE_R8:
1046                 cinfo->ret.storage = ArgInDoubleSSEReg;
1047                 cinfo->ret.reg = AMD64_XMM0;
1048                 break;
1049         case MONO_TYPE_GENERICINST:
1050                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1051                         cinfo->ret.storage = ArgInIReg;
1052                         cinfo->ret.reg = AMD64_RAX;
1053                         break;
1054                 }
1055                 /* fall through */
1056 #if defined( __native_client_codegen__ )
1057         case MONO_TYPE_TYPEDBYREF:
1058 #endif
1059         case MONO_TYPE_VALUETYPE: {
1060                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1061
1062                 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1063                 if (cinfo->ret.storage == ArgOnStack) {
1064                         cinfo->vtype_retaddr = TRUE;
1065                         /* The caller passes the address where the value is stored */
1066                 }
1067                 break;
1068         }
1069 #if !defined( __native_client_codegen__ )
1070         case MONO_TYPE_TYPEDBYREF:
1071                 /* Same as a valuetype with size 24 */
1072                 cinfo->vtype_retaddr = TRUE;
1073                 break;
1074 #endif
1075         case MONO_TYPE_VOID:
1076                 break;
1077         default:
1078                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1079         }
1080
1081         pstart = 0;
1082         /*
1083          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1084          * the first argument, allowing 'this' to be always passed in the first arg reg.
1085          * Also do this if the first argument is a reference type, since virtual calls
1086          * are sometimes made using calli without sig->hasthis set, like in the delegate
1087          * invoke wrappers.
1088          */
1089         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1090                 if (sig->hasthis) {
1091                         add_general (&gr, &stack_size, cinfo->args + 0);
1092                 } else {
1093                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1094                         pstart = 1;
1095                 }
1096                 add_general (&gr, &stack_size, &cinfo->ret);
1097                 cinfo->vret_arg_index = 1;
1098         } else {
1099                 /* this */
1100                 if (sig->hasthis)
1101                         add_general (&gr, &stack_size, cinfo->args + 0);
1102
1103                 if (cinfo->vtype_retaddr)
1104                         add_general (&gr, &stack_size, &cinfo->ret);
1105         }
1106
1107         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1108                 gr = PARAM_REGS;
1109                 fr = FLOAT_PARAM_REGS;
1110
1111                 /* Emit the signature cookie just before the implicit arguments */
1112                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1113         }
1114
1115         for (i = pstart; i < sig->param_count; ++i) {
1116                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1117                 MonoType *ptype;
1118
1119 #ifdef TARGET_WIN32
1120                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1121                 if (gr > fr)
1122                         fr = gr;
1123                 else if (fr > gr)
1124                         gr = fr;
1125 #endif
1126
1127                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1128                         /* We allways pass the sig cookie on the stack for simplicity */
1129                         /*
1130                          * Prevent implicit arguments + the sig cookie from being passed
1131                          * in registers.
1132                          */
1133                         gr = PARAM_REGS;
1134                         fr = FLOAT_PARAM_REGS;
1135
1136                         /* Emit the signature cookie just before the implicit arguments */
1137                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1138                 }
1139
1140                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1141                 switch (ptype->type) {
1142                 case MONO_TYPE_I1:
1143                 case MONO_TYPE_U1:
1144                         add_general (&gr, &stack_size, ainfo);
1145                         break;
1146                 case MONO_TYPE_I2:
1147                 case MONO_TYPE_U2:
1148                         add_general (&gr, &stack_size, ainfo);
1149                         break;
1150                 case MONO_TYPE_I4:
1151                 case MONO_TYPE_U4:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I:
1155                 case MONO_TYPE_U:
1156                 case MONO_TYPE_PTR:
1157                 case MONO_TYPE_FNPTR:
1158                 case MONO_TYPE_CLASS:
1159                 case MONO_TYPE_OBJECT:
1160                 case MONO_TYPE_STRING:
1161                 case MONO_TYPE_SZARRAY:
1162                 case MONO_TYPE_ARRAY:
1163                         add_general (&gr, &stack_size, ainfo);
1164                         break;
1165                 case MONO_TYPE_GENERICINST:
1166                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1167                                 add_general (&gr, &stack_size, ainfo);
1168                                 break;
1169                         }
1170                         /* fall through */
1171                 case MONO_TYPE_VALUETYPE:
1172                 case MONO_TYPE_TYPEDBYREF:
1173                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1174                         break;
1175                 case MONO_TYPE_U8:
1176
1177                 case MONO_TYPE_I8:
1178                         add_general (&gr, &stack_size, ainfo);
1179                         break;
1180                 case MONO_TYPE_R4:
1181                         add_float (&fr, &stack_size, ainfo, FALSE);
1182                         break;
1183                 case MONO_TYPE_R8:
1184                         add_float (&fr, &stack_size, ainfo, TRUE);
1185                         break;
1186                 default:
1187                         g_assert_not_reached ();
1188                 }
1189         }
1190
1191         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1192                 gr = PARAM_REGS;
1193                 fr = FLOAT_PARAM_REGS;
1194
1195                 /* Emit the signature cookie just before the implicit arguments */
1196                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1197         }
1198
1199         cinfo->stack_usage = stack_size;
1200         cinfo->reg_usage = gr;
1201         cinfo->freg_usage = fr;
1202         return cinfo;
1203 }
1204
1205 /*
1206  * mono_arch_get_argument_info:
1207  * @csig:  a method signature
1208  * @param_count: the number of parameters to consider
1209  * @arg_info: an array to store the result infos
1210  *
1211  * Gathers information on parameters such as size, alignment and
1212  * padding. arg_info should be large enought to hold param_count + 1 entries.
1213  *
1214  * Returns the size of the argument area on the stack.
1215  */
1216 int
1217 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1218 {
1219         int k;
1220         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1221         guint32 args_size = cinfo->stack_usage;
1222
1223         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1224         if (csig->hasthis) {
1225                 arg_info [0].offset = 0;
1226         }
1227
1228         for (k = 0; k < param_count; k++) {
1229                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1230                 /* FIXME: */
1231                 arg_info [k + 1].size = 0;
1232         }
1233
1234         g_free (cinfo);
1235
1236         return args_size;
1237 }
1238
1239 gboolean
1240 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1241 {
1242         CallInfo *c1, *c2;
1243         gboolean res;
1244         MonoType *callee_ret;
1245
1246         c1 = get_call_info (NULL, NULL, caller_sig);
1247         c2 = get_call_info (NULL, NULL, callee_sig);
1248         res = c1->stack_usage >= c2->stack_usage;
1249         callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1250         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1251                 /* An address on the callee's stack is passed as the first argument */
1252                 res = FALSE;
1253
1254         g_free (c1);
1255         g_free (c2);
1256
1257         return res;
1258 }
1259
1260 /*
1261  * Initialize the cpu to execute managed code.
1262  */
1263 void
1264 mono_arch_cpu_init (void)
1265 {
1266 #ifndef _MSC_VER
1267         guint16 fpcw;
1268
1269         /* spec compliance requires running with double precision */
1270         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1271         fpcw &= ~X86_FPCW_PRECC_MASK;
1272         fpcw |= X86_FPCW_PREC_DOUBLE;
1273         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275 #else
1276         /* TODO: This is crashing on Win64 right now.
1277         * _control87 (_PC_53, MCW_PC);
1278         */
1279 #endif
1280 }
1281
1282 /*
1283  * Initialize architecture specific code.
1284  */
1285 void
1286 mono_arch_init (void)
1287 {
1288         int flags;
1289
1290         mono_mutex_init_recursive (&mini_arch_mutex);
1291 #if defined(__native_client_codegen__)
1292         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1293         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1294         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1295         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1296 #endif
1297
1298 #ifdef MONO_ARCH_NOMAP32BIT
1299         flags = MONO_MMAP_READ;
1300         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1301         breakpoint_size = 13;
1302         breakpoint_fault_size = 3;
1303 #else
1304         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1305         /* amd64_mov_reg_mem () */
1306         breakpoint_size = 8;
1307         breakpoint_fault_size = 8;
1308 #endif
1309
1310         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1311         single_step_fault_size = 4;
1312
1313         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1314         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1315         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1316
1317         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1318         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1319         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1320 }
1321
1322 /*
1323  * Cleanup architecture specific code.
1324  */
1325 void
1326 mono_arch_cleanup (void)
1327 {
1328         mono_mutex_destroy (&mini_arch_mutex);
1329 #if defined(__native_client_codegen__)
1330         mono_native_tls_free (nacl_instruction_depth);
1331         mono_native_tls_free (nacl_rex_tag);
1332         mono_native_tls_free (nacl_legacy_prefix_tag);
1333 #endif
1334 }
1335
1336 /*
1337  * This function returns the optimizations supported on this cpu.
1338  */
1339 guint32
1340 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1341 {
1342         guint32 opts = 0;
1343
1344         *exclude_mask = 0;
1345
1346         if (mono_hwcap_x86_has_cmov) {
1347                 opts |= MONO_OPT_CMOV;
1348
1349                 if (mono_hwcap_x86_has_fcmov)
1350                         opts |= MONO_OPT_FCMOV;
1351                 else
1352                         *exclude_mask |= MONO_OPT_FCMOV;
1353         } else {
1354                 *exclude_mask |= MONO_OPT_CMOV;
1355         }
1356
1357         return opts;
1358 }
1359
1360 /*
1361  * This function test for all SSE functions supported.
1362  *
1363  * Returns a bitmask corresponding to all supported versions.
1364  *
1365  */
1366 guint32
1367 mono_arch_cpu_enumerate_simd_versions (void)
1368 {
1369         guint32 sse_opts = 0;
1370
1371         if (mono_hwcap_x86_has_sse1)
1372                 sse_opts |= SIMD_VERSION_SSE1;
1373
1374         if (mono_hwcap_x86_has_sse2)
1375                 sse_opts |= SIMD_VERSION_SSE2;
1376
1377         if (mono_hwcap_x86_has_sse3)
1378                 sse_opts |= SIMD_VERSION_SSE3;
1379
1380         if (mono_hwcap_x86_has_ssse3)
1381                 sse_opts |= SIMD_VERSION_SSSE3;
1382
1383         if (mono_hwcap_x86_has_sse41)
1384                 sse_opts |= SIMD_VERSION_SSE41;
1385
1386         if (mono_hwcap_x86_has_sse42)
1387                 sse_opts |= SIMD_VERSION_SSE42;
1388
1389         if (mono_hwcap_x86_has_sse4a)
1390                 sse_opts |= SIMD_VERSION_SSE4a;
1391
1392         return sse_opts;
1393 }
1394
1395 #ifndef DISABLE_JIT
1396
1397 GList *
1398 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1399 {
1400         GList *vars = NULL;
1401         int i;
1402
1403         for (i = 0; i < cfg->num_varinfo; i++) {
1404                 MonoInst *ins = cfg->varinfo [i];
1405                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1406
1407                 /* unused vars */
1408                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1409                         continue;
1410
1411                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1412                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1413                         continue;
1414
1415                 if (mono_is_regsize_var (ins->inst_vtype)) {
1416                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1417                         g_assert (i == vmv->idx);
1418                         vars = g_list_prepend (vars, vmv);
1419                 }
1420         }
1421
1422         vars = mono_varlist_sort (cfg, vars, 0);
1423
1424         return vars;
1425 }
1426
1427 /**
1428  * mono_arch_compute_omit_fp:
1429  *
1430  *   Determine whenever the frame pointer can be eliminated.
1431  */
1432 static void
1433 mono_arch_compute_omit_fp (MonoCompile *cfg)
1434 {
1435         MonoMethodSignature *sig;
1436         MonoMethodHeader *header;
1437         int i, locals_size;
1438         CallInfo *cinfo;
1439
1440         if (cfg->arch.omit_fp_computed)
1441                 return;
1442
1443         header = cfg->header;
1444
1445         sig = mono_method_signature (cfg->method);
1446
1447         if (!cfg->arch.cinfo)
1448                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1449         cinfo = cfg->arch.cinfo;
1450
1451         /*
1452          * FIXME: Remove some of the restrictions.
1453          */
1454         cfg->arch.omit_fp = TRUE;
1455         cfg->arch.omit_fp_computed = TRUE;
1456
1457 #ifdef __native_client_codegen__
1458         /* NaCl modules may not change the value of RBP, so it cannot be */
1459         /* used as a normal register, but it can be used as a frame pointer*/
1460         cfg->disable_omit_fp = TRUE;
1461         cfg->arch.omit_fp = FALSE;
1462 #endif
1463
1464         if (cfg->disable_omit_fp)
1465                 cfg->arch.omit_fp = FALSE;
1466
1467         if (!debug_omit_fp ())
1468                 cfg->arch.omit_fp = FALSE;
1469         /*
1470         if (cfg->method->save_lmf)
1471                 cfg->arch.omit_fp = FALSE;
1472         */
1473         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1474                 cfg->arch.omit_fp = FALSE;
1475         if (header->num_clauses)
1476                 cfg->arch.omit_fp = FALSE;
1477         if (cfg->param_area)
1478                 cfg->arch.omit_fp = FALSE;
1479         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1480                 cfg->arch.omit_fp = FALSE;
1481         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1482                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1483                 cfg->arch.omit_fp = FALSE;
1484         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1485                 ArgInfo *ainfo = &cinfo->args [i];
1486
1487                 if (ainfo->storage == ArgOnStack) {
1488                         /*
1489                          * The stack offset can only be determined when the frame
1490                          * size is known.
1491                          */
1492                         cfg->arch.omit_fp = FALSE;
1493                 }
1494         }
1495
1496         locals_size = 0;
1497         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1498                 MonoInst *ins = cfg->varinfo [i];
1499                 int ialign;
1500
1501                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1502         }
1503 }
1504
1505 GList *
1506 mono_arch_get_global_int_regs (MonoCompile *cfg)
1507 {
1508         GList *regs = NULL;
1509
1510         mono_arch_compute_omit_fp (cfg);
1511
1512         if (cfg->arch.omit_fp)
1513                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1514
1515         /* We use the callee saved registers for global allocation */
1516         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1517         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1518         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1519         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1520 #ifndef __native_client_codegen__
1521         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1522 #endif
1523 #ifdef TARGET_WIN32
1524         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1525         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1526 #endif
1527
1528         return regs;
1529 }
1530
1531 GList*
1532 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1533 {
1534         GList *regs = NULL;
1535         int i;
1536
1537         /* All XMM registers */
1538         for (i = 0; i < 16; ++i)
1539                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1540
1541         return regs;
1542 }
1543
1544 GList*
1545 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1546 {
1547         static GList *r = NULL;
1548
1549         if (r == NULL) {
1550                 GList *regs = NULL;
1551
1552                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1553                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1554                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1555                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1556                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1557 #ifndef __native_client_codegen__
1558                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1559 #endif
1560
1561                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1562                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1563                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1564                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1565                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1566                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1567                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1568                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1569
1570                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1571         }
1572
1573         return r;
1574 }
1575
1576 GList*
1577 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1578 {
1579         int i;
1580         static GList *r = NULL;
1581
1582         if (r == NULL) {
1583                 GList *regs = NULL;
1584
1585                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1586                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1587
1588                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1589         }
1590
1591         return r;
1592 }
1593
1594 /*
1595  * mono_arch_regalloc_cost:
1596  *
1597  *  Return the cost, in number of memory references, of the action of
1598  * allocating the variable VMV into a register during global register
1599  * allocation.
1600  */
1601 guint32
1602 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1603 {
1604         MonoInst *ins = cfg->varinfo [vmv->idx];
1605
1606         if (cfg->method->save_lmf)
1607                 /* The register is already saved */
1608                 /* substract 1 for the invisible store in the prolog */
1609                 return (ins->opcode == OP_ARG) ? 0 : 1;
1610         else
1611                 /* push+pop */
1612                 return (ins->opcode == OP_ARG) ? 1 : 2;
1613 }
1614
1615 /*
1616  * mono_arch_fill_argument_info:
1617  *
1618  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1619  * of the method.
1620  */
1621 void
1622 mono_arch_fill_argument_info (MonoCompile *cfg)
1623 {
1624         MonoType *sig_ret;
1625         MonoMethodSignature *sig;
1626         MonoInst *ins;
1627         int i;
1628         CallInfo *cinfo;
1629
1630         sig = mono_method_signature (cfg->method);
1631
1632         cinfo = cfg->arch.cinfo;
1633         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1634
1635         /*
1636          * Contrary to mono_arch_allocate_vars (), the information should describe
1637          * where the arguments are at the beginning of the method, not where they can be
1638          * accessed during the execution of the method. The later makes no sense for the
1639          * global register allocator, since a variable can be in more than one location.
1640          */
1641         if (sig_ret->type != MONO_TYPE_VOID) {
1642                 switch (cinfo->ret.storage) {
1643                 case ArgInIReg:
1644                 case ArgInFloatSSEReg:
1645                 case ArgInDoubleSSEReg:
1646                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1647                                 cfg->vret_addr->opcode = OP_REGVAR;
1648                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1649                         }
1650                         else {
1651                                 cfg->ret->opcode = OP_REGVAR;
1652                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1653                         }
1654                         break;
1655                 case ArgValuetypeInReg:
1656                         cfg->ret->opcode = OP_REGOFFSET;
1657                         cfg->ret->inst_basereg = -1;
1658                         cfg->ret->inst_offset = -1;
1659                         break;
1660                 default:
1661                         g_assert_not_reached ();
1662                 }
1663         }
1664
1665         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1666                 ArgInfo *ainfo = &cinfo->args [i];
1667
1668                 ins = cfg->args [i];
1669
1670                 switch (ainfo->storage) {
1671                 case ArgInIReg:
1672                 case ArgInFloatSSEReg:
1673                 case ArgInDoubleSSEReg:
1674                         ins->opcode = OP_REGVAR;
1675                         ins->inst_c0 = ainfo->reg;
1676                         break;
1677                 case ArgOnStack:
1678                         ins->opcode = OP_REGOFFSET;
1679                         ins->inst_basereg = -1;
1680                         ins->inst_offset = -1;
1681                         break;
1682                 case ArgValuetypeInReg:
1683                         /* Dummy */
1684                         ins->opcode = OP_NOP;
1685                         break;
1686                 default:
1687                         g_assert_not_reached ();
1688                 }
1689         }
1690 }
1691
1692 void
1693 mono_arch_allocate_vars (MonoCompile *cfg)
1694 {
1695         MonoType *sig_ret;
1696         MonoMethodSignature *sig;
1697         MonoInst *ins;
1698         int i, offset;
1699         guint32 locals_stack_size, locals_stack_align;
1700         gint32 *offsets;
1701         CallInfo *cinfo;
1702
1703         sig = mono_method_signature (cfg->method);
1704
1705         cinfo = cfg->arch.cinfo;
1706         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1707
1708         mono_arch_compute_omit_fp (cfg);
1709
1710         /*
1711          * We use the ABI calling conventions for managed code as well.
1712          * Exception: valuetypes are only sometimes passed or returned in registers.
1713          */
1714
1715         /*
1716          * The stack looks like this:
1717          * <incoming arguments passed on the stack>
1718          * <return value>
1719          * <lmf/caller saved registers>
1720          * <locals>
1721          * <spill area>
1722          * <localloc area>  -> grows dynamically
1723          * <params area>
1724          */
1725
1726         if (cfg->arch.omit_fp) {
1727                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1728                 cfg->frame_reg = AMD64_RSP;
1729                 offset = 0;
1730         } else {
1731                 /* Locals are allocated backwards from %fp */
1732                 cfg->frame_reg = AMD64_RBP;
1733                 offset = 0;
1734         }
1735
1736         cfg->arch.saved_iregs = cfg->used_int_regs;
1737         if (cfg->method->save_lmf)
1738                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1739                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1740
1741         if (cfg->arch.omit_fp)
1742                 cfg->arch.reg_save_area_offset = offset;
1743         /* Reserve space for callee saved registers */
1744         for (i = 0; i < AMD64_NREG; ++i)
1745                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1746                         offset += sizeof(mgreg_t);
1747                 }
1748         if (!cfg->arch.omit_fp)
1749                 cfg->arch.reg_save_area_offset = -offset;
1750
1751         if (sig_ret->type != MONO_TYPE_VOID) {
1752                 switch (cinfo->ret.storage) {
1753                 case ArgInIReg:
1754                 case ArgInFloatSSEReg:
1755                 case ArgInDoubleSSEReg:
1756                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1757                                 /* The register is volatile */
1758                                 cfg->vret_addr->opcode = OP_REGOFFSET;
1759                                 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1760                                 if (cfg->arch.omit_fp) {
1761                                         cfg->vret_addr->inst_offset = offset;
1762                                         offset += 8;
1763                                 } else {
1764                                         offset += 8;
1765                                         cfg->vret_addr->inst_offset = -offset;
1766                                 }
1767                                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1768                                         printf ("vret_addr =");
1769                                         mono_print_ins (cfg->vret_addr);
1770                                 }
1771                         }
1772                         else {
1773                                 cfg->ret->opcode = OP_REGVAR;
1774                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1775                         }
1776                         break;
1777                 case ArgValuetypeInReg:
1778                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1779                         cfg->ret->opcode = OP_REGOFFSET;
1780                         cfg->ret->inst_basereg = cfg->frame_reg;
1781                         if (cfg->arch.omit_fp) {
1782                                 cfg->ret->inst_offset = offset;
1783                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1784                         } else {
1785                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1786                                 cfg->ret->inst_offset = - offset;
1787                         }
1788                         break;
1789                 default:
1790                         g_assert_not_reached ();
1791                 }
1792                 cfg->ret->dreg = cfg->ret->inst_c0;
1793         }
1794
1795         /* Allocate locals */
1796         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1797         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1798                 char *mname = mono_method_full_name (cfg->method, TRUE);
1799                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1800                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1801                 g_free (mname);
1802                 return;
1803         }
1804
1805         if (locals_stack_align) {
1806                 offset += (locals_stack_align - 1);
1807                 offset &= ~(locals_stack_align - 1);
1808         }
1809         if (cfg->arch.omit_fp) {
1810                 cfg->locals_min_stack_offset = offset;
1811                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1812         } else {
1813                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1814                 cfg->locals_max_stack_offset = - offset;
1815         }
1816
1817         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1818                 if (offsets [i] != -1) {
1819                         MonoInst *ins = cfg->varinfo [i];
1820                         ins->opcode = OP_REGOFFSET;
1821                         ins->inst_basereg = cfg->frame_reg;
1822                         if (cfg->arch.omit_fp)
1823                                 ins->inst_offset = (offset + offsets [i]);
1824                         else
1825                                 ins->inst_offset = - (offset + offsets [i]);
1826                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1827                 }
1828         }
1829         offset += locals_stack_size;
1830
1831         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1832                 g_assert (!cfg->arch.omit_fp);
1833                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1834                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1835         }
1836
1837         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1838                 ins = cfg->args [i];
1839                 if (ins->opcode != OP_REGVAR) {
1840                         ArgInfo *ainfo = &cinfo->args [i];
1841                         gboolean inreg = TRUE;
1842
1843                         /* FIXME: Allocate volatile arguments to registers */
1844                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1845                                 inreg = FALSE;
1846
1847                         /*
1848                          * Under AMD64, all registers used to pass arguments to functions
1849                          * are volatile across calls.
1850                          * FIXME: Optimize this.
1851                          */
1852                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1853                                 inreg = FALSE;
1854
1855                         ins->opcode = OP_REGOFFSET;
1856
1857                         switch (ainfo->storage) {
1858                         case ArgInIReg:
1859                         case ArgInFloatSSEReg:
1860                         case ArgInDoubleSSEReg:
1861                                 if (inreg) {
1862                                         ins->opcode = OP_REGVAR;
1863                                         ins->dreg = ainfo->reg;
1864                                 }
1865                                 break;
1866                         case ArgOnStack:
1867                                 g_assert (!cfg->arch.omit_fp);
1868                                 ins->opcode = OP_REGOFFSET;
1869                                 ins->inst_basereg = cfg->frame_reg;
1870                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1871                                 break;
1872                         case ArgValuetypeInReg:
1873                                 break;
1874                         case ArgValuetypeAddrInIReg: {
1875                                 MonoInst *indir;
1876                                 g_assert (!cfg->arch.omit_fp);
1877
1878                                 MONO_INST_NEW (cfg, indir, 0);
1879                                 indir->opcode = OP_REGOFFSET;
1880                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1881                                         indir->inst_basereg = cfg->frame_reg;
1882                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1883                                         offset += (sizeof (gpointer));
1884                                         indir->inst_offset = - offset;
1885                                 }
1886                                 else {
1887                                         indir->inst_basereg = cfg->frame_reg;
1888                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1889                                 }
1890
1891                                 ins->opcode = OP_VTARG_ADDR;
1892                                 ins->inst_left = indir;
1893
1894                                 break;
1895                         }
1896                         default:
1897                                 NOT_IMPLEMENTED;
1898                         }
1899
1900                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1901                                 ins->opcode = OP_REGOFFSET;
1902                                 ins->inst_basereg = cfg->frame_reg;
1903                                 /* These arguments are saved to the stack in the prolog */
1904                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1905                                 if (cfg->arch.omit_fp) {
1906                                         ins->inst_offset = offset;
1907                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1908                                         // Arguments are yet supported by the stack map creation code
1909                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1910                                 } else {
1911                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1912                                         ins->inst_offset = - offset;
1913                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1914                                 }
1915                         }
1916                 }
1917         }
1918
1919         cfg->stack_offset = offset;
1920 }
1921
1922 void
1923 mono_arch_create_vars (MonoCompile *cfg)
1924 {
1925         MonoMethodSignature *sig;
1926         CallInfo *cinfo;
1927         MonoType *sig_ret;
1928
1929         sig = mono_method_signature (cfg->method);
1930
1931         if (!cfg->arch.cinfo)
1932                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1933         cinfo = cfg->arch.cinfo;
1934
1935         if (cinfo->ret.storage == ArgValuetypeInReg)
1936                 cfg->ret_var_is_local = TRUE;
1937
1938         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1939         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1940                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1941                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1942                         printf ("vret_addr = ");
1943                         mono_print_ins (cfg->vret_addr);
1944                 }
1945         }
1946
1947         if (cfg->gen_sdb_seq_points) {
1948                 MonoInst *ins;
1949
1950                 if (cfg->compile_aot) {
1951                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1952                         ins->flags |= MONO_INST_VOLATILE;
1953                         cfg->arch.seq_point_info_var = ins;
1954
1955                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1956                         ins->flags |= MONO_INST_VOLATILE;
1957                         cfg->arch.ss_tramp_var = ins;
1958                 }
1959
1960             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1961                 ins->flags |= MONO_INST_VOLATILE;
1962                 cfg->arch.ss_trigger_page_var = ins;
1963         }
1964
1965         if (cfg->method->save_lmf)
1966                 cfg->create_lmf_var = TRUE;
1967
1968         if (cfg->method->save_lmf) {
1969                 cfg->lmf_ir = TRUE;
1970 #if !defined(TARGET_WIN32)
1971                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1972                         cfg->lmf_ir_mono_lmf = TRUE;
1973 #endif
1974         }
1975 }
1976
1977 static void
1978 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1979 {
1980         MonoInst *ins;
1981
1982         switch (storage) {
1983         case ArgInIReg:
1984                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1985                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1986                 ins->sreg1 = tree->dreg;
1987                 MONO_ADD_INS (cfg->cbb, ins);
1988                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1989                 break;
1990         case ArgInFloatSSEReg:
1991                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1992                 ins->dreg = mono_alloc_freg (cfg);
1993                 ins->sreg1 = tree->dreg;
1994                 MONO_ADD_INS (cfg->cbb, ins);
1995
1996                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1997                 break;
1998         case ArgInDoubleSSEReg:
1999                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2000                 ins->dreg = mono_alloc_freg (cfg);
2001                 ins->sreg1 = tree->dreg;
2002                 MONO_ADD_INS (cfg->cbb, ins);
2003
2004                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2005
2006                 break;
2007         default:
2008                 g_assert_not_reached ();
2009         }
2010 }
2011
2012 static int
2013 arg_storage_to_load_membase (ArgStorage storage)
2014 {
2015         switch (storage) {
2016         case ArgInIReg:
2017 #if defined(__mono_ilp32__)
2018                 return OP_LOADI8_MEMBASE;
2019 #else
2020                 return OP_LOAD_MEMBASE;
2021 #endif
2022         case ArgInDoubleSSEReg:
2023                 return OP_LOADR8_MEMBASE;
2024         case ArgInFloatSSEReg:
2025                 return OP_LOADR4_MEMBASE;
2026         default:
2027                 g_assert_not_reached ();
2028         }
2029
2030         return -1;
2031 }
2032
2033 static void
2034 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2035 {
2036         MonoMethodSignature *tmp_sig;
2037         int sig_reg;
2038
2039         if (call->tail_call)
2040                 NOT_IMPLEMENTED;
2041
2042         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2043
2044         /*
2045          * mono_ArgIterator_Setup assumes the signature cookie is
2046          * passed first and all the arguments which were before it are
2047          * passed on the stack after the signature. So compensate by
2048          * passing a different signature.
2049          */
2050         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2051         tmp_sig->param_count -= call->signature->sentinelpos;
2052         tmp_sig->sentinelpos = 0;
2053         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2054
2055         sig_reg = mono_alloc_ireg (cfg);
2056         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2057
2058         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2059 }
2060
2061 #ifdef ENABLE_LLVM
2062 static inline LLVMArgStorage
2063 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2064 {
2065         switch (storage) {
2066         case ArgInIReg:
2067                 return LLVMArgInIReg;
2068         case ArgNone:
2069                 return LLVMArgNone;
2070         default:
2071                 g_assert_not_reached ();
2072                 return LLVMArgNone;
2073         }
2074 }
2075
2076 LLVMCallInfo*
2077 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2078 {
2079         int i, n;
2080         CallInfo *cinfo;
2081         ArgInfo *ainfo;
2082         int j;
2083         LLVMCallInfo *linfo;
2084         MonoType *t, *sig_ret;
2085
2086         n = sig->param_count + sig->hasthis;
2087         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2088
2089         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2090
2091         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2092
2093         /*
2094          * LLVM always uses the native ABI while we use our own ABI, the
2095          * only difference is the handling of vtypes:
2096          * - we only pass/receive them in registers in some cases, and only
2097          *   in 1 or 2 integer registers.
2098          */
2099         if (cinfo->ret.storage == ArgValuetypeInReg) {
2100                 if (sig->pinvoke) {
2101                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2102                         cfg->disable_llvm = TRUE;
2103                         return linfo;
2104                 }
2105
2106                 linfo->ret.storage = LLVMArgVtypeInReg;
2107                 for (j = 0; j < 2; ++j)
2108                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2109         }
2110
2111         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2112                 /* Vtype returned using a hidden argument */
2113                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2114                 linfo->vret_arg_index = cinfo->vret_arg_index;
2115         }
2116
2117         for (i = 0; i < n; ++i) {
2118                 ainfo = cinfo->args + i;
2119
2120                 if (i >= sig->hasthis)
2121                         t = sig->params [i - sig->hasthis];
2122                 else
2123                         t = &mono_defaults.int_class->byval_arg;
2124
2125                 linfo->args [i].storage = LLVMArgNone;
2126
2127                 switch (ainfo->storage) {
2128                 case ArgInIReg:
2129                         linfo->args [i].storage = LLVMArgInIReg;
2130                         break;
2131                 case ArgInDoubleSSEReg:
2132                 case ArgInFloatSSEReg:
2133                         linfo->args [i].storage = LLVMArgInFPReg;
2134                         break;
2135                 case ArgOnStack:
2136                         if (MONO_TYPE_ISSTRUCT (t)) {
2137                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2138                         } else {
2139                                 linfo->args [i].storage = LLVMArgInIReg;
2140                                 if (!t->byref) {
2141                                         if (t->type == MONO_TYPE_R4)
2142                                                 linfo->args [i].storage = LLVMArgInFPReg;
2143                                         else if (t->type == MONO_TYPE_R8)
2144                                                 linfo->args [i].storage = LLVMArgInFPReg;
2145                                 }
2146                         }
2147                         break;
2148                 case ArgValuetypeInReg:
2149                         if (sig->pinvoke) {
2150                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2151                                 cfg->disable_llvm = TRUE;
2152                                 return linfo;
2153                         }
2154
2155                         linfo->args [i].storage = LLVMArgVtypeInReg;
2156                         for (j = 0; j < 2; ++j)
2157                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2158                         break;
2159                 default:
2160                         cfg->exception_message = g_strdup ("ainfo->storage");
2161                         cfg->disable_llvm = TRUE;
2162                         break;
2163                 }
2164         }
2165
2166         return linfo;
2167 }
2168 #endif
2169
2170 void
2171 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2172 {
2173         MonoInst *arg, *in;
2174         MonoMethodSignature *sig;
2175         MonoType *sig_ret;
2176         int i, n;
2177         CallInfo *cinfo;
2178         ArgInfo *ainfo;
2179
2180         sig = call->signature;
2181         n = sig->param_count + sig->hasthis;
2182
2183         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2184
2185         sig_ret = sig->ret;
2186
2187         if (COMPILE_LLVM (cfg)) {
2188                 /* We shouldn't be called in the llvm case */
2189                 cfg->disable_llvm = TRUE;
2190                 return;
2191         }
2192
2193         /*
2194          * Emit all arguments which are passed on the stack to prevent register
2195          * allocation problems.
2196          */
2197         for (i = 0; i < n; ++i) {
2198                 MonoType *t;
2199                 ainfo = cinfo->args + i;
2200
2201                 in = call->args [i];
2202
2203                 if (sig->hasthis && i == 0)
2204                         t = &mono_defaults.object_class->byval_arg;
2205                 else
2206                         t = sig->params [i - sig->hasthis];
2207
2208                 t = mini_get_underlying_type (cfg, t);
2209                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2210                         if (!t->byref) {
2211                                 if (t->type == MONO_TYPE_R4)
2212                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2213                                 else if (t->type == MONO_TYPE_R8)
2214                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2215                                 else
2216                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2217                         } else {
2218                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2219                         }
2220                         if (cfg->compute_gc_maps) {
2221                                 MonoInst *def;
2222
2223                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2224                         }
2225                 }
2226         }
2227
2228         /*
2229          * Emit all parameters passed in registers in non-reverse order for better readability
2230          * and to help the optimization in emit_prolog ().
2231          */
2232         for (i = 0; i < n; ++i) {
2233                 ainfo = cinfo->args + i;
2234
2235                 in = call->args [i];
2236
2237                 if (ainfo->storage == ArgInIReg)
2238                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2239         }
2240
2241         for (i = n - 1; i >= 0; --i) {
2242                 ainfo = cinfo->args + i;
2243
2244                 in = call->args [i];
2245
2246                 switch (ainfo->storage) {
2247                 case ArgInIReg:
2248                         /* Already done */
2249                         break;
2250                 case ArgInFloatSSEReg:
2251                 case ArgInDoubleSSEReg:
2252                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2253                         break;
2254                 case ArgOnStack:
2255                 case ArgValuetypeInReg:
2256                 case ArgValuetypeAddrInIReg:
2257                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2258                                 MonoInst *call_inst = (MonoInst*)call;
2259                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2260                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2261                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2262                                 guint32 align;
2263                                 guint32 size;
2264
2265                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2266                                         size = sizeof (MonoTypedRef);
2267                                         align = sizeof (gpointer);
2268                                 }
2269                                 else {
2270                                         if (sig->pinvoke)
2271                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2272                                         else {
2273                                                 /*
2274                                                  * Other backends use mono_type_stack_size (), but that
2275                                                  * aligns the size to 8, which is larger than the size of
2276                                                  * the source, leading to reads of invalid memory if the
2277                                                  * source is at the end of address space.
2278                                                  */
2279                                                 size = mono_class_value_size (in->klass, &align);
2280                                         }
2281                                 }
2282                                 g_assert (in->klass);
2283
2284                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2285                                         /* Avoid asserts in emit_memcpy () */
2286                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2287                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2288                                         /* Continue normally */
2289                                 }
2290
2291                                 if (size > 0) {
2292                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2293                                         arg->sreg1 = in->dreg;
2294                                         arg->klass = in->klass;
2295                                         arg->backend.size = size;
2296                                         arg->inst_p0 = call;
2297                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2298                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2299
2300                                         MONO_ADD_INS (cfg->cbb, arg);
2301                                 }
2302                         }
2303                         break;
2304                 default:
2305                         g_assert_not_reached ();
2306                 }
2307
2308                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2309                         /* Emit the signature cookie just before the implicit arguments */
2310                         emit_sig_cookie (cfg, call, cinfo);
2311         }
2312
2313         /* Handle the case where there are no implicit arguments */
2314         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2315                 emit_sig_cookie (cfg, call, cinfo);
2316
2317         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2318         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2319                 MonoInst *vtarg;
2320
2321                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2322                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2323                                 /*
2324                                  * Tell the JIT to use a more efficient calling convention: call using
2325                                  * OP_CALL, compute the result location after the call, and save the
2326                                  * result there.
2327                                  */
2328                                 call->vret_in_reg = TRUE;
2329                                 /*
2330                                  * Nullify the instruction computing the vret addr to enable
2331                                  * future optimizations.
2332                                  */
2333                                 if (call->vret_var)
2334                                         NULLIFY_INS (call->vret_var);
2335                         } else {
2336                                 if (call->tail_call)
2337                                         NOT_IMPLEMENTED;
2338                                 /*
2339                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2340                                  * the stack. Push the address here, so the call instruction can
2341                                  * access it.
2342                                  */
2343                                 if (!cfg->arch.vret_addr_loc) {
2344                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2345                                         /* Prevent it from being register allocated or optimized away */
2346                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2347                                 }
2348
2349                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2350                         }
2351                 }
2352                 else {
2353                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2354                         vtarg->sreg1 = call->vret_var->dreg;
2355                         vtarg->dreg = mono_alloc_preg (cfg);
2356                         MONO_ADD_INS (cfg->cbb, vtarg);
2357
2358                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2359                 }
2360         }
2361
2362         if (cfg->method->save_lmf) {
2363                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2364                 MONO_ADD_INS (cfg->cbb, arg);
2365         }
2366
2367         call->stack_usage = cinfo->stack_usage;
2368 }
2369
2370 void
2371 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2372 {
2373         MonoInst *arg;
2374         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2375         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2376         int size = ins->backend.size;
2377
2378         if (ainfo->storage == ArgValuetypeInReg) {
2379                 MonoInst *load;
2380                 int part;
2381
2382                 for (part = 0; part < 2; ++part) {
2383                         if (ainfo->pair_storage [part] == ArgNone)
2384                                 continue;
2385
2386                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2387                         load->inst_basereg = src->dreg;
2388                         load->inst_offset = part * sizeof(mgreg_t);
2389
2390                         switch (ainfo->pair_storage [part]) {
2391                         case ArgInIReg:
2392                                 load->dreg = mono_alloc_ireg (cfg);
2393                                 break;
2394                         case ArgInDoubleSSEReg:
2395                         case ArgInFloatSSEReg:
2396                                 load->dreg = mono_alloc_freg (cfg);
2397                                 break;
2398                         default:
2399                                 g_assert_not_reached ();
2400                         }
2401                         MONO_ADD_INS (cfg->cbb, load);
2402
2403                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2404                 }
2405         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2406                 MonoInst *vtaddr, *load;
2407                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2408
2409                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2410                 cfg->has_indirection = TRUE;
2411                 load->inst_p0 = vtaddr;
2412                 vtaddr->flags |= MONO_INST_INDIRECT;
2413                 load->type = STACK_MP;
2414                 load->klass = vtaddr->klass;
2415                 load->dreg = mono_alloc_ireg (cfg);
2416                 MONO_ADD_INS (cfg->cbb, load);
2417                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2418
2419                 if (ainfo->pair_storage [0] == ArgInIReg) {
2420                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2421                         arg->dreg = mono_alloc_ireg (cfg);
2422                         arg->sreg1 = load->dreg;
2423                         arg->inst_imm = 0;
2424                         MONO_ADD_INS (cfg->cbb, arg);
2425                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2426                 } else {
2427                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2428                 }
2429         } else {
2430                 if (size == 8) {
2431                         int dreg = mono_alloc_ireg (cfg);
2432
2433                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2434                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2435                 } else if (size <= 40) {
2436                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2437                 } else {
2438                         // FIXME: Code growth
2439                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2440                 }
2441
2442                 if (cfg->compute_gc_maps) {
2443                         MonoInst *def;
2444                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2445                 }
2446         }
2447 }
2448
2449 void
2450 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2451 {
2452         MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2453
2454         if (ret->type == MONO_TYPE_R4) {
2455                 if (COMPILE_LLVM (cfg))
2456                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2457                 else
2458                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2459                 return;
2460         } else if (ret->type == MONO_TYPE_R8) {
2461                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2462                 return;
2463         }
2464
2465         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2466 }
2467
2468 #endif /* DISABLE_JIT */
2469
2470 #define EMIT_COND_BRANCH(ins,cond,sign) \
2471         if (ins->inst_true_bb->native_offset) { \
2472                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2473         } else { \
2474                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2475                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2476             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2477                         x86_branch8 (code, cond, 0, sign); \
2478                 else \
2479                         x86_branch32 (code, cond, 0, sign); \
2480 }
2481
2482 typedef struct {
2483         MonoMethodSignature *sig;
2484         CallInfo *cinfo;
2485 } ArchDynCallInfo;
2486
2487 static gboolean
2488 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2489 {
2490         int i;
2491
2492 #ifdef HOST_WIN32
2493         return FALSE;
2494 #endif
2495
2496         switch (cinfo->ret.storage) {
2497         case ArgNone:
2498         case ArgInIReg:
2499                 break;
2500         case ArgValuetypeInReg: {
2501                 ArgInfo *ainfo = &cinfo->ret;
2502
2503                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2504                         return FALSE;
2505                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2506                         return FALSE;
2507                 break;
2508         }
2509         default:
2510                 return FALSE;
2511         }
2512
2513         for (i = 0; i < cinfo->nargs; ++i) {
2514                 ArgInfo *ainfo = &cinfo->args [i];
2515                 switch (ainfo->storage) {
2516                 case ArgInIReg:
2517                         break;
2518                 case ArgValuetypeInReg:
2519                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2520                                 return FALSE;
2521                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2522                                 return FALSE;
2523                         break;
2524                 default:
2525                         return FALSE;
2526                 }
2527         }
2528
2529         return TRUE;
2530 }
2531
2532 /*
2533  * mono_arch_dyn_call_prepare:
2534  *
2535  *   Return a pointer to an arch-specific structure which contains information
2536  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2537  * supported for SIG.
2538  * This function is equivalent to ffi_prep_cif in libffi.
2539  */
2540 MonoDynCallInfo*
2541 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2542 {
2543         ArchDynCallInfo *info;
2544         CallInfo *cinfo;
2545
2546         cinfo = get_call_info (NULL, NULL, sig);
2547
2548         if (!dyn_call_supported (sig, cinfo)) {
2549                 g_free (cinfo);
2550                 return NULL;
2551         }
2552
2553         info = g_new0 (ArchDynCallInfo, 1);
2554         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2555         info->sig = sig;
2556         info->cinfo = cinfo;
2557
2558         return (MonoDynCallInfo*)info;
2559 }
2560
2561 /*
2562  * mono_arch_dyn_call_free:
2563  *
2564  *   Free a MonoDynCallInfo structure.
2565  */
2566 void
2567 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2568 {
2569         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2570
2571         g_free (ainfo->cinfo);
2572         g_free (ainfo);
2573 }
2574
2575 #if !defined(__native_client__)
2576 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2577 #define GREG_TO_PTR(greg) (gpointer)(greg)
2578 #else
2579 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2580 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2581 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2582 #endif
2583
2584 /*
2585  * mono_arch_get_start_dyn_call:
2586  *
2587  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2588  * store the result into BUF.
2589  * ARGS should be an array of pointers pointing to the arguments.
2590  * RET should point to a memory buffer large enought to hold the result of the
2591  * call.
2592  * This function should be as fast as possible, any work which does not depend
2593  * on the actual values of the arguments should be done in
2594  * mono_arch_dyn_call_prepare ().
2595  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2596  * libffi.
2597  */
2598 void
2599 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2600 {
2601         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2602         DynCallArgs *p = (DynCallArgs*)buf;
2603         int arg_index, greg, i, pindex;
2604         MonoMethodSignature *sig = dinfo->sig;
2605
2606         g_assert (buf_len >= sizeof (DynCallArgs));
2607
2608         p->res = 0;
2609         p->ret = ret;
2610
2611         arg_index = 0;
2612         greg = 0;
2613         pindex = 0;
2614
2615         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2616                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2617                 if (!sig->hasthis)
2618                         pindex = 1;
2619         }
2620
2621         if (dinfo->cinfo->vtype_retaddr)
2622                 p->regs [greg ++] = PTR_TO_GREG(ret);
2623
2624         for (i = pindex; i < sig->param_count; i++) {
2625                 MonoType *t = mini_type_get_underlying_type (NULL, sig->params [i]);
2626                 gpointer *arg = args [arg_index ++];
2627
2628                 if (t->byref) {
2629                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2630                         continue;
2631                 }
2632
2633                 switch (t->type) {
2634                 case MONO_TYPE_STRING:
2635                 case MONO_TYPE_CLASS:
2636                 case MONO_TYPE_ARRAY:
2637                 case MONO_TYPE_SZARRAY:
2638                 case MONO_TYPE_OBJECT:
2639                 case MONO_TYPE_PTR:
2640                 case MONO_TYPE_I:
2641                 case MONO_TYPE_U:
2642 #if !defined(__mono_ilp32__)
2643                 case MONO_TYPE_I8:
2644                 case MONO_TYPE_U8:
2645 #endif
2646                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2647                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2648                         break;
2649 #if defined(__mono_ilp32__)
2650                 case MONO_TYPE_I8:
2651                 case MONO_TYPE_U8:
2652                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2653                         p->regs [greg ++] = *(guint64*)(arg);
2654                         break;
2655 #endif
2656                 case MONO_TYPE_U1:
2657                         p->regs [greg ++] = *(guint8*)(arg);
2658                         break;
2659                 case MONO_TYPE_I1:
2660                         p->regs [greg ++] = *(gint8*)(arg);
2661                         break;
2662                 case MONO_TYPE_I2:
2663                         p->regs [greg ++] = *(gint16*)(arg);
2664                         break;
2665                 case MONO_TYPE_U2:
2666                         p->regs [greg ++] = *(guint16*)(arg);
2667                         break;
2668                 case MONO_TYPE_I4:
2669                         p->regs [greg ++] = *(gint32*)(arg);
2670                         break;
2671                 case MONO_TYPE_U4:
2672                         p->regs [greg ++] = *(guint32*)(arg);
2673                         break;
2674                 case MONO_TYPE_GENERICINST:
2675                     if (MONO_TYPE_IS_REFERENCE (t)) {
2676                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2677                                 break;
2678                         } else {
2679                                 /* Fall through */
2680                         }
2681                 case MONO_TYPE_VALUETYPE: {
2682                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2683
2684                         g_assert (ainfo->storage == ArgValuetypeInReg);
2685                         if (ainfo->pair_storage [0] != ArgNone) {
2686                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2687                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2688                         }
2689                         if (ainfo->pair_storage [1] != ArgNone) {
2690                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2691                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2692                         }
2693                         break;
2694                 }
2695                 default:
2696                         g_assert_not_reached ();
2697                 }
2698         }
2699
2700         g_assert (greg <= PARAM_REGS);
2701 }
2702
2703 /*
2704  * mono_arch_finish_dyn_call:
2705  *
2706  *   Store the result of a dyn call into the return value buffer passed to
2707  * start_dyn_call ().
2708  * This function should be as fast as possible, any work which does not depend
2709  * on the actual values of the arguments should be done in
2710  * mono_arch_dyn_call_prepare ().
2711  */
2712 void
2713 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2714 {
2715         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2716         MonoMethodSignature *sig = dinfo->sig;
2717         guint8 *ret = ((DynCallArgs*)buf)->ret;
2718         mgreg_t res = ((DynCallArgs*)buf)->res;
2719         MonoType *sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
2720
2721         switch (sig_ret->type) {
2722         case MONO_TYPE_VOID:
2723                 *(gpointer*)ret = NULL;
2724                 break;
2725         case MONO_TYPE_STRING:
2726         case MONO_TYPE_CLASS:
2727         case MONO_TYPE_ARRAY:
2728         case MONO_TYPE_SZARRAY:
2729         case MONO_TYPE_OBJECT:
2730         case MONO_TYPE_I:
2731         case MONO_TYPE_U:
2732         case MONO_TYPE_PTR:
2733                 *(gpointer*)ret = GREG_TO_PTR(res);
2734                 break;
2735         case MONO_TYPE_I1:
2736                 *(gint8*)ret = res;
2737                 break;
2738         case MONO_TYPE_U1:
2739                 *(guint8*)ret = res;
2740                 break;
2741         case MONO_TYPE_I2:
2742                 *(gint16*)ret = res;
2743                 break;
2744         case MONO_TYPE_U2:
2745                 *(guint16*)ret = res;
2746                 break;
2747         case MONO_TYPE_I4:
2748                 *(gint32*)ret = res;
2749                 break;
2750         case MONO_TYPE_U4:
2751                 *(guint32*)ret = res;
2752                 break;
2753         case MONO_TYPE_I8:
2754                 *(gint64*)ret = res;
2755                 break;
2756         case MONO_TYPE_U8:
2757                 *(guint64*)ret = res;
2758                 break;
2759         case MONO_TYPE_GENERICINST:
2760                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2761                         *(gpointer*)ret = GREG_TO_PTR(res);
2762                         break;
2763                 } else {
2764                         /* Fall through */
2765                 }
2766         case MONO_TYPE_VALUETYPE:
2767                 if (dinfo->cinfo->vtype_retaddr) {
2768                         /* Nothing to do */
2769                 } else {
2770                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2771
2772                         g_assert (ainfo->storage == ArgValuetypeInReg);
2773
2774                         if (ainfo->pair_storage [0] != ArgNone) {
2775                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2776                                 ((mgreg_t*)ret)[0] = res;
2777                         }
2778
2779                         g_assert (ainfo->pair_storage [1] == ArgNone);
2780                 }
2781                 break;
2782         default:
2783                 g_assert_not_reached ();
2784         }
2785 }
2786
2787 /* emit an exception if condition is fail */
2788 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2789         do {                                                        \
2790                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2791                 if (tins == NULL) {                                                                             \
2792                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2793                                         MONO_PATCH_INFO_EXC, exc_name);  \
2794                         x86_branch32 (code, cond, 0, signed);               \
2795                 } else {        \
2796                         EMIT_COND_BRANCH (tins, cond, signed);  \
2797                 }                       \
2798         } while (0);
2799
2800 #define EMIT_FPCOMPARE(code) do { \
2801         amd64_fcompp (code); \
2802         amd64_fnstsw (code); \
2803 } while (0);
2804
2805 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2806     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2807         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2808         amd64_ ##op (code); \
2809         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2810         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2811 } while (0);
2812
2813 static guint8*
2814 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2815 {
2816         gboolean no_patch = FALSE;
2817
2818         /*
2819          * FIXME: Add support for thunks
2820          */
2821         {
2822                 gboolean near_call = FALSE;
2823
2824                 /*
2825                  * Indirect calls are expensive so try to make a near call if possible.
2826                  * The caller memory is allocated by the code manager so it is
2827                  * guaranteed to be at a 32 bit offset.
2828                  */
2829
2830                 if (patch_type != MONO_PATCH_INFO_ABS) {
2831                         /* The target is in memory allocated using the code manager */
2832                         near_call = TRUE;
2833
2834                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2835                                 if (((MonoMethod*)data)->klass->image->aot_module)
2836                                         /* The callee might be an AOT method */
2837                                         near_call = FALSE;
2838                                 if (((MonoMethod*)data)->dynamic)
2839                                         /* The target is in malloc-ed memory */
2840                                         near_call = FALSE;
2841                         }
2842
2843                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2844                                 /*
2845                                  * The call might go directly to a native function without
2846                                  * the wrapper.
2847                                  */
2848                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2849                                 if (mi) {
2850                                         gconstpointer target = mono_icall_get_wrapper (mi);
2851                                         if ((((guint64)target) >> 32) != 0)
2852                                                 near_call = FALSE;
2853                                 }
2854                         }
2855                 }
2856                 else {
2857                         MonoJumpInfo *jinfo = NULL;
2858
2859                         if (cfg->abs_patches)
2860                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2861                         if (jinfo) {
2862                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2863                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2864                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2865                                                 near_call = TRUE;
2866                                         no_patch = TRUE;
2867                                 } else {
2868                                         /*
2869                                          * This is not really an optimization, but required because the
2870                                          * generic class init trampolines use R11 to pass the vtable.
2871                                          */
2872                                         near_call = TRUE;
2873                                 }
2874                         } else {
2875                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2876                                 if (info) {
2877                                         if (info->func == info->wrapper) {
2878                                                 /* No wrapper */
2879                                                 if ((((guint64)info->func) >> 32) == 0)
2880                                                         near_call = TRUE;
2881                                         }
2882                                         else {
2883                                                 /* See the comment in mono_codegen () */
2884                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2885                                                         near_call = TRUE;
2886                                         }
2887                                 }
2888                                 else if ((((guint64)data) >> 32) == 0) {
2889                                         near_call = TRUE;
2890                                         no_patch = TRUE;
2891                                 }
2892                         }
2893                 }
2894
2895                 if (cfg->method->dynamic)
2896                         /* These methods are allocated using malloc */
2897                         near_call = FALSE;
2898
2899 #ifdef MONO_ARCH_NOMAP32BIT
2900                 near_call = FALSE;
2901 #endif
2902 #if defined(__native_client__)
2903                 /* Always use near_call == TRUE for Native Client */
2904                 near_call = TRUE;
2905 #endif
2906                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2907                 if (optimize_for_xen)
2908                         near_call = FALSE;
2909
2910                 if (cfg->compile_aot) {
2911                         near_call = TRUE;
2912                         no_patch = TRUE;
2913                 }
2914
2915                 if (near_call) {
2916                         /*
2917                          * Align the call displacement to an address divisible by 4 so it does
2918                          * not span cache lines. This is required for code patching to work on SMP
2919                          * systems.
2920                          */
2921                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2922                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2923                                 amd64_padding (code, pad_size);
2924                         }
2925                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2926                         amd64_call_code (code, 0);
2927                 }
2928                 else {
2929                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2930                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2931                         amd64_call_reg (code, GP_SCRATCH_REG);
2932                 }
2933         }
2934
2935         return code;
2936 }
2937
2938 static inline guint8*
2939 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2940 {
2941 #ifdef TARGET_WIN32
2942         if (win64_adjust_stack)
2943                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2944 #endif
2945         code = emit_call_body (cfg, code, patch_type, data);
2946 #ifdef TARGET_WIN32
2947         if (win64_adjust_stack)
2948                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2949 #endif
2950
2951         return code;
2952 }
2953
2954 static inline int
2955 store_membase_imm_to_store_membase_reg (int opcode)
2956 {
2957         switch (opcode) {
2958         case OP_STORE_MEMBASE_IMM:
2959                 return OP_STORE_MEMBASE_REG;
2960         case OP_STOREI4_MEMBASE_IMM:
2961                 return OP_STOREI4_MEMBASE_REG;
2962         case OP_STOREI8_MEMBASE_IMM:
2963                 return OP_STOREI8_MEMBASE_REG;
2964         }
2965
2966         return -1;
2967 }
2968
2969 #ifndef DISABLE_JIT
2970
2971 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2972
2973 /*
2974  * mono_arch_peephole_pass_1:
2975  *
2976  *   Perform peephole opts which should/can be performed before local regalloc
2977  */
2978 void
2979 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2980 {
2981         MonoInst *ins, *n;
2982
2983         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2984                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2985
2986                 switch (ins->opcode) {
2987                 case OP_ADD_IMM:
2988                 case OP_IADD_IMM:
2989                 case OP_LADD_IMM:
2990                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2991                                 /*
2992                                  * X86_LEA is like ADD, but doesn't have the
2993                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2994                                  * its operand to 64 bit.
2995                                  */
2996                                 ins->opcode = OP_X86_LEA_MEMBASE;
2997                                 ins->inst_basereg = ins->sreg1;
2998                         }
2999                         break;
3000                 case OP_LXOR:
3001                 case OP_IXOR:
3002                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3003                                 MonoInst *ins2;
3004
3005                                 /*
3006                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3007                                  * the latter has length 2-3 instead of 6 (reverse constant
3008                                  * propagation). These instruction sequences are very common
3009                                  * in the initlocals bblock.
3010                                  */
3011                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3012                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3013                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3014                                                 ins2->sreg1 = ins->dreg;
3015                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3016                                                 /* Continue */
3017                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3018                                                 NULLIFY_INS (ins2);
3019                                                 /* Continue */
3020                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3021                                                 /* Continue */
3022                                         } else {
3023                                                 break;
3024                                         }
3025                                 }
3026                         }
3027                         break;
3028                 case OP_COMPARE_IMM:
3029                 case OP_LCOMPARE_IMM:
3030                         /* OP_COMPARE_IMM (reg, 0)
3031                          * -->
3032                          * OP_AMD64_TEST_NULL (reg)
3033                          */
3034                         if (!ins->inst_imm)
3035                                 ins->opcode = OP_AMD64_TEST_NULL;
3036                         break;
3037                 case OP_ICOMPARE_IMM:
3038                         if (!ins->inst_imm)
3039                                 ins->opcode = OP_X86_TEST_NULL;
3040                         break;
3041                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3042                         /*
3043                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3044                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3045                          * -->
3046                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3047                          * OP_COMPARE_IMM reg, imm
3048                          *
3049                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3050                          */
3051                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3052                             ins->inst_basereg == last_ins->inst_destbasereg &&
3053                             ins->inst_offset == last_ins->inst_offset) {
3054                                         ins->opcode = OP_ICOMPARE_IMM;
3055                                         ins->sreg1 = last_ins->sreg1;
3056
3057                                         /* check if we can remove cmp reg,0 with test null */
3058                                         if (!ins->inst_imm)
3059                                                 ins->opcode = OP_X86_TEST_NULL;
3060                                 }
3061
3062                         break;
3063                 }
3064
3065                 mono_peephole_ins (bb, ins);
3066         }
3067 }
3068
3069 void
3070 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3071 {
3072         MonoInst *ins, *n;
3073
3074         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3075                 switch (ins->opcode) {
3076                 case OP_ICONST:
3077                 case OP_I8CONST: {
3078                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3079                         /* reg = 0 -> XOR (reg, reg) */
3080                         /* XOR sets cflags on x86, so we cant do it always */
3081                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3082                                 ins->opcode = OP_LXOR;
3083                                 ins->sreg1 = ins->dreg;
3084                                 ins->sreg2 = ins->dreg;
3085                                 /* Fall through */
3086                         } else {
3087                                 break;
3088                         }
3089                 }
3090                 case OP_LXOR:
3091                         /*
3092                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3093                          * 0 result into 64 bits.
3094                          */
3095                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3096                                 ins->opcode = OP_IXOR;
3097                         }
3098                         /* Fall through */
3099                 case OP_IXOR:
3100                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3101                                 MonoInst *ins2;
3102
3103                                 /*
3104                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3105                                  * the latter has length 2-3 instead of 6 (reverse constant
3106                                  * propagation). These instruction sequences are very common
3107                                  * in the initlocals bblock.
3108                                  */
3109                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3110                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3111                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3112                                                 ins2->sreg1 = ins->dreg;
3113                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3114                                                 /* Continue */
3115                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3116                                                 NULLIFY_INS (ins2);
3117                                                 /* Continue */
3118                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3119                                                 /* Continue */
3120                                         } else {
3121                                                 break;
3122                                         }
3123                                 }
3124                         }
3125                         break;
3126                 case OP_IADD_IMM:
3127                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3128                                 ins->opcode = OP_X86_INC_REG;
3129                         break;
3130                 case OP_ISUB_IMM:
3131                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3132                                 ins->opcode = OP_X86_DEC_REG;
3133                         break;
3134                 }
3135
3136                 mono_peephole_ins (bb, ins);
3137         }
3138 }
3139
3140 #define NEW_INS(cfg,ins,dest,op) do {   \
3141                 MONO_INST_NEW ((cfg), (dest), (op)); \
3142         (dest)->cil_code = (ins)->cil_code; \
3143         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3144         } while (0)
3145
3146 /*
3147  * mono_arch_lowering_pass:
3148  *
3149  *  Converts complex opcodes into simpler ones so that each IR instruction
3150  * corresponds to one machine instruction.
3151  */
3152 void
3153 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3154 {
3155         MonoInst *ins, *n, *temp;
3156
3157         /*
3158          * FIXME: Need to add more instructions, but the current machine
3159          * description can't model some parts of the composite instructions like
3160          * cdq.
3161          */
3162         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3163                 switch (ins->opcode) {
3164                 case OP_DIV_IMM:
3165                 case OP_REM_IMM:
3166                 case OP_IDIV_IMM:
3167                 case OP_IDIV_UN_IMM:
3168                 case OP_IREM_UN_IMM:
3169                 case OP_LREM_IMM:
3170                 case OP_IREM_IMM:
3171                         mono_decompose_op_imm (cfg, bb, ins);
3172                         break;
3173                 case OP_COMPARE_IMM:
3174                 case OP_LCOMPARE_IMM:
3175                         if (!amd64_is_imm32 (ins->inst_imm)) {
3176                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3177                                 temp->inst_c0 = ins->inst_imm;
3178                                 temp->dreg = mono_alloc_ireg (cfg);
3179                                 ins->opcode = OP_COMPARE;
3180                                 ins->sreg2 = temp->dreg;
3181                         }
3182                         break;
3183 #ifndef __mono_ilp32__
3184                 case OP_LOAD_MEMBASE:
3185 #endif
3186                 case OP_LOADI8_MEMBASE:
3187 #ifndef __native_client_codegen__
3188                 /*  Don't generate memindex opcodes (to simplify */
3189                 /*  read sandboxing) */
3190                         if (!amd64_is_imm32 (ins->inst_offset)) {
3191                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3192                                 temp->inst_c0 = ins->inst_offset;
3193                                 temp->dreg = mono_alloc_ireg (cfg);
3194                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3195                                 ins->inst_indexreg = temp->dreg;
3196                         }
3197 #endif
3198                         break;
3199 #ifndef __mono_ilp32__
3200                 case OP_STORE_MEMBASE_IMM:
3201 #endif
3202                 case OP_STOREI8_MEMBASE_IMM:
3203                         if (!amd64_is_imm32 (ins->inst_imm)) {
3204                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3205                                 temp->inst_c0 = ins->inst_imm;
3206                                 temp->dreg = mono_alloc_ireg (cfg);
3207                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3208                                 ins->sreg1 = temp->dreg;
3209                         }
3210                         break;
3211 #ifdef MONO_ARCH_SIMD_INTRINSICS
3212                 case OP_EXPAND_I1: {
3213                                 int temp_reg1 = mono_alloc_ireg (cfg);
3214                                 int temp_reg2 = mono_alloc_ireg (cfg);
3215                                 int original_reg = ins->sreg1;
3216
3217                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3218                                 temp->sreg1 = original_reg;
3219                                 temp->dreg = temp_reg1;
3220
3221                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3222                                 temp->sreg1 = temp_reg1;
3223                                 temp->dreg = temp_reg2;
3224                                 temp->inst_imm = 8;
3225
3226                                 NEW_INS (cfg, ins, temp, OP_LOR);
3227                                 temp->sreg1 = temp->dreg = temp_reg2;
3228                                 temp->sreg2 = temp_reg1;
3229
3230                                 ins->opcode = OP_EXPAND_I2;
3231                                 ins->sreg1 = temp_reg2;
3232                         }
3233                         break;
3234 #endif
3235                 default:
3236                         break;
3237                 }
3238         }
3239
3240         bb->max_vreg = cfg->next_vreg;
3241 }
3242
3243 static const int
3244 branch_cc_table [] = {
3245         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3246         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3247         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3248 };
3249
3250 /* Maps CMP_... constants to X86_CC_... constants */
3251 static const int
3252 cc_table [] = {
3253         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3254         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3255 };
3256
3257 static const int
3258 cc_signed_table [] = {
3259         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3260         FALSE, FALSE, FALSE, FALSE
3261 };
3262
3263 /*#include "cprop.c"*/
3264
3265 static unsigned char*
3266 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3267 {
3268         if (size == 8)
3269                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3270         else
3271                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3272
3273         if (size == 1)
3274                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3275         else if (size == 2)
3276                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3277         return code;
3278 }
3279
3280 static unsigned char*
3281 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3282 {
3283         int sreg = tree->sreg1;
3284         int need_touch = FALSE;
3285
3286 #if defined(TARGET_WIN32)
3287         need_touch = TRUE;
3288 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3289         if (!tree->flags & MONO_INST_INIT)
3290                 need_touch = TRUE;
3291 #endif
3292
3293         if (need_touch) {
3294                 guint8* br[5];
3295
3296                 /*
3297                  * Under Windows:
3298                  * If requested stack size is larger than one page,
3299                  * perform stack-touch operation
3300                  */
3301                 /*
3302                  * Generate stack probe code.
3303                  * Under Windows, it is necessary to allocate one page at a time,
3304                  * "touching" stack after each successful sub-allocation. This is
3305                  * because of the way stack growth is implemented - there is a
3306                  * guard page before the lowest stack page that is currently commited.
3307                  * Stack normally grows sequentially so OS traps access to the
3308                  * guard page and commits more pages when needed.
3309                  */
3310                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3311                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3312
3313                 br[2] = code; /* loop */
3314                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3315                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3316                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3317                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3318                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3319                 amd64_patch (br[3], br[2]);
3320                 amd64_test_reg_reg (code, sreg, sreg);
3321                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3322                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3323
3324                 br[1] = code; x86_jump8 (code, 0);
3325
3326                 amd64_patch (br[0], code);
3327                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3328                 amd64_patch (br[1], code);
3329                 amd64_patch (br[4], code);
3330         }
3331         else
3332                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3333
3334         if (tree->flags & MONO_INST_INIT) {
3335                 int offset = 0;
3336                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3337                         amd64_push_reg (code, AMD64_RAX);
3338                         offset += 8;
3339                 }
3340                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3341                         amd64_push_reg (code, AMD64_RCX);
3342                         offset += 8;
3343                 }
3344                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3345                         amd64_push_reg (code, AMD64_RDI);
3346                         offset += 8;
3347                 }
3348
3349                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3350                 if (sreg != AMD64_RCX)
3351                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3352                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3353
3354                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3355                 if (cfg->param_area)
3356                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3357                 amd64_cld (code);
3358 #if defined(__default_codegen__)
3359                 amd64_prefix (code, X86_REP_PREFIX);
3360                 amd64_stosl (code);
3361 #elif defined(__native_client_codegen__)
3362                 /* NaCl stos pseudo-instruction */
3363                 amd64_codegen_pre(code);
3364                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3365                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3366                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3367                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3368                 amd64_prefix (code, X86_REP_PREFIX);
3369                 amd64_stosl (code);
3370                 amd64_codegen_post(code);
3371 #endif /* __native_client_codegen__ */
3372
3373                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3374                         amd64_pop_reg (code, AMD64_RDI);
3375                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3376                         amd64_pop_reg (code, AMD64_RCX);
3377                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3378                         amd64_pop_reg (code, AMD64_RAX);
3379         }
3380         return code;
3381 }
3382
3383 static guint8*
3384 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3385 {
3386         CallInfo *cinfo;
3387         guint32 quad;
3388
3389         /* Move return value to the target register */
3390         /* FIXME: do this in the local reg allocator */
3391         switch (ins->opcode) {
3392         case OP_CALL:
3393         case OP_CALL_REG:
3394         case OP_CALL_MEMBASE:
3395         case OP_LCALL:
3396         case OP_LCALL_REG:
3397         case OP_LCALL_MEMBASE:
3398                 g_assert (ins->dreg == AMD64_RAX);
3399                 break;
3400         case OP_FCALL:
3401         case OP_FCALL_REG:
3402         case OP_FCALL_MEMBASE: {
3403                 MonoType *rtype = mini_get_underlying_type (cfg, ((MonoCallInst*)ins)->signature->ret);
3404                 if (rtype->type == MONO_TYPE_R4) {
3405                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3406                 }
3407                 else {
3408                         if (ins->dreg != AMD64_XMM0)
3409                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3410                 }
3411                 break;
3412         }
3413         case OP_RCALL:
3414         case OP_RCALL_REG:
3415         case OP_RCALL_MEMBASE:
3416                 if (ins->dreg != AMD64_XMM0)
3417                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3418                 break;
3419         case OP_VCALL:
3420         case OP_VCALL_REG:
3421         case OP_VCALL_MEMBASE:
3422         case OP_VCALL2:
3423         case OP_VCALL2_REG:
3424         case OP_VCALL2_MEMBASE:
3425                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3426                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3427                         MonoInst *loc = cfg->arch.vret_addr_loc;
3428
3429                         /* Load the destination address */
3430                         g_assert (loc->opcode == OP_REGOFFSET);
3431                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3432
3433                         for (quad = 0; quad < 2; quad ++) {
3434                                 switch (cinfo->ret.pair_storage [quad]) {
3435                                 case ArgInIReg:
3436                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3437                                         break;
3438                                 case ArgInFloatSSEReg:
3439                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3440                                         break;
3441                                 case ArgInDoubleSSEReg:
3442                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3443                                         break;
3444                                 case ArgNone:
3445                                         break;
3446                                 default:
3447                                         NOT_IMPLEMENTED;
3448                                 }
3449                         }
3450                 }
3451                 break;
3452         }
3453
3454         return code;
3455 }
3456
3457 #endif /* DISABLE_JIT */
3458
3459 #ifdef __APPLE__
3460 static int tls_gs_offset;
3461 #endif
3462
3463 gboolean
3464 mono_amd64_have_tls_get (void)
3465 {
3466 #ifdef TARGET_MACH
3467         static gboolean have_tls_get = FALSE;
3468         static gboolean inited = FALSE;
3469         guint8 *ins;
3470
3471         if (inited)
3472                 return have_tls_get;
3473
3474         ins = (guint8*)pthread_getspecific;
3475
3476         /*
3477          * We're looking for these two instructions:
3478          *
3479          * mov    %gs:[offset](,%rdi,8),%rax
3480          * retq
3481          */
3482         have_tls_get = ins [0] == 0x65 &&
3483                        ins [1] == 0x48 &&
3484                        ins [2] == 0x8b &&
3485                        ins [3] == 0x04 &&
3486                        ins [4] == 0xfd &&
3487                        ins [6] == 0x00 &&
3488                        ins [7] == 0x00 &&
3489                        ins [8] == 0x00 &&
3490                        ins [9] == 0xc3;
3491
3492         inited = TRUE;
3493
3494         tls_gs_offset = ins[5];
3495
3496         return have_tls_get;
3497 #elif defined(TARGET_ANDROID)
3498         return FALSE;
3499 #else
3500         return TRUE;
3501 #endif
3502 }
3503
3504 int
3505 mono_amd64_get_tls_gs_offset (void)
3506 {
3507 #ifdef TARGET_OSX
3508         return tls_gs_offset;
3509 #else
3510         g_assert_not_reached ();
3511         return -1;
3512 #endif
3513 }
3514
3515 /*
3516  * mono_amd64_emit_tls_get:
3517  * @code: buffer to store code to
3518  * @dreg: hard register where to place the result
3519  * @tls_offset: offset info
3520  *
3521  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3522  * the dreg register the item in the thread local storage identified
3523  * by tls_offset.
3524  *
3525  * Returns: a pointer to the end of the stored code
3526  */
3527 guint8*
3528 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3529 {
3530 #ifdef TARGET_WIN32
3531         if (tls_offset < 64) {
3532                 x86_prefix (code, X86_GS_PREFIX);
3533                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3534         } else {
3535                 guint8 *buf [16];
3536
3537                 g_assert (tls_offset < 0x440);
3538                 /* Load TEB->TlsExpansionSlots */
3539                 x86_prefix (code, X86_GS_PREFIX);
3540                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3541                 amd64_test_reg_reg (code, dreg, dreg);
3542                 buf [0] = code;
3543                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3544                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3545                 amd64_patch (buf [0], code);
3546         }
3547 #elif defined(__APPLE__)
3548         x86_prefix (code, X86_GS_PREFIX);
3549         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3550 #else
3551         if (optimize_for_xen) {
3552                 x86_prefix (code, X86_FS_PREFIX);
3553                 amd64_mov_reg_mem (code, dreg, 0, 8);
3554                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3555         } else {
3556                 x86_prefix (code, X86_FS_PREFIX);
3557                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3558         }
3559 #endif
3560         return code;
3561 }
3562
3563 static guint8*
3564 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3565 {
3566         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3567 #ifdef TARGET_OSX
3568         if (dreg != offset_reg)
3569                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3570         amd64_prefix (code, X86_GS_PREFIX);
3571         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3572 #elif defined(__linux__)
3573         int tmpreg = -1;
3574
3575         if (dreg == offset_reg) {
3576                 /* Use a temporary reg by saving it to the redzone */
3577                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3578                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3579                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3580                 offset_reg = tmpreg;
3581         }
3582         x86_prefix (code, X86_FS_PREFIX);
3583         amd64_mov_reg_mem (code, dreg, 0, 8);
3584         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3585         if (tmpreg != -1)
3586                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3587 #else
3588         g_assert_not_reached ();
3589 #endif
3590         return code;
3591 }
3592
3593 static guint8*
3594 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3595 {
3596 #ifdef TARGET_WIN32
3597         g_assert_not_reached ();
3598 #elif defined(__APPLE__)
3599         x86_prefix (code, X86_GS_PREFIX);
3600         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3601 #else
3602         g_assert (!optimize_for_xen);
3603         x86_prefix (code, X86_FS_PREFIX);
3604         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3605 #endif
3606         return code;
3607 }
3608
3609 static guint8*
3610 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3611 {
3612         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3613 #ifdef TARGET_WIN32
3614         g_assert_not_reached ();
3615 #elif defined(__APPLE__)
3616         x86_prefix (code, X86_GS_PREFIX);
3617         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3618 #else
3619         x86_prefix (code, X86_FS_PREFIX);
3620         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3621 #endif
3622         return code;
3623 }
3624
3625  /*
3626  * mono_arch_translate_tls_offset:
3627  *
3628  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3629  */
3630 int
3631 mono_arch_translate_tls_offset (int offset)
3632 {
3633 #ifdef __APPLE__
3634         return tls_gs_offset + (offset * 8);
3635 #else
3636         return offset;
3637 #endif
3638 }
3639
3640 /*
3641  * emit_setup_lmf:
3642  *
3643  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3644  */
3645 static guint8*
3646 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3647 {
3648         /*
3649          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3650          */
3651         /*
3652          * sp is saved right before calls but we need to save it here too so
3653          * async stack walks would work.
3654          */
3655         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3656         /* Save rbp */
3657         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3658         if (cfg->arch.omit_fp && cfa_offset != -1)
3659                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3660
3661         /* These can't contain refs */
3662         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3663         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3664         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3665         /* These are handled automatically by the stack marking code */
3666         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3667
3668         return code;
3669 }
3670
3671 #define REAL_PRINT_REG(text,reg) \
3672 mono_assert (reg >= 0); \
3673 amd64_push_reg (code, AMD64_RAX); \
3674 amd64_push_reg (code, AMD64_RDX); \
3675 amd64_push_reg (code, AMD64_RCX); \
3676 amd64_push_reg (code, reg); \
3677 amd64_push_imm (code, reg); \
3678 amd64_push_imm (code, text " %d %p\n"); \
3679 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3680 amd64_call_reg (code, AMD64_RAX); \
3681 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3682 amd64_pop_reg (code, AMD64_RCX); \
3683 amd64_pop_reg (code, AMD64_RDX); \
3684 amd64_pop_reg (code, AMD64_RAX);
3685
3686 /* benchmark and set based on cpu */
3687 #define LOOP_ALIGNMENT 8
3688 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3689
3690 #ifndef DISABLE_JIT
3691 void
3692 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3693 {
3694         MonoInst *ins;
3695         MonoCallInst *call;
3696         guint offset;
3697         guint8 *code = cfg->native_code + cfg->code_len;
3698         int max_len;
3699
3700         /* Fix max_offset estimate for each successor bb */
3701         if (cfg->opt & MONO_OPT_BRANCH) {
3702                 int current_offset = cfg->code_len;
3703                 MonoBasicBlock *current_bb;
3704                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3705                         current_bb->max_offset = current_offset;
3706                         current_offset += current_bb->max_length;
3707                 }
3708         }
3709
3710         if (cfg->opt & MONO_OPT_LOOP) {
3711                 int pad, align = LOOP_ALIGNMENT;
3712                 /* set alignment depending on cpu */
3713                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3714                         pad = align - pad;
3715                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3716                         amd64_padding (code, pad);
3717                         cfg->code_len += pad;
3718                         bb->native_offset = cfg->code_len;
3719                 }
3720         }
3721
3722 #if defined(__native_client_codegen__)
3723         /* For Native Client, all indirect call/jump targets must be */
3724         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3725         /* indirectly as well.                                       */
3726         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3727                                       (bb->flags & BB_EXCEPTION_HANDLER);
3728
3729         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3730                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3731                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3732                 cfg->code_len += pad;
3733                 bb->native_offset = cfg->code_len;
3734         }
3735 #endif  /*__native_client_codegen__*/
3736
3737         if (cfg->verbose_level > 2)
3738                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3739
3740         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3741                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3742                 g_assert (!cfg->compile_aot);
3743
3744                 cov->data [bb->dfn].cil_code = bb->cil_code;
3745                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3746                 /* this is not thread save, but good enough */
3747                 amd64_inc_membase (code, AMD64_R11, 0);
3748         }
3749
3750         offset = code - cfg->native_code;
3751
3752         mono_debug_open_block (cfg, bb, offset);
3753
3754     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3755                 x86_breakpoint (code);
3756
3757         MONO_BB_FOR_EACH_INS (bb, ins) {
3758                 offset = code - cfg->native_code;
3759
3760                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3761
3762 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3763
3764                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3765                         cfg->code_size *= 2;
3766                         cfg->native_code = mono_realloc_native_code(cfg);
3767                         code = cfg->native_code + offset;
3768                         cfg->stat_code_reallocs++;
3769                 }
3770
3771                 if (cfg->debug_info)
3772                         mono_debug_record_line_number (cfg, ins, offset);
3773
3774                 switch (ins->opcode) {
3775                 case OP_BIGMUL:
3776                         amd64_mul_reg (code, ins->sreg2, TRUE);
3777                         break;
3778                 case OP_BIGMUL_UN:
3779                         amd64_mul_reg (code, ins->sreg2, FALSE);
3780                         break;
3781                 case OP_X86_SETEQ_MEMBASE:
3782                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3783                         break;
3784                 case OP_STOREI1_MEMBASE_IMM:
3785                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3786                         break;
3787                 case OP_STOREI2_MEMBASE_IMM:
3788                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3789                         break;
3790                 case OP_STOREI4_MEMBASE_IMM:
3791                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3792                         break;
3793                 case OP_STOREI1_MEMBASE_REG:
3794                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3795                         break;
3796                 case OP_STOREI2_MEMBASE_REG:
3797                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3798                         break;
3799                 /* In AMD64 NaCl, pointers are 4 bytes, */
3800                 /*  so STORE_* != STOREI8_*. Likewise below. */
3801                 case OP_STORE_MEMBASE_REG:
3802                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3803                         break;
3804                 case OP_STOREI8_MEMBASE_REG:
3805                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3806                         break;
3807                 case OP_STOREI4_MEMBASE_REG:
3808                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3809                         break;
3810                 case OP_STORE_MEMBASE_IMM:
3811 #ifndef __native_client_codegen__
3812                         /* In NaCl, this could be a PCONST type, which could */
3813                         /* mean a pointer type was copied directly into the  */
3814                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3815                         /* the value would be 0x00000000FFFFFFFF which is    */
3816                         /* not proper for an imm32 unless you cast it.       */
3817                         g_assert (amd64_is_imm32 (ins->inst_imm));
3818 #endif
3819                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3820                         break;
3821                 case OP_STOREI8_MEMBASE_IMM:
3822                         g_assert (amd64_is_imm32 (ins->inst_imm));
3823                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3824                         break;
3825                 case OP_LOAD_MEM:
3826 #ifdef __mono_ilp32__
3827                         /* In ILP32, pointers are 4 bytes, so separate these */
3828                         /* cases, use literal 8 below where we really want 8 */
3829                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3830                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3831                         break;
3832 #endif
3833                 case OP_LOADI8_MEM:
3834                         // FIXME: Decompose this earlier
3835                         if (amd64_is_imm32 (ins->inst_imm))
3836                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3837                         else {
3838                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3839                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3840                         }
3841                         break;
3842                 case OP_LOADI4_MEM:
3843                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3844                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3845                         break;
3846                 case OP_LOADU4_MEM:
3847                         // FIXME: Decompose this earlier
3848                         if (amd64_is_imm32 (ins->inst_imm))
3849                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3850                         else {
3851                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3852                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3853                         }
3854                         break;
3855                 case OP_LOADU1_MEM:
3856                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3857                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3858                         break;
3859                 case OP_LOADU2_MEM:
3860                         /* For NaCl, pointers are 4 bytes, so separate these */
3861                         /* cases, use literal 8 below where we really want 8 */
3862                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3863                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3864                         break;
3865                 case OP_LOAD_MEMBASE:
3866                         g_assert (amd64_is_imm32 (ins->inst_offset));
3867                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3868                         break;
3869                 case OP_LOADI8_MEMBASE:
3870                         /* Use literal 8 instead of sizeof pointer or */
3871                         /* register, we really want 8 for this opcode */
3872                         g_assert (amd64_is_imm32 (ins->inst_offset));
3873                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3874                         break;
3875                 case OP_LOADI4_MEMBASE:
3876                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3877                         break;
3878                 case OP_LOADU4_MEMBASE:
3879                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3880                         break;
3881                 case OP_LOADU1_MEMBASE:
3882                         /* The cpu zero extends the result into 64 bits */
3883                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3884                         break;
3885                 case OP_LOADI1_MEMBASE:
3886                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3887                         break;
3888                 case OP_LOADU2_MEMBASE:
3889                         /* The cpu zero extends the result into 64 bits */
3890                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3891                         break;
3892                 case OP_LOADI2_MEMBASE:
3893                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3894                         break;
3895                 case OP_AMD64_LOADI8_MEMINDEX:
3896                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3897                         break;
3898                 case OP_LCONV_TO_I1:
3899                 case OP_ICONV_TO_I1:
3900                 case OP_SEXT_I1:
3901                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3902                         break;
3903                 case OP_LCONV_TO_I2:
3904                 case OP_ICONV_TO_I2:
3905                 case OP_SEXT_I2:
3906                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3907                         break;
3908                 case OP_LCONV_TO_U1:
3909                 case OP_ICONV_TO_U1:
3910                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3911                         break;
3912                 case OP_LCONV_TO_U2:
3913                 case OP_ICONV_TO_U2:
3914                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3915                         break;
3916                 case OP_ZEXT_I4:
3917                         /* Clean out the upper word */
3918                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3919                         break;
3920                 case OP_SEXT_I4:
3921                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3922                         break;
3923                 case OP_COMPARE:
3924                 case OP_LCOMPARE:
3925                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3926                         break;
3927                 case OP_COMPARE_IMM:
3928 #if defined(__mono_ilp32__)
3929                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3930                         g_assert (amd64_is_imm32 (ins->inst_imm));
3931                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3932                         break;
3933 #endif
3934                 case OP_LCOMPARE_IMM:
3935                         g_assert (amd64_is_imm32 (ins->inst_imm));
3936                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3937                         break;
3938                 case OP_X86_COMPARE_REG_MEMBASE:
3939                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3940                         break;
3941                 case OP_X86_TEST_NULL:
3942                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3943                         break;
3944                 case OP_AMD64_TEST_NULL:
3945                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3946                         break;
3947
3948                 case OP_X86_ADD_REG_MEMBASE:
3949                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3950                         break;
3951                 case OP_X86_SUB_REG_MEMBASE:
3952                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3953                         break;
3954                 case OP_X86_AND_REG_MEMBASE:
3955                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3956                         break;
3957                 case OP_X86_OR_REG_MEMBASE:
3958                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3959                         break;
3960                 case OP_X86_XOR_REG_MEMBASE:
3961                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3962                         break;
3963
3964                 case OP_X86_ADD_MEMBASE_IMM:
3965                         /* FIXME: Make a 64 version too */
3966                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3967                         break;
3968                 case OP_X86_SUB_MEMBASE_IMM:
3969                         g_assert (amd64_is_imm32 (ins->inst_imm));
3970                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3971                         break;
3972                 case OP_X86_AND_MEMBASE_IMM:
3973                         g_assert (amd64_is_imm32 (ins->inst_imm));
3974                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3975                         break;
3976                 case OP_X86_OR_MEMBASE_IMM:
3977                         g_assert (amd64_is_imm32 (ins->inst_imm));
3978                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3979                         break;
3980                 case OP_X86_XOR_MEMBASE_IMM:
3981                         g_assert (amd64_is_imm32 (ins->inst_imm));
3982                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3983                         break;
3984                 case OP_X86_ADD_MEMBASE_REG:
3985                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3986                         break;
3987                 case OP_X86_SUB_MEMBASE_REG:
3988                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3989                         break;
3990                 case OP_X86_AND_MEMBASE_REG:
3991                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3992                         break;
3993                 case OP_X86_OR_MEMBASE_REG:
3994                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3995                         break;
3996                 case OP_X86_XOR_MEMBASE_REG:
3997                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3998                         break;
3999                 case OP_X86_INC_MEMBASE:
4000                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4001                         break;
4002                 case OP_X86_INC_REG:
4003                         amd64_inc_reg_size (code, ins->dreg, 4);
4004                         break;
4005                 case OP_X86_DEC_MEMBASE:
4006                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4007                         break;
4008                 case OP_X86_DEC_REG:
4009                         amd64_dec_reg_size (code, ins->dreg, 4);
4010                         break;
4011                 case OP_X86_MUL_REG_MEMBASE:
4012                 case OP_X86_MUL_MEMBASE_REG:
4013                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4014                         break;
4015                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4016                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4017                         break;
4018                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4019                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4020                         break;
4021                 case OP_AMD64_COMPARE_MEMBASE_REG:
4022                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4023                         break;
4024                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4025                         g_assert (amd64_is_imm32 (ins->inst_imm));
4026                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4027                         break;
4028                 case OP_X86_COMPARE_MEMBASE8_IMM:
4029                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4030                         break;
4031                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4032                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4033                         break;
4034                 case OP_AMD64_COMPARE_REG_MEMBASE:
4035                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4036                         break;
4037
4038                 case OP_AMD64_ADD_REG_MEMBASE:
4039                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4040                         break;
4041                 case OP_AMD64_SUB_REG_MEMBASE:
4042                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4043                         break;
4044                 case OP_AMD64_AND_REG_MEMBASE:
4045                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4046                         break;
4047                 case OP_AMD64_OR_REG_MEMBASE:
4048                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4049                         break;
4050                 case OP_AMD64_XOR_REG_MEMBASE:
4051                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4052                         break;
4053
4054                 case OP_AMD64_ADD_MEMBASE_REG:
4055                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4056                         break;
4057                 case OP_AMD64_SUB_MEMBASE_REG:
4058                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4059                         break;
4060                 case OP_AMD64_AND_MEMBASE_REG:
4061                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4062                         break;
4063                 case OP_AMD64_OR_MEMBASE_REG:
4064                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4065                         break;
4066                 case OP_AMD64_XOR_MEMBASE_REG:
4067                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4068                         break;
4069
4070                 case OP_AMD64_ADD_MEMBASE_IMM:
4071                         g_assert (amd64_is_imm32 (ins->inst_imm));
4072                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4073                         break;
4074                 case OP_AMD64_SUB_MEMBASE_IMM:
4075                         g_assert (amd64_is_imm32 (ins->inst_imm));
4076                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4077                         break;
4078                 case OP_AMD64_AND_MEMBASE_IMM:
4079                         g_assert (amd64_is_imm32 (ins->inst_imm));
4080                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4081                         break;
4082                 case OP_AMD64_OR_MEMBASE_IMM:
4083                         g_assert (amd64_is_imm32 (ins->inst_imm));
4084                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4085                         break;
4086                 case OP_AMD64_XOR_MEMBASE_IMM:
4087                         g_assert (amd64_is_imm32 (ins->inst_imm));
4088                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4089                         break;
4090
4091                 case OP_BREAK:
4092                         amd64_breakpoint (code);
4093                         break;
4094                 case OP_RELAXED_NOP:
4095                         x86_prefix (code, X86_REP_PREFIX);
4096                         x86_nop (code);
4097                         break;
4098                 case OP_HARD_NOP:
4099                         x86_nop (code);
4100                         break;
4101                 case OP_NOP:
4102                 case OP_DUMMY_USE:
4103                 case OP_DUMMY_STORE:
4104                 case OP_DUMMY_ICONST:
4105                 case OP_DUMMY_R8CONST:
4106                 case OP_NOT_REACHED:
4107                 case OP_NOT_NULL:
4108                         break;
4109                 case OP_IL_SEQ_POINT:
4110                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4111                         break;
4112                 case OP_SEQ_POINT: {
4113                         int i;
4114
4115                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4116                                 if (cfg->compile_aot) {
4117                                         MonoInst *var = cfg->arch.ss_tramp_var;
4118                                         guint8 *label;
4119
4120                                         /* Load ss_tramp_var */
4121                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4122                                         /* Load the trampoline address */
4123                                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4124                                         /* Call it if it is non-null */
4125                                         amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4126                                         label = code;
4127                                         amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4128                                         amd64_call_reg (code, AMD64_R11);
4129                                         amd64_patch (label, code);
4130                                 } else {
4131                                         /*
4132                                          * Read from the single stepping trigger page. This will cause a
4133                                          * SIGSEGV when single stepping is enabled.
4134                                          * We do this _before_ the breakpoint, so single stepping after
4135                                          * a breakpoint is hit will step to the next IL offset.
4136                                          */
4137                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
4138
4139                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4140                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4141                                 }
4142                         }
4143
4144                         /*
4145                          * This is the address which is saved in seq points,
4146                          */
4147                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4148
4149                         if (cfg->compile_aot) {
4150                                 guint32 offset = code - cfg->native_code;
4151                                 guint32 val;
4152                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4153                                 guint8 *label;
4154
4155                                 /* Load info var */
4156                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4157                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4158                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4159                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4160                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4161                                 label = code;
4162                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4163                                 /* Call the trampoline */
4164                                 amd64_call_reg (code, AMD64_R11);
4165                                 amd64_patch (label, code);
4166                         } else {
4167                                 /*
4168                                  * A placeholder for a possible breakpoint inserted by
4169                                  * mono_arch_set_breakpoint ().
4170                                  */
4171                                 for (i = 0; i < breakpoint_size; ++i)
4172                                         x86_nop (code);
4173                         }
4174                         /*
4175                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4176                          * to another IL offset.
4177                          */
4178                         x86_nop (code);
4179                         break;
4180                 }
4181                 case OP_ADDCC:
4182                 case OP_LADDCC:
4183                 case OP_LADD:
4184                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4185                         break;
4186                 case OP_ADC:
4187                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4188                         break;
4189                 case OP_ADD_IMM:
4190                 case OP_LADD_IMM:
4191                         g_assert (amd64_is_imm32 (ins->inst_imm));
4192                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4193                         break;
4194                 case OP_ADC_IMM:
4195                         g_assert (amd64_is_imm32 (ins->inst_imm));
4196                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4197                         break;
4198                 case OP_SUBCC:
4199                 case OP_LSUBCC:
4200                 case OP_LSUB:
4201                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4202                         break;
4203                 case OP_SBB:
4204                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4205                         break;
4206                 case OP_SUB_IMM:
4207                 case OP_LSUB_IMM:
4208                         g_assert (amd64_is_imm32 (ins->inst_imm));
4209                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4210                         break;
4211                 case OP_SBB_IMM:
4212                         g_assert (amd64_is_imm32 (ins->inst_imm));
4213                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4214                         break;
4215                 case OP_LAND:
4216                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4217                         break;
4218                 case OP_AND_IMM:
4219                 case OP_LAND_IMM:
4220                         g_assert (amd64_is_imm32 (ins->inst_imm));
4221                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4222                         break;
4223                 case OP_LMUL:
4224                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4225                         break;
4226                 case OP_MUL_IMM:
4227                 case OP_LMUL_IMM:
4228                 case OP_IMUL_IMM: {
4229                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4230
4231                         switch (ins->inst_imm) {
4232                         case 2:
4233                                 /* MOV r1, r2 */
4234                                 /* ADD r1, r1 */
4235                                 if (ins->dreg != ins->sreg1)
4236                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4237                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4238                                 break;
4239                         case 3:
4240                                 /* LEA r1, [r2 + r2*2] */
4241                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4242                                 break;
4243                         case 5:
4244                                 /* LEA r1, [r2 + r2*4] */
4245                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4246                                 break;
4247                         case 6:
4248                                 /* LEA r1, [r2 + r2*2] */
4249                                 /* ADD r1, r1          */
4250                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4251                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4252                                 break;
4253                         case 9:
4254                                 /* LEA r1, [r2 + r2*8] */
4255                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4256                                 break;
4257                         case 10:
4258                                 /* LEA r1, [r2 + r2*4] */
4259                                 /* ADD r1, r1          */
4260                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4261                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4262                                 break;
4263                         case 12:
4264                                 /* LEA r1, [r2 + r2*2] */
4265                                 /* SHL r1, 2           */
4266                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4267                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4268                                 break;
4269                         case 25:
4270                                 /* LEA r1, [r2 + r2*4] */
4271                                 /* LEA r1, [r1 + r1*4] */
4272                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4273                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4274                                 break;
4275                         case 100:
4276                                 /* LEA r1, [r2 + r2*4] */
4277                                 /* SHL r1, 2           */
4278                                 /* LEA r1, [r1 + r1*4] */
4279                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4280                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4281                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4282                                 break;
4283                         default:
4284                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4285                                 break;
4286                         }
4287                         break;
4288                 }
4289                 case OP_LDIV:
4290                 case OP_LREM:
4291 #if defined( __native_client_codegen__ )
4292                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4293                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4294 #endif
4295                         /* Regalloc magic makes the div/rem cases the same */
4296                         if (ins->sreg2 == AMD64_RDX) {
4297                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4298                                 amd64_cdq (code);
4299                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4300                         } else {
4301                                 amd64_cdq (code);
4302                                 amd64_div_reg (code, ins->sreg2, TRUE);
4303                         }
4304                         break;
4305                 case OP_LDIV_UN:
4306                 case OP_LREM_UN:
4307 #if defined( __native_client_codegen__ )
4308                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4309                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4310 #endif
4311                         if (ins->sreg2 == AMD64_RDX) {
4312                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4313                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4314                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4315                         } else {
4316                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4317                                 amd64_div_reg (code, ins->sreg2, FALSE);
4318                         }
4319                         break;
4320                 case OP_IDIV:
4321                 case OP_IREM:
4322 #if defined( __native_client_codegen__ )
4323                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4324                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4325 #endif
4326                         if (ins->sreg2 == AMD64_RDX) {
4327                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4328                                 amd64_cdq_size (code, 4);
4329                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4330                         } else {
4331                                 amd64_cdq_size (code, 4);
4332                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4333                         }
4334                         break;
4335                 case OP_IDIV_UN:
4336                 case OP_IREM_UN:
4337 #if defined( __native_client_codegen__ )
4338                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4339                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4340 #endif
4341                         if (ins->sreg2 == AMD64_RDX) {
4342                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4343                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4344                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4345                         } else {
4346                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4347                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4348                         }
4349                         break;
4350                 case OP_LMUL_OVF:
4351                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4352                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4353                         break;
4354                 case OP_LOR:
4355                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4356                         break;
4357                 case OP_OR_IMM:
4358                 case OP_LOR_IMM:
4359                         g_assert (amd64_is_imm32 (ins->inst_imm));
4360                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4361                         break;
4362                 case OP_LXOR:
4363                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4364                         break;
4365                 case OP_XOR_IMM:
4366                 case OP_LXOR_IMM:
4367                         g_assert (amd64_is_imm32 (ins->inst_imm));
4368                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4369                         break;
4370                 case OP_LSHL:
4371                         g_assert (ins->sreg2 == AMD64_RCX);
4372                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4373                         break;
4374                 case OP_LSHR:
4375                         g_assert (ins->sreg2 == AMD64_RCX);
4376                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4377                         break;
4378                 case OP_SHR_IMM:
4379                 case OP_LSHR_IMM:
4380                         g_assert (amd64_is_imm32 (ins->inst_imm));
4381                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4382                         break;
4383                 case OP_SHR_UN_IMM:
4384                         g_assert (amd64_is_imm32 (ins->inst_imm));
4385                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4386                         break;
4387                 case OP_LSHR_UN_IMM:
4388                         g_assert (amd64_is_imm32 (ins->inst_imm));
4389                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4390                         break;
4391                 case OP_LSHR_UN:
4392                         g_assert (ins->sreg2 == AMD64_RCX);
4393                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4394                         break;
4395                 case OP_SHL_IMM:
4396                 case OP_LSHL_IMM:
4397                         g_assert (amd64_is_imm32 (ins->inst_imm));
4398                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4399                         break;
4400
4401                 case OP_IADDCC:
4402                 case OP_IADD:
4403                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4404                         break;
4405                 case OP_IADC:
4406                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4407                         break;
4408                 case OP_IADD_IMM:
4409                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4410                         break;
4411                 case OP_IADC_IMM:
4412                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4413                         break;
4414                 case OP_ISUBCC:
4415                 case OP_ISUB:
4416                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4417                         break;
4418                 case OP_ISBB:
4419                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4420                         break;
4421                 case OP_ISUB_IMM:
4422                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4423                         break;
4424                 case OP_ISBB_IMM:
4425                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4426                         break;
4427                 case OP_IAND:
4428                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4429                         break;
4430                 case OP_IAND_IMM:
4431                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4432                         break;
4433                 case OP_IOR:
4434                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4435                         break;
4436                 case OP_IOR_IMM:
4437                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4438                         break;
4439                 case OP_IXOR:
4440                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4441                         break;
4442                 case OP_IXOR_IMM:
4443                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4444                         break;
4445                 case OP_INEG:
4446                         amd64_neg_reg_size (code, ins->sreg1, 4);
4447                         break;
4448                 case OP_INOT:
4449                         amd64_not_reg_size (code, ins->sreg1, 4);
4450                         break;
4451                 case OP_ISHL:
4452                         g_assert (ins->sreg2 == AMD64_RCX);
4453                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4454                         break;
4455                 case OP_ISHR:
4456                         g_assert (ins->sreg2 == AMD64_RCX);
4457                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4458                         break;
4459                 case OP_ISHR_IMM:
4460                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4461                         break;
4462                 case OP_ISHR_UN_IMM:
4463                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4464                         break;
4465                 case OP_ISHR_UN:
4466                         g_assert (ins->sreg2 == AMD64_RCX);
4467                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4468                         break;
4469                 case OP_ISHL_IMM:
4470                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4471                         break;
4472                 case OP_IMUL:
4473                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4474                         break;
4475                 case OP_IMUL_OVF:
4476                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4477                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4478                         break;
4479                 case OP_IMUL_OVF_UN:
4480                 case OP_LMUL_OVF_UN: {
4481                         /* the mul operation and the exception check should most likely be split */
4482                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4483                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4484                         /*g_assert (ins->sreg2 == X86_EAX);
4485                         g_assert (ins->dreg == X86_EAX);*/
4486                         if (ins->sreg2 == X86_EAX) {
4487                                 non_eax_reg = ins->sreg1;
4488                         } else if (ins->sreg1 == X86_EAX) {
4489                                 non_eax_reg = ins->sreg2;
4490                         } else {
4491                                 /* no need to save since we're going to store to it anyway */
4492                                 if (ins->dreg != X86_EAX) {
4493                                         saved_eax = TRUE;
4494                                         amd64_push_reg (code, X86_EAX);
4495                                 }
4496                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4497                                 non_eax_reg = ins->sreg2;
4498                         }
4499                         if (ins->dreg == X86_EDX) {
4500                                 if (!saved_eax) {
4501                                         saved_eax = TRUE;
4502                                         amd64_push_reg (code, X86_EAX);
4503                                 }
4504                         } else {
4505                                 saved_edx = TRUE;
4506                                 amd64_push_reg (code, X86_EDX);
4507                         }
4508                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4509                         /* save before the check since pop and mov don't change the flags */
4510                         if (ins->dreg != X86_EAX)
4511                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4512                         if (saved_edx)
4513                                 amd64_pop_reg (code, X86_EDX);
4514                         if (saved_eax)
4515                                 amd64_pop_reg (code, X86_EAX);
4516                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4517                         break;
4518                 }
4519                 case OP_ICOMPARE:
4520                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4521                         break;
4522                 case OP_ICOMPARE_IMM:
4523                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4524                         break;
4525                 case OP_IBEQ:
4526                 case OP_IBLT:
4527                 case OP_IBGT:
4528                 case OP_IBGE:
4529                 case OP_IBLE:
4530                 case OP_LBEQ:
4531                 case OP_LBLT:
4532                 case OP_LBGT:
4533                 case OP_LBGE:
4534                 case OP_LBLE:
4535                 case OP_IBNE_UN:
4536                 case OP_IBLT_UN:
4537                 case OP_IBGT_UN:
4538                 case OP_IBGE_UN:
4539                 case OP_IBLE_UN:
4540                 case OP_LBNE_UN:
4541                 case OP_LBLT_UN:
4542                 case OP_LBGT_UN:
4543                 case OP_LBGE_UN:
4544                 case OP_LBLE_UN:
4545                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4546                         break;
4547
4548                 case OP_CMOV_IEQ:
4549                 case OP_CMOV_IGE:
4550                 case OP_CMOV_IGT:
4551                 case OP_CMOV_ILE:
4552                 case OP_CMOV_ILT:
4553                 case OP_CMOV_INE_UN:
4554                 case OP_CMOV_IGE_UN:
4555                 case OP_CMOV_IGT_UN:
4556                 case OP_CMOV_ILE_UN:
4557                 case OP_CMOV_ILT_UN:
4558                 case OP_CMOV_LEQ:
4559                 case OP_CMOV_LGE:
4560                 case OP_CMOV_LGT:
4561                 case OP_CMOV_LLE:
4562                 case OP_CMOV_LLT:
4563                 case OP_CMOV_LNE_UN:
4564                 case OP_CMOV_LGE_UN:
4565                 case OP_CMOV_LGT_UN:
4566                 case OP_CMOV_LLE_UN:
4567                 case OP_CMOV_LLT_UN:
4568                         g_assert (ins->dreg == ins->sreg1);
4569                         /* This needs to operate on 64 bit values */
4570                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4571                         break;
4572
4573                 case OP_LNOT:
4574                         amd64_not_reg (code, ins->sreg1);
4575                         break;
4576                 case OP_LNEG:
4577                         amd64_neg_reg (code, ins->sreg1);
4578                         break;
4579
4580                 case OP_ICONST:
4581                 case OP_I8CONST:
4582                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4583                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4584                         else
4585                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4586                         break;
4587                 case OP_AOTCONST:
4588                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4589                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4590                         break;
4591                 case OP_JUMP_TABLE:
4592                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4593                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4594                         break;
4595                 case OP_MOVE:
4596                         if (ins->dreg != ins->sreg1)
4597                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4598                         break;
4599                 case OP_AMD64_SET_XMMREG_R4: {
4600                         if (cfg->r4fp) {
4601                                 if (ins->dreg != ins->sreg1)
4602                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4603                         } else {
4604                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4605                         }
4606                         break;
4607                 }
4608                 case OP_AMD64_SET_XMMREG_R8: {
4609                         if (ins->dreg != ins->sreg1)
4610                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4611                         break;
4612                 }
4613                 case OP_TAILCALL: {
4614                         MonoCallInst *call = (MonoCallInst*)ins;
4615                         int i, save_area_offset;
4616
4617                         g_assert (!cfg->method->save_lmf);
4618
4619                         /* Restore callee saved registers */
4620                         save_area_offset = cfg->arch.reg_save_area_offset;
4621                         for (i = 0; i < AMD64_NREG; ++i)
4622                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4623                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4624                                         save_area_offset += 8;
4625                                 }
4626
4627                         if (cfg->arch.omit_fp) {
4628                                 if (cfg->arch.stack_alloc_size)
4629                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4630                                 // FIXME:
4631                                 if (call->stack_usage)
4632                                         NOT_IMPLEMENTED;
4633                         } else {
4634                                 /* Copy arguments on the stack to our argument area */
4635                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4636                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4637                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4638                                 }
4639
4640                                 amd64_leave (code);
4641                         }
4642
4643                         offset = code - cfg->native_code;
4644                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4645                         if (cfg->compile_aot)
4646                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4647                         else
4648                                 amd64_set_reg_template (code, AMD64_R11);
4649                         amd64_jump_reg (code, AMD64_R11);
4650                         ins->flags |= MONO_INST_GC_CALLSITE;
4651                         ins->backend.pc_offset = code - cfg->native_code;
4652                         break;
4653                 }
4654                 case OP_CHECK_THIS:
4655                         /* ensure ins->sreg1 is not NULL */
4656                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4657                         break;
4658                 case OP_ARGLIST: {
4659                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4660                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4661                         break;
4662                 }
4663                 case OP_CALL:
4664                 case OP_FCALL:
4665                 case OP_RCALL:
4666                 case OP_LCALL:
4667                 case OP_VCALL:
4668                 case OP_VCALL2:
4669                 case OP_VOIDCALL:
4670                         call = (MonoCallInst*)ins;
4671                         /*
4672                          * The AMD64 ABI forces callers to know about varargs.
4673                          */
4674                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4675                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4676                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4677                                 /*
4678                                  * Since the unmanaged calling convention doesn't contain a
4679                                  * 'vararg' entry, we have to treat every pinvoke call as a
4680                                  * potential vararg call.
4681                                  */
4682                                 guint32 nregs, i;
4683                                 nregs = 0;
4684                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4685                                         if (call->used_fregs & (1 << i))
4686                                                 nregs ++;
4687                                 if (!nregs)
4688                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4689                                 else
4690                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4691                         }
4692
4693                         if (ins->flags & MONO_INST_HAS_METHOD)
4694                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4695                         else
4696                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4697                         ins->flags |= MONO_INST_GC_CALLSITE;
4698                         ins->backend.pc_offset = code - cfg->native_code;
4699                         code = emit_move_return_value (cfg, ins, code);
4700                         break;
4701                 case OP_FCALL_REG:
4702                 case OP_RCALL_REG:
4703                 case OP_LCALL_REG:
4704                 case OP_VCALL_REG:
4705                 case OP_VCALL2_REG:
4706                 case OP_VOIDCALL_REG:
4707                 case OP_CALL_REG:
4708                         call = (MonoCallInst*)ins;
4709
4710                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4711                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4712                                 ins->sreg1 = AMD64_R11;
4713                         }
4714
4715                         /*
4716                          * The AMD64 ABI forces callers to know about varargs.
4717                          */
4718                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4719                                 if (ins->sreg1 == AMD64_RAX) {
4720                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4721                                         ins->sreg1 = AMD64_R11;
4722                                 }
4723                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4724                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4725                                 /*
4726                                  * Since the unmanaged calling convention doesn't contain a
4727                                  * 'vararg' entry, we have to treat every pinvoke call as a
4728                                  * potential vararg call.
4729                                  */
4730                                 guint32 nregs, i;
4731                                 nregs = 0;
4732                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4733                                         if (call->used_fregs & (1 << i))
4734                                                 nregs ++;
4735                                 if (ins->sreg1 == AMD64_RAX) {
4736                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4737                                         ins->sreg1 = AMD64_R11;
4738                                 }
4739                                 if (!nregs)
4740                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4741                                 else
4742                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4743                         }
4744
4745                         amd64_call_reg (code, ins->sreg1);
4746                         ins->flags |= MONO_INST_GC_CALLSITE;
4747                         ins->backend.pc_offset = code - cfg->native_code;
4748                         code = emit_move_return_value (cfg, ins, code);
4749                         break;
4750                 case OP_FCALL_MEMBASE:
4751                 case OP_RCALL_MEMBASE:
4752                 case OP_LCALL_MEMBASE:
4753                 case OP_VCALL_MEMBASE:
4754                 case OP_VCALL2_MEMBASE:
4755                 case OP_VOIDCALL_MEMBASE:
4756                 case OP_CALL_MEMBASE:
4757                         call = (MonoCallInst*)ins;
4758
4759                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4760                         ins->flags |= MONO_INST_GC_CALLSITE;
4761                         ins->backend.pc_offset = code - cfg->native_code;
4762                         code = emit_move_return_value (cfg, ins, code);
4763                         break;
4764                 case OP_DYN_CALL: {
4765                         int i;
4766                         MonoInst *var = cfg->dyn_call_var;
4767
4768                         g_assert (var->opcode == OP_REGOFFSET);
4769
4770                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4771                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4772                         /* r10 = ftn */
4773                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4774
4775                         /* Save args buffer */
4776                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4777
4778                         /* Set argument registers */
4779                         for (i = 0; i < PARAM_REGS; ++i)
4780                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4781
4782                         /* Make the call */
4783                         amd64_call_reg (code, AMD64_R10);
4784
4785                         ins->flags |= MONO_INST_GC_CALLSITE;
4786                         ins->backend.pc_offset = code - cfg->native_code;
4787
4788                         /* Save result */
4789                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4790                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4791                         break;
4792                 }
4793                 case OP_AMD64_SAVE_SP_TO_LMF: {
4794                         MonoInst *lmf_var = cfg->lmf_var;
4795                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4796                         break;
4797                 }
4798                 case OP_X86_PUSH:
4799                         g_assert_not_reached ();
4800                         amd64_push_reg (code, ins->sreg1);
4801                         break;
4802                 case OP_X86_PUSH_IMM:
4803                         g_assert_not_reached ();
4804                         g_assert (amd64_is_imm32 (ins->inst_imm));
4805                         amd64_push_imm (code, ins->inst_imm);
4806                         break;
4807                 case OP_X86_PUSH_MEMBASE:
4808                         g_assert_not_reached ();
4809                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4810                         break;
4811                 case OP_X86_PUSH_OBJ: {
4812                         int size = ALIGN_TO (ins->inst_imm, 8);
4813
4814                         g_assert_not_reached ();
4815
4816                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4817                         amd64_push_reg (code, AMD64_RDI);
4818                         amd64_push_reg (code, AMD64_RSI);
4819                         amd64_push_reg (code, AMD64_RCX);
4820                         if (ins->inst_offset)
4821                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4822                         else
4823                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4824                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4825                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4826                         amd64_cld (code);
4827                         amd64_prefix (code, X86_REP_PREFIX);
4828                         amd64_movsd (code);
4829                         amd64_pop_reg (code, AMD64_RCX);
4830                         amd64_pop_reg (code, AMD64_RSI);
4831                         amd64_pop_reg (code, AMD64_RDI);
4832                         break;
4833                 }
4834                 case OP_GENERIC_CLASS_INIT: {
4835                         static int byte_offset = -1;
4836                         static guint8 bitmask;
4837                         guint8 *jump;
4838
4839                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4840
4841                         if (byte_offset < 0)
4842                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4843
4844                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4845                         jump = code;
4846                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4847
4848                         code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ADDR, "specific_trampoline_generic_class_init", FALSE);
4849                         ins->flags |= MONO_INST_GC_CALLSITE;
4850                         ins->backend.pc_offset = code - cfg->native_code;
4851
4852                         x86_patch (jump, code);
4853                         break;
4854                 }
4855
4856                 case OP_X86_LEA:
4857                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4858                         break;
4859                 case OP_X86_LEA_MEMBASE:
4860                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4861                         break;
4862                 case OP_X86_XCHG:
4863                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4864                         break;
4865                 case OP_LOCALLOC:
4866                         /* keep alignment */
4867                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4868                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4869                         code = mono_emit_stack_alloc (cfg, code, ins);
4870                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4871                         if (cfg->param_area)
4872                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4873                         break;
4874                 case OP_LOCALLOC_IMM: {
4875                         guint32 size = ins->inst_imm;
4876                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4877
4878                         if (ins->flags & MONO_INST_INIT) {
4879                                 if (size < 64) {
4880                                         int i;
4881
4882                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4883                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4884
4885                                         for (i = 0; i < size; i += 8)
4886                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4887                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4888                                 } else {
4889                                         amd64_mov_reg_imm (code, ins->dreg, size);
4890                                         ins->sreg1 = ins->dreg;
4891
4892                                         code = mono_emit_stack_alloc (cfg, code, ins);
4893                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4894                                 }
4895                         } else {
4896                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4897                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4898                         }
4899                         if (cfg->param_area)
4900                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4901                         break;
4902                 }
4903                 case OP_THROW: {
4904                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4905                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4906                                              (gpointer)"mono_arch_throw_exception", FALSE);
4907                         ins->flags |= MONO_INST_GC_CALLSITE;
4908                         ins->backend.pc_offset = code - cfg->native_code;
4909                         break;
4910                 }
4911                 case OP_RETHROW: {
4912                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4913                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4914                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4915                         ins->flags |= MONO_INST_GC_CALLSITE;
4916                         ins->backend.pc_offset = code - cfg->native_code;
4917                         break;
4918                 }
4919                 case OP_CALL_HANDLER:
4920                         /* Align stack */
4921                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4922                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4923                         amd64_call_imm (code, 0);
4924                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4925                         /* Restore stack alignment */
4926                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4927                         break;
4928                 case OP_START_HANDLER: {
4929                         /* Even though we're saving RSP, use sizeof */
4930                         /* gpointer because spvar is of type IntPtr */
4931                         /* see: mono_create_spvar_for_region */
4932                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4933                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4934
4935                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4936                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4937                                 cfg->param_area) {
4938                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4939                         }
4940                         break;
4941                 }
4942                 case OP_ENDFINALLY: {
4943                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4944                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4945                         amd64_ret (code);
4946                         break;
4947                 }
4948                 case OP_ENDFILTER: {
4949                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4950                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4951                         /* The local allocator will put the result into RAX */
4952                         amd64_ret (code);
4953                         break;
4954                 }
4955                 case OP_GET_EX_OBJ:
4956                         if (ins->dreg != AMD64_RAX)
4957                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4958                         break;
4959                 case OP_LABEL:
4960                         ins->inst_c0 = code - cfg->native_code;
4961                         break;
4962                 case OP_BR:
4963                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4964                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4965                         //break;
4966                                 if (ins->inst_target_bb->native_offset) {
4967                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4968                                 } else {
4969                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4970                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4971                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4972                                                 x86_jump8 (code, 0);
4973                                         else
4974                                                 x86_jump32 (code, 0);
4975                         }
4976                         break;
4977                 case OP_BR_REG:
4978                         amd64_jump_reg (code, ins->sreg1);
4979                         break;
4980                 case OP_ICNEQ:
4981                 case OP_ICGE:
4982                 case OP_ICLE:
4983                 case OP_ICGE_UN:
4984                 case OP_ICLE_UN:
4985
4986                 case OP_CEQ:
4987                 case OP_LCEQ:
4988                 case OP_ICEQ:
4989                 case OP_CLT:
4990                 case OP_LCLT:
4991                 case OP_ICLT:
4992                 case OP_CGT:
4993                 case OP_ICGT:
4994                 case OP_LCGT:
4995                 case OP_CLT_UN:
4996                 case OP_LCLT_UN:
4997                 case OP_ICLT_UN:
4998                 case OP_CGT_UN:
4999                 case OP_LCGT_UN:
5000                 case OP_ICGT_UN:
5001                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5002                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5003                         break;
5004                 case OP_COND_EXC_EQ:
5005                 case OP_COND_EXC_NE_UN:
5006                 case OP_COND_EXC_LT:
5007                 case OP_COND_EXC_LT_UN:
5008                 case OP_COND_EXC_GT:
5009                 case OP_COND_EXC_GT_UN:
5010                 case OP_COND_EXC_GE:
5011                 case OP_COND_EXC_GE_UN:
5012                 case OP_COND_EXC_LE:
5013                 case OP_COND_EXC_LE_UN:
5014                 case OP_COND_EXC_IEQ:
5015                 case OP_COND_EXC_INE_UN:
5016                 case OP_COND_EXC_ILT:
5017                 case OP_COND_EXC_ILT_UN:
5018                 case OP_COND_EXC_IGT:
5019                 case OP_COND_EXC_IGT_UN:
5020                 case OP_COND_EXC_IGE:
5021                 case OP_COND_EXC_IGE_UN:
5022                 case OP_COND_EXC_ILE:
5023                 case OP_COND_EXC_ILE_UN:
5024                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5025                         break;
5026                 case OP_COND_EXC_OV:
5027                 case OP_COND_EXC_NO:
5028                 case OP_COND_EXC_C:
5029                 case OP_COND_EXC_NC:
5030                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5031                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5032                         break;
5033                 case OP_COND_EXC_IOV:
5034                 case OP_COND_EXC_INO:
5035                 case OP_COND_EXC_IC:
5036                 case OP_COND_EXC_INC:
5037                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5038                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5039                         break;
5040
5041                 /* floating point opcodes */
5042                 case OP_R8CONST: {
5043                         double d = *(double *)ins->inst_p0;
5044
5045                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5046                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5047                         }
5048                         else {
5049                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5050                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5051                         }
5052                         break;
5053                 }
5054                 case OP_R4CONST: {
5055                         float f = *(float *)ins->inst_p0;
5056
5057                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5058                                 if (cfg->r4fp)
5059                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5060                                 else
5061                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5062                         }
5063                         else {
5064                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5065                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5066                                 if (!cfg->r4fp)
5067                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5068                         }
5069                         break;
5070                 }
5071                 case OP_STORER8_MEMBASE_REG:
5072                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5073                         break;
5074                 case OP_LOADR8_MEMBASE:
5075                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5076                         break;
5077                 case OP_STORER4_MEMBASE_REG:
5078                         if (cfg->r4fp) {
5079                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5080                         } else {
5081                                 /* This requires a double->single conversion */
5082                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5083                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5084                         }
5085                         break;
5086                 case OP_LOADR4_MEMBASE:
5087                         if (cfg->r4fp) {
5088                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5089                         } else {
5090                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5091                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5092                         }
5093                         break;
5094                 case OP_ICONV_TO_R4:
5095                         if (cfg->r4fp) {
5096                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5097                         } else {
5098                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5099                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5100                         }
5101                         break;
5102                 case OP_ICONV_TO_R8:
5103                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5104                         break;
5105                 case OP_LCONV_TO_R4:
5106                         if (cfg->r4fp) {
5107                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5108                         } else {
5109                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5110                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5111                         }
5112                         break;
5113                 case OP_LCONV_TO_R8:
5114                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5115                         break;
5116                 case OP_FCONV_TO_R4:
5117                         if (cfg->r4fp) {
5118                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5119                         } else {
5120                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5121                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5122                         }
5123                         break;
5124                 case OP_FCONV_TO_I1:
5125                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5126                         break;
5127                 case OP_FCONV_TO_U1:
5128                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5129                         break;
5130                 case OP_FCONV_TO_I2:
5131                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5132                         break;
5133                 case OP_FCONV_TO_U2:
5134                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5135                         break;
5136                 case OP_FCONV_TO_U4:
5137                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5138                         break;
5139                 case OP_FCONV_TO_I4:
5140                 case OP_FCONV_TO_I:
5141                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5142                         break;
5143                 case OP_FCONV_TO_I8:
5144                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5145                         break;
5146
5147                 case OP_RCONV_TO_I1:
5148                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5149                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5150                         break;
5151                 case OP_RCONV_TO_U1:
5152                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5153                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5154                         break;
5155                 case OP_RCONV_TO_I2:
5156                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5157                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5158                         break;
5159                 case OP_RCONV_TO_U2:
5160                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5161                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5162                         break;
5163                 case OP_RCONV_TO_I4:
5164                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5165                         break;
5166                 case OP_RCONV_TO_U4:
5167                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5168                         break;
5169                 case OP_RCONV_TO_I8:
5170                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5171                         break;
5172                 case OP_RCONV_TO_R8:
5173                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5174                         break;
5175                 case OP_RCONV_TO_R4:
5176                         if (ins->dreg != ins->sreg1)
5177                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5178                         break;
5179
5180                 case OP_LCONV_TO_R_UN: {
5181                         guint8 *br [2];
5182
5183                         /* Based on gcc code */
5184                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5185                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5186
5187                         /* Positive case */
5188                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5189                         br [1] = code; x86_jump8 (code, 0);
5190                         amd64_patch (br [0], code);
5191
5192                         /* Negative case */
5193                         /* Save to the red zone */
5194                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5195                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5196                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5197                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5198                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5199                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5200                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5201                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5202                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5203                         /* Restore */
5204                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5205                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5206                         amd64_patch (br [1], code);
5207                         break;
5208                 }
5209                 case OP_LCONV_TO_OVF_U4:
5210                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5211                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5212                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5213                         break;
5214                 case OP_LCONV_TO_OVF_I4_UN:
5215                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5216                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5217                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5218                         break;
5219                 case OP_FMOVE:
5220                         if (ins->dreg != ins->sreg1)
5221                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5222                         break;
5223                 case OP_RMOVE:
5224                         if (ins->dreg != ins->sreg1)
5225                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5226                         break;
5227                 case OP_MOVE_F_TO_I4:
5228                         if (cfg->r4fp) {
5229                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5230                         } else {
5231                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5232                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5233                         }
5234                         break;
5235                 case OP_MOVE_I4_TO_F:
5236                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5237                         if (!cfg->r4fp)
5238                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5239                         break;
5240                 case OP_MOVE_F_TO_I8:
5241                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5242                         break;
5243                 case OP_MOVE_I8_TO_F:
5244                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5245                         break;
5246                 case OP_FADD:
5247                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5248                         break;
5249                 case OP_FSUB:
5250                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5251                         break;
5252                 case OP_FMUL:
5253                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5254                         break;
5255                 case OP_FDIV:
5256                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5257                         break;
5258                 case OP_FNEG: {
5259                         static double r8_0 = -0.0;
5260
5261                         g_assert (ins->sreg1 == ins->dreg);
5262
5263                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5264                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5265                         break;
5266                 }
5267                 case OP_SIN:
5268                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5269                         break;
5270                 case OP_COS:
5271                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5272                         break;
5273                 case OP_ABS: {
5274                         static guint64 d = 0x7fffffffffffffffUL;
5275
5276                         g_assert (ins->sreg1 == ins->dreg);
5277
5278                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5279                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5280                         break;
5281                 }
5282                 case OP_SQRT:
5283                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5284                         break;
5285
5286                 case OP_RADD:
5287                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5288                         break;
5289                 case OP_RSUB:
5290                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5291                         break;
5292                 case OP_RMUL:
5293                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5294                         break;
5295                 case OP_RDIV:
5296                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5297                         break;
5298                 case OP_RNEG: {
5299                         static float r4_0 = -0.0;
5300
5301                         g_assert (ins->sreg1 == ins->dreg);
5302
5303                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5304                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5305                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5306                         break;
5307                 }
5308
5309                 case OP_IMIN:
5310                         g_assert (cfg->opt & MONO_OPT_CMOV);
5311                         g_assert (ins->dreg == ins->sreg1);
5312                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5313                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5314                         break;
5315                 case OP_IMIN_UN:
5316                         g_assert (cfg->opt & MONO_OPT_CMOV);
5317                         g_assert (ins->dreg == ins->sreg1);
5318                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5319                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5320                         break;
5321                 case OP_IMAX:
5322                         g_assert (cfg->opt & MONO_OPT_CMOV);
5323                         g_assert (ins->dreg == ins->sreg1);
5324                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5325                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5326                         break;
5327                 case OP_IMAX_UN:
5328                         g_assert (cfg->opt & MONO_OPT_CMOV);
5329                         g_assert (ins->dreg == ins->sreg1);
5330                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5331                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5332                         break;
5333                 case OP_LMIN:
5334                         g_assert (cfg->opt & MONO_OPT_CMOV);
5335                         g_assert (ins->dreg == ins->sreg1);
5336                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5337                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5338                         break;
5339                 case OP_LMIN_UN:
5340                         g_assert (cfg->opt & MONO_OPT_CMOV);
5341                         g_assert (ins->dreg == ins->sreg1);
5342                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5343                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5344                         break;
5345                 case OP_LMAX:
5346                         g_assert (cfg->opt & MONO_OPT_CMOV);
5347                         g_assert (ins->dreg == ins->sreg1);
5348                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5349                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5350                         break;
5351                 case OP_LMAX_UN:
5352                         g_assert (cfg->opt & MONO_OPT_CMOV);
5353                         g_assert (ins->dreg == ins->sreg1);
5354                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5355                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5356                         break;
5357                 case OP_X86_FPOP:
5358                         break;
5359                 case OP_FCOMPARE:
5360                         /*
5361                          * The two arguments are swapped because the fbranch instructions
5362                          * depend on this for the non-sse case to work.
5363                          */
5364                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5365                         break;
5366                 case OP_RCOMPARE:
5367                         /*
5368                          * FIXME: Get rid of this.
5369                          * The two arguments are swapped because the fbranch instructions
5370                          * depend on this for the non-sse case to work.
5371                          */
5372                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5373                         break;
5374                 case OP_FCNEQ:
5375                 case OP_FCEQ: {
5376                         /* zeroing the register at the start results in
5377                          * shorter and faster code (we can also remove the widening op)
5378                          */
5379                         guchar *unordered_check;
5380
5381                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5382                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5383                         unordered_check = code;
5384                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5385
5386                         if (ins->opcode == OP_FCEQ) {
5387                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5388                                 amd64_patch (unordered_check, code);
5389                         } else {
5390                                 guchar *jump_to_end;
5391                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5392                                 jump_to_end = code;
5393                                 x86_jump8 (code, 0);
5394                                 amd64_patch (unordered_check, code);
5395                                 amd64_inc_reg (code, ins->dreg);
5396                                 amd64_patch (jump_to_end, code);
5397                         }
5398                         break;
5399                 }
5400                 case OP_FCLT:
5401                 case OP_FCLT_UN: {
5402                         /* zeroing the register at the start results in
5403                          * shorter and faster code (we can also remove the widening op)
5404                          */
5405                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5406                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5407                         if (ins->opcode == OP_FCLT_UN) {
5408                                 guchar *unordered_check = code;
5409                                 guchar *jump_to_end;
5410                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5411                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5412                                 jump_to_end = code;
5413                                 x86_jump8 (code, 0);
5414                                 amd64_patch (unordered_check, code);
5415                                 amd64_inc_reg (code, ins->dreg);
5416                                 amd64_patch (jump_to_end, code);
5417                         } else {
5418                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5419                         }
5420                         break;
5421                 }
5422                 case OP_FCLE: {
5423                         guchar *unordered_check;
5424                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5425                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5426                         unordered_check = code;
5427                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5428                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5429                         amd64_patch (unordered_check, code);
5430                         break;
5431                 }
5432                 case OP_FCGT:
5433                 case OP_FCGT_UN: {
5434                         /* zeroing the register at the start results in
5435                          * shorter and faster code (we can also remove the widening op)
5436                          */
5437                         guchar *unordered_check;
5438
5439                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5440                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5441                         if (ins->opcode == OP_FCGT) {
5442                                 unordered_check = code;
5443                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5444                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5445                                 amd64_patch (unordered_check, code);
5446                         } else {
5447                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5448                         }
5449                         break;
5450                 }
5451                 case OP_FCGE: {
5452                         guchar *unordered_check;
5453                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5454                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5455                         unordered_check = code;
5456                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5457                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5458                         amd64_patch (unordered_check, code);
5459                         break;
5460                 }
5461
5462                 case OP_RCEQ:
5463                 case OP_RCGT:
5464                 case OP_RCLT:
5465                 case OP_RCLT_UN:
5466                 case OP_RCGT_UN: {
5467                         int x86_cond;
5468                         gboolean unordered = FALSE;
5469
5470                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5471                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5472
5473                         switch (ins->opcode) {
5474                         case OP_RCEQ:
5475                                 x86_cond = X86_CC_EQ;
5476                                 break;
5477                         case OP_RCGT:
5478                                 x86_cond = X86_CC_LT;
5479                                 break;
5480                         case OP_RCLT:
5481                                 x86_cond = X86_CC_GT;
5482                                 break;
5483                         case OP_RCLT_UN:
5484                                 x86_cond = X86_CC_GT;
5485                                 unordered = TRUE;
5486                                 break;
5487                         case OP_RCGT_UN:
5488                                 x86_cond = X86_CC_LT;
5489                                 unordered = TRUE;
5490                                 break;
5491                         default:
5492                                 g_assert_not_reached ();
5493                                 break;
5494                         }
5495
5496                         if (unordered) {
5497                                 guchar *unordered_check;
5498                                 guchar *jump_to_end;
5499
5500                                 unordered_check = code;
5501                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5502                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5503                                 jump_to_end = code;
5504                                 x86_jump8 (code, 0);
5505                                 amd64_patch (unordered_check, code);
5506                                 amd64_inc_reg (code, ins->dreg);
5507                                 amd64_patch (jump_to_end, code);
5508                         } else {
5509                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5510                         }
5511                         break;
5512                 }
5513                 case OP_FCLT_MEMBASE:
5514                 case OP_FCGT_MEMBASE:
5515                 case OP_FCLT_UN_MEMBASE:
5516                 case OP_FCGT_UN_MEMBASE:
5517                 case OP_FCEQ_MEMBASE: {
5518                         guchar *unordered_check, *jump_to_end;
5519                         int x86_cond;
5520
5521                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5522                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5523
5524                         switch (ins->opcode) {
5525                         case OP_FCEQ_MEMBASE:
5526                                 x86_cond = X86_CC_EQ;
5527                                 break;
5528                         case OP_FCLT_MEMBASE:
5529                         case OP_FCLT_UN_MEMBASE:
5530                                 x86_cond = X86_CC_LT;
5531                                 break;
5532                         case OP_FCGT_MEMBASE:
5533                         case OP_FCGT_UN_MEMBASE:
5534                                 x86_cond = X86_CC_GT;
5535                                 break;
5536                         default:
5537                                 g_assert_not_reached ();
5538                         }
5539
5540                         unordered_check = code;
5541                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5542                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5543
5544                         switch (ins->opcode) {
5545                         case OP_FCEQ_MEMBASE:
5546                         case OP_FCLT_MEMBASE:
5547                         case OP_FCGT_MEMBASE:
5548                                 amd64_patch (unordered_check, code);
5549                                 break;
5550                         case OP_FCLT_UN_MEMBASE:
5551                         case OP_FCGT_UN_MEMBASE:
5552                                 jump_to_end = code;
5553                                 x86_jump8 (code, 0);
5554                                 amd64_patch (unordered_check, code);
5555                                 amd64_inc_reg (code, ins->dreg);
5556                                 amd64_patch (jump_to_end, code);
5557                                 break;
5558                         default:
5559                                 break;
5560                         }
5561                         break;
5562                 }
5563                 case OP_FBEQ: {
5564                         guchar *jump = code;
5565                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5566                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5567                         amd64_patch (jump, code);
5568                         break;
5569                 }
5570                 case OP_FBNE_UN:
5571                         /* Branch if C013 != 100 */
5572                         /* branch if !ZF or (PF|CF) */
5573                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5574                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5575                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5576                         break;
5577                 case OP_FBLT:
5578                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5579                         break;
5580                 case OP_FBLT_UN:
5581                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5582                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5583                         break;
5584                 case OP_FBGT:
5585                 case OP_FBGT_UN:
5586                         if (ins->opcode == OP_FBGT) {
5587                                 guchar *br1;
5588
5589                                 /* skip branch if C1=1 */
5590                                 br1 = code;
5591                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5592                                 /* branch if (C0 | C3) = 1 */
5593                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5594                                 amd64_patch (br1, code);
5595                                 break;
5596                         } else {
5597                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5598                         }
5599                         break;
5600                 case OP_FBGE: {
5601                         /* Branch if C013 == 100 or 001 */
5602                         guchar *br1;
5603
5604                         /* skip branch if C1=1 */
5605                         br1 = code;
5606                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5607                         /* branch if (C0 | C3) = 1 */
5608                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5609                         amd64_patch (br1, code);
5610                         break;
5611                 }
5612                 case OP_FBGE_UN:
5613                         /* Branch if C013 == 000 */
5614                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5615                         break;
5616                 case OP_FBLE: {
5617                         /* Branch if C013=000 or 100 */
5618                         guchar *br1;
5619
5620                         /* skip branch if C1=1 */
5621                         br1 = code;
5622                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5623                         /* branch if C0=0 */
5624                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5625                         amd64_patch (br1, code);
5626                         break;
5627                 }
5628                 case OP_FBLE_UN:
5629                         /* Branch if C013 != 001 */
5630                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5631                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5632                         break;
5633                 case OP_CKFINITE:
5634                         /* Transfer value to the fp stack */
5635                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5636                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5637                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5638
5639                         amd64_push_reg (code, AMD64_RAX);
5640                         amd64_fxam (code);
5641                         amd64_fnstsw (code);
5642                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5643                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5644                         amd64_pop_reg (code, AMD64_RAX);
5645                         amd64_fstp (code, 0);
5646                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5647                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5648                         break;
5649                 case OP_TLS_GET: {
5650                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5651                         break;
5652                 }
5653                 case OP_TLS_GET_REG:
5654                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5655                         break;
5656                 case OP_TLS_SET: {
5657                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5658                         break;
5659                 }
5660                 case OP_TLS_SET_REG: {
5661                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5662                         break;
5663                 }
5664                 case OP_MEMORY_BARRIER: {
5665                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5666                                 x86_mfence (code);
5667                         break;
5668                 }
5669                 case OP_ATOMIC_ADD_I4:
5670                 case OP_ATOMIC_ADD_I8: {
5671                         int dreg = ins->dreg;
5672                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5673
5674                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5675                                 dreg = AMD64_R11;
5676
5677                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5678                         amd64_prefix (code, X86_LOCK_PREFIX);
5679                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5680                         /* dreg contains the old value, add with sreg2 value */
5681                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5682
5683                         if (ins->dreg != dreg)
5684                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5685
5686                         break;
5687                 }
5688                 case OP_ATOMIC_EXCHANGE_I4:
5689                 case OP_ATOMIC_EXCHANGE_I8: {
5690                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5691
5692                         /* LOCK prefix is implied. */
5693                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5694                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5695                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5696                         break;
5697                 }
5698                 case OP_ATOMIC_CAS_I4:
5699                 case OP_ATOMIC_CAS_I8: {
5700                         guint32 size;
5701
5702                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5703                                 size = 8;
5704                         else
5705                                 size = 4;
5706
5707                         /*
5708                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5709                          * an explanation of how this works.
5710                          */
5711                         g_assert (ins->sreg3 == AMD64_RAX);
5712                         g_assert (ins->sreg1 != AMD64_RAX);
5713                         g_assert (ins->sreg1 != ins->sreg2);
5714
5715                         amd64_prefix (code, X86_LOCK_PREFIX);
5716                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5717
5718                         if (ins->dreg != AMD64_RAX)
5719                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5720                         break;
5721                 }
5722                 case OP_ATOMIC_LOAD_I1: {
5723                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5724                         break;
5725                 }
5726                 case OP_ATOMIC_LOAD_U1: {
5727                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5728                         break;
5729                 }
5730                 case OP_ATOMIC_LOAD_I2: {
5731                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5732                         break;
5733                 }
5734                 case OP_ATOMIC_LOAD_U2: {
5735                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5736                         break;
5737                 }
5738                 case OP_ATOMIC_LOAD_I4: {
5739                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5740                         break;
5741                 }
5742                 case OP_ATOMIC_LOAD_U4:
5743                 case OP_ATOMIC_LOAD_I8:
5744                 case OP_ATOMIC_LOAD_U8: {
5745                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5746                         break;
5747                 }
5748                 case OP_ATOMIC_LOAD_R4: {
5749                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5750                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5751                         break;
5752                 }
5753                 case OP_ATOMIC_LOAD_R8: {
5754                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5755                         break;
5756                 }
5757                 case OP_ATOMIC_STORE_I1:
5758                 case OP_ATOMIC_STORE_U1:
5759                 case OP_ATOMIC_STORE_I2:
5760                 case OP_ATOMIC_STORE_U2:
5761                 case OP_ATOMIC_STORE_I4:
5762                 case OP_ATOMIC_STORE_U4:
5763                 case OP_ATOMIC_STORE_I8:
5764                 case OP_ATOMIC_STORE_U8: {
5765                         int size;
5766
5767                         switch (ins->opcode) {
5768                         case OP_ATOMIC_STORE_I1:
5769                         case OP_ATOMIC_STORE_U1:
5770                                 size = 1;
5771                                 break;
5772                         case OP_ATOMIC_STORE_I2:
5773                         case OP_ATOMIC_STORE_U2:
5774                                 size = 2;
5775                                 break;
5776                         case OP_ATOMIC_STORE_I4:
5777                         case OP_ATOMIC_STORE_U4:
5778                                 size = 4;
5779                                 break;
5780                         case OP_ATOMIC_STORE_I8:
5781                         case OP_ATOMIC_STORE_U8:
5782                                 size = 8;
5783                                 break;
5784                         }
5785
5786                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5787
5788                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5789                                 x86_mfence (code);
5790                         break;
5791                 }
5792                 case OP_ATOMIC_STORE_R4: {
5793                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5794                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5795
5796                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5797                                 x86_mfence (code);
5798                         break;
5799                 }
5800                 case OP_ATOMIC_STORE_R8: {
5801                         x86_nop (code);
5802                         x86_nop (code);
5803                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5804                         x86_nop (code);
5805                         x86_nop (code);
5806
5807                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5808                                 x86_mfence (code);
5809                         break;
5810                 }
5811                 case OP_CARD_TABLE_WBARRIER: {
5812                         int ptr = ins->sreg1;
5813                         int value = ins->sreg2;
5814                         guchar *br = 0;
5815                         int nursery_shift, card_table_shift;
5816                         gpointer card_table_mask;
5817                         size_t nursery_size;
5818
5819                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5820                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5821                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5822
5823                         /*If either point to the stack we can simply avoid the WB. This happens due to
5824                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5825                          */
5826                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5827                                 continue;
5828
5829                         /*
5830                          * We need one register we can clobber, we choose EDX and make sreg1
5831                          * fixed EAX to work around limitations in the local register allocator.
5832                          * sreg2 might get allocated to EDX, but that is not a problem since
5833                          * we use it before clobbering EDX.
5834                          */
5835                         g_assert (ins->sreg1 == AMD64_RAX);
5836
5837                         /*
5838                          * This is the code we produce:
5839                          *
5840                          *   edx = value
5841                          *   edx >>= nursery_shift
5842                          *   cmp edx, (nursery_start >> nursery_shift)
5843                          *   jne done
5844                          *   edx = ptr
5845                          *   edx >>= card_table_shift
5846                          *   edx += cardtable
5847                          *   [edx] = 1
5848                          * done:
5849                          */
5850
5851                         if (mono_gc_card_table_nursery_check ()) {
5852                                 if (value != AMD64_RDX)
5853                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5854                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5855                                 if (shifted_nursery_start >> 31) {
5856                                         /*
5857                                          * The value we need to compare against is 64 bits, so we need
5858                                          * another spare register.  We use RBX, which we save and
5859                                          * restore.
5860                                          */
5861                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5862                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5863                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5864                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5865                                 } else {
5866                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5867                                 }
5868                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5869                         }
5870                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5871                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5872                         if (card_table_mask)
5873                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5874
5875                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5876                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5877
5878                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5879
5880                         if (mono_gc_card_table_nursery_check ())
5881                                 x86_patch (br, code);
5882                         break;
5883                 }
5884 #ifdef MONO_ARCH_SIMD_INTRINSICS
5885                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5886                 case OP_ADDPS:
5887                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5888                         break;
5889                 case OP_DIVPS:
5890                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5891                         break;
5892                 case OP_MULPS:
5893                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5894                         break;
5895                 case OP_SUBPS:
5896                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5897                         break;
5898                 case OP_MAXPS:
5899                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5900                         break;
5901                 case OP_MINPS:
5902                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904                 case OP_COMPPS:
5905                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5906                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5907                         break;
5908                 case OP_ANDPS:
5909                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5910                         break;
5911                 case OP_ANDNPS:
5912                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5913                         break;
5914                 case OP_ORPS:
5915                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5916                         break;
5917                 case OP_XORPS:
5918                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_SQRTPS:
5921                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5922                         break;
5923                 case OP_RSQRTPS:
5924                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5925                         break;
5926                 case OP_RCPPS:
5927                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5928                         break;
5929                 case OP_ADDSUBPS:
5930                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5931                         break;
5932                 case OP_HADDPS:
5933                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5934                         break;
5935                 case OP_HSUBPS:
5936                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5937                         break;
5938                 case OP_DUPPS_HIGH:
5939                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5940                         break;
5941                 case OP_DUPPS_LOW:
5942                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5943                         break;
5944
5945                 case OP_PSHUFLEW_HIGH:
5946                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5947                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5948                         break;
5949                 case OP_PSHUFLEW_LOW:
5950                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5951                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5952                         break;
5953                 case OP_PSHUFLED:
5954                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5955                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5956                         break;
5957                 case OP_SHUFPS:
5958                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5959                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5960                         break;
5961                 case OP_SHUFPD:
5962                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5963                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5964                         break;
5965
5966                 case OP_ADDPD:
5967                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5968                         break;
5969                 case OP_DIVPD:
5970                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_MULPD:
5973                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_SUBPD:
5976                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978                 case OP_MAXPD:
5979                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981                 case OP_MINPD:
5982                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984                 case OP_COMPPD:
5985                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5986                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5987                         break;
5988                 case OP_ANDPD:
5989                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5990                         break;
5991                 case OP_ANDNPD:
5992                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5993                         break;
5994                 case OP_ORPD:
5995                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5996                         break;
5997                 case OP_XORPD:
5998                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5999                         break;
6000                 case OP_SQRTPD:
6001                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6002                         break;
6003                 case OP_ADDSUBPD:
6004                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6005                         break;
6006                 case OP_HADDPD:
6007                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009                 case OP_HSUBPD:
6010                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_DUPPD:
6013                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6014                         break;
6015
6016                 case OP_EXTRACT_MASK:
6017                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6018                         break;
6019
6020                 case OP_PAND:
6021                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6022                         break;
6023                 case OP_POR:
6024                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6025                         break;
6026                 case OP_PXOR:
6027                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6028                         break;
6029
6030                 case OP_PADDB:
6031                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6032                         break;
6033                 case OP_PADDW:
6034                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6035                         break;
6036                 case OP_PADDD:
6037                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6038                         break;
6039                 case OP_PADDQ:
6040                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6041                         break;
6042
6043                 case OP_PSUBB:
6044                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6045                         break;
6046                 case OP_PSUBW:
6047                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049                 case OP_PSUBD:
6050                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6051                         break;
6052                 case OP_PSUBQ:
6053                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6054                         break;
6055
6056                 case OP_PMAXB_UN:
6057                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6058                         break;
6059                 case OP_PMAXW_UN:
6060                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062                 case OP_PMAXD_UN:
6063                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6064                         break;
6065
6066                 case OP_PMAXB:
6067                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6068                         break;
6069                 case OP_PMAXW:
6070                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6071                         break;
6072                 case OP_PMAXD:
6073                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6074                         break;
6075
6076                 case OP_PAVGB_UN:
6077                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079                 case OP_PAVGW_UN:
6080                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082
6083                 case OP_PMINB_UN:
6084                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6085                         break;
6086                 case OP_PMINW_UN:
6087                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089                 case OP_PMIND_UN:
6090                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092
6093                 case OP_PMINB:
6094                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096                 case OP_PMINW:
6097                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099                 case OP_PMIND:
6100                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102
6103                 case OP_PCMPEQB:
6104                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106                 case OP_PCMPEQW:
6107                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109                 case OP_PCMPEQD:
6110                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_PCMPEQQ:
6113                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115
6116                 case OP_PCMPGTB:
6117                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6118                         break;
6119                 case OP_PCMPGTW:
6120                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122                 case OP_PCMPGTD:
6123                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6124                         break;
6125                 case OP_PCMPGTQ:
6126                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6127                         break;
6128
6129                 case OP_PSUM_ABS_DIFF:
6130                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6131                         break;
6132
6133                 case OP_UNPACK_LOWB:
6134                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6135                         break;
6136                 case OP_UNPACK_LOWW:
6137                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6138                         break;
6139                 case OP_UNPACK_LOWD:
6140                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6141                         break;
6142                 case OP_UNPACK_LOWQ:
6143                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6144                         break;
6145                 case OP_UNPACK_LOWPS:
6146                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148                 case OP_UNPACK_LOWPD:
6149                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6150                         break;
6151
6152                 case OP_UNPACK_HIGHB:
6153                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6154                         break;
6155                 case OP_UNPACK_HIGHW:
6156                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6157                         break;
6158                 case OP_UNPACK_HIGHD:
6159                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6160                         break;
6161                 case OP_UNPACK_HIGHQ:
6162                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6163                         break;
6164                 case OP_UNPACK_HIGHPS:
6165                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6166                         break;
6167                 case OP_UNPACK_HIGHPD:
6168                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6169                         break;
6170
6171                 case OP_PACKW:
6172                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6173                         break;
6174                 case OP_PACKD:
6175                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6176                         break;
6177                 case OP_PACKW_UN:
6178                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6179                         break;
6180                 case OP_PACKD_UN:
6181                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6182                         break;
6183
6184                 case OP_PADDB_SAT_UN:
6185                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6186                         break;
6187                 case OP_PSUBB_SAT_UN:
6188                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6189                         break;
6190                 case OP_PADDW_SAT_UN:
6191                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6192                         break;
6193                 case OP_PSUBW_SAT_UN:
6194                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6195                         break;
6196
6197                 case OP_PADDB_SAT:
6198                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6199                         break;
6200                 case OP_PSUBB_SAT:
6201                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6202                         break;
6203                 case OP_PADDW_SAT:
6204                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6205                         break;
6206                 case OP_PSUBW_SAT:
6207                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6208                         break;
6209
6210                 case OP_PMULW:
6211                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6212                         break;
6213                 case OP_PMULD:
6214                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6215                         break;
6216                 case OP_PMULQ:
6217                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6218                         break;
6219                 case OP_PMULW_HIGH_UN:
6220                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6221                         break;
6222                 case OP_PMULW_HIGH:
6223                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6224                         break;
6225
6226                 case OP_PSHRW:
6227                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6228                         break;
6229                 case OP_PSHRW_REG:
6230                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6231                         break;
6232
6233                 case OP_PSARW:
6234                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6235                         break;
6236                 case OP_PSARW_REG:
6237                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6238                         break;
6239
6240                 case OP_PSHLW:
6241                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6242                         break;
6243                 case OP_PSHLW_REG:
6244                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6245                         break;
6246
6247                 case OP_PSHRD:
6248                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6249                         break;
6250                 case OP_PSHRD_REG:
6251                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6252                         break;
6253
6254                 case OP_PSARD:
6255                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6256                         break;
6257                 case OP_PSARD_REG:
6258                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6259                         break;
6260
6261                 case OP_PSHLD:
6262                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6263                         break;
6264                 case OP_PSHLD_REG:
6265                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6266                         break;
6267
6268                 case OP_PSHRQ:
6269                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6270                         break;
6271                 case OP_PSHRQ_REG:
6272                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6273                         break;
6274
6275                 /*TODO: This is appart of the sse spec but not added
6276                 case OP_PSARQ:
6277                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6278                         break;
6279                 case OP_PSARQ_REG:
6280                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6281                         break;
6282                 */
6283
6284                 case OP_PSHLQ:
6285                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6286                         break;
6287                 case OP_PSHLQ_REG:
6288                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6289                         break;
6290                 case OP_CVTDQ2PD:
6291                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6292                         break;
6293                 case OP_CVTDQ2PS:
6294                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6295                         break;
6296                 case OP_CVTPD2DQ:
6297                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6298                         break;
6299                 case OP_CVTPD2PS:
6300                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6301                         break;
6302                 case OP_CVTPS2DQ:
6303                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6304                         break;
6305                 case OP_CVTPS2PD:
6306                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6307                         break;
6308                 case OP_CVTTPD2DQ:
6309                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6310                         break;
6311                 case OP_CVTTPS2DQ:
6312                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6313                         break;
6314
6315                 case OP_ICONV_TO_X:
6316                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6317                         break;
6318                 case OP_EXTRACT_I4:
6319                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6320                         break;
6321                 case OP_EXTRACT_I8:
6322                         if (ins->inst_c0) {
6323                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6324                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6325                         } else {
6326                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6327                         }
6328                         break;
6329                 case OP_EXTRACT_I1:
6330                 case OP_EXTRACT_U1:
6331                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6332                         if (ins->inst_c0)
6333                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6334                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6335                         break;
6336                 case OP_EXTRACT_I2:
6337                 case OP_EXTRACT_U2:
6338                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6339                         if (ins->inst_c0)
6340                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6341                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6342                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6343                         break;
6344                 case OP_EXTRACT_R8:
6345                         if (ins->inst_c0)
6346                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6347                         else
6348                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6349                         break;
6350                 case OP_INSERT_I2:
6351                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6352                         break;
6353                 case OP_EXTRACTX_U2:
6354                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6355                         break;
6356                 case OP_INSERTX_U1_SLOW:
6357                         /*sreg1 is the extracted ireg (scratch)
6358                         /sreg2 is the to be inserted ireg (scratch)
6359                         /dreg is the xreg to receive the value*/
6360
6361                         /*clear the bits from the extracted word*/
6362                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6363                         /*shift the value to insert if needed*/
6364                         if (ins->inst_c0 & 1)
6365                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6366                         /*join them together*/
6367                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6368                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6369                         break;
6370                 case OP_INSERTX_I4_SLOW:
6371                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6372                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6373                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6374                         break;
6375                 case OP_INSERTX_I8_SLOW:
6376                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6377                         if (ins->inst_c0)
6378                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6379                         else
6380                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6381                         break;
6382
6383                 case OP_INSERTX_R4_SLOW:
6384                         switch (ins->inst_c0) {
6385                         case 0:
6386                                 if (cfg->r4fp)
6387                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6388                                 else
6389                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6390                                 break;
6391                         case 1:
6392                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6393                                 if (cfg->r4fp)
6394                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6395                                 else
6396                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6397                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6398                                 break;
6399                         case 2:
6400                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6401                                 if (cfg->r4fp)
6402                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6403                                 else
6404                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6405                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6406                                 break;
6407                         case 3:
6408                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6409                                 if (cfg->r4fp)
6410                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6411                                 else
6412                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6413                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6414                                 break;
6415                         }
6416                         break;
6417                 case OP_INSERTX_R8_SLOW:
6418                         if (ins->inst_c0)
6419                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6420                         else
6421                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6422                         break;
6423                 case OP_STOREX_MEMBASE_REG:
6424                 case OP_STOREX_MEMBASE:
6425                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6426                         break;
6427                 case OP_LOADX_MEMBASE:
6428                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6429                         break;
6430                 case OP_LOADX_ALIGNED_MEMBASE:
6431                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6432                         break;
6433                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6434                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6435                         break;
6436                 case OP_STOREX_NTA_MEMBASE_REG:
6437                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6438                         break;
6439                 case OP_PREFETCH_MEMBASE:
6440                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6441                         break;
6442
6443                 case OP_XMOVE:
6444                         /*FIXME the peephole pass should have killed this*/
6445                         if (ins->dreg != ins->sreg1)
6446                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6447                         break;
6448                 case OP_XZERO:
6449                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6450                         break;
6451                 case OP_ICONV_TO_R4_RAW:
6452                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6453                         break;
6454
6455                 case OP_FCONV_TO_R8_X:
6456                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6457                         break;
6458
6459                 case OP_XCONV_R8_TO_I4:
6460                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6461                         switch (ins->backend.source_opcode) {
6462                         case OP_FCONV_TO_I1:
6463                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6464                                 break;
6465                         case OP_FCONV_TO_U1:
6466                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6467                                 break;
6468                         case OP_FCONV_TO_I2:
6469                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6470                                 break;
6471                         case OP_FCONV_TO_U2:
6472                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6473                                 break;
6474                         }
6475                         break;
6476
6477                 case OP_EXPAND_I2:
6478                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6479                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6480                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6481                         break;
6482                 case OP_EXPAND_I4:
6483                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6484                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6485                         break;
6486                 case OP_EXPAND_I8:
6487                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6488                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6489                         break;
6490                 case OP_EXPAND_R4:
6491                         if (cfg->r4fp) {
6492                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6493                         } else {
6494                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6495                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6496                         }
6497                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6498                         break;
6499                 case OP_EXPAND_R8:
6500                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6501                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6502                         break;
6503 #endif
6504                 case OP_LIVERANGE_START: {
6505                         if (cfg->verbose_level > 1)
6506                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6507                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6508                         break;
6509                 }
6510                 case OP_LIVERANGE_END: {
6511                         if (cfg->verbose_level > 1)
6512                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6513                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6514                         break;
6515                 }
6516                 case OP_GC_SAFE_POINT: {
6517                         const char *polling_func = NULL;
6518                         int compare_val = 0;
6519                         guint8 *br [1];
6520
6521 #if defined (USE_COOP_GC)
6522                         polling_func = "mono_threads_state_poll";
6523                         compare_val = 1;
6524 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6525                         polling_func = "mono_nacl_gc";
6526                         compare_val = 0xFFFFFFFF;
6527 #endif
6528                         if (!polling_func)
6529                                 break;
6530
6531                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6532                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6533                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6534                         amd64_patch (br[0], code);
6535                         break;
6536                 }
6537
6538                 case OP_GC_LIVENESS_DEF:
6539                 case OP_GC_LIVENESS_USE:
6540                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6541                         ins->backend.pc_offset = code - cfg->native_code;
6542                         break;
6543                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6544                         ins->backend.pc_offset = code - cfg->native_code;
6545                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6546                         break;
6547                 default:
6548                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6549                         g_assert_not_reached ();
6550                 }
6551
6552                 if ((code - cfg->native_code - offset) > max_len) {
6553 #if !defined(__native_client_codegen__)
6554                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6555                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6556                         g_assert_not_reached ();
6557 #endif
6558                 }
6559         }
6560
6561         cfg->code_len = code - cfg->native_code;
6562 }
6563
6564 #endif /* DISABLE_JIT */
6565
6566 void
6567 mono_arch_register_lowlevel_calls (void)
6568 {
6569         /* The signature doesn't matter */
6570         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6571 }
6572
6573 void
6574 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6575 {
6576         unsigned char *ip = ji->ip.i + code;
6577
6578         /*
6579          * Debug code to help track down problems where the target of a near call is
6580          * is not valid.
6581          */
6582         if (amd64_is_near_call (ip)) {
6583                 gint64 disp = (guint8*)target - (guint8*)ip;
6584
6585                 if (!amd64_is_imm32 (disp)) {
6586                         printf ("TYPE: %d\n", ji->type);
6587                         switch (ji->type) {
6588                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6589                                 printf ("V: %s\n", ji->data.name);
6590                                 break;
6591                         case MONO_PATCH_INFO_METHOD_JUMP:
6592                         case MONO_PATCH_INFO_METHOD:
6593                                 printf ("V: %s\n", ji->data.method->name);
6594                                 break;
6595                         default:
6596                                 break;
6597                         }
6598                 }
6599         }
6600
6601         amd64_patch (ip, (gpointer)target);
6602 }
6603
6604 #ifndef DISABLE_JIT
6605
6606 static int
6607 get_max_epilog_size (MonoCompile *cfg)
6608 {
6609         int max_epilog_size = 16;
6610
6611         if (cfg->method->save_lmf)
6612                 max_epilog_size += 256;
6613
6614         if (mono_jit_trace_calls != NULL)
6615                 max_epilog_size += 50;
6616
6617         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6618                 max_epilog_size += 50;
6619
6620         max_epilog_size += (AMD64_NREG * 2);
6621
6622         return max_epilog_size;
6623 }
6624
6625 /*
6626  * This macro is used for testing whenever the unwinder works correctly at every point
6627  * where an async exception can happen.
6628  */
6629 /* This will generate a SIGSEGV at the given point in the code */
6630 #define async_exc_point(code) do { \
6631     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6632          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6633              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6634          cfg->arch.async_point_count ++; \
6635     } \
6636 } while (0)
6637
6638 guint8 *
6639 mono_arch_emit_prolog (MonoCompile *cfg)
6640 {
6641         MonoMethod *method = cfg->method;
6642         MonoBasicBlock *bb;
6643         MonoMethodSignature *sig;
6644         MonoInst *ins;
6645         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6646         guint8 *code;
6647         CallInfo *cinfo;
6648         MonoInst *lmf_var = cfg->lmf_var;
6649         gboolean args_clobbered = FALSE;
6650         gboolean trace = FALSE;
6651 #ifdef __native_client_codegen__
6652         guint alignment_check;
6653 #endif
6654
6655         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6656
6657 #if defined(__default_codegen__)
6658         code = cfg->native_code = g_malloc (cfg->code_size);
6659 #elif defined(__native_client_codegen__)
6660         /* native_code_alloc is not 32-byte aligned, native_code is. */
6661         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6662
6663         /* Align native_code to next nearest kNaclAlignment byte. */
6664         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6665         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6666
6667         code = cfg->native_code;
6668
6669         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6670         g_assert (alignment_check == 0);
6671 #endif
6672
6673         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6674                 trace = TRUE;
6675
6676         /* Amount of stack space allocated by register saving code */
6677         pos = 0;
6678
6679         /* Offset between RSP and the CFA */
6680         cfa_offset = 0;
6681
6682         /*
6683          * The prolog consists of the following parts:
6684          * FP present:
6685          * - push rbp, mov rbp, rsp
6686          * - save callee saved regs using pushes
6687          * - allocate frame
6688          * - save rgctx if needed
6689          * - save lmf if needed
6690          * FP not present:
6691          * - allocate frame
6692          * - save rgctx if needed
6693          * - save lmf if needed
6694          * - save callee saved regs using moves
6695          */
6696
6697         // CFA = sp + 8
6698         cfa_offset = 8;
6699         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6700         // IP saved at CFA - 8
6701         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6702         async_exc_point (code);
6703         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6704
6705         if (!cfg->arch.omit_fp) {
6706                 amd64_push_reg (code, AMD64_RBP);
6707                 cfa_offset += 8;
6708                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6709                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6710                 async_exc_point (code);
6711 #ifdef TARGET_WIN32
6712                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6713 #endif
6714                 /* These are handled automatically by the stack marking code */
6715                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6716
6717                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6718                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6719                 async_exc_point (code);
6720 #ifdef TARGET_WIN32
6721                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6722 #endif
6723         }
6724
6725         /* The param area is always at offset 0 from sp */
6726         /* This needs to be allocated here, since it has to come after the spill area */
6727         if (cfg->param_area) {
6728                 if (cfg->arch.omit_fp)
6729                         // FIXME:
6730                         g_assert_not_reached ();
6731                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6732         }
6733
6734         if (cfg->arch.omit_fp) {
6735                 /*
6736                  * On enter, the stack is misaligned by the pushing of the return
6737                  * address. It is either made aligned by the pushing of %rbp, or by
6738                  * this.
6739                  */
6740                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6741                 if ((alloc_size % 16) == 0) {
6742                         alloc_size += 8;
6743                         /* Mark the padding slot as NOREF */
6744                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6745                 }
6746         } else {
6747                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6748                 if (cfg->stack_offset != alloc_size) {
6749                         /* Mark the padding slot as NOREF */
6750                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6751                 }
6752                 cfg->arch.sp_fp_offset = alloc_size;
6753                 alloc_size -= pos;
6754         }
6755
6756         cfg->arch.stack_alloc_size = alloc_size;
6757
6758         /* Allocate stack frame */
6759         if (alloc_size) {
6760                 /* See mono_emit_stack_alloc */
6761 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6762                 guint32 remaining_size = alloc_size;
6763                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6764                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6765                 guint32 offset = code - cfg->native_code;
6766                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6767                         while (required_code_size >= (cfg->code_size - offset))
6768                                 cfg->code_size *= 2;
6769                         cfg->native_code = mono_realloc_native_code (cfg);
6770                         code = cfg->native_code + offset;
6771                         cfg->stat_code_reallocs++;
6772                 }
6773
6774                 while (remaining_size >= 0x1000) {
6775                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6776                         if (cfg->arch.omit_fp) {
6777                                 cfa_offset += 0x1000;
6778                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6779                         }
6780                         async_exc_point (code);
6781 #ifdef TARGET_WIN32
6782                         if (cfg->arch.omit_fp)
6783                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6784 #endif
6785
6786                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6787                         remaining_size -= 0x1000;
6788                 }
6789                 if (remaining_size) {
6790                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6791                         if (cfg->arch.omit_fp) {
6792                                 cfa_offset += remaining_size;
6793                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6794                                 async_exc_point (code);
6795                         }
6796 #ifdef TARGET_WIN32
6797                         if (cfg->arch.omit_fp)
6798                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6799 #endif
6800                 }
6801 #else
6802                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6803                 if (cfg->arch.omit_fp) {
6804                         cfa_offset += alloc_size;
6805                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6806                         async_exc_point (code);
6807                 }
6808 #endif
6809         }
6810
6811         /* Stack alignment check */
6812 #if 0
6813         {
6814                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6815                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6816                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6817                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6818                 amd64_breakpoint (code);
6819         }
6820 #endif
6821
6822         if (mini_get_debug_options ()->init_stacks) {
6823                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6824
6825                 /* Save registers to the red zone */
6826                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6827                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6828
6829                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6830                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6831                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6832
6833                 amd64_cld (code);
6834 #if defined(__default_codegen__)
6835                 amd64_prefix (code, X86_REP_PREFIX);
6836                 amd64_stosl (code);
6837 #elif defined(__native_client_codegen__)
6838                 /* NaCl stos pseudo-instruction */
6839                 amd64_codegen_pre (code);
6840                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6841                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6842                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6843                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6844                 amd64_prefix (code, X86_REP_PREFIX);
6845                 amd64_stosl (code);
6846                 amd64_codegen_post (code);
6847 #endif /* __native_client_codegen__ */
6848
6849                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6850                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6851         }
6852
6853         /* Save LMF */
6854         if (method->save_lmf)
6855                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6856
6857         /* Save callee saved registers */
6858         if (cfg->arch.omit_fp) {
6859                 save_area_offset = cfg->arch.reg_save_area_offset;
6860                 /* Save caller saved registers after sp is adjusted */
6861                 /* The registers are saved at the bottom of the frame */
6862                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6863         } else {
6864                 /* The registers are saved just below the saved rbp */
6865                 save_area_offset = cfg->arch.reg_save_area_offset;
6866         }
6867
6868         for (i = 0; i < AMD64_NREG; ++i) {
6869                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6870                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6871
6872                         if (cfg->arch.omit_fp) {
6873                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6874                                 /* These are handled automatically by the stack marking code */
6875                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6876                         } else {
6877                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6878                                 // FIXME: GC
6879                         }
6880
6881                         save_area_offset += 8;
6882                         async_exc_point (code);
6883                 }
6884         }
6885
6886         /* store runtime generic context */
6887         if (cfg->rgctx_var) {
6888                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6889                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6890
6891                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6892
6893                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6894                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6895         }
6896
6897         /* compute max_length in order to use short forward jumps */
6898         max_epilog_size = get_max_epilog_size (cfg);
6899         if (cfg->opt & MONO_OPT_BRANCH) {
6900                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6901                         MonoInst *ins;
6902                         int max_length = 0;
6903
6904                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6905                                 max_length += 6;
6906                         /* max alignment for loops */
6907                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6908                                 max_length += LOOP_ALIGNMENT;
6909 #ifdef __native_client_codegen__
6910                         /* max alignment for native client */
6911                         max_length += kNaClAlignment;
6912 #endif
6913
6914                         MONO_BB_FOR_EACH_INS (bb, ins) {
6915 #ifdef __native_client_codegen__
6916                                 {
6917                                         int space_in_block = kNaClAlignment -
6918                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6919                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6920                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6921                                                 max_length += space_in_block;
6922                                         }
6923                                 }
6924 #endif  /*__native_client_codegen__*/
6925                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6926                         }
6927
6928                         /* Take prolog and epilog instrumentation into account */
6929                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6930                                 max_length += max_epilog_size;
6931
6932                         bb->max_length = max_length;
6933                 }
6934         }
6935
6936         sig = mono_method_signature (method);
6937         pos = 0;
6938
6939         cinfo = cfg->arch.cinfo;
6940
6941         if (sig->ret->type != MONO_TYPE_VOID) {
6942                 /* Save volatile arguments to the stack */
6943                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6944                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6945         }
6946
6947         /* Keep this in sync with emit_load_volatile_arguments */
6948         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6949                 ArgInfo *ainfo = cinfo->args + i;
6950
6951                 ins = cfg->args [i];
6952
6953                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6954                         /* Unused arguments */
6955                         continue;
6956
6957                 /* Save volatile arguments to the stack */
6958                 if (ins->opcode != OP_REGVAR) {
6959                         switch (ainfo->storage) {
6960                         case ArgInIReg: {
6961                                 guint32 size = 8;
6962
6963                                 /* FIXME: I1 etc */
6964                                 /*
6965                                 if (stack_offset & 0x1)
6966                                         size = 1;
6967                                 else if (stack_offset & 0x2)
6968                                         size = 2;
6969                                 else if (stack_offset & 0x4)
6970                                         size = 4;
6971                                 else
6972                                         size = 8;
6973                                 */
6974                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6975
6976                                 /*
6977                                  * Save the original location of 'this',
6978                                  * get_generic_info_from_stack_frame () needs this to properly look up
6979                                  * the argument value during the handling of async exceptions.
6980                                  */
6981                                 if (ins == cfg->args [0]) {
6982                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6983                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6984                                 }
6985                                 break;
6986                         }
6987                         case ArgInFloatSSEReg:
6988                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6989                                 break;
6990                         case ArgInDoubleSSEReg:
6991                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6992                                 break;
6993                         case ArgValuetypeInReg:
6994                                 for (quad = 0; quad < 2; quad ++) {
6995                                         switch (ainfo->pair_storage [quad]) {
6996                                         case ArgInIReg:
6997                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6998                                                 break;
6999                                         case ArgInFloatSSEReg:
7000                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7001                                                 break;
7002                                         case ArgInDoubleSSEReg:
7003                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7004                                                 break;
7005                                         case ArgNone:
7006                                                 break;
7007                                         default:
7008                                                 g_assert_not_reached ();
7009                                         }
7010                                 }
7011                                 break;
7012                         case ArgValuetypeAddrInIReg:
7013                                 if (ainfo->pair_storage [0] == ArgInIReg)
7014                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7015                                 break;
7016                         default:
7017                                 break;
7018                         }
7019                 } else {
7020                         /* Argument allocated to (non-volatile) register */
7021                         switch (ainfo->storage) {
7022                         case ArgInIReg:
7023                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7024                                 break;
7025                         case ArgOnStack:
7026                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7027                                 break;
7028                         default:
7029                                 g_assert_not_reached ();
7030                         }
7031
7032                         if (ins == cfg->args [0]) {
7033                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7034                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7035                         }
7036                 }
7037         }
7038
7039         if (cfg->method->save_lmf)
7040                 args_clobbered = TRUE;
7041
7042         if (trace) {
7043                 args_clobbered = TRUE;
7044                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7045         }
7046
7047         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7048                 args_clobbered = TRUE;
7049
7050         /*
7051          * Optimize the common case of the first bblock making a call with the same
7052          * arguments as the method. This works because the arguments are still in their
7053          * original argument registers.
7054          * FIXME: Generalize this
7055          */
7056         if (!args_clobbered) {
7057                 MonoBasicBlock *first_bb = cfg->bb_entry;
7058                 MonoInst *next;
7059                 int filter = FILTER_IL_SEQ_POINT;
7060
7061                 next = mono_bb_first_inst (first_bb, filter);
7062                 if (!next && first_bb->next_bb) {
7063                         first_bb = first_bb->next_bb;
7064                         next = mono_bb_first_inst (first_bb, filter);
7065                 }
7066
7067                 if (first_bb->in_count > 1)
7068                         next = NULL;
7069
7070                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7071                         ArgInfo *ainfo = cinfo->args + i;
7072                         gboolean match = FALSE;
7073
7074                         ins = cfg->args [i];
7075                         if (ins->opcode != OP_REGVAR) {
7076                                 switch (ainfo->storage) {
7077                                 case ArgInIReg: {
7078                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7079                                                 if (next->dreg == ainfo->reg) {
7080                                                         NULLIFY_INS (next);
7081                                                         match = TRUE;
7082                                                 } else {
7083                                                         next->opcode = OP_MOVE;
7084                                                         next->sreg1 = ainfo->reg;
7085                                                         /* Only continue if the instruction doesn't change argument regs */
7086                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7087                                                                 match = TRUE;
7088                                                 }
7089                                         }
7090                                         break;
7091                                 }
7092                                 default:
7093                                         break;
7094                                 }
7095                         } else {
7096                                 /* Argument allocated to (non-volatile) register */
7097                                 switch (ainfo->storage) {
7098                                 case ArgInIReg:
7099                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7100                                                 NULLIFY_INS (next);
7101                                                 match = TRUE;
7102                                         }
7103                                         break;
7104                                 default:
7105                                         break;
7106                                 }
7107                         }
7108
7109                         if (match) {
7110                                 next = mono_inst_next (next, filter);
7111                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7112                                 if (!next)
7113                                         break;
7114                         }
7115                 }
7116         }
7117
7118         if (cfg->gen_sdb_seq_points) {
7119                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7120
7121                 /* Initialize seq_point_info_var */
7122                 if (cfg->compile_aot) {
7123                         /* Initialize the variable from a GOT slot */
7124                         /* Same as OP_AOTCONST */
7125                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7126                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7127                         g_assert (info_var->opcode == OP_REGOFFSET);
7128                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7129                 }
7130
7131                 if (cfg->compile_aot) {
7132                         /* Initialize ss_tramp_var */
7133                         ins = cfg->arch.ss_tramp_var;
7134                         g_assert (ins->opcode == OP_REGOFFSET);
7135
7136                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7137                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7138                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7139                 } else {
7140                         /* Initialize ss_trigger_page_var */
7141                         ins = cfg->arch.ss_trigger_page_var;
7142
7143                         g_assert (ins->opcode == OP_REGOFFSET);
7144
7145                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7146                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7147                 }
7148         }
7149
7150         cfg->code_len = code - cfg->native_code;
7151
7152         g_assert (cfg->code_len < cfg->code_size);
7153
7154         return code;
7155 }
7156
7157 void
7158 mono_arch_emit_epilog (MonoCompile *cfg)
7159 {
7160         MonoMethod *method = cfg->method;
7161         int quad, i;
7162         guint8 *code;
7163         int max_epilog_size;
7164         CallInfo *cinfo;
7165         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7166         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7167
7168         max_epilog_size = get_max_epilog_size (cfg);
7169
7170         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7171                 cfg->code_size *= 2;
7172                 cfg->native_code = mono_realloc_native_code (cfg);
7173                 cfg->stat_code_reallocs++;
7174         }
7175         code = cfg->native_code + cfg->code_len;
7176
7177         cfg->has_unwind_info_for_epilog = TRUE;
7178
7179         /* Mark the start of the epilog */
7180         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7181
7182         /* Save the uwind state which is needed by the out-of-line code */
7183         mono_emit_unwind_op_remember_state (cfg, code);
7184
7185         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7186                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7187
7188         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7189
7190         if (method->save_lmf) {
7191                 /* check if we need to restore protection of the stack after a stack overflow */
7192                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7193                         guint8 *patch;
7194                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7195                         /* we load the value in a separate instruction: this mechanism may be
7196                          * used later as a safer way to do thread interruption
7197                          */
7198                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7199                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7200                         patch = code;
7201                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7202                         /* note that the call trampoline will preserve eax/edx */
7203                         x86_call_reg (code, X86_ECX);
7204                         x86_patch (patch, code);
7205                 } else {
7206                         /* FIXME: maybe save the jit tls in the prolog */
7207                 }
7208                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7209                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7210                 }
7211         }
7212
7213         /* Restore callee saved regs */
7214         for (i = 0; i < AMD64_NREG; ++i) {
7215                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7216                         /* Restore only used_int_regs, not arch.saved_iregs */
7217                         if (cfg->used_int_regs & (1 << i)) {
7218                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7219                                 mono_emit_unwind_op_same_value (cfg, code, i);
7220                                 async_exc_point (code);
7221                         }
7222                         save_area_offset += 8;
7223                 }
7224         }
7225
7226         /* Load returned vtypes into registers if needed */
7227         cinfo = cfg->arch.cinfo;
7228         if (cinfo->ret.storage == ArgValuetypeInReg) {
7229                 ArgInfo *ainfo = &cinfo->ret;
7230                 MonoInst *inst = cfg->ret;
7231
7232                 for (quad = 0; quad < 2; quad ++) {
7233                         switch (ainfo->pair_storage [quad]) {
7234                         case ArgInIReg:
7235                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7236                                 break;
7237                         case ArgInFloatSSEReg:
7238                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7239                                 break;
7240                         case ArgInDoubleSSEReg:
7241                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7242                                 break;
7243                         case ArgNone:
7244                                 break;
7245                         default:
7246                                 g_assert_not_reached ();
7247                         }
7248                 }
7249         }
7250
7251         if (cfg->arch.omit_fp) {
7252                 if (cfg->arch.stack_alloc_size) {
7253                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7254                 }
7255         } else {
7256                 amd64_leave (code);
7257                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7258         }
7259         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7260         async_exc_point (code);
7261         amd64_ret (code);
7262
7263         /* Restore the unwind state to be the same as before the epilog */
7264         mono_emit_unwind_op_restore_state (cfg, code);
7265
7266         cfg->code_len = code - cfg->native_code;
7267
7268         g_assert (cfg->code_len < cfg->code_size);
7269 }
7270
7271 void
7272 mono_arch_emit_exceptions (MonoCompile *cfg)
7273 {
7274         MonoJumpInfo *patch_info;
7275         int nthrows, i;
7276         guint8 *code;
7277         MonoClass *exc_classes [16];
7278         guint8 *exc_throw_start [16], *exc_throw_end [16];
7279         guint32 code_size = 0;
7280
7281         /* Compute needed space */
7282         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7283                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7284                         code_size += 40;
7285                 if (patch_info->type == MONO_PATCH_INFO_R8)
7286                         code_size += 8 + 15; /* sizeof (double) + alignment */
7287                 if (patch_info->type == MONO_PATCH_INFO_R4)
7288                         code_size += 4 + 15; /* sizeof (float) + alignment */
7289                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7290                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7291         }
7292
7293 #ifdef __native_client_codegen__
7294         /* Give us extra room on Native Client.  This could be   */
7295         /* more carefully calculated, but bundle alignment makes */
7296         /* it much trickier, so *2 like other places is good.    */
7297         code_size *= 2;
7298 #endif
7299
7300         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7301                 cfg->code_size *= 2;
7302                 cfg->native_code = mono_realloc_native_code (cfg);
7303                 cfg->stat_code_reallocs++;
7304         }
7305
7306         code = cfg->native_code + cfg->code_len;
7307
7308         /* add code to raise exceptions */
7309         nthrows = 0;
7310         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7311                 switch (patch_info->type) {
7312                 case MONO_PATCH_INFO_EXC: {
7313                         MonoClass *exc_class;
7314                         guint8 *buf, *buf2;
7315                         guint32 throw_ip;
7316
7317                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7318
7319                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7320                         g_assert (exc_class);
7321                         throw_ip = patch_info->ip.i;
7322
7323                         //x86_breakpoint (code);
7324                         /* Find a throw sequence for the same exception class */
7325                         for (i = 0; i < nthrows; ++i)
7326                                 if (exc_classes [i] == exc_class)
7327                                         break;
7328                         if (i < nthrows) {
7329                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7330                                 x86_jump_code (code, exc_throw_start [i]);
7331                                 patch_info->type = MONO_PATCH_INFO_NONE;
7332                         }
7333                         else {
7334                                 buf = code;
7335                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7336                                 buf2 = code;
7337
7338                                 if (nthrows < 16) {
7339                                         exc_classes [nthrows] = exc_class;
7340                                         exc_throw_start [nthrows] = code;
7341                                 }
7342                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7343
7344                                 patch_info->type = MONO_PATCH_INFO_NONE;
7345
7346                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7347
7348                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7349                                 while (buf < buf2)
7350                                         x86_nop (buf);
7351
7352                                 if (nthrows < 16) {
7353                                         exc_throw_end [nthrows] = code;
7354                                         nthrows ++;
7355                                 }
7356                         }
7357                         break;
7358                 }
7359                 default:
7360                         /* do nothing */
7361                         break;
7362                 }
7363                 g_assert(code < cfg->native_code + cfg->code_size);
7364         }
7365
7366         /* Handle relocations with RIP relative addressing */
7367         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7368                 gboolean remove = FALSE;
7369                 guint8 *orig_code = code;
7370
7371                 switch (patch_info->type) {
7372                 case MONO_PATCH_INFO_R8:
7373                 case MONO_PATCH_INFO_R4: {
7374                         guint8 *pos, *patch_pos;
7375                         guint32 target_pos;
7376
7377                         /* The SSE opcodes require a 16 byte alignment */
7378 #if defined(__default_codegen__)
7379                         code = (guint8*)ALIGN_TO (code, 16);
7380 #elif defined(__native_client_codegen__)
7381                         {
7382                                 /* Pad this out with HLT instructions  */
7383                                 /* or we can get garbage bytes emitted */
7384                                 /* which will fail validation          */
7385                                 guint8 *aligned_code;
7386                                 /* extra align to make room for  */
7387                                 /* mov/push below                      */
7388                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7389                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7390                                 /* The technique of hiding data in an  */
7391                                 /* instruction has a problem here: we  */
7392                                 /* need the data aligned to a 16-byte  */
7393                                 /* boundary but the instruction cannot */
7394                                 /* cross the bundle boundary. so only  */
7395                                 /* odd multiples of 16 can be used     */
7396                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7397                                         aligned_code += 16;
7398                                 }
7399                                 while (code < aligned_code) {
7400                                         *(code++) = 0xf4; /* hlt */
7401                                 }
7402                         }
7403 #endif
7404
7405                         pos = cfg->native_code + patch_info->ip.i;
7406                         if (IS_REX (pos [1])) {
7407                                 patch_pos = pos + 5;
7408                                 target_pos = code - pos - 9;
7409                         }
7410                         else {
7411                                 patch_pos = pos + 4;
7412                                 target_pos = code - pos - 8;
7413                         }
7414
7415                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7416 #ifdef __native_client_codegen__
7417                                 /* Hide 64-bit data in a         */
7418                                 /* "mov imm64, r11" instruction. */
7419                                 /* write it before the start of  */
7420                                 /* the data*/
7421                                 *(code-2) = 0x49; /* prefix      */
7422                                 *(code-1) = 0xbb; /* mov X, %r11 */
7423 #endif
7424                                 *(double*)code = *(double*)patch_info->data.target;
7425                                 code += sizeof (double);
7426                         } else {
7427 #ifdef __native_client_codegen__
7428                                 /* Hide 32-bit data in a        */
7429                                 /* "push imm32" instruction.    */
7430                                 *(code-1) = 0x68; /* push */
7431 #endif
7432                                 *(float*)code = *(float*)patch_info->data.target;
7433                                 code += sizeof (float);
7434                         }
7435
7436                         *(guint32*)(patch_pos) = target_pos;
7437
7438                         remove = TRUE;
7439                         break;
7440                 }
7441                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7442                         guint8 *pos;
7443
7444                         if (cfg->compile_aot)
7445                                 continue;
7446
7447                         /*loading is faster against aligned addresses.*/
7448                         code = (guint8*)ALIGN_TO (code, 8);
7449                         memset (orig_code, 0, code - orig_code);
7450
7451                         pos = cfg->native_code + patch_info->ip.i;
7452
7453                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7454                         if (IS_REX (pos [1]))
7455                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7456                         else
7457                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7458
7459                         *(gpointer*)code = (gpointer)patch_info->data.target;
7460                         code += sizeof (gpointer);
7461
7462                         remove = TRUE;
7463                         break;
7464                 }
7465                 default:
7466                         break;
7467                 }
7468
7469                 if (remove) {
7470                         if (patch_info == cfg->patch_info)
7471                                 cfg->patch_info = patch_info->next;
7472                         else {
7473                                 MonoJumpInfo *tmp;
7474
7475                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7476                                         ;
7477                                 tmp->next = patch_info->next;
7478                         }
7479                 }
7480                 g_assert (code < cfg->native_code + cfg->code_size);
7481         }
7482
7483         cfg->code_len = code - cfg->native_code;
7484
7485         g_assert (cfg->code_len < cfg->code_size);
7486
7487 }
7488
7489 #endif /* DISABLE_JIT */
7490
7491 void*
7492 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7493 {
7494         guchar *code = p;
7495         MonoMethodSignature *sig;
7496         MonoInst *inst;
7497         int i, n, stack_area = 0;
7498
7499         /* Keep this in sync with mono_arch_get_argument_info */
7500
7501         if (enable_arguments) {
7502                 /* Allocate a new area on the stack and save arguments there */
7503                 sig = mono_method_signature (cfg->method);
7504
7505                 n = sig->param_count + sig->hasthis;
7506
7507                 stack_area = ALIGN_TO (n * 8, 16);
7508
7509                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7510
7511                 for (i = 0; i < n; ++i) {
7512                         inst = cfg->args [i];
7513
7514                         if (inst->opcode == OP_REGVAR)
7515                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7516                         else {
7517                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7518                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7519                         }
7520                 }
7521         }
7522
7523         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7524         amd64_set_reg_template (code, AMD64_ARG_REG1);
7525         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7526         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7527
7528         if (enable_arguments)
7529                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7530
7531         return code;
7532 }
7533
7534 enum {
7535         SAVE_NONE,
7536         SAVE_STRUCT,
7537         SAVE_EAX,
7538         SAVE_EAX_EDX,
7539         SAVE_XMM
7540 };
7541
7542 void*
7543 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7544 {
7545         guchar *code = p;
7546         int save_mode = SAVE_NONE;
7547         MonoMethod *method = cfg->method;
7548         MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7549         int i;
7550
7551         switch (ret_type->type) {
7552         case MONO_TYPE_VOID:
7553                 /* special case string .ctor icall */
7554                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7555                         save_mode = SAVE_EAX;
7556                 else
7557                         save_mode = SAVE_NONE;
7558                 break;
7559         case MONO_TYPE_I8:
7560         case MONO_TYPE_U8:
7561                 save_mode = SAVE_EAX;
7562                 break;
7563         case MONO_TYPE_R4:
7564         case MONO_TYPE_R8:
7565                 save_mode = SAVE_XMM;
7566                 break;
7567         case MONO_TYPE_GENERICINST:
7568                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7569                         save_mode = SAVE_EAX;
7570                         break;
7571                 }
7572                 /* Fall through */
7573         case MONO_TYPE_VALUETYPE:
7574                 save_mode = SAVE_STRUCT;
7575                 break;
7576         default:
7577                 save_mode = SAVE_EAX;
7578                 break;
7579         }
7580
7581         /* Save the result and copy it into the proper argument register */
7582         switch (save_mode) {
7583         case SAVE_EAX:
7584                 amd64_push_reg (code, AMD64_RAX);
7585                 /* Align stack */
7586                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7587                 if (enable_arguments)
7588                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7589                 break;
7590         case SAVE_STRUCT:
7591                 /* FIXME: */
7592                 if (enable_arguments)
7593                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7594                 break;
7595         case SAVE_XMM:
7596                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7597                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7598                 /* Align stack */
7599                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7600                 /*
7601                  * The result is already in the proper argument register so no copying
7602                  * needed.
7603                  */
7604                 break;
7605         case SAVE_NONE:
7606                 break;
7607         default:
7608                 g_assert_not_reached ();
7609         }
7610
7611         /* Set %al since this is a varargs call */
7612         if (save_mode == SAVE_XMM)
7613                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7614         else
7615                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7616
7617         if (preserve_argument_registers) {
7618                 for (i = 0; i < PARAM_REGS; ++i)
7619                         amd64_push_reg (code, param_regs [i]);
7620         }
7621
7622         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7623         amd64_set_reg_template (code, AMD64_ARG_REG1);
7624         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7625
7626         if (preserve_argument_registers) {
7627                 for (i = PARAM_REGS - 1; i >= 0; --i)
7628                         amd64_pop_reg (code, param_regs [i]);
7629         }
7630
7631         /* Restore result */
7632         switch (save_mode) {
7633         case SAVE_EAX:
7634                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7635                 amd64_pop_reg (code, AMD64_RAX);
7636                 break;
7637         case SAVE_STRUCT:
7638                 /* FIXME: */
7639                 break;
7640         case SAVE_XMM:
7641                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7642                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7643                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7644                 break;
7645         case SAVE_NONE:
7646                 break;
7647         default:
7648                 g_assert_not_reached ();
7649         }
7650
7651         return code;
7652 }
7653
7654 void
7655 mono_arch_flush_icache (guint8 *code, gint size)
7656 {
7657         /* Not needed */
7658 }
7659
7660 void
7661 mono_arch_flush_register_windows (void)
7662 {
7663 }
7664
7665 gboolean
7666 mono_arch_is_inst_imm (gint64 imm)
7667 {
7668         return amd64_is_imm32 (imm);
7669 }
7670
7671 /*
7672  * Determine whenever the trap whose info is in SIGINFO is caused by
7673  * integer overflow.
7674  */
7675 gboolean
7676 mono_arch_is_int_overflow (void *sigctx, void *info)
7677 {
7678         MonoContext ctx;
7679         guint8* rip;
7680         int reg;
7681         gint64 value;
7682
7683         mono_sigctx_to_monoctx (sigctx, &ctx);
7684
7685         rip = (guint8*)ctx.rip;
7686
7687         if (IS_REX (rip [0])) {
7688                 reg = amd64_rex_b (rip [0]);
7689                 rip ++;
7690         }
7691         else
7692                 reg = 0;
7693
7694         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7695                 /* idiv REG */
7696                 reg += x86_modrm_rm (rip [1]);
7697
7698                 switch (reg) {
7699                 case AMD64_RAX:
7700                         value = ctx.rax;
7701                         break;
7702                 case AMD64_RBX:
7703                         value = ctx.rbx;
7704                         break;
7705                 case AMD64_RCX:
7706                         value = ctx.rcx;
7707                         break;
7708                 case AMD64_RDX:
7709                         value = ctx.rdx;
7710                         break;
7711                 case AMD64_RBP:
7712                         value = ctx.rbp;
7713                         break;
7714                 case AMD64_RSP:
7715                         value = ctx.rsp;
7716                         break;
7717                 case AMD64_RSI:
7718                         value = ctx.rsi;
7719                         break;
7720                 case AMD64_RDI:
7721                         value = ctx.rdi;
7722                         break;
7723                 case AMD64_R12:
7724                         value = ctx.r12;
7725                         break;
7726                 case AMD64_R13:
7727                         value = ctx.r13;
7728                         break;
7729                 case AMD64_R14:
7730                         value = ctx.r14;
7731                         break;
7732                 case AMD64_R15:
7733                         value = ctx.r15;
7734                         break;
7735                 default:
7736                         g_assert_not_reached ();
7737                         reg = -1;
7738                 }
7739
7740                 if (value == -1)
7741                         return TRUE;
7742         }
7743
7744         return FALSE;
7745 }
7746
7747 guint32
7748 mono_arch_get_patch_offset (guint8 *code)
7749 {
7750         return 3;
7751 }
7752
7753 /**
7754  * mono_breakpoint_clean_code:
7755  *
7756  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7757  * breakpoints in the original code, they are removed in the copy.
7758  *
7759  * Returns TRUE if no sw breakpoint was present.
7760  */
7761 gboolean
7762 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7763 {
7764         /*
7765          * If method_start is non-NULL we need to perform bound checks, since we access memory
7766          * at code - offset we could go before the start of the method and end up in a different
7767          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7768          * instead.
7769          */
7770         if (!method_start || code - offset >= method_start) {
7771                 memcpy (buf, code - offset, size);
7772         } else {
7773                 int diff = code - method_start;
7774                 memset (buf, 0, size);
7775                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7776         }
7777         return TRUE;
7778 }
7779
7780 #if defined(__native_client_codegen__)
7781 /* For membase calls, we want the base register. for Native Client,  */
7782 /* all indirect calls have the following sequence with the given sizes: */
7783 /* mov %eXX,%eXX                                [2-3]   */
7784 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7785 /* and $0xffffffffffffffe0,%r11d                [4]     */
7786 /* add %r15,%r11                                [3]     */
7787 /* callq *%r11                                  [3]     */
7788
7789
7790 /* Determine if code points to a NaCl call-through-register sequence, */
7791 /* (i.e., the last 3 instructions listed above) */
7792 int
7793 is_nacl_call_reg_sequence(guint8* code)
7794 {
7795         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7796                                "\x4d\x03\xdf"     /* add */
7797                                "\x41\xff\xd3";   /* call */
7798         return memcmp(code, sequence, 10) == 0;
7799 }
7800
7801 /* Determine if code points to the first opcode of the mov membase component */
7802 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7803 /* (there could be a REX prefix before the opcode but it is ignored) */
7804 static int
7805 is_nacl_indirect_call_membase_sequence(guint8* code)
7806 {
7807                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7808         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7809                /* and that src reg = dest reg */
7810                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7811                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7812                IS_REX(code[2]) &&
7813                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7814                /* and has dst of r11 and base of r15 */
7815                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7816                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7817 }
7818 #endif /* __native_client_codegen__ */
7819
7820 int
7821 mono_arch_get_this_arg_reg (guint8 *code)
7822 {
7823         return AMD64_ARG_REG1;
7824 }
7825
7826 gpointer
7827 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7828 {
7829         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7830 }
7831
7832 #define MAX_ARCH_DELEGATE_PARAMS 10
7833
7834 static gpointer
7835 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7836 {
7837         guint8 *code, *start;
7838         int i;
7839
7840         if (has_target) {
7841                 start = code = mono_global_codeman_reserve (64);
7842
7843                 /* Replace the this argument with the target */
7844                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7845                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7846                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7847
7848                 g_assert ((code - start) < 64);
7849         } else {
7850                 start = code = mono_global_codeman_reserve (64);
7851
7852                 if (param_count == 0) {
7853                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7854                 } else {
7855                         /* We have to shift the arguments left */
7856                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7857                         for (i = 0; i < param_count; ++i) {
7858 #ifdef TARGET_WIN32
7859                                 if (i < 3)
7860                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7861                                 else
7862                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7863 #else
7864                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7865 #endif
7866                         }
7867
7868                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7869                 }
7870                 g_assert ((code - start) < 64);
7871         }
7872
7873         nacl_global_codeman_validate (&start, 64, &code);
7874         mono_arch_flush_icache (start, code - start);
7875
7876         if (code_len)
7877                 *code_len = code - start;
7878
7879         if (mono_jit_map_is_enabled ()) {
7880                 char *buff;
7881                 if (has_target)
7882                         buff = (char*)"delegate_invoke_has_target";
7883                 else
7884                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7885                 mono_emit_jit_tramp (start, code - start, buff);
7886                 if (!has_target)
7887                         g_free (buff);
7888         }
7889         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7890
7891         return start;
7892 }
7893
7894 /*
7895  * mono_arch_get_delegate_invoke_impls:
7896  *
7897  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7898  * trampolines.
7899  */
7900 GSList*
7901 mono_arch_get_delegate_invoke_impls (void)
7902 {
7903         GSList *res = NULL;
7904         guint8 *code;
7905         guint32 code_len;
7906         int i;
7907         char *tramp_name;
7908
7909         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7910         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7911
7912         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7913                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7914                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7915                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7916                 g_free (tramp_name);
7917         }
7918
7919         return res;
7920 }
7921
7922 gpointer
7923 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7924 {
7925         guint8 *code, *start;
7926         int i;
7927
7928         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7929                 return NULL;
7930
7931         /* FIXME: Support more cases */
7932         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7933                 return NULL;
7934
7935         if (has_target) {
7936                 static guint8* cached = NULL;
7937
7938                 if (cached)
7939                         return cached;
7940
7941                 if (mono_aot_only)
7942                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7943                 else
7944                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7945
7946                 mono_memory_barrier ();
7947
7948                 cached = start;
7949         } else {
7950                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7951                 for (i = 0; i < sig->param_count; ++i)
7952                         if (!mono_is_regsize_var (sig->params [i]))
7953                                 return NULL;
7954                 if (sig->param_count > 4)
7955                         return NULL;
7956
7957                 code = cache [sig->param_count];
7958                 if (code)
7959                         return code;
7960
7961                 if (mono_aot_only) {
7962                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7963                         start = mono_aot_get_trampoline (name);
7964                         g_free (name);
7965                 } else {
7966                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7967                 }
7968
7969                 mono_memory_barrier ();
7970
7971                 cache [sig->param_count] = start;
7972         }
7973
7974         return start;
7975 }
7976
7977 gpointer
7978 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7979 {
7980         guint8 *code, *start;
7981         int size = 20;
7982
7983         start = code = mono_global_codeman_reserve (size);
7984
7985         /* Replace the this argument with the target */
7986         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7987         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7988
7989         if (load_imt_reg) {
7990                 /* Load the IMT reg */
7991                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7992         }
7993
7994         /* Load the vtable */
7995         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7996         amd64_jump_membase (code, AMD64_RAX, offset);
7997         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7998
7999         return start;
8000 }
8001
8002 void
8003 mono_arch_finish_init (void)
8004 {
8005 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8006         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8007 #endif
8008 }
8009
8010 void
8011 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8012 {
8013 }
8014
8015 #if defined(__default_codegen__)
8016 #define CMP_SIZE (6 + 1)
8017 #define CMP_REG_REG_SIZE (4 + 1)
8018 #define BR_SMALL_SIZE 2
8019 #define BR_LARGE_SIZE 6
8020 #define MOV_REG_IMM_SIZE 10
8021 #define MOV_REG_IMM_32BIT_SIZE 6
8022 #define JUMP_REG_SIZE (2 + 1)
8023 #elif defined(__native_client_codegen__)
8024 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8025 #define CMP_SIZE ((6 + 1) * 2 - 1)
8026 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8027 #define BR_SMALL_SIZE (2 * 2 - 1)
8028 #define BR_LARGE_SIZE (6 * 2 - 1)
8029 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8030 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8031 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8032 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8033 /* Jump membase's size is large and unpredictable    */
8034 /* in native client, just pad it out a whole bundle. */
8035 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8036 #endif
8037
8038 static int
8039 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8040 {
8041         int i, distance = 0;
8042         for (i = start; i < target; ++i)
8043                 distance += imt_entries [i]->chunk_size;
8044         return distance;
8045 }
8046
8047 /*
8048  * LOCKING: called with the domain lock held
8049  */
8050 gpointer
8051 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8052         gpointer fail_tramp)
8053 {
8054         int i;
8055         int size = 0;
8056         guint8 *code, *start;
8057         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8058
8059         for (i = 0; i < count; ++i) {
8060                 MonoIMTCheckItem *item = imt_entries [i];
8061                 if (item->is_equals) {
8062                         if (item->check_target_idx) {
8063                                 if (!item->compare_done) {
8064                                         if (amd64_is_imm32 (item->key))
8065                                                 item->chunk_size += CMP_SIZE;
8066                                         else
8067                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8068                                 }
8069                                 if (item->has_target_code) {
8070                                         item->chunk_size += MOV_REG_IMM_SIZE;
8071                                 } else {
8072                                         if (vtable_is_32bit)
8073                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8074                                         else
8075                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8076 #ifdef __native_client_codegen__
8077                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8078 #endif
8079                                 }
8080                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8081                         } else {
8082                                 if (fail_tramp) {
8083                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8084                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8085                                 } else {
8086                                         if (vtable_is_32bit)
8087                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8088                                         else
8089                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8090                                         item->chunk_size += JUMP_REG_SIZE;
8091                                         /* with assert below:
8092                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8093                                          */
8094 #ifdef __native_client_codegen__
8095                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8096 #endif
8097                                 }
8098                         }
8099                 } else {
8100                         if (amd64_is_imm32 (item->key))
8101                                 item->chunk_size += CMP_SIZE;
8102                         else
8103                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8104                         item->chunk_size += BR_LARGE_SIZE;
8105                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8106                 }
8107                 size += item->chunk_size;
8108         }
8109 #if defined(__native_client__) && defined(__native_client_codegen__)
8110         /* In Native Client, we don't re-use thunks, allocate from the */
8111         /* normal code manager paths. */
8112         code = mono_domain_code_reserve (domain, size);
8113 #else
8114         if (fail_tramp)
8115                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8116         else
8117                 code = mono_domain_code_reserve (domain, size);
8118 #endif
8119         start = code;
8120         for (i = 0; i < count; ++i) {
8121                 MonoIMTCheckItem *item = imt_entries [i];
8122                 item->code_target = code;
8123                 if (item->is_equals) {
8124                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8125
8126                         if (item->check_target_idx || fail_case) {
8127                                 if (!item->compare_done || fail_case) {
8128                                         if (amd64_is_imm32 (item->key))
8129                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8130                                         else {
8131                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8132                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8133                                         }
8134                                 }
8135                                 item->jmp_code = code;
8136                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8137                                 if (item->has_target_code) {
8138                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8139                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8140                                 } else {
8141                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8142                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8143                                 }
8144
8145                                 if (fail_case) {
8146                                         amd64_patch (item->jmp_code, code);
8147                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8148                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8149                                         item->jmp_code = NULL;
8150                                 }
8151                         } else {
8152                                 /* enable the commented code to assert on wrong method */
8153 #if 0
8154                                 if (amd64_is_imm32 (item->key))
8155                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8156                                 else {
8157                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8158                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8159                                 }
8160                                 item->jmp_code = code;
8161                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8162                                 /* See the comment below about R10 */
8163                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8164                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8165                                 amd64_patch (item->jmp_code, code);
8166                                 amd64_breakpoint (code);
8167                                 item->jmp_code = NULL;
8168 #else
8169                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8170                                    needs to be preserved.  R10 needs
8171                                    to be preserved for calls which
8172                                    require a runtime generic context,
8173                                    but interface calls don't. */
8174                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8175                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8176 #endif
8177                         }
8178                 } else {
8179                         if (amd64_is_imm32 (item->key))
8180                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8181                         else {
8182                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8183                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8184                         }
8185                         item->jmp_code = code;
8186                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8187                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8188                         else
8189                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8190                 }
8191                 g_assert (code - item->code_target <= item->chunk_size);
8192         }
8193         /* patch the branches to get to the target items */
8194         for (i = 0; i < count; ++i) {
8195                 MonoIMTCheckItem *item = imt_entries [i];
8196                 if (item->jmp_code) {
8197                         if (item->check_target_idx) {
8198                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8199                         }
8200                 }
8201         }
8202
8203         if (!fail_tramp)
8204                 mono_stats.imt_thunks_size += code - start;
8205         g_assert (code - start <= size);
8206
8207         nacl_domain_code_validate(domain, &start, size, &code);
8208         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8209
8210         return start;
8211 }
8212
8213 MonoMethod*
8214 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8215 {
8216         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8217 }
8218
8219 MonoVTable*
8220 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8221 {
8222         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8223 }
8224
8225 GSList*
8226 mono_arch_get_cie_program (void)
8227 {
8228         GSList *l = NULL;
8229
8230         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8231         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8232
8233         return l;
8234 }
8235
8236 #ifndef DISABLE_JIT
8237
8238 MonoInst*
8239 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8240 {
8241         MonoInst *ins = NULL;
8242         int opcode = 0;
8243
8244         if (cmethod->klass == mono_defaults.math_class) {
8245                 if (strcmp (cmethod->name, "Sin") == 0) {
8246                         opcode = OP_SIN;
8247                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8248                         opcode = OP_COS;
8249                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8250                         opcode = OP_SQRT;
8251                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8252                         opcode = OP_ABS;
8253                 }
8254
8255                 if (opcode && fsig->param_count == 1) {
8256                         MONO_INST_NEW (cfg, ins, opcode);
8257                         ins->type = STACK_R8;
8258                         ins->dreg = mono_alloc_freg (cfg);
8259                         ins->sreg1 = args [0]->dreg;
8260                         MONO_ADD_INS (cfg->cbb, ins);
8261                 }
8262
8263                 opcode = 0;
8264                 if (cfg->opt & MONO_OPT_CMOV) {
8265                         if (strcmp (cmethod->name, "Min") == 0) {
8266                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8267                                         opcode = OP_IMIN;
8268                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8269                                         opcode = OP_IMIN_UN;
8270                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8271                                         opcode = OP_LMIN;
8272                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8273                                         opcode = OP_LMIN_UN;
8274                         } else if (strcmp (cmethod->name, "Max") == 0) {
8275                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8276                                         opcode = OP_IMAX;
8277                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8278                                         opcode = OP_IMAX_UN;
8279                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8280                                         opcode = OP_LMAX;
8281                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8282                                         opcode = OP_LMAX_UN;
8283                         }
8284                 }
8285
8286                 if (opcode && fsig->param_count == 2) {
8287                         MONO_INST_NEW (cfg, ins, opcode);
8288                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8289                         ins->dreg = mono_alloc_ireg (cfg);
8290                         ins->sreg1 = args [0]->dreg;
8291                         ins->sreg2 = args [1]->dreg;
8292                         MONO_ADD_INS (cfg->cbb, ins);
8293                 }
8294
8295 #if 0
8296                 /* OP_FREM is not IEEE compatible */
8297                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8298                         MONO_INST_NEW (cfg, ins, OP_FREM);
8299                         ins->inst_i0 = args [0];
8300                         ins->inst_i1 = args [1];
8301                 }
8302 #endif
8303         }
8304
8305         return ins;
8306 }
8307 #endif
8308
8309 gboolean
8310 mono_arch_print_tree (MonoInst *tree, int arity)
8311 {
8312         return 0;
8313 }
8314
8315 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8316
8317 mgreg_t
8318 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8319 {
8320         switch (reg) {
8321         case AMD64_RCX: return ctx->rcx;
8322         case AMD64_RDX: return ctx->rdx;
8323         case AMD64_RBX: return ctx->rbx;
8324         case AMD64_RBP: return ctx->rbp;
8325         case AMD64_RSP: return ctx->rsp;
8326         default:
8327                 return _CTX_REG (ctx, rax, reg);
8328         }
8329 }
8330
8331 void
8332 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8333 {
8334         switch (reg) {
8335         case AMD64_RCX:
8336                 ctx->rcx = val;
8337                 break;
8338         case AMD64_RDX:
8339                 ctx->rdx = val;
8340                 break;
8341         case AMD64_RBX:
8342                 ctx->rbx = val;
8343                 break;
8344         case AMD64_RBP:
8345                 ctx->rbp = val;
8346                 break;
8347         case AMD64_RSP:
8348                 ctx->rsp = val;
8349                 break;
8350         default:
8351                 _CTX_REG (ctx, rax, reg) = val;
8352         }
8353 }
8354
8355 gpointer
8356 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8357 {
8358         gpointer *sp, old_value;
8359         char *bp;
8360
8361         /*Load the spvar*/
8362         bp = MONO_CONTEXT_GET_BP (ctx);
8363         sp = *(gpointer*)(bp + clause->exvar_offset);
8364
8365         old_value = *sp;
8366         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8367                 return old_value;
8368
8369         *sp = new_value;
8370
8371         return old_value;
8372 }
8373
8374 /*
8375  * mono_arch_emit_load_aotconst:
8376  *
8377  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8378  * TARGET from the mscorlib GOT in full-aot code.
8379  * On AMD64, the result is placed into R11.
8380  */
8381 guint8*
8382 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8383 {
8384         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8385         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8386
8387         return code;
8388 }
8389
8390 /*
8391  * mono_arch_get_trampolines:
8392  *
8393  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8394  * for AOT.
8395  */
8396 GSList *
8397 mono_arch_get_trampolines (gboolean aot)
8398 {
8399         return mono_amd64_get_exception_trampolines (aot);
8400 }
8401
8402 /* Soft Debug support */
8403 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8404
8405 /*
8406  * mono_arch_set_breakpoint:
8407  *
8408  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8409  * The location should contain code emitted by OP_SEQ_POINT.
8410  */
8411 void
8412 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8413 {
8414         guint8 *code = ip;
8415         guint8 *orig_code = code;
8416
8417         if (ji->from_aot) {
8418                 guint32 native_offset = ip - (guint8*)ji->code_start;
8419                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8420
8421                 g_assert (info->bp_addrs [native_offset] == 0);
8422                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8423         } else {
8424                 /*
8425                  * In production, we will use int3 (has to fix the size in the md
8426                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8427                  * instead.
8428                  */
8429                 g_assert (code [0] == 0x90);
8430                 if (breakpoint_size == 8) {
8431                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8432                 } else {
8433                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8434                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8435                 }
8436
8437                 g_assert (code - orig_code == breakpoint_size);
8438         }
8439 }
8440
8441 /*
8442  * mono_arch_clear_breakpoint:
8443  *
8444  *   Clear the breakpoint at IP.
8445  */
8446 void
8447 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8448 {
8449         guint8 *code = ip;
8450         int i;
8451
8452         if (ji->from_aot) {
8453                 guint32 native_offset = ip - (guint8*)ji->code_start;
8454                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8455
8456                 info->bp_addrs [native_offset] = NULL;
8457         } else {
8458                 for (i = 0; i < breakpoint_size; ++i)
8459                         x86_nop (code);
8460         }
8461 }
8462
8463 gboolean
8464 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8465 {
8466 #ifdef HOST_WIN32
8467         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8468         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8469                 return TRUE;
8470         else
8471                 return FALSE;
8472 #else
8473         siginfo_t* sinfo = (siginfo_t*) info;
8474         /* Sometimes the address is off by 4 */
8475         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8476                 return TRUE;
8477         else
8478                 return FALSE;
8479 #endif
8480 }
8481
8482 /*
8483  * mono_arch_skip_breakpoint:
8484  *
8485  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8486  * we resume, the instruction is not executed again.
8487  */
8488 void
8489 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8490 {
8491         if (ji->from_aot) {
8492                 /* The breakpoint instruction is a call */
8493         } else {
8494                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8495         }
8496 }
8497
8498 /*
8499  * mono_arch_start_single_stepping:
8500  *
8501  *   Start single stepping.
8502  */
8503 void
8504 mono_arch_start_single_stepping (void)
8505 {
8506         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8507         ss_trampoline = mini_get_single_step_trampoline ();
8508 }
8509
8510 /*
8511  * mono_arch_stop_single_stepping:
8512  *
8513  *   Stop single stepping.
8514  */
8515 void
8516 mono_arch_stop_single_stepping (void)
8517 {
8518         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8519         ss_trampoline = NULL;
8520 }
8521
8522 /*
8523  * mono_arch_is_single_step_event:
8524  *
8525  *   Return whenever the machine state in SIGCTX corresponds to a single
8526  * step event.
8527  */
8528 gboolean
8529 mono_arch_is_single_step_event (void *info, void *sigctx)
8530 {
8531 #ifdef HOST_WIN32
8532         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8533         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8534                 return TRUE;
8535         else
8536                 return FALSE;
8537 #else
8538         siginfo_t* sinfo = (siginfo_t*) info;
8539         /* Sometimes the address is off by 4 */
8540         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8541                 return TRUE;
8542         else
8543                 return FALSE;
8544 #endif
8545 }
8546
8547 /*
8548  * mono_arch_skip_single_step:
8549  *
8550  *   Modify CTX so the ip is placed after the single step trigger instruction,
8551  * we resume, the instruction is not executed again.
8552  */
8553 void
8554 mono_arch_skip_single_step (MonoContext *ctx)
8555 {
8556         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8557 }
8558
8559 /*
8560  * mono_arch_create_seq_point_info:
8561  *
8562  *   Return a pointer to a data structure which is used by the sequence
8563  * point implementation in AOTed code.
8564  */
8565 gpointer
8566 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8567 {
8568         SeqPointInfo *info;
8569         MonoJitInfo *ji;
8570
8571         // FIXME: Add a free function
8572
8573         mono_domain_lock (domain);
8574         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8575                                                                 code);
8576         mono_domain_unlock (domain);
8577
8578         if (!info) {
8579                 ji = mono_jit_info_table_find (domain, (char*)code);
8580                 g_assert (ji);
8581
8582                 // FIXME: Optimize the size
8583                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8584
8585                 info->ss_tramp_addr = &ss_trampoline;
8586
8587                 mono_domain_lock (domain);
8588                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8589                                                          code, info);
8590                 mono_domain_unlock (domain);
8591         }
8592
8593         return info;
8594 }
8595
8596 void
8597 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8598 {
8599         ext->lmf.previous_lmf = prev_lmf;
8600         /* Mark that this is a MonoLMFExt */
8601         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8602         ext->lmf.rsp = (gssize)ext;
8603 }
8604
8605 #endif
8606
8607 gboolean
8608 mono_arch_opcode_supported (int opcode)
8609 {
8610         switch (opcode) {
8611         case OP_ATOMIC_ADD_I4:
8612         case OP_ATOMIC_ADD_I8:
8613         case OP_ATOMIC_EXCHANGE_I4:
8614         case OP_ATOMIC_EXCHANGE_I8:
8615         case OP_ATOMIC_CAS_I4:
8616         case OP_ATOMIC_CAS_I8:
8617         case OP_ATOMIC_LOAD_I1:
8618         case OP_ATOMIC_LOAD_I2:
8619         case OP_ATOMIC_LOAD_I4:
8620         case OP_ATOMIC_LOAD_I8:
8621         case OP_ATOMIC_LOAD_U1:
8622         case OP_ATOMIC_LOAD_U2:
8623         case OP_ATOMIC_LOAD_U4:
8624         case OP_ATOMIC_LOAD_U8:
8625         case OP_ATOMIC_LOAD_R4:
8626         case OP_ATOMIC_LOAD_R8:
8627         case OP_ATOMIC_STORE_I1:
8628         case OP_ATOMIC_STORE_I2:
8629         case OP_ATOMIC_STORE_I4:
8630         case OP_ATOMIC_STORE_I8:
8631         case OP_ATOMIC_STORE_U1:
8632         case OP_ATOMIC_STORE_U2:
8633         case OP_ATOMIC_STORE_U4:
8634         case OP_ATOMIC_STORE_U8:
8635         case OP_ATOMIC_STORE_R4:
8636         case OP_ATOMIC_STORE_R8:
8637                 return TRUE;
8638         default:
8639                 return FALSE;
8640         }
8641 }