mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 /* Offset between fp and the first argument in the callee */
  89 #define ARGS_OFFSET 16
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return mono_debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 #ifdef __native_client_codegen__
 182
 183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 184 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 186 /* We only want to force bundle alignment for the top level instruction,    */
 187 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 188 static MonoNativeTlsKey nacl_instruction_depth;
 189
 190 static MonoNativeTlsKey nacl_rex_tag;
 191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 192
 193 void
 194 amd64_nacl_clear_legacy_prefix_tag ()
 195 {
 196         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 197 }
 198
 199 void
 200 amd64_nacl_tag_legacy_prefix (guint8* code)
 201 {
 202         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 203                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 204 }
 205
 206 void
 207 amd64_nacl_tag_rex (guint8* code)
 208 {
 209         mono_native_tls_set_value (nacl_rex_tag, code);
 210 }
 211
 212 guint8*
 213 amd64_nacl_get_legacy_prefix_tag ()
 214 {
 215         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 216 }
 217
 218 guint8*
 219 amd64_nacl_get_rex_tag ()
 220 {
 221         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 222 }
 223
 224 /* Increment the instruction "depth" described above */
 225 void
 226 amd64_nacl_instruction_pre ()
 227 {
 228         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 229         depth++;
 230         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 231 }
 232
 233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 234 /* alignment if depth == 0 (top level instruction)                          */
 235 /* IN: start, end    pointers to instruction beginning and end              */
 236 /* OUT: start, end   pointers to beginning and end after possible alignment */
 237 /* GLOBALS: nacl_instruction_depth     defined above                        */
 238 void
 239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth--;
 243         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 244
 245         g_assert ( depth >= 0 );
 246         if (depth == 0) {
 247                 uintptr_t space_in_block;
 248                 uintptr_t instlen;
 249                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 250                 /* if legacy prefix is present, and if it was emitted before */
 251                 /* the start of the instruction sequence, adjust the start   */
 252                 if (prefix != NULL && prefix < *start) {
 253                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 254                         *start = prefix;
 255                 }
 256                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 257                 instlen = (uintptr_t)(*end - *start);
 258                 /* Only check for instructions which are less than        */
 259                 /* kNaClAlignment. The only instructions that should ever */
 260                 /* be that long are call sequences, which are already     */
 261                 /* padded out to align the return to the next bundle.     */
 262                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 263                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 264                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 265                         const size_t length = (size_t)((*end)-(*start));
 266                         g_assert (length < MAX_NACL_INST_LENGTH);
 267
 268                         memcpy (copy_of_instruction, *start, length);
 269                         *start = mono_arch_nacl_pad (*start, space_in_block);
 270                         memcpy (*start, copy_of_instruction, length);
 271                         *end = *start + length;
 272                 }
 273                 amd64_nacl_clear_legacy_prefix_tag ();
 274                 amd64_nacl_tag_rex (NULL);
 275         }
 276 }
 277
 278 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 279 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 280 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 281 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 282 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 283 /* IN:      code                                                            */
 284 /*             pointer to current instruction stream (in the                */
 285 /*             middle of an instruction, after opcode is emitted)           */
 286 /*          basereg/offset/dreg                                             */
 287 /*             operands of normal membase address                           */
 288 /* OUT:     code                                                            */
 289 /*             pointer to the end of the membase/memindex emit              */
 290 /* GLOBALS: nacl_rex_tag                                                    */
 291 /*             position in instruction stream that rex prefix was emitted   */
 292 /*          nacl_legacy_prefix_tag                                          */
 293 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 294 void
 295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 296 {
 297         gint8 true_basereg = basereg;
 298
 299         /* Cache these values, they might change  */
 300         /* as new instructions are emitted below. */
 301         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 302         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 303
 304         /* 'basereg' is given masked to 0x7 at this point, so check */
 305         /* the rex prefix to see if this is an extended register.   */
 306         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 307                 true_basereg |= 0x8;
 308         }
 309
 310 #define X86_LEA_OPCODE (0x8D)
 311
 312         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 313                 guint8* old_instruction_start;
 314
 315                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 316                 /* 32-bits of the old base register (new index register)     */
 317                 guint8 buf[32];
 318                 guint8* buf_ptr = buf;
 319                 size_t insert_len;
 320
 321                 g_assert (rex_tag != NULL);
 322
 323                 if (IS_REX(*rex_tag)) {
 324                         /* The old rex.B should be the new rex.X */
 325                         if (*rex_tag & AMD64_REX_B) {
 326                                 *rex_tag |= AMD64_REX_X;
 327                         }
 328                         /* Since our new base is %r15 set rex.B */
 329                         *rex_tag |= AMD64_REX_B;
 330                 } else {
 331                         /* Shift the instruction by one byte  */
 332                         /* so we can insert a rex prefix      */
 333                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 334                         *code += 1;
 335                         /* New rex prefix only needs rex.B for %r15 base */
 336                         *rex_tag = AMD64_REX(AMD64_REX_B);
 337                 }
 338
 339                 if (legacy_prefix_tag) {
 340                         old_instruction_start = legacy_prefix_tag;
 341                 } else {
 342                         old_instruction_start = rex_tag;
 343                 }
 344
 345                 /* Clears the upper 32-bits of the previous base register */
 346                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 347                 insert_len = buf_ptr - buf;
 348
 349                 /* Move the old instruction forward to make */
 350                 /* room for 'mov' stored in 'buf_ptr'       */
 351                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 352                 *code += insert_len;
 353                 memcpy (old_instruction_start, buf, insert_len);
 354
 355                 /* Sandboxed replacement for the normal membase_emit */
 356                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 357
 358         } else {
 359                 /* Normal default behavior, emit membase memory location */
 360                 x86_membase_emit_body (*code, dreg, basereg, offset);
 361         }
 362 }
 363
 364
 365 static inline unsigned char*
 366 amd64_skip_nops (unsigned char* code)
 367 {
 368         guint8 in_nop;
 369         do {
 370                 in_nop = 0;
 371                 if (   code[0] == 0x90) {
 372                         in_nop = 1;
 373                         code += 1;
 374                 }
 375                 if (   code[0] == 0x66 && code[1] == 0x90) {
 376                         in_nop = 1;
 377                         code += 2;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x00) {
 381                         in_nop = 1;
 382                         code += 3;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x40 && code[3] == 0x00) {
 386                         in_nop = 1;
 387                         code += 4;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x44 && code[3] == 0x00
 391                  && code[4] == 0x00) {
 392                         in_nop = 1;
 393                         code += 5;
 394                 }
 395                 if (code[0] == 0x66 && code[1] == 0x0f
 396                  && code[2] == 0x1f && code[3] == 0x44
 397                  && code[4] == 0x00 && code[5] == 0x00) {
 398                         in_nop = 1;
 399                         code += 6;
 400                 }
 401                 if (code[0] == 0x0f && code[1] == 0x1f
 402                  && code[2] == 0x80 && code[3] == 0x00
 403                  && code[4] == 0x00 && code[5] == 0x00
 404                  && code[6] == 0x00) {
 405                         in_nop = 1;
 406                         code += 7;
 407                 }
 408                 if (code[0] == 0x0f && code[1] == 0x1f
 409                  && code[2] == 0x84 && code[3] == 0x00
 410                  && code[4] == 0x00 && code[5] == 0x00
 411                  && code[6] == 0x00 && code[7] == 0x00) {
 412                         in_nop = 1;
 413                         code += 8;
 414                 }
 415         } while ( in_nop );
 416         return code;
 417 }
 418
 419 guint8*
 420 mono_arch_nacl_skip_nops (guint8* code)
 421 {
 422   return amd64_skip_nops(code);
 423 }
 424
 425 #endif /*__native_client_codegen__*/
 426
 427 static inline void
 428 amd64_patch (unsigned char* code, gpointer target)
 429 {
 430         guint8 rex = 0;
 431
 432 #ifdef __native_client_codegen__
 433         code = amd64_skip_nops (code);
 434 #endif
 435 #if defined(__native_client_codegen__) && defined(__native_client__)
 436         if (nacl_is_code_address (code)) {
 437                 /* For tail calls, code is patched after being installed */
 438                 /* but not through the normal "patch callsite" method.   */
 439                 unsigned char buf[kNaClAlignment];
 440                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 441                 int ret;
 442                 memcpy (buf, aligned_code, kNaClAlignment);
 443                 /* Patch a temp buffer of bundle size, */
 444                 /* then install to actual location.    */
 445                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 446                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 447                 g_assert (ret == 0);
 448                 return;
 449         }
 450         target = nacl_modify_patch_target (target);
 451 #endif
 452
 453         /* Skip REX */
 454         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 455                 rex = code [0];
 456                 code += 1;
 457         }
 458
 459         if ((code [0] & 0xf8) == 0xb8) {
 460                 /* amd64_set_reg_template */
 461                 *(guint64*)(code + 1) = (guint64)target;
 462         }
 463         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 464                 /* mov 0(%rip), %dreg */
 465                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 466         }
 467         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 468                 /* call *<OFFSET>(%rip) */
 469                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 470         }
 471         else if (code [0] == 0xe8) {
 472                 /* call <DISP> */
 473                 gint64 disp = (guint8*)target - (guint8*)code;
 474                 g_assert (amd64_is_imm32 (disp));
 475                 x86_patch (code, (unsigned char*)target);
 476         }
 477         else
 478                 x86_patch (code, (unsigned char*)target);
 479 }
 480
 481 void
 482 mono_amd64_patch (unsigned char* code, gpointer target)
 483 {
 484         amd64_patch (code, target);
 485 }
 486
 487 typedef enum {
 488         ArgInIReg,
 489         ArgInFloatSSEReg,
 490         ArgInDoubleSSEReg,
 491         ArgOnStack,
 492         ArgValuetypeInReg,
 493         ArgValuetypeAddrInIReg,
 494         ArgNone /* only in pair_storage */
 495 } ArgStorage;
 496
 497 typedef struct {
 498         gint16 offset;
 499         gint8  reg;
 500         ArgStorage storage;
 501
 502         /* Only if storage == ArgValuetypeInReg */
 503         ArgStorage pair_storage [2];
 504         gint8 pair_regs [2];
 505         /* The size of each pair */
 506         int pair_size [2];
 507         int nregs;
 508 } ArgInfo;
 509
 510 typedef struct {
 511         int nargs;
 512         guint32 stack_usage;
 513         guint32 reg_usage;
 514         guint32 freg_usage;
 515         gboolean need_stack_align;
 516         gboolean vtype_retaddr;
 517         /* The index of the vret arg in the argument list */
 518         int vret_arg_index;
 519         ArgInfo ret;
 520         ArgInfo sig_cookie;
 521         ArgInfo args [1];
 522 } CallInfo;
 523
 524 #define DEBUG(a) if (cfg->verbose_level > 1) a
 525
 526 #ifdef HOST_WIN32
 527 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 528
 529 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 530 #else
 531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 532
 533  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #endif
 535
 536 static void inline
 537 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 538 {
 539     ainfo->offset = *stack_size;
 540
 541     if (*gr >= PARAM_REGS) {
 542                 ainfo->storage = ArgOnStack;
 543                 /* Since the same stack slot size is used for all arg */
 544                 /*  types, it needs to be big enough to hold them all */
 545                 (*stack_size) += sizeof(mgreg_t);
 546     }
 547     else {
 548                 ainfo->storage = ArgInIReg;
 549                 ainfo->reg = param_regs [*gr];
 550                 (*gr) ++;
 551     }
 552 }
 553
 554 #ifdef HOST_WIN32
 555 #define FLOAT_PARAM_REGS 4
 556 #else
 557 #define FLOAT_PARAM_REGS 8
 558 #endif
 559
 560 static void inline
 561 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 562 {
 563     ainfo->offset = *stack_size;
 564
 565     if (*gr >= FLOAT_PARAM_REGS) {
 566                 ainfo->storage = ArgOnStack;
 567                 /* Since the same stack slot size is used for both float */
 568                 /*  types, it needs to be big enough to hold them both */
 569                 (*stack_size) += sizeof(mgreg_t);
 570     }
 571     else {
 572                 /* A double register */
 573                 if (is_double)
 574                         ainfo->storage = ArgInDoubleSSEReg;
 575                 else
 576                         ainfo->storage = ArgInFloatSSEReg;
 577                 ainfo->reg = *gr;
 578                 (*gr) += 1;
 579     }
 580 }
 581
 582 typedef enum ArgumentClass {
 583         ARG_CLASS_NO_CLASS,
 584         ARG_CLASS_MEMORY,
 585         ARG_CLASS_INTEGER,
 586         ARG_CLASS_SSE
 587 } ArgumentClass;
 588
 589 static ArgumentClass
 590 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 591 {
 592         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 593         MonoType *ptype;
 594
 595         ptype = mini_type_get_underlying_type (gsctx, type);
 596         switch (ptype->type) {
 597         case MONO_TYPE_BOOLEAN:
 598         case MONO_TYPE_CHAR:
 599         case MONO_TYPE_I1:
 600         case MONO_TYPE_U1:
 601         case MONO_TYPE_I2:
 602         case MONO_TYPE_U2:
 603         case MONO_TYPE_I4:
 604         case MONO_TYPE_U4:
 605         case MONO_TYPE_I:
 606         case MONO_TYPE_U:
 607         case MONO_TYPE_STRING:
 608         case MONO_TYPE_OBJECT:
 609         case MONO_TYPE_CLASS:
 610         case MONO_TYPE_SZARRAY:
 611         case MONO_TYPE_PTR:
 612         case MONO_TYPE_FNPTR:
 613         case MONO_TYPE_ARRAY:
 614         case MONO_TYPE_I8:
 615         case MONO_TYPE_U8:
 616                 class2 = ARG_CLASS_INTEGER;
 617                 break;
 618         case MONO_TYPE_R4:
 619         case MONO_TYPE_R8:
 620 #ifdef HOST_WIN32
 621                 class2 = ARG_CLASS_INTEGER;
 622 #else
 623                 class2 = ARG_CLASS_SSE;
 624 #endif
 625                 break;
 626
 627         case MONO_TYPE_TYPEDBYREF:
 628                 g_assert_not_reached ();
 629
 630         case MONO_TYPE_GENERICINST:
 631                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 632                         class2 = ARG_CLASS_INTEGER;
 633                         break;
 634                 }
 635                 /* fall through */
 636         case MONO_TYPE_VALUETYPE: {
 637                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 638                 int i;
 639
 640                 for (i = 0; i < info->num_fields; ++i) {
 641                         class2 = class1;
 642                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 643                 }
 644                 break;
 645         }
 646         default:
 647                 g_assert_not_reached ();
 648         }
 649
 650         /* Merge */
 651         if (class1 == class2)
 652                 ;
 653         else if (class1 == ARG_CLASS_NO_CLASS)
 654                 class1 = class2;
 655         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 656                 class1 = ARG_CLASS_MEMORY;
 657         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 658                 class1 = ARG_CLASS_INTEGER;
 659         else
 660                 class1 = ARG_CLASS_SSE;
 661
 662         return class1;
 663 }
 664 #ifdef __native_client_codegen__
 665
 666 /* Default alignment for Native Client is 32-byte. */
 667 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 668
 669 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 670 /* Check that alignment doesn't cross an alignment boundary.             */
 671 guint8*
 672 mono_arch_nacl_pad(guint8 *code, int pad)
 673 {
 674         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 675
 676         if (pad == 0) return code;
 677         /* assertion: alignment cannot cross a block boundary */
 678         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 679                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 680         while (pad >= kMaxPadding) {
 681                 amd64_padding (code, kMaxPadding);
 682                 pad -= kMaxPadding;
 683         }
 684         if (pad != 0) amd64_padding (code, pad);
 685         return code;
 686 }
 687 #endif
 688
 689 static int
 690 count_fields_nested (MonoClass *klass)
 691 {
 692         MonoMarshalType *info;
 693         int i, count;
 694
 695         info = mono_marshal_load_type_info (klass);
 696         g_assert(info);
 697         count = 0;
 698         for (i = 0; i < info->num_fields; ++i) {
 699                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 700                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 701                 else
 702                         count ++;
 703         }
 704         return count;
 705 }
 706
 707 static int
 708 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 709 {
 710         MonoMarshalType *info;
 711         int i;
 712
 713         info = mono_marshal_load_type_info (klass);
 714         g_assert(info);
 715         for (i = 0; i < info->num_fields; ++i) {
 716                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 717                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 718                 } else {
 719                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 720                         fields [index].offset += offset;
 721                         index ++;
 722                 }
 723         }
 724         return index;
 725 }
 726
 727 static void
 728 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 729                            gboolean is_return,
 730                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 731 {
 732         guint32 size, quad, nquads, i, nfields;
 733         /* Keep track of the size used in each quad so we can */
 734         /* use the right size when copying args/return vars.  */
 735         guint32 quadsize [2] = {8, 8};
 736         ArgumentClass args [2];
 737         MonoMarshalType *info = NULL;
 738         MonoMarshalField *fields = NULL;
 739         MonoClass *klass;
 740         MonoGenericSharingContext tmp_gsctx;
 741         gboolean pass_on_stack = FALSE;
 742
 743         /*
 744          * The gsctx currently contains no data, it is only used for checking whenever
 745          * open types are allowed, some callers like mono_arch_get_argument_info ()
 746          * don't pass it to us, so work around that.
 747          */
 748         if (!gsctx)
 749                 gsctx = &tmp_gsctx;
 750
 751         klass = mono_class_from_mono_type (type);
 752         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 753 #ifndef HOST_WIN32
 754         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 755                 /* We pass and return vtypes of size 8 in a register */
 756         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 757                 pass_on_stack = TRUE;
 758         }
 759 #else
 760         if (!sig->pinvoke) {
 761                 pass_on_stack = TRUE;
 762         }
 763 #endif
 764
 765         /* If this struct can't be split up naturally into 8-byte */
 766         /* chunks (registers), pass it on the stack.              */
 767         if (sig->pinvoke && !pass_on_stack) {
 768                 guint32 align;
 769                 guint32 field_size;
 770
 771                 info = mono_marshal_load_type_info (klass);
 772                 g_assert (info);
 773
 774                 /*
 775                  * Collect field information recursively to be able to
 776                  * handle nested structures.
 777                  */
 778                 nfields = count_fields_nested (klass);
 779                 fields = g_new0 (MonoMarshalField, nfields);
 780                 collect_field_info_nested (klass, fields, 0, 0);
 781
 782                 for (i = 0; i < nfields; ++i) {
 783                         field_size = mono_marshal_type_size (fields [i].field->type,
 784                                                            fields [i].mspec,
 785                                                            &align, TRUE, klass->unicode);
 786                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 787                                 pass_on_stack = TRUE;
 788                                 break;
 789                         }
 790                 }
 791         }
 792
 793         if (pass_on_stack) {
 794                 /* Allways pass in memory */
 795                 ainfo->offset = *stack_size;
 796                 *stack_size += ALIGN_TO (size, 8);
 797                 ainfo->storage = ArgOnStack;
 798
 799                 g_free (fields);
 800                 return;
 801         }
 802
 803         /* FIXME: Handle structs smaller than 8 bytes */
 804         //if ((size % 8) != 0)
 805         //      NOT_IMPLEMENTED;
 806
 807         if (size > 8)
 808                 nquads = 2;
 809         else
 810                 nquads = 1;
 811
 812         if (!sig->pinvoke) {
 813                 int n = mono_class_value_size (klass, NULL);
 814
 815                 quadsize [0] = n >= 8 ? 8 : n;
 816                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 817
 818                 /* Always pass in 1 or 2 integer registers */
 819                 args [0] = ARG_CLASS_INTEGER;
 820                 args [1] = ARG_CLASS_INTEGER;
 821                 /* Only the simplest cases are supported */
 822                 if (is_return && nquads != 1) {
 823                         args [0] = ARG_CLASS_MEMORY;
 824                         args [1] = ARG_CLASS_MEMORY;
 825                 }
 826         } else {
 827                 /*
 828                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 829                  * The X87 and SSEUP stuff is left out since there are no such types in
 830                  * the CLR.
 831                  */
 832                 g_assert (info);
 833                 g_assert (fields);
 834
 835 #ifndef HOST_WIN32
 836                 if (info->native_size > 16) {
 837                         ainfo->offset = *stack_size;
 838                         *stack_size += ALIGN_TO (info->native_size, 8);
 839                         ainfo->storage = ArgOnStack;
 840
 841                         g_free (fields);
 842                         return;
 843                 }
 844 #else
 845                 switch (info->native_size) {
 846                 case 1: case 2: case 4: case 8:
 847                         break;
 848                 default:
 849                         if (is_return) {
 850                                 ainfo->storage = ArgOnStack;
 851                                 ainfo->offset = *stack_size;
 852                                 *stack_size += ALIGN_TO (info->native_size, 8);
 853                         }
 854                         else {
 855                                 ainfo->storage = ArgValuetypeAddrInIReg;
 856
 857                                 if (*gr < PARAM_REGS) {
 858                                         ainfo->pair_storage [0] = ArgInIReg;
 859                                         ainfo->pair_regs [0] = param_regs [*gr];
 860                                         (*gr) ++;
 861                                 }
 862                                 else {
 863                                         ainfo->pair_storage [0] = ArgOnStack;
 864                                         ainfo->offset = *stack_size;
 865                                         *stack_size += 8;
 866                                 }
 867                         }
 868
 869                         g_free (fields);
 870                         return;
 871                 }
 872 #endif
 873
 874                 args [0] = ARG_CLASS_NO_CLASS;
 875                 args [1] = ARG_CLASS_NO_CLASS;
 876                 for (quad = 0; quad < nquads; ++quad) {
 877                         int size;
 878                         guint32 align;
 879                         ArgumentClass class1;
 880
 881                         if (nfields == 0)
 882                                 class1 = ARG_CLASS_MEMORY;
 883                         else
 884                                 class1 = ARG_CLASS_NO_CLASS;
 885                         for (i = 0; i < nfields; ++i) {
 886                                 size = mono_marshal_type_size (fields [i].field->type,
 887                                                                                            fields [i].mspec,
 888                                                                                            &align, TRUE, klass->unicode);
 889                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 890                                         /* Unaligned field */
 891                                         NOT_IMPLEMENTED;
 892                                 }
 893
 894                                 /* Skip fields in other quad */
 895                                 if ((quad == 0) && (fields [i].offset >= 8))
 896                                         continue;
 897                                 if ((quad == 1) && (fields [i].offset < 8))
 898                                         continue;
 899
 900                                 /* How far into this quad this data extends.*/
 901                                 /* (8 is size of quad) */
 902                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 903
 904                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 905                         }
 906                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 907                         args [quad] = class1;
 908                 }
 909         }
 910
 911         g_free (fields);
 912
 913         /* Post merger cleanup */
 914         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 915                 args [0] = args [1] = ARG_CLASS_MEMORY;
 916
 917         /* Allocate registers */
 918         {
 919                 int orig_gr = *gr;
 920                 int orig_fr = *fr;
 921
 922                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 923                         quadsize [0] ++;
 924                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 925                         quadsize [1] ++;
 926
 927                 ainfo->storage = ArgValuetypeInReg;
 928                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 929                 g_assert (quadsize [0] <= 8);
 930                 g_assert (quadsize [1] <= 8);
 931                 ainfo->pair_size [0] = quadsize [0];
 932                 ainfo->pair_size [1] = quadsize [1];
 933                 ainfo->nregs = nquads;
 934                 for (quad = 0; quad < nquads; ++quad) {
 935                         switch (args [quad]) {
 936                         case ARG_CLASS_INTEGER:
 937                                 if (*gr >= PARAM_REGS)
 938                                         args [quad] = ARG_CLASS_MEMORY;
 939                                 else {
 940                                         ainfo->pair_storage [quad] = ArgInIReg;
 941                                         if (is_return)
 942                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 943                                         else
 944                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 945                                         (*gr) ++;
 946                                 }
 947                                 break;
 948                         case ARG_CLASS_SSE:
 949                                 if (*fr >= FLOAT_PARAM_REGS)
 950                                         args [quad] = ARG_CLASS_MEMORY;
 951                                 else {
 952                                         if (quadsize[quad] <= 4)
 953                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 954                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 955                                         ainfo->pair_regs [quad] = *fr;
 956                                         (*fr) ++;
 957                                 }
 958                                 break;
 959                         case ARG_CLASS_MEMORY:
 960                                 break;
 961                         default:
 962                                 g_assert_not_reached ();
 963                         }
 964                 }
 965
 966                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 967                         /* Revert possible register assignments */
 968                         *gr = orig_gr;
 969                         *fr = orig_fr;
 970
 971                         ainfo->offset = *stack_size;
 972                         if (sig->pinvoke)
 973                                 *stack_size += ALIGN_TO (info->native_size, 8);
 974                         else
 975                                 *stack_size += nquads * sizeof(mgreg_t);
 976                         ainfo->storage = ArgOnStack;
 977                 }
 978         }
 979 }
 980
 981 /*
 982  * get_call_info:
 983  *
 984  *  Obtain information about a call according to the calling convention.
 985  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 986  * Draft Version 0.23" document for more information.
 987  */
 988 static CallInfo*
 989 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 990 {
 991         guint32 i, gr, fr, pstart;
 992         MonoType *ret_type;
 993         int n = sig->hasthis + sig->param_count;
 994         guint32 stack_size = 0;
 995         CallInfo *cinfo;
 996         gboolean is_pinvoke = sig->pinvoke;
 997
 998         if (mp)
 999                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1000         else
1001                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002
1003         cinfo->nargs = n;
1004
1005         gr = 0;
1006         fr = 0;
1007
1008 #ifdef HOST_WIN32
1009         /* Reserve space where the callee can save the argument registers */
1010         stack_size = 4 * sizeof (mgreg_t);
1011 #endif
1012
1013         /* return value */
1014         {
1015                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1016                 switch (ret_type->type) {
1017                 case MONO_TYPE_BOOLEAN:
1018                 case MONO_TYPE_I1:
1019                 case MONO_TYPE_U1:
1020                 case MONO_TYPE_I2:
1021                 case MONO_TYPE_U2:
1022                 case MONO_TYPE_CHAR:
1023                 case MONO_TYPE_I4:
1024                 case MONO_TYPE_U4:
1025                 case MONO_TYPE_I:
1026                 case MONO_TYPE_U:
1027                 case MONO_TYPE_PTR:
1028                 case MONO_TYPE_FNPTR:
1029                 case MONO_TYPE_CLASS:
1030                 case MONO_TYPE_OBJECT:
1031                 case MONO_TYPE_SZARRAY:
1032                 case MONO_TYPE_ARRAY:
1033                 case MONO_TYPE_STRING:
1034                         cinfo->ret.storage = ArgInIReg;
1035                         cinfo->ret.reg = AMD64_RAX;
1036                         break;
1037                 case MONO_TYPE_U8:
1038                 case MONO_TYPE_I8:
1039                         cinfo->ret.storage = ArgInIReg;
1040                         cinfo->ret.reg = AMD64_RAX;
1041                         break;
1042                 case MONO_TYPE_R4:
1043                         cinfo->ret.storage = ArgInFloatSSEReg;
1044                         cinfo->ret.reg = AMD64_XMM0;
1045                         break;
1046                 case MONO_TYPE_R8:
1047                         cinfo->ret.storage = ArgInDoubleSSEReg;
1048                         cinfo->ret.reg = AMD64_XMM0;
1049                         break;
1050                 case MONO_TYPE_GENERICINST:
1051                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1052                                 cinfo->ret.storage = ArgInIReg;
1053                                 cinfo->ret.reg = AMD64_RAX;
1054                                 break;
1055                         }
1056                         /* fall through */
1057 #if defined( __native_client_codegen__ )
1058                 case MONO_TYPE_TYPEDBYREF:
1059 #endif
1060                 case MONO_TYPE_VALUETYPE: {
1061                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1062
1063                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1064                         if (cinfo->ret.storage == ArgOnStack) {
1065                                 cinfo->vtype_retaddr = TRUE;
1066                                 /* The caller passes the address where the value is stored */
1067                         }
1068                         break;
1069                 }
1070 #if !defined( __native_client_codegen__ )
1071                 case MONO_TYPE_TYPEDBYREF:
1072                         /* Same as a valuetype with size 24 */
1073                         cinfo->vtype_retaddr = TRUE;
1074                         break;
1075 #endif
1076                 case MONO_TYPE_VOID:
1077                         break;
1078                 default:
1079                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1080                 }
1081         }
1082
1083         pstart = 0;
1084         /*
1085          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1086          * the first argument, allowing 'this' to be always passed in the first arg reg.
1087          * Also do this if the first argument is a reference type, since virtual calls
1088          * are sometimes made using calli without sig->hasthis set, like in the delegate
1089          * invoke wrappers.
1090          */
1091         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1092                 if (sig->hasthis) {
1093                         add_general (&gr, &stack_size, cinfo->args + 0);
1094                 } else {
1095                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1096                         pstart = 1;
1097                 }
1098                 add_general (&gr, &stack_size, &cinfo->ret);
1099                 cinfo->vret_arg_index = 1;
1100         } else {
1101                 /* this */
1102                 if (sig->hasthis)
1103                         add_general (&gr, &stack_size, cinfo->args + 0);
1104
1105                 if (cinfo->vtype_retaddr)
1106                         add_general (&gr, &stack_size, &cinfo->ret);
1107         }
1108
1109         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1110                 gr = PARAM_REGS;
1111                 fr = FLOAT_PARAM_REGS;
1112
1113                 /* Emit the signature cookie just before the implicit arguments */
1114                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1115         }
1116
1117         for (i = pstart; i < sig->param_count; ++i) {
1118                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1119                 MonoType *ptype;
1120
1121 #ifdef HOST_WIN32
1122                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1123                 if (gr > fr)
1124                         fr = gr;
1125                 else if (fr > gr)
1126                         gr = fr;
1127 #endif
1128
1129                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1130                         /* We allways pass the sig cookie on the stack for simplicity */
1131                         /*
1132                          * Prevent implicit arguments + the sig cookie from being passed
1133                          * in registers.
1134                          */
1135                         gr = PARAM_REGS;
1136                         fr = FLOAT_PARAM_REGS;
1137
1138                         /* Emit the signature cookie just before the implicit arguments */
1139                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1140                 }
1141
1142                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1143                 switch (ptype->type) {
1144                 case MONO_TYPE_BOOLEAN:
1145                 case MONO_TYPE_I1:
1146                 case MONO_TYPE_U1:
1147                         add_general (&gr, &stack_size, ainfo);
1148                         break;
1149                 case MONO_TYPE_I2:
1150                 case MONO_TYPE_U2:
1151                 case MONO_TYPE_CHAR:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I4:
1155                 case MONO_TYPE_U4:
1156                         add_general (&gr, &stack_size, ainfo);
1157                         break;
1158                 case MONO_TYPE_I:
1159                 case MONO_TYPE_U:
1160                 case MONO_TYPE_PTR:
1161                 case MONO_TYPE_FNPTR:
1162                 case MONO_TYPE_CLASS:
1163                 case MONO_TYPE_OBJECT:
1164                 case MONO_TYPE_STRING:
1165                 case MONO_TYPE_SZARRAY:
1166                 case MONO_TYPE_ARRAY:
1167                         add_general (&gr, &stack_size, ainfo);
1168                         break;
1169                 case MONO_TYPE_GENERICINST:
1170                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1171                                 add_general (&gr, &stack_size, ainfo);
1172                                 break;
1173                         }
1174                         /* fall through */
1175                 case MONO_TYPE_VALUETYPE:
1176                 case MONO_TYPE_TYPEDBYREF:
1177                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1178                         break;
1179                 case MONO_TYPE_U8:
1180
1181                 case MONO_TYPE_I8:
1182                         add_general (&gr, &stack_size, ainfo);
1183                         break;
1184                 case MONO_TYPE_R4:
1185                         add_float (&fr, &stack_size, ainfo, FALSE);
1186                         break;
1187                 case MONO_TYPE_R8:
1188                         add_float (&fr, &stack_size, ainfo, TRUE);
1189                         break;
1190                 default:
1191                         g_assert_not_reached ();
1192                 }
1193         }
1194
1195         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1196                 gr = PARAM_REGS;
1197                 fr = FLOAT_PARAM_REGS;
1198
1199                 /* Emit the signature cookie just before the implicit arguments */
1200                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1201         }
1202
1203         cinfo->stack_usage = stack_size;
1204         cinfo->reg_usage = gr;
1205         cinfo->freg_usage = fr;
1206         return cinfo;
1207 }
1208
1209 /*
1210  * mono_arch_get_argument_info:
1211  * @csig:  a method signature
1212  * @param_count: the number of parameters to consider
1213  * @arg_info: an array to store the result infos
1214  *
1215  * Gathers information on parameters such as size, alignment and
1216  * padding. arg_info should be large enought to hold param_count + 1 entries.
1217  *
1218  * Returns the size of the argument area on the stack.
1219  */
1220 int
1221 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1222 {
1223         int k;
1224         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1225         guint32 args_size = cinfo->stack_usage;
1226
1227         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1228         if (csig->hasthis) {
1229                 arg_info [0].offset = 0;
1230         }
1231
1232         for (k = 0; k < param_count; k++) {
1233                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1234                 /* FIXME: */
1235                 arg_info [k + 1].size = 0;
1236         }
1237
1238         g_free (cinfo);
1239
1240         return args_size;
1241 }
1242
1243 gboolean
1244 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1245 {
1246         CallInfo *c1, *c2;
1247         gboolean res;
1248         MonoType *callee_ret;
1249
1250         c1 = get_call_info (NULL, NULL, caller_sig);
1251         c2 = get_call_info (NULL, NULL, callee_sig);
1252         res = c1->stack_usage >= c2->stack_usage;
1253         callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1254         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1255                 /* An address on the callee's stack is passed as the first argument */
1256                 res = FALSE;
1257
1258         g_free (c1);
1259         g_free (c2);
1260
1261         return res;
1262 }
1263
1264 /*
1265  * Initialize the cpu to execute managed code.
1266  */
1267 void
1268 mono_arch_cpu_init (void)
1269 {
1270 #ifndef _MSC_VER
1271         guint16 fpcw;
1272
1273         /* spec compliance requires running with double precision */
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275         fpcw &= ~X86_FPCW_PRECC_MASK;
1276         fpcw |= X86_FPCW_PREC_DOUBLE;
1277         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1278         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1279 #else
1280         /* TODO: This is crashing on Win64 right now.
1281         * _control87 (_PC_53, MCW_PC);
1282         */
1283 #endif
1284 }
1285
1286 /*
1287  * Initialize architecture specific code.
1288  */
1289 void
1290 mono_arch_init (void)
1291 {
1292         int flags;
1293
1294         mono_mutex_init_recursive (&mini_arch_mutex);
1295 #if defined(__native_client_codegen__)
1296         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1297         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1298         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1299         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1300 #endif
1301
1302 #ifdef MONO_ARCH_NOMAP32BIT
1303         flags = MONO_MMAP_READ;
1304         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1305         breakpoint_size = 13;
1306         breakpoint_fault_size = 3;
1307 #else
1308         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1309         /* amd64_mov_reg_mem () */
1310         breakpoint_size = 8;
1311         breakpoint_fault_size = 8;
1312 #endif
1313
1314         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1315         single_step_fault_size = 4;
1316
1317         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1318         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1319         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1320
1321         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1322         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1323         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1324 }
1325
1326 /*
1327  * Cleanup architecture specific code.
1328  */
1329 void
1330 mono_arch_cleanup (void)
1331 {
1332         mono_mutex_destroy (&mini_arch_mutex);
1333 #if defined(__native_client_codegen__)
1334         mono_native_tls_free (nacl_instruction_depth);
1335         mono_native_tls_free (nacl_rex_tag);
1336         mono_native_tls_free (nacl_legacy_prefix_tag);
1337 #endif
1338 }
1339
1340 /*
1341  * This function returns the optimizations supported on this cpu.
1342  */
1343 guint32
1344 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1345 {
1346         guint32 opts = 0;
1347
1348         *exclude_mask = 0;
1349
1350         if (mono_hwcap_x86_has_cmov) {
1351                 opts |= MONO_OPT_CMOV;
1352
1353                 if (mono_hwcap_x86_has_fcmov)
1354                         opts |= MONO_OPT_FCMOV;
1355                 else
1356                         *exclude_mask |= MONO_OPT_FCMOV;
1357         } else {
1358                 *exclude_mask |= MONO_OPT_CMOV;
1359         }
1360
1361         return opts;
1362 }
1363
1364 /*
1365  * This function test for all SSE functions supported.
1366  *
1367  * Returns a bitmask corresponding to all supported versions.
1368  *
1369  */
1370 guint32
1371 mono_arch_cpu_enumerate_simd_versions (void)
1372 {
1373         guint32 sse_opts = 0;
1374
1375         if (mono_hwcap_x86_has_sse1)
1376                 sse_opts |= SIMD_VERSION_SSE1;
1377
1378         if (mono_hwcap_x86_has_sse2)
1379                 sse_opts |= SIMD_VERSION_SSE2;
1380
1381         if (mono_hwcap_x86_has_sse3)
1382                 sse_opts |= SIMD_VERSION_SSE3;
1383
1384         if (mono_hwcap_x86_has_ssse3)
1385                 sse_opts |= SIMD_VERSION_SSSE3;
1386
1387         if (mono_hwcap_x86_has_sse41)
1388                 sse_opts |= SIMD_VERSION_SSE41;
1389
1390         if (mono_hwcap_x86_has_sse42)
1391                 sse_opts |= SIMD_VERSION_SSE42;
1392
1393         if (mono_hwcap_x86_has_sse4a)
1394                 sse_opts |= SIMD_VERSION_SSE4a;
1395
1396         return sse_opts;
1397 }
1398
1399 #ifndef DISABLE_JIT
1400
1401 GList *
1402 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1403 {
1404         GList *vars = NULL;
1405         int i;
1406
1407         for (i = 0; i < cfg->num_varinfo; i++) {
1408                 MonoInst *ins = cfg->varinfo [i];
1409                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1410
1411                 /* unused vars */
1412                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1413                         continue;
1414
1415                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1416                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1417                         continue;
1418
1419                 if (mono_is_regsize_var (ins->inst_vtype)) {
1420                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1421                         g_assert (i == vmv->idx);
1422                         vars = g_list_prepend (vars, vmv);
1423                 }
1424         }
1425
1426         vars = mono_varlist_sort (cfg, vars, 0);
1427
1428         return vars;
1429 }
1430
1431 /**
1432  * mono_arch_compute_omit_fp:
1433  *
1434  *   Determine whenever the frame pointer can be eliminated.
1435  */
1436 static void
1437 mono_arch_compute_omit_fp (MonoCompile *cfg)
1438 {
1439         MonoMethodSignature *sig;
1440         MonoMethodHeader *header;
1441         int i, locals_size;
1442         CallInfo *cinfo;
1443
1444         if (cfg->arch.omit_fp_computed)
1445                 return;
1446
1447         header = cfg->header;
1448
1449         sig = mono_method_signature (cfg->method);
1450
1451         if (!cfg->arch.cinfo)
1452                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1453         cinfo = cfg->arch.cinfo;
1454
1455         /*
1456          * FIXME: Remove some of the restrictions.
1457          */
1458         cfg->arch.omit_fp = TRUE;
1459         cfg->arch.omit_fp_computed = TRUE;
1460
1461 #ifdef __native_client_codegen__
1462         /* NaCl modules may not change the value of RBP, so it cannot be */
1463         /* used as a normal register, but it can be used as a frame pointer*/
1464         cfg->disable_omit_fp = TRUE;
1465         cfg->arch.omit_fp = FALSE;
1466 #endif
1467
1468         if (cfg->disable_omit_fp)
1469                 cfg->arch.omit_fp = FALSE;
1470
1471         if (!debug_omit_fp ())
1472                 cfg->arch.omit_fp = FALSE;
1473         /*
1474         if (cfg->method->save_lmf)
1475                 cfg->arch.omit_fp = FALSE;
1476         */
1477         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1478                 cfg->arch.omit_fp = FALSE;
1479         if (header->num_clauses)
1480                 cfg->arch.omit_fp = FALSE;
1481         if (cfg->param_area)
1482                 cfg->arch.omit_fp = FALSE;
1483         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1484                 cfg->arch.omit_fp = FALSE;
1485         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1486                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1487                 cfg->arch.omit_fp = FALSE;
1488         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1489                 ArgInfo *ainfo = &cinfo->args [i];
1490
1491                 if (ainfo->storage == ArgOnStack) {
1492                         /*
1493                          * The stack offset can only be determined when the frame
1494                          * size is known.
1495                          */
1496                         cfg->arch.omit_fp = FALSE;
1497                 }
1498         }
1499
1500         locals_size = 0;
1501         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1502                 MonoInst *ins = cfg->varinfo [i];
1503                 int ialign;
1504
1505                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1506         }
1507 }
1508
1509 GList *
1510 mono_arch_get_global_int_regs (MonoCompile *cfg)
1511 {
1512         GList *regs = NULL;
1513
1514         mono_arch_compute_omit_fp (cfg);
1515
1516         if (cfg->globalra) {
1517                 if (cfg->arch.omit_fp)
1518                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1519
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1522                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1523                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1524 #ifndef __native_client_codegen__
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1526 #endif
1527
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1531                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1532                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1533                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1534                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1535                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1536         } else {
1537                 if (cfg->arch.omit_fp)
1538                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1539
1540                 /* We use the callee saved registers for global allocation */
1541                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1542                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1543                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1544                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1545 #ifndef __native_client_codegen__
1546                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1547 #endif
1548 #ifdef HOST_WIN32
1549                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1550                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1551 #endif
1552         }
1553
1554         return regs;
1555 }
1556
1557 GList*
1558 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1559 {
1560         GList *regs = NULL;
1561         int i;
1562
1563         /* All XMM registers */
1564         for (i = 0; i < 16; ++i)
1565                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1566
1567         return regs;
1568 }
1569
1570 GList*
1571 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1572 {
1573         static GList *r = NULL;
1574
1575         if (r == NULL) {
1576                 GList *regs = NULL;
1577
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1581                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1582                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1583 #ifndef __native_client_codegen__
1584                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1585 #endif
1586
1587                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1588                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1589                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1590                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1591                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1592                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1593                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1594                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1595
1596                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1597         }
1598
1599         return r;
1600 }
1601
1602 GList*
1603 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1604 {
1605         int i;
1606         static GList *r = NULL;
1607
1608         if (r == NULL) {
1609                 GList *regs = NULL;
1610
1611                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1612                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1613
1614                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1615         }
1616
1617         return r;
1618 }
1619
1620 /*
1621  * mono_arch_regalloc_cost:
1622  *
1623  *  Return the cost, in number of memory references, of the action of
1624  * allocating the variable VMV into a register during global register
1625  * allocation.
1626  */
1627 guint32
1628 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1629 {
1630         MonoInst *ins = cfg->varinfo [vmv->idx];
1631
1632         if (cfg->method->save_lmf)
1633                 /* The register is already saved */
1634                 /* substract 1 for the invisible store in the prolog */
1635                 return (ins->opcode == OP_ARG) ? 0 : 1;
1636         else
1637                 /* push+pop */
1638                 return (ins->opcode == OP_ARG) ? 1 : 2;
1639 }
1640
1641 /*
1642  * mono_arch_fill_argument_info:
1643  *
1644  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1645  * of the method.
1646  */
1647 void
1648 mono_arch_fill_argument_info (MonoCompile *cfg)
1649 {
1650         MonoType *sig_ret;
1651         MonoMethodSignature *sig;
1652         MonoMethodHeader *header;
1653         MonoInst *ins;
1654         int i;
1655         CallInfo *cinfo;
1656
1657         header = cfg->header;
1658
1659         sig = mono_method_signature (cfg->method);
1660
1661         cinfo = cfg->arch.cinfo;
1662         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1663
1664         /*
1665          * Contrary to mono_arch_allocate_vars (), the information should describe
1666          * where the arguments are at the beginning of the method, not where they can be
1667          * accessed during the execution of the method. The later makes no sense for the
1668          * global register allocator, since a variable can be in more than one location.
1669          */
1670         if (sig_ret->type != MONO_TYPE_VOID) {
1671                 switch (cinfo->ret.storage) {
1672                 case ArgInIReg:
1673                 case ArgInFloatSSEReg:
1674                 case ArgInDoubleSSEReg:
1675                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1676                                 cfg->vret_addr->opcode = OP_REGVAR;
1677                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1678                         }
1679                         else {
1680                                 cfg->ret->opcode = OP_REGVAR;
1681                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1682                         }
1683                         break;
1684                 case ArgValuetypeInReg:
1685                         cfg->ret->opcode = OP_REGOFFSET;
1686                         cfg->ret->inst_basereg = -1;
1687                         cfg->ret->inst_offset = -1;
1688                         break;
1689                 default:
1690                         g_assert_not_reached ();
1691                 }
1692         }
1693
1694         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1695                 ArgInfo *ainfo = &cinfo->args [i];
1696                 MonoType *arg_type;
1697
1698                 ins = cfg->args [i];
1699
1700                 if (sig->hasthis && (i == 0))
1701                         arg_type = &mono_defaults.object_class->byval_arg;
1702                 else
1703                         arg_type = sig->params [i - sig->hasthis];
1704
1705                 switch (ainfo->storage) {
1706                 case ArgInIReg:
1707                 case ArgInFloatSSEReg:
1708                 case ArgInDoubleSSEReg:
1709                         ins->opcode = OP_REGVAR;
1710                         ins->inst_c0 = ainfo->reg;
1711                         break;
1712                 case ArgOnStack:
1713                         ins->opcode = OP_REGOFFSET;
1714                         ins->inst_basereg = -1;
1715                         ins->inst_offset = -1;
1716                         break;
1717                 case ArgValuetypeInReg:
1718                         /* Dummy */
1719                         ins->opcode = OP_NOP;
1720                         break;
1721                 default:
1722                         g_assert_not_reached ();
1723                 }
1724         }
1725 }
1726
1727 void
1728 mono_arch_allocate_vars (MonoCompile *cfg)
1729 {
1730         MonoType *sig_ret;
1731         MonoMethodSignature *sig;
1732         MonoMethodHeader *header;
1733         MonoInst *ins;
1734         int i, offset;
1735         guint32 locals_stack_size, locals_stack_align;
1736         gint32 *offsets;
1737         CallInfo *cinfo;
1738
1739         header = cfg->header;
1740
1741         sig = mono_method_signature (cfg->method);
1742
1743         cinfo = cfg->arch.cinfo;
1744         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1745
1746         mono_arch_compute_omit_fp (cfg);
1747
1748         /*
1749          * We use the ABI calling conventions for managed code as well.
1750          * Exception: valuetypes are only sometimes passed or returned in registers.
1751          */
1752
1753         /*
1754          * The stack looks like this:
1755          * <incoming arguments passed on the stack>
1756          * <return value>
1757          * <lmf/caller saved registers>
1758          * <locals>
1759          * <spill area>
1760          * <localloc area>  -> grows dynamically
1761          * <params area>
1762          */
1763
1764         if (cfg->arch.omit_fp) {
1765                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1766                 cfg->frame_reg = AMD64_RSP;
1767                 offset = 0;
1768         } else {
1769                 /* Locals are allocated backwards from %fp */
1770                 cfg->frame_reg = AMD64_RBP;
1771                 offset = 0;
1772         }
1773
1774         cfg->arch.saved_iregs = cfg->used_int_regs;
1775         if (cfg->method->save_lmf)
1776                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1777                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1778
1779         if (cfg->arch.omit_fp)
1780                 cfg->arch.reg_save_area_offset = offset;
1781         /* Reserve space for callee saved registers */
1782         for (i = 0; i < AMD64_NREG; ++i)
1783                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1784                         offset += sizeof(mgreg_t);
1785                 }
1786         if (!cfg->arch.omit_fp)
1787                 cfg->arch.reg_save_area_offset = -offset;
1788
1789         if (sig_ret->type != MONO_TYPE_VOID) {
1790                 switch (cinfo->ret.storage) {
1791                 case ArgInIReg:
1792                 case ArgInFloatSSEReg:
1793                 case ArgInDoubleSSEReg:
1794                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1795                                 if (cfg->globalra) {
1796                                         cfg->vret_addr->opcode = OP_REGVAR;
1797                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1798                                 } else {
1799                                         /* The register is volatile */
1800                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1801                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1802                                         if (cfg->arch.omit_fp) {
1803                                                 cfg->vret_addr->inst_offset = offset;
1804                                                 offset += 8;
1805                                         } else {
1806                                                 offset += 8;
1807                                                 cfg->vret_addr->inst_offset = -offset;
1808                                         }
1809                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1810                                                 printf ("vret_addr =");
1811                                                 mono_print_ins (cfg->vret_addr);
1812                                         }
1813                                 }
1814                         }
1815                         else {
1816                                 cfg->ret->opcode = OP_REGVAR;
1817                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1818                         }
1819                         break;
1820                 case ArgValuetypeInReg:
1821                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1822                         cfg->ret->opcode = OP_REGOFFSET;
1823                         cfg->ret->inst_basereg = cfg->frame_reg;
1824                         if (cfg->arch.omit_fp) {
1825                                 cfg->ret->inst_offset = offset;
1826                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1827                         } else {
1828                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1829                                 cfg->ret->inst_offset = - offset;
1830                         }
1831                         break;
1832                 default:
1833                         g_assert_not_reached ();
1834                 }
1835                 if (!cfg->globalra)
1836                         cfg->ret->dreg = cfg->ret->inst_c0;
1837         }
1838
1839         /* Allocate locals */
1840         if (!cfg->globalra) {
1841                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1842                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1843                         char *mname = mono_method_full_name (cfg->method, TRUE);
1844                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1845                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1846                         g_free (mname);
1847                         return;
1848                 }
1849
1850                 if (locals_stack_align) {
1851                         offset += (locals_stack_align - 1);
1852                         offset &= ~(locals_stack_align - 1);
1853                 }
1854                 if (cfg->arch.omit_fp) {
1855                         cfg->locals_min_stack_offset = offset;
1856                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1857                 } else {
1858                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1859                         cfg->locals_max_stack_offset = - offset;
1860                 }
1861
1862                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1863                         if (offsets [i] != -1) {
1864                                 MonoInst *ins = cfg->varinfo [i];
1865                                 ins->opcode = OP_REGOFFSET;
1866                                 ins->inst_basereg = cfg->frame_reg;
1867                                 if (cfg->arch.omit_fp)
1868                                         ins->inst_offset = (offset + offsets [i]);
1869                                 else
1870                                         ins->inst_offset = - (offset + offsets [i]);
1871                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1872                         }
1873                 }
1874                 offset += locals_stack_size;
1875         }
1876
1877         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1878                 g_assert (!cfg->arch.omit_fp);
1879                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1880                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1881         }
1882
1883         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1884                 ins = cfg->args [i];
1885                 if (ins->opcode != OP_REGVAR) {
1886                         ArgInfo *ainfo = &cinfo->args [i];
1887                         gboolean inreg = TRUE;
1888                         MonoType *arg_type;
1889
1890                         if (sig->hasthis && (i == 0))
1891                                 arg_type = &mono_defaults.object_class->byval_arg;
1892                         else
1893                                 arg_type = sig->params [i - sig->hasthis];
1894
1895                         if (cfg->globalra) {
1896                                 /* The new allocator needs info about the original locations of the arguments */
1897                                 switch (ainfo->storage) {
1898                                 case ArgInIReg:
1899                                 case ArgInFloatSSEReg:
1900                                 case ArgInDoubleSSEReg:
1901                                         ins->opcode = OP_REGVAR;
1902                                         ins->inst_c0 = ainfo->reg;
1903                                         break;
1904                                 case ArgOnStack:
1905                                         g_assert (!cfg->arch.omit_fp);
1906                                         ins->opcode = OP_REGOFFSET;
1907                                         ins->inst_basereg = cfg->frame_reg;
1908                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1909                                         break;
1910                                 case ArgValuetypeInReg:
1911                                         ins->opcode = OP_REGOFFSET;
1912                                         ins->inst_basereg = cfg->frame_reg;
1913                                         /* These arguments are saved to the stack in the prolog */
1914                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1915                                         if (cfg->arch.omit_fp) {
1916                                                 ins->inst_offset = offset;
1917                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1918                                         } else {
1919                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1920                                                 ins->inst_offset = - offset;
1921                                         }
1922                                         break;
1923                                 default:
1924                                         g_assert_not_reached ();
1925                                 }
1926
1927                                 continue;
1928                         }
1929
1930                         /* FIXME: Allocate volatile arguments to registers */
1931                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1932                                 inreg = FALSE;
1933
1934                         /*
1935                          * Under AMD64, all registers used to pass arguments to functions
1936                          * are volatile across calls.
1937                          * FIXME: Optimize this.
1938                          */
1939                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1940                                 inreg = FALSE;
1941
1942                         ins->opcode = OP_REGOFFSET;
1943
1944                         switch (ainfo->storage) {
1945                         case ArgInIReg:
1946                         case ArgInFloatSSEReg:
1947                         case ArgInDoubleSSEReg:
1948                                 if (inreg) {
1949                                         ins->opcode = OP_REGVAR;
1950                                         ins->dreg = ainfo->reg;
1951                                 }
1952                                 break;
1953                         case ArgOnStack:
1954                                 g_assert (!cfg->arch.omit_fp);
1955                                 ins->opcode = OP_REGOFFSET;
1956                                 ins->inst_basereg = cfg->frame_reg;
1957                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1958                                 break;
1959                         case ArgValuetypeInReg:
1960                                 break;
1961                         case ArgValuetypeAddrInIReg: {
1962                                 MonoInst *indir;
1963                                 g_assert (!cfg->arch.omit_fp);
1964
1965                                 MONO_INST_NEW (cfg, indir, 0);
1966                                 indir->opcode = OP_REGOFFSET;
1967                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1968                                         indir->inst_basereg = cfg->frame_reg;
1969                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1970                                         offset += (sizeof (gpointer));
1971                                         indir->inst_offset = - offset;
1972                                 }
1973                                 else {
1974                                         indir->inst_basereg = cfg->frame_reg;
1975                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1976                                 }
1977
1978                                 ins->opcode = OP_VTARG_ADDR;
1979                                 ins->inst_left = indir;
1980
1981                                 break;
1982                         }
1983                         default:
1984                                 NOT_IMPLEMENTED;
1985                         }
1986
1987                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1988                                 ins->opcode = OP_REGOFFSET;
1989                                 ins->inst_basereg = cfg->frame_reg;
1990                                 /* These arguments are saved to the stack in the prolog */
1991                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1992                                 if (cfg->arch.omit_fp) {
1993                                         ins->inst_offset = offset;
1994                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1995                                         // Arguments are yet supported by the stack map creation code
1996                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1997                                 } else {
1998                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1999                                         ins->inst_offset = - offset;
2000                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2001                                 }
2002                         }
2003                 }
2004         }
2005
2006         cfg->stack_offset = offset;
2007 }
2008
2009 void
2010 mono_arch_create_vars (MonoCompile *cfg)
2011 {
2012         MonoMethodSignature *sig;
2013         CallInfo *cinfo;
2014         MonoType *sig_ret;
2015
2016         sig = mono_method_signature (cfg->method);
2017
2018         if (!cfg->arch.cinfo)
2019                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2020         cinfo = cfg->arch.cinfo;
2021
2022         if (cinfo->ret.storage == ArgValuetypeInReg)
2023                 cfg->ret_var_is_local = TRUE;
2024
2025         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2026         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2027                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2028                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2029                         printf ("vret_addr = ");
2030                         mono_print_ins (cfg->vret_addr);
2031                 }
2032         }
2033
2034         if (cfg->gen_seq_points_debug_data) {
2035                 MonoInst *ins;
2036
2037                 if (cfg->compile_aot) {
2038                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2039                         ins->flags |= MONO_INST_VOLATILE;
2040                         cfg->arch.seq_point_info_var = ins;
2041                 }
2042
2043             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2044                 ins->flags |= MONO_INST_VOLATILE;
2045                 cfg->arch.ss_trigger_page_var = ins;
2046         }
2047
2048         if (cfg->method->save_lmf)
2049                 cfg->create_lmf_var = TRUE;
2050
2051         if (cfg->method->save_lmf) {
2052                 cfg->lmf_ir = TRUE;
2053 #if !defined(HOST_WIN32)
2054                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2055                         cfg->lmf_ir_mono_lmf = TRUE;
2056 #endif
2057         }
2058 }
2059
2060 static void
2061 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2062 {
2063         MonoInst *ins;
2064
2065         switch (storage) {
2066         case ArgInIReg:
2067                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2068                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2069                 ins->sreg1 = tree->dreg;
2070                 MONO_ADD_INS (cfg->cbb, ins);
2071                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2072                 break;
2073         case ArgInFloatSSEReg:
2074                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2075                 ins->dreg = mono_alloc_freg (cfg);
2076                 ins->sreg1 = tree->dreg;
2077                 MONO_ADD_INS (cfg->cbb, ins);
2078
2079                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2080                 break;
2081         case ArgInDoubleSSEReg:
2082                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2083                 ins->dreg = mono_alloc_freg (cfg);
2084                 ins->sreg1 = tree->dreg;
2085                 MONO_ADD_INS (cfg->cbb, ins);
2086
2087                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2088
2089                 break;
2090         default:
2091                 g_assert_not_reached ();
2092         }
2093 }
2094
2095 static int
2096 arg_storage_to_load_membase (ArgStorage storage)
2097 {
2098         switch (storage) {
2099         case ArgInIReg:
2100 #if defined(__mono_ilp32__)
2101                 return OP_LOADI8_MEMBASE;
2102 #else
2103                 return OP_LOAD_MEMBASE;
2104 #endif
2105         case ArgInDoubleSSEReg:
2106                 return OP_LOADR8_MEMBASE;
2107         case ArgInFloatSSEReg:
2108                 return OP_LOADR4_MEMBASE;
2109         default:
2110                 g_assert_not_reached ();
2111         }
2112
2113         return -1;
2114 }
2115
2116 static void
2117 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2118 {
2119         MonoMethodSignature *tmp_sig;
2120         int sig_reg;
2121
2122         if (call->tail_call)
2123                 NOT_IMPLEMENTED;
2124
2125         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2126
2127         /*
2128          * mono_ArgIterator_Setup assumes the signature cookie is
2129          * passed first and all the arguments which were before it are
2130          * passed on the stack after the signature. So compensate by
2131          * passing a different signature.
2132          */
2133         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2134         tmp_sig->param_count -= call->signature->sentinelpos;
2135         tmp_sig->sentinelpos = 0;
2136         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2137
2138         sig_reg = mono_alloc_ireg (cfg);
2139         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2140
2141         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2142 }
2143
2144 static inline LLVMArgStorage
2145 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2146 {
2147         switch (storage) {
2148         case ArgInIReg:
2149                 return LLVMArgInIReg;
2150         case ArgNone:
2151                 return LLVMArgNone;
2152         default:
2153                 g_assert_not_reached ();
2154                 return LLVMArgNone;
2155         }
2156 }
2157
2158 #ifdef ENABLE_LLVM
2159 LLVMCallInfo*
2160 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2161 {
2162         int i, n;
2163         CallInfo *cinfo;
2164         ArgInfo *ainfo;
2165         int j;
2166         LLVMCallInfo *linfo;
2167         MonoType *t, *sig_ret;
2168
2169         n = sig->param_count + sig->hasthis;
2170         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2171
2172         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2173
2174         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2175
2176         /*
2177          * LLVM always uses the native ABI while we use our own ABI, the
2178          * only difference is the handling of vtypes:
2179          * - we only pass/receive them in registers in some cases, and only
2180          *   in 1 or 2 integer registers.
2181          */
2182         if (cinfo->ret.storage == ArgValuetypeInReg) {
2183                 if (sig->pinvoke) {
2184                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2185                         cfg->disable_llvm = TRUE;
2186                         return linfo;
2187                 }
2188
2189                 linfo->ret.storage = LLVMArgVtypeInReg;
2190                 for (j = 0; j < 2; ++j)
2191                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2192         }
2193
2194         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2195                 /* Vtype returned using a hidden argument */
2196                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2197                 linfo->vret_arg_index = cinfo->vret_arg_index;
2198         }
2199
2200         for (i = 0; i < n; ++i) {
2201                 ainfo = cinfo->args + i;
2202
2203                 if (i >= sig->hasthis)
2204                         t = sig->params [i - sig->hasthis];
2205                 else
2206                         t = &mono_defaults.int_class->byval_arg;
2207
2208                 linfo->args [i].storage = LLVMArgNone;
2209
2210                 switch (ainfo->storage) {
2211                 case ArgInIReg:
2212                         linfo->args [i].storage = LLVMArgInIReg;
2213                         break;
2214                 case ArgInDoubleSSEReg:
2215                 case ArgInFloatSSEReg:
2216                         linfo->args [i].storage = LLVMArgInFPReg;
2217                         break;
2218                 case ArgOnStack:
2219                         if (MONO_TYPE_ISSTRUCT (t)) {
2220                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2221                         } else {
2222                                 linfo->args [i].storage = LLVMArgInIReg;
2223                                 if (!t->byref) {
2224                                         if (t->type == MONO_TYPE_R4)
2225                                                 linfo->args [i].storage = LLVMArgInFPReg;
2226                                         else if (t->type == MONO_TYPE_R8)
2227                                                 linfo->args [i].storage = LLVMArgInFPReg;
2228                                 }
2229                         }
2230                         break;
2231                 case ArgValuetypeInReg:
2232                         if (sig->pinvoke) {
2233                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2234                                 cfg->disable_llvm = TRUE;
2235                                 return linfo;
2236                         }
2237
2238                         linfo->args [i].storage = LLVMArgVtypeInReg;
2239                         for (j = 0; j < 2; ++j)
2240                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2241                         break;
2242                 default:
2243                         cfg->exception_message = g_strdup ("ainfo->storage");
2244                         cfg->disable_llvm = TRUE;
2245                         break;
2246                 }
2247         }
2248
2249         return linfo;
2250 }
2251 #endif
2252
2253 void
2254 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2255 {
2256         MonoInst *arg, *in;
2257         MonoMethodSignature *sig;
2258         MonoType *sig_ret;
2259         int i, n, stack_size;
2260         CallInfo *cinfo;
2261         ArgInfo *ainfo;
2262
2263         stack_size = 0;
2264
2265         sig = call->signature;
2266         n = sig->param_count + sig->hasthis;
2267
2268         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2269
2270         sig_ret = sig->ret;
2271
2272         if (COMPILE_LLVM (cfg)) {
2273                 /* We shouldn't be called in the llvm case */
2274                 cfg->disable_llvm = TRUE;
2275                 return;
2276         }
2277
2278         /*
2279          * Emit all arguments which are passed on the stack to prevent register
2280          * allocation problems.
2281          */
2282         for (i = 0; i < n; ++i) {
2283                 MonoType *t;
2284                 ainfo = cinfo->args + i;
2285
2286                 in = call->args [i];
2287
2288                 if (sig->hasthis && i == 0)
2289                         t = &mono_defaults.object_class->byval_arg;
2290                 else
2291                         t = sig->params [i - sig->hasthis];
2292
2293                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2294                         if (!t->byref) {
2295                                 if (t->type == MONO_TYPE_R4)
2296                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2297                                 else if (t->type == MONO_TYPE_R8)
2298                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2299                                 else
2300                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2301                         } else {
2302                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2303                         }
2304                         if (cfg->compute_gc_maps) {
2305                                 MonoInst *def;
2306
2307                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2308                         }
2309                 }
2310         }
2311
2312         /*
2313          * Emit all parameters passed in registers in non-reverse order for better readability
2314          * and to help the optimization in emit_prolog ().
2315          */
2316         for (i = 0; i < n; ++i) {
2317                 ainfo = cinfo->args + i;
2318
2319                 in = call->args [i];
2320
2321                 if (ainfo->storage == ArgInIReg)
2322                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2323         }
2324
2325         for (i = n - 1; i >= 0; --i) {
2326                 ainfo = cinfo->args + i;
2327
2328                 in = call->args [i];
2329
2330                 switch (ainfo->storage) {
2331                 case ArgInIReg:
2332                         /* Already done */
2333                         break;
2334                 case ArgInFloatSSEReg:
2335                 case ArgInDoubleSSEReg:
2336                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2337                         break;
2338                 case ArgOnStack:
2339                 case ArgValuetypeInReg:
2340                 case ArgValuetypeAddrInIReg:
2341                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2342                                 MonoInst *call_inst = (MonoInst*)call;
2343                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2344                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2345                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2346                                 guint32 align;
2347                                 guint32 size;
2348
2349                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2350                                         size = sizeof (MonoTypedRef);
2351                                         align = sizeof (gpointer);
2352                                 }
2353                                 else {
2354                                         if (sig->pinvoke)
2355                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2356                                         else {
2357                                                 /*
2358                                                  * Other backends use mono_type_stack_size (), but that
2359                                                  * aligns the size to 8, which is larger than the size of
2360                                                  * the source, leading to reads of invalid memory if the
2361                                                  * source is at the end of address space.
2362                                                  */
2363                                                 size = mono_class_value_size (in->klass, &align);
2364                                         }
2365                                 }
2366                                 g_assert (in->klass);
2367
2368                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2369                                         /* Avoid asserts in emit_memcpy () */
2370                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2371                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2372                                         /* Continue normally */
2373                                 }
2374
2375                                 if (size > 0) {
2376                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2377                                         arg->sreg1 = in->dreg;
2378                                         arg->klass = in->klass;
2379                                         arg->backend.size = size;
2380                                         arg->inst_p0 = call;
2381                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2382                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2383
2384                                         MONO_ADD_INS (cfg->cbb, arg);
2385                                 }
2386                         }
2387                         break;
2388                 default:
2389                         g_assert_not_reached ();
2390                 }
2391
2392                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2393                         /* Emit the signature cookie just before the implicit arguments */
2394                         emit_sig_cookie (cfg, call, cinfo);
2395         }
2396
2397         /* Handle the case where there are no implicit arguments */
2398         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2399                 emit_sig_cookie (cfg, call, cinfo);
2400
2401         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2402         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2403                 MonoInst *vtarg;
2404
2405                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2406                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2407                                 /*
2408                                  * Tell the JIT to use a more efficient calling convention: call using
2409                                  * OP_CALL, compute the result location after the call, and save the
2410                                  * result there.
2411                                  */
2412                                 call->vret_in_reg = TRUE;
2413                                 /*
2414                                  * Nullify the instruction computing the vret addr to enable
2415                                  * future optimizations.
2416                                  */
2417                                 if (call->vret_var)
2418                                         NULLIFY_INS (call->vret_var);
2419                         } else {
2420                                 if (call->tail_call)
2421                                         NOT_IMPLEMENTED;
2422                                 /*
2423                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2424                                  * the stack. Push the address here, so the call instruction can
2425                                  * access it.
2426                                  */
2427                                 if (!cfg->arch.vret_addr_loc) {
2428                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2429                                         /* Prevent it from being register allocated or optimized away */
2430                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2431                                 }
2432
2433                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2434                         }
2435                 }
2436                 else {
2437                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2438                         vtarg->sreg1 = call->vret_var->dreg;
2439                         vtarg->dreg = mono_alloc_preg (cfg);
2440                         MONO_ADD_INS (cfg->cbb, vtarg);
2441
2442                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2443                 }
2444         }
2445
2446         if (cfg->method->save_lmf) {
2447                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2448                 MONO_ADD_INS (cfg->cbb, arg);
2449         }
2450
2451         call->stack_usage = cinfo->stack_usage;
2452 }
2453
2454 void
2455 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2456 {
2457         MonoInst *arg;
2458         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2459         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2460         int size = ins->backend.size;
2461
2462         if (ainfo->storage == ArgValuetypeInReg) {
2463                 MonoInst *load;
2464                 int part;
2465
2466                 for (part = 0; part < 2; ++part) {
2467                         if (ainfo->pair_storage [part] == ArgNone)
2468                                 continue;
2469
2470                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2471                         load->inst_basereg = src->dreg;
2472                         load->inst_offset = part * sizeof(mgreg_t);
2473
2474                         switch (ainfo->pair_storage [part]) {
2475                         case ArgInIReg:
2476                                 load->dreg = mono_alloc_ireg (cfg);
2477                                 break;
2478                         case ArgInDoubleSSEReg:
2479                         case ArgInFloatSSEReg:
2480                                 load->dreg = mono_alloc_freg (cfg);
2481                                 break;
2482                         default:
2483                                 g_assert_not_reached ();
2484                         }
2485                         MONO_ADD_INS (cfg->cbb, load);
2486
2487                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2488                 }
2489         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2490                 MonoInst *vtaddr, *load;
2491                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2492
2493                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2494                 cfg->has_indirection = TRUE;
2495                 load->inst_p0 = vtaddr;
2496                 vtaddr->flags |= MONO_INST_INDIRECT;
2497                 load->type = STACK_MP;
2498                 load->klass = vtaddr->klass;
2499                 load->dreg = mono_alloc_ireg (cfg);
2500                 MONO_ADD_INS (cfg->cbb, load);
2501                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2502
2503                 if (ainfo->pair_storage [0] == ArgInIReg) {
2504                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2505                         arg->dreg = mono_alloc_ireg (cfg);
2506                         arg->sreg1 = load->dreg;
2507                         arg->inst_imm = 0;
2508                         MONO_ADD_INS (cfg->cbb, arg);
2509                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2510                 } else {
2511                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2512                 }
2513         } else {
2514                 if (size == 8) {
2515                         int dreg = mono_alloc_ireg (cfg);
2516
2517                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2518                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2519                 } else if (size <= 40) {
2520                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2521                 } else {
2522                         // FIXME: Code growth
2523                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2524                 }
2525
2526                 if (cfg->compute_gc_maps) {
2527                         MonoInst *def;
2528                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2529                 }
2530         }
2531 }
2532
2533 void
2534 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2535 {
2536         MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2537
2538         if (ret->type == MONO_TYPE_R4) {
2539                 if (COMPILE_LLVM (cfg))
2540                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2541                 else
2542                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2543                 return;
2544         } else if (ret->type == MONO_TYPE_R8) {
2545                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2546                 return;
2547         }
2548
2549         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2550 }
2551
2552 #endif /* DISABLE_JIT */
2553
2554 #define EMIT_COND_BRANCH(ins,cond,sign) \
2555         if (ins->inst_true_bb->native_offset) { \
2556                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2557         } else { \
2558                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2559                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2560             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2561                         x86_branch8 (code, cond, 0, sign); \
2562                 else \
2563                         x86_branch32 (code, cond, 0, sign); \
2564 }
2565
2566 typedef struct {
2567         MonoMethodSignature *sig;
2568         CallInfo *cinfo;
2569 } ArchDynCallInfo;
2570
2571 static gboolean
2572 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2573 {
2574         int i;
2575
2576 #ifdef HOST_WIN32
2577         return FALSE;
2578 #endif
2579
2580         switch (cinfo->ret.storage) {
2581         case ArgNone:
2582         case ArgInIReg:
2583                 break;
2584         case ArgValuetypeInReg: {
2585                 ArgInfo *ainfo = &cinfo->ret;
2586
2587                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2588                         return FALSE;
2589                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2590                         return FALSE;
2591                 break;
2592         }
2593         default:
2594                 return FALSE;
2595         }
2596
2597         for (i = 0; i < cinfo->nargs; ++i) {
2598                 ArgInfo *ainfo = &cinfo->args [i];
2599                 switch (ainfo->storage) {
2600                 case ArgInIReg:
2601                         break;
2602                 case ArgValuetypeInReg:
2603                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2604                                 return FALSE;
2605                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2606                                 return FALSE;
2607                         break;
2608                 default:
2609                         return FALSE;
2610                 }
2611         }
2612
2613         return TRUE;
2614 }
2615
2616 /*
2617  * mono_arch_dyn_call_prepare:
2618  *
2619  *   Return a pointer to an arch-specific structure which contains information
2620  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2621  * supported for SIG.
2622  * This function is equivalent to ffi_prep_cif in libffi.
2623  */
2624 MonoDynCallInfo*
2625 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2626 {
2627         ArchDynCallInfo *info;
2628         CallInfo *cinfo;
2629
2630         cinfo = get_call_info (NULL, NULL, sig);
2631
2632         if (!dyn_call_supported (sig, cinfo)) {
2633                 g_free (cinfo);
2634                 return NULL;
2635         }
2636
2637         info = g_new0 (ArchDynCallInfo, 1);
2638         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2639         info->sig = sig;
2640         info->cinfo = cinfo;
2641
2642         return (MonoDynCallInfo*)info;
2643 }
2644
2645 /*
2646  * mono_arch_dyn_call_free:
2647  *
2648  *   Free a MonoDynCallInfo structure.
2649  */
2650 void
2651 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2652 {
2653         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2654
2655         g_free (ainfo->cinfo);
2656         g_free (ainfo);
2657 }
2658
2659 #if !defined(__native_client__)
2660 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2661 #define GREG_TO_PTR(greg) (gpointer)(greg)
2662 #else
2663 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2664 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2665 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2666 #endif
2667
2668 /*
2669  * mono_arch_get_start_dyn_call:
2670  *
2671  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2672  * store the result into BUF.
2673  * ARGS should be an array of pointers pointing to the arguments.
2674  * RET should point to a memory buffer large enought to hold the result of the
2675  * call.
2676  * This function should be as fast as possible, any work which does not depend
2677  * on the actual values of the arguments should be done in
2678  * mono_arch_dyn_call_prepare ().
2679  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2680  * libffi.
2681  */
2682 void
2683 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2684 {
2685         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2686         DynCallArgs *p = (DynCallArgs*)buf;
2687         int arg_index, greg, i, pindex;
2688         MonoMethodSignature *sig = dinfo->sig;
2689
2690         g_assert (buf_len >= sizeof (DynCallArgs));
2691
2692         p->res = 0;
2693         p->ret = ret;
2694
2695         arg_index = 0;
2696         greg = 0;
2697         pindex = 0;
2698
2699         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2700                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2701                 if (!sig->hasthis)
2702                         pindex = 1;
2703         }
2704
2705         if (dinfo->cinfo->vtype_retaddr)
2706                 p->regs [greg ++] = PTR_TO_GREG(ret);
2707
2708         for (i = pindex; i < sig->param_count; i++) {
2709                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2710                 gpointer *arg = args [arg_index ++];
2711
2712                 if (t->byref) {
2713                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2714                         continue;
2715                 }
2716
2717                 switch (t->type) {
2718                 case MONO_TYPE_STRING:
2719                 case MONO_TYPE_CLASS:
2720                 case MONO_TYPE_ARRAY:
2721                 case MONO_TYPE_SZARRAY:
2722                 case MONO_TYPE_OBJECT:
2723                 case MONO_TYPE_PTR:
2724                 case MONO_TYPE_I:
2725                 case MONO_TYPE_U:
2726 #if !defined(__mono_ilp32__)
2727                 case MONO_TYPE_I8:
2728                 case MONO_TYPE_U8:
2729 #endif
2730                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2731                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2732                         break;
2733 #if defined(__mono_ilp32__)
2734                 case MONO_TYPE_I8:
2735                 case MONO_TYPE_U8:
2736                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2737                         p->regs [greg ++] = *(guint64*)(arg);
2738                         break;
2739 #endif
2740                 case MONO_TYPE_BOOLEAN:
2741                 case MONO_TYPE_U1:
2742                         p->regs [greg ++] = *(guint8*)(arg);
2743                         break;
2744                 case MONO_TYPE_I1:
2745                         p->regs [greg ++] = *(gint8*)(arg);
2746                         break;
2747                 case MONO_TYPE_I2:
2748                         p->regs [greg ++] = *(gint16*)(arg);
2749                         break;
2750                 case MONO_TYPE_U2:
2751                 case MONO_TYPE_CHAR:
2752                         p->regs [greg ++] = *(guint16*)(arg);
2753                         break;
2754                 case MONO_TYPE_I4:
2755                         p->regs [greg ++] = *(gint32*)(arg);
2756                         break;
2757                 case MONO_TYPE_U4:
2758                         p->regs [greg ++] = *(guint32*)(arg);
2759                         break;
2760                 case MONO_TYPE_GENERICINST:
2761                     if (MONO_TYPE_IS_REFERENCE (t)) {
2762                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2763                                 break;
2764                         } else {
2765                                 /* Fall through */
2766                         }
2767                 case MONO_TYPE_VALUETYPE: {
2768                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2769
2770                         g_assert (ainfo->storage == ArgValuetypeInReg);
2771                         if (ainfo->pair_storage [0] != ArgNone) {
2772                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2773                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2774                         }
2775                         if (ainfo->pair_storage [1] != ArgNone) {
2776                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2777                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2778                         }
2779                         break;
2780                 }
2781                 default:
2782                         g_assert_not_reached ();
2783                 }
2784         }
2785
2786         g_assert (greg <= PARAM_REGS);
2787 }
2788
2789 /*
2790  * mono_arch_finish_dyn_call:
2791  *
2792  *   Store the result of a dyn call into the return value buffer passed to
2793  * start_dyn_call ().
2794  * This function should be as fast as possible, any work which does not depend
2795  * on the actual values of the arguments should be done in
2796  * mono_arch_dyn_call_prepare ().
2797  */
2798 void
2799 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2800 {
2801         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2802         MonoMethodSignature *sig = dinfo->sig;
2803         guint8 *ret = ((DynCallArgs*)buf)->ret;
2804         mgreg_t res = ((DynCallArgs*)buf)->res;
2805         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2806
2807         switch (sig_ret->type) {
2808         case MONO_TYPE_VOID:
2809                 *(gpointer*)ret = NULL;
2810                 break;
2811         case MONO_TYPE_STRING:
2812         case MONO_TYPE_CLASS:
2813         case MONO_TYPE_ARRAY:
2814         case MONO_TYPE_SZARRAY:
2815         case MONO_TYPE_OBJECT:
2816         case MONO_TYPE_I:
2817         case MONO_TYPE_U:
2818         case MONO_TYPE_PTR:
2819                 *(gpointer*)ret = GREG_TO_PTR(res);
2820                 break;
2821         case MONO_TYPE_I1:
2822                 *(gint8*)ret = res;
2823                 break;
2824         case MONO_TYPE_U1:
2825         case MONO_TYPE_BOOLEAN:
2826                 *(guint8*)ret = res;
2827                 break;
2828         case MONO_TYPE_I2:
2829                 *(gint16*)ret = res;
2830                 break;
2831         case MONO_TYPE_U2:
2832         case MONO_TYPE_CHAR:
2833                 *(guint16*)ret = res;
2834                 break;
2835         case MONO_TYPE_I4:
2836                 *(gint32*)ret = res;
2837                 break;
2838         case MONO_TYPE_U4:
2839                 *(guint32*)ret = res;
2840                 break;
2841         case MONO_TYPE_I8:
2842                 *(gint64*)ret = res;
2843                 break;
2844         case MONO_TYPE_U8:
2845                 *(guint64*)ret = res;
2846                 break;
2847         case MONO_TYPE_GENERICINST:
2848                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2849                         *(gpointer*)ret = GREG_TO_PTR(res);
2850                         break;
2851                 } else {
2852                         /* Fall through */
2853                 }
2854         case MONO_TYPE_VALUETYPE:
2855                 if (dinfo->cinfo->vtype_retaddr) {
2856                         /* Nothing to do */
2857                 } else {
2858                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2859
2860                         g_assert (ainfo->storage == ArgValuetypeInReg);
2861
2862                         if (ainfo->pair_storage [0] != ArgNone) {
2863                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2864                                 ((mgreg_t*)ret)[0] = res;
2865                         }
2866
2867                         g_assert (ainfo->pair_storage [1] == ArgNone);
2868                 }
2869                 break;
2870         default:
2871                 g_assert_not_reached ();
2872         }
2873 }
2874
2875 /* emit an exception if condition is fail */
2876 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2877         do {                                                        \
2878                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2879                 if (tins == NULL) {                                                                             \
2880                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2881                                         MONO_PATCH_INFO_EXC, exc_name);  \
2882                         x86_branch32 (code, cond, 0, signed);               \
2883                 } else {        \
2884                         EMIT_COND_BRANCH (tins, cond, signed);  \
2885                 }                       \
2886         } while (0);
2887
2888 #define EMIT_FPCOMPARE(code) do { \
2889         amd64_fcompp (code); \
2890         amd64_fnstsw (code); \
2891 } while (0);
2892
2893 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2894     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2895         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2896         amd64_ ##op (code); \
2897         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2898         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2899 } while (0);
2900
2901 static guint8*
2902 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2903 {
2904         gboolean no_patch = FALSE;
2905
2906         /*
2907          * FIXME: Add support for thunks
2908          */
2909         {
2910                 gboolean near_call = FALSE;
2911
2912                 /*
2913                  * Indirect calls are expensive so try to make a near call if possible.
2914                  * The caller memory is allocated by the code manager so it is
2915                  * guaranteed to be at a 32 bit offset.
2916                  */
2917
2918                 if (patch_type != MONO_PATCH_INFO_ABS) {
2919                         /* The target is in memory allocated using the code manager */
2920                         near_call = TRUE;
2921
2922                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2923                                 if (((MonoMethod*)data)->klass->image->aot_module)
2924                                         /* The callee might be an AOT method */
2925                                         near_call = FALSE;
2926                                 if (((MonoMethod*)data)->dynamic)
2927                                         /* The target is in malloc-ed memory */
2928                                         near_call = FALSE;
2929                         }
2930
2931                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2932                                 /*
2933                                  * The call might go directly to a native function without
2934                                  * the wrapper.
2935                                  */
2936                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2937                                 if (mi) {
2938                                         gconstpointer target = mono_icall_get_wrapper (mi);
2939                                         if ((((guint64)target) >> 32) != 0)
2940                                                 near_call = FALSE;
2941                                 }
2942                         }
2943                 }
2944                 else {
2945                         MonoJumpInfo *jinfo = NULL;
2946
2947                         if (cfg->abs_patches)
2948                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2949                         if (jinfo) {
2950                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2951                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2952                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2953                                                 near_call = TRUE;
2954                                         no_patch = TRUE;
2955                                 } else {
2956                                         /*
2957                                          * This is not really an optimization, but required because the
2958                                          * generic class init trampolines use R11 to pass the vtable.
2959                                          */
2960                                         near_call = TRUE;
2961                                 }
2962                         } else {
2963                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2964                                 if (info) {
2965                                         if (info->func == info->wrapper) {
2966                                                 /* No wrapper */
2967                                                 if ((((guint64)info->func) >> 32) == 0)
2968                                                         near_call = TRUE;
2969                                         }
2970                                         else {
2971                                                 /* See the comment in mono_codegen () */
2972                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2973                                                         near_call = TRUE;
2974                                         }
2975                                 }
2976                                 else if ((((guint64)data) >> 32) == 0) {
2977                                         near_call = TRUE;
2978                                         no_patch = TRUE;
2979                                 }
2980                         }
2981                 }
2982
2983                 if (cfg->method->dynamic)
2984                         /* These methods are allocated using malloc */
2985                         near_call = FALSE;
2986
2987 #ifdef MONO_ARCH_NOMAP32BIT
2988                 near_call = FALSE;
2989 #endif
2990 #if defined(__native_client__)
2991                 /* Always use near_call == TRUE for Native Client */
2992                 near_call = TRUE;
2993 #endif
2994                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2995                 if (optimize_for_xen)
2996                         near_call = FALSE;
2997
2998                 if (cfg->compile_aot) {
2999                         near_call = TRUE;
3000                         no_patch = TRUE;
3001                 }
3002
3003                 if (near_call) {
3004                         /*
3005                          * Align the call displacement to an address divisible by 4 so it does
3006                          * not span cache lines. This is required for code patching to work on SMP
3007                          * systems.
3008                          */
3009                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3010                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3011                                 amd64_padding (code, pad_size);
3012                         }
3013                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3014                         amd64_call_code (code, 0);
3015                 }
3016                 else {
3017                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3018                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3019                         amd64_call_reg (code, GP_SCRATCH_REG);
3020                 }
3021         }
3022
3023         return code;
3024 }
3025
3026 static inline guint8*
3027 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3028 {
3029 #ifdef HOST_WIN32
3030         if (win64_adjust_stack)
3031                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3032 #endif
3033         code = emit_call_body (cfg, code, patch_type, data);
3034 #ifdef HOST_WIN32
3035         if (win64_adjust_stack)
3036                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3037 #endif
3038
3039         return code;
3040 }
3041
3042 static inline int
3043 store_membase_imm_to_store_membase_reg (int opcode)
3044 {
3045         switch (opcode) {
3046         case OP_STORE_MEMBASE_IMM:
3047                 return OP_STORE_MEMBASE_REG;
3048         case OP_STOREI4_MEMBASE_IMM:
3049                 return OP_STOREI4_MEMBASE_REG;
3050         case OP_STOREI8_MEMBASE_IMM:
3051                 return OP_STOREI8_MEMBASE_REG;
3052         }
3053
3054         return -1;
3055 }
3056
3057 #ifndef DISABLE_JIT
3058
3059 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3060
3061 /*
3062  * mono_arch_peephole_pass_1:
3063  *
3064  *   Perform peephole opts which should/can be performed before local regalloc
3065  */
3066 void
3067 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3068 {
3069         MonoInst *ins, *n;
3070
3071         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3072                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3073
3074                 switch (ins->opcode) {
3075                 case OP_ADD_IMM:
3076                 case OP_IADD_IMM:
3077                 case OP_LADD_IMM:
3078                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3079                                 /*
3080                                  * X86_LEA is like ADD, but doesn't have the
3081                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3082                                  * its operand to 64 bit.
3083                                  */
3084                                 ins->opcode = OP_X86_LEA_MEMBASE;
3085                                 ins->inst_basereg = ins->sreg1;
3086                         }
3087                         break;
3088                 case OP_LXOR:
3089                 case OP_IXOR:
3090                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3091                                 MonoInst *ins2;
3092
3093                                 /*
3094                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3095                                  * the latter has length 2-3 instead of 6 (reverse constant
3096                                  * propagation). These instruction sequences are very common
3097                                  * in the initlocals bblock.
3098                                  */
3099                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3100                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3101                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3102                                                 ins2->sreg1 = ins->dreg;
3103                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3104                                                 /* Continue */
3105                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3106                                                 NULLIFY_INS (ins2);
3107                                                 /* Continue */
3108                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3109                                                 /* Continue */
3110                                         } else {
3111                                                 break;
3112                                         }
3113                                 }
3114                         }
3115                         break;
3116                 case OP_COMPARE_IMM:
3117                 case OP_LCOMPARE_IMM:
3118                         /* OP_COMPARE_IMM (reg, 0)
3119                          * -->
3120                          * OP_AMD64_TEST_NULL (reg)
3121                          */
3122                         if (!ins->inst_imm)
3123                                 ins->opcode = OP_AMD64_TEST_NULL;
3124                         break;
3125                 case OP_ICOMPARE_IMM:
3126                         if (!ins->inst_imm)
3127                                 ins->opcode = OP_X86_TEST_NULL;
3128                         break;
3129                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3130                         /*
3131                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3132                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3133                          * -->
3134                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3135                          * OP_COMPARE_IMM reg, imm
3136                          *
3137                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3138                          */
3139                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3140                             ins->inst_basereg == last_ins->inst_destbasereg &&
3141                             ins->inst_offset == last_ins->inst_offset) {
3142                                         ins->opcode = OP_ICOMPARE_IMM;
3143                                         ins->sreg1 = last_ins->sreg1;
3144
3145                                         /* check if we can remove cmp reg,0 with test null */
3146                                         if (!ins->inst_imm)
3147                                                 ins->opcode = OP_X86_TEST_NULL;
3148                                 }
3149
3150                         break;
3151                 }
3152
3153                 mono_peephole_ins (bb, ins);
3154         }
3155 }
3156
3157 void
3158 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3159 {
3160         MonoInst *ins, *n;
3161
3162         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3163                 switch (ins->opcode) {
3164                 case OP_ICONST:
3165                 case OP_I8CONST: {
3166                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3167                         /* reg = 0 -> XOR (reg, reg) */
3168                         /* XOR sets cflags on x86, so we cant do it always */
3169                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3170                                 ins->opcode = OP_LXOR;
3171                                 ins->sreg1 = ins->dreg;
3172                                 ins->sreg2 = ins->dreg;
3173                                 /* Fall through */
3174                         } else {
3175                                 break;
3176                         }
3177                 }
3178                 case OP_LXOR:
3179                         /*
3180                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3181                          * 0 result into 64 bits.
3182                          */
3183                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3184                                 ins->opcode = OP_IXOR;
3185                         }
3186                         /* Fall through */
3187                 case OP_IXOR:
3188                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3189                                 MonoInst *ins2;
3190
3191                                 /*
3192                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3193                                  * the latter has length 2-3 instead of 6 (reverse constant
3194                                  * propagation). These instruction sequences are very common
3195                                  * in the initlocals bblock.
3196                                  */
3197                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3198                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3199                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3200                                                 ins2->sreg1 = ins->dreg;
3201                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3202                                                 /* Continue */
3203                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3204                                                 NULLIFY_INS (ins2);
3205                                                 /* Continue */
3206                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3207                                                 /* Continue */
3208                                         } else {
3209                                                 break;
3210                                         }
3211                                 }
3212                         }
3213                         break;
3214                 case OP_IADD_IMM:
3215                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3216                                 ins->opcode = OP_X86_INC_REG;
3217                         break;
3218                 case OP_ISUB_IMM:
3219                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3220                                 ins->opcode = OP_X86_DEC_REG;
3221                         break;
3222                 }
3223
3224                 mono_peephole_ins (bb, ins);
3225         }
3226 }
3227
3228 #define NEW_INS(cfg,ins,dest,op) do {   \
3229                 MONO_INST_NEW ((cfg), (dest), (op)); \
3230         (dest)->cil_code = (ins)->cil_code; \
3231         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3232         } while (0)
3233
3234 /*
3235  * mono_arch_lowering_pass:
3236  *
3237  *  Converts complex opcodes into simpler ones so that each IR instruction
3238  * corresponds to one machine instruction.
3239  */
3240 void
3241 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3242 {
3243         MonoInst *ins, *n, *temp;
3244
3245         /*
3246          * FIXME: Need to add more instructions, but the current machine
3247          * description can't model some parts of the composite instructions like
3248          * cdq.
3249          */
3250         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3251                 switch (ins->opcode) {
3252                 case OP_DIV_IMM:
3253                 case OP_REM_IMM:
3254                 case OP_IDIV_IMM:
3255                 case OP_IDIV_UN_IMM:
3256                 case OP_IREM_UN_IMM:
3257                 case OP_LREM_IMM:
3258                 case OP_IREM_IMM:
3259                         mono_decompose_op_imm (cfg, bb, ins);
3260                         break;
3261                 case OP_COMPARE_IMM:
3262                 case OP_LCOMPARE_IMM:
3263                         if (!amd64_is_imm32 (ins->inst_imm)) {
3264                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3265                                 temp->inst_c0 = ins->inst_imm;
3266                                 temp->dreg = mono_alloc_ireg (cfg);
3267                                 ins->opcode = OP_COMPARE;
3268                                 ins->sreg2 = temp->dreg;
3269                         }
3270                         break;
3271 #ifndef __mono_ilp32__
3272                 case OP_LOAD_MEMBASE:
3273 #endif
3274                 case OP_LOADI8_MEMBASE:
3275 #ifndef __native_client_codegen__
3276                 /*  Don't generate memindex opcodes (to simplify */
3277                 /*  read sandboxing) */
3278                         if (!amd64_is_imm32 (ins->inst_offset)) {
3279                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3280                                 temp->inst_c0 = ins->inst_offset;
3281                                 temp->dreg = mono_alloc_ireg (cfg);
3282                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3283                                 ins->inst_indexreg = temp->dreg;
3284                         }
3285 #endif
3286                         break;
3287 #ifndef __mono_ilp32__
3288                 case OP_STORE_MEMBASE_IMM:
3289 #endif
3290                 case OP_STOREI8_MEMBASE_IMM:
3291                         if (!amd64_is_imm32 (ins->inst_imm)) {
3292                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3293                                 temp->inst_c0 = ins->inst_imm;
3294                                 temp->dreg = mono_alloc_ireg (cfg);
3295                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3296                                 ins->sreg1 = temp->dreg;
3297                         }
3298                         break;
3299 #ifdef MONO_ARCH_SIMD_INTRINSICS
3300                 case OP_EXPAND_I1: {
3301                                 int temp_reg1 = mono_alloc_ireg (cfg);
3302                                 int temp_reg2 = mono_alloc_ireg (cfg);
3303                                 int original_reg = ins->sreg1;
3304
3305                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3306                                 temp->sreg1 = original_reg;
3307                                 temp->dreg = temp_reg1;
3308
3309                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3310                                 temp->sreg1 = temp_reg1;
3311                                 temp->dreg = temp_reg2;
3312                                 temp->inst_imm = 8;
3313
3314                                 NEW_INS (cfg, ins, temp, OP_LOR);
3315                                 temp->sreg1 = temp->dreg = temp_reg2;
3316                                 temp->sreg2 = temp_reg1;
3317
3318                                 ins->opcode = OP_EXPAND_I2;
3319                                 ins->sreg1 = temp_reg2;
3320                         }
3321                         break;
3322 #endif
3323                 default:
3324                         break;
3325                 }
3326         }
3327
3328         bb->max_vreg = cfg->next_vreg;
3329 }
3330
3331 static const int
3332 branch_cc_table [] = {
3333         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3334         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3335         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3336 };
3337
3338 /* Maps CMP_... constants to X86_CC_... constants */
3339 static const int
3340 cc_table [] = {
3341         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3342         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3343 };
3344
3345 static const int
3346 cc_signed_table [] = {
3347         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3348         FALSE, FALSE, FALSE, FALSE
3349 };
3350
3351 /*#include "cprop.c"*/
3352
3353 static unsigned char*
3354 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3355 {
3356         if (size == 8)
3357                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3358         else
3359                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3360
3361         if (size == 1)
3362                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3363         else if (size == 2)
3364                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3365         return code;
3366 }
3367
3368 static unsigned char*
3369 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3370 {
3371         int sreg = tree->sreg1;
3372         int need_touch = FALSE;
3373
3374 #if defined(HOST_WIN32)
3375         need_touch = TRUE;
3376 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3377         if (!tree->flags & MONO_INST_INIT)
3378                 need_touch = TRUE;
3379 #endif
3380
3381         if (need_touch) {
3382                 guint8* br[5];
3383
3384                 /*
3385                  * Under Windows:
3386                  * If requested stack size is larger than one page,
3387                  * perform stack-touch operation
3388                  */
3389                 /*
3390                  * Generate stack probe code.
3391                  * Under Windows, it is necessary to allocate one page at a time,
3392                  * "touching" stack after each successful sub-allocation. This is
3393                  * because of the way stack growth is implemented - there is a
3394                  * guard page before the lowest stack page that is currently commited.
3395                  * Stack normally grows sequentially so OS traps access to the
3396                  * guard page and commits more pages when needed.
3397                  */
3398                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3399                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3400
3401                 br[2] = code; /* loop */
3402                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3403                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3404                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3405                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3406                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3407                 amd64_patch (br[3], br[2]);
3408                 amd64_test_reg_reg (code, sreg, sreg);
3409                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3410                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3411
3412                 br[1] = code; x86_jump8 (code, 0);
3413
3414                 amd64_patch (br[0], code);
3415                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3416                 amd64_patch (br[1], code);
3417                 amd64_patch (br[4], code);
3418         }
3419         else
3420                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3421
3422         if (tree->flags & MONO_INST_INIT) {
3423                 int offset = 0;
3424                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3425                         amd64_push_reg (code, AMD64_RAX);
3426                         offset += 8;
3427                 }
3428                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3429                         amd64_push_reg (code, AMD64_RCX);
3430                         offset += 8;
3431                 }
3432                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3433                         amd64_push_reg (code, AMD64_RDI);
3434                         offset += 8;
3435                 }
3436
3437                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3438                 if (sreg != AMD64_RCX)
3439                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3440                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3441
3442                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3443                 if (cfg->param_area)
3444                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3445                 amd64_cld (code);
3446 #if defined(__default_codegen__)
3447                 amd64_prefix (code, X86_REP_PREFIX);
3448                 amd64_stosl (code);
3449 #elif defined(__native_client_codegen__)
3450                 /* NaCl stos pseudo-instruction */
3451                 amd64_codegen_pre(code);
3452                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3453                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3454                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3455                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3456                 amd64_prefix (code, X86_REP_PREFIX);
3457                 amd64_stosl (code);
3458                 amd64_codegen_post(code);
3459 #endif /* __native_client_codegen__ */
3460
3461                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3462                         amd64_pop_reg (code, AMD64_RDI);
3463                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3464                         amd64_pop_reg (code, AMD64_RCX);
3465                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3466                         amd64_pop_reg (code, AMD64_RAX);
3467         }
3468         return code;
3469 }
3470
3471 static guint8*
3472 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3473 {
3474         CallInfo *cinfo;
3475         guint32 quad;
3476
3477         /* Move return value to the target register */
3478         /* FIXME: do this in the local reg allocator */
3479         switch (ins->opcode) {
3480         case OP_CALL:
3481         case OP_CALL_REG:
3482         case OP_CALL_MEMBASE:
3483         case OP_LCALL:
3484         case OP_LCALL_REG:
3485         case OP_LCALL_MEMBASE:
3486                 g_assert (ins->dreg == AMD64_RAX);
3487                 break;
3488         case OP_FCALL:
3489         case OP_FCALL_REG:
3490         case OP_FCALL_MEMBASE:
3491                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3492                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3493                 }
3494                 else {
3495                         if (ins->dreg != AMD64_XMM0)
3496                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3497                 }
3498                 break;
3499         case OP_RCALL:
3500         case OP_RCALL_REG:
3501         case OP_RCALL_MEMBASE:
3502                 if (ins->dreg != AMD64_XMM0)
3503                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3504                 break;
3505         case OP_VCALL:
3506         case OP_VCALL_REG:
3507         case OP_VCALL_MEMBASE:
3508         case OP_VCALL2:
3509         case OP_VCALL2_REG:
3510         case OP_VCALL2_MEMBASE:
3511                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3512                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3513                         MonoInst *loc = cfg->arch.vret_addr_loc;
3514
3515                         /* Load the destination address */
3516                         g_assert (loc->opcode == OP_REGOFFSET);
3517                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3518
3519                         for (quad = 0; quad < 2; quad ++) {
3520                                 switch (cinfo->ret.pair_storage [quad]) {
3521                                 case ArgInIReg:
3522                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3523                                         break;
3524                                 case ArgInFloatSSEReg:
3525                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3526                                         break;
3527                                 case ArgInDoubleSSEReg:
3528                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3529                                         break;
3530                                 case ArgNone:
3531                                         break;
3532                                 default:
3533                                         NOT_IMPLEMENTED;
3534                                 }
3535                         }
3536                 }
3537                 break;
3538         }
3539
3540         return code;
3541 }
3542
3543 #endif /* DISABLE_JIT */
3544
3545 #ifdef __APPLE__
3546 static int tls_gs_offset;
3547 #endif
3548
3549 gboolean
3550 mono_amd64_have_tls_get (void)
3551 {
3552 #ifdef TARGET_MACH
3553         static gboolean have_tls_get = FALSE;
3554         static gboolean inited = FALSE;
3555         guint8 *ins;
3556
3557         if (inited)
3558                 return have_tls_get;
3559
3560         ins = (guint8*)pthread_getspecific;
3561
3562         /*
3563          * We're looking for these two instructions:
3564          *
3565          * mov    %gs:[offset](,%rdi,8),%rax
3566          * retq
3567          */
3568         have_tls_get = ins [0] == 0x65 &&
3569                        ins [1] == 0x48 &&
3570                        ins [2] == 0x8b &&
3571                        ins [3] == 0x04 &&
3572                        ins [4] == 0xfd &&
3573                        ins [6] == 0x00 &&
3574                        ins [7] == 0x00 &&
3575                        ins [8] == 0x00 &&
3576                        ins [9] == 0xc3;
3577
3578         inited = TRUE;
3579
3580         tls_gs_offset = ins[5];
3581
3582         return have_tls_get;
3583 #elif defined(TARGET_ANDROID)
3584         return FALSE;
3585 #else
3586         return TRUE;
3587 #endif
3588 }
3589
3590 int
3591 mono_amd64_get_tls_gs_offset (void)
3592 {
3593 #ifdef TARGET_OSX
3594         return tls_gs_offset;
3595 #else
3596         g_assert_not_reached ();
3597         return -1;
3598 #endif
3599 }
3600
3601 /*
3602  * mono_amd64_emit_tls_get:
3603  * @code: buffer to store code to
3604  * @dreg: hard register where to place the result
3605  * @tls_offset: offset info
3606  *
3607  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3608  * the dreg register the item in the thread local storage identified
3609  * by tls_offset.
3610  *
3611  * Returns: a pointer to the end of the stored code
3612  */
3613 guint8*
3614 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3615 {
3616 #ifdef HOST_WIN32
3617         if (tls_offset < 64) {
3618                 x86_prefix (code, X86_GS_PREFIX);
3619                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3620         } else {
3621                 guint8 *buf [16];
3622
3623                 g_assert (tls_offset < 0x440);
3624                 /* Load TEB->TlsExpansionSlots */
3625                 x86_prefix (code, X86_GS_PREFIX);
3626                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3627                 amd64_test_reg_reg (code, dreg, dreg);
3628                 buf [0] = code;
3629                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3630                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3631                 amd64_patch (buf [0], code);
3632         }
3633 #elif defined(__APPLE__)
3634         x86_prefix (code, X86_GS_PREFIX);
3635         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3636 #else
3637         if (optimize_for_xen) {
3638                 x86_prefix (code, X86_FS_PREFIX);
3639                 amd64_mov_reg_mem (code, dreg, 0, 8);
3640                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3641         } else {
3642                 x86_prefix (code, X86_FS_PREFIX);
3643                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3644         }
3645 #endif
3646         return code;
3647 }
3648
3649 static guint8*
3650 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3651 {
3652         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3653 #ifdef TARGET_OSX
3654         if (dreg != offset_reg)
3655                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3656         amd64_prefix (code, X86_GS_PREFIX);
3657         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3658 #elif defined(__linux__)
3659         int tmpreg = -1;
3660
3661         if (dreg == offset_reg) {
3662                 /* Use a temporary reg by saving it to the redzone */
3663                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3664                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3665                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3666                 offset_reg = tmpreg;
3667         }
3668         x86_prefix (code, X86_FS_PREFIX);
3669         amd64_mov_reg_mem (code, dreg, 0, 8);
3670         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3671         if (tmpreg != -1)
3672                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3673 #else
3674         g_assert_not_reached ();
3675 #endif
3676         return code;
3677 }
3678
3679 static guint8*
3680 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3681 {
3682 #ifdef HOST_WIN32
3683         g_assert_not_reached ();
3684 #elif defined(__APPLE__)
3685         x86_prefix (code, X86_GS_PREFIX);
3686         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3687 #else
3688         g_assert (!optimize_for_xen);
3689         x86_prefix (code, X86_FS_PREFIX);
3690         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3691 #endif
3692         return code;
3693 }
3694
3695 static guint8*
3696 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3697 {
3698         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3699 #ifdef HOST_WIN32
3700         g_assert_not_reached ();
3701 #elif defined(__APPLE__)
3702         x86_prefix (code, X86_GS_PREFIX);
3703         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3704 #else
3705         x86_prefix (code, X86_FS_PREFIX);
3706         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3707 #endif
3708         return code;
3709 }
3710
3711  /*
3712  * mono_arch_translate_tls_offset:
3713  *
3714  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3715  */
3716 int
3717 mono_arch_translate_tls_offset (int offset)
3718 {
3719 #ifdef __APPLE__
3720         return tls_gs_offset + (offset * 8);
3721 #else
3722         return offset;
3723 #endif
3724 }
3725
3726 /*
3727  * emit_setup_lmf:
3728  *
3729  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3730  */
3731 static guint8*
3732 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3733 {
3734         /*
3735          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3736          */
3737         /*
3738          * sp is saved right before calls but we need to save it here too so
3739          * async stack walks would work.
3740          */
3741         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3742         /* Save rbp */
3743         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3744         if (cfg->arch.omit_fp && cfa_offset != -1)
3745                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3746
3747         /* These can't contain refs */
3748         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3749         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3750         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3751         /* These are handled automatically by the stack marking code */
3752         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3753
3754         return code;
3755 }
3756
3757 #define REAL_PRINT_REG(text,reg) \
3758 mono_assert (reg >= 0); \
3759 amd64_push_reg (code, AMD64_RAX); \
3760 amd64_push_reg (code, AMD64_RDX); \
3761 amd64_push_reg (code, AMD64_RCX); \
3762 amd64_push_reg (code, reg); \
3763 amd64_push_imm (code, reg); \
3764 amd64_push_imm (code, text " %d %p\n"); \
3765 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3766 amd64_call_reg (code, AMD64_RAX); \
3767 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3768 amd64_pop_reg (code, AMD64_RCX); \
3769 amd64_pop_reg (code, AMD64_RDX); \
3770 amd64_pop_reg (code, AMD64_RAX);
3771
3772 /* benchmark and set based on cpu */
3773 #define LOOP_ALIGNMENT 8
3774 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3775
3776 #ifndef DISABLE_JIT
3777 void
3778 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3779 {
3780         MonoInst *ins;
3781         MonoCallInst *call;
3782         guint offset;
3783         guint8 *code = cfg->native_code + cfg->code_len;
3784         MonoInst *last_ins = NULL;
3785         guint last_offset = 0;
3786         int max_len;
3787
3788         /* Fix max_offset estimate for each successor bb */
3789         if (cfg->opt & MONO_OPT_BRANCH) {
3790                 int current_offset = cfg->code_len;
3791                 MonoBasicBlock *current_bb;
3792                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3793                         current_bb->max_offset = current_offset;
3794                         current_offset += current_bb->max_length;
3795                 }
3796         }
3797
3798         if (cfg->opt & MONO_OPT_LOOP) {
3799                 int pad, align = LOOP_ALIGNMENT;
3800                 /* set alignment depending on cpu */
3801                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3802                         pad = align - pad;
3803                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3804                         amd64_padding (code, pad);
3805                         cfg->code_len += pad;
3806                         bb->native_offset = cfg->code_len;
3807                 }
3808         }
3809
3810 #if defined(__native_client_codegen__)
3811         /* For Native Client, all indirect call/jump targets must be */
3812         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3813         /* indirectly as well.                                       */
3814         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3815                                       (bb->flags & BB_EXCEPTION_HANDLER);
3816
3817         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3818                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3819                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3820                 cfg->code_len += pad;
3821                 bb->native_offset = cfg->code_len;
3822         }
3823 #endif  /*__native_client_codegen__*/
3824
3825         if (cfg->verbose_level > 2)
3826                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3827
3828         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3829                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3830                 g_assert (!cfg->compile_aot);
3831
3832                 cov->data [bb->dfn].cil_code = bb->cil_code;
3833                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3834                 /* this is not thread save, but good enough */
3835                 amd64_inc_membase (code, AMD64_R11, 0);
3836         }
3837
3838         offset = code - cfg->native_code;
3839
3840         mono_debug_open_block (cfg, bb, offset);
3841
3842     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3843                 x86_breakpoint (code);
3844
3845         MONO_BB_FOR_EACH_INS (bb, ins) {
3846                 offset = code - cfg->native_code;
3847
3848                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3849
3850 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3851
3852                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3853                         cfg->code_size *= 2;
3854                         cfg->native_code = mono_realloc_native_code(cfg);
3855                         code = cfg->native_code + offset;
3856                         cfg->stat_code_reallocs++;
3857                 }
3858
3859                 if (cfg->debug_info)
3860                         mono_debug_record_line_number (cfg, ins, offset);
3861
3862                 switch (ins->opcode) {
3863                 case OP_BIGMUL:
3864                         amd64_mul_reg (code, ins->sreg2, TRUE);
3865                         break;
3866                 case OP_BIGMUL_UN:
3867                         amd64_mul_reg (code, ins->sreg2, FALSE);
3868                         break;
3869                 case OP_X86_SETEQ_MEMBASE:
3870                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3871                         break;
3872                 case OP_STOREI1_MEMBASE_IMM:
3873                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3874                         break;
3875                 case OP_STOREI2_MEMBASE_IMM:
3876                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3877                         break;
3878                 case OP_STOREI4_MEMBASE_IMM:
3879                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3880                         break;
3881                 case OP_STOREI1_MEMBASE_REG:
3882                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3883                         break;
3884                 case OP_STOREI2_MEMBASE_REG:
3885                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3886                         break;
3887                 /* In AMD64 NaCl, pointers are 4 bytes, */
3888                 /*  so STORE_* != STOREI8_*. Likewise below. */
3889                 case OP_STORE_MEMBASE_REG:
3890                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3891                         break;
3892                 case OP_STOREI8_MEMBASE_REG:
3893                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3894                         break;
3895                 case OP_STOREI4_MEMBASE_REG:
3896                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3897                         break;
3898                 case OP_STORE_MEMBASE_IMM:
3899 #ifndef __native_client_codegen__
3900                         /* In NaCl, this could be a PCONST type, which could */
3901                         /* mean a pointer type was copied directly into the  */
3902                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3903                         /* the value would be 0x00000000FFFFFFFF which is    */
3904                         /* not proper for an imm32 unless you cast it.       */
3905                         g_assert (amd64_is_imm32 (ins->inst_imm));
3906 #endif
3907                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3908                         break;
3909                 case OP_STOREI8_MEMBASE_IMM:
3910                         g_assert (amd64_is_imm32 (ins->inst_imm));
3911                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3912                         break;
3913                 case OP_LOAD_MEM:
3914 #ifdef __mono_ilp32__
3915                         /* In ILP32, pointers are 4 bytes, so separate these */
3916                         /* cases, use literal 8 below where we really want 8 */
3917                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3918                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3919                         break;
3920 #endif
3921                 case OP_LOADI8_MEM:
3922                         // FIXME: Decompose this earlier
3923                         if (amd64_is_imm32 (ins->inst_imm))
3924                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3925                         else {
3926                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3927                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3928                         }
3929                         break;
3930                 case OP_LOADI4_MEM:
3931                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3932                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3933                         break;
3934                 case OP_LOADU4_MEM:
3935                         // FIXME: Decompose this earlier
3936                         if (amd64_is_imm32 (ins->inst_imm))
3937                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3938                         else {
3939                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3940                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3941                         }
3942                         break;
3943                 case OP_LOADU1_MEM:
3944                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3945                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3946                         break;
3947                 case OP_LOADU2_MEM:
3948                         /* For NaCl, pointers are 4 bytes, so separate these */
3949                         /* cases, use literal 8 below where we really want 8 */
3950                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3951                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3952                         break;
3953                 case OP_LOAD_MEMBASE:
3954                         g_assert (amd64_is_imm32 (ins->inst_offset));
3955                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3956                         break;
3957                 case OP_LOADI8_MEMBASE:
3958                         /* Use literal 8 instead of sizeof pointer or */
3959                         /* register, we really want 8 for this opcode */
3960                         g_assert (amd64_is_imm32 (ins->inst_offset));
3961                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3962                         break;
3963                 case OP_LOADI4_MEMBASE:
3964                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3965                         break;
3966                 case OP_LOADU4_MEMBASE:
3967                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3968                         break;
3969                 case OP_LOADU1_MEMBASE:
3970                         /* The cpu zero extends the result into 64 bits */
3971                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3972                         break;
3973                 case OP_LOADI1_MEMBASE:
3974                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3975                         break;
3976                 case OP_LOADU2_MEMBASE:
3977                         /* The cpu zero extends the result into 64 bits */
3978                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3979                         break;
3980                 case OP_LOADI2_MEMBASE:
3981                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3982                         break;
3983                 case OP_AMD64_LOADI8_MEMINDEX:
3984                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3985                         break;
3986                 case OP_LCONV_TO_I1:
3987                 case OP_ICONV_TO_I1:
3988                 case OP_SEXT_I1:
3989                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3990                         break;
3991                 case OP_LCONV_TO_I2:
3992                 case OP_ICONV_TO_I2:
3993                 case OP_SEXT_I2:
3994                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3995                         break;
3996                 case OP_LCONV_TO_U1:
3997                 case OP_ICONV_TO_U1:
3998                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3999                         break;
4000                 case OP_LCONV_TO_U2:
4001                 case OP_ICONV_TO_U2:
4002                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4003                         break;
4004                 case OP_ZEXT_I4:
4005                         /* Clean out the upper word */
4006                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4007                         break;
4008                 case OP_SEXT_I4:
4009                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4010                         break;
4011                 case OP_COMPARE:
4012                 case OP_LCOMPARE:
4013                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4014                         break;
4015                 case OP_COMPARE_IMM:
4016 #if defined(__mono_ilp32__)
4017                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4018                         g_assert (amd64_is_imm32 (ins->inst_imm));
4019                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4020                         break;
4021 #endif
4022                 case OP_LCOMPARE_IMM:
4023                         g_assert (amd64_is_imm32 (ins->inst_imm));
4024                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4025                         break;
4026                 case OP_X86_COMPARE_REG_MEMBASE:
4027                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4028                         break;
4029                 case OP_X86_TEST_NULL:
4030                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4031                         break;
4032                 case OP_AMD64_TEST_NULL:
4033                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4034                         break;
4035
4036                 case OP_X86_ADD_REG_MEMBASE:
4037                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4038                         break;
4039                 case OP_X86_SUB_REG_MEMBASE:
4040                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4041                         break;
4042                 case OP_X86_AND_REG_MEMBASE:
4043                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4044                         break;
4045                 case OP_X86_OR_REG_MEMBASE:
4046                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4047                         break;
4048                 case OP_X86_XOR_REG_MEMBASE:
4049                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4050                         break;
4051
4052                 case OP_X86_ADD_MEMBASE_IMM:
4053                         /* FIXME: Make a 64 version too */
4054                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4055                         break;
4056                 case OP_X86_SUB_MEMBASE_IMM:
4057                         g_assert (amd64_is_imm32 (ins->inst_imm));
4058                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4059                         break;
4060                 case OP_X86_AND_MEMBASE_IMM:
4061                         g_assert (amd64_is_imm32 (ins->inst_imm));
4062                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4063                         break;
4064                 case OP_X86_OR_MEMBASE_IMM:
4065                         g_assert (amd64_is_imm32 (ins->inst_imm));
4066                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4067                         break;
4068                 case OP_X86_XOR_MEMBASE_IMM:
4069                         g_assert (amd64_is_imm32 (ins->inst_imm));
4070                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4071                         break;
4072                 case OP_X86_ADD_MEMBASE_REG:
4073                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4074                         break;
4075                 case OP_X86_SUB_MEMBASE_REG:
4076                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4077                         break;
4078                 case OP_X86_AND_MEMBASE_REG:
4079                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4080                         break;
4081                 case OP_X86_OR_MEMBASE_REG:
4082                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4083                         break;
4084                 case OP_X86_XOR_MEMBASE_REG:
4085                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4086                         break;
4087                 case OP_X86_INC_MEMBASE:
4088                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4089                         break;
4090                 case OP_X86_INC_REG:
4091                         amd64_inc_reg_size (code, ins->dreg, 4);
4092                         break;
4093                 case OP_X86_DEC_MEMBASE:
4094                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4095                         break;
4096                 case OP_X86_DEC_REG:
4097                         amd64_dec_reg_size (code, ins->dreg, 4);
4098                         break;
4099                 case OP_X86_MUL_REG_MEMBASE:
4100                 case OP_X86_MUL_MEMBASE_REG:
4101                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4102                         break;
4103                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4104                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4105                         break;
4106                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4107                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4108                         break;
4109                 case OP_AMD64_COMPARE_MEMBASE_REG:
4110                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4111                         break;
4112                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4113                         g_assert (amd64_is_imm32 (ins->inst_imm));
4114                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4115                         break;
4116                 case OP_X86_COMPARE_MEMBASE8_IMM:
4117                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4118                         break;
4119                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4120                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4121                         break;
4122                 case OP_AMD64_COMPARE_REG_MEMBASE:
4123                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4124                         break;
4125
4126                 case OP_AMD64_ADD_REG_MEMBASE:
4127                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4128                         break;
4129                 case OP_AMD64_SUB_REG_MEMBASE:
4130                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4131                         break;
4132                 case OP_AMD64_AND_REG_MEMBASE:
4133                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4134                         break;
4135                 case OP_AMD64_OR_REG_MEMBASE:
4136                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4137                         break;
4138                 case OP_AMD64_XOR_REG_MEMBASE:
4139                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4140                         break;
4141
4142                 case OP_AMD64_ADD_MEMBASE_REG:
4143                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4144                         break;
4145                 case OP_AMD64_SUB_MEMBASE_REG:
4146                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4147                         break;
4148                 case OP_AMD64_AND_MEMBASE_REG:
4149                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4150                         break;
4151                 case OP_AMD64_OR_MEMBASE_REG:
4152                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4153                         break;
4154                 case OP_AMD64_XOR_MEMBASE_REG:
4155                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4156                         break;
4157
4158                 case OP_AMD64_ADD_MEMBASE_IMM:
4159                         g_assert (amd64_is_imm32 (ins->inst_imm));
4160                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4161                         break;
4162                 case OP_AMD64_SUB_MEMBASE_IMM:
4163                         g_assert (amd64_is_imm32 (ins->inst_imm));
4164                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4165                         break;
4166                 case OP_AMD64_AND_MEMBASE_IMM:
4167                         g_assert (amd64_is_imm32 (ins->inst_imm));
4168                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4169                         break;
4170                 case OP_AMD64_OR_MEMBASE_IMM:
4171                         g_assert (amd64_is_imm32 (ins->inst_imm));
4172                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4173                         break;
4174                 case OP_AMD64_XOR_MEMBASE_IMM:
4175                         g_assert (amd64_is_imm32 (ins->inst_imm));
4176                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4177                         break;
4178
4179                 case OP_BREAK:
4180                         amd64_breakpoint (code);
4181                         break;
4182                 case OP_RELAXED_NOP:
4183                         x86_prefix (code, X86_REP_PREFIX);
4184                         x86_nop (code);
4185                         break;
4186                 case OP_HARD_NOP:
4187                         x86_nop (code);
4188                         break;
4189                 case OP_NOP:
4190                 case OP_DUMMY_USE:
4191                 case OP_DUMMY_STORE:
4192                 case OP_DUMMY_ICONST:
4193                 case OP_DUMMY_R8CONST:
4194                 case OP_NOT_REACHED:
4195                 case OP_NOT_NULL:
4196                         break;
4197                 case OP_IL_SEQ_POINT:
4198                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4199                         break;
4200                 case OP_SEQ_POINT: {
4201                         int i;
4202
4203                         /*
4204                          * Read from the single stepping trigger page. This will cause a
4205                          * SIGSEGV when single stepping is enabled.
4206                          * We do this _before_ the breakpoint, so single stepping after
4207                          * a breakpoint is hit will step to the next IL offset.
4208                          */
4209                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4210                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4211
4212                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4213                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4214                         }
4215
4216                         /*
4217                          * This is the address which is saved in seq points,
4218                          */
4219                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4220
4221                         if (cfg->compile_aot) {
4222                                 guint32 offset = code - cfg->native_code;
4223                                 guint32 val;
4224                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4225
4226                                 /* Load info var */
4227                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4228                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4229                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4230                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4231                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4232                         } else {
4233                                 /*
4234                                  * A placeholder for a possible breakpoint inserted by
4235                                  * mono_arch_set_breakpoint ().
4236                                  */
4237                                 for (i = 0; i < breakpoint_size; ++i)
4238                                         x86_nop (code);
4239                         }
4240                         /*
4241                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4242                          * to another IL offset.
4243                          */
4244                         x86_nop (code);
4245                         break;
4246                 }
4247                 case OP_ADDCC:
4248                 case OP_LADDCC:
4249                 case OP_LADD:
4250                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4251                         break;
4252                 case OP_ADC:
4253                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4254                         break;
4255                 case OP_ADD_IMM:
4256                 case OP_LADD_IMM:
4257                         g_assert (amd64_is_imm32 (ins->inst_imm));
4258                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4259                         break;
4260                 case OP_ADC_IMM:
4261                         g_assert (amd64_is_imm32 (ins->inst_imm));
4262                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4263                         break;
4264                 case OP_SUBCC:
4265                 case OP_LSUBCC:
4266                 case OP_LSUB:
4267                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4268                         break;
4269                 case OP_SBB:
4270                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4271                         break;
4272                 case OP_SUB_IMM:
4273                 case OP_LSUB_IMM:
4274                         g_assert (amd64_is_imm32 (ins->inst_imm));
4275                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4276                         break;
4277                 case OP_SBB_IMM:
4278                         g_assert (amd64_is_imm32 (ins->inst_imm));
4279                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4280                         break;
4281                 case OP_LAND:
4282                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4283                         break;
4284                 case OP_AND_IMM:
4285                 case OP_LAND_IMM:
4286                         g_assert (amd64_is_imm32 (ins->inst_imm));
4287                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4288                         break;
4289                 case OP_LMUL:
4290                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4291                         break;
4292                 case OP_MUL_IMM:
4293                 case OP_LMUL_IMM:
4294                 case OP_IMUL_IMM: {
4295                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4296
4297                         switch (ins->inst_imm) {
4298                         case 2:
4299                                 /* MOV r1, r2 */
4300                                 /* ADD r1, r1 */
4301                                 if (ins->dreg != ins->sreg1)
4302                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4303                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4304                                 break;
4305                         case 3:
4306                                 /* LEA r1, [r2 + r2*2] */
4307                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4308                                 break;
4309                         case 5:
4310                                 /* LEA r1, [r2 + r2*4] */
4311                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4312                                 break;
4313                         case 6:
4314                                 /* LEA r1, [r2 + r2*2] */
4315                                 /* ADD r1, r1          */
4316                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4317                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4318                                 break;
4319                         case 9:
4320                                 /* LEA r1, [r2 + r2*8] */
4321                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4322                                 break;
4323                         case 10:
4324                                 /* LEA r1, [r2 + r2*4] */
4325                                 /* ADD r1, r1          */
4326                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4327                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4328                                 break;
4329                         case 12:
4330                                 /* LEA r1, [r2 + r2*2] */
4331                                 /* SHL r1, 2           */
4332                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4333                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4334                                 break;
4335                         case 25:
4336                                 /* LEA r1, [r2 + r2*4] */
4337                                 /* LEA r1, [r1 + r1*4] */
4338                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4339                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4340                                 break;
4341                         case 100:
4342                                 /* LEA r1, [r2 + r2*4] */
4343                                 /* SHL r1, 2           */
4344                                 /* LEA r1, [r1 + r1*4] */
4345                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4346                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4347                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4348                                 break;
4349                         default:
4350                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4351                                 break;
4352                         }
4353                         break;
4354                 }
4355                 case OP_LDIV:
4356                 case OP_LREM:
4357 #if defined( __native_client_codegen__ )
4358                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4359                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4360 #endif
4361                         /* Regalloc magic makes the div/rem cases the same */
4362                         if (ins->sreg2 == AMD64_RDX) {
4363                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4364                                 amd64_cdq (code);
4365                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4366                         } else {
4367                                 amd64_cdq (code);
4368                                 amd64_div_reg (code, ins->sreg2, TRUE);
4369                         }
4370                         break;
4371                 case OP_LDIV_UN:
4372                 case OP_LREM_UN:
4373 #if defined( __native_client_codegen__ )
4374                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4375                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4376 #endif
4377                         if (ins->sreg2 == AMD64_RDX) {
4378                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4379                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4380                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4381                         } else {
4382                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4383                                 amd64_div_reg (code, ins->sreg2, FALSE);
4384                         }
4385                         break;
4386                 case OP_IDIV:
4387                 case OP_IREM:
4388 #if defined( __native_client_codegen__ )
4389                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4390                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4391 #endif
4392                         if (ins->sreg2 == AMD64_RDX) {
4393                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4394                                 amd64_cdq_size (code, 4);
4395                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4396                         } else {
4397                                 amd64_cdq_size (code, 4);
4398                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4399                         }
4400                         break;
4401                 case OP_IDIV_UN:
4402                 case OP_IREM_UN:
4403 #if defined( __native_client_codegen__ )
4404                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4405                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4406 #endif
4407                         if (ins->sreg2 == AMD64_RDX) {
4408                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4409                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4410                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4411                         } else {
4412                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4413                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4414                         }
4415                         break;
4416                 case OP_LMUL_OVF:
4417                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4418                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4419                         break;
4420                 case OP_LOR:
4421                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4422                         break;
4423                 case OP_OR_IMM:
4424                 case OP_LOR_IMM:
4425                         g_assert (amd64_is_imm32 (ins->inst_imm));
4426                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4427                         break;
4428                 case OP_LXOR:
4429                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4430                         break;
4431                 case OP_XOR_IMM:
4432                 case OP_LXOR_IMM:
4433                         g_assert (amd64_is_imm32 (ins->inst_imm));
4434                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4435                         break;
4436                 case OP_LSHL:
4437                         g_assert (ins->sreg2 == AMD64_RCX);
4438                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4439                         break;
4440                 case OP_LSHR:
4441                         g_assert (ins->sreg2 == AMD64_RCX);
4442                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4443                         break;
4444                 case OP_SHR_IMM:
4445                         g_assert (amd64_is_imm32 (ins->inst_imm));
4446                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4447                         break;
4448                 case OP_LSHR_IMM:
4449                         g_assert (amd64_is_imm32 (ins->inst_imm));
4450                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4451                         break;
4452                 case OP_SHR_UN_IMM:
4453                         g_assert (amd64_is_imm32 (ins->inst_imm));
4454                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4455                         break;
4456                 case OP_LSHR_UN_IMM:
4457                         g_assert (amd64_is_imm32 (ins->inst_imm));
4458                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4459                         break;
4460                 case OP_LSHR_UN:
4461                         g_assert (ins->sreg2 == AMD64_RCX);
4462                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4463                         break;
4464                 case OP_SHL_IMM:
4465                         g_assert (amd64_is_imm32 (ins->inst_imm));
4466                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4467                         break;
4468                 case OP_LSHL_IMM:
4469                         g_assert (amd64_is_imm32 (ins->inst_imm));
4470                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4471                         break;
4472
4473                 case OP_IADDCC:
4474                 case OP_IADD:
4475                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4476                         break;
4477                 case OP_IADC:
4478                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4479                         break;
4480                 case OP_IADD_IMM:
4481                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4482                         break;
4483                 case OP_IADC_IMM:
4484                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4485                         break;
4486                 case OP_ISUBCC:
4487                 case OP_ISUB:
4488                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4489                         break;
4490                 case OP_ISBB:
4491                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4492                         break;
4493                 case OP_ISUB_IMM:
4494                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4495                         break;
4496                 case OP_ISBB_IMM:
4497                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4498                         break;
4499                 case OP_IAND:
4500                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4501                         break;
4502                 case OP_IAND_IMM:
4503                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4504                         break;
4505                 case OP_IOR:
4506                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4507                         break;
4508                 case OP_IOR_IMM:
4509                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4510                         break;
4511                 case OP_IXOR:
4512                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4513                         break;
4514                 case OP_IXOR_IMM:
4515                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4516                         break;
4517                 case OP_INEG:
4518                         amd64_neg_reg_size (code, ins->sreg1, 4);
4519                         break;
4520                 case OP_INOT:
4521                         amd64_not_reg_size (code, ins->sreg1, 4);
4522                         break;
4523                 case OP_ISHL:
4524                         g_assert (ins->sreg2 == AMD64_RCX);
4525                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4526                         break;
4527                 case OP_ISHR:
4528                         g_assert (ins->sreg2 == AMD64_RCX);
4529                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4530                         break;
4531                 case OP_ISHR_IMM:
4532                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4533                         break;
4534                 case OP_ISHR_UN_IMM:
4535                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4536                         break;
4537                 case OP_ISHR_UN:
4538                         g_assert (ins->sreg2 == AMD64_RCX);
4539                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4540                         break;
4541                 case OP_ISHL_IMM:
4542                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4543                         break;
4544                 case OP_IMUL:
4545                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4546                         break;
4547                 case OP_IMUL_OVF:
4548                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4549                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4550                         break;
4551                 case OP_IMUL_OVF_UN:
4552                 case OP_LMUL_OVF_UN: {
4553                         /* the mul operation and the exception check should most likely be split */
4554                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4555                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4556                         /*g_assert (ins->sreg2 == X86_EAX);
4557                         g_assert (ins->dreg == X86_EAX);*/
4558                         if (ins->sreg2 == X86_EAX) {
4559                                 non_eax_reg = ins->sreg1;
4560                         } else if (ins->sreg1 == X86_EAX) {
4561                                 non_eax_reg = ins->sreg2;
4562                         } else {
4563                                 /* no need to save since we're going to store to it anyway */
4564                                 if (ins->dreg != X86_EAX) {
4565                                         saved_eax = TRUE;
4566                                         amd64_push_reg (code, X86_EAX);
4567                                 }
4568                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4569                                 non_eax_reg = ins->sreg2;
4570                         }
4571                         if (ins->dreg == X86_EDX) {
4572                                 if (!saved_eax) {
4573                                         saved_eax = TRUE;
4574                                         amd64_push_reg (code, X86_EAX);
4575                                 }
4576                         } else {
4577                                 saved_edx = TRUE;
4578                                 amd64_push_reg (code, X86_EDX);
4579                         }
4580                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4581                         /* save before the check since pop and mov don't change the flags */
4582                         if (ins->dreg != X86_EAX)
4583                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4584                         if (saved_edx)
4585                                 amd64_pop_reg (code, X86_EDX);
4586                         if (saved_eax)
4587                                 amd64_pop_reg (code, X86_EAX);
4588                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4589                         break;
4590                 }
4591                 case OP_ICOMPARE:
4592                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4593                         break;
4594                 case OP_ICOMPARE_IMM:
4595                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4596                         break;
4597                 case OP_IBEQ:
4598                 case OP_IBLT:
4599                 case OP_IBGT:
4600                 case OP_IBGE:
4601                 case OP_IBLE:
4602                 case OP_LBEQ:
4603                 case OP_LBLT:
4604                 case OP_LBGT:
4605                 case OP_LBGE:
4606                 case OP_LBLE:
4607                 case OP_IBNE_UN:
4608                 case OP_IBLT_UN:
4609                 case OP_IBGT_UN:
4610                 case OP_IBGE_UN:
4611                 case OP_IBLE_UN:
4612                 case OP_LBNE_UN:
4613                 case OP_LBLT_UN:
4614                 case OP_LBGT_UN:
4615                 case OP_LBGE_UN:
4616                 case OP_LBLE_UN:
4617                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4618                         break;
4619
4620                 case OP_CMOV_IEQ:
4621                 case OP_CMOV_IGE:
4622                 case OP_CMOV_IGT:
4623                 case OP_CMOV_ILE:
4624                 case OP_CMOV_ILT:
4625                 case OP_CMOV_INE_UN:
4626                 case OP_CMOV_IGE_UN:
4627                 case OP_CMOV_IGT_UN:
4628                 case OP_CMOV_ILE_UN:
4629                 case OP_CMOV_ILT_UN:
4630                 case OP_CMOV_LEQ:
4631                 case OP_CMOV_LGE:
4632                 case OP_CMOV_LGT:
4633                 case OP_CMOV_LLE:
4634                 case OP_CMOV_LLT:
4635                 case OP_CMOV_LNE_UN:
4636                 case OP_CMOV_LGE_UN:
4637                 case OP_CMOV_LGT_UN:
4638                 case OP_CMOV_LLE_UN:
4639                 case OP_CMOV_LLT_UN:
4640                         g_assert (ins->dreg == ins->sreg1);
4641                         /* This needs to operate on 64 bit values */
4642                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4643                         break;
4644
4645                 case OP_LNOT:
4646                         amd64_not_reg (code, ins->sreg1);
4647                         break;
4648                 case OP_LNEG:
4649                         amd64_neg_reg (code, ins->sreg1);
4650                         break;
4651
4652                 case OP_ICONST:
4653                 case OP_I8CONST:
4654                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4655                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4656                         else
4657                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4658                         break;
4659                 case OP_AOTCONST:
4660                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4661                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4662                         break;
4663                 case OP_JUMP_TABLE:
4664                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4665                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4666                         break;
4667                 case OP_MOVE:
4668                         if (ins->dreg != ins->sreg1)
4669                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4670                         break;
4671                 case OP_AMD64_SET_XMMREG_R4: {
4672                         if (cfg->r4fp) {
4673                                 if (ins->dreg != ins->sreg1)
4674                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4675                         } else {
4676                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4677                         }
4678                         break;
4679                 }
4680                 case OP_AMD64_SET_XMMREG_R8: {
4681                         if (ins->dreg != ins->sreg1)
4682                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4683                         break;
4684                 }
4685                 case OP_TAILCALL: {
4686                         MonoCallInst *call = (MonoCallInst*)ins;
4687                         int i, save_area_offset;
4688
4689                         g_assert (!cfg->method->save_lmf);
4690
4691                         /* Restore callee saved registers */
4692                         save_area_offset = cfg->arch.reg_save_area_offset;
4693                         for (i = 0; i < AMD64_NREG; ++i)
4694                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4695                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4696                                         save_area_offset += 8;
4697                                 }
4698
4699                         if (cfg->arch.omit_fp) {
4700                                 if (cfg->arch.stack_alloc_size)
4701                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4702                                 // FIXME:
4703                                 if (call->stack_usage)
4704                                         NOT_IMPLEMENTED;
4705                         } else {
4706                                 /* Copy arguments on the stack to our argument area */
4707                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4708                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4709                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4710                                 }
4711
4712                                 amd64_leave (code);
4713                         }
4714
4715                         offset = code - cfg->native_code;
4716                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4717                         if (cfg->compile_aot)
4718                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4719                         else
4720                                 amd64_set_reg_template (code, AMD64_R11);
4721                         amd64_jump_reg (code, AMD64_R11);
4722                         ins->flags |= MONO_INST_GC_CALLSITE;
4723                         ins->backend.pc_offset = code - cfg->native_code;
4724                         break;
4725                 }
4726                 case OP_CHECK_THIS:
4727                         /* ensure ins->sreg1 is not NULL */
4728                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4729                         break;
4730                 case OP_ARGLIST: {
4731                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4732                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4733                         break;
4734                 }
4735                 case OP_CALL:
4736                 case OP_FCALL:
4737                 case OP_RCALL:
4738                 case OP_LCALL:
4739                 case OP_VCALL:
4740                 case OP_VCALL2:
4741                 case OP_VOIDCALL:
4742                         call = (MonoCallInst*)ins;
4743                         /*
4744                          * The AMD64 ABI forces callers to know about varargs.
4745                          */
4746                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4747                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4748                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4749                                 /*
4750                                  * Since the unmanaged calling convention doesn't contain a
4751                                  * 'vararg' entry, we have to treat every pinvoke call as a
4752                                  * potential vararg call.
4753                                  */
4754                                 guint32 nregs, i;
4755                                 nregs = 0;
4756                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4757                                         if (call->used_fregs & (1 << i))
4758                                                 nregs ++;
4759                                 if (!nregs)
4760                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4761                                 else
4762                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4763                         }
4764
4765                         if (ins->flags & MONO_INST_HAS_METHOD)
4766                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4767                         else
4768                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4769                         ins->flags |= MONO_INST_GC_CALLSITE;
4770                         ins->backend.pc_offset = code - cfg->native_code;
4771                         code = emit_move_return_value (cfg, ins, code);
4772                         break;
4773                 case OP_FCALL_REG:
4774                 case OP_RCALL_REG:
4775                 case OP_LCALL_REG:
4776                 case OP_VCALL_REG:
4777                 case OP_VCALL2_REG:
4778                 case OP_VOIDCALL_REG:
4779                 case OP_CALL_REG:
4780                         call = (MonoCallInst*)ins;
4781
4782                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4783                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4784                                 ins->sreg1 = AMD64_R11;
4785                         }
4786
4787                         /*
4788                          * The AMD64 ABI forces callers to know about varargs.
4789                          */
4790                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4791                                 if (ins->sreg1 == AMD64_RAX) {
4792                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4793                                         ins->sreg1 = AMD64_R11;
4794                                 }
4795                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4796                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4797                                 /*
4798                                  * Since the unmanaged calling convention doesn't contain a
4799                                  * 'vararg' entry, we have to treat every pinvoke call as a
4800                                  * potential vararg call.
4801                                  */
4802                                 guint32 nregs, i;
4803                                 nregs = 0;
4804                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4805                                         if (call->used_fregs & (1 << i))
4806                                                 nregs ++;
4807                                 if (ins->sreg1 == AMD64_RAX) {
4808                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4809                                         ins->sreg1 = AMD64_R11;
4810                                 }
4811                                 if (!nregs)
4812                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4813                                 else
4814                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4815                         }
4816
4817                         amd64_call_reg (code, ins->sreg1);
4818                         ins->flags |= MONO_INST_GC_CALLSITE;
4819                         ins->backend.pc_offset = code - cfg->native_code;
4820                         code = emit_move_return_value (cfg, ins, code);
4821                         break;
4822                 case OP_FCALL_MEMBASE:
4823                 case OP_RCALL_MEMBASE:
4824                 case OP_LCALL_MEMBASE:
4825                 case OP_VCALL_MEMBASE:
4826                 case OP_VCALL2_MEMBASE:
4827                 case OP_VOIDCALL_MEMBASE:
4828                 case OP_CALL_MEMBASE:
4829                         call = (MonoCallInst*)ins;
4830
4831                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4832                         ins->flags |= MONO_INST_GC_CALLSITE;
4833                         ins->backend.pc_offset = code - cfg->native_code;
4834                         code = emit_move_return_value (cfg, ins, code);
4835                         break;
4836                 case OP_DYN_CALL: {
4837                         int i;
4838                         MonoInst *var = cfg->dyn_call_var;
4839
4840                         g_assert (var->opcode == OP_REGOFFSET);
4841
4842                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4843                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4844                         /* r10 = ftn */
4845                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4846
4847                         /* Save args buffer */
4848                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4849
4850                         /* Set argument registers */
4851                         for (i = 0; i < PARAM_REGS; ++i)
4852                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4853
4854                         /* Make the call */
4855                         amd64_call_reg (code, AMD64_R10);
4856
4857                         ins->flags |= MONO_INST_GC_CALLSITE;
4858                         ins->backend.pc_offset = code - cfg->native_code;
4859
4860                         /* Save result */
4861                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4862                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4863                         break;
4864                 }
4865                 case OP_AMD64_SAVE_SP_TO_LMF: {
4866                         MonoInst *lmf_var = cfg->lmf_var;
4867                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4868                         break;
4869                 }
4870                 case OP_X86_PUSH:
4871                         g_assert_not_reached ();
4872                         amd64_push_reg (code, ins->sreg1);
4873                         break;
4874                 case OP_X86_PUSH_IMM:
4875                         g_assert_not_reached ();
4876                         g_assert (amd64_is_imm32 (ins->inst_imm));
4877                         amd64_push_imm (code, ins->inst_imm);
4878                         break;
4879                 case OP_X86_PUSH_MEMBASE:
4880                         g_assert_not_reached ();
4881                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4882                         break;
4883                 case OP_X86_PUSH_OBJ: {
4884                         int size = ALIGN_TO (ins->inst_imm, 8);
4885
4886                         g_assert_not_reached ();
4887
4888                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4889                         amd64_push_reg (code, AMD64_RDI);
4890                         amd64_push_reg (code, AMD64_RSI);
4891                         amd64_push_reg (code, AMD64_RCX);
4892                         if (ins->inst_offset)
4893                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4894                         else
4895                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4896                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4897                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4898                         amd64_cld (code);
4899                         amd64_prefix (code, X86_REP_PREFIX);
4900                         amd64_movsd (code);
4901                         amd64_pop_reg (code, AMD64_RCX);
4902                         amd64_pop_reg (code, AMD64_RSI);
4903                         amd64_pop_reg (code, AMD64_RDI);
4904                         break;
4905                 }
4906                 case OP_X86_LEA:
4907                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4908                         break;
4909                 case OP_X86_LEA_MEMBASE:
4910                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4911                         break;
4912                 case OP_X86_XCHG:
4913                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4914                         break;
4915                 case OP_LOCALLOC:
4916                         /* keep alignment */
4917                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4918                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4919                         code = mono_emit_stack_alloc (cfg, code, ins);
4920                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4921                         if (cfg->param_area)
4922                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4923                         break;
4924                 case OP_LOCALLOC_IMM: {
4925                         guint32 size = ins->inst_imm;
4926                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4927
4928                         if (ins->flags & MONO_INST_INIT) {
4929                                 if (size < 64) {
4930                                         int i;
4931
4932                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4933                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4934
4935                                         for (i = 0; i < size; i += 8)
4936                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4937                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4938                                 } else {
4939                                         amd64_mov_reg_imm (code, ins->dreg, size);
4940                                         ins->sreg1 = ins->dreg;
4941
4942                                         code = mono_emit_stack_alloc (cfg, code, ins);
4943                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4944                                 }
4945                         } else {
4946                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4947                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4948                         }
4949                         if (cfg->param_area)
4950                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4951                         break;
4952                 }
4953                 case OP_THROW: {
4954                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4955                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4956                                              (gpointer)"mono_arch_throw_exception", FALSE);
4957                         ins->flags |= MONO_INST_GC_CALLSITE;
4958                         ins->backend.pc_offset = code - cfg->native_code;
4959                         break;
4960                 }
4961                 case OP_RETHROW: {
4962                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4963                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4964                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4965                         ins->flags |= MONO_INST_GC_CALLSITE;
4966                         ins->backend.pc_offset = code - cfg->native_code;
4967                         break;
4968                 }
4969                 case OP_CALL_HANDLER:
4970                         /* Align stack */
4971                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4972                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4973                         amd64_call_imm (code, 0);
4974                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4975                         /* Restore stack alignment */
4976                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4977                         break;
4978                 case OP_START_HANDLER: {
4979                         /* Even though we're saving RSP, use sizeof */
4980                         /* gpointer because spvar is of type IntPtr */
4981                         /* see: mono_create_spvar_for_region */
4982                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4983                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4984
4985                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4986                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4987                                 cfg->param_area) {
4988                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4989                         }
4990                         break;
4991                 }
4992                 case OP_ENDFINALLY: {
4993                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4994                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4995                         amd64_ret (code);
4996                         break;
4997                 }
4998                 case OP_ENDFILTER: {
4999                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5000                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5001                         /* The local allocator will put the result into RAX */
5002                         amd64_ret (code);
5003                         break;
5004                 }
5005
5006                 case OP_LABEL:
5007                         ins->inst_c0 = code - cfg->native_code;
5008                         break;
5009                 case OP_BR:
5010                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5011                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5012                         //break;
5013                                 if (ins->inst_target_bb->native_offset) {
5014                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5015                                 } else {
5016                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5017                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5018                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5019                                                 x86_jump8 (code, 0);
5020                                         else
5021                                                 x86_jump32 (code, 0);
5022                         }
5023                         break;
5024                 case OP_BR_REG:
5025                         amd64_jump_reg (code, ins->sreg1);
5026                         break;
5027                 case OP_ICNEQ:
5028                 case OP_ICGE:
5029                 case OP_ICLE:
5030                 case OP_ICGE_UN:
5031                 case OP_ICLE_UN:
5032
5033                 case OP_CEQ:
5034                 case OP_LCEQ:
5035                 case OP_ICEQ:
5036                 case OP_CLT:
5037                 case OP_LCLT:
5038                 case OP_ICLT:
5039                 case OP_CGT:
5040                 case OP_ICGT:
5041                 case OP_LCGT:
5042                 case OP_CLT_UN:
5043                 case OP_LCLT_UN:
5044                 case OP_ICLT_UN:
5045                 case OP_CGT_UN:
5046                 case OP_LCGT_UN:
5047                 case OP_ICGT_UN:
5048                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5049                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5050                         break;
5051                 case OP_COND_EXC_EQ:
5052                 case OP_COND_EXC_NE_UN:
5053                 case OP_COND_EXC_LT:
5054                 case OP_COND_EXC_LT_UN:
5055                 case OP_COND_EXC_GT:
5056                 case OP_COND_EXC_GT_UN:
5057                 case OP_COND_EXC_GE:
5058                 case OP_COND_EXC_GE_UN:
5059                 case OP_COND_EXC_LE:
5060                 case OP_COND_EXC_LE_UN:
5061                 case OP_COND_EXC_IEQ:
5062                 case OP_COND_EXC_INE_UN:
5063                 case OP_COND_EXC_ILT:
5064                 case OP_COND_EXC_ILT_UN:
5065                 case OP_COND_EXC_IGT:
5066                 case OP_COND_EXC_IGT_UN:
5067                 case OP_COND_EXC_IGE:
5068                 case OP_COND_EXC_IGE_UN:
5069                 case OP_COND_EXC_ILE:
5070                 case OP_COND_EXC_ILE_UN:
5071                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5072                         break;
5073                 case OP_COND_EXC_OV:
5074                 case OP_COND_EXC_NO:
5075                 case OP_COND_EXC_C:
5076                 case OP_COND_EXC_NC:
5077                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5078                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5079                         break;
5080                 case OP_COND_EXC_IOV:
5081                 case OP_COND_EXC_INO:
5082                 case OP_COND_EXC_IC:
5083                 case OP_COND_EXC_INC:
5084                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5085                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5086                         break;
5087
5088                 /* floating point opcodes */
5089                 case OP_R8CONST: {
5090                         double d = *(double *)ins->inst_p0;
5091
5092                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5093                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5094                         }
5095                         else {
5096                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5097                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5098                         }
5099                         break;
5100                 }
5101                 case OP_R4CONST: {
5102                         float f = *(float *)ins->inst_p0;
5103
5104                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5105                                 if (cfg->r4fp)
5106                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5107                                 else
5108                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5109                         }
5110                         else {
5111                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5112                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5113                                 if (!cfg->r4fp)
5114                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5115                         }
5116                         break;
5117                 }
5118                 case OP_STORER8_MEMBASE_REG:
5119                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5120                         break;
5121                 case OP_LOADR8_MEMBASE:
5122                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5123                         break;
5124                 case OP_STORER4_MEMBASE_REG:
5125                         if (cfg->r4fp) {
5126                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5127                         } else {
5128                                 /* This requires a double->single conversion */
5129                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5130                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5131                         }
5132                         break;
5133                 case OP_LOADR4_MEMBASE:
5134                         if (cfg->r4fp) {
5135                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5136                         } else {
5137                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5138                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5139                         }
5140                         break;
5141                 case OP_ICONV_TO_R4:
5142                         if (cfg->r4fp) {
5143                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5144                         } else {
5145                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5146                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5147                         }
5148                         break;
5149                 case OP_ICONV_TO_R8:
5150                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5151                         break;
5152                 case OP_LCONV_TO_R4:
5153                         if (cfg->r4fp) {
5154                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5155                         } else {
5156                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5157                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5158                         }
5159                         break;
5160                 case OP_LCONV_TO_R8:
5161                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5162                         break;
5163                 case OP_FCONV_TO_R4:
5164                         if (cfg->r4fp) {
5165                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5166                         } else {
5167                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5168                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5169                         }
5170                         break;
5171                 case OP_FCONV_TO_I1:
5172                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5173                         break;
5174                 case OP_FCONV_TO_U1:
5175                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5176                         break;
5177                 case OP_FCONV_TO_I2:
5178                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5179                         break;
5180                 case OP_FCONV_TO_U2:
5181                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5182                         break;
5183                 case OP_FCONV_TO_U4:
5184                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5185                         break;
5186                 case OP_FCONV_TO_I4:
5187                 case OP_FCONV_TO_I:
5188                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5189                         break;
5190                 case OP_FCONV_TO_I8:
5191                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5192                         break;
5193
5194                 case OP_RCONV_TO_I1:
5195                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5196                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5197                         break;
5198                 case OP_RCONV_TO_U1:
5199                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5200                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5201                         break;
5202                 case OP_RCONV_TO_I2:
5203                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5204                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5205                         break;
5206                 case OP_RCONV_TO_U2:
5207                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5208                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5209                         break;
5210                 case OP_RCONV_TO_I4:
5211                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5212                         break;
5213                 case OP_RCONV_TO_U4:
5214                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5215                         break;
5216                 case OP_RCONV_TO_I8:
5217                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5218                         break;
5219                 case OP_RCONV_TO_R8:
5220                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5221                         break;
5222                 case OP_RCONV_TO_R4:
5223                         if (ins->dreg != ins->sreg1)
5224                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5225                         break;
5226
5227                 case OP_LCONV_TO_R_UN: {
5228                         guint8 *br [2];
5229
5230                         /* Based on gcc code */
5231                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5232                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5233
5234                         /* Positive case */
5235                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5236                         br [1] = code; x86_jump8 (code, 0);
5237                         amd64_patch (br [0], code);
5238
5239                         /* Negative case */
5240                         /* Save to the red zone */
5241                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5242                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5243                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5244                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5245                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5246                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5247                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5248                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5249                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5250                         /* Restore */
5251                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5252                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5253                         amd64_patch (br [1], code);
5254                         break;
5255                 }
5256                 case OP_LCONV_TO_OVF_U4:
5257                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5258                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5259                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5260                         break;
5261                 case OP_LCONV_TO_OVF_I4_UN:
5262                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5263                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5264                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5265                         break;
5266                 case OP_FMOVE:
5267                         if (ins->dreg != ins->sreg1)
5268                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5269                         break;
5270                 case OP_RMOVE:
5271                         if (ins->dreg != ins->sreg1)
5272                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5273                         break;
5274                 case OP_MOVE_F_TO_I4:
5275                         if (cfg->r4fp) {
5276                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5277                         } else {
5278                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5279                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5280                         }
5281                         break;
5282                 case OP_MOVE_I4_TO_F:
5283                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5284                         if (!cfg->r4fp)
5285                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5286                         break;
5287                 case OP_MOVE_F_TO_I8:
5288                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5289                         break;
5290                 case OP_MOVE_I8_TO_F:
5291                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5292                         break;
5293                 case OP_FADD:
5294                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5295                         break;
5296                 case OP_FSUB:
5297                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5298                         break;
5299                 case OP_FMUL:
5300                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5301                         break;
5302                 case OP_FDIV:
5303                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5304                         break;
5305                 case OP_FNEG: {
5306                         static double r8_0 = -0.0;
5307
5308                         g_assert (ins->sreg1 == ins->dreg);
5309
5310                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5311                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5312                         break;
5313                 }
5314                 case OP_SIN:
5315                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5316                         break;
5317                 case OP_COS:
5318                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5319                         break;
5320                 case OP_ABS: {
5321                         static guint64 d = 0x7fffffffffffffffUL;
5322
5323                         g_assert (ins->sreg1 == ins->dreg);
5324
5325                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5326                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5327                         break;
5328                 }
5329                 case OP_SQRT:
5330                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5331                         break;
5332
5333                 case OP_RADD:
5334                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5335                         break;
5336                 case OP_RSUB:
5337                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5338                         break;
5339                 case OP_RMUL:
5340                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5341                         break;
5342                 case OP_RDIV:
5343                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5344                         break;
5345                 case OP_RNEG: {
5346                         static float r4_0 = -0.0;
5347
5348                         g_assert (ins->sreg1 == ins->dreg);
5349
5350                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5351                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5352                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5353                         break;
5354                 }
5355
5356                 case OP_IMIN:
5357                         g_assert (cfg->opt & MONO_OPT_CMOV);
5358                         g_assert (ins->dreg == ins->sreg1);
5359                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5360                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5361                         break;
5362                 case OP_IMIN_UN:
5363                         g_assert (cfg->opt & MONO_OPT_CMOV);
5364                         g_assert (ins->dreg == ins->sreg1);
5365                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5366                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5367                         break;
5368                 case OP_IMAX:
5369                         g_assert (cfg->opt & MONO_OPT_CMOV);
5370                         g_assert (ins->dreg == ins->sreg1);
5371                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5372                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5373                         break;
5374                 case OP_IMAX_UN:
5375                         g_assert (cfg->opt & MONO_OPT_CMOV);
5376                         g_assert (ins->dreg == ins->sreg1);
5377                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5378                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5379                         break;
5380                 case OP_LMIN:
5381                         g_assert (cfg->opt & MONO_OPT_CMOV);
5382                         g_assert (ins->dreg == ins->sreg1);
5383                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5384                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5385                         break;
5386                 case OP_LMIN_UN:
5387                         g_assert (cfg->opt & MONO_OPT_CMOV);
5388                         g_assert (ins->dreg == ins->sreg1);
5389                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5390                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5391                         break;
5392                 case OP_LMAX:
5393                         g_assert (cfg->opt & MONO_OPT_CMOV);
5394                         g_assert (ins->dreg == ins->sreg1);
5395                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5396                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5397                         break;
5398                 case OP_LMAX_UN:
5399                         g_assert (cfg->opt & MONO_OPT_CMOV);
5400                         g_assert (ins->dreg == ins->sreg1);
5401                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5402                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5403                         break;
5404                 case OP_X86_FPOP:
5405                         break;
5406                 case OP_FCOMPARE:
5407                         /*
5408                          * The two arguments are swapped because the fbranch instructions
5409                          * depend on this for the non-sse case to work.
5410                          */
5411                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5412                         break;
5413                 case OP_RCOMPARE:
5414                         /*
5415                          * FIXME: Get rid of this.
5416                          * The two arguments are swapped because the fbranch instructions
5417                          * depend on this for the non-sse case to work.
5418                          */
5419                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5420                         break;
5421                 case OP_FCNEQ:
5422                 case OP_FCEQ: {
5423                         /* zeroing the register at the start results in
5424                          * shorter and faster code (we can also remove the widening op)
5425                          */
5426                         guchar *unordered_check;
5427
5428                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5429                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5430                         unordered_check = code;
5431                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5432
5433                         if (ins->opcode == OP_FCEQ) {
5434                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5435                                 amd64_patch (unordered_check, code);
5436                         } else {
5437                                 guchar *jump_to_end;
5438                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5439                                 jump_to_end = code;
5440                                 x86_jump8 (code, 0);
5441                                 amd64_patch (unordered_check, code);
5442                                 amd64_inc_reg (code, ins->dreg);
5443                                 amd64_patch (jump_to_end, code);
5444                         }
5445                         break;
5446                 }
5447                 case OP_FCLT:
5448                 case OP_FCLT_UN: {
5449                         /* zeroing the register at the start results in
5450                          * shorter and faster code (we can also remove the widening op)
5451                          */
5452                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5453                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5454                         if (ins->opcode == OP_FCLT_UN) {
5455                                 guchar *unordered_check = code;
5456                                 guchar *jump_to_end;
5457                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5458                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5459                                 jump_to_end = code;
5460                                 x86_jump8 (code, 0);
5461                                 amd64_patch (unordered_check, code);
5462                                 amd64_inc_reg (code, ins->dreg);
5463                                 amd64_patch (jump_to_end, code);
5464                         } else {
5465                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5466                         }
5467                         break;
5468                 }
5469                 case OP_FCLE: {
5470                         guchar *unordered_check;
5471                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5472                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5473                         unordered_check = code;
5474                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5475                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5476                         amd64_patch (unordered_check, code);
5477                         break;
5478                 }
5479                 case OP_FCGT:
5480                 case OP_FCGT_UN: {
5481                         /* zeroing the register at the start results in
5482                          * shorter and faster code (we can also remove the widening op)
5483                          */
5484                         guchar *unordered_check;
5485
5486                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5487                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5488                         if (ins->opcode == OP_FCGT) {
5489                                 unordered_check = code;
5490                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5491                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5492                                 amd64_patch (unordered_check, code);
5493                         } else {
5494                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5495                         }
5496                         break;
5497                 }
5498                 case OP_FCGE: {
5499                         guchar *unordered_check;
5500                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5501                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5502                         unordered_check = code;
5503                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5504                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5505                         amd64_patch (unordered_check, code);
5506                         break;
5507                 }
5508
5509                 case OP_RCEQ:
5510                 case OP_RCGT:
5511                 case OP_RCLT:
5512                 case OP_RCLT_UN:
5513                 case OP_RCGT_UN: {
5514                         int x86_cond;
5515                         gboolean unordered = FALSE;
5516
5517                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5518                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5519
5520                         switch (ins->opcode) {
5521                         case OP_RCEQ:
5522                                 x86_cond = X86_CC_EQ;
5523                                 break;
5524                         case OP_RCGT:
5525                                 x86_cond = X86_CC_LT;
5526                                 break;
5527                         case OP_RCLT:
5528                                 x86_cond = X86_CC_GT;
5529                                 break;
5530                         case OP_RCLT_UN:
5531                                 x86_cond = X86_CC_GT;
5532                                 unordered = TRUE;
5533                                 break;
5534                         case OP_RCGT_UN:
5535                                 x86_cond = X86_CC_LT;
5536                                 unordered = TRUE;
5537                                 break;
5538                         default:
5539                                 g_assert_not_reached ();
5540                                 break;
5541                         }
5542
5543                         if (unordered) {
5544                                 guchar *unordered_check;
5545                                 guchar *jump_to_end;
5546
5547                                 unordered_check = code;
5548                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5549                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5550                                 jump_to_end = code;
5551                                 x86_jump8 (code, 0);
5552                                 amd64_patch (unordered_check, code);
5553                                 amd64_inc_reg (code, ins->dreg);
5554                                 amd64_patch (jump_to_end, code);
5555                         } else {
5556                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5557                         }
5558                         break;
5559                 }
5560                 case OP_FCLT_MEMBASE:
5561                 case OP_FCGT_MEMBASE:
5562                 case OP_FCLT_UN_MEMBASE:
5563                 case OP_FCGT_UN_MEMBASE:
5564                 case OP_FCEQ_MEMBASE: {
5565                         guchar *unordered_check, *jump_to_end;
5566                         int x86_cond;
5567
5568                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5569                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5570
5571                         switch (ins->opcode) {
5572                         case OP_FCEQ_MEMBASE:
5573                                 x86_cond = X86_CC_EQ;
5574                                 break;
5575                         case OP_FCLT_MEMBASE:
5576                         case OP_FCLT_UN_MEMBASE:
5577                                 x86_cond = X86_CC_LT;
5578                                 break;
5579                         case OP_FCGT_MEMBASE:
5580                         case OP_FCGT_UN_MEMBASE:
5581                                 x86_cond = X86_CC_GT;
5582                                 break;
5583                         default:
5584                                 g_assert_not_reached ();
5585                         }
5586
5587                         unordered_check = code;
5588                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5589                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5590
5591                         switch (ins->opcode) {
5592                         case OP_FCEQ_MEMBASE:
5593                         case OP_FCLT_MEMBASE:
5594                         case OP_FCGT_MEMBASE:
5595                                 amd64_patch (unordered_check, code);
5596                                 break;
5597                         case OP_FCLT_UN_MEMBASE:
5598                         case OP_FCGT_UN_MEMBASE:
5599                                 jump_to_end = code;
5600                                 x86_jump8 (code, 0);
5601                                 amd64_patch (unordered_check, code);
5602                                 amd64_inc_reg (code, ins->dreg);
5603                                 amd64_patch (jump_to_end, code);
5604                                 break;
5605                         default:
5606                                 break;
5607                         }
5608                         break;
5609                 }
5610                 case OP_FBEQ: {
5611                         guchar *jump = code;
5612                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5613                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5614                         amd64_patch (jump, code);
5615                         break;
5616                 }
5617                 case OP_FBNE_UN:
5618                         /* Branch if C013 != 100 */
5619                         /* branch if !ZF or (PF|CF) */
5620                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5621                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5622                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5623                         break;
5624                 case OP_FBLT:
5625                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5626                         break;
5627                 case OP_FBLT_UN:
5628                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5629                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5630                         break;
5631                 case OP_FBGT:
5632                 case OP_FBGT_UN:
5633                         if (ins->opcode == OP_FBGT) {
5634                                 guchar *br1;
5635
5636                                 /* skip branch if C1=1 */
5637                                 br1 = code;
5638                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5639                                 /* branch if (C0 | C3) = 1 */
5640                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5641                                 amd64_patch (br1, code);
5642                                 break;
5643                         } else {
5644                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5645                         }
5646                         break;
5647                 case OP_FBGE: {
5648                         /* Branch if C013 == 100 or 001 */
5649                         guchar *br1;
5650
5651                         /* skip branch if C1=1 */
5652                         br1 = code;
5653                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5654                         /* branch if (C0 | C3) = 1 */
5655                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5656                         amd64_patch (br1, code);
5657                         break;
5658                 }
5659                 case OP_FBGE_UN:
5660                         /* Branch if C013 == 000 */
5661                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5662                         break;
5663                 case OP_FBLE: {
5664                         /* Branch if C013=000 or 100 */
5665                         guchar *br1;
5666
5667                         /* skip branch if C1=1 */
5668                         br1 = code;
5669                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5670                         /* branch if C0=0 */
5671                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5672                         amd64_patch (br1, code);
5673                         break;
5674                 }
5675                 case OP_FBLE_UN:
5676                         /* Branch if C013 != 001 */
5677                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5678                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5679                         break;
5680                 case OP_CKFINITE:
5681                         /* Transfer value to the fp stack */
5682                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5683                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5684                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5685
5686                         amd64_push_reg (code, AMD64_RAX);
5687                         amd64_fxam (code);
5688                         amd64_fnstsw (code);
5689                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5690                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5691                         amd64_pop_reg (code, AMD64_RAX);
5692                         amd64_fstp (code, 0);
5693                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5694                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5695                         break;
5696                 case OP_TLS_GET: {
5697                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5698                         break;
5699                 }
5700                 case OP_TLS_GET_REG:
5701                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5702                         break;
5703                 case OP_TLS_SET: {
5704                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5705                         break;
5706                 }
5707                 case OP_TLS_SET_REG: {
5708                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5709                         break;
5710                 }
5711                 case OP_MEMORY_BARRIER: {
5712                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5713                                 x86_mfence (code);
5714                         break;
5715                 }
5716                 case OP_ATOMIC_ADD_I4:
5717                 case OP_ATOMIC_ADD_I8: {
5718                         int dreg = ins->dreg;
5719                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5720
5721                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5722                                 dreg = AMD64_R11;
5723
5724                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5725                         amd64_prefix (code, X86_LOCK_PREFIX);
5726                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5727                         /* dreg contains the old value, add with sreg2 value */
5728                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5729
5730                         if (ins->dreg != dreg)
5731                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5732
5733                         break;
5734                 }
5735                 case OP_ATOMIC_EXCHANGE_I4:
5736                 case OP_ATOMIC_EXCHANGE_I8: {
5737                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5738
5739                         /* LOCK prefix is implied. */
5740                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5741                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5742                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5743                         break;
5744                 }
5745                 case OP_ATOMIC_CAS_I4:
5746                 case OP_ATOMIC_CAS_I8: {
5747                         guint32 size;
5748
5749                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5750                                 size = 8;
5751                         else
5752                                 size = 4;
5753
5754                         /*
5755                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5756                          * an explanation of how this works.
5757                          */
5758                         g_assert (ins->sreg3 == AMD64_RAX);
5759                         g_assert (ins->sreg1 != AMD64_RAX);
5760                         g_assert (ins->sreg1 != ins->sreg2);
5761
5762                         amd64_prefix (code, X86_LOCK_PREFIX);
5763                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5764
5765                         if (ins->dreg != AMD64_RAX)
5766                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5767                         break;
5768                 }
5769                 case OP_ATOMIC_LOAD_I1: {
5770                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5771                         break;
5772                 }
5773                 case OP_ATOMIC_LOAD_U1: {
5774                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5775                         break;
5776                 }
5777                 case OP_ATOMIC_LOAD_I2: {
5778                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5779                         break;
5780                 }
5781                 case OP_ATOMIC_LOAD_U2: {
5782                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5783                         break;
5784                 }
5785                 case OP_ATOMIC_LOAD_I4: {
5786                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5787                         break;
5788                 }
5789                 case OP_ATOMIC_LOAD_U4:
5790                 case OP_ATOMIC_LOAD_I8:
5791                 case OP_ATOMIC_LOAD_U8: {
5792                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5793                         break;
5794                 }
5795                 case OP_ATOMIC_LOAD_R4: {
5796                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5797                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5798                         break;
5799                 }
5800                 case OP_ATOMIC_LOAD_R8: {
5801                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5802                         break;
5803                 }
5804                 case OP_ATOMIC_STORE_I1:
5805                 case OP_ATOMIC_STORE_U1:
5806                 case OP_ATOMIC_STORE_I2:
5807                 case OP_ATOMIC_STORE_U2:
5808                 case OP_ATOMIC_STORE_I4:
5809                 case OP_ATOMIC_STORE_U4:
5810                 case OP_ATOMIC_STORE_I8:
5811                 case OP_ATOMIC_STORE_U8: {
5812                         int size;
5813
5814                         switch (ins->opcode) {
5815                         case OP_ATOMIC_STORE_I1:
5816                         case OP_ATOMIC_STORE_U1:
5817                                 size = 1;
5818                                 break;
5819                         case OP_ATOMIC_STORE_I2:
5820                         case OP_ATOMIC_STORE_U2:
5821                                 size = 2;
5822                                 break;
5823                         case OP_ATOMIC_STORE_I4:
5824                         case OP_ATOMIC_STORE_U4:
5825                                 size = 4;
5826                                 break;
5827                         case OP_ATOMIC_STORE_I8:
5828                         case OP_ATOMIC_STORE_U8:
5829                                 size = 8;
5830                                 break;
5831                         }
5832
5833                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5834
5835                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5836                                 x86_mfence (code);
5837                         break;
5838                 }
5839                 case OP_ATOMIC_STORE_R4: {
5840                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5841                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5842
5843                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5844                                 x86_mfence (code);
5845                         break;
5846                 }
5847                 case OP_ATOMIC_STORE_R8: {
5848                         x86_nop (code);
5849                         x86_nop (code);
5850                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5851                         x86_nop (code);
5852                         x86_nop (code);
5853
5854                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5855                                 x86_mfence (code);
5856                         break;
5857                 }
5858                 case OP_CARD_TABLE_WBARRIER: {
5859                         int ptr = ins->sreg1;
5860                         int value = ins->sreg2;
5861                         guchar *br = 0;
5862                         int nursery_shift, card_table_shift;
5863                         gpointer card_table_mask;
5864                         size_t nursery_size;
5865
5866                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5867                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5868                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5869
5870                         /*If either point to the stack we can simply avoid the WB. This happens due to
5871                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5872                          */
5873                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5874                                 continue;
5875
5876                         /*
5877                          * We need one register we can clobber, we choose EDX and make sreg1
5878                          * fixed EAX to work around limitations in the local register allocator.
5879                          * sreg2 might get allocated to EDX, but that is not a problem since
5880                          * we use it before clobbering EDX.
5881                          */
5882                         g_assert (ins->sreg1 == AMD64_RAX);
5883
5884                         /*
5885                          * This is the code we produce:
5886                          *
5887                          *   edx = value
5888                          *   edx >>= nursery_shift
5889                          *   cmp edx, (nursery_start >> nursery_shift)
5890                          *   jne done
5891                          *   edx = ptr
5892                          *   edx >>= card_table_shift
5893                          *   edx += cardtable
5894                          *   [edx] = 1
5895                          * done:
5896                          */
5897
5898                         if (mono_gc_card_table_nursery_check ()) {
5899                                 if (value != AMD64_RDX)
5900                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5901                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5902                                 if (shifted_nursery_start >> 31) {
5903                                         /*
5904                                          * The value we need to compare against is 64 bits, so we need
5905                                          * another spare register.  We use RBX, which we save and
5906                                          * restore.
5907                                          */
5908                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5909                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5910                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5911                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5912                                 } else {
5913                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5914                                 }
5915                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5916                         }
5917                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5918                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5919                         if (card_table_mask)
5920                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5921
5922                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5923                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5924
5925                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5926
5927                         if (mono_gc_card_table_nursery_check ())
5928                                 x86_patch (br, code);
5929                         break;
5930                 }
5931 #ifdef MONO_ARCH_SIMD_INTRINSICS
5932                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5933                 case OP_ADDPS:
5934                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936                 case OP_DIVPS:
5937                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_MULPS:
5940                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942                 case OP_SUBPS:
5943                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5944                         break;
5945                 case OP_MAXPS:
5946                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 case OP_MINPS:
5949                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5950                         break;
5951                 case OP_COMPPS:
5952                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5953                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5954                         break;
5955                 case OP_ANDPS:
5956                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5957                         break;
5958                 case OP_ANDNPS:
5959                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5960                         break;
5961                 case OP_ORPS:
5962                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5963                         break;
5964                 case OP_XORPS:
5965                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5966                         break;
5967                 case OP_SQRTPS:
5968                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5969                         break;
5970                 case OP_RSQRTPS:
5971                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5972                         break;
5973                 case OP_RCPPS:
5974                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5975                         break;
5976                 case OP_ADDSUBPS:
5977                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5978                         break;
5979                 case OP_HADDPS:
5980                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982                 case OP_HSUBPS:
5983                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_DUPPS_HIGH:
5986                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5987                         break;
5988                 case OP_DUPPS_LOW:
5989                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5990                         break;
5991
5992                 case OP_PSHUFLEW_HIGH:
5993                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5994                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5995                         break;
5996                 case OP_PSHUFLEW_LOW:
5997                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5998                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5999                         break;
6000                 case OP_PSHUFLED:
6001                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6002                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6003                         break;
6004                 case OP_SHUFPS:
6005                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6006                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6007                         break;
6008                 case OP_SHUFPD:
6009                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6010                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6011                         break;
6012
6013                 case OP_ADDPD:
6014                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6015                         break;
6016                 case OP_DIVPD:
6017                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6018                         break;
6019                 case OP_MULPD:
6020                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6021                         break;
6022                 case OP_SUBPD:
6023                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025                 case OP_MAXPD:
6026                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028                 case OP_MINPD:
6029                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6030                         break;
6031                 case OP_COMPPD:
6032                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6033                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6034                         break;
6035                 case OP_ANDPD:
6036                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038                 case OP_ANDNPD:
6039                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041                 case OP_ORPD:
6042                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044                 case OP_XORPD:
6045                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047                 case OP_SQRTPD:
6048                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6049                         break;
6050                 case OP_ADDSUBPD:
6051                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6052                         break;
6053                 case OP_HADDPD:
6054                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6055                         break;
6056                 case OP_HSUBPD:
6057                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6058                         break;
6059                 case OP_DUPPD:
6060                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6061                         break;
6062
6063                 case OP_EXTRACT_MASK:
6064                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6065                         break;
6066
6067                 case OP_PAND:
6068                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_POR:
6071                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_PXOR:
6074                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076
6077                 case OP_PADDB:
6078                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080                 case OP_PADDW:
6081                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083                 case OP_PADDD:
6084                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6085                         break;
6086                 case OP_PADDQ:
6087                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089
6090                 case OP_PSUBB:
6091                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093                 case OP_PSUBW:
6094                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096                 case OP_PSUBD:
6097                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099                 case OP_PSUBQ:
6100                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102
6103                 case OP_PMAXB_UN:
6104                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106                 case OP_PMAXW_UN:
6107                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109                 case OP_PMAXD_UN:
6110                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112
6113                 case OP_PMAXB:
6114                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6115                         break;
6116                 case OP_PMAXW:
6117                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6118                         break;
6119                 case OP_PMAXD:
6120                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122
6123                 case OP_PAVGB_UN:
6124                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6125                         break;
6126                 case OP_PAVGW_UN:
6127                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129
6130                 case OP_PMINB_UN:
6131                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6132                         break;
6133                 case OP_PMINW_UN:
6134                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6135                         break;
6136                 case OP_PMIND_UN:
6137                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6138                         break;
6139
6140                 case OP_PMINB:
6141                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6142                         break;
6143                 case OP_PMINW:
6144                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6145                         break;
6146                 case OP_PMIND:
6147                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6148                         break;
6149
6150                 case OP_PCMPEQB:
6151                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6152                         break;
6153                 case OP_PCMPEQW:
6154                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6155                         break;
6156                 case OP_PCMPEQD:
6157                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6158                         break;
6159                 case OP_PCMPEQQ:
6160                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6161                         break;
6162
6163                 case OP_PCMPGTB:
6164                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6165                         break;
6166                 case OP_PCMPGTW:
6167                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6168                         break;
6169                 case OP_PCMPGTD:
6170                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6171                         break;
6172                 case OP_PCMPGTQ:
6173                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6174                         break;
6175
6176                 case OP_PSUM_ABS_DIFF:
6177                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6178                         break;
6179
6180                 case OP_UNPACK_LOWB:
6181                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6182                         break;
6183                 case OP_UNPACK_LOWW:
6184                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6185                         break;
6186                 case OP_UNPACK_LOWD:
6187                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6188                         break;
6189                 case OP_UNPACK_LOWQ:
6190                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6191                         break;
6192                 case OP_UNPACK_LOWPS:
6193                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6194                         break;
6195                 case OP_UNPACK_LOWPD:
6196                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6197                         break;
6198
6199                 case OP_UNPACK_HIGHB:
6200                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6201                         break;
6202                 case OP_UNPACK_HIGHW:
6203                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6204                         break;
6205                 case OP_UNPACK_HIGHD:
6206                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6207                         break;
6208                 case OP_UNPACK_HIGHQ:
6209                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6210                         break;
6211                 case OP_UNPACK_HIGHPS:
6212                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6213                         break;
6214                 case OP_UNPACK_HIGHPD:
6215                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6216                         break;
6217
6218                 case OP_PACKW:
6219                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6220                         break;
6221                 case OP_PACKD:
6222                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6223                         break;
6224                 case OP_PACKW_UN:
6225                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6226                         break;
6227                 case OP_PACKD_UN:
6228                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6229                         break;
6230
6231                 case OP_PADDB_SAT_UN:
6232                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6233                         break;
6234                 case OP_PSUBB_SAT_UN:
6235                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6236                         break;
6237                 case OP_PADDW_SAT_UN:
6238                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6239                         break;
6240                 case OP_PSUBW_SAT_UN:
6241                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6242                         break;
6243
6244                 case OP_PADDB_SAT:
6245                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6246                         break;
6247                 case OP_PSUBB_SAT:
6248                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6249                         break;
6250                 case OP_PADDW_SAT:
6251                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6252                         break;
6253                 case OP_PSUBW_SAT:
6254                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6255                         break;
6256
6257                 case OP_PMULW:
6258                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6259                         break;
6260                 case OP_PMULD:
6261                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6262                         break;
6263                 case OP_PMULQ:
6264                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6265                         break;
6266                 case OP_PMULW_HIGH_UN:
6267                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6268                         break;
6269                 case OP_PMULW_HIGH:
6270                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6271                         break;
6272
6273                 case OP_PSHRW:
6274                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6275                         break;
6276                 case OP_PSHRW_REG:
6277                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6278                         break;
6279
6280                 case OP_PSARW:
6281                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6282                         break;
6283                 case OP_PSARW_REG:
6284                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6285                         break;
6286
6287                 case OP_PSHLW:
6288                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6289                         break;
6290                 case OP_PSHLW_REG:
6291                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6292                         break;
6293
6294                 case OP_PSHRD:
6295                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6296                         break;
6297                 case OP_PSHRD_REG:
6298                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6299                         break;
6300
6301                 case OP_PSARD:
6302                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6303                         break;
6304                 case OP_PSARD_REG:
6305                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6306                         break;
6307
6308                 case OP_PSHLD:
6309                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6310                         break;
6311                 case OP_PSHLD_REG:
6312                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6313                         break;
6314
6315                 case OP_PSHRQ:
6316                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6317                         break;
6318                 case OP_PSHRQ_REG:
6319                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6320                         break;
6321
6322                 /*TODO: This is appart of the sse spec but not added
6323                 case OP_PSARQ:
6324                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6325                         break;
6326                 case OP_PSARQ_REG:
6327                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6328                         break;
6329                 */
6330
6331                 case OP_PSHLQ:
6332                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6333                         break;
6334                 case OP_PSHLQ_REG:
6335                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6336                         break;
6337                 case OP_CVTDQ2PD:
6338                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6339                         break;
6340                 case OP_CVTDQ2PS:
6341                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6342                         break;
6343                 case OP_CVTPD2DQ:
6344                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6345                         break;
6346                 case OP_CVTPD2PS:
6347                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6348                         break;
6349                 case OP_CVTPS2DQ:
6350                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6351                         break;
6352                 case OP_CVTPS2PD:
6353                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6354                         break;
6355                 case OP_CVTTPD2DQ:
6356                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6357                         break;
6358                 case OP_CVTTPS2DQ:
6359                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6360                         break;
6361
6362                 case OP_ICONV_TO_X:
6363                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6364                         break;
6365                 case OP_EXTRACT_I4:
6366                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6367                         break;
6368                 case OP_EXTRACT_I8:
6369                         if (ins->inst_c0) {
6370                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6371                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6372                         } else {
6373                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6374                         }
6375                         break;
6376                 case OP_EXTRACT_I1:
6377                 case OP_EXTRACT_U1:
6378                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6379                         if (ins->inst_c0)
6380                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6381                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6382                         break;
6383                 case OP_EXTRACT_I2:
6384                 case OP_EXTRACT_U2:
6385                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6386                         if (ins->inst_c0)
6387                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6388                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6389                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6390                         break;
6391                 case OP_EXTRACT_R8:
6392                         if (ins->inst_c0)
6393                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6394                         else
6395                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6396                         break;
6397                 case OP_INSERT_I2:
6398                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6399                         break;
6400                 case OP_EXTRACTX_U2:
6401                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6402                         break;
6403                 case OP_INSERTX_U1_SLOW:
6404                         /*sreg1 is the extracted ireg (scratch)
6405                         /sreg2 is the to be inserted ireg (scratch)
6406                         /dreg is the xreg to receive the value*/
6407
6408                         /*clear the bits from the extracted word*/
6409                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6410                         /*shift the value to insert if needed*/
6411                         if (ins->inst_c0 & 1)
6412                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6413                         /*join them together*/
6414                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6415                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6416                         break;
6417                 case OP_INSERTX_I4_SLOW:
6418                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6419                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6420                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6421                         break;
6422                 case OP_INSERTX_I8_SLOW:
6423                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6424                         if (ins->inst_c0)
6425                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6426                         else
6427                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6428                         break;
6429
6430                 case OP_INSERTX_R4_SLOW:
6431                         switch (ins->inst_c0) {
6432                         case 0:
6433                                 if (cfg->r4fp)
6434                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6435                                 else
6436                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6437                                 break;
6438                         case 1:
6439                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6440                                 if (cfg->r4fp)
6441                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6442                                 else
6443                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6444                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6445                                 break;
6446                         case 2:
6447                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6448                                 if (cfg->r4fp)
6449                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6450                                 else
6451                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6452                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6453                                 break;
6454                         case 3:
6455                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6456                                 if (cfg->r4fp)
6457                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6458                                 else
6459                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6460                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6461                                 break;
6462                         }
6463                         break;
6464                 case OP_INSERTX_R8_SLOW:
6465                         if (ins->inst_c0)
6466                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6467                         else
6468                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6469                         break;
6470                 case OP_STOREX_MEMBASE_REG:
6471                 case OP_STOREX_MEMBASE:
6472                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6473                         break;
6474                 case OP_LOADX_MEMBASE:
6475                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6476                         break;
6477                 case OP_LOADX_ALIGNED_MEMBASE:
6478                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6479                         break;
6480                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6481                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6482                         break;
6483                 case OP_STOREX_NTA_MEMBASE_REG:
6484                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6485                         break;
6486                 case OP_PREFETCH_MEMBASE:
6487                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6488                         break;
6489
6490                 case OP_XMOVE:
6491                         /*FIXME the peephole pass should have killed this*/
6492                         if (ins->dreg != ins->sreg1)
6493                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6494                         break;
6495                 case OP_XZERO:
6496                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6497                         break;
6498                 case OP_ICONV_TO_R4_RAW:
6499                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6500                         break;
6501
6502                 case OP_FCONV_TO_R8_X:
6503                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6504                         break;
6505
6506                 case OP_XCONV_R8_TO_I4:
6507                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6508                         switch (ins->backend.source_opcode) {
6509                         case OP_FCONV_TO_I1:
6510                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6511                                 break;
6512                         case OP_FCONV_TO_U1:
6513                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6514                                 break;
6515                         case OP_FCONV_TO_I2:
6516                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6517                                 break;
6518                         case OP_FCONV_TO_U2:
6519                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6520                                 break;
6521                         }
6522                         break;
6523
6524                 case OP_EXPAND_I2:
6525                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6526                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6527                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6528                         break;
6529                 case OP_EXPAND_I4:
6530                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6531                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6532                         break;
6533                 case OP_EXPAND_I8:
6534                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6535                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6536                         break;
6537                 case OP_EXPAND_R4:
6538                         if (cfg->r4fp) {
6539                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6540                         } else {
6541                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6542                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6543                         }
6544                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6545                         break;
6546                 case OP_EXPAND_R8:
6547                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6548                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6549                         break;
6550 #endif
6551                 case OP_LIVERANGE_START: {
6552                         if (cfg->verbose_level > 1)
6553                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6554                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6555                         break;
6556                 }
6557                 case OP_LIVERANGE_END: {
6558                         if (cfg->verbose_level > 1)
6559                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6560                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6561                         break;
6562                 }
6563                 case OP_NACL_GC_SAFE_POINT: {
6564 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6565                         if (cfg->compile_aot)
6566                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6567                         else {
6568                                 guint8 *br [1];
6569
6570                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6571                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6572                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6573                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6574                                 amd64_patch (br[0], code);
6575                         }
6576 #endif
6577                         break;
6578                 }
6579                 case OP_GC_LIVENESS_DEF:
6580                 case OP_GC_LIVENESS_USE:
6581                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6582                         ins->backend.pc_offset = code - cfg->native_code;
6583                         break;
6584                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6585                         ins->backend.pc_offset = code - cfg->native_code;
6586                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6587                         break;
6588                 default:
6589                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6590                         g_assert_not_reached ();
6591                 }
6592
6593                 if ((code - cfg->native_code - offset) > max_len) {
6594 #if !defined(__native_client_codegen__)
6595                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6596                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6597                         g_assert_not_reached ();
6598 #endif
6599                 }
6600
6601                 last_ins = ins;
6602                 last_offset = offset;
6603         }
6604
6605         cfg->code_len = code - cfg->native_code;
6606 }
6607
6608 #endif /* DISABLE_JIT */
6609
6610 void
6611 mono_arch_register_lowlevel_calls (void)
6612 {
6613         /* The signature doesn't matter */
6614         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6615 }
6616
6617 void
6618 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6619 {
6620         MonoJumpInfo *patch_info;
6621         gboolean compile_aot = !run_cctors;
6622
6623         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6624                 unsigned char *ip = patch_info->ip.i + code;
6625                 unsigned char *target;
6626
6627                 if (compile_aot) {
6628                         switch (patch_info->type) {
6629                         case MONO_PATCH_INFO_BB:
6630                         case MONO_PATCH_INFO_LABEL:
6631                                 break;
6632                         default:
6633                                 /* No need to patch these */
6634                                 continue;
6635                         }
6636                 }
6637
6638                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6639
6640                 switch (patch_info->type) {
6641                 case MONO_PATCH_INFO_NONE:
6642                         continue;
6643                 case MONO_PATCH_INFO_METHOD_REL:
6644                 case MONO_PATCH_INFO_R8:
6645                 case MONO_PATCH_INFO_R4:
6646                         g_assert_not_reached ();
6647                         continue;
6648                 case MONO_PATCH_INFO_BB:
6649                         break;
6650                 default:
6651                         break;
6652                 }
6653
6654                 /*
6655                  * Debug code to help track down problems where the target of a near call is
6656                  * is not valid.
6657                  */
6658                 if (amd64_is_near_call (ip)) {
6659                         gint64 disp = (guint8*)target - (guint8*)ip;
6660
6661                         if (!amd64_is_imm32 (disp)) {
6662                                 printf ("TYPE: %d\n", patch_info->type);
6663                                 switch (patch_info->type) {
6664                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6665                                         printf ("V: %s\n", patch_info->data.name);
6666                                         break;
6667                                 case MONO_PATCH_INFO_METHOD_JUMP:
6668                                 case MONO_PATCH_INFO_METHOD:
6669                                         printf ("V: %s\n", patch_info->data.method->name);
6670                                         break;
6671                                 default:
6672                                         break;
6673                                 }
6674                         }
6675                 }
6676
6677                 amd64_patch (ip, (gpointer)target);
6678         }
6679 }
6680
6681 #ifndef DISABLE_JIT
6682
6683 static int
6684 get_max_epilog_size (MonoCompile *cfg)
6685 {
6686         int max_epilog_size = 16;
6687
6688         if (cfg->method->save_lmf)
6689                 max_epilog_size += 256;
6690
6691         if (mono_jit_trace_calls != NULL)
6692                 max_epilog_size += 50;
6693
6694         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6695                 max_epilog_size += 50;
6696
6697         max_epilog_size += (AMD64_NREG * 2);
6698
6699         return max_epilog_size;
6700 }
6701
6702 /*
6703  * This macro is used for testing whenever the unwinder works correctly at every point
6704  * where an async exception can happen.
6705  */
6706 /* This will generate a SIGSEGV at the given point in the code */
6707 #define async_exc_point(code) do { \
6708     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6709          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6710              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6711          cfg->arch.async_point_count ++; \
6712     } \
6713 } while (0)
6714
6715 guint8 *
6716 mono_arch_emit_prolog (MonoCompile *cfg)
6717 {
6718         MonoMethod *method = cfg->method;
6719         MonoBasicBlock *bb;
6720         MonoMethodSignature *sig;
6721         MonoInst *ins;
6722         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6723         guint8 *code;
6724         CallInfo *cinfo;
6725         MonoInst *lmf_var = cfg->lmf_var;
6726         gboolean args_clobbered = FALSE;
6727         gboolean trace = FALSE;
6728 #ifdef __native_client_codegen__
6729         guint alignment_check;
6730 #endif
6731
6732         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6733
6734 #if defined(__default_codegen__)
6735         code = cfg->native_code = g_malloc (cfg->code_size);
6736 #elif defined(__native_client_codegen__)
6737         /* native_code_alloc is not 32-byte aligned, native_code is. */
6738         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6739
6740         /* Align native_code to next nearest kNaclAlignment byte. */
6741         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6742         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6743
6744         code = cfg->native_code;
6745
6746         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6747         g_assert (alignment_check == 0);
6748 #endif
6749
6750         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6751                 trace = TRUE;
6752
6753         /* Amount of stack space allocated by register saving code */
6754         pos = 0;
6755
6756         /* Offset between RSP and the CFA */
6757         cfa_offset = 0;
6758
6759         /*
6760          * The prolog consists of the following parts:
6761          * FP present:
6762          * - push rbp, mov rbp, rsp
6763          * - save callee saved regs using pushes
6764          * - allocate frame
6765          * - save rgctx if needed
6766          * - save lmf if needed
6767          * FP not present:
6768          * - allocate frame
6769          * - save rgctx if needed
6770          * - save lmf if needed
6771          * - save callee saved regs using moves
6772          */
6773
6774         // CFA = sp + 8
6775         cfa_offset = 8;
6776         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6777         // IP saved at CFA - 8
6778         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6779         async_exc_point (code);
6780         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6781
6782         if (!cfg->arch.omit_fp) {
6783                 amd64_push_reg (code, AMD64_RBP);
6784                 cfa_offset += 8;
6785                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6786                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6787                 async_exc_point (code);
6788 #ifdef HOST_WIN32
6789                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6790 #endif
6791                 /* These are handled automatically by the stack marking code */
6792                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6793
6794                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6795                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6796                 async_exc_point (code);
6797 #ifdef HOST_WIN32
6798                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6799 #endif
6800         }
6801
6802         /* The param area is always at offset 0 from sp */
6803         /* This needs to be allocated here, since it has to come after the spill area */
6804         if (cfg->param_area) {
6805                 if (cfg->arch.omit_fp)
6806                         // FIXME:
6807                         g_assert_not_reached ();
6808                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6809         }
6810
6811         if (cfg->arch.omit_fp) {
6812                 /*
6813                  * On enter, the stack is misaligned by the pushing of the return
6814                  * address. It is either made aligned by the pushing of %rbp, or by
6815                  * this.
6816                  */
6817                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6818                 if ((alloc_size % 16) == 0) {
6819                         alloc_size += 8;
6820                         /* Mark the padding slot as NOREF */
6821                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6822                 }
6823         } else {
6824                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6825                 if (cfg->stack_offset != alloc_size) {
6826                         /* Mark the padding slot as NOREF */
6827                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6828                 }
6829                 cfg->arch.sp_fp_offset = alloc_size;
6830                 alloc_size -= pos;
6831         }
6832
6833         cfg->arch.stack_alloc_size = alloc_size;
6834
6835         /* Allocate stack frame */
6836         if (alloc_size) {
6837                 /* See mono_emit_stack_alloc */
6838 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6839                 guint32 remaining_size = alloc_size;
6840                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6841                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6842                 guint32 offset = code - cfg->native_code;
6843                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6844                         while (required_code_size >= (cfg->code_size - offset))
6845                                 cfg->code_size *= 2;
6846                         cfg->native_code = mono_realloc_native_code (cfg);
6847                         code = cfg->native_code + offset;
6848                         cfg->stat_code_reallocs++;
6849                 }
6850
6851                 while (remaining_size >= 0x1000) {
6852                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6853                         if (cfg->arch.omit_fp) {
6854                                 cfa_offset += 0x1000;
6855                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6856                         }
6857                         async_exc_point (code);
6858 #ifdef HOST_WIN32
6859                         if (cfg->arch.omit_fp)
6860                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6861 #endif
6862
6863                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6864                         remaining_size -= 0x1000;
6865                 }
6866                 if (remaining_size) {
6867                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6868                         if (cfg->arch.omit_fp) {
6869                                 cfa_offset += remaining_size;
6870                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6871                                 async_exc_point (code);
6872                         }
6873 #ifdef HOST_WIN32
6874                         if (cfg->arch.omit_fp)
6875                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6876 #endif
6877                 }
6878 #else
6879                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6880                 if (cfg->arch.omit_fp) {
6881                         cfa_offset += alloc_size;
6882                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6883                         async_exc_point (code);
6884                 }
6885 #endif
6886         }
6887
6888         /* Stack alignment check */
6889 #if 0
6890         {
6891                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6892                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6893                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6894                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6895                 amd64_breakpoint (code);
6896         }
6897 #endif
6898
6899         if (mini_get_debug_options ()->init_stacks) {
6900                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6901
6902                 /* Save registers to the red zone */
6903                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6904                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6905
6906                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6907                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6908                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6909
6910                 amd64_cld (code);
6911 #if defined(__default_codegen__)
6912                 amd64_prefix (code, X86_REP_PREFIX);
6913                 amd64_stosl (code);
6914 #elif defined(__native_client_codegen__)
6915                 /* NaCl stos pseudo-instruction */
6916                 amd64_codegen_pre (code);
6917                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6918                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6919                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6920                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6921                 amd64_prefix (code, X86_REP_PREFIX);
6922                 amd64_stosl (code);
6923                 amd64_codegen_post (code);
6924 #endif /* __native_client_codegen__ */
6925
6926                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6927                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6928         }
6929
6930         /* Save LMF */
6931         if (method->save_lmf)
6932                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6933
6934         /* Save callee saved registers */
6935         if (cfg->arch.omit_fp) {
6936                 save_area_offset = cfg->arch.reg_save_area_offset;
6937                 /* Save caller saved registers after sp is adjusted */
6938                 /* The registers are saved at the bottom of the frame */
6939                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6940         } else {
6941                 /* The registers are saved just below the saved rbp */
6942                 save_area_offset = cfg->arch.reg_save_area_offset;
6943         }
6944
6945         for (i = 0; i < AMD64_NREG; ++i) {
6946                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6947                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6948
6949                         if (cfg->arch.omit_fp) {
6950                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6951                                 /* These are handled automatically by the stack marking code */
6952                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6953                         } else {
6954                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6955                                 // FIXME: GC
6956                         }
6957
6958                         save_area_offset += 8;
6959                         async_exc_point (code);
6960                 }
6961         }
6962
6963         /* store runtime generic context */
6964         if (cfg->rgctx_var) {
6965                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6966                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6967
6968                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6969
6970                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6971                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6972         }
6973
6974         /* compute max_length in order to use short forward jumps */
6975         max_epilog_size = get_max_epilog_size (cfg);
6976         if (cfg->opt & MONO_OPT_BRANCH) {
6977                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6978                         MonoInst *ins;
6979                         int max_length = 0;
6980
6981                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6982                                 max_length += 6;
6983                         /* max alignment for loops */
6984                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6985                                 max_length += LOOP_ALIGNMENT;
6986 #ifdef __native_client_codegen__
6987                         /* max alignment for native client */
6988                         max_length += kNaClAlignment;
6989 #endif
6990
6991                         MONO_BB_FOR_EACH_INS (bb, ins) {
6992 #ifdef __native_client_codegen__
6993                                 {
6994                                         int space_in_block = kNaClAlignment -
6995                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6996                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6997                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6998                                                 max_length += space_in_block;
6999                                         }
7000                                 }
7001 #endif  /*__native_client_codegen__*/
7002                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7003                         }
7004
7005                         /* Take prolog and epilog instrumentation into account */
7006                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7007                                 max_length += max_epilog_size;
7008
7009                         bb->max_length = max_length;
7010                 }
7011         }
7012
7013         sig = mono_method_signature (method);
7014         pos = 0;
7015
7016         cinfo = cfg->arch.cinfo;
7017
7018         if (sig->ret->type != MONO_TYPE_VOID) {
7019                 /* Save volatile arguments to the stack */
7020                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7021                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7022         }
7023
7024         /* Keep this in sync with emit_load_volatile_arguments */
7025         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7026                 ArgInfo *ainfo = cinfo->args + i;
7027                 gint32 stack_offset;
7028                 MonoType *arg_type;
7029
7030                 ins = cfg->args [i];
7031
7032                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7033                         /* Unused arguments */
7034                         continue;
7035
7036                 if (sig->hasthis && (i == 0))
7037                         arg_type = &mono_defaults.object_class->byval_arg;
7038                 else
7039                         arg_type = sig->params [i - sig->hasthis];
7040
7041                 stack_offset = ainfo->offset + ARGS_OFFSET;
7042
7043                 if (cfg->globalra) {
7044                         /* All the other moves are done by the register allocator */
7045                         switch (ainfo->storage) {
7046                         case ArgInFloatSSEReg:
7047                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
7048                                 break;
7049                         case ArgValuetypeInReg:
7050                                 for (quad = 0; quad < 2; quad ++) {
7051                                         switch (ainfo->pair_storage [quad]) {
7052                                         case ArgInIReg:
7053                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7054                                                 break;
7055                                         case ArgInFloatSSEReg:
7056                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7057                                                 break;
7058                                         case ArgInDoubleSSEReg:
7059                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7060                                                 break;
7061                                         case ArgNone:
7062                                                 break;
7063                                         default:
7064                                                 g_assert_not_reached ();
7065                                         }
7066                                 }
7067                                 break;
7068                         default:
7069                                 break;
7070                         }
7071
7072                         continue;
7073                 }
7074
7075                 /* Save volatile arguments to the stack */
7076                 if (ins->opcode != OP_REGVAR) {
7077                         switch (ainfo->storage) {
7078                         case ArgInIReg: {
7079                                 guint32 size = 8;
7080
7081                                 /* FIXME: I1 etc */
7082                                 /*
7083                                 if (stack_offset & 0x1)
7084                                         size = 1;
7085                                 else if (stack_offset & 0x2)
7086                                         size = 2;
7087                                 else if (stack_offset & 0x4)
7088                                         size = 4;
7089                                 else
7090                                         size = 8;
7091                                 */
7092                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7093
7094                                 /*
7095                                  * Save the original location of 'this',
7096                                  * get_generic_info_from_stack_frame () needs this to properly look up
7097                                  * the argument value during the handling of async exceptions.
7098                                  */
7099                                 if (ins == cfg->args [0]) {
7100                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7101                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7102                                 }
7103                                 break;
7104                         }
7105                         case ArgInFloatSSEReg:
7106                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7107                                 break;
7108                         case ArgInDoubleSSEReg:
7109                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7110                                 break;
7111                         case ArgValuetypeInReg:
7112                                 for (quad = 0; quad < 2; quad ++) {
7113                                         switch (ainfo->pair_storage [quad]) {
7114                                         case ArgInIReg:
7115                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7116                                                 break;
7117                                         case ArgInFloatSSEReg:
7118                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7119                                                 break;
7120                                         case ArgInDoubleSSEReg:
7121                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7122                                                 break;
7123                                         case ArgNone:
7124                                                 break;
7125                                         default:
7126                                                 g_assert_not_reached ();
7127                                         }
7128                                 }
7129                                 break;
7130                         case ArgValuetypeAddrInIReg:
7131                                 if (ainfo->pair_storage [0] == ArgInIReg)
7132                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7133                                 break;
7134                         default:
7135                                 break;
7136                         }
7137                 } else {
7138                         /* Argument allocated to (non-volatile) register */
7139                         switch (ainfo->storage) {
7140                         case ArgInIReg:
7141                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7142                                 break;
7143                         case ArgOnStack:
7144                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7145                                 break;
7146                         default:
7147                                 g_assert_not_reached ();
7148                         }
7149
7150                         if (ins == cfg->args [0]) {
7151                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7152                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7153                         }
7154                 }
7155         }
7156
7157         if (cfg->method->save_lmf)
7158                 args_clobbered = TRUE;
7159
7160         if (trace) {
7161                 args_clobbered = TRUE;
7162                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7163         }
7164
7165         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7166                 args_clobbered = TRUE;
7167
7168         /*
7169          * Optimize the common case of the first bblock making a call with the same
7170          * arguments as the method. This works because the arguments are still in their
7171          * original argument registers.
7172          * FIXME: Generalize this
7173          */
7174         if (!args_clobbered) {
7175                 MonoBasicBlock *first_bb = cfg->bb_entry;
7176                 MonoInst *next;
7177                 int filter = FILTER_IL_SEQ_POINT;
7178
7179                 next = mono_bb_first_inst (first_bb, filter);
7180                 if (!next && first_bb->next_bb) {
7181                         first_bb = first_bb->next_bb;
7182                         next = mono_bb_first_inst (first_bb, filter);
7183                 }
7184
7185                 if (first_bb->in_count > 1)
7186                         next = NULL;
7187
7188                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7189                         ArgInfo *ainfo = cinfo->args + i;
7190                         gboolean match = FALSE;
7191
7192                         ins = cfg->args [i];
7193                         if (ins->opcode != OP_REGVAR) {
7194                                 switch (ainfo->storage) {
7195                                 case ArgInIReg: {
7196                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7197                                                 if (next->dreg == ainfo->reg) {
7198                                                         NULLIFY_INS (next);
7199                                                         match = TRUE;
7200                                                 } else {
7201                                                         next->opcode = OP_MOVE;
7202                                                         next->sreg1 = ainfo->reg;
7203                                                         /* Only continue if the instruction doesn't change argument regs */
7204                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7205                                                                 match = TRUE;
7206                                                 }
7207                                         }
7208                                         break;
7209                                 }
7210                                 default:
7211                                         break;
7212                                 }
7213                         } else {
7214                                 /* Argument allocated to (non-volatile) register */
7215                                 switch (ainfo->storage) {
7216                                 case ArgInIReg:
7217                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7218                                                 NULLIFY_INS (next);
7219                                                 match = TRUE;
7220                                         }
7221                                         break;
7222                                 default:
7223                                         break;
7224                                 }
7225                         }
7226
7227                         if (match) {
7228                                 next = mono_inst_next (next, filter);
7229                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7230                                 if (!next)
7231                                         break;
7232                         }
7233                 }
7234         }
7235
7236         if (cfg->gen_seq_points_debug_data) {
7237                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7238
7239                 /* Initialize seq_point_info_var */
7240                 if (cfg->compile_aot) {
7241                         /* Initialize the variable from a GOT slot */
7242                         /* Same as OP_AOTCONST */
7243                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7244                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7245                         g_assert (info_var->opcode == OP_REGOFFSET);
7246                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7247                 }
7248
7249                 /* Initialize ss_trigger_page_var */
7250                 ins = cfg->arch.ss_trigger_page_var;
7251
7252                 g_assert (ins->opcode == OP_REGOFFSET);
7253
7254                 if (cfg->compile_aot) {
7255                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7256                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7257                 } else {
7258                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7259                 }
7260                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7261         }
7262
7263         cfg->code_len = code - cfg->native_code;
7264
7265         g_assert (cfg->code_len < cfg->code_size);
7266
7267         return code;
7268 }
7269
7270 void
7271 mono_arch_emit_epilog (MonoCompile *cfg)
7272 {
7273         MonoMethod *method = cfg->method;
7274         int quad, pos, i;
7275         guint8 *code;
7276         int max_epilog_size;
7277         CallInfo *cinfo;
7278         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7279         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7280
7281         max_epilog_size = get_max_epilog_size (cfg);
7282
7283         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7284                 cfg->code_size *= 2;
7285                 cfg->native_code = mono_realloc_native_code (cfg);
7286                 cfg->stat_code_reallocs++;
7287         }
7288         code = cfg->native_code + cfg->code_len;
7289
7290         cfg->has_unwind_info_for_epilog = TRUE;
7291
7292         /* Mark the start of the epilog */
7293         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7294
7295         /* Save the uwind state which is needed by the out-of-line code */
7296         mono_emit_unwind_op_remember_state (cfg, code);
7297
7298         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7299                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7300
7301         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7302         pos = 0;
7303
7304         if (method->save_lmf) {
7305                 /* check if we need to restore protection of the stack after a stack overflow */
7306                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7307                         guint8 *patch;
7308                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7309                         /* we load the value in a separate instruction: this mechanism may be
7310                          * used later as a safer way to do thread interruption
7311                          */
7312                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7313                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7314                         patch = code;
7315                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7316                         /* note that the call trampoline will preserve eax/edx */
7317                         x86_call_reg (code, X86_ECX);
7318                         x86_patch (patch, code);
7319                 } else {
7320                         /* FIXME: maybe save the jit tls in the prolog */
7321                 }
7322                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7323                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7324                 }
7325         }
7326
7327         /* Restore callee saved regs */
7328         for (i = 0; i < AMD64_NREG; ++i) {
7329                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7330                         /* Restore only used_int_regs, not arch.saved_iregs */
7331                         if (cfg->used_int_regs & (1 << i)) {
7332                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7333                                 mono_emit_unwind_op_same_value (cfg, code, i);
7334                                 async_exc_point (code);
7335                         }
7336                         save_area_offset += 8;
7337                 }
7338         }
7339
7340         /* Load returned vtypes into registers if needed */
7341         cinfo = cfg->arch.cinfo;
7342         if (cinfo->ret.storage == ArgValuetypeInReg) {
7343                 ArgInfo *ainfo = &cinfo->ret;
7344                 MonoInst *inst = cfg->ret;
7345
7346                 for (quad = 0; quad < 2; quad ++) {
7347                         switch (ainfo->pair_storage [quad]) {
7348                         case ArgInIReg:
7349                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7350                                 break;
7351                         case ArgInFloatSSEReg:
7352                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7353                                 break;
7354                         case ArgInDoubleSSEReg:
7355                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7356                                 break;
7357                         case ArgNone:
7358                                 break;
7359                         default:
7360                                 g_assert_not_reached ();
7361                         }
7362                 }
7363         }
7364
7365         if (cfg->arch.omit_fp) {
7366                 if (cfg->arch.stack_alloc_size) {
7367                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7368                 }
7369         } else {
7370                 amd64_leave (code);
7371                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7372         }
7373         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7374         async_exc_point (code);
7375         amd64_ret (code);
7376
7377         /* Restore the unwind state to be the same as before the epilog */
7378         mono_emit_unwind_op_restore_state (cfg, code);
7379
7380         cfg->code_len = code - cfg->native_code;
7381
7382         g_assert (cfg->code_len < cfg->code_size);
7383 }
7384
7385 void
7386 mono_arch_emit_exceptions (MonoCompile *cfg)
7387 {
7388         MonoJumpInfo *patch_info;
7389         int nthrows, i;
7390         guint8 *code;
7391         MonoClass *exc_classes [16];
7392         guint8 *exc_throw_start [16], *exc_throw_end [16];
7393         guint32 code_size = 0;
7394
7395         /* Compute needed space */
7396         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7397                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7398                         code_size += 40;
7399                 if (patch_info->type == MONO_PATCH_INFO_R8)
7400                         code_size += 8 + 15; /* sizeof (double) + alignment */
7401                 if (patch_info->type == MONO_PATCH_INFO_R4)
7402                         code_size += 4 + 15; /* sizeof (float) + alignment */
7403                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7404                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7405         }
7406
7407 #ifdef __native_client_codegen__
7408         /* Give us extra room on Native Client.  This could be   */
7409         /* more carefully calculated, but bundle alignment makes */
7410         /* it much trickier, so *2 like other places is good.    */
7411         code_size *= 2;
7412 #endif
7413
7414         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7415                 cfg->code_size *= 2;
7416                 cfg->native_code = mono_realloc_native_code (cfg);
7417                 cfg->stat_code_reallocs++;
7418         }
7419
7420         code = cfg->native_code + cfg->code_len;
7421
7422         /* add code to raise exceptions */
7423         nthrows = 0;
7424         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7425                 switch (patch_info->type) {
7426                 case MONO_PATCH_INFO_EXC: {
7427                         MonoClass *exc_class;
7428                         guint8 *buf, *buf2;
7429                         guint32 throw_ip;
7430
7431                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7432
7433                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7434                         g_assert (exc_class);
7435                         throw_ip = patch_info->ip.i;
7436
7437                         //x86_breakpoint (code);
7438                         /* Find a throw sequence for the same exception class */
7439                         for (i = 0; i < nthrows; ++i)
7440                                 if (exc_classes [i] == exc_class)
7441                                         break;
7442                         if (i < nthrows) {
7443                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7444                                 x86_jump_code (code, exc_throw_start [i]);
7445                                 patch_info->type = MONO_PATCH_INFO_NONE;
7446                         }
7447                         else {
7448                                 buf = code;
7449                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7450                                 buf2 = code;
7451
7452                                 if (nthrows < 16) {
7453                                         exc_classes [nthrows] = exc_class;
7454                                         exc_throw_start [nthrows] = code;
7455                                 }
7456                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7457
7458                                 patch_info->type = MONO_PATCH_INFO_NONE;
7459
7460                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7461
7462                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7463                                 while (buf < buf2)
7464                                         x86_nop (buf);
7465
7466                                 if (nthrows < 16) {
7467                                         exc_throw_end [nthrows] = code;
7468                                         nthrows ++;
7469                                 }
7470                         }
7471                         break;
7472                 }
7473                 default:
7474                         /* do nothing */
7475                         break;
7476                 }
7477                 g_assert(code < cfg->native_code + cfg->code_size);
7478         }
7479
7480         /* Handle relocations with RIP relative addressing */
7481         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7482                 gboolean remove = FALSE;
7483                 guint8 *orig_code = code;
7484
7485                 switch (patch_info->type) {
7486                 case MONO_PATCH_INFO_R8:
7487                 case MONO_PATCH_INFO_R4: {
7488                         guint8 *pos, *patch_pos;
7489                         guint32 target_pos;
7490
7491                         /* The SSE opcodes require a 16 byte alignment */
7492 #if defined(__default_codegen__)
7493                         code = (guint8*)ALIGN_TO (code, 16);
7494 #elif defined(__native_client_codegen__)
7495                         {
7496                                 /* Pad this out with HLT instructions  */
7497                                 /* or we can get garbage bytes emitted */
7498                                 /* which will fail validation          */
7499                                 guint8 *aligned_code;
7500                                 /* extra align to make room for  */
7501                                 /* mov/push below                      */
7502                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7503                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7504                                 /* The technique of hiding data in an  */
7505                                 /* instruction has a problem here: we  */
7506                                 /* need the data aligned to a 16-byte  */
7507                                 /* boundary but the instruction cannot */
7508                                 /* cross the bundle boundary. so only  */
7509                                 /* odd multiples of 16 can be used     */
7510                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7511                                         aligned_code += 16;
7512                                 }
7513                                 while (code < aligned_code) {
7514                                         *(code++) = 0xf4; /* hlt */
7515                                 }
7516                         }
7517 #endif
7518
7519                         pos = cfg->native_code + patch_info->ip.i;
7520                         if (IS_REX (pos [1])) {
7521                                 patch_pos = pos + 5;
7522                                 target_pos = code - pos - 9;
7523                         }
7524                         else {
7525                                 patch_pos = pos + 4;
7526                                 target_pos = code - pos - 8;
7527                         }
7528
7529                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7530 #ifdef __native_client_codegen__
7531                                 /* Hide 64-bit data in a         */
7532                                 /* "mov imm64, r11" instruction. */
7533                                 /* write it before the start of  */
7534                                 /* the data*/
7535                                 *(code-2) = 0x49; /* prefix      */
7536                                 *(code-1) = 0xbb; /* mov X, %r11 */
7537 #endif
7538                                 *(double*)code = *(double*)patch_info->data.target;
7539                                 code += sizeof (double);
7540                         } else {
7541 #ifdef __native_client_codegen__
7542                                 /* Hide 32-bit data in a        */
7543                                 /* "push imm32" instruction.    */
7544                                 *(code-1) = 0x68; /* push */
7545 #endif
7546                                 *(float*)code = *(float*)patch_info->data.target;
7547                                 code += sizeof (float);
7548                         }
7549
7550                         *(guint32*)(patch_pos) = target_pos;
7551
7552                         remove = TRUE;
7553                         break;
7554                 }
7555                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7556                         guint8 *pos;
7557
7558                         if (cfg->compile_aot)
7559                                 continue;
7560
7561                         /*loading is faster against aligned addresses.*/
7562                         code = (guint8*)ALIGN_TO (code, 8);
7563                         memset (orig_code, 0, code - orig_code);
7564
7565                         pos = cfg->native_code + patch_info->ip.i;
7566
7567                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7568                         if (IS_REX (pos [1]))
7569                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7570                         else
7571                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7572
7573                         *(gpointer*)code = (gpointer)patch_info->data.target;
7574                         code += sizeof (gpointer);
7575
7576                         remove = TRUE;
7577                         break;
7578                 }
7579                 default:
7580                         break;
7581                 }
7582
7583                 if (remove) {
7584                         if (patch_info == cfg->patch_info)
7585                                 cfg->patch_info = patch_info->next;
7586                         else {
7587                                 MonoJumpInfo *tmp;
7588
7589                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7590                                         ;
7591                                 tmp->next = patch_info->next;
7592                         }
7593                 }
7594                 g_assert (code < cfg->native_code + cfg->code_size);
7595         }
7596
7597         cfg->code_len = code - cfg->native_code;
7598
7599         g_assert (cfg->code_len < cfg->code_size);
7600
7601 }
7602
7603 #endif /* DISABLE_JIT */
7604
7605 void*
7606 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7607 {
7608         guchar *code = p;
7609         CallInfo *cinfo = NULL;
7610         MonoMethodSignature *sig;
7611         MonoInst *inst;
7612         int i, n, stack_area = 0;
7613
7614         /* Keep this in sync with mono_arch_get_argument_info */
7615
7616         if (enable_arguments) {
7617                 /* Allocate a new area on the stack and save arguments there */
7618                 sig = mono_method_signature (cfg->method);
7619
7620                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7621
7622                 n = sig->param_count + sig->hasthis;
7623
7624                 stack_area = ALIGN_TO (n * 8, 16);
7625
7626                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7627
7628                 for (i = 0; i < n; ++i) {
7629                         inst = cfg->args [i];
7630
7631                         if (inst->opcode == OP_REGVAR)
7632                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7633                         else {
7634                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7635                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7636                         }
7637                 }
7638         }
7639
7640         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7641         amd64_set_reg_template (code, AMD64_ARG_REG1);
7642         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7643         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7644
7645         if (enable_arguments)
7646                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7647
7648         return code;
7649 }
7650
7651 enum {
7652         SAVE_NONE,
7653         SAVE_STRUCT,
7654         SAVE_EAX,
7655         SAVE_EAX_EDX,
7656         SAVE_XMM
7657 };
7658
7659 void*
7660 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7661 {
7662         guchar *code = p;
7663         int save_mode = SAVE_NONE;
7664         MonoMethod *method = cfg->method;
7665         MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7666         int i;
7667
7668         switch (ret_type->type) {
7669         case MONO_TYPE_VOID:
7670                 /* special case string .ctor icall */
7671                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7672                         save_mode = SAVE_EAX;
7673                 else
7674                         save_mode = SAVE_NONE;
7675                 break;
7676         case MONO_TYPE_I8:
7677         case MONO_TYPE_U8:
7678                 save_mode = SAVE_EAX;
7679                 break;
7680         case MONO_TYPE_R4:
7681         case MONO_TYPE_R8:
7682                 save_mode = SAVE_XMM;
7683                 break;
7684         case MONO_TYPE_GENERICINST:
7685                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7686                         save_mode = SAVE_EAX;
7687                         break;
7688                 }
7689                 /* Fall through */
7690         case MONO_TYPE_VALUETYPE:
7691                 save_mode = SAVE_STRUCT;
7692                 break;
7693         default:
7694                 save_mode = SAVE_EAX;
7695                 break;
7696         }
7697
7698         /* Save the result and copy it into the proper argument register */
7699         switch (save_mode) {
7700         case SAVE_EAX:
7701                 amd64_push_reg (code, AMD64_RAX);
7702                 /* Align stack */
7703                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7704                 if (enable_arguments)
7705                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7706                 break;
7707         case SAVE_STRUCT:
7708                 /* FIXME: */
7709                 if (enable_arguments)
7710                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7711                 break;
7712         case SAVE_XMM:
7713                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7714                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7715                 /* Align stack */
7716                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7717                 /*
7718                  * The result is already in the proper argument register so no copying
7719                  * needed.
7720                  */
7721                 break;
7722         case SAVE_NONE:
7723                 break;
7724         default:
7725                 g_assert_not_reached ();
7726         }
7727
7728         /* Set %al since this is a varargs call */
7729         if (save_mode == SAVE_XMM)
7730                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7731         else
7732                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7733
7734         if (preserve_argument_registers) {
7735                 for (i = 0; i < PARAM_REGS; ++i)
7736                         amd64_push_reg (code, param_regs [i]);
7737         }
7738
7739         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7740         amd64_set_reg_template (code, AMD64_ARG_REG1);
7741         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7742
7743         if (preserve_argument_registers) {
7744                 for (i = PARAM_REGS - 1; i >= 0; --i)
7745                         amd64_pop_reg (code, param_regs [i]);
7746         }
7747
7748         /* Restore result */
7749         switch (save_mode) {
7750         case SAVE_EAX:
7751                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7752                 amd64_pop_reg (code, AMD64_RAX);
7753                 break;
7754         case SAVE_STRUCT:
7755                 /* FIXME: */
7756                 break;
7757         case SAVE_XMM:
7758                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7759                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7760                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7761                 break;
7762         case SAVE_NONE:
7763                 break;
7764         default:
7765                 g_assert_not_reached ();
7766         }
7767
7768         return code;
7769 }
7770
7771 void
7772 mono_arch_flush_icache (guint8 *code, gint size)
7773 {
7774         /* Not needed */
7775 }
7776
7777 void
7778 mono_arch_flush_register_windows (void)
7779 {
7780 }
7781
7782 gboolean
7783 mono_arch_is_inst_imm (gint64 imm)
7784 {
7785         return amd64_is_imm32 (imm);
7786 }
7787
7788 /*
7789  * Determine whenever the trap whose info is in SIGINFO is caused by
7790  * integer overflow.
7791  */
7792 gboolean
7793 mono_arch_is_int_overflow (void *sigctx, void *info)
7794 {
7795         MonoContext ctx;
7796         guint8* rip;
7797         int reg;
7798         gint64 value;
7799
7800         mono_sigctx_to_monoctx (sigctx, &ctx);
7801
7802         rip = (guint8*)ctx.rip;
7803
7804         if (IS_REX (rip [0])) {
7805                 reg = amd64_rex_b (rip [0]);
7806                 rip ++;
7807         }
7808         else
7809                 reg = 0;
7810
7811         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7812                 /* idiv REG */
7813                 reg += x86_modrm_rm (rip [1]);
7814
7815                 switch (reg) {
7816                 case AMD64_RAX:
7817                         value = ctx.rax;
7818                         break;
7819                 case AMD64_RBX:
7820                         value = ctx.rbx;
7821                         break;
7822                 case AMD64_RCX:
7823                         value = ctx.rcx;
7824                         break;
7825                 case AMD64_RDX:
7826                         value = ctx.rdx;
7827                         break;
7828                 case AMD64_RBP:
7829                         value = ctx.rbp;
7830                         break;
7831                 case AMD64_RSP:
7832                         value = ctx.rsp;
7833                         break;
7834                 case AMD64_RSI:
7835                         value = ctx.rsi;
7836                         break;
7837                 case AMD64_RDI:
7838                         value = ctx.rdi;
7839                         break;
7840                 case AMD64_R12:
7841                         value = ctx.r12;
7842                         break;
7843                 case AMD64_R13:
7844                         value = ctx.r13;
7845                         break;
7846                 case AMD64_R14:
7847                         value = ctx.r14;
7848                         break;
7849                 case AMD64_R15:
7850                         value = ctx.r15;
7851                         break;
7852                 default:
7853                         g_assert_not_reached ();
7854                         reg = -1;
7855                 }
7856
7857                 if (value == -1)
7858                         return TRUE;
7859         }
7860
7861         return FALSE;
7862 }
7863
7864 guint32
7865 mono_arch_get_patch_offset (guint8 *code)
7866 {
7867         return 3;
7868 }
7869
7870 /**
7871  * mono_breakpoint_clean_code:
7872  *
7873  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7874  * breakpoints in the original code, they are removed in the copy.
7875  *
7876  * Returns TRUE if no sw breakpoint was present.
7877  */
7878 gboolean
7879 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7880 {
7881         /*
7882          * If method_start is non-NULL we need to perform bound checks, since we access memory
7883          * at code - offset we could go before the start of the method and end up in a different
7884          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7885          * instead.
7886          */
7887         if (!method_start || code - offset >= method_start) {
7888                 memcpy (buf, code - offset, size);
7889         } else {
7890                 int diff = code - method_start;
7891                 memset (buf, 0, size);
7892                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7893         }
7894         return TRUE;
7895 }
7896
7897 #if defined(__native_client_codegen__)
7898 /* For membase calls, we want the base register. for Native Client,  */
7899 /* all indirect calls have the following sequence with the given sizes: */
7900 /* mov %eXX,%eXX                                [2-3]   */
7901 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7902 /* and $0xffffffffffffffe0,%r11d                [4]     */
7903 /* add %r15,%r11                                [3]     */
7904 /* callq *%r11                                  [3]     */
7905
7906
7907 /* Determine if code points to a NaCl call-through-register sequence, */
7908 /* (i.e., the last 3 instructions listed above) */
7909 int
7910 is_nacl_call_reg_sequence(guint8* code)
7911 {
7912         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7913                                "\x4d\x03\xdf"     /* add */
7914                                "\x41\xff\xd3";   /* call */
7915         return memcmp(code, sequence, 10) == 0;
7916 }
7917
7918 /* Determine if code points to the first opcode of the mov membase component */
7919 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7920 /* (there could be a REX prefix before the opcode but it is ignored) */
7921 static int
7922 is_nacl_indirect_call_membase_sequence(guint8* code)
7923 {
7924                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7925         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7926                /* and that src reg = dest reg */
7927                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7928                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7929                IS_REX(code[2]) &&
7930                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7931                /* and has dst of r11 and base of r15 */
7932                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7933                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7934 }
7935 #endif /* __native_client_codegen__ */
7936
7937 int
7938 mono_arch_get_this_arg_reg (guint8 *code)
7939 {
7940         return AMD64_ARG_REG1;
7941 }
7942
7943 gpointer
7944 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7945 {
7946         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7947 }
7948
7949 #define MAX_ARCH_DELEGATE_PARAMS 10
7950
7951 static gpointer
7952 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7953 {
7954         guint8 *code, *start;
7955         int i;
7956
7957         if (has_target) {
7958                 start = code = mono_global_codeman_reserve (64);
7959
7960                 /* Replace the this argument with the target */
7961                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7962                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7963                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7964
7965                 g_assert ((code - start) < 64);
7966         } else {
7967                 start = code = mono_global_codeman_reserve (64);
7968
7969                 if (param_count == 0) {
7970                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7971                 } else {
7972                         /* We have to shift the arguments left */
7973                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7974                         for (i = 0; i < param_count; ++i) {
7975 #ifdef HOST_WIN32
7976                                 if (i < 3)
7977                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7978                                 else
7979                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7980 #else
7981                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7982 #endif
7983                         }
7984
7985                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7986                 }
7987                 g_assert ((code - start) < 64);
7988         }
7989
7990         nacl_global_codeman_validate (&start, 64, &code);
7991
7992         if (code_len)
7993                 *code_len = code - start;
7994
7995         if (mono_jit_map_is_enabled ()) {
7996                 char *buff;
7997                 if (has_target)
7998                         buff = (char*)"delegate_invoke_has_target";
7999                 else
8000                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8001                 mono_emit_jit_tramp (start, code - start, buff);
8002                 if (!has_target)
8003                         g_free (buff);
8004         }
8005         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8006
8007         return start;
8008 }
8009
8010 /*
8011  * mono_arch_get_delegate_invoke_impls:
8012  *
8013  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8014  * trampolines.
8015  */
8016 GSList*
8017 mono_arch_get_delegate_invoke_impls (void)
8018 {
8019         GSList *res = NULL;
8020         guint8 *code;
8021         guint32 code_len;
8022         int i;
8023         char *tramp_name;
8024
8025         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
8026         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
8027
8028         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
8029                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
8030                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
8031                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
8032                 g_free (tramp_name);
8033         }
8034
8035         return res;
8036 }
8037
8038 gpointer
8039 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8040 {
8041         guint8 *code, *start;
8042         int i;
8043
8044         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8045                 return NULL;
8046
8047         /* FIXME: Support more cases */
8048         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
8049                 return NULL;
8050
8051         if (has_target) {
8052                 static guint8* cached = NULL;
8053
8054                 if (cached)
8055                         return cached;
8056
8057                 if (mono_aot_only)
8058                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8059                 else
8060                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
8061
8062                 mono_memory_barrier ();
8063
8064                 cached = start;
8065         } else {
8066                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8067                 for (i = 0; i < sig->param_count; ++i)
8068                         if (!mono_is_regsize_var (sig->params [i]))
8069                                 return NULL;
8070                 if (sig->param_count > 4)
8071                         return NULL;
8072
8073                 code = cache [sig->param_count];
8074                 if (code)
8075                         return code;
8076
8077                 if (mono_aot_only) {
8078                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8079                         start = mono_aot_get_trampoline (name);
8080                         g_free (name);
8081                 } else {
8082                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8083                 }
8084
8085                 mono_memory_barrier ();
8086
8087                 cache [sig->param_count] = start;
8088         }
8089
8090         return start;
8091 }
8092
8093 gpointer
8094 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8095 {
8096         guint8 *code, *start;
8097         int size = 20;
8098
8099         start = code = mono_global_codeman_reserve (size);
8100
8101         /* Replace the this argument with the target */
8102         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8103         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8104
8105         if (load_imt_reg) {
8106                 /* Load the IMT reg */
8107                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8108         }
8109
8110         /* Load the vtable */
8111         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8112         amd64_jump_membase (code, AMD64_RAX, offset);
8113         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8114
8115         return start;
8116 }
8117
8118 void
8119 mono_arch_finish_init (void)
8120 {
8121 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8122         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8123 #endif
8124 }
8125
8126 void
8127 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8128 {
8129 }
8130
8131 #if defined(__default_codegen__)
8132 #define CMP_SIZE (6 + 1)
8133 #define CMP_REG_REG_SIZE (4 + 1)
8134 #define BR_SMALL_SIZE 2
8135 #define BR_LARGE_SIZE 6
8136 #define MOV_REG_IMM_SIZE 10
8137 #define MOV_REG_IMM_32BIT_SIZE 6
8138 #define JUMP_REG_SIZE (2 + 1)
8139 #elif defined(__native_client_codegen__)
8140 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8141 #define CMP_SIZE ((6 + 1) * 2 - 1)
8142 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8143 #define BR_SMALL_SIZE (2 * 2 - 1)
8144 #define BR_LARGE_SIZE (6 * 2 - 1)
8145 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8146 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8147 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8148 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8149 /* Jump membase's size is large and unpredictable    */
8150 /* in native client, just pad it out a whole bundle. */
8151 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8152 #endif
8153
8154 static int
8155 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8156 {
8157         int i, distance = 0;
8158         for (i = start; i < target; ++i)
8159                 distance += imt_entries [i]->chunk_size;
8160         return distance;
8161 }
8162
8163 /*
8164  * LOCKING: called with the domain lock held
8165  */
8166 gpointer
8167 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8168         gpointer fail_tramp)
8169 {
8170         int i;
8171         int size = 0;
8172         guint8 *code, *start;
8173         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8174
8175         for (i = 0; i < count; ++i) {
8176                 MonoIMTCheckItem *item = imt_entries [i];
8177                 if (item->is_equals) {
8178                         if (item->check_target_idx) {
8179                                 if (!item->compare_done) {
8180                                         if (amd64_is_imm32 (item->key))
8181                                                 item->chunk_size += CMP_SIZE;
8182                                         else
8183                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8184                                 }
8185                                 if (item->has_target_code) {
8186                                         item->chunk_size += MOV_REG_IMM_SIZE;
8187                                 } else {
8188                                         if (vtable_is_32bit)
8189                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8190                                         else
8191                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8192 #ifdef __native_client_codegen__
8193                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8194 #endif
8195                                 }
8196                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8197                         } else {
8198                                 if (fail_tramp) {
8199                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8200                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8201                                 } else {
8202                                         if (vtable_is_32bit)
8203                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8204                                         else
8205                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8206                                         item->chunk_size += JUMP_REG_SIZE;
8207                                         /* with assert below:
8208                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8209                                          */
8210 #ifdef __native_client_codegen__
8211                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8212 #endif
8213                                 }
8214                         }
8215                 } else {
8216                         if (amd64_is_imm32 (item->key))
8217                                 item->chunk_size += CMP_SIZE;
8218                         else
8219                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8220                         item->chunk_size += BR_LARGE_SIZE;
8221                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8222                 }
8223                 size += item->chunk_size;
8224         }
8225 #if defined(__native_client__) && defined(__native_client_codegen__)
8226         /* In Native Client, we don't re-use thunks, allocate from the */
8227         /* normal code manager paths. */
8228         code = mono_domain_code_reserve (domain, size);
8229 #else
8230         if (fail_tramp)
8231                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8232         else
8233                 code = mono_domain_code_reserve (domain, size);
8234 #endif
8235         start = code;
8236         for (i = 0; i < count; ++i) {
8237                 MonoIMTCheckItem *item = imt_entries [i];
8238                 item->code_target = code;
8239                 if (item->is_equals) {
8240                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8241
8242                         if (item->check_target_idx || fail_case) {
8243                                 if (!item->compare_done || fail_case) {
8244                                         if (amd64_is_imm32 (item->key))
8245                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8246                                         else {
8247                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8248                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8249                                         }
8250                                 }
8251                                 item->jmp_code = code;
8252                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8253                                 if (item->has_target_code) {
8254                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8255                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8256                                 } else {
8257                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8258                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8259                                 }
8260
8261                                 if (fail_case) {
8262                                         amd64_patch (item->jmp_code, code);
8263                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8264                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8265                                         item->jmp_code = NULL;
8266                                 }
8267                         } else {
8268                                 /* enable the commented code to assert on wrong method */
8269 #if 0
8270                                 if (amd64_is_imm32 (item->key))
8271                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8272                                 else {
8273                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8274                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8275                                 }
8276                                 item->jmp_code = code;
8277                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8278                                 /* See the comment below about R10 */
8279                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8280                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8281                                 amd64_patch (item->jmp_code, code);
8282                                 amd64_breakpoint (code);
8283                                 item->jmp_code = NULL;
8284 #else
8285                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8286                                    needs to be preserved.  R10 needs
8287                                    to be preserved for calls which
8288                                    require a runtime generic context,
8289                                    but interface calls don't. */
8290                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8291                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8292 #endif
8293                         }
8294                 } else {
8295                         if (amd64_is_imm32 (item->key))
8296                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8297                         else {
8298                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8299                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8300                         }
8301                         item->jmp_code = code;
8302                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8303                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8304                         else
8305                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8306                 }
8307                 g_assert (code - item->code_target <= item->chunk_size);
8308         }
8309         /* patch the branches to get to the target items */
8310         for (i = 0; i < count; ++i) {
8311                 MonoIMTCheckItem *item = imt_entries [i];
8312                 if (item->jmp_code) {
8313                         if (item->check_target_idx) {
8314                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8315                         }
8316                 }
8317         }
8318
8319         if (!fail_tramp)
8320                 mono_stats.imt_thunks_size += code - start;
8321         g_assert (code - start <= size);
8322
8323         nacl_domain_code_validate(domain, &start, size, &code);
8324         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8325
8326         return start;
8327 }
8328
8329 MonoMethod*
8330 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8331 {
8332         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8333 }
8334
8335 MonoVTable*
8336 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8337 {
8338         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8339 }
8340
8341 GSList*
8342 mono_arch_get_cie_program (void)
8343 {
8344         GSList *l = NULL;
8345
8346         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8347         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8348
8349         return l;
8350 }
8351
8352 #ifndef DISABLE_JIT
8353
8354 MonoInst*
8355 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8356 {
8357         MonoInst *ins = NULL;
8358         int opcode = 0;
8359
8360         if (cmethod->klass == mono_defaults.math_class) {
8361                 if (strcmp (cmethod->name, "Sin") == 0) {
8362                         opcode = OP_SIN;
8363                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8364                         opcode = OP_COS;
8365                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8366                         opcode = OP_SQRT;
8367                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8368                         opcode = OP_ABS;
8369                 }
8370
8371                 if (opcode && fsig->param_count == 1) {
8372                         MONO_INST_NEW (cfg, ins, opcode);
8373                         ins->type = STACK_R8;
8374                         ins->dreg = mono_alloc_freg (cfg);
8375                         ins->sreg1 = args [0]->dreg;
8376                         MONO_ADD_INS (cfg->cbb, ins);
8377                 }
8378
8379                 opcode = 0;
8380                 if (cfg->opt & MONO_OPT_CMOV) {
8381                         if (strcmp (cmethod->name, "Min") == 0) {
8382                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8383                                         opcode = OP_IMIN;
8384                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8385                                         opcode = OP_IMIN_UN;
8386                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8387                                         opcode = OP_LMIN;
8388                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8389                                         opcode = OP_LMIN_UN;
8390                         } else if (strcmp (cmethod->name, "Max") == 0) {
8391                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8392                                         opcode = OP_IMAX;
8393                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8394                                         opcode = OP_IMAX_UN;
8395                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8396                                         opcode = OP_LMAX;
8397                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8398                                         opcode = OP_LMAX_UN;
8399                         }
8400                 }
8401
8402                 if (opcode && fsig->param_count == 2) {
8403                         MONO_INST_NEW (cfg, ins, opcode);
8404                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8405                         ins->dreg = mono_alloc_ireg (cfg);
8406                         ins->sreg1 = args [0]->dreg;
8407                         ins->sreg2 = args [1]->dreg;
8408                         MONO_ADD_INS (cfg->cbb, ins);
8409                 }
8410
8411 #if 0
8412                 /* OP_FREM is not IEEE compatible */
8413                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8414                         MONO_INST_NEW (cfg, ins, OP_FREM);
8415                         ins->inst_i0 = args [0];
8416                         ins->inst_i1 = args [1];
8417                 }
8418 #endif
8419         }
8420
8421         return ins;
8422 }
8423 #endif
8424
8425 gboolean
8426 mono_arch_print_tree (MonoInst *tree, int arity)
8427 {
8428         return 0;
8429 }
8430
8431 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8432
8433 mgreg_t
8434 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8435 {
8436         switch (reg) {
8437         case AMD64_RCX: return ctx->rcx;
8438         case AMD64_RDX: return ctx->rdx;
8439         case AMD64_RBX: return ctx->rbx;
8440         case AMD64_RBP: return ctx->rbp;
8441         case AMD64_RSP: return ctx->rsp;
8442         default:
8443                 return _CTX_REG (ctx, rax, reg);
8444         }
8445 }
8446
8447 void
8448 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8449 {
8450         switch (reg) {
8451         case AMD64_RCX:
8452                 ctx->rcx = val;
8453                 break;
8454         case AMD64_RDX:
8455                 ctx->rdx = val;
8456                 break;
8457         case AMD64_RBX:
8458                 ctx->rbx = val;
8459                 break;
8460         case AMD64_RBP:
8461                 ctx->rbp = val;
8462                 break;
8463         case AMD64_RSP:
8464                 ctx->rsp = val;
8465                 break;
8466         default:
8467                 _CTX_REG (ctx, rax, reg) = val;
8468         }
8469 }
8470
8471 gpointer
8472 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8473 {
8474         gpointer *sp, old_value;
8475         char *bp;
8476
8477         /*Load the spvar*/
8478         bp = MONO_CONTEXT_GET_BP (ctx);
8479         sp = *(gpointer*)(bp + clause->exvar_offset);
8480
8481         old_value = *sp;
8482         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8483                 return old_value;
8484
8485         *sp = new_value;
8486
8487         return old_value;
8488 }
8489
8490 /*
8491  * mono_arch_emit_load_aotconst:
8492  *
8493  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8494  * TARGET from the mscorlib GOT in full-aot code.
8495  * On AMD64, the result is placed into R11.
8496  */
8497 guint8*
8498 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8499 {
8500         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8501         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8502
8503         return code;
8504 }
8505
8506 /*
8507  * mono_arch_get_trampolines:
8508  *
8509  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8510  * for AOT.
8511  */
8512 GSList *
8513 mono_arch_get_trampolines (gboolean aot)
8514 {
8515         return mono_amd64_get_exception_trampolines (aot);
8516 }
8517
8518 /* Soft Debug support */
8519 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8520
8521 /*
8522  * mono_arch_set_breakpoint:
8523  *
8524  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8525  * The location should contain code emitted by OP_SEQ_POINT.
8526  */
8527 void
8528 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8529 {
8530         guint8 *code = ip;
8531         guint8 *orig_code = code;
8532
8533         if (ji->from_aot) {
8534                 guint32 native_offset = ip - (guint8*)ji->code_start;
8535                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8536
8537                 g_assert (info->bp_addrs [native_offset] == 0);
8538                 info->bp_addrs [native_offset] = bp_trigger_page;
8539         } else {
8540                 /*
8541                  * In production, we will use int3 (has to fix the size in the md
8542                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8543                  * instead.
8544                  */
8545                 g_assert (code [0] == 0x90);
8546                 if (breakpoint_size == 8) {
8547                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8548                 } else {
8549                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8550                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8551                 }
8552
8553                 g_assert (code - orig_code == breakpoint_size);
8554         }
8555 }
8556
8557 /*
8558  * mono_arch_clear_breakpoint:
8559  *
8560  *   Clear the breakpoint at IP.
8561  */
8562 void
8563 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8564 {
8565         guint8 *code = ip;
8566         int i;
8567
8568         if (ji->from_aot) {
8569                 guint32 native_offset = ip - (guint8*)ji->code_start;
8570                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8571
8572                 g_assert (info->bp_addrs [native_offset] == 0);
8573                 info->bp_addrs [native_offset] = info;
8574         } else {
8575                 for (i = 0; i < breakpoint_size; ++i)
8576                         x86_nop (code);
8577         }
8578 }
8579
8580 gboolean
8581 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8582 {
8583 #ifdef HOST_WIN32
8584         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8585         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8586                 return TRUE;
8587         else
8588                 return FALSE;
8589 #else
8590         siginfo_t* sinfo = (siginfo_t*) info;
8591         /* Sometimes the address is off by 4 */
8592         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8593                 return TRUE;
8594         else
8595                 return FALSE;
8596 #endif
8597 }
8598
8599 /*
8600  * mono_arch_skip_breakpoint:
8601  *
8602  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8603  * we resume, the instruction is not executed again.
8604  */
8605 void
8606 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8607 {
8608         if (ji->from_aot) {
8609                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8610                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8611         } else {
8612                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8613         }
8614 }
8615
8616 /*
8617  * mono_arch_start_single_stepping:
8618  *
8619  *   Start single stepping.
8620  */
8621 void
8622 mono_arch_start_single_stepping (void)
8623 {
8624         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8625 }
8626
8627 /*
8628  * mono_arch_stop_single_stepping:
8629  *
8630  *   Stop single stepping.
8631  */
8632 void
8633 mono_arch_stop_single_stepping (void)
8634 {
8635         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8636 }
8637
8638 /*
8639  * mono_arch_is_single_step_event:
8640  *
8641  *   Return whenever the machine state in SIGCTX corresponds to a single
8642  * step event.
8643  */
8644 gboolean
8645 mono_arch_is_single_step_event (void *info, void *sigctx)
8646 {
8647 #ifdef HOST_WIN32
8648         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8649         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8650                 return TRUE;
8651         else
8652                 return FALSE;
8653 #else
8654         siginfo_t* sinfo = (siginfo_t*) info;
8655         /* Sometimes the address is off by 4 */
8656         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8657                 return TRUE;
8658         else
8659                 return FALSE;
8660 #endif
8661 }
8662
8663 /*
8664  * mono_arch_skip_single_step:
8665  *
8666  *   Modify CTX so the ip is placed after the single step trigger instruction,
8667  * we resume, the instruction is not executed again.
8668  */
8669 void
8670 mono_arch_skip_single_step (MonoContext *ctx)
8671 {
8672         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8673 }
8674
8675 /*
8676  * mono_arch_create_seq_point_info:
8677  *
8678  *   Return a pointer to a data structure which is used by the sequence
8679  * point implementation in AOTed code.
8680  */
8681 gpointer
8682 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8683 {
8684         SeqPointInfo *info;
8685         MonoJitInfo *ji;
8686         int i;
8687
8688         // FIXME: Add a free function
8689
8690         mono_domain_lock (domain);
8691         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8692                                                                 code);
8693         mono_domain_unlock (domain);
8694
8695         if (!info) {
8696                 ji = mono_jit_info_table_find (domain, (char*)code);
8697                 g_assert (ji);
8698
8699                 // FIXME: Optimize the size
8700                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8701
8702                 info->ss_trigger_page = ss_trigger_page;
8703                 info->bp_trigger_page = bp_trigger_page;
8704                 /* Initialize to a valid address */
8705                 for (i = 0; i < ji->code_size; ++i)
8706                         info->bp_addrs [i] = info;
8707
8708                 mono_domain_lock (domain);
8709                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8710                                                          code, info);
8711                 mono_domain_unlock (domain);
8712         }
8713
8714         return info;
8715 }
8716
8717 void
8718 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8719 {
8720         ext->lmf.previous_lmf = prev_lmf;
8721         /* Mark that this is a MonoLMFExt */
8722         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8723         ext->lmf.rsp = (gssize)ext;
8724 }
8725
8726 #endif
8727
8728 gboolean
8729 mono_arch_opcode_supported (int opcode)
8730 {
8731         switch (opcode) {
8732         case OP_ATOMIC_ADD_I4:
8733         case OP_ATOMIC_ADD_I8:
8734         case OP_ATOMIC_EXCHANGE_I4:
8735         case OP_ATOMIC_EXCHANGE_I8:
8736         case OP_ATOMIC_CAS_I4:
8737         case OP_ATOMIC_CAS_I8:
8738         case OP_ATOMIC_LOAD_I1:
8739         case OP_ATOMIC_LOAD_I2:
8740         case OP_ATOMIC_LOAD_I4:
8741         case OP_ATOMIC_LOAD_I8:
8742         case OP_ATOMIC_LOAD_U1:
8743         case OP_ATOMIC_LOAD_U2:
8744         case OP_ATOMIC_LOAD_U4:
8745         case OP_ATOMIC_LOAD_U8:
8746         case OP_ATOMIC_LOAD_R4:
8747         case OP_ATOMIC_LOAD_R8:
8748         case OP_ATOMIC_STORE_I1:
8749         case OP_ATOMIC_STORE_I2:
8750         case OP_ATOMIC_STORE_I4:
8751         case OP_ATOMIC_STORE_I8:
8752         case OP_ATOMIC_STORE_U1:
8753         case OP_ATOMIC_STORE_U2:
8754         case OP_ATOMIC_STORE_U4:
8755         case OP_ATOMIC_STORE_U8:
8756         case OP_ATOMIC_STORE_R4:
8757         case OP_ATOMIC_STORE_R8:
8758                 return TRUE;
8759         default:
8760                 return FALSE;
8761         }
8762 }