mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *
  11  * (C) 2003 Ximian, Inc.
  12  */
  13 #include "mini.h"
  14 #include <string.h>
  15 #include <math.h>
  16 #include <unistd.h>
  17
  18 #include <mono/metadata/appdomain.h>
  19 #include <mono/metadata/debug-helpers.h>
  20 #include <mono/metadata/threads.h>
  21 #include <mono/metadata/profiler-private.h>
  22 #include <mono/metadata/mono-debug.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-amd64.h"
  27 #include "inssel.h"
  28 #include "cpu-amd64.h"
  29
  30 static gint lmf_tls_offset = -1;
  31 static gint lmf_addr_tls_offset = -1;
  32 static gint appdomain_tls_offset = -1;
  33 static gint thread_tls_offset = -1;
  34
  35 #ifdef MONO_XEN_OPT
  36 static gboolean optimize_for_xen = TRUE;
  37 #else
  38 #define optimize_for_xen 0
  39 #endif
  40
  41 static gboolean use_sse2 = !MONO_ARCH_USE_FPSTACK;
  42
  43 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  44
  45 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  46
  47 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  48
  49 #ifdef PLATFORM_WIN32
  50 /* Under windows, the default pinvoke calling convention is stdcall */
  51 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  52 #else
  53 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  54 #endif
  55
  56 #define ARGS_OFFSET 16
  57 #define GP_SCRATCH_REG AMD64_R11
  58
  59 /*
  60  * AMD64 register usage:
  61  * - callee saved registers are used for global register allocation
  62  * - %r11 is used for materializing 64 bit constants in opcodes
  63  * - the rest is used for local allocation
  64  */
  65
  66 /*
  67  * Floating point comparison results:
  68  *                  ZF PF CF
  69  * A > B            0  0  0
  70  * A < B            0  0  1
  71  * A = B            1  0  0
  72  * A > B            0  0  0
  73  * UNORDERED        1  1  1
  74  */
  75
  76 #define NOT_IMPLEMENTED g_assert_not_reached ()
  77
  78 const char*
  79 mono_arch_regname (int reg) {
  80         switch (reg) {
  81         case AMD64_RAX: return "%rax";
  82         case AMD64_RBX: return "%rbx";
  83         case AMD64_RCX: return "%rcx";
  84         case AMD64_RDX: return "%rdx";
  85         case AMD64_RSP: return "%rsp";
  86         case AMD64_RBP: return "%rbp";
  87         case AMD64_RDI: return "%rdi";
  88         case AMD64_RSI: return "%rsi";
  89         case AMD64_R8: return "%r8";
  90         case AMD64_R9: return "%r9";
  91         case AMD64_R10: return "%r10";
  92         case AMD64_R11: return "%r11";
  93         case AMD64_R12: return "%r12";
  94         case AMD64_R13: return "%r13";
  95         case AMD64_R14: return "%r14";
  96         case AMD64_R15: return "%r15";
  97         }
  98         return "unknown";
  99 }
 100
 101 static const char * xmmregs [] = {
 102         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 103         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 104 };
 105
 106 const char*
 107 mono_arch_fregname (int reg)
 108 {
 109         if (reg < AMD64_XMM_NREG)
 110                 return xmmregs [reg];
 111         else
 112                 return "unknown";
 113 }
 114
 115 G_GNUC_UNUSED static void
 116 break_count (void)
 117 {
 118 }
 119
 120 G_GNUC_UNUSED static gboolean
 121 debug_count (void)
 122 {
 123         static int count = 0;
 124         count ++;
 125
 126         if (!getenv ("COUNT"))
 127                 return TRUE;
 128
 129         if (count == atoi (getenv ("COUNT"))) {
 130                 break_count ();
 131         }
 132
 133         if (count > atoi (getenv ("COUNT"))) {
 134                 return FALSE;
 135         }
 136
 137         return TRUE;
 138 }
 139
 140 static gboolean
 141 debug_omit_fp (void)
 142 {
 143 #if 0
 144         return debug_count ();
 145 #else
 146         return TRUE;
 147 #endif
 148 }
 149
 150 static inline gboolean
 151 amd64_is_near_call (guint8 *code)
 152 {
 153         /* Skip REX */
 154         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 155                 code += 1;
 156
 157         return code [0] == 0xe8;
 158 }
 159
 160 static inline void
 161 amd64_patch (unsigned char* code, gpointer target)
 162 {
 163         /* Skip REX */
 164         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 165                 code += 1;
 166
 167         if ((code [0] & 0xf8) == 0xb8) {
 168                 /* amd64_set_reg_template */
 169                 *(guint64*)(code + 1) = (guint64)target;
 170         }
 171         else if (code [0] == 0x8b) {
 172                 /* mov 0(%rip), %dreg */
 173                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 174         }
 175         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 176                 /* call *<OFFSET>(%rip) */
 177                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 178         }
 179         else if ((code [0] == 0xe8)) {
 180                 /* call <DISP> */
 181                 gint64 disp = (guint8*)target - (guint8*)code;
 182                 g_assert (amd64_is_imm32 (disp));
 183                 x86_patch (code, (unsigned char*)target);
 184         }
 185         else
 186                 x86_patch (code, (unsigned char*)target);
 187 }
 188
 189 typedef enum {
 190         ArgInIReg,
 191         ArgInFloatSSEReg,
 192         ArgInDoubleSSEReg,
 193         ArgOnStack,
 194         ArgValuetypeInReg,
 195         ArgNone /* only in pair_storage */
 196 } ArgStorage;
 197
 198 typedef struct {
 199         gint16 offset;
 200         gint8  reg;
 201         ArgStorage storage;
 202
 203         /* Only if storage == ArgValuetypeInReg */
 204         ArgStorage pair_storage [2];
 205         gint8 pair_regs [2];
 206 } ArgInfo;
 207
 208 typedef struct {
 209         int nargs;
 210         guint32 stack_usage;
 211         guint32 reg_usage;
 212         guint32 freg_usage;
 213         gboolean need_stack_align;
 214         ArgInfo ret;
 215         ArgInfo sig_cookie;
 216         ArgInfo args [1];
 217 } CallInfo;
 218
 219 #define DEBUG(a) if (cfg->verbose_level > 1) a
 220
 221 #define NEW_ICONST(cfg,dest,val) do {   \
 222                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 223                 (dest)->opcode = OP_ICONST;     \
 224                 (dest)->inst_c0 = (val);        \
 225                 (dest)->type = STACK_I4;        \
 226         } while (0)
 227
 228 #define PARAM_REGS 6
 229
 230 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 231
 232 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 233
 234 static void inline
 235 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 236 {
 237     ainfo->offset = *stack_size;
 238
 239     if (*gr >= PARAM_REGS) {
 240                 ainfo->storage = ArgOnStack;
 241                 (*stack_size) += sizeof (gpointer);
 242     }
 243     else {
 244                 ainfo->storage = ArgInIReg;
 245                 ainfo->reg = param_regs [*gr];
 246                 (*gr) ++;
 247     }
 248 }
 249
 250 #define FLOAT_PARAM_REGS 8
 251
 252 static void inline
 253 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 254 {
 255     ainfo->offset = *stack_size;
 256
 257     if (*gr >= FLOAT_PARAM_REGS) {
 258                 ainfo->storage = ArgOnStack;
 259                 (*stack_size) += sizeof (gpointer);
 260     }
 261     else {
 262                 /* A double register */
 263                 if (is_double)
 264                         ainfo->storage = ArgInDoubleSSEReg;
 265                 else
 266                         ainfo->storage = ArgInFloatSSEReg;
 267                 ainfo->reg = *gr;
 268                 (*gr) += 1;
 269     }
 270 }
 271
 272 typedef enum ArgumentClass {
 273         ARG_CLASS_NO_CLASS,
 274         ARG_CLASS_MEMORY,
 275         ARG_CLASS_INTEGER,
 276         ARG_CLASS_SSE
 277 } ArgumentClass;
 278
 279 static ArgumentClass
 280 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 281 {
 282         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 283         MonoType *ptype;
 284
 285         ptype = mono_type_get_underlying_type (type);
 286         switch (ptype->type) {
 287         case MONO_TYPE_BOOLEAN:
 288         case MONO_TYPE_CHAR:
 289         case MONO_TYPE_I1:
 290         case MONO_TYPE_U1:
 291         case MONO_TYPE_I2:
 292         case MONO_TYPE_U2:
 293         case MONO_TYPE_I4:
 294         case MONO_TYPE_U4:
 295         case MONO_TYPE_I:
 296         case MONO_TYPE_U:
 297         case MONO_TYPE_STRING:
 298         case MONO_TYPE_OBJECT:
 299         case MONO_TYPE_CLASS:
 300         case MONO_TYPE_SZARRAY:
 301         case MONO_TYPE_PTR:
 302         case MONO_TYPE_FNPTR:
 303         case MONO_TYPE_ARRAY:
 304         case MONO_TYPE_I8:
 305         case MONO_TYPE_U8:
 306                 class2 = ARG_CLASS_INTEGER;
 307                 break;
 308         case MONO_TYPE_R4:
 309         case MONO_TYPE_R8:
 310                 class2 = ARG_CLASS_SSE;
 311                 break;
 312
 313         case MONO_TYPE_TYPEDBYREF:
 314                 g_assert_not_reached ();
 315
 316         case MONO_TYPE_GENERICINST:
 317                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 318                         class2 = ARG_CLASS_INTEGER;
 319                         break;
 320                 }
 321                 /* fall through */
 322         case MONO_TYPE_VALUETYPE: {
 323                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 324                 int i;
 325
 326                 for (i = 0; i < info->num_fields; ++i) {
 327                         class2 = class1;
 328                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 329                 }
 330                 break;
 331         }
 332         default:
 333                 g_assert_not_reached ();
 334         }
 335
 336         /* Merge */
 337         if (class1 == class2)
 338                 ;
 339         else if (class1 == ARG_CLASS_NO_CLASS)
 340                 class1 = class2;
 341         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 342                 class1 = ARG_CLASS_MEMORY;
 343         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 344                 class1 = ARG_CLASS_INTEGER;
 345         else
 346                 class1 = ARG_CLASS_SSE;
 347
 348         return class1;
 349 }
 350
 351 static void
 352 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 353                gboolean is_return,
 354                guint32 *gr, guint32 *fr, guint32 *stack_size)
 355 {
 356         guint32 size, quad, nquads, i;
 357         ArgumentClass args [2];
 358         MonoMarshalType *info;
 359         MonoClass *klass;
 360
 361         klass = mono_class_from_mono_type (type);
 362         if (sig->pinvoke)
 363                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 364         else
 365                 size = mono_type_stack_size (&klass->byval_arg, NULL);
 366
 367         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 368                 /* Allways pass in memory */
 369                 ainfo->offset = *stack_size;
 370                 *stack_size += ALIGN_TO (size, 8);
 371                 ainfo->storage = ArgOnStack;
 372
 373                 return;
 374         }
 375
 376         /* FIXME: Handle structs smaller than 8 bytes */
 377         //if ((size % 8) != 0)
 378         //      NOT_IMPLEMENTED;
 379
 380         if (size > 8)
 381                 nquads = 2;
 382         else
 383                 nquads = 1;
 384
 385         /*
 386          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 387          * The X87 and SSEUP stuff is left out since there are no such types in
 388          * the CLR.
 389          */
 390         info = mono_marshal_load_type_info (klass);
 391         g_assert (info);
 392         if (info->native_size > 16) {
 393                 ainfo->offset = *stack_size;
 394                 *stack_size += ALIGN_TO (info->native_size, 8);
 395                 ainfo->storage = ArgOnStack;
 396
 397                 return;
 398         }
 399
 400         args [0] = ARG_CLASS_NO_CLASS;
 401         args [1] = ARG_CLASS_NO_CLASS;
 402         for (quad = 0; quad < nquads; ++quad) {
 403                 int size;
 404                 guint32 align;
 405                 ArgumentClass class1;
 406
 407                 class1 = ARG_CLASS_NO_CLASS;
 408                 for (i = 0; i < info->num_fields; ++i) {
 409                         size = mono_marshal_type_size (info->fields [i].field->type,
 410                                                                                    info->fields [i].mspec,
 411                                                                                    &align, TRUE, klass->unicode);
 412                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 413                                 /* Unaligned field */
 414                                 NOT_IMPLEMENTED;
 415                         }
 416
 417                         /* Skip fields in other quad */
 418                         if ((quad == 0) && (info->fields [i].offset >= 8))
 419                                 continue;
 420                         if ((quad == 1) && (info->fields [i].offset < 8))
 421                                 continue;
 422
 423                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 424                 }
 425                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 426                 args [quad] = class1;
 427         }
 428
 429         /* Post merger cleanup */
 430         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 431                 args [0] = args [1] = ARG_CLASS_MEMORY;
 432
 433         /* Allocate registers */
 434         {
 435                 int orig_gr = *gr;
 436                 int orig_fr = *fr;
 437
 438                 ainfo->storage = ArgValuetypeInReg;
 439                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 440                 for (quad = 0; quad < nquads; ++quad) {
 441                         switch (args [quad]) {
 442                         case ARG_CLASS_INTEGER:
 443                                 if (*gr >= PARAM_REGS)
 444                                         args [quad] = ARG_CLASS_MEMORY;
 445                                 else {
 446                                         ainfo->pair_storage [quad] = ArgInIReg;
 447                                         if (is_return)
 448                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 449                                         else
 450                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 451                                         (*gr) ++;
 452                                 }
 453                                 break;
 454                         case ARG_CLASS_SSE:
 455                                 if (*fr >= FLOAT_PARAM_REGS)
 456                                         args [quad] = ARG_CLASS_MEMORY;
 457                                 else {
 458                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 459                                         ainfo->pair_regs [quad] = *fr;
 460                                         (*fr) ++;
 461                                 }
 462                                 break;
 463                         case ARG_CLASS_MEMORY:
 464                                 break;
 465                         default:
 466                                 g_assert_not_reached ();
 467                         }
 468                 }
 469
 470                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 471                         /* Revert possible register assignments */
 472                         *gr = orig_gr;
 473                         *fr = orig_fr;
 474
 475                         ainfo->offset = *stack_size;
 476                         *stack_size += ALIGN_TO (info->native_size, 8);
 477                         ainfo->storage = ArgOnStack;
 478                 }
 479         }
 480 }
 481
 482 /*
 483  * get_call_info:
 484  *
 485  *  Obtain information about a call according to the calling convention.
 486  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 487  * Draft Version 0.23" document for more information.
 488  */
 489 static CallInfo*
 490 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 491 {
 492         guint32 i, gr, fr;
 493         MonoType *ret_type;
 494         int n = sig->hasthis + sig->param_count;
 495         guint32 stack_size = 0;
 496         CallInfo *cinfo;
 497
 498         if (mp)
 499                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 500         else
 501                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 502
 503         gr = 0;
 504         fr = 0;
 505
 506         /* return value */
 507         {
 508                 ret_type = mono_type_get_underlying_type (sig->ret);
 509                 switch (ret_type->type) {
 510                 case MONO_TYPE_BOOLEAN:
 511                 case MONO_TYPE_I1:
 512                 case MONO_TYPE_U1:
 513                 case MONO_TYPE_I2:
 514                 case MONO_TYPE_U2:
 515                 case MONO_TYPE_CHAR:
 516                 case MONO_TYPE_I4:
 517                 case MONO_TYPE_U4:
 518                 case MONO_TYPE_I:
 519                 case MONO_TYPE_U:
 520                 case MONO_TYPE_PTR:
 521                 case MONO_TYPE_FNPTR:
 522                 case MONO_TYPE_CLASS:
 523                 case MONO_TYPE_OBJECT:
 524                 case MONO_TYPE_SZARRAY:
 525                 case MONO_TYPE_ARRAY:
 526                 case MONO_TYPE_STRING:
 527                         cinfo->ret.storage = ArgInIReg;
 528                         cinfo->ret.reg = AMD64_RAX;
 529                         break;
 530                 case MONO_TYPE_U8:
 531                 case MONO_TYPE_I8:
 532                         cinfo->ret.storage = ArgInIReg;
 533                         cinfo->ret.reg = AMD64_RAX;
 534                         break;
 535                 case MONO_TYPE_R4:
 536                         cinfo->ret.storage = ArgInFloatSSEReg;
 537                         cinfo->ret.reg = AMD64_XMM0;
 538                         break;
 539                 case MONO_TYPE_R8:
 540                         cinfo->ret.storage = ArgInDoubleSSEReg;
 541                         cinfo->ret.reg = AMD64_XMM0;
 542                         break;
 543                 case MONO_TYPE_GENERICINST:
 544                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 545                                 cinfo->ret.storage = ArgInIReg;
 546                                 cinfo->ret.reg = AMD64_RAX;
 547                                 break;
 548                         }
 549                         /* fall through */
 550                 case MONO_TYPE_VALUETYPE: {
 551                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 552
 553                         add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 554                         if (cinfo->ret.storage == ArgOnStack)
 555                                 /* The caller passes the address where the value is stored */
 556                                 add_general (&gr, &stack_size, &cinfo->ret);
 557                         break;
 558                 }
 559                 case MONO_TYPE_TYPEDBYREF:
 560                         /* Same as a valuetype with size 24 */
 561                         add_general (&gr, &stack_size, &cinfo->ret);
 562                         ;
 563                         break;
 564                 case MONO_TYPE_VOID:
 565                         break;
 566                 default:
 567                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 568                 }
 569         }
 570
 571         /* this */
 572         if (sig->hasthis)
 573                 add_general (&gr, &stack_size, cinfo->args + 0);
 574
 575         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 576                 gr = PARAM_REGS;
 577                 fr = FLOAT_PARAM_REGS;
 578
 579                 /* Emit the signature cookie just before the implicit arguments */
 580                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 581         }
 582
 583         for (i = 0; i < sig->param_count; ++i) {
 584                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 585                 MonoType *ptype;
 586
 587                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 588                         /* We allways pass the sig cookie on the stack for simplicity */
 589                         /*
 590                          * Prevent implicit arguments + the sig cookie from being passed
 591                          * in registers.
 592                          */
 593                         gr = PARAM_REGS;
 594                         fr = FLOAT_PARAM_REGS;
 595
 596                         /* Emit the signature cookie just before the implicit arguments */
 597                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 598                 }
 599
 600                 if (sig->params [i]->byref) {
 601                         add_general (&gr, &stack_size, ainfo);
 602                         continue;
 603                 }
 604                 ptype = mono_type_get_underlying_type (sig->params [i]);
 605                 switch (ptype->type) {
 606                 case MONO_TYPE_BOOLEAN:
 607                 case MONO_TYPE_I1:
 608                 case MONO_TYPE_U1:
 609                         add_general (&gr, &stack_size, ainfo);
 610                         break;
 611                 case MONO_TYPE_I2:
 612                 case MONO_TYPE_U2:
 613                 case MONO_TYPE_CHAR:
 614                         add_general (&gr, &stack_size, ainfo);
 615                         break;
 616                 case MONO_TYPE_I4:
 617                 case MONO_TYPE_U4:
 618                         add_general (&gr, &stack_size, ainfo);
 619                         break;
 620                 case MONO_TYPE_I:
 621                 case MONO_TYPE_U:
 622                 case MONO_TYPE_PTR:
 623                 case MONO_TYPE_FNPTR:
 624                 case MONO_TYPE_CLASS:
 625                 case MONO_TYPE_OBJECT:
 626                 case MONO_TYPE_STRING:
 627                 case MONO_TYPE_SZARRAY:
 628                 case MONO_TYPE_ARRAY:
 629                         add_general (&gr, &stack_size, ainfo);
 630                         break;
 631                 case MONO_TYPE_GENERICINST:
 632                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 633                                 add_general (&gr, &stack_size, ainfo);
 634                                 break;
 635                         }
 636                         /* fall through */
 637                 case MONO_TYPE_VALUETYPE:
 638                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 639                         break;
 640                 case MONO_TYPE_TYPEDBYREF:
 641                         stack_size += sizeof (MonoTypedRef);
 642                         ainfo->storage = ArgOnStack;
 643                         break;
 644                 case MONO_TYPE_U8:
 645                 case MONO_TYPE_I8:
 646                         add_general (&gr, &stack_size, ainfo);
 647                         break;
 648                 case MONO_TYPE_R4:
 649                         add_float (&fr, &stack_size, ainfo, FALSE);
 650                         break;
 651                 case MONO_TYPE_R8:
 652                         add_float (&fr, &stack_size, ainfo, TRUE);
 653                         break;
 654                 default:
 655                         g_assert_not_reached ();
 656                 }
 657         }
 658
 659         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 660                 gr = PARAM_REGS;
 661                 fr = FLOAT_PARAM_REGS;
 662
 663                 /* Emit the signature cookie just before the implicit arguments */
 664                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 665         }
 666
 667         if (stack_size & 0x8) {
 668                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 669                 cinfo->need_stack_align = TRUE;
 670                 stack_size += 8;
 671         }
 672
 673         cinfo->stack_usage = stack_size;
 674         cinfo->reg_usage = gr;
 675         cinfo->freg_usage = fr;
 676         return cinfo;
 677 }
 678
 679 /*
 680  * mono_arch_get_argument_info:
 681  * @csig:  a method signature
 682  * @param_count: the number of parameters to consider
 683  * @arg_info: an array to store the result infos
 684  *
 685  * Gathers information on parameters such as size, alignment and
 686  * padding. arg_info should be large enought to hold param_count + 1 entries.
 687  *
 688  * Returns the size of the argument area on the stack.
 689  */
 690 int
 691 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 692 {
 693         int k;
 694         CallInfo *cinfo = get_call_info (NULL, csig, FALSE);
 695         guint32 args_size = cinfo->stack_usage;
 696
 697         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 698         if (csig->hasthis) {
 699                 arg_info [0].offset = 0;
 700         }
 701
 702         for (k = 0; k < param_count; k++) {
 703                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 704                 /* FIXME: */
 705                 arg_info [k + 1].size = 0;
 706         }
 707
 708         g_free (cinfo);
 709
 710         return args_size;
 711 }
 712
 713 static int
 714 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 715 {
 716         return 0;
 717 }
 718
 719 /*
 720  * Initialize the cpu to execute managed code.
 721  */
 722 void
 723 mono_arch_cpu_init (void)
 724 {
 725 #ifndef _MSC_VER
 726         guint16 fpcw;
 727
 728         /* spec compliance requires running with double precision */
 729         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 730         fpcw &= ~X86_FPCW_PRECC_MASK;
 731         fpcw |= X86_FPCW_PREC_DOUBLE;
 732         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 733         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 734 #else
 735         _control87 (_PC_53, MCW_PC);
 736 #endif
 737 }
 738
 739 /*
 740  * This function returns the optimizations supported on this cpu.
 741  */
 742 guint32
 743 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 744 {
 745         int eax, ebx, ecx, edx;
 746         guint32 opts = 0;
 747
 748         /* FIXME: AMD64 */
 749
 750         *exclude_mask = 0;
 751         /* Feature Flags function, flags returned in EDX. */
 752         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 753                 if (edx & (1 << 15)) {
 754                         opts |= MONO_OPT_CMOV;
 755                         if (edx & 1)
 756                                 opts |= MONO_OPT_FCMOV;
 757                         else
 758                                 *exclude_mask |= MONO_OPT_FCMOV;
 759                 } else
 760                         *exclude_mask |= MONO_OPT_CMOV;
 761         }
 762         return opts;
 763 }
 764
 765 gboolean
 766 mono_amd64_is_sse2 (void)
 767 {
 768         return use_sse2;
 769 }
 770
 771 GList *
 772 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 773 {
 774         GList *vars = NULL;
 775         int i;
 776
 777         for (i = 0; i < cfg->num_varinfo; i++) {
 778                 MonoInst *ins = cfg->varinfo [i];
 779                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 780
 781                 /* unused vars */
 782                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 783                         continue;
 784
 785                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 786                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 787                         continue;
 788
 789                 if (mono_is_regsize_var (ins->inst_vtype)) {
 790                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 791                         g_assert (i == vmv->idx);
 792                         vars = g_list_prepend (vars, vmv);
 793                 }
 794         }
 795
 796         vars = mono_varlist_sort (cfg, vars, 0);
 797
 798         return vars;
 799 }
 800
 801 /**
 802  * mono_arch_compute_omit_fp:
 803  *
 804  *   Determine whenever the frame pointer can be eliminated.
 805  */
 806 static void
 807 mono_arch_compute_omit_fp (MonoCompile *cfg)
 808 {
 809         MonoMethodSignature *sig;
 810         MonoMethodHeader *header;
 811         int i;
 812         CallInfo *cinfo;
 813
 814         if (cfg->arch.omit_fp_computed)
 815                 return;
 816
 817         header = mono_method_get_header (cfg->method);
 818
 819         sig = mono_method_signature (cfg->method);
 820
 821         if (!cfg->arch.cinfo)
 822                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig, FALSE);
 823         cinfo = cfg->arch.cinfo;
 824
 825         /*
 826          * FIXME: Remove some of the restrictions.
 827          */
 828         cfg->arch.omit_fp = TRUE;
 829         cfg->arch.omit_fp_computed = TRUE;
 830
 831         /* Temporarily disable this when running in the debugger until we have support
 832          * for this in the debugger. */
 833         if (mono_debug_using_mono_debugger ())
 834                 cfg->arch.omit_fp = FALSE;
 835
 836         if (!debug_omit_fp ())
 837                 cfg->arch.omit_fp = FALSE;
 838         /*
 839         if (cfg->method->save_lmf)
 840                 cfg->arch.omit_fp = FALSE;
 841         */
 842         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 843                 cfg->arch.omit_fp = FALSE;
 844         if (header->num_clauses)
 845                 cfg->arch.omit_fp = FALSE;
 846         if (cfg->param_area)
 847                 cfg->arch.omit_fp = FALSE;
 848         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 849                 cfg->arch.omit_fp = FALSE;
 850         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 851                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 852                 cfg->arch.omit_fp = FALSE;
 853         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 854                 ArgInfo *ainfo = &cinfo->args [i];
 855
 856                 if (ainfo->storage == ArgOnStack) {
 857                         /*
 858                          * The stack offset can only be determined when the frame
 859                          * size is known.
 860                          */
 861                         cfg->arch.omit_fp = FALSE;
 862                 }
 863         }
 864
 865         if (cfg->num_varinfo > 10000) {
 866                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
 867                 cfg->arch.omit_fp = FALSE;
 868         }
 869 }
 870
 871 GList *
 872 mono_arch_get_global_int_regs (MonoCompile *cfg)
 873 {
 874         GList *regs = NULL;
 875
 876         mono_arch_compute_omit_fp (cfg);
 877
 878         if (cfg->arch.omit_fp)
 879                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
 880
 881         /* We use the callee saved registers for global allocation */
 882         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 883         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 884         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 885         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 886         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 887
 888         return regs;
 889 }
 890
 891 /*
 892  * mono_arch_regalloc_cost:
 893  *
 894  *  Return the cost, in number of memory references, of the action of
 895  * allocating the variable VMV into a register during global register
 896  * allocation.
 897  */
 898 guint32
 899 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 900 {
 901         MonoInst *ins = cfg->varinfo [vmv->idx];
 902
 903         if (cfg->method->save_lmf)
 904                 /* The register is already saved */
 905                 /* substract 1 for the invisible store in the prolog */
 906                 return (ins->opcode == OP_ARG) ? 0 : 1;
 907         else
 908                 /* push+pop */
 909                 return (ins->opcode == OP_ARG) ? 1 : 2;
 910 }
 911
 912 void
 913 mono_arch_allocate_vars (MonoCompile *cfg)
 914 {
 915         MonoMethodSignature *sig;
 916         MonoMethodHeader *header;
 917         MonoInst *inst;
 918         int i, offset;
 919         guint32 locals_stack_size, locals_stack_align;
 920         gint32 *offsets;
 921         CallInfo *cinfo;
 922
 923         header = mono_method_get_header (cfg->method);
 924
 925         sig = mono_method_signature (cfg->method);
 926
 927         cinfo = cfg->arch.cinfo;
 928
 929         mono_arch_compute_omit_fp (cfg);
 930
 931         /*
 932          * We use the ABI calling conventions for managed code as well.
 933          * Exception: valuetypes are never passed or returned in registers.
 934          */
 935
 936         if (cfg->arch.omit_fp) {
 937                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 938                 cfg->frame_reg = AMD64_RSP;
 939                 offset = 0;
 940         } else {
 941                 /* Locals are allocated backwards from %fp */
 942                 cfg->frame_reg = AMD64_RBP;
 943                 offset = 0;
 944         }
 945
 946         cfg->arch.reg_save_area_offset = offset;
 947
 948         /* Reserve space for caller saved registers */
 949         for (i = 0; i < AMD64_NREG; ++i)
 950                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
 951                         offset += sizeof (gpointer);
 952                 }
 953
 954         if (cfg->method->save_lmf) {
 955                 /* Reserve stack space for saving LMF + argument regs */
 956                 guint32 size = sizeof (MonoLMF);
 957
 958                 if (lmf_addr_tls_offset == -1)
 959                         /* Need to save argument regs too */
 960                         size += (AMD64_NREG * 8) + (8 * 8);
 961
 962                 if (cfg->arch.omit_fp) {
 963                         cfg->arch.lmf_offset = offset;
 964                         offset += size;
 965                 }
 966                 else {
 967                         offset += size;
 968                         cfg->arch.lmf_offset = -offset;
 969                 }
 970         }
 971
 972         if (sig->ret->type != MONO_TYPE_VOID) {
 973                 switch (cinfo->ret.storage) {
 974                 case ArgInIReg:
 975                 case ArgInFloatSSEReg:
 976                 case ArgInDoubleSSEReg:
 977                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
 978                                 /* The register is volatile */
 979                                 cfg->ret->opcode = OP_REGOFFSET;
 980                                 cfg->ret->inst_basereg = cfg->frame_reg;
 981                                 if (cfg->arch.omit_fp) {
 982                                         cfg->ret->inst_offset = offset;
 983                                         offset += 8;
 984                                 } else {
 985                                         offset += 8;
 986                                         cfg->ret->inst_offset = -offset;
 987                                 }
 988                         }
 989                         else {
 990                                 cfg->ret->opcode = OP_REGVAR;
 991                                 cfg->ret->inst_c0 = cinfo->ret.reg;
 992                         }
 993                         break;
 994                 case ArgValuetypeInReg:
 995                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 996                         g_assert (!cfg->arch.omit_fp);
 997                         offset += 16;
 998                         cfg->ret->opcode = OP_REGOFFSET;
 999                         cfg->ret->inst_basereg = cfg->frame_reg;
1000                         cfg->ret->inst_offset = - offset;
1001                         break;
1002                 default:
1003                         g_assert_not_reached ();
1004                 }
1005                 cfg->ret->dreg = cfg->ret->inst_c0;
1006         }
1007
1008         /* Allocate locals */
1009         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1010         if (locals_stack_align) {
1011                 offset += (locals_stack_align - 1);
1012                 offset &= ~(locals_stack_align - 1);
1013         }
1014         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1015                 if (offsets [i] != -1) {
1016                         MonoInst *inst = cfg->varinfo [i];
1017                         inst->opcode = OP_REGOFFSET;
1018                         inst->inst_basereg = cfg->frame_reg;
1019                         if (cfg->arch.omit_fp)
1020                                 inst->inst_offset = (offset + offsets [i]);
1021                         else
1022                                 inst->inst_offset = - (offset + offsets [i]);
1023                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1024                 }
1025         }
1026         offset += locals_stack_size;
1027
1028         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1029                 g_assert (!cfg->arch.omit_fp);
1030                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1031                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1032         }
1033
1034         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1035                 inst = cfg->args [i];
1036                 if (inst->opcode != OP_REGVAR) {
1037                         ArgInfo *ainfo = &cinfo->args [i];
1038                         gboolean inreg = TRUE;
1039                         MonoType *arg_type;
1040
1041                         if (sig->hasthis && (i == 0))
1042                                 arg_type = &mono_defaults.object_class->byval_arg;
1043                         else
1044                                 arg_type = sig->params [i - sig->hasthis];
1045
1046                         /* FIXME: Allocate volatile arguments to registers */
1047                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1048                                 inreg = FALSE;
1049
1050                         /*
1051                          * Under AMD64, all registers used to pass arguments to functions
1052                          * are volatile across calls.
1053                          * FIXME: Optimize this.
1054                          */
1055                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1056                                 inreg = FALSE;
1057
1058                         inst->opcode = OP_REGOFFSET;
1059
1060                         switch (ainfo->storage) {
1061                         case ArgInIReg:
1062                         case ArgInFloatSSEReg:
1063                         case ArgInDoubleSSEReg:
1064                                 inst->opcode = OP_REGVAR;
1065                                 inst->dreg = ainfo->reg;
1066                                 break;
1067                         case ArgOnStack:
1068                                 g_assert (!cfg->arch.omit_fp);
1069                                 inst->opcode = OP_REGOFFSET;
1070                                 inst->inst_basereg = cfg->frame_reg;
1071                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1072                                 break;
1073                         case ArgValuetypeInReg:
1074                                 break;
1075                         default:
1076                                 NOT_IMPLEMENTED;
1077                         }
1078
1079                         if (!inreg && (ainfo->storage != ArgOnStack)) {
1080                                 inst->opcode = OP_REGOFFSET;
1081                                 inst->inst_basereg = cfg->frame_reg;
1082                                 /* These arguments are saved to the stack in the prolog */
1083                                 if (cfg->arch.omit_fp) {
1084                                         inst->inst_offset = offset;
1085                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1086                                 } else {
1087                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1088                                         inst->inst_offset = - offset;
1089                                 }
1090                         }
1091                 }
1092         }
1093
1094         cfg->stack_offset = offset;
1095 }
1096
1097 void
1098 mono_arch_create_vars (MonoCompile *cfg)
1099 {
1100         MonoMethodSignature *sig;
1101         CallInfo *cinfo;
1102
1103         sig = mono_method_signature (cfg->method);
1104
1105         if (!cfg->arch.cinfo)
1106                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig, FALSE);
1107         cinfo = cfg->arch.cinfo;
1108
1109         if (cinfo->ret.storage == ArgValuetypeInReg)
1110                 cfg->ret_var_is_local = TRUE;
1111 }
1112
1113 static void
1114 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1115 {
1116         switch (storage) {
1117         case ArgInIReg:
1118                 arg->opcode = OP_OUTARG_REG;
1119                 arg->inst_left = tree;
1120                 arg->inst_call = call;
1121                 arg->backend.reg3 = reg;
1122                 break;
1123         case ArgInFloatSSEReg:
1124                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1125                 arg->inst_left = tree;
1126                 arg->inst_call = call;
1127                 arg->backend.reg3 = reg;
1128                 break;
1129         case ArgInDoubleSSEReg:
1130                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1131                 arg->inst_left = tree;
1132                 arg->inst_call = call;
1133                 arg->backend.reg3 = reg;
1134                 break;
1135         default:
1136                 g_assert_not_reached ();
1137         }
1138 }
1139
1140 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1141  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1142  */
1143
1144 static int
1145 arg_storage_to_ldind (ArgStorage storage)
1146 {
1147         switch (storage) {
1148         case ArgInIReg:
1149                 return CEE_LDIND_I;
1150         case ArgInDoubleSSEReg:
1151                 return CEE_LDIND_R8;
1152         case ArgInFloatSSEReg:
1153                 return CEE_LDIND_R4;
1154         default:
1155                 g_assert_not_reached ();
1156         }
1157
1158         return -1;
1159 }
1160
1161 static void
1162 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1163 {
1164         MonoInst *arg;
1165         MonoMethodSignature *tmp_sig;
1166         MonoInst *sig_arg;
1167
1168         /* FIXME: Add support for signature tokens to AOT */
1169         cfg->disable_aot = TRUE;
1170
1171         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1172
1173         /*
1174          * mono_ArgIterator_Setup assumes the signature cookie is
1175          * passed first and all the arguments which were before it are
1176          * passed on the stack after the signature. So compensate by
1177          * passing a different signature.
1178          */
1179         tmp_sig = mono_metadata_signature_dup (call->signature);
1180         tmp_sig->param_count -= call->signature->sentinelpos;
1181         tmp_sig->sentinelpos = 0;
1182         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1183
1184         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1185         sig_arg->inst_p0 = tmp_sig;
1186
1187         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1188         arg->inst_left = sig_arg;
1189         arg->type = STACK_PTR;
1190
1191         /* prepend, so they get reversed */
1192         arg->next = call->out_args;
1193         call->out_args = arg;
1194 }
1195
1196 /*
1197  * take the arguments and generate the arch-specific
1198  * instructions to properly call the function in call.
1199  * This includes pushing, moving arguments to the right register
1200  * etc.
1201  * Issue: who does the spilling if needed, and when?
1202  */
1203 MonoCallInst*
1204 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1205         MonoInst *arg, *in;
1206         MonoMethodSignature *sig;
1207         int i, n, stack_size;
1208         CallInfo *cinfo;
1209         ArgInfo *ainfo;
1210
1211         stack_size = 0;
1212
1213         sig = call->signature;
1214         n = sig->param_count + sig->hasthis;
1215
1216         cinfo = get_call_info (cfg->mempool, sig, sig->pinvoke);
1217
1218         for (i = 0; i < n; ++i) {
1219                 ainfo = cinfo->args + i;
1220
1221                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1222                         /* Emit the signature cookie just before the implicit arguments */
1223                         emit_sig_cookie (cfg, call, cinfo);
1224                 }
1225
1226                 if (is_virtual && i == 0) {
1227                         /* the argument will be attached to the call instruction */
1228                         in = call->args [i];
1229                 } else {
1230                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1231                         in = call->args [i];
1232                         arg->cil_code = in->cil_code;
1233                         arg->inst_left = in;
1234                         arg->type = in->type;
1235                         /* prepend, so they get reversed */
1236                         arg->next = call->out_args;
1237                         call->out_args = arg;
1238
1239                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1240                                 guint32 align;
1241                                 guint32 size;
1242
1243                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1244                                         size = sizeof (MonoTypedRef);
1245                                         align = sizeof (gpointer);
1246                                 }
1247                                 else
1248                                 if (sig->pinvoke)
1249                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1250                                 else {
1251                                         /*
1252                                          * Other backends use mono_type_stack_size (), but that
1253                                          * aligns the size to 8, which is larger than the size of
1254                                          * the source, leading to reads of invalid memory if the
1255                                          * source is at the end of address space.
1256                                          */
1257                                         size = mono_class_value_size (in->klass, &align);
1258                                 }
1259                                 if (ainfo->storage == ArgValuetypeInReg) {
1260                                         if (ainfo->pair_storage [1] == ArgNone) {
1261                                                 MonoInst *load;
1262
1263                                                 /* Simpler case */
1264
1265                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1266                                                 load->inst_left = in;
1267
1268                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1269                                         }
1270                                         else {
1271                                                 /* Trees can't be shared so make a copy */
1272                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1273                                                 MonoInst *load, *load2, *offset_ins;
1274
1275                                                 /* Reg1 */
1276                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1277                                                 load->ssa_op = MONO_SSA_LOAD;
1278                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1279
1280                                                 NEW_ICONST (cfg, offset_ins, 0);
1281                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1282                                                 load2->inst_left = load;
1283                                                 load2->inst_right = offset_ins;
1284
1285                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1286                                                 load->inst_left = load2;
1287
1288                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1289
1290                                                 /* Reg2 */
1291                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1292                                                 load->ssa_op = MONO_SSA_LOAD;
1293                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1294
1295                                                 NEW_ICONST (cfg, offset_ins, 8);
1296                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1297                                                 load2->inst_left = load;
1298                                                 load2->inst_right = offset_ins;
1299
1300                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1301                                                 load->inst_left = load2;
1302
1303                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1304                                                 arg->cil_code = in->cil_code;
1305                                                 arg->type = in->type;
1306                                                 /* prepend, so they get reversed */
1307                                                 arg->next = call->out_args;
1308                                                 call->out_args = arg;
1309
1310                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1311
1312                                                 /* Prepend a copy inst */
1313                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1314                                                 arg->cil_code = in->cil_code;
1315                                                 arg->ssa_op = MONO_SSA_STORE;
1316                                                 arg->inst_left = vtaddr;
1317                                                 arg->inst_right = in;
1318                                                 arg->type = in->type;
1319
1320                                                 /* prepend, so they get reversed */
1321                                                 arg->next = call->out_args;
1322                                                 call->out_args = arg;
1323                                         }
1324                                 }
1325                                 else {
1326                                         arg->opcode = OP_OUTARG_VT;
1327                                         arg->klass = in->klass;
1328                                         arg->backend.is_pinvoke = sig->pinvoke;
1329                                         arg->inst_imm = size;
1330                                 }
1331                         }
1332                         else {
1333                                 switch (ainfo->storage) {
1334                                 case ArgInIReg:
1335                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1336                                         break;
1337                                 case ArgInFloatSSEReg:
1338                                 case ArgInDoubleSSEReg:
1339                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1340                                         break;
1341                                 case ArgOnStack:
1342                                         arg->opcode = OP_OUTARG;
1343                                         if (!sig->params [i - sig->hasthis]->byref) {
1344                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1345                                                         arg->opcode = OP_OUTARG_R4;
1346                                                 else
1347                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1348                                                                 arg->opcode = OP_OUTARG_R8;
1349                                         }
1350                                         break;
1351                                 default:
1352                                         g_assert_not_reached ();
1353                                 }
1354                         }
1355                 }
1356         }
1357
1358         /* Handle the case where there are no implicit arguments */
1359         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1360                 emit_sig_cookie (cfg, call, cinfo);
1361         }
1362
1363         if (cinfo->need_stack_align) {
1364                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1365                 /* prepend, so they get reversed */
1366                 arg->next = call->out_args;
1367                 call->out_args = arg;
1368         }
1369
1370         call->stack_usage = cinfo->stack_usage;
1371         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1372         cfg->flags |= MONO_CFG_HAS_CALLS;
1373
1374         return call;
1375 }
1376
1377 #define EMIT_COND_BRANCH(ins,cond,sign) \
1378 if (ins->flags & MONO_INST_BRLABEL) { \
1379         if (ins->inst_i0->inst_c0) { \
1380                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1381         } else { \
1382                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1383                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1384                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1385                         x86_branch8 (code, cond, 0, sign); \
1386                 else \
1387                         x86_branch32 (code, cond, 0, sign); \
1388         } \
1389 } else { \
1390         if (ins->inst_true_bb->native_offset) { \
1391                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1392         } else { \
1393                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1394                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1395                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1396                         x86_branch8 (code, cond, 0, sign); \
1397                 else \
1398                         x86_branch32 (code, cond, 0, sign); \
1399         } \
1400 }
1401
1402 /* emit an exception if condition is fail */
1403 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1404         do {                                                        \
1405                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1406                 if (tins == NULL) {                                                                             \
1407                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1408                                         MONO_PATCH_INFO_EXC, exc_name);  \
1409                         x86_branch32 (code, cond, 0, signed);               \
1410                 } else {        \
1411                         EMIT_COND_BRANCH (tins, cond, signed);  \
1412                 }                       \
1413         } while (0);
1414
1415 #define EMIT_FPCOMPARE(code) do { \
1416         amd64_fcompp (code); \
1417         amd64_fnstsw (code); \
1418 } while (0);
1419
1420 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1421     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1422         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1423         amd64_ ##op (code); \
1424         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1425         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1426 } while (0);
1427
1428 static guint8*
1429 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1430 {
1431         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1432
1433         /*
1434          * FIXME: Add support for thunks
1435          */
1436         {
1437                 gboolean near_call = FALSE;
1438
1439                 /*
1440                  * Indirect calls are expensive so try to make a near call if possible.
1441                  * The caller memory is allocated by the code manager so it is
1442                  * guaranteed to be at a 32 bit offset.
1443                  */
1444
1445                 if (patch_type != MONO_PATCH_INFO_ABS) {
1446                         /* The target is in memory allocated using the code manager */
1447                         near_call = TRUE;
1448
1449                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1450                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1451                                         /* The callee might be an AOT method */
1452                                         near_call = FALSE;
1453                         }
1454
1455                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1456                                 /*
1457                                  * The call might go directly to a native function without
1458                                  * the wrapper.
1459                                  */
1460                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1461                                 if (mi) {
1462                                         gconstpointer target = mono_icall_get_wrapper (mi);
1463                                         if ((((guint64)target) >> 32) != 0)
1464                                                 near_call = FALSE;
1465                                 }
1466                         }
1467                 }
1468                 else {
1469                         if (mono_find_class_init_trampoline_by_addr (data))
1470                                 near_call = TRUE;
1471                         else {
1472                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1473                                 if (info) {
1474                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1475                                                 strstr (cfg->method->name, info->name)) {
1476                                                 /* A call to the wrapped function */
1477                                                 if ((((guint64)data) >> 32) == 0)
1478                                                         near_call = TRUE;
1479                                         }
1480                                         else if (info->func == info->wrapper) {
1481                                                 /* No wrapper */
1482                                                 if ((((guint64)info->func) >> 32) == 0)
1483                                                         near_call = TRUE;
1484                                         }
1485                                         else {
1486                                                 /* See the comment in mono_codegen () */
1487                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1488                                                         near_call = TRUE;
1489                                         }
1490                                 }
1491                                 else if ((((guint64)data) >> 32) == 0)
1492                                         near_call = TRUE;
1493                         }
1494                 }
1495
1496                 if (cfg->method->dynamic)
1497                         /* These methods are allocated using malloc */
1498                         near_call = FALSE;
1499
1500                 if (cfg->compile_aot)
1501                         near_call = TRUE;
1502
1503 #ifdef MONO_ARCH_NOMAP32BIT
1504                 near_call = FALSE;
1505 #endif
1506
1507                 if (near_call) {
1508                         amd64_call_code (code, 0);
1509                 }
1510                 else {
1511                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1512                         amd64_call_reg (code, GP_SCRATCH_REG);
1513                 }
1514         }
1515
1516         return code;
1517 }
1518
1519 static inline guint8*
1520 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1521 {
1522         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1523
1524         return emit_call_body (cfg, code, patch_type, data);
1525 }
1526
1527 static inline int
1528 store_membase_imm_to_store_membase_reg (int opcode)
1529 {
1530         switch (opcode) {
1531         case OP_STORE_MEMBASE_IMM:
1532                 return OP_STORE_MEMBASE_REG;
1533         case OP_STOREI4_MEMBASE_IMM:
1534                 return OP_STOREI4_MEMBASE_REG;
1535         case OP_STOREI8_MEMBASE_IMM:
1536                 return OP_STOREI8_MEMBASE_REG;
1537         }
1538
1539         return -1;
1540 }
1541
1542 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
1543
1544 /*
1545  * peephole_pass_1:
1546  *
1547  *   Perform peephole opts which should/can be performed before local regalloc
1548  */
1549 static void
1550 peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1551 {
1552         MonoInst *ins, *last_ins = NULL;
1553         ins = bb->code;
1554
1555         while (ins) {
1556
1557                 switch (ins->opcode) {
1558                 case OP_ADD_IMM:
1559                 case OP_IADD_IMM:
1560                 case OP_LADD_IMM:
1561                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
1562                                 /*
1563                                  * X86_LEA is like ADD, but doesn't have the
1564                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
1565                                  * its operand to 64 bit.
1566                                  */
1567                                 ins->opcode = OP_X86_LEA_MEMBASE;
1568                                 ins->inst_basereg = ins->sreg1;
1569                                 /* Fall through */
1570                         }
1571                         else
1572                                 break;
1573                 case CEE_XOR:
1574                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1575                                 MonoInst *ins2;
1576
1577                                 /*
1578                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
1579                                  * the latter has length 2-3 instead of 6 (reverse constant
1580                                  * propagation). These instruction sequences are very common
1581                                  * in the initlocals bblock.
1582                                  */
1583                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1584                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
1585                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
1586                                                 ins2->sreg1 = ins->dreg;
1587                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
1588                                                 /* Continue */
1589                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
1590                                                 NULLIFY_INS (ins2);
1591                                                 /* Continue */
1592                                         } else {
1593                                                 break;
1594                                         }
1595                                 }
1596                         }
1597                         break;
1598                 case OP_COMPARE_IMM:
1599                         /* OP_COMPARE_IMM (reg, 0)
1600                          * -->
1601                          * OP_AMD64_TEST_NULL (reg)
1602                          */
1603                         if (!ins->inst_imm)
1604                                 ins->opcode = OP_AMD64_TEST_NULL;
1605                         break;
1606                 case OP_ICOMPARE_IMM:
1607                         if (!ins->inst_imm)
1608                                 ins->opcode = OP_X86_TEST_NULL;
1609                         break;
1610                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1611                         /*
1612                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1613                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1614                          * -->
1615                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1616                          * OP_COMPARE_IMM reg, imm
1617                          *
1618                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1619                          */
1620                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1621                             ins->inst_basereg == last_ins->inst_destbasereg &&
1622                             ins->inst_offset == last_ins->inst_offset) {
1623                                         ins->opcode = OP_ICOMPARE_IMM;
1624                                         ins->sreg1 = last_ins->sreg1;
1625
1626                                         /* check if we can remove cmp reg,0 with test null */
1627                                         if (!ins->inst_imm)
1628                                                 ins->opcode = OP_X86_TEST_NULL;
1629                                 }
1630
1631                         break;
1632                 case OP_LOAD_MEMBASE:
1633                 case OP_LOADI4_MEMBASE:
1634                         /*
1635                          * Note: if reg1 = reg2 the load op is removed
1636                          *
1637                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1638                          * OP_LOAD_MEMBASE offset(basereg), reg2
1639                          * -->
1640                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1641                          * OP_MOVE reg1, reg2
1642                          */
1643                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1644                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1645                             ins->inst_basereg == last_ins->inst_destbasereg &&
1646                             ins->inst_offset == last_ins->inst_offset) {
1647                                 if (ins->dreg == last_ins->sreg1) {
1648                                         last_ins->next = ins->next;
1649                                         ins = ins->next;
1650                                         continue;
1651                                 } else {
1652                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1653                                         ins->opcode = OP_MOVE;
1654                                         ins->sreg1 = last_ins->sreg1;
1655                                 }
1656
1657                         /*
1658                          * Note: reg1 must be different from the basereg in the second load
1659                          * Note: if reg1 = reg2 is equal then second load is removed
1660                          *
1661                          * OP_LOAD_MEMBASE offset(basereg), reg1
1662                          * OP_LOAD_MEMBASE offset(basereg), reg2
1663                          * -->
1664                          * OP_LOAD_MEMBASE offset(basereg), reg1
1665                          * OP_MOVE reg1, reg2
1666                          */
1667                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1668                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1669                               ins->inst_basereg != last_ins->dreg &&
1670                               ins->inst_basereg == last_ins->inst_basereg &&
1671                               ins->inst_offset == last_ins->inst_offset) {
1672
1673                                 if (ins->dreg == last_ins->dreg) {
1674                                         last_ins->next = ins->next;
1675                                         ins = ins->next;
1676                                         continue;
1677                                 } else {
1678                                         ins->opcode = OP_MOVE;
1679                                         ins->sreg1 = last_ins->dreg;
1680                                 }
1681
1682                                 //g_assert_not_reached ();
1683
1684 #if 0
1685                         /*
1686                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1687                          * OP_LOAD_MEMBASE offset(basereg), reg
1688                          * -->
1689                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1690                          * OP_ICONST reg, imm
1691                          */
1692                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1693                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1694                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1695                                    ins->inst_offset == last_ins->inst_offset) {
1696                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1697                                 ins->opcode = OP_ICONST;
1698                                 ins->inst_c0 = last_ins->inst_imm;
1699                                 g_assert_not_reached (); // check this rule
1700 #endif
1701                         }
1702                         break;
1703                 case OP_LOADI1_MEMBASE:
1704                         /*
1705                          * Note: if reg1 = reg2 the load op is removed
1706                          *
1707                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1708                          * OP_LOAD_MEMBASE offset(basereg), reg2
1709                          * -->
1710                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1711                          * OP_MOVE reg1, reg2
1712                          */
1713                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1714                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1715                                         ins->inst_offset == last_ins->inst_offset) {
1716                                 if (ins->dreg == last_ins->sreg1) {
1717                                         last_ins->next = ins->next;
1718                                         ins = ins->next;
1719                                         continue;
1720                                 } else {
1721                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1722                                         ins->opcode = OP_MOVE;
1723                                         ins->sreg1 = last_ins->sreg1;
1724                                 }
1725                         }
1726                         break;
1727                 case OP_LOADI2_MEMBASE:
1728                         /*
1729                          * Note: if reg1 = reg2 the load op is removed
1730                          *
1731                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1732                          * OP_LOAD_MEMBASE offset(basereg), reg2
1733                          * -->
1734                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1735                          * OP_MOVE reg1, reg2
1736                          */
1737                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1738                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1739                                         ins->inst_offset == last_ins->inst_offset) {
1740                                 if (ins->dreg == last_ins->sreg1) {
1741                                         last_ins->next = ins->next;
1742                                         ins = ins->next;
1743                                         continue;
1744                                 } else {
1745                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1746                                         ins->opcode = OP_MOVE;
1747                                         ins->sreg1 = last_ins->sreg1;
1748                                 }
1749                         }
1750                         break;
1751                 case CEE_CONV_I4:
1752                 case CEE_CONV_U4:
1753                 case OP_MOVE:
1754                 case OP_FMOVE:
1755                         /*
1756                          * Removes:
1757                          *
1758                          * OP_MOVE reg, reg
1759                          */
1760                         if (ins->dreg == ins->sreg1) {
1761                                 if (last_ins)
1762                                         last_ins->next = ins->next;
1763                                 ins = ins->next;
1764                                 continue;
1765                         }
1766                         /*
1767                          * Removes:
1768                          *
1769                          * OP_MOVE sreg, dreg
1770                          * OP_MOVE dreg, sreg
1771                          */
1772                         if (last_ins && last_ins->opcode == OP_MOVE &&
1773                             ins->sreg1 == last_ins->dreg &&
1774                             ins->dreg == last_ins->sreg1) {
1775                                 last_ins->next = ins->next;
1776                                 ins = ins->next;
1777                                 continue;
1778                         }
1779                         break;
1780                 }
1781                 last_ins = ins;
1782                 ins = ins->next;
1783         }
1784         bb->last_ins = last_ins;
1785 }
1786
1787 static void
1788 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1789 {
1790         MonoInst *ins, *last_ins = NULL;
1791         ins = bb->code;
1792
1793         while (ins) {
1794
1795                 switch (ins->opcode) {
1796                 case OP_ICONST:
1797                 case OP_I8CONST:
1798                         /* reg = 0 -> XOR (reg, reg) */
1799                         /* XOR sets cflags on x86, so we cant do it always */
1800                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1801                                 ins->opcode = OP_LXOR;
1802                                 ins->sreg1 = ins->dreg;
1803                                 ins->sreg2 = ins->dreg;
1804                                 /* Fall through */
1805                         }
1806                         else
1807                                 break;
1808                 case CEE_XOR:
1809                 case OP_LXOR:
1810                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1811                                 MonoInst *ins2;
1812
1813                                 /*
1814                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
1815                                  * the latter has length 2-3 instead of 6 (reverse constant
1816                                  * propagation). These instruction sequences are very common
1817                                  * in the initlocals bblock.
1818                                  */
1819                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1820                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
1821                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
1822                                                 ins2->sreg1 = ins->dreg;
1823                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
1824                                                 /* Continue */
1825                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
1826                                                 NULLIFY_INS (ins2);
1827                                                 /* Continue */
1828                                         } else {
1829                                                 break;
1830                                         }
1831                                 }
1832                         }
1833                         break;
1834                 case OP_IADD_IMM:
1835                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1836                                 ins->opcode = OP_X86_INC_REG;
1837                         break;
1838                 case OP_ISUB_IMM:
1839                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1840                                 ins->opcode = OP_X86_DEC_REG;
1841                         break;
1842                 case OP_MUL_IMM:
1843                         /* remove unnecessary multiplication with 1 */
1844                         if (ins->inst_imm == 1) {
1845                                 if (ins->dreg != ins->sreg1) {
1846                                         ins->opcode = OP_MOVE;
1847                                 } else {
1848                                         last_ins->next = ins->next;
1849                                         ins = ins->next;
1850                                         continue;
1851                                 }
1852                         }
1853                         break;
1854                 case OP_COMPARE_IMM:
1855                         /* OP_COMPARE_IMM (reg, 0)
1856                          * -->
1857                          * OP_AMD64_TEST_NULL (reg)
1858                          */
1859                         if (!ins->inst_imm)
1860                                 ins->opcode = OP_AMD64_TEST_NULL;
1861                         break;
1862                 case OP_ICOMPARE_IMM:
1863                         if (!ins->inst_imm)
1864                                 ins->opcode = OP_X86_TEST_NULL;
1865                         break;
1866                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1867                         /*
1868                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1869                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1870                          * -->
1871                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1872                          * OP_COMPARE_IMM reg, imm
1873                          *
1874                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1875                          */
1876                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1877                             ins->inst_basereg == last_ins->inst_destbasereg &&
1878                             ins->inst_offset == last_ins->inst_offset) {
1879                                         ins->opcode = OP_ICOMPARE_IMM;
1880                                         ins->sreg1 = last_ins->sreg1;
1881
1882                                         /* check if we can remove cmp reg,0 with test null */
1883                                         if (!ins->inst_imm)
1884                                                 ins->opcode = OP_X86_TEST_NULL;
1885                                 }
1886
1887                         break;
1888                 case OP_LOAD_MEMBASE:
1889                 case OP_LOADI4_MEMBASE:
1890                         /*
1891                          * Note: if reg1 = reg2 the load op is removed
1892                          *
1893                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1894                          * OP_LOAD_MEMBASE offset(basereg), reg2
1895                          * -->
1896                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1897                          * OP_MOVE reg1, reg2
1898                          */
1899                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1900                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1901                             ins->inst_basereg == last_ins->inst_destbasereg &&
1902                             ins->inst_offset == last_ins->inst_offset) {
1903                                 if (ins->dreg == last_ins->sreg1) {
1904                                         last_ins->next = ins->next;
1905                                         ins = ins->next;
1906                                         continue;
1907                                 } else {
1908                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1909                                         ins->opcode = OP_MOVE;
1910                                         ins->sreg1 = last_ins->sreg1;
1911                                 }
1912
1913                         /*
1914                          * Note: reg1 must be different from the basereg in the second load
1915                          * Note: if reg1 = reg2 is equal then second load is removed
1916                          *
1917                          * OP_LOAD_MEMBASE offset(basereg), reg1
1918                          * OP_LOAD_MEMBASE offset(basereg), reg2
1919                          * -->
1920                          * OP_LOAD_MEMBASE offset(basereg), reg1
1921                          * OP_MOVE reg1, reg2
1922                          */
1923                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1924                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1925                               ins->inst_basereg != last_ins->dreg &&
1926                               ins->inst_basereg == last_ins->inst_basereg &&
1927                               ins->inst_offset == last_ins->inst_offset) {
1928
1929                                 if (ins->dreg == last_ins->dreg) {
1930                                         last_ins->next = ins->next;
1931                                         ins = ins->next;
1932                                         continue;
1933                                 } else {
1934                                         ins->opcode = OP_MOVE;
1935                                         ins->sreg1 = last_ins->dreg;
1936                                 }
1937
1938                                 //g_assert_not_reached ();
1939
1940 #if 0
1941                         /*
1942                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1943                          * OP_LOAD_MEMBASE offset(basereg), reg
1944                          * -->
1945                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1946                          * OP_ICONST reg, imm
1947                          */
1948                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1949                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1950                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1951                                    ins->inst_offset == last_ins->inst_offset) {
1952                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1953                                 ins->opcode = OP_ICONST;
1954                                 ins->inst_c0 = last_ins->inst_imm;
1955                                 g_assert_not_reached (); // check this rule
1956 #endif
1957                         }
1958                         break;
1959                 case OP_LOADI1_MEMBASE:
1960                         /*
1961                          * Note: if reg1 = reg2 the load op is removed
1962                          *
1963                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1964                          * OP_LOAD_MEMBASE offset(basereg), reg2
1965                          * -->
1966                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1967                          * OP_MOVE reg1, reg2
1968                          */
1969                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1970                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1971                                         ins->inst_offset == last_ins->inst_offset) {
1972                                 if (ins->dreg == last_ins->sreg1) {
1973                                         last_ins->next = ins->next;
1974                                         ins = ins->next;
1975                                         continue;
1976                                 } else {
1977                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1978                                         ins->opcode = OP_MOVE;
1979                                         ins->sreg1 = last_ins->sreg1;
1980                                 }
1981                         }
1982                         break;
1983                 case OP_LOADI2_MEMBASE:
1984                         /*
1985                          * Note: if reg1 = reg2 the load op is removed
1986                          *
1987                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1988                          * OP_LOAD_MEMBASE offset(basereg), reg2
1989                          * -->
1990                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1991                          * OP_MOVE reg1, reg2
1992                          */
1993                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1994                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1995                                         ins->inst_offset == last_ins->inst_offset) {
1996                                 if (ins->dreg == last_ins->sreg1) {
1997                                         last_ins->next = ins->next;
1998                                         ins = ins->next;
1999                                         continue;
2000                                 } else {
2001                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2002                                         ins->opcode = OP_MOVE;
2003                                         ins->sreg1 = last_ins->sreg1;
2004                                 }
2005                         }
2006                         break;
2007                 case CEE_CONV_I4:
2008                 case CEE_CONV_U4:
2009                 case OP_MOVE:
2010                 case OP_FMOVE:
2011                         /*
2012                          * Removes:
2013                          *
2014                          * OP_MOVE reg, reg
2015                          */
2016                         if (ins->dreg == ins->sreg1) {
2017                                 if (last_ins)
2018                                         last_ins->next = ins->next;
2019                                 ins = ins->next;
2020                                 continue;
2021                         }
2022                         /*
2023                          * Removes:
2024                          *
2025                          * OP_MOVE sreg, dreg
2026                          * OP_MOVE dreg, sreg
2027                          */
2028                         if (last_ins && last_ins->opcode == OP_MOVE &&
2029                             ins->sreg1 == last_ins->dreg &&
2030                             ins->dreg == last_ins->sreg1) {
2031                                 last_ins->next = ins->next;
2032                                 ins = ins->next;
2033                                 continue;
2034                         }
2035                         break;
2036                 }
2037                 last_ins = ins;
2038                 ins = ins->next;
2039         }
2040         bb->last_ins = last_ins;
2041 }
2042
2043 static void
2044 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
2045 {
2046         if (ins == NULL) {
2047                 ins = bb->code;
2048                 bb->code = to_insert;
2049                 to_insert->next = ins;
2050         }
2051         else {
2052                 to_insert->next = ins->next;
2053                 ins->next = to_insert;
2054         }
2055 }
2056
2057 #define NEW_INS(cfg,dest,op) do {       \
2058                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
2059                 (dest)->opcode = (op);  \
2060         insert_after_ins (bb, last_ins, (dest)); \
2061         } while (0)
2062
2063 /*
2064  * mono_arch_lowering_pass:
2065  *
2066  *  Converts complex opcodes into simpler ones so that each IR instruction
2067  * corresponds to one machine instruction.
2068  */
2069 static void
2070 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2071 {
2072         MonoInst *ins, *temp, *last_ins = NULL;
2073         ins = bb->code;
2074
2075         if (bb->max_vreg > cfg->rs->next_vreg)
2076                 cfg->rs->next_vreg = bb->max_vreg;
2077
2078         /*
2079          * FIXME: Need to add more instructions, but the current machine
2080          * description can't model some parts of the composite instructions like
2081          * cdq.
2082          */
2083         while (ins) {
2084                 switch (ins->opcode) {
2085                 case OP_DIV_IMM:
2086                 case OP_REM_IMM:
2087                 case OP_IDIV_IMM:
2088                 case OP_IREM_IMM:
2089                         NEW_INS (cfg, temp, OP_ICONST);
2090                         temp->inst_c0 = ins->inst_imm;
2091                         temp->dreg = mono_regstate_next_int (cfg->rs);
2092                         switch (ins->opcode) {
2093                         case OP_DIV_IMM:
2094                                 ins->opcode = OP_LDIV;
2095                                 break;
2096                         case OP_REM_IMM:
2097                                 ins->opcode = OP_LREM;
2098                                 break;
2099                         case OP_IDIV_IMM:
2100                                 ins->opcode = OP_IDIV;
2101                                 break;
2102                         case OP_IREM_IMM:
2103                                 ins->opcode = OP_IREM;
2104                                 break;
2105                         }
2106                         ins->sreg2 = temp->dreg;
2107                         break;
2108                 case OP_COMPARE_IMM:
2109                         if (!amd64_is_imm32 (ins->inst_imm)) {
2110                                 NEW_INS (cfg, temp, OP_I8CONST);
2111                                 temp->inst_c0 = ins->inst_imm;
2112                                 temp->dreg = mono_regstate_next_int (cfg->rs);
2113                                 ins->opcode = OP_COMPARE;
2114                                 ins->sreg2 = temp->dreg;
2115                         }
2116                         break;
2117                 case OP_LOAD_MEMBASE:
2118                 case OP_LOADI8_MEMBASE:
2119                         if (!amd64_is_imm32 (ins->inst_offset)) {
2120                                 NEW_INS (cfg, temp, OP_I8CONST);
2121                                 temp->inst_c0 = ins->inst_offset;
2122                                 temp->dreg = mono_regstate_next_int (cfg->rs);
2123                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2124                                 ins->inst_indexreg = temp->dreg;
2125                         }
2126                         break;
2127                 case OP_STORE_MEMBASE_IMM:
2128                 case OP_STOREI8_MEMBASE_IMM:
2129                         if (!amd64_is_imm32 (ins->inst_imm)) {
2130                                 NEW_INS (cfg, temp, OP_I8CONST);
2131                                 temp->inst_c0 = ins->inst_imm;
2132                                 temp->dreg = mono_regstate_next_int (cfg->rs);
2133                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2134                                 ins->sreg1 = temp->dreg;
2135                         }
2136                         break;
2137                 default:
2138                         break;
2139                 }
2140                 last_ins = ins;
2141                 ins = ins->next;
2142         }
2143         bb->last_ins = last_ins;
2144
2145         bb->max_vreg = cfg->rs->next_vreg;
2146 }
2147
2148 static const int
2149 branch_cc_table [] = {
2150         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2151         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2152         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2153 };
2154
2155 /* Maps CMP_... constants to X86_CC_... constants */
2156 static const int
2157 cc_table [] = {
2158         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2159         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2160 };
2161
2162 static const int
2163 cc_signed_table [] = {
2164         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2165         FALSE, FALSE, FALSE, FALSE
2166 };
2167
2168 /*#include "cprop.c"*/
2169
2170 /*
2171  * Local register allocation.
2172  * We first scan the list of instructions and we save the liveness info of
2173  * each register (when the register is first used, when it's value is set etc.).
2174  * We also reverse the list of instructions (in the InstList list) because assigning
2175  * registers backwards allows for more tricks to be used.
2176  */
2177 void
2178 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
2179 {
2180         if (!bb->code)
2181                 return;
2182
2183         mono_arch_lowering_pass (cfg, bb);
2184
2185         if (cfg->opt & MONO_OPT_PEEPHOLE)
2186                 peephole_pass_1 (cfg, bb);
2187
2188         mono_local_regalloc (cfg, bb);
2189 }
2190
2191 static unsigned char*
2192 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2193 {
2194         if (use_sse2) {
2195                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2196         }
2197         else {
2198                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
2199                 x86_fnstcw_membase(code, AMD64_RSP, 0);
2200                 amd64_mov_reg_membase (code, dreg, AMD64_RSP, 0, 2);
2201                 amd64_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2202                 amd64_mov_membase_reg (code, AMD64_RSP, 2, dreg, 2);
2203                 amd64_fldcw_membase (code, AMD64_RSP, 2);
2204                 amd64_push_reg (code, AMD64_RAX); // SP = SP - 8
2205                 amd64_fist_pop_membase (code, AMD64_RSP, 0, size == 8);
2206                 amd64_pop_reg (code, dreg);
2207                 amd64_fldcw_membase (code, AMD64_RSP, 0);
2208                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
2209         }
2210
2211         if (size == 1)
2212                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2213         else if (size == 2)
2214                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2215         return code;
2216 }
2217
2218 static unsigned char*
2219 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2220 {
2221         int sreg = tree->sreg1;
2222         int need_touch = FALSE;
2223
2224 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2225         if (!tree->flags & MONO_INST_INIT)
2226                 need_touch = TRUE;
2227 #endif
2228
2229         if (need_touch) {
2230                 guint8* br[5];
2231
2232                 /*
2233                  * Under Windows:
2234                  * If requested stack size is larger than one page,
2235                  * perform stack-touch operation
2236                  */
2237                 /*
2238                  * Generate stack probe code.
2239                  * Under Windows, it is necessary to allocate one page at a time,
2240                  * "touching" stack after each successful sub-allocation. This is
2241                  * because of the way stack growth is implemented - there is a
2242                  * guard page before the lowest stack page that is currently commited.
2243                  * Stack normally grows sequentially so OS traps access to the
2244                  * guard page and commits more pages when needed.
2245                  */
2246                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2247                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2248
2249                 br[2] = code; /* loop */
2250                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2251                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2252                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2253                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2254                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2255                 amd64_patch (br[3], br[2]);
2256                 amd64_test_reg_reg (code, sreg, sreg);
2257                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2258                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2259
2260                 br[1] = code; x86_jump8 (code, 0);
2261
2262                 amd64_patch (br[0], code);
2263                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2264                 amd64_patch (br[1], code);
2265                 amd64_patch (br[4], code);
2266         }
2267         else
2268                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2269
2270         if (tree->flags & MONO_INST_INIT) {
2271                 int offset = 0;
2272                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2273                         amd64_push_reg (code, AMD64_RAX);
2274                         offset += 8;
2275                 }
2276                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2277                         amd64_push_reg (code, AMD64_RCX);
2278                         offset += 8;
2279                 }
2280                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2281                         amd64_push_reg (code, AMD64_RDI);
2282                         offset += 8;
2283                 }
2284
2285                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2286                 if (sreg != AMD64_RCX)
2287                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2288                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2289
2290                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2291                 amd64_cld (code);
2292                 amd64_prefix (code, X86_REP_PREFIX);
2293                 amd64_stosl (code);
2294
2295                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2296                         amd64_pop_reg (code, AMD64_RDI);
2297                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2298                         amd64_pop_reg (code, AMD64_RCX);
2299                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2300                         amd64_pop_reg (code, AMD64_RAX);
2301         }
2302         return code;
2303 }
2304
2305 static guint8*
2306 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2307 {
2308         CallInfo *cinfo;
2309         guint32 quad;
2310
2311         /* Move return value to the target register */
2312         /* FIXME: do this in the local reg allocator */
2313         switch (ins->opcode) {
2314         case CEE_CALL:
2315         case OP_CALL_REG:
2316         case OP_CALL_MEMBASE:
2317         case OP_LCALL:
2318         case OP_LCALL_REG:
2319         case OP_LCALL_MEMBASE:
2320                 g_assert (ins->dreg == AMD64_RAX);
2321                 break;
2322         case OP_FCALL:
2323         case OP_FCALL_REG:
2324         case OP_FCALL_MEMBASE:
2325                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2326                         if (use_sse2)
2327                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2328                         else {
2329                                 /* FIXME: optimize this */
2330                                 amd64_movss_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2331                                 amd64_fld_membase (code, AMD64_RSP, -8, FALSE);
2332                         }
2333                 }
2334                 else {
2335                         if (use_sse2) {
2336                                 if (ins->dreg != AMD64_XMM0)
2337                                         amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2338                         }
2339                         else {
2340                                 /* FIXME: optimize this */
2341                                 amd64_movsd_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2342                                 amd64_fld_membase (code, AMD64_RSP, -8, TRUE);
2343                         }
2344                 }
2345                 break;
2346         case OP_VCALL:
2347         case OP_VCALL_REG:
2348         case OP_VCALL_MEMBASE:
2349                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2350                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2351                         /* Pop the destination address from the stack */
2352                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2353                         amd64_pop_reg (code, AMD64_RCX);
2354
2355                         for (quad = 0; quad < 2; quad ++) {
2356                                 switch (cinfo->ret.pair_storage [quad]) {
2357                                 case ArgInIReg:
2358                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2359                                         break;
2360                                 case ArgInFloatSSEReg:
2361                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2362                                         break;
2363                                 case ArgInDoubleSSEReg:
2364                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2365                                         break;
2366                                 case ArgNone:
2367                                         break;
2368                                 default:
2369                                         NOT_IMPLEMENTED;
2370                                 }
2371                         }
2372                 }
2373                 break;
2374         }
2375
2376         return code;
2377 }
2378
2379 /*
2380  * emit_tls_get:
2381  * @code: buffer to store code to
2382  * @dreg: hard register where to place the result
2383  * @tls_offset: offset info
2384  *
2385  * emit_tls_get emits in @code the native code that puts in the dreg register
2386  * the item in the thread local storage identified by tls_offset.
2387  *
2388  * Returns: a pointer to the end of the stored code
2389  */
2390 static guint8*
2391 emit_tls_get (guint8* code, int dreg, int tls_offset)
2392 {
2393         if (optimize_for_xen) {
2394                 x86_prefix (code, X86_FS_PREFIX);
2395                 amd64_mov_reg_mem (code, dreg, 0, 8);
2396                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2397         } else {
2398                 x86_prefix (code, X86_FS_PREFIX);
2399                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2400         }
2401         return code;
2402 }
2403
2404 /*
2405  * emit_load_volatile_arguments:
2406  *
2407  *  Load volatile arguments from the stack to the original input registers.
2408  * Required before a tail call.
2409  */
2410 static guint8*
2411 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2412 {
2413         MonoMethod *method = cfg->method;
2414         MonoMethodSignature *sig;
2415         MonoInst *inst;
2416         CallInfo *cinfo;
2417         guint32 i;
2418
2419         /* FIXME: Generate intermediate code instead */
2420
2421         sig = mono_method_signature (method);
2422
2423         cinfo = cfg->arch.cinfo;
2424
2425         /* This is the opposite of the code in emit_prolog */
2426
2427         if (sig->ret->type != MONO_TYPE_VOID) {
2428                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
2429                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->ret->inst_basereg, cfg->ret->inst_offset, 8);
2430                 }
2431         }
2432
2433         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2434                 ArgInfo *ainfo = cinfo->args + i;
2435                 MonoType *arg_type;
2436                 inst = cfg->args [i];
2437
2438                 if (sig->hasthis && (i == 0))
2439                         arg_type = &mono_defaults.object_class->byval_arg;
2440                 else
2441                         arg_type = sig->params [i - sig->hasthis];
2442
2443                 if (inst->opcode != OP_REGVAR) {
2444                         switch (ainfo->storage) {
2445                         case ArgInIReg: {
2446                                 guint32 size = 8;
2447
2448                                 /* FIXME: I1 etc */
2449                                 amd64_mov_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset, size);
2450                                 break;
2451                         }
2452                         case ArgInFloatSSEReg:
2453                                 amd64_movss_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2454                                 break;
2455                         case ArgInDoubleSSEReg:
2456                                 amd64_movsd_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2457                                 break;
2458                         default:
2459                                 break;
2460                         }
2461                 }
2462                 else {
2463                         g_assert (ainfo->storage == ArgInIReg);
2464
2465                         amd64_mov_reg_reg (code, ainfo->reg, inst->dreg, 8);
2466                 }
2467         }
2468
2469         return code;
2470 }
2471
2472 #define REAL_PRINT_REG(text,reg) \
2473 mono_assert (reg >= 0); \
2474 amd64_push_reg (code, AMD64_RAX); \
2475 amd64_push_reg (code, AMD64_RDX); \
2476 amd64_push_reg (code, AMD64_RCX); \
2477 amd64_push_reg (code, reg); \
2478 amd64_push_imm (code, reg); \
2479 amd64_push_imm (code, text " %d %p\n"); \
2480 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2481 amd64_call_reg (code, AMD64_RAX); \
2482 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2483 amd64_pop_reg (code, AMD64_RCX); \
2484 amd64_pop_reg (code, AMD64_RDX); \
2485 amd64_pop_reg (code, AMD64_RAX);
2486
2487 /* benchmark and set based on cpu */
2488 #define LOOP_ALIGNMENT 8
2489 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2490
2491 void
2492 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2493 {
2494         MonoInst *ins;
2495         MonoCallInst *call;
2496         guint offset;
2497         guint8 *code = cfg->native_code + cfg->code_len;
2498         MonoInst *last_ins = NULL;
2499         guint last_offset = 0;
2500         int max_len, cpos;
2501
2502         if (cfg->opt & MONO_OPT_PEEPHOLE)
2503                 peephole_pass (cfg, bb);
2504
2505         if (cfg->opt & MONO_OPT_LOOP) {
2506                 int pad, align = LOOP_ALIGNMENT;
2507                 /* set alignment depending on cpu */
2508                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2509                         pad = align - pad;
2510                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2511                         amd64_padding (code, pad);
2512                         cfg->code_len += pad;
2513                         bb->native_offset = cfg->code_len;
2514                 }
2515         }
2516
2517         if (cfg->verbose_level > 2)
2518                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2519
2520         cpos = bb->max_offset;
2521
2522         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2523                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2524                 g_assert (!cfg->compile_aot);
2525                 cpos += 6;
2526
2527                 cov->data [bb->dfn].cil_code = bb->cil_code;
2528                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2529                 /* this is not thread save, but good enough */
2530                 amd64_inc_membase (code, AMD64_R11, 0);
2531         }
2532
2533         offset = code - cfg->native_code;
2534
2535         mono_debug_open_block (cfg, bb, offset);
2536
2537         ins = bb->code;
2538         while (ins) {
2539                 offset = code - cfg->native_code;
2540
2541                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2542
2543                 if (offset > (cfg->code_size - max_len - 16)) {
2544                         cfg->code_size *= 2;
2545                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2546                         code = cfg->native_code + offset;
2547                         mono_jit_stats.code_reallocs++;
2548                 }
2549
2550                 mono_debug_record_line_number (cfg, ins, offset);
2551
2552                 switch (ins->opcode) {
2553                 case OP_BIGMUL:
2554                         amd64_mul_reg (code, ins->sreg2, TRUE);
2555                         break;
2556                 case OP_BIGMUL_UN:
2557                         amd64_mul_reg (code, ins->sreg2, FALSE);
2558                         break;
2559                 case OP_X86_SETEQ_MEMBASE:
2560                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2561                         break;
2562                 case OP_STOREI1_MEMBASE_IMM:
2563                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2564                         break;
2565                 case OP_STOREI2_MEMBASE_IMM:
2566                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2567                         break;
2568                 case OP_STOREI4_MEMBASE_IMM:
2569                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2570                         break;
2571                 case OP_STOREI1_MEMBASE_REG:
2572                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2573                         break;
2574                 case OP_STOREI2_MEMBASE_REG:
2575                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2576                         break;
2577                 case OP_STORE_MEMBASE_REG:
2578                 case OP_STOREI8_MEMBASE_REG:
2579                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2580                         break;
2581                 case OP_STOREI4_MEMBASE_REG:
2582                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2583                         break;
2584                 case OP_STORE_MEMBASE_IMM:
2585                 case OP_STOREI8_MEMBASE_IMM:
2586                         g_assert (amd64_is_imm32 (ins->inst_imm));
2587                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2588                         break;
2589                 case CEE_LDIND_I:
2590                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, sizeof (gpointer));
2591                         break;
2592                 case CEE_LDIND_I4:
2593                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2594                         break;
2595                 case CEE_LDIND_U4:
2596                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2597                         break;
2598                 case OP_LOADU4_MEM:
2599                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2600                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2601                         break;
2602                 case OP_LOAD_MEMBASE:
2603                 case OP_LOADI8_MEMBASE:
2604                         g_assert (amd64_is_imm32 (ins->inst_offset));
2605                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2606                         break;
2607                 case OP_LOADI4_MEMBASE:
2608                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2609                         break;
2610                 case OP_LOADU4_MEMBASE:
2611                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2612                         break;
2613                 case OP_LOADU1_MEMBASE:
2614                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2615                         break;
2616                 case OP_LOADI1_MEMBASE:
2617                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2618                         break;
2619                 case OP_LOADU2_MEMBASE:
2620                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2621                         break;
2622                 case OP_LOADI2_MEMBASE:
2623                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2624                         break;
2625                 case OP_AMD64_LOADI8_MEMINDEX:
2626                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2627                         break;
2628                 case CEE_CONV_I1:
2629                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2630                         break;
2631                 case CEE_CONV_I2:
2632                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2633                         break;
2634                 case CEE_CONV_U1:
2635                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2636                         break;
2637                 case CEE_CONV_U2:
2638                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2639                         break;
2640                 case CEE_CONV_U8:
2641                 case CEE_CONV_U:
2642                         /* Clean out the upper word */
2643                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2644                         break;
2645                 case CEE_CONV_I8:
2646                 case CEE_CONV_I:
2647                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2648                         break;
2649                 case OP_COMPARE:
2650                 case OP_LCOMPARE:
2651                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2652                         break;
2653                 case OP_COMPARE_IMM:
2654                         g_assert (amd64_is_imm32 (ins->inst_imm));
2655                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2656                         break;
2657                 case OP_X86_COMPARE_REG_MEMBASE:
2658                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2659                         break;
2660                 case OP_X86_TEST_NULL:
2661                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2662                         break;
2663                 case OP_AMD64_TEST_NULL:
2664                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2665                         break;
2666                 case OP_X86_ADD_MEMBASE_IMM:
2667                         /* FIXME: Make a 64 version too */
2668                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2669                         break;
2670                 case OP_X86_ADD_MEMBASE:
2671                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2672                         break;
2673                 case OP_X86_SUB_MEMBASE_IMM:
2674                         g_assert (amd64_is_imm32 (ins->inst_imm));
2675                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2676                         break;
2677                 case OP_X86_SUB_MEMBASE:
2678                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2679                         break;
2680                 case OP_X86_INC_MEMBASE:
2681                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2682                         break;
2683                 case OP_X86_INC_REG:
2684                         amd64_inc_reg_size (code, ins->dreg, 4);
2685                         break;
2686                 case OP_X86_DEC_MEMBASE:
2687                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2688                         break;
2689                 case OP_X86_DEC_REG:
2690                         amd64_dec_reg_size (code, ins->dreg, 4);
2691                         break;
2692                 case OP_X86_MUL_MEMBASE:
2693                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2694                         break;
2695                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2696                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2697                         break;
2698                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2699                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2700                         break;
2701                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2702                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2703                         break;
2704                 case OP_BREAK:
2705                         amd64_breakpoint (code);
2706                         break;
2707                 case OP_ADDCC:
2708                 case CEE_ADD:
2709                 case OP_LADD:
2710                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2711                         break;
2712                 case OP_ADC:
2713                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2714                         break;
2715                 case OP_ADD_IMM:
2716                         g_assert (amd64_is_imm32 (ins->inst_imm));
2717                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2718                         break;
2719                 case OP_ADC_IMM:
2720                         g_assert (amd64_is_imm32 (ins->inst_imm));
2721                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2722                         break;
2723                 case OP_SUBCC:
2724                 case CEE_SUB:
2725                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2726                         break;
2727                 case OP_SBB:
2728                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2729                         break;
2730                 case OP_SUB_IMM:
2731                         g_assert (amd64_is_imm32 (ins->inst_imm));
2732                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2733                         break;
2734                 case OP_SBB_IMM:
2735                         g_assert (amd64_is_imm32 (ins->inst_imm));
2736                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2737                         break;
2738                 case CEE_AND:
2739                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2740                         break;
2741                 case OP_AND_IMM:
2742                         g_assert (amd64_is_imm32 (ins->inst_imm));
2743                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2744                         break;
2745                 case CEE_MUL:
2746                 case OP_LMUL:
2747                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2748                         break;
2749                 case OP_MUL_IMM:
2750                 case OP_LMUL_IMM:
2751                 case OP_IMUL_IMM: {
2752                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2753
2754                         switch (ins->inst_imm) {
2755                         case 2:
2756                                 /* MOV r1, r2 */
2757                                 /* ADD r1, r1 */
2758                                 if (ins->dreg != ins->sreg1)
2759                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2760                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2761                                 break;
2762                         case 3:
2763                                 /* LEA r1, [r2 + r2*2] */
2764                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2765                                 break;
2766                         case 5:
2767                                 /* LEA r1, [r2 + r2*4] */
2768                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2769                                 break;
2770                         case 6:
2771                                 /* LEA r1, [r2 + r2*2] */
2772                                 /* ADD r1, r1          */
2773                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2774                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2775                                 break;
2776                         case 9:
2777                                 /* LEA r1, [r2 + r2*8] */
2778                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2779                                 break;
2780                         case 10:
2781                                 /* LEA r1, [r2 + r2*4] */
2782                                 /* ADD r1, r1          */
2783                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2784                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2785                                 break;
2786                         case 12:
2787                                 /* LEA r1, [r2 + r2*2] */
2788                                 /* SHL r1, 2           */
2789                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2790                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2791                                 break;
2792                         case 25:
2793                                 /* LEA r1, [r2 + r2*4] */
2794                                 /* LEA r1, [r1 + r1*4] */
2795                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2796                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2797                                 break;
2798                         case 100:
2799                                 /* LEA r1, [r2 + r2*4] */
2800                                 /* SHL r1, 2           */
2801                                 /* LEA r1, [r1 + r1*4] */
2802                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2803                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2804                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2805                                 break;
2806                         default:
2807                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2808                                 break;
2809                         }
2810                         break;
2811                 }
2812                 case CEE_DIV:
2813                 case OP_LDIV:
2814                 case CEE_REM:
2815                 case OP_LREM:
2816                         /* Regalloc magic makes the div/rem cases the same */
2817                         if (ins->sreg2 == AMD64_RDX) {
2818                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2819                                 amd64_cdq (code);
2820                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
2821                         } else {
2822                                 amd64_cdq (code);
2823                                 amd64_div_reg (code, ins->sreg2, TRUE);
2824                         }
2825                         break;
2826                 case CEE_DIV_UN:
2827                 case OP_LDIV_UN:
2828                 case CEE_REM_UN:
2829                 case OP_LREM_UN:
2830                         if (ins->sreg2 == AMD64_RDX) {
2831                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2832                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2833                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
2834                         } else {
2835                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2836                                 amd64_div_reg (code, ins->sreg2, FALSE);
2837                         }
2838                         break;
2839                 case OP_IDIV:
2840                 case OP_IREM:
2841                         if (ins->sreg2 == AMD64_RDX) {
2842                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2843                                 amd64_cdq_size (code, 4);
2844                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
2845                         } else {
2846                                 amd64_cdq_size (code, 4);
2847                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2848                         }
2849                         break;
2850                 case OP_IDIV_UN:
2851                 case OP_IREM_UN:
2852                         if (ins->sreg2 == AMD64_RDX) {
2853                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2854                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2855                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
2856                         } else {
2857                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2858                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2859                         }
2860                         break;
2861                 case OP_LMUL_OVF:
2862                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2863                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2864                         break;
2865                 case CEE_OR:
2866                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2867                         break;
2868                 case OP_OR_IMM
2869 :                       g_assert (amd64_is_imm32 (ins->inst_imm));
2870                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2871                         break;
2872                 case CEE_XOR:
2873                 case OP_LXOR:
2874                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2875                         break;
2876                 case OP_XOR_IMM:
2877                         g_assert (amd64_is_imm32 (ins->inst_imm));
2878                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2879                         break;
2880                 case CEE_SHL:
2881                 case OP_LSHL:
2882                         g_assert (ins->sreg2 == AMD64_RCX);
2883                         amd64_shift_reg (code, X86_SHL, ins->dreg);
2884                         break;
2885                 case CEE_SHR:
2886                 case OP_LSHR:
2887                         g_assert (ins->sreg2 == AMD64_RCX);
2888                         amd64_shift_reg (code, X86_SAR, ins->dreg);
2889                         break;
2890                 case OP_SHR_IMM:
2891                         g_assert (amd64_is_imm32 (ins->inst_imm));
2892                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2893                         break;
2894                 case OP_LSHR_IMM:
2895                         g_assert (amd64_is_imm32 (ins->inst_imm));
2896                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2897                         break;
2898                 case OP_SHR_UN_IMM:
2899                         g_assert (amd64_is_imm32 (ins->inst_imm));
2900                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2901                         break;
2902                 case OP_LSHR_UN_IMM:
2903                         g_assert (amd64_is_imm32 (ins->inst_imm));
2904                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2905                         break;
2906                 case CEE_SHR_UN:
2907                         g_assert (ins->sreg2 == AMD64_RCX);
2908                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2909                         break;
2910                 case OP_LSHR_UN:
2911                         g_assert (ins->sreg2 == AMD64_RCX);
2912                         amd64_shift_reg (code, X86_SHR, ins->dreg);
2913                         break;
2914                 case OP_SHL_IMM:
2915                         g_assert (amd64_is_imm32 (ins->inst_imm));
2916                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2917                         break;
2918                 case OP_LSHL_IMM:
2919                         g_assert (amd64_is_imm32 (ins->inst_imm));
2920                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2921                         break;
2922
2923                 case OP_IADDCC:
2924                 case OP_IADD:
2925                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
2926                         break;
2927                 case OP_IADC:
2928                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
2929                         break;
2930                 case OP_IADD_IMM:
2931                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
2932                         break;
2933                 case OP_IADC_IMM:
2934                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
2935                         break;
2936                 case OP_ISUBCC:
2937                 case OP_ISUB:
2938                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
2939                         break;
2940                 case OP_ISBB:
2941                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
2942                         break;
2943                 case OP_ISUB_IMM:
2944                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
2945                         break;
2946                 case OP_ISBB_IMM:
2947                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
2948                         break;
2949                 case OP_IAND:
2950                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
2951                         break;
2952                 case OP_IAND_IMM:
2953                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
2954                         break;
2955                 case OP_IOR:
2956                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
2957                         break;
2958                 case OP_IOR_IMM:
2959                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
2960                         break;
2961                 case OP_IXOR:
2962                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
2963                         break;
2964                 case OP_IXOR_IMM:
2965                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
2966                         break;
2967                 case OP_INEG:
2968                         amd64_neg_reg_size (code, ins->sreg1, 4);
2969                         break;
2970                 case OP_INOT:
2971                         amd64_not_reg_size (code, ins->sreg1, 4);
2972                         break;
2973                 case OP_ISHL:
2974                         g_assert (ins->sreg2 == AMD64_RCX);
2975                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
2976                         break;
2977                 case OP_ISHR:
2978                         g_assert (ins->sreg2 == AMD64_RCX);
2979                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
2980                         break;
2981                 case OP_ISHR_IMM:
2982                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2983                         break;
2984                 case OP_ISHR_UN_IMM:
2985                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2986                         break;
2987                 case OP_ISHR_UN:
2988                         g_assert (ins->sreg2 == AMD64_RCX);
2989                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2990                         break;
2991                 case OP_ISHL_IMM:
2992                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2993                         break;
2994                 case OP_IMUL:
2995                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2996                         break;
2997                 case OP_IMUL_OVF:
2998                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2999                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3000                         break;
3001                 case OP_IMUL_OVF_UN:
3002                 case OP_LMUL_OVF_UN: {
3003                         /* the mul operation and the exception check should most likely be split */
3004                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3005                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3006                         /*g_assert (ins->sreg2 == X86_EAX);
3007                         g_assert (ins->dreg == X86_EAX);*/
3008                         if (ins->sreg2 == X86_EAX) {
3009                                 non_eax_reg = ins->sreg1;
3010                         } else if (ins->sreg1 == X86_EAX) {
3011                                 non_eax_reg = ins->sreg2;
3012                         } else {
3013                                 /* no need to save since we're going to store to it anyway */
3014                                 if (ins->dreg != X86_EAX) {
3015                                         saved_eax = TRUE;
3016                                         amd64_push_reg (code, X86_EAX);
3017                                 }
3018                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3019                                 non_eax_reg = ins->sreg2;
3020                         }
3021                         if (ins->dreg == X86_EDX) {
3022                                 if (!saved_eax) {
3023                                         saved_eax = TRUE;
3024                                         amd64_push_reg (code, X86_EAX);
3025                                 }
3026                         } else {
3027                                 saved_edx = TRUE;
3028                                 amd64_push_reg (code, X86_EDX);
3029                         }
3030                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3031                         /* save before the check since pop and mov don't change the flags */
3032                         if (ins->dreg != X86_EAX)
3033                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3034                         if (saved_edx)
3035                                 amd64_pop_reg (code, X86_EDX);
3036                         if (saved_eax)
3037                                 amd64_pop_reg (code, X86_EAX);
3038                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3039                         break;
3040                 }
3041                 case OP_ICOMPARE:
3042                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3043                         break;
3044                 case OP_ICOMPARE_IMM:
3045                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3046                         break;
3047                 case OP_IBEQ:
3048                 case OP_IBLT:
3049                 case OP_IBGT:
3050                 case OP_IBGE:
3051                 case OP_IBLE:
3052                 case OP_IBNE_UN:
3053                 case OP_IBLT_UN:
3054                 case OP_IBGT_UN:
3055                 case OP_IBGE_UN:
3056                 case OP_IBLE_UN:
3057                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3058                         break;
3059                 case CEE_NOT:
3060                         amd64_not_reg (code, ins->sreg1);
3061                         break;
3062                 case CEE_NEG:
3063                         amd64_neg_reg (code, ins->sreg1);
3064                         break;
3065                 case OP_SEXT_I1:
3066                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3067                         break;
3068                 case OP_SEXT_I2:
3069                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3070                         break;
3071                 case OP_SEXT_I4:
3072                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3073                         break;
3074                 case OP_ICONST:
3075                 case OP_I8CONST:
3076                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3077                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3078                         else
3079                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3080                         break;
3081                 case OP_AOTCONST:
3082                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3083                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3084                         break;
3085                 case CEE_CONV_I4:
3086                 case CEE_CONV_U4:
3087                 case OP_MOVE:
3088                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3089                         break;
3090                 case OP_AMD64_SET_XMMREG_R4: {
3091                         if (use_sse2) {
3092                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3093                         }
3094                         else {
3095                                 amd64_fst_membase (code, AMD64_RSP, -8, FALSE, TRUE);
3096                                 /* ins->dreg is set to -1 by the reg allocator */
3097                                 amd64_movss_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
3098                         }
3099                         break;
3100                 }
3101                 case OP_AMD64_SET_XMMREG_R8: {
3102                         if (use_sse2) {
3103                                 if (ins->dreg != ins->sreg1)
3104                                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3105                         }
3106                         else {
3107                                 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE);
3108                                 /* ins->dreg is set to -1 by the reg allocator */
3109                                 amd64_movsd_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
3110                         }
3111                         break;
3112                 }
3113                 case OP_JMP: {
3114                         /*
3115                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3116                          * Keep in sync with the code in emit_epilog.
3117                          */
3118                         int pos = 0, i;
3119
3120                         /* FIXME: no tracing support... */
3121                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3122                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3123
3124                         g_assert (!cfg->method->save_lmf);
3125
3126                         code = emit_load_volatile_arguments (cfg, code);
3127
3128                         if (cfg->arch.omit_fp) {
3129                                 guint32 save_offset = 0;
3130                                 /* Pop callee-saved registers */
3131                                 for (i = 0; i < AMD64_NREG; ++i)
3132                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3133                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3134                                                 save_offset += 8;
3135                                         }
3136                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3137                         }
3138                         else {
3139                                 for (i = 0; i < AMD64_NREG; ++i)
3140                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3141                                                 pos -= sizeof (gpointer);
3142
3143                                 if (pos)
3144                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3145
3146                                 /* Pop registers in reverse order */
3147                                 for (i = AMD64_NREG - 1; i > 0; --i)
3148                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3149                                                 amd64_pop_reg (code, i);
3150                                         }
3151
3152                                 amd64_leave (code);
3153                         }
3154
3155                         offset = code - cfg->native_code;
3156                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3157                         if (cfg->compile_aot)
3158                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3159                         else
3160                                 amd64_set_reg_template (code, AMD64_R11);
3161                         amd64_jump_reg (code, AMD64_R11);
3162                         break;
3163                 }
3164                 case OP_CHECK_THIS:
3165                         /* ensure ins->sreg1 is not NULL */
3166                         amd64_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
3167                         break;
3168                 case OP_ARGLIST: {
3169                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3170                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3171                         break;
3172                 }
3173                 case OP_FCALL:
3174                 case OP_LCALL:
3175                 case OP_VCALL:
3176                 case OP_VOIDCALL:
3177                 case CEE_CALL:
3178                         call = (MonoCallInst*)ins;
3179                         /*
3180                          * The AMD64 ABI forces callers to know about varargs.
3181                          */
3182                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3183                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3184                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3185                                 /*
3186                                  * Since the unmanaged calling convention doesn't contain a
3187                                  * 'vararg' entry, we have to treat every pinvoke call as a
3188                                  * potential vararg call.
3189                                  */
3190                                 guint32 nregs, i;
3191                                 nregs = 0;
3192                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3193                                         if (call->used_fregs & (1 << i))
3194                                                 nregs ++;
3195                                 if (!nregs)
3196                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3197                                 else
3198                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3199                         }
3200
3201                         if (ins->flags & MONO_INST_HAS_METHOD)
3202                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3203                         else
3204                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3205                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3206                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3207                         code = emit_move_return_value (cfg, ins, code);
3208                         break;
3209                 case OP_FCALL_REG:
3210                 case OP_LCALL_REG:
3211                 case OP_VCALL_REG:
3212                 case OP_VOIDCALL_REG:
3213                 case OP_CALL_REG:
3214                         call = (MonoCallInst*)ins;
3215
3216                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3217                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3218                                 ins->sreg1 = AMD64_R11;
3219                         }
3220
3221                         /*
3222                          * The AMD64 ABI forces callers to know about varargs.
3223                          */
3224                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3225                                 if (ins->sreg1 == AMD64_RAX) {
3226                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3227                                         ins->sreg1 = AMD64_R11;
3228                                 }
3229                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3230                         }
3231                         amd64_call_reg (code, ins->sreg1);
3232                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3233                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3234                         code = emit_move_return_value (cfg, ins, code);
3235                         break;
3236                 case OP_FCALL_MEMBASE:
3237                 case OP_LCALL_MEMBASE:
3238                 case OP_VCALL_MEMBASE:
3239                 case OP_VOIDCALL_MEMBASE:
3240                 case OP_CALL_MEMBASE:
3241                         call = (MonoCallInst*)ins;
3242
3243                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3244                                 /*
3245                                  * Can't use R11 because it is clobbered by the trampoline
3246                                  * code, and the reg value is needed by get_vcall_slot_addr.
3247                                  */
3248                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3249                                 ins->sreg1 = AMD64_RAX;
3250                         }
3251
3252                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3253                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3254                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3255                         code = emit_move_return_value (cfg, ins, code);
3256                         break;
3257                 case OP_OUTARG:
3258                 case OP_X86_PUSH:
3259                         amd64_push_reg (code, ins->sreg1);
3260                         break;
3261                 case OP_X86_PUSH_IMM:
3262                         g_assert (amd64_is_imm32 (ins->inst_imm));
3263                         amd64_push_imm (code, ins->inst_imm);
3264                         break;
3265                 case OP_X86_PUSH_MEMBASE:
3266                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3267                         break;
3268                 case OP_X86_PUSH_OBJ:
3269                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3270                         amd64_push_reg (code, AMD64_RDI);
3271                         amd64_push_reg (code, AMD64_RSI);
3272                         amd64_push_reg (code, AMD64_RCX);
3273                         if (ins->inst_offset)
3274                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3275                         else
3276                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3277                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3278                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3279                         amd64_cld (code);
3280                         amd64_prefix (code, X86_REP_PREFIX);
3281                         amd64_movsd (code);
3282                         amd64_pop_reg (code, AMD64_RCX);
3283                         amd64_pop_reg (code, AMD64_RSI);
3284                         amd64_pop_reg (code, AMD64_RDI);
3285                         break;
3286                 case OP_X86_LEA:
3287                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3288                         break;
3289                 case OP_X86_LEA_MEMBASE:
3290                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3291                         break;
3292                 case OP_X86_XCHG:
3293                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3294                         break;
3295                 case OP_LOCALLOC:
3296                         /* keep alignment */
3297                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3298                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3299                         code = mono_emit_stack_alloc (code, ins);
3300                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3301                         break;
3302                 case CEE_RET:
3303                         amd64_ret (code);
3304                         break;
3305                 case OP_THROW: {
3306                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3307                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3308                                              (gpointer)"mono_arch_throw_exception");
3309                         break;
3310                 }
3311                 case OP_RETHROW: {
3312                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3313                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3314                                              (gpointer)"mono_arch_rethrow_exception");
3315                         break;
3316                 }
3317                 case OP_CALL_HANDLER:
3318                         /* Align stack */
3319                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3320                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3321                         amd64_call_imm (code, 0);
3322                         /* Restore stack alignment */
3323                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3324                         break;
3325
3326                 case OP_LABEL:
3327                         ins->inst_c0 = code - cfg->native_code;
3328                         break;
3329                 case OP_NOP:
3330                         break;
3331                 case OP_BR:
3332                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3333                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3334                         //break;
3335                         if (ins->flags & MONO_INST_BRLABEL) {
3336                                 if (ins->inst_i0->inst_c0) {
3337                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3338                                 } else {
3339                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3340                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3341                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3342                                                 x86_jump8 (code, 0);
3343                                         else
3344                                                 x86_jump32 (code, 0);
3345                                 }
3346                         } else {
3347                                 if (ins->inst_target_bb->native_offset) {
3348                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3349                                 } else {
3350                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3351                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3352                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3353                                                 x86_jump8 (code, 0);
3354                                         else
3355                                                 x86_jump32 (code, 0);
3356                                 }
3357                         }
3358                         break;
3359                 case OP_BR_REG:
3360                         amd64_jump_reg (code, ins->sreg1);
3361                         break;
3362                 case OP_CEQ:
3363                 case OP_ICEQ:
3364                 case OP_CLT:
3365                 case OP_ICLT:
3366                 case OP_CGT:
3367                 case OP_ICGT:
3368                 case OP_CLT_UN:
3369                 case OP_ICLT_UN:
3370                 case OP_CGT_UN:
3371                 case OP_ICGT_UN:
3372                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3373                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3374                         break;
3375                 case OP_COND_EXC_EQ:
3376                 case OP_COND_EXC_NE_UN:
3377                 case OP_COND_EXC_LT:
3378                 case OP_COND_EXC_LT_UN:
3379                 case OP_COND_EXC_GT:
3380                 case OP_COND_EXC_GT_UN:
3381                 case OP_COND_EXC_GE:
3382                 case OP_COND_EXC_GE_UN:
3383                 case OP_COND_EXC_LE:
3384                 case OP_COND_EXC_LE_UN:
3385                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3386                         break;
3387                 case OP_COND_EXC_OV:
3388                 case OP_COND_EXC_NO:
3389                 case OP_COND_EXC_C:
3390                 case OP_COND_EXC_NC:
3391                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3392                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3393                         break;
3394                 case OP_COND_EXC_IOV:
3395                 case OP_COND_EXC_IC:
3396                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3397                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3398                         break;
3399                 case CEE_BEQ:
3400                 case CEE_BNE_UN:
3401                 case CEE_BLT:
3402                 case CEE_BLT_UN:
3403                 case CEE_BGT:
3404                 case CEE_BGT_UN:
3405                 case CEE_BGE:
3406                 case CEE_BGE_UN:
3407                 case CEE_BLE:
3408                 case CEE_BLE_UN:
3409                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3410                         break;
3411
3412                 /* floating point opcodes */
3413                 case OP_R8CONST: {
3414                         double d = *(double *)ins->inst_p0;
3415
3416                         if (use_sse2) {
3417                                 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3418                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3419                                 }
3420                                 else {
3421                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3422                                         amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3423                                 }
3424                         }
3425                         else if ((d == 0.0) && (mono_signbit (d) == 0)) {
3426                                 amd64_fldz (code);
3427                         } else if (d == 1.0) {
3428                                 x86_fld1 (code);
3429                         } else {
3430                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3431                                 amd64_fld_membase (code, AMD64_RIP, 0, TRUE);
3432                         }
3433                         break;
3434                 }
3435                 case OP_R4CONST: {
3436                         float f = *(float *)ins->inst_p0;
3437
3438                         if (use_sse2) {
3439                                 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3440                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3441                                 }
3442                                 else {
3443                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3444                                         amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3445                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3446                                 }
3447                         }
3448                         else if ((f == 0.0) && (mono_signbit (f) == 0)) {
3449                                 amd64_fldz (code);
3450                         } else if (f == 1.0) {
3451                                 x86_fld1 (code);
3452                         } else {
3453                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3454                                 amd64_fld_membase (code, AMD64_RIP, 0, FALSE);
3455                         }
3456                         break;
3457                 }
3458                 case OP_STORER8_MEMBASE_REG:
3459                         if (use_sse2)
3460                                 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3461                         else
3462                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3463                         break;
3464                 case OP_LOADR8_SPILL_MEMBASE:
3465                         if (use_sse2)
3466                                 g_assert_not_reached ();
3467                         amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3468                         amd64_fxch (code, 1);
3469                         break;
3470                 case OP_LOADR8_MEMBASE:
3471                         if (use_sse2)
3472                                 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3473                         else
3474                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3475                         break;
3476                 case OP_STORER4_MEMBASE_REG:
3477                         if (use_sse2) {
3478                                 /* This requires a double->single conversion */
3479                                 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3480                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3481                         }
3482                         else
3483                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3484                         break;
3485                 case OP_LOADR4_MEMBASE:
3486                         if (use_sse2) {
3487                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3488                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3489                         }
3490                         else
3491                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3492                         break;
3493                 case CEE_CONV_R4: /* FIXME: change precision */
3494                 case CEE_CONV_R8:
3495                         if (use_sse2)
3496                                 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3497                         else {
3498                                 amd64_push_reg (code, ins->sreg1);
3499                                 amd64_fild_membase (code, AMD64_RSP, 0, FALSE);
3500                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3501                         }
3502                         break;
3503                 case CEE_CONV_R_UN:
3504                         /* Emulated */
3505                         g_assert_not_reached ();
3506                         break;
3507                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3508                 case OP_LCONV_TO_R8:
3509                         if (use_sse2)
3510                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3511                         else {
3512                                 amd64_push_reg (code, ins->sreg1);
3513                                 amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3514                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3515                         }
3516                         break;
3517                 case OP_X86_FP_LOAD_I8:
3518                         if (use_sse2)
3519                                 g_assert_not_reached ();
3520                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3521                         break;
3522                 case OP_X86_FP_LOAD_I4:
3523                         if (use_sse2)
3524                                 g_assert_not_reached ();
3525                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3526                         break;
3527                 case OP_FCONV_TO_I1:
3528                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3529                         break;
3530                 case OP_FCONV_TO_U1:
3531                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3532                         break;
3533                 case OP_FCONV_TO_I2:
3534                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3535                         break;
3536                 case OP_FCONV_TO_U2:
3537                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3538                         break;
3539                 case OP_FCONV_TO_I4:
3540                 case OP_FCONV_TO_I:
3541                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3542                         break;
3543                 case OP_FCONV_TO_I8:
3544                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3545                         break;
3546                 case OP_LCONV_TO_R_UN: {
3547                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3548                         guint8 *br;
3549
3550                         if (use_sse2)
3551                                 g_assert_not_reached ();
3552
3553                         /* load 64bit integer to FP stack */
3554                         amd64_push_imm (code, 0);
3555                         amd64_push_reg (code, ins->sreg2);
3556                         amd64_push_reg (code, ins->sreg1);
3557                         amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3558                         /* store as 80bit FP value */
3559                         x86_fst80_membase (code, AMD64_RSP, 0);
3560
3561                         /* test if lreg is negative */
3562                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
3563                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3564
3565                         /* add correction constant mn */
3566                         x86_fld80_mem (code, mn);
3567                         x86_fld80_membase (code, AMD64_RSP, 0);
3568                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3569                         x86_fst80_membase (code, AMD64_RSP, 0);
3570
3571                         amd64_patch (br, code);
3572
3573                         x86_fld80_membase (code, AMD64_RSP, 0);
3574                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 12);
3575
3576                         break;
3577                 }
3578                 case CEE_CONV_OVF_U4:
3579                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3580                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3581                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3582                         break;
3583                 case CEE_CONV_OVF_I4_UN:
3584                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3585                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3586                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3587                         break;
3588                 case OP_FMOVE:
3589                         if (use_sse2 && (ins->dreg != ins->sreg1))
3590                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3591                         break;
3592                 case OP_FADD:
3593                         if (use_sse2)
3594                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3595                         else
3596                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3597                         break;
3598                 case OP_FSUB:
3599                         if (use_sse2)
3600                                 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3601                         else
3602                                 amd64_fp_op_reg (code, X86_FSUB, 1, TRUE);
3603                         break;
3604                 case OP_FMUL:
3605                         if (use_sse2)
3606                                 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3607                         else
3608                                 amd64_fp_op_reg (code, X86_FMUL, 1, TRUE);
3609                         break;
3610                 case OP_FDIV:
3611                         if (use_sse2)
3612                                 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3613                         else
3614                                 amd64_fp_op_reg (code, X86_FDIV, 1, TRUE);
3615                         break;
3616                 case OP_FNEG:
3617                         if (use_sse2) {
3618                                 static double r8_0 = -0.0;
3619
3620                                 g_assert (ins->sreg1 == ins->dreg);
3621
3622                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3623                                 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3624                         }
3625                         else
3626                                 amd64_fchs (code);
3627                         break;
3628                 case OP_SIN:
3629                         if (use_sse2) {
3630                                 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3631                         }
3632                         else {
3633                                 amd64_fsin (code);
3634                                 amd64_fldz (code);
3635                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3636                         }
3637                         break;
3638                 case OP_COS:
3639                         if (use_sse2) {
3640                                 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3641                         }
3642                         else {
3643                                 amd64_fcos (code);
3644                                 amd64_fldz (code);
3645                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3646                         }
3647                         break;
3648                 case OP_ABS:
3649                         if (use_sse2) {
3650                                 EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
3651                         }
3652                         else
3653                                 amd64_fabs (code);
3654                         break;
3655                 case OP_TAN: {
3656                         /*
3657                          * it really doesn't make sense to inline all this code,
3658                          * it's here just to show that things may not be as simple
3659                          * as they appear.
3660                          */
3661                         guchar *check_pos, *end_tan, *pop_jump;
3662                         if (use_sse2)
3663                                 g_assert_not_reached ();
3664                         amd64_push_reg (code, AMD64_RAX);
3665                         amd64_fptan (code);
3666                         amd64_fnstsw (code);
3667                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3668                         check_pos = code;
3669                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3670                         amd64_fstp (code, 0); /* pop the 1.0 */
3671                         end_tan = code;
3672                         x86_jump8 (code, 0);
3673                         amd64_fldpi (code);
3674                         amd64_fp_op (code, X86_FADD, 0);
3675                         amd64_fxch (code, 1);
3676                         x86_fprem1 (code);
3677                         amd64_fstsw (code);
3678                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3679                         pop_jump = code;
3680                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3681                         amd64_fstp (code, 1);
3682                         amd64_fptan (code);
3683                         amd64_patch (pop_jump, code);
3684                         amd64_fstp (code, 0); /* pop the 1.0 */
3685                         amd64_patch (check_pos, code);
3686                         amd64_patch (end_tan, code);
3687                         amd64_fldz (code);
3688                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3689                         amd64_pop_reg (code, AMD64_RAX);
3690                         break;
3691                 }
3692                 case OP_ATAN:
3693                         if (use_sse2)
3694                                 g_assert_not_reached ();
3695                         x86_fld1 (code);
3696                         amd64_fpatan (code);
3697                         amd64_fldz (code);
3698                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3699                         break;
3700                 case OP_SQRT:
3701                         if (use_sse2) {
3702                                 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3703                         }
3704                         else
3705                                 amd64_fsqrt (code);
3706                         break;
3707                 case OP_X86_FPOP:
3708                         if (!use_sse2)
3709                                 amd64_fstp (code, 0);
3710                         break;
3711                 case OP_FREM: {
3712                         guint8 *l1, *l2;
3713
3714                         if (use_sse2)
3715                                 g_assert_not_reached ();
3716                         amd64_push_reg (code, AMD64_RAX);
3717                         /* we need to exchange ST(0) with ST(1) */
3718                         amd64_fxch (code, 1);
3719
3720                         /* this requires a loop, because fprem somtimes
3721                          * returns a partial remainder */
3722                         l1 = code;
3723                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3724                         /* x86_fprem1 (code); */
3725                         amd64_fprem (code);
3726                         amd64_fnstsw (code);
3727                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_C2);
3728                         l2 = code + 2;
3729                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3730
3731                         /* pop result */
3732                         amd64_fstp (code, 1);
3733
3734                         amd64_pop_reg (code, AMD64_RAX);
3735                         break;
3736                 }
3737                 case OP_FCOMPARE:
3738                         if (use_sse2) {
3739                                 /*
3740                                  * The two arguments are swapped because the fbranch instructions
3741                                  * depend on this for the non-sse case to work.
3742                                  */
3743                                 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3744                                 break;
3745                         }
3746                         if (cfg->opt & MONO_OPT_FCMOV) {
3747                                 amd64_fcomip (code, 1);
3748                                 amd64_fstp (code, 0);
3749                                 break;
3750                         }
3751                         /* this overwrites EAX */
3752                         EMIT_FPCOMPARE(code);
3753                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3754                         break;
3755                 case OP_FCEQ:
3756                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3757                                 /* zeroing the register at the start results in
3758                                  * shorter and faster code (we can also remove the widening op)
3759                                  */
3760                                 guchar *unordered_check;
3761                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3762
3763                                 if (use_sse2)
3764                                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3765                                 else {
3766                                         amd64_fcomip (code, 1);
3767                                         amd64_fstp (code, 0);
3768                                 }
3769                                 unordered_check = code;
3770                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3771                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3772                                 amd64_patch (unordered_check, code);
3773                                 break;
3774                         }
3775                         if (ins->dreg != AMD64_RAX)
3776                                 amd64_push_reg (code, AMD64_RAX);
3777
3778                         EMIT_FPCOMPARE(code);
3779                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3780                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3781                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3782                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3783
3784                         if (ins->dreg != AMD64_RAX)
3785                                 amd64_pop_reg (code, AMD64_RAX);
3786                         break;
3787                 case OP_FCLT:
3788                 case OP_FCLT_UN:
3789                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3790                                 /* zeroing the register at the start results in
3791                                  * shorter and faster code (we can also remove the widening op)
3792                                  */
3793                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3794                                 if (use_sse2)
3795                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3796                                 else {
3797                                         amd64_fcomip (code, 1);
3798                                         amd64_fstp (code, 0);
3799                                 }
3800                                 if (ins->opcode == OP_FCLT_UN) {
3801                                         guchar *unordered_check = code;
3802                                         guchar *jump_to_end;
3803                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3804                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3805                                         jump_to_end = code;
3806                                         x86_jump8 (code, 0);
3807                                         amd64_patch (unordered_check, code);
3808                                         amd64_inc_reg (code, ins->dreg);
3809                                         amd64_patch (jump_to_end, code);
3810                                 } else {
3811                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3812                                 }
3813                                 break;
3814                         }
3815                         if (ins->dreg != AMD64_RAX)
3816                                 amd64_push_reg (code, AMD64_RAX);
3817
3818                         EMIT_FPCOMPARE(code);
3819                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3820                         if (ins->opcode == OP_FCLT_UN) {
3821                                 guchar *is_not_zero_check, *end_jump;
3822                                 is_not_zero_check = code;
3823                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3824                                 end_jump = code;
3825                                 x86_jump8 (code, 0);
3826                                 amd64_patch (is_not_zero_check, code);
3827                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3828
3829                                 amd64_patch (end_jump, code);
3830                         }
3831                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3832                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3833
3834                         if (ins->dreg != AMD64_RAX)
3835                                 amd64_pop_reg (code, AMD64_RAX);
3836                         break;
3837                 case OP_FCGT:
3838                 case OP_FCGT_UN:
3839                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3840                                 /* zeroing the register at the start results in
3841                                  * shorter and faster code (we can also remove the widening op)
3842                                  */
3843                                 guchar *unordered_check;
3844                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3845                                 if (use_sse2)
3846                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3847                                 else {
3848                                         amd64_fcomip (code, 1);
3849                                         amd64_fstp (code, 0);
3850                                 }
3851                                 if (ins->opcode == OP_FCGT) {
3852                                         unordered_check = code;
3853                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3854                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3855                                         amd64_patch (unordered_check, code);
3856                                 } else {
3857                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3858                                 }
3859                                 break;
3860                         }
3861                         if (ins->dreg != AMD64_RAX)
3862                                 amd64_push_reg (code, AMD64_RAX);
3863
3864                         EMIT_FPCOMPARE(code);
3865                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3866                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3867                         if (ins->opcode == OP_FCGT_UN) {
3868                                 guchar *is_not_zero_check, *end_jump;
3869                                 is_not_zero_check = code;
3870                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3871                                 end_jump = code;
3872                                 x86_jump8 (code, 0);
3873                                 amd64_patch (is_not_zero_check, code);
3874                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3875
3876                                 amd64_patch (end_jump, code);
3877                         }
3878                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3879                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3880
3881                         if (ins->dreg != AMD64_RAX)
3882                                 amd64_pop_reg (code, AMD64_RAX);
3883                         break;
3884                 case OP_FCLT_MEMBASE:
3885                 case OP_FCGT_MEMBASE:
3886                 case OP_FCLT_UN_MEMBASE:
3887                 case OP_FCGT_UN_MEMBASE:
3888                 case OP_FCEQ_MEMBASE: {
3889                         guchar *unordered_check, *jump_to_end;
3890                         int x86_cond;
3891                         g_assert (use_sse2);
3892
3893                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3894                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
3895
3896                         switch (ins->opcode) {
3897                         case OP_FCEQ_MEMBASE:
3898                                 x86_cond = X86_CC_EQ;
3899                                 break;
3900                         case OP_FCLT_MEMBASE:
3901                         case OP_FCLT_UN_MEMBASE:
3902                                 x86_cond = X86_CC_LT;
3903                                 break;
3904                         case OP_FCGT_MEMBASE:
3905                         case OP_FCGT_UN_MEMBASE:
3906                                 x86_cond = X86_CC_GT;
3907                                 break;
3908                         default:
3909                                 g_assert_not_reached ();
3910                         }
3911
3912                         unordered_check = code;
3913                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3914                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
3915
3916                         switch (ins->opcode) {
3917                         case OP_FCEQ_MEMBASE:
3918                         case OP_FCLT_MEMBASE:
3919                         case OP_FCGT_MEMBASE:
3920                                 amd64_patch (unordered_check, code);
3921                                 break;
3922                         case OP_FCLT_UN_MEMBASE:
3923                         case OP_FCGT_UN_MEMBASE:
3924                                 jump_to_end = code;
3925                                 x86_jump8 (code, 0);
3926                                 amd64_patch (unordered_check, code);
3927                                 amd64_inc_reg (code, ins->dreg);
3928                                 amd64_patch (jump_to_end, code);
3929                                 break;
3930                         default:
3931                                 break;
3932                         }
3933                         break;
3934                 }
3935                 case OP_FBEQ:
3936                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3937                                 guchar *jump = code;
3938                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
3939                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3940                                 amd64_patch (jump, code);
3941                                 break;
3942                         }
3943                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3944                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3945                         break;
3946                 case OP_FBNE_UN:
3947                         /* Branch if C013 != 100 */
3948                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3949                                 /* branch if !ZF or (PF|CF) */
3950                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3951                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3952                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3953                                 break;
3954                         }
3955                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3956                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3957                         break;
3958                 case OP_FBLT:
3959                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3960                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3961                                 break;
3962                         }
3963                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3964                         break;
3965                 case OP_FBLT_UN:
3966                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3967                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3968                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3969                                 break;
3970                         }
3971                         if (ins->opcode == OP_FBLT_UN) {
3972                                 guchar *is_not_zero_check, *end_jump;
3973                                 is_not_zero_check = code;
3974                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3975                                 end_jump = code;
3976                                 x86_jump8 (code, 0);
3977                                 amd64_patch (is_not_zero_check, code);
3978                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3979
3980                                 amd64_patch (end_jump, code);
3981                         }
3982                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3983                         break;
3984                 case OP_FBGT:
3985                 case OP_FBGT_UN:
3986                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3987                                 if (ins->opcode == OP_FBGT) {
3988                                         guchar *br1;
3989
3990                                         /* skip branch if C1=1 */
3991                                         br1 = code;
3992                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3993                                         /* branch if (C0 | C3) = 1 */
3994                                         EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3995                                         amd64_patch (br1, code);
3996                                         break;
3997                                 } else {
3998                                         EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3999                                 }
4000                                 break;
4001                         }
4002                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4003                         if (ins->opcode == OP_FBGT_UN) {
4004                                 guchar *is_not_zero_check, *end_jump;
4005                                 is_not_zero_check = code;
4006                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4007                                 end_jump = code;
4008                                 x86_jump8 (code, 0);
4009                                 amd64_patch (is_not_zero_check, code);
4010                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
4011
4012                                 amd64_patch (end_jump, code);
4013                         }
4014                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4015                         break;
4016                 case OP_FBGE:
4017                         /* Branch if C013 == 100 or 001 */
4018                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4019                                 guchar *br1;
4020
4021                                 /* skip branch if C1=1 */
4022                                 br1 = code;
4023                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4024                                 /* branch if (C0 | C3) = 1 */
4025                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4026                                 amd64_patch (br1, code);
4027                                 break;
4028                         }
4029                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4030                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4031                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
4032                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4033                         break;
4034                 case OP_FBGE_UN:
4035                         /* Branch if C013 == 000 */
4036                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4037                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4038                                 break;
4039                         }
4040                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4041                         break;
4042                 case OP_FBLE:
4043                         /* Branch if C013=000 or 100 */
4044                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4045                                 guchar *br1;
4046
4047                                 /* skip branch if C1=1 */
4048                                 br1 = code;
4049                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4050                                 /* branch if C0=0 */
4051                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4052                                 amd64_patch (br1, code);
4053                                 break;
4054                         }
4055                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, (X86_FP_C0|X86_FP_C1));
4056                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4057                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4058                         break;
4059                 case OP_FBLE_UN:
4060                         /* Branch if C013 != 001 */
4061                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4062                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4063                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4064                                 break;
4065                         }
4066                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4067                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4068                         break;
4069                 case OP_CKFINITE: {
4070                         if (use_sse2) {
4071                                 /* Transfer value to the fp stack */
4072                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4073                                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4074                                 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4075                         }
4076                         amd64_push_reg (code, AMD64_RAX);
4077                         amd64_fxam (code);
4078                         amd64_fnstsw (code);
4079                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4080                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4081                         amd64_pop_reg (code, AMD64_RAX);
4082                         if (use_sse2) {
4083                                 amd64_fstp (code, 0);
4084                         }
4085                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4086                         if (use_sse2)
4087                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4088                         break;
4089                 }
4090                 case OP_TLS_GET: {
4091                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4092                         break;
4093                 }
4094                 case OP_MEMORY_BARRIER: {
4095                         /* Not needed on amd64 */
4096                         break;
4097                 }
4098                 case OP_ATOMIC_ADD_I4:
4099                 case OP_ATOMIC_ADD_I8: {
4100                         int dreg = ins->dreg;
4101                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4102
4103                         if (dreg == ins->inst_basereg)
4104                                 dreg = AMD64_R11;
4105
4106                         if (dreg != ins->sreg2)
4107                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4108
4109                         x86_prefix (code, X86_LOCK_PREFIX);
4110                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4111
4112                         if (dreg != ins->dreg)
4113                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4114
4115                         break;
4116                 }
4117                 case OP_ATOMIC_ADD_NEW_I4:
4118                 case OP_ATOMIC_ADD_NEW_I8: {
4119                         int dreg = ins->dreg;
4120                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4121
4122                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4123                                 dreg = AMD64_R11;
4124
4125                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4126                         amd64_prefix (code, X86_LOCK_PREFIX);
4127                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4128                         /* dreg contains the old value, add with sreg2 value */
4129                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4130
4131                         if (ins->dreg != dreg)
4132                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4133
4134                         break;
4135                 }
4136                 case OP_ATOMIC_EXCHANGE_I4:
4137                 case OP_ATOMIC_EXCHANGE_I8: {
4138                         guchar *br[2];
4139                         int sreg2 = ins->sreg2;
4140                         int breg = ins->inst_basereg;
4141                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
4142
4143                         /*
4144                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
4145                          * an explanation of how this works.
4146                          */
4147
4148                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4149                          * hack to overcome limits in x86 reg allocator
4150                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4151                          */
4152                         /* The pushes invalidate rsp */
4153                         if ((breg == AMD64_RAX) || (breg == AMD64_RSP)) {
4154                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4155                                 breg = AMD64_R11;
4156                         }
4157
4158                         if (ins->dreg != AMD64_RAX)
4159                                 amd64_push_reg (code, AMD64_RAX);
4160
4161                         /* We need the EAX reg for the cmpxchg */
4162                         if (ins->sreg2 == AMD64_RAX) {
4163                                 amd64_push_reg (code, AMD64_RDX);
4164                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4165                                 sreg2 = AMD64_RDX;
4166                         }
4167
4168                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4169
4170                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4171                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4172                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4173                         amd64_patch (br [1], br [0]);
4174
4175                         if (ins->dreg != AMD64_RAX) {
4176                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4177                                 amd64_pop_reg (code, AMD64_RAX);
4178                         }
4179
4180                         if (ins->sreg2 != sreg2)
4181                                 amd64_pop_reg (code, AMD64_RDX);
4182
4183                         break;
4184                 }
4185                 default:
4186                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4187                         g_assert_not_reached ();
4188                 }
4189
4190                 if ((code - cfg->native_code - offset) > max_len) {
4191                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4192                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4193                         g_assert_not_reached ();
4194                 }
4195
4196                 cpos += max_len;
4197
4198                 last_ins = ins;
4199                 last_offset = offset;
4200
4201                 ins = ins->next;
4202         }
4203
4204         cfg->code_len = code - cfg->native_code;
4205 }
4206
4207 void
4208 mono_arch_register_lowlevel_calls (void)
4209 {
4210 }
4211
4212 void
4213 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4214 {
4215         MonoJumpInfo *patch_info;
4216         gboolean compile_aot = !run_cctors;
4217
4218         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4219                 unsigned char *ip = patch_info->ip.i + code;
4220                 const unsigned char *target;
4221
4222                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4223
4224                 if (compile_aot) {
4225                         switch (patch_info->type) {
4226                         case MONO_PATCH_INFO_BB:
4227                         case MONO_PATCH_INFO_LABEL:
4228                                 break;
4229                         default:
4230                                 /* No need to patch these */
4231                                 continue;
4232                         }
4233                 }
4234
4235                 switch (patch_info->type) {
4236                 case MONO_PATCH_INFO_NONE:
4237                         continue;
4238                 case MONO_PATCH_INFO_METHOD_REL:
4239                 case MONO_PATCH_INFO_R8:
4240                 case MONO_PATCH_INFO_R4:
4241                         g_assert_not_reached ();
4242                         continue;
4243                 case MONO_PATCH_INFO_BB:
4244                         break;
4245                 default:
4246                         break;
4247                 }
4248
4249                 /*
4250                  * Debug code to help track down problems where the target of a near call is
4251                  * is not valid.
4252                  */
4253                 if (amd64_is_near_call (ip)) {
4254                         gint64 disp = (guint8*)target - (guint8*)ip;
4255
4256                         if (!amd64_is_imm32 (disp)) {
4257                                 printf ("TYPE: %d\n", patch_info->type);
4258                                 switch (patch_info->type) {
4259                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4260                                         printf ("V: %s\n", patch_info->data.name);
4261                                         break;
4262                                 case MONO_PATCH_INFO_METHOD_JUMP:
4263                                 case MONO_PATCH_INFO_METHOD:
4264                                         printf ("V: %s\n", patch_info->data.method->name);
4265                                         break;
4266                                 default:
4267                                         break;
4268                                 }
4269                         }
4270                 }
4271
4272                 amd64_patch (ip, (gpointer)target);
4273         }
4274 }
4275
4276 guint8 *
4277 mono_arch_emit_prolog (MonoCompile *cfg)
4278 {
4279         MonoMethod *method = cfg->method;
4280         MonoBasicBlock *bb;
4281         MonoMethodSignature *sig;
4282         MonoInst *inst;
4283         int alloc_size, pos, max_offset, i, quad;
4284         guint8 *code;
4285         CallInfo *cinfo;
4286         gint32 lmf_offset = cfg->arch.lmf_offset;
4287
4288         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
4289         code = cfg->native_code = g_malloc (cfg->code_size);
4290
4291         /* Amount of stack space allocated by register saving code */
4292         pos = 0;
4293
4294         /*
4295          * The prolog consists of the following parts:
4296          * FP present:
4297          * - push rbp, mov rbp, rsp
4298          * - save callee saved regs using pushes
4299          * - allocate frame
4300          * - save lmf if needed
4301          * FP not present:
4302          * - allocate frame
4303          * - save lmf if needed
4304          * - save callee saved regs using moves
4305          */
4306
4307         if (!cfg->arch.omit_fp) {
4308                 amd64_push_reg (code, AMD64_RBP);
4309                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4310         }
4311
4312         /* Save callee saved registers */
4313         if (!cfg->arch.omit_fp && !method->save_lmf) {
4314                 for (i = 0; i < AMD64_NREG; ++i)
4315                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4316                                 amd64_push_reg (code, i);
4317                                 pos += sizeof (gpointer);
4318                         }
4319         }
4320
4321         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4322
4323         alloc_size -= pos;
4324
4325         if (cfg->arch.omit_fp)
4326                 /*
4327                  * On enter, the stack is misaligned by the the pushing of the return
4328                  * address. It is either made aligned by the pushing of %rbp, or by
4329                  * this.
4330                  */
4331                 alloc_size += 8;
4332
4333         cfg->arch.stack_alloc_size = alloc_size;
4334
4335         /* Allocate stack frame */
4336         if (alloc_size) {
4337                 /* See mono_emit_stack_alloc */
4338 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4339                 guint32 remaining_size = alloc_size;
4340                 while (remaining_size >= 0x1000) {
4341                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4342                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4343                         remaining_size -= 0x1000;
4344                 }
4345                 if (remaining_size)
4346                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4347 #else
4348                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4349 #endif
4350         }
4351
4352         /* Stack alignment check */
4353 #if 0
4354         {
4355                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4356                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4357                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4358                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4359                 amd64_breakpoint (code);
4360         }
4361 #endif
4362
4363         /* Save LMF */
4364         if (method->save_lmf) {
4365                 /* Save ip */
4366                 amd64_lea_membase (code, AMD64_R11, AMD64_RIP, 0);
4367                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, 8);
4368                 /* Save fp */
4369                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), AMD64_RBP, 8);
4370                 /* Save sp */
4371                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4372                 /* Skip method (only needed for trampoline LMF frames) */
4373                 /* Save callee saved regs */
4374                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4375                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4376                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4377                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4378                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4379         }
4380
4381         /* Save callee saved registers */
4382         if (cfg->arch.omit_fp && !method->save_lmf) {
4383                 gint32 save_area_offset = 0;
4384
4385                 /* Save caller saved registers after sp is adjusted */
4386                 /* The registers are saved at the bottom of the frame */
4387                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4388                 for (i = 0; i < AMD64_NREG; ++i)
4389                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4390                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4391                                 save_area_offset += 8;
4392                         }
4393         }
4394
4395         /* compute max_offset in order to use short forward jumps */
4396         max_offset = 0;
4397         if (cfg->opt & MONO_OPT_BRANCH) {
4398                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4399                         MonoInst *ins = bb->code;
4400                         bb->max_offset = max_offset;
4401
4402                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4403                                 max_offset += 6;
4404                         /* max alignment for loops */
4405                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4406                                 max_offset += LOOP_ALIGNMENT;
4407
4408                         while (ins) {
4409                                 if (ins->opcode == OP_LABEL)
4410                                         ins->inst_c1 = max_offset;
4411
4412                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4413                                 ins = ins->next;
4414                         }
4415                 }
4416         }
4417
4418         sig = mono_method_signature (method);
4419         pos = 0;
4420
4421         cinfo = cfg->arch.cinfo;
4422
4423         if (sig->ret->type != MONO_TYPE_VOID) {
4424                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
4425                         /* Save volatile arguments to the stack */
4426                         amd64_mov_membase_reg (code, cfg->ret->inst_basereg, cfg->ret->inst_offset, cinfo->ret.reg, 8);
4427                 }
4428         }
4429
4430         /* Keep this in sync with emit_load_volatile_arguments */
4431         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4432                 ArgInfo *ainfo = cinfo->args + i;
4433                 gint32 stack_offset;
4434                 MonoType *arg_type;
4435                 inst = cfg->args [i];
4436
4437                 if (sig->hasthis && (i == 0))
4438                         arg_type = &mono_defaults.object_class->byval_arg;
4439                 else
4440                         arg_type = sig->params [i - sig->hasthis];
4441
4442                 stack_offset = ainfo->offset + ARGS_OFFSET;
4443
4444                 /* Save volatile arguments to the stack */
4445                 if (inst->opcode != OP_REGVAR) {
4446                         switch (ainfo->storage) {
4447                         case ArgInIReg: {
4448                                 guint32 size = 8;
4449
4450                                 /* FIXME: I1 etc */
4451                                 /*
4452                                 if (stack_offset & 0x1)
4453                                         size = 1;
4454                                 else if (stack_offset & 0x2)
4455                                         size = 2;
4456                                 else if (stack_offset & 0x4)
4457                                         size = 4;
4458                                 else
4459                                         size = 8;
4460                                 */
4461                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, size);
4462                                 break;
4463                         }
4464                         case ArgInFloatSSEReg:
4465                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4466                                 break;
4467                         case ArgInDoubleSSEReg:
4468                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4469                                 break;
4470                         case ArgValuetypeInReg:
4471                                 for (quad = 0; quad < 2; quad ++) {
4472                                         switch (ainfo->pair_storage [quad]) {
4473                                         case ArgInIReg:
4474                                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4475                                                 break;
4476                                         case ArgInFloatSSEReg:
4477                                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4478                                                 break;
4479                                         case ArgInDoubleSSEReg:
4480                                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4481                                                 break;
4482                                         case ArgNone:
4483                                                 break;
4484                                         default:
4485                                                 g_assert_not_reached ();
4486                                         }
4487                                 }
4488                                 break;
4489                         default:
4490                                 break;
4491                         }
4492                 }
4493
4494                 if (inst->opcode == OP_REGVAR) {
4495                         /* Argument allocated to (non-volatile) register */
4496                         switch (ainfo->storage) {
4497                         case ArgInIReg:
4498                                 amd64_mov_reg_reg (code, inst->dreg, ainfo->reg, 8);
4499                                 break;
4500                         case ArgOnStack:
4501                                 amd64_mov_reg_membase (code, inst->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4502                                 break;
4503                         default:
4504                                 g_assert_not_reached ();
4505                         }
4506                 }
4507         }
4508
4509         /* Might need to attach the thread to the JIT */
4510         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4511                 guint64 domain = (guint64)cfg->domain;
4512
4513                 /*
4514                  * The call might clobber argument registers, but they are already
4515                  * saved to the stack/global regs.
4516                  */
4517                 if (lmf_addr_tls_offset != -1) {
4518                         guint8 *buf;
4519
4520                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4521                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4522                         buf = code;
4523                         x86_branch8 (code, X86_CC_NE, 0, 0);
4524                         if ((domain >> 32) == 0)
4525                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 4);
4526                         else
4527                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 8);
4528                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4529                         amd64_patch (buf, code);
4530                 } else {
4531                         g_assert (!cfg->compile_aot);
4532                         if ((domain >> 32) == 0)
4533                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 4);
4534                         else
4535                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 8);
4536                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4537                 }
4538         }
4539
4540         if (method->save_lmf) {
4541                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4542                         /*
4543                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4544                          * through the mono_lmf_addr TLS variable.
4545                          */
4546                         /* %rax = previous_lmf */
4547                         x86_prefix (code, X86_FS_PREFIX);
4548                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4549
4550                         /* Save previous_lmf */
4551                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4552                         /* Set new lmf */
4553                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4554                         x86_prefix (code, X86_FS_PREFIX);
4555                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4556                 } else {
4557                         if (lmf_addr_tls_offset != -1) {
4558                                 /* Load lmf quicky using the FS register */
4559                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4560                         }
4561                         else {
4562                                 /*
4563                                  * The call might clobber argument registers, but they are already
4564                                  * saved to the stack/global regs.
4565                                  */
4566                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4567                                                                   (gpointer)"mono_get_lmf_addr");
4568                         }
4569
4570                         /* Save lmf_addr */
4571                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4572                         /* Save previous_lmf */
4573                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4574                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4575                         /* Set new lmf */
4576                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4577                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4578                 }
4579         }
4580
4581         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4582                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4583
4584         cfg->code_len = code - cfg->native_code;
4585
4586         g_assert (cfg->code_len < cfg->code_size);
4587
4588         return code;
4589 }
4590
4591 void
4592 mono_arch_emit_epilog (MonoCompile *cfg)
4593 {
4594         MonoMethod *method = cfg->method;
4595         int quad, pos, i;
4596         guint8 *code;
4597         int max_epilog_size = 16;
4598         CallInfo *cinfo;
4599         gint32 lmf_offset = cfg->arch.lmf_offset;
4600
4601         if (cfg->method->save_lmf)
4602                 max_epilog_size += 256;
4603
4604         if (mono_jit_trace_calls != NULL)
4605                 max_epilog_size += 50;
4606
4607         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4608                 max_epilog_size += 50;
4609
4610         max_epilog_size += (AMD64_NREG * 2);
4611
4612         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4613                 cfg->code_size *= 2;
4614                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4615                 mono_jit_stats.code_reallocs++;
4616         }
4617
4618         code = cfg->native_code + cfg->code_len;
4619
4620         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4621                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4622
4623         /* the code restoring the registers must be kept in sync with OP_JMP */
4624         pos = 0;
4625
4626         if (method->save_lmf) {
4627                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4628                         /*
4629                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4630                          * through the mono_lmf_addr TLS variable.
4631                          */
4632                         /* reg = previous_lmf */
4633                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4634                         x86_prefix (code, X86_FS_PREFIX);
4635                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4636                 } else {
4637                         /* Restore previous lmf */
4638                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4639                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4640                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4641                 }
4642
4643                 /* Restore caller saved regs */
4644                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4645                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), 8);
4646                 }
4647                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4648                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4649                 }
4650                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4651                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4652                 }
4653                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4654                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4655                 }
4656                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4657                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4658                 }
4659                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4660                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4661                 }
4662         } else {
4663
4664                 if (cfg->arch.omit_fp) {
4665                         gint32 save_area_offset = 0;
4666
4667                         for (i = 0; i < AMD64_NREG; ++i)
4668                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4669                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4670                                         save_area_offset += 8;
4671                                 }
4672                 }
4673                 else {
4674                         for (i = 0; i < AMD64_NREG; ++i)
4675                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4676                                         pos -= sizeof (gpointer);
4677
4678                         if (pos) {
4679                                 if (pos == - sizeof (gpointer)) {
4680                                         /* Only one register, so avoid lea */
4681                                         for (i = AMD64_NREG - 1; i > 0; --i)
4682                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4683                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4684                                                 }
4685                                 }
4686                                 else {
4687                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4688
4689                                         /* Pop registers in reverse order */
4690                                         for (i = AMD64_NREG - 1; i > 0; --i)
4691                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4692                                                         amd64_pop_reg (code, i);
4693                                                 }
4694                                 }
4695                         }
4696                 }
4697         }
4698
4699         /* Load returned vtypes into registers if needed */
4700         cinfo = cfg->arch.cinfo;
4701         if (cinfo->ret.storage == ArgValuetypeInReg) {
4702                 ArgInfo *ainfo = &cinfo->ret;
4703                 MonoInst *inst = cfg->ret;
4704
4705                 for (quad = 0; quad < 2; quad ++) {
4706                         switch (ainfo->pair_storage [quad]) {
4707                         case ArgInIReg:
4708                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
4709                                 break;
4710                         case ArgInFloatSSEReg:
4711                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4712                                 break;
4713                         case ArgInDoubleSSEReg:
4714                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4715                                 break;
4716                         case ArgNone:
4717                                 break;
4718                         default:
4719                                 g_assert_not_reached ();
4720                         }
4721                 }
4722         }
4723
4724         if (cfg->arch.omit_fp) {
4725                 if (cfg->arch.stack_alloc_size)
4726                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4727         } else {
4728                 amd64_leave (code);
4729         }
4730         amd64_ret (code);
4731
4732         cfg->code_len = code - cfg->native_code;
4733
4734         g_assert (cfg->code_len < cfg->code_size);
4735
4736         if (cfg->arch.omit_fp) {
4737                 /*
4738                  * Encode the stack size into used_int_regs so the exception handler
4739                  * can access it.
4740                  */
4741                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
4742                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
4743         }
4744 }
4745
4746 void
4747 mono_arch_emit_exceptions (MonoCompile *cfg)
4748 {
4749         MonoJumpInfo *patch_info;
4750         int nthrows, i;
4751         guint8 *code;
4752         MonoClass *exc_classes [16];
4753         guint8 *exc_throw_start [16], *exc_throw_end [16];
4754         guint32 code_size = 0;
4755
4756         /* Compute needed space */
4757         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4758                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4759                         code_size += 40;
4760                 if (patch_info->type == MONO_PATCH_INFO_R8)
4761                         code_size += 8 + 15; /* sizeof (double) + alignment */
4762                 if (patch_info->type == MONO_PATCH_INFO_R4)
4763                         code_size += 4 + 15; /* sizeof (float) + alignment */
4764         }
4765
4766         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4767                 cfg->code_size *= 2;
4768                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4769                 mono_jit_stats.code_reallocs++;
4770         }
4771
4772         code = cfg->native_code + cfg->code_len;
4773
4774         /* add code to raise exceptions */
4775         nthrows = 0;
4776         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4777                 switch (patch_info->type) {
4778                 case MONO_PATCH_INFO_EXC: {
4779                         MonoClass *exc_class;
4780                         guint8 *buf, *buf2;
4781                         guint32 throw_ip;
4782
4783                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
4784
4785                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4786                         g_assert (exc_class);
4787                         throw_ip = patch_info->ip.i;
4788
4789                         //x86_breakpoint (code);
4790                         /* Find a throw sequence for the same exception class */
4791                         for (i = 0; i < nthrows; ++i)
4792                                 if (exc_classes [i] == exc_class)
4793                                         break;
4794                         if (i < nthrows) {
4795                                 amd64_mov_reg_imm (code, AMD64_RSI, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4796                                 x86_jump_code (code, exc_throw_start [i]);
4797                                 patch_info->type = MONO_PATCH_INFO_NONE;
4798                         }
4799                         else {
4800                                 buf = code;
4801                                 amd64_mov_reg_imm_size (code, AMD64_RSI, 0xf0f0f0f0, 4);
4802                                 buf2 = code;
4803
4804                                 if (nthrows < 16) {
4805                                         exc_classes [nthrows] = exc_class;
4806                                         exc_throw_start [nthrows] = code;
4807                                 }
4808
4809                                 amd64_mov_reg_imm (code, AMD64_RDI, exc_class->type_token);
4810                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4811                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4812                                 patch_info->ip.i = code - cfg->native_code;
4813
4814                                 code = emit_call_body (cfg, code, patch_info->type, patch_info->data.name);
4815
4816                                 amd64_mov_reg_imm (buf, AMD64_RSI, (code - cfg->native_code) - throw_ip);
4817                                 while (buf < buf2)
4818                                         x86_nop (buf);
4819
4820                                 if (nthrows < 16) {
4821                                         exc_throw_end [nthrows] = code;
4822                                         nthrows ++;
4823                                 }
4824                         }
4825                         break;
4826                 }
4827                 default:
4828                         /* do nothing */
4829                         break;
4830                 }
4831         }
4832
4833         /* Handle relocations with RIP relative addressing */
4834         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4835                 gboolean remove = FALSE;
4836
4837                 switch (patch_info->type) {
4838                 case MONO_PATCH_INFO_R8:
4839                 case MONO_PATCH_INFO_R4: {
4840                         guint8 *pos;
4841
4842                         if (use_sse2) {
4843                                 /* The SSE opcodes require a 16 byte alignment */
4844                                 code = (guint8*)ALIGN_TO (code, 16);
4845                         } else {
4846                                 code = (guint8*)ALIGN_TO (code, 8);
4847                         }
4848
4849                         pos = cfg->native_code + patch_info->ip.i;
4850
4851
4852                         if (use_sse2) {
4853                                 if (IS_REX (pos [1]))
4854                                         *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
4855                                 else
4856                                         *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4857                         } else {
4858                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4859                         }
4860
4861                         if (patch_info->type == MONO_PATCH_INFO_R8) {
4862                                 *(double*)code = *(double*)patch_info->data.target;
4863                                 code += sizeof (double);
4864                         } else {
4865                                 *(float*)code = *(float*)patch_info->data.target;
4866                                 code += sizeof (float);
4867                         }
4868
4869                         remove = TRUE;
4870                         break;
4871                 }
4872                 default:
4873                         break;
4874                 }
4875
4876                 if (remove) {
4877                         if (patch_info == cfg->patch_info)
4878                                 cfg->patch_info = patch_info->next;
4879                         else {
4880                                 MonoJumpInfo *tmp;
4881
4882                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
4883                                         ;
4884                                 tmp->next = patch_info->next;
4885                         }
4886                 }
4887         }
4888
4889         cfg->code_len = code - cfg->native_code;
4890
4891         g_assert (cfg->code_len < cfg->code_size);
4892
4893 }
4894
4895 void*
4896 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4897 {
4898         guchar *code = p;
4899         CallInfo *cinfo = NULL;
4900         MonoMethodSignature *sig;
4901         MonoInst *inst;
4902         int i, n, stack_area = 0;
4903
4904         /* Keep this in sync with mono_arch_get_argument_info */
4905
4906         if (enable_arguments) {
4907                 /* Allocate a new area on the stack and save arguments there */
4908                 sig = mono_method_signature (cfg->method);
4909
4910                 cinfo = get_call_info (cfg->mempool, sig, FALSE);
4911
4912                 n = sig->param_count + sig->hasthis;
4913
4914                 stack_area = ALIGN_TO (n * 8, 16);
4915
4916                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
4917
4918                 for (i = 0; i < n; ++i) {
4919                         inst = cfg->args [i];
4920
4921                         if (inst->opcode == OP_REGVAR)
4922                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
4923                         else {
4924                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
4925                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
4926                         }
4927                 }
4928         }
4929
4930         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4931         amd64_set_reg_template (code, AMD64_RDI);
4932         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RSP, 8);
4933         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4934
4935         if (enable_arguments)
4936                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
4937
4938         return code;
4939 }
4940
4941 enum {
4942         SAVE_NONE,
4943         SAVE_STRUCT,
4944         SAVE_EAX,
4945         SAVE_EAX_EDX,
4946         SAVE_XMM
4947 };
4948
4949 void*
4950 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4951 {
4952         guchar *code = p;
4953         int save_mode = SAVE_NONE;
4954         MonoMethod *method = cfg->method;
4955         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
4956
4957         switch (rtype) {
4958         case MONO_TYPE_VOID:
4959                 /* special case string .ctor icall */
4960                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4961                         save_mode = SAVE_EAX;
4962                 else
4963                         save_mode = SAVE_NONE;
4964                 break;
4965         case MONO_TYPE_I8:
4966         case MONO_TYPE_U8:
4967                 save_mode = SAVE_EAX;
4968                 break;
4969         case MONO_TYPE_R4:
4970         case MONO_TYPE_R8:
4971                 save_mode = SAVE_XMM;
4972                 break;
4973         case MONO_TYPE_GENERICINST:
4974                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
4975                         save_mode = SAVE_EAX;
4976                         break;
4977                 }
4978                 /* Fall through */
4979         case MONO_TYPE_VALUETYPE:
4980                 save_mode = SAVE_STRUCT;
4981                 break;
4982         default:
4983                 save_mode = SAVE_EAX;
4984                 break;
4985         }
4986
4987         /* Save the result and copy it into the proper argument register */
4988         switch (save_mode) {
4989         case SAVE_EAX:
4990                 amd64_push_reg (code, AMD64_RAX);
4991                 /* Align stack */
4992                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4993                 if (enable_arguments)
4994                         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RAX, 8);
4995                 break;
4996         case SAVE_STRUCT:
4997                 /* FIXME: */
4998                 if (enable_arguments)
4999                         amd64_mov_reg_imm (code, AMD64_RSI, 0);
5000                 break;
5001         case SAVE_XMM:
5002                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5003                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5004                 /* Align stack */
5005                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5006                 /*
5007                  * The result is already in the proper argument register so no copying
5008                  * needed.
5009                  */
5010                 break;
5011         case SAVE_NONE:
5012                 break;
5013         default:
5014                 g_assert_not_reached ();
5015         }
5016
5017         /* Set %al since this is a varargs call */
5018         if (save_mode == SAVE_XMM)
5019                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5020         else
5021                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5022
5023         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5024         amd64_set_reg_template (code, AMD64_RDI);
5025         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
5026
5027         /* Restore result */
5028         switch (save_mode) {
5029         case SAVE_EAX:
5030                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5031                 amd64_pop_reg (code, AMD64_RAX);
5032                 break;
5033         case SAVE_STRUCT:
5034                 /* FIXME: */
5035                 break;
5036         case SAVE_XMM:
5037                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5038                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5039                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5040                 break;
5041         case SAVE_NONE:
5042                 break;
5043         default:
5044                 g_assert_not_reached ();
5045         }
5046
5047         return code;
5048 }
5049
5050 void
5051 mono_arch_flush_icache (guint8 *code, gint size)
5052 {
5053         /* Not needed */
5054 }
5055
5056 void
5057 mono_arch_flush_register_windows (void)
5058 {
5059 }
5060
5061 gboolean
5062 mono_arch_is_inst_imm (gint64 imm)
5063 {
5064         return amd64_is_imm32 (imm);
5065 }
5066
5067 /*
5068  * Determine whenever the trap whose info is in SIGINFO is caused by
5069  * integer overflow.
5070  */
5071 gboolean
5072 mono_arch_is_int_overflow (void *sigctx, void *info)
5073 {
5074         MonoContext ctx;
5075         guint8* rip;
5076         int reg;
5077         gint64 value;
5078
5079         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5080
5081         rip = (guint8*)ctx.rip;
5082
5083         if (IS_REX (rip [0])) {
5084                 reg = amd64_rex_b (rip [0]);
5085                 rip ++;
5086         }
5087         else
5088                 reg = 0;
5089
5090         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5091                 /* idiv REG */
5092                 reg += x86_modrm_rm (rip [1]);
5093
5094                 switch (reg) {
5095                 case AMD64_RAX:
5096                         value = ctx.rax;
5097                         break;
5098                 case AMD64_RBX:
5099                         value = ctx.rbx;
5100                         break;
5101                 case AMD64_RCX:
5102                         value = ctx.rcx;
5103                         break;
5104                 case AMD64_RDX:
5105                         value = ctx.rdx;
5106                         break;
5107                 case AMD64_RBP:
5108                         value = ctx.rbp;
5109                         break;
5110                 case AMD64_RSP:
5111                         value = ctx.rsp;
5112                         break;
5113                 case AMD64_RSI:
5114                         value = ctx.rsi;
5115                         break;
5116                 case AMD64_RDI:
5117                         value = ctx.rdi;
5118                         break;
5119                 case AMD64_R12:
5120                         value = ctx.r12;
5121                         break;
5122                 case AMD64_R13:
5123                         value = ctx.r13;
5124                         break;
5125                 case AMD64_R14:
5126                         value = ctx.r14;
5127                         break;
5128                 case AMD64_R15:
5129                         value = ctx.r15;
5130                         break;
5131                 default:
5132                         g_assert_not_reached ();
5133                         reg = -1;
5134                 }
5135
5136                 if (value == -1)
5137                         return TRUE;
5138         }
5139
5140         return FALSE;
5141 }
5142
5143 guint32
5144 mono_arch_get_patch_offset (guint8 *code)
5145 {
5146         return 3;
5147 }
5148
5149 gpointer*
5150 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5151 {
5152         guint32 reg;
5153         guint32 disp;
5154         guint8 rex = 0;
5155
5156         /* go to the start of the call instruction
5157          *
5158          * address_byte = (m << 6) | (o << 3) | reg
5159          * call opcode: 0xff address_byte displacement
5160          * 0xff m=1,o=2 imm8
5161          * 0xff m=2,o=2 imm32
5162          */
5163         code -= 7;
5164
5165         /*
5166          * A given byte sequence can match more than case here, so we have to be
5167          * really careful about the ordering of the cases. Longer sequences
5168          * come first.
5169          */
5170         if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5171                         /*
5172                          * This is a interface call
5173                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5174                          * ff 10                  callq  *(%rax)
5175                          */
5176                 if (IS_REX (code [4]))
5177                         rex = code [4];
5178                 reg = amd64_modrm_rm (code [6]);
5179                 disp = 0;
5180         }
5181         else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5182                 /* call OFFSET(%rip) */
5183                 disp = *(guint32*)(code + 3);
5184                 return (gpointer*)(code + disp + 7);
5185         }
5186         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5187                 /* call *[reg+disp32] */
5188                 if (IS_REX (code [0]))
5189                         rex = code [0];
5190                 reg = amd64_modrm_rm (code [2]);
5191                 disp = *(guint32*)(code + 3);
5192                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5193         }
5194         else if (code [2] == 0xe8) {
5195                 /* call <ADDR> */
5196                 return NULL;
5197         }
5198         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5199                 /* call *%reg */
5200                 return NULL;
5201         }
5202         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5203                 /* call *[reg+disp8] */
5204                 if (IS_REX (code [3]))
5205                         rex = code [3];
5206                 reg = amd64_modrm_rm (code [5]);
5207                 disp = *(guint8*)(code + 6);
5208                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5209         }
5210         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5211                         /*
5212                          * This is a interface call: should check the above code can't catch it earlier
5213                          * 8b 40 30   mov    0x30(%eax),%eax
5214                          * ff 10      call   *(%eax)
5215                          */
5216                 if (IS_REX (code [4]))
5217                         rex = code [4];
5218                 reg = amd64_modrm_rm (code [6]);
5219                 disp = 0;
5220         }
5221         else
5222                 g_assert_not_reached ();
5223
5224         reg += amd64_rex_b (rex);
5225
5226         /* R11 is clobbered by the trampoline code */
5227         g_assert (reg != AMD64_R11);
5228
5229         return (gpointer)(((guint64)(regs [reg])) + disp);
5230 }
5231
5232 gpointer
5233 mono_arch_get_this_arg_from_call (MonoMethodSignature *sig, gssize *regs, guint8 *code)
5234 {
5235         if (MONO_TYPE_ISSTRUCT (sig->ret))
5236                 return (gpointer)regs [AMD64_RSI];
5237         else
5238                 return (gpointer)regs [AMD64_RDI];
5239 }
5240
5241 gpointer
5242 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5243 {
5244         guint8 *code, *start;
5245         MonoDomain *domain = mono_domain_get ();
5246         int i;
5247
5248         /* FIXME: Support more cases */
5249         if (MONO_TYPE_ISSTRUCT (sig->ret))
5250                 return NULL;
5251
5252         if (has_target) {
5253                 mono_domain_lock (domain);
5254                 start = code = mono_code_manager_reserve (domain->code_mp, 64);
5255                 mono_domain_unlock (domain);
5256
5257                 /* Replace the this argument with the target */
5258                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RDI, 8);
5259                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5260                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5261
5262                 g_assert ((code - start) < 64);
5263         } else {
5264                 for (i = 0; i < sig->param_count; ++i)
5265                         if (!mono_is_regsize_var (sig->params [i]))
5266                                 return NULL;
5267                 if (sig->param_count > 4)
5268                         return NULL;
5269
5270                 mono_domain_lock (domain);
5271                 start = code = mono_code_manager_reserve (domain->code_mp, 64);
5272                 mono_domain_unlock (domain);
5273
5274                 if (sig->param_count == 0) {
5275                         amd64_jump_membase (code, AMD64_RDI, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5276                 } else {
5277                         /* We have to shift the arguments left */
5278                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RDI, 8);
5279                         for (i = 0; i < sig->param_count; ++i)
5280                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5281
5282                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5283                 }
5284                 g_assert ((code - start) < 64);
5285         }
5286
5287         return start;
5288 }
5289
5290 /*
5291  * Support for fast access to the thread-local lmf structure using the GS
5292  * segment register on NPTL + kernel 2.6.x.
5293  */
5294
5295 static gboolean tls_offset_inited = FALSE;
5296
5297 void
5298 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5299 {
5300         if (!tls_offset_inited) {
5301                 tls_offset_inited = TRUE;
5302 #ifdef MONO_XEN_OPT
5303                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5304 #endif
5305                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5306                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5307                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5308                 thread_tls_offset = mono_thread_get_tls_offset ();
5309         }
5310 }
5311
5312 void
5313 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5314 {
5315 }
5316
5317 void
5318 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
5319 {
5320         MonoCallInst *call = (MonoCallInst*)inst;
5321         CallInfo * cinfo = get_call_info (cfg->mempool, inst->signature, FALSE);
5322
5323         if (vt_reg != -1) {
5324                 MonoInst *vtarg;
5325
5326                 if (cinfo->ret.storage == ArgValuetypeInReg) {
5327                         /*
5328                          * The valuetype is in RAX:RDX after the call, need to be copied to
5329                          * the stack. Push the address here, so the call instruction can
5330                          * access it.
5331                          */
5332                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
5333                         vtarg->sreg1 = vt_reg;
5334                         mono_bblock_add_inst (cfg->cbb, vtarg);
5335
5336                         /* Align stack */
5337                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
5338                 }
5339                 else {
5340                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
5341                         vtarg->sreg1 = vt_reg;
5342                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
5343                         mono_bblock_add_inst (cfg->cbb, vtarg);
5344
5345                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
5346                 }
5347         }
5348
5349         /* add the this argument */
5350         if (this_reg != -1) {
5351                 MonoInst *this;
5352                 MONO_INST_NEW (cfg, this, OP_MOVE);
5353                 this->type = this_type;
5354                 this->sreg1 = this_reg;
5355                 this->dreg = mono_regstate_next_int (cfg->rs);
5356                 mono_bblock_add_inst (cfg->cbb, this);
5357
5358                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
5359         }
5360 }
5361
5362 MonoInst*
5363 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5364 {
5365         MonoInst *ins = NULL;
5366
5367         if (cmethod->klass == mono_defaults.math_class) {
5368                 if (strcmp (cmethod->name, "Sin") == 0) {
5369                         MONO_INST_NEW (cfg, ins, OP_SIN);
5370                         ins->inst_i0 = args [0];
5371                 } else if (strcmp (cmethod->name, "Cos") == 0) {
5372                         MONO_INST_NEW (cfg, ins, OP_COS);
5373                         ins->inst_i0 = args [0];
5374                 } else if (strcmp (cmethod->name, "Tan") == 0) {
5375                         if (use_sse2)
5376                                 return ins;
5377                         MONO_INST_NEW (cfg, ins, OP_TAN);
5378                         ins->inst_i0 = args [0];
5379                 } else if (strcmp (cmethod->name, "Atan") == 0) {
5380                         if (use_sse2)
5381                                 return ins;
5382                         MONO_INST_NEW (cfg, ins, OP_ATAN);
5383                         ins->inst_i0 = args [0];
5384                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5385                         MONO_INST_NEW (cfg, ins, OP_SQRT);
5386                         ins->inst_i0 = args [0];
5387                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5388                         MONO_INST_NEW (cfg, ins, OP_ABS);
5389                         ins->inst_i0 = args [0];
5390                 }
5391 #if 0
5392                 /* OP_FREM is not IEEE compatible */
5393                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5394                         MONO_INST_NEW (cfg, ins, OP_FREM);
5395                         ins->inst_i0 = args [0];
5396                         ins->inst_i1 = args [1];
5397                 }
5398 #endif
5399         } else if (cmethod->klass == mono_defaults.thread_class &&
5400                            strcmp (cmethod->name, "MemoryBarrier") == 0) {
5401                 MONO_INST_NEW (cfg, ins, OP_MEMORY_BARRIER);
5402         } else if(cmethod->klass->image == mono_defaults.corlib &&
5403                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
5404                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
5405
5406                 if (strcmp (cmethod->name, "Increment") == 0) {
5407                         MonoInst *ins_iconst;
5408                         guint32 opcode;
5409
5410                         if (fsig->params [0]->type == MONO_TYPE_I4)
5411                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5412                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5413                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5414                         else
5415                                 g_assert_not_reached ();
5416                         MONO_INST_NEW (cfg, ins, opcode);
5417                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5418                         ins_iconst->inst_c0 = 1;
5419
5420                         ins->inst_i0 = args [0];
5421                         ins->inst_i1 = ins_iconst;
5422                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
5423                         MonoInst *ins_iconst;
5424                         guint32 opcode;
5425
5426                         if (fsig->params [0]->type == MONO_TYPE_I4)
5427                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5428                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5429                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5430                         else
5431                                 g_assert_not_reached ();
5432                         MONO_INST_NEW (cfg, ins, opcode);
5433                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5434                         ins_iconst->inst_c0 = -1;
5435
5436                         ins->inst_i0 = args [0];
5437                         ins->inst_i1 = ins_iconst;
5438                 } else if (strcmp (cmethod->name, "Add") == 0) {
5439                         guint32 opcode;
5440
5441                         if (fsig->params [0]->type == MONO_TYPE_I4)
5442                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5443                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5444                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5445                         else
5446                                 g_assert_not_reached ();
5447
5448                         MONO_INST_NEW (cfg, ins, opcode);
5449
5450                         ins->inst_i0 = args [0];
5451                         ins->inst_i1 = args [1];
5452                 } else if (strcmp (cmethod->name, "Exchange") == 0) {
5453                         guint32 opcode;
5454
5455                         if (fsig->params [0]->type == MONO_TYPE_I4)
5456                                 opcode = OP_ATOMIC_EXCHANGE_I4;
5457                         else if ((fsig->params [0]->type == MONO_TYPE_I8) ||
5458                                          (fsig->params [0]->type == MONO_TYPE_I) ||
5459                                          (fsig->params [0]->type == MONO_TYPE_OBJECT))
5460                                 opcode = OP_ATOMIC_EXCHANGE_I8;
5461                         else
5462                                 return NULL;
5463
5464                         MONO_INST_NEW (cfg, ins, opcode);
5465
5466                         ins->inst_i0 = args [0];
5467                         ins->inst_i1 = args [1];
5468                 } else if (strcmp (cmethod->name, "Read") == 0 && (fsig->params [0]->type == MONO_TYPE_I8)) {
5469                         /* 64 bit reads are already atomic */
5470                         MONO_INST_NEW (cfg, ins, CEE_LDIND_I8);
5471                         ins->inst_i0 = args [0];
5472                 }
5473
5474                 /*
5475                  * Can't implement CompareExchange methods this way since they have
5476                  * three arguments.
5477                  */
5478         }
5479
5480         return ins;
5481 }
5482
5483 gboolean
5484 mono_arch_print_tree (MonoInst *tree, int arity)
5485 {
5486         return 0;
5487 }
5488
5489 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5490 {
5491         MonoInst* ins;
5492
5493         if (appdomain_tls_offset == -1)
5494                 return NULL;
5495
5496         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5497         ins->inst_offset = appdomain_tls_offset;
5498         return ins;
5499 }
5500
5501 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5502 {
5503         MonoInst* ins;
5504
5505         if (thread_tls_offset == -1)
5506                 return NULL;
5507
5508         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5509         ins->inst_offset = thread_tls_offset;
5510         return ins;
5511 }