mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 /* Offset between fp and the first argument in the callee */
  89 #define ARGS_OFFSET 16
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return mono_debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 #ifdef __native_client_codegen__
 182
 183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 184 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 186 /* We only want to force bundle alignment for the top level instruction,    */
 187 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 188 static MonoNativeTlsKey nacl_instruction_depth;
 189
 190 static MonoNativeTlsKey nacl_rex_tag;
 191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 192
 193 void
 194 amd64_nacl_clear_legacy_prefix_tag ()
 195 {
 196         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 197 }
 198
 199 void
 200 amd64_nacl_tag_legacy_prefix (guint8* code)
 201 {
 202         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 203                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 204 }
 205
 206 void
 207 amd64_nacl_tag_rex (guint8* code)
 208 {
 209         mono_native_tls_set_value (nacl_rex_tag, code);
 210 }
 211
 212 guint8*
 213 amd64_nacl_get_legacy_prefix_tag ()
 214 {
 215         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 216 }
 217
 218 guint8*
 219 amd64_nacl_get_rex_tag ()
 220 {
 221         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 222 }
 223
 224 /* Increment the instruction "depth" described above */
 225 void
 226 amd64_nacl_instruction_pre ()
 227 {
 228         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 229         depth++;
 230         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 231 }
 232
 233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 234 /* alignment if depth == 0 (top level instruction)                          */
 235 /* IN: start, end    pointers to instruction beginning and end              */
 236 /* OUT: start, end   pointers to beginning and end after possible alignment */
 237 /* GLOBALS: nacl_instruction_depth     defined above                        */
 238 void
 239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth--;
 243         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 244
 245         g_assert ( depth >= 0 );
 246         if (depth == 0) {
 247                 uintptr_t space_in_block;
 248                 uintptr_t instlen;
 249                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 250                 /* if legacy prefix is present, and if it was emitted before */
 251                 /* the start of the instruction sequence, adjust the start   */
 252                 if (prefix != NULL && prefix < *start) {
 253                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 254                         *start = prefix;
 255                 }
 256                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 257                 instlen = (uintptr_t)(*end - *start);
 258                 /* Only check for instructions which are less than        */
 259                 /* kNaClAlignment. The only instructions that should ever */
 260                 /* be that long are call sequences, which are already     */
 261                 /* padded out to align the return to the next bundle.     */
 262                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 263                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 264                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 265                         const size_t length = (size_t)((*end)-(*start));
 266                         g_assert (length < MAX_NACL_INST_LENGTH);
 267
 268                         memcpy (copy_of_instruction, *start, length);
 269                         *start = mono_arch_nacl_pad (*start, space_in_block);
 270                         memcpy (*start, copy_of_instruction, length);
 271                         *end = *start + length;
 272                 }
 273                 amd64_nacl_clear_legacy_prefix_tag ();
 274                 amd64_nacl_tag_rex (NULL);
 275         }
 276 }
 277
 278 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 279 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 280 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 281 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 282 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 283 /* IN:      code                                                            */
 284 /*             pointer to current instruction stream (in the                */
 285 /*             middle of an instruction, after opcode is emitted)           */
 286 /*          basereg/offset/dreg                                             */
 287 /*             operands of normal membase address                           */
 288 /* OUT:     code                                                            */
 289 /*             pointer to the end of the membase/memindex emit              */
 290 /* GLOBALS: nacl_rex_tag                                                    */
 291 /*             position in instruction stream that rex prefix was emitted   */
 292 /*          nacl_legacy_prefix_tag                                          */
 293 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 294 void
 295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 296 {
 297         gint8 true_basereg = basereg;
 298
 299         /* Cache these values, they might change  */
 300         /* as new instructions are emitted below. */
 301         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 302         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 303
 304         /* 'basereg' is given masked to 0x7 at this point, so check */
 305         /* the rex prefix to see if this is an extended register.   */
 306         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 307                 true_basereg |= 0x8;
 308         }
 309
 310 #define X86_LEA_OPCODE (0x8D)
 311
 312         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 313                 guint8* old_instruction_start;
 314
 315                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 316                 /* 32-bits of the old base register (new index register)     */
 317                 guint8 buf[32];
 318                 guint8* buf_ptr = buf;
 319                 size_t insert_len;
 320
 321                 g_assert (rex_tag != NULL);
 322
 323                 if (IS_REX(*rex_tag)) {
 324                         /* The old rex.B should be the new rex.X */
 325                         if (*rex_tag & AMD64_REX_B) {
 326                                 *rex_tag |= AMD64_REX_X;
 327                         }
 328                         /* Since our new base is %r15 set rex.B */
 329                         *rex_tag |= AMD64_REX_B;
 330                 } else {
 331                         /* Shift the instruction by one byte  */
 332                         /* so we can insert a rex prefix      */
 333                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 334                         *code += 1;
 335                         /* New rex prefix only needs rex.B for %r15 base */
 336                         *rex_tag = AMD64_REX(AMD64_REX_B);
 337                 }
 338
 339                 if (legacy_prefix_tag) {
 340                         old_instruction_start = legacy_prefix_tag;
 341                 } else {
 342                         old_instruction_start = rex_tag;
 343                 }
 344
 345                 /* Clears the upper 32-bits of the previous base register */
 346                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 347                 insert_len = buf_ptr - buf;
 348
 349                 /* Move the old instruction forward to make */
 350                 /* room for 'mov' stored in 'buf_ptr'       */
 351                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 352                 *code += insert_len;
 353                 memcpy (old_instruction_start, buf, insert_len);
 354
 355                 /* Sandboxed replacement for the normal membase_emit */
 356                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 357
 358         } else {
 359                 /* Normal default behavior, emit membase memory location */
 360                 x86_membase_emit_body (*code, dreg, basereg, offset);
 361         }
 362 }
 363
 364
 365 static inline unsigned char*
 366 amd64_skip_nops (unsigned char* code)
 367 {
 368         guint8 in_nop;
 369         do {
 370                 in_nop = 0;
 371                 if (   code[0] == 0x90) {
 372                         in_nop = 1;
 373                         code += 1;
 374                 }
 375                 if (   code[0] == 0x66 && code[1] == 0x90) {
 376                         in_nop = 1;
 377                         code += 2;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x00) {
 381                         in_nop = 1;
 382                         code += 3;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x40 && code[3] == 0x00) {
 386                         in_nop = 1;
 387                         code += 4;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x44 && code[3] == 0x00
 391                  && code[4] == 0x00) {
 392                         in_nop = 1;
 393                         code += 5;
 394                 }
 395                 if (code[0] == 0x66 && code[1] == 0x0f
 396                  && code[2] == 0x1f && code[3] == 0x44
 397                  && code[4] == 0x00 && code[5] == 0x00) {
 398                         in_nop = 1;
 399                         code += 6;
 400                 }
 401                 if (code[0] == 0x0f && code[1] == 0x1f
 402                  && code[2] == 0x80 && code[3] == 0x00
 403                  && code[4] == 0x00 && code[5] == 0x00
 404                  && code[6] == 0x00) {
 405                         in_nop = 1;
 406                         code += 7;
 407                 }
 408                 if (code[0] == 0x0f && code[1] == 0x1f
 409                  && code[2] == 0x84 && code[3] == 0x00
 410                  && code[4] == 0x00 && code[5] == 0x00
 411                  && code[6] == 0x00 && code[7] == 0x00) {
 412                         in_nop = 1;
 413                         code += 8;
 414                 }
 415         } while ( in_nop );
 416         return code;
 417 }
 418
 419 guint8*
 420 mono_arch_nacl_skip_nops (guint8* code)
 421 {
 422   return amd64_skip_nops(code);
 423 }
 424
 425 #endif /*__native_client_codegen__*/
 426
 427 static inline void
 428 amd64_patch (unsigned char* code, gpointer target)
 429 {
 430         guint8 rex = 0;
 431
 432 #ifdef __native_client_codegen__
 433         code = amd64_skip_nops (code);
 434 #endif
 435 #if defined(__native_client_codegen__) && defined(__native_client__)
 436         if (nacl_is_code_address (code)) {
 437                 /* For tail calls, code is patched after being installed */
 438                 /* but not through the normal "patch callsite" method.   */
 439                 unsigned char buf[kNaClAlignment];
 440                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 441                 int ret;
 442                 memcpy (buf, aligned_code, kNaClAlignment);
 443                 /* Patch a temp buffer of bundle size, */
 444                 /* then install to actual location.    */
 445                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 446                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 447                 g_assert (ret == 0);
 448                 return;
 449         }
 450         target = nacl_modify_patch_target (target);
 451 #endif
 452
 453         /* Skip REX */
 454         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 455                 rex = code [0];
 456                 code += 1;
 457         }
 458
 459         if ((code [0] & 0xf8) == 0xb8) {
 460                 /* amd64_set_reg_template */
 461                 *(guint64*)(code + 1) = (guint64)target;
 462         }
 463         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 464                 /* mov 0(%rip), %dreg */
 465                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 466         }
 467         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 468                 /* call *<OFFSET>(%rip) */
 469                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 470         }
 471         else if (code [0] == 0xe8) {
 472                 /* call <DISP> */
 473                 gint64 disp = (guint8*)target - (guint8*)code;
 474                 g_assert (amd64_is_imm32 (disp));
 475                 x86_patch (code, (unsigned char*)target);
 476         }
 477         else
 478                 x86_patch (code, (unsigned char*)target);
 479 }
 480
 481 void
 482 mono_amd64_patch (unsigned char* code, gpointer target)
 483 {
 484         amd64_patch (code, target);
 485 }
 486
 487 typedef enum {
 488         ArgInIReg,
 489         ArgInFloatSSEReg,
 490         ArgInDoubleSSEReg,
 491         ArgOnStack,
 492         ArgValuetypeInReg,
 493         ArgValuetypeAddrInIReg,
 494         ArgNone /* only in pair_storage */
 495 } ArgStorage;
 496
 497 typedef struct {
 498         gint16 offset;
 499         gint8  reg;
 500         ArgStorage storage;
 501
 502         /* Only if storage == ArgValuetypeInReg */
 503         ArgStorage pair_storage [2];
 504         gint8 pair_regs [2];
 505         int nregs;
 506 } ArgInfo;
 507
 508 typedef struct {
 509         int nargs;
 510         guint32 stack_usage;
 511         guint32 reg_usage;
 512         guint32 freg_usage;
 513         gboolean need_stack_align;
 514         gboolean vtype_retaddr;
 515         /* The index of the vret arg in the argument list */
 516         int vret_arg_index;
 517         ArgInfo ret;
 518         ArgInfo sig_cookie;
 519         ArgInfo args [1];
 520 } CallInfo;
 521
 522 #define DEBUG(a) if (cfg->verbose_level > 1) a
 523
 524 #ifdef HOST_WIN32
 525 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 526
 527 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 528 #else
 529 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 530
 531  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 532 #endif
 533
 534 static void inline
 535 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 536 {
 537     ainfo->offset = *stack_size;
 538
 539     if (*gr >= PARAM_REGS) {
 540                 ainfo->storage = ArgOnStack;
 541                 /* Since the same stack slot size is used for all arg */
 542                 /*  types, it needs to be big enough to hold them all */
 543                 (*stack_size) += sizeof(mgreg_t);
 544     }
 545     else {
 546                 ainfo->storage = ArgInIReg;
 547                 ainfo->reg = param_regs [*gr];
 548                 (*gr) ++;
 549     }
 550 }
 551
 552 #ifdef HOST_WIN32
 553 #define FLOAT_PARAM_REGS 4
 554 #else
 555 #define FLOAT_PARAM_REGS 8
 556 #endif
 557
 558 static void inline
 559 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 560 {
 561     ainfo->offset = *stack_size;
 562
 563     if (*gr >= FLOAT_PARAM_REGS) {
 564                 ainfo->storage = ArgOnStack;
 565                 /* Since the same stack slot size is used for both float */
 566                 /*  types, it needs to be big enough to hold them both */
 567                 (*stack_size) += sizeof(mgreg_t);
 568     }
 569     else {
 570                 /* A double register */
 571                 if (is_double)
 572                         ainfo->storage = ArgInDoubleSSEReg;
 573                 else
 574                         ainfo->storage = ArgInFloatSSEReg;
 575                 ainfo->reg = *gr;
 576                 (*gr) += 1;
 577     }
 578 }
 579
 580 typedef enum ArgumentClass {
 581         ARG_CLASS_NO_CLASS,
 582         ARG_CLASS_MEMORY,
 583         ARG_CLASS_INTEGER,
 584         ARG_CLASS_SSE
 585 } ArgumentClass;
 586
 587 static ArgumentClass
 588 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 589 {
 590         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 591         MonoType *ptype;
 592
 593         ptype = mini_type_get_underlying_type (gsctx, type);
 594         switch (ptype->type) {
 595         case MONO_TYPE_BOOLEAN:
 596         case MONO_TYPE_CHAR:
 597         case MONO_TYPE_I1:
 598         case MONO_TYPE_U1:
 599         case MONO_TYPE_I2:
 600         case MONO_TYPE_U2:
 601         case MONO_TYPE_I4:
 602         case MONO_TYPE_U4:
 603         case MONO_TYPE_I:
 604         case MONO_TYPE_U:
 605         case MONO_TYPE_STRING:
 606         case MONO_TYPE_OBJECT:
 607         case MONO_TYPE_CLASS:
 608         case MONO_TYPE_SZARRAY:
 609         case MONO_TYPE_PTR:
 610         case MONO_TYPE_FNPTR:
 611         case MONO_TYPE_ARRAY:
 612         case MONO_TYPE_I8:
 613         case MONO_TYPE_U8:
 614                 class2 = ARG_CLASS_INTEGER;
 615                 break;
 616         case MONO_TYPE_R4:
 617         case MONO_TYPE_R8:
 618 #ifdef HOST_WIN32
 619                 class2 = ARG_CLASS_INTEGER;
 620 #else
 621                 class2 = ARG_CLASS_SSE;
 622 #endif
 623                 break;
 624
 625         case MONO_TYPE_TYPEDBYREF:
 626                 g_assert_not_reached ();
 627
 628         case MONO_TYPE_GENERICINST:
 629                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 630                         class2 = ARG_CLASS_INTEGER;
 631                         break;
 632                 }
 633                 /* fall through */
 634         case MONO_TYPE_VALUETYPE: {
 635                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 636                 int i;
 637
 638                 for (i = 0; i < info->num_fields; ++i) {
 639                         class2 = class1;
 640                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 641                 }
 642                 break;
 643         }
 644         default:
 645                 g_assert_not_reached ();
 646         }
 647
 648         /* Merge */
 649         if (class1 == class2)
 650                 ;
 651         else if (class1 == ARG_CLASS_NO_CLASS)
 652                 class1 = class2;
 653         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 654                 class1 = ARG_CLASS_MEMORY;
 655         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 656                 class1 = ARG_CLASS_INTEGER;
 657         else
 658                 class1 = ARG_CLASS_SSE;
 659
 660         return class1;
 661 }
 662 #ifdef __native_client_codegen__
 663
 664 /* Default alignment for Native Client is 32-byte. */
 665 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 666
 667 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 668 /* Check that alignment doesn't cross an alignment boundary.             */
 669 guint8*
 670 mono_arch_nacl_pad(guint8 *code, int pad)
 671 {
 672         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 673
 674         if (pad == 0) return code;
 675         /* assertion: alignment cannot cross a block boundary */
 676         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 677                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 678         while (pad >= kMaxPadding) {
 679                 amd64_padding (code, kMaxPadding);
 680                 pad -= kMaxPadding;
 681         }
 682         if (pad != 0) amd64_padding (code, pad);
 683         return code;
 684 }
 685 #endif
 686
 687 static int
 688 count_fields_nested (MonoClass *klass)
 689 {
 690         MonoMarshalType *info;
 691         guint32 align;
 692         int i, count;
 693
 694         info = mono_marshal_load_type_info (klass);
 695         g_assert(info);
 696         count = 0;
 697         for (i = 0; i < info->num_fields; ++i) {
 698                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 699                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 700                 else
 701                         count ++;
 702         }
 703         return count;
 704 }
 705
 706 static int
 707 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 708 {
 709         MonoMarshalType *info;
 710         guint32 align;
 711         int i;
 712
 713         info = mono_marshal_load_type_info (klass);
 714         g_assert(info);
 715         for (i = 0; i < info->num_fields; ++i) {
 716                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 717                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 718                 } else {
 719                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 720                         fields [index].offset += offset;
 721                         index ++;
 722                 }
 723         }
 724         return index;
 725 }
 726
 727 static void
 728 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 729                            gboolean is_return,
 730                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 731 {
 732         guint32 size, quad, nquads, i, nfields;
 733         /* Keep track of the size used in each quad so we can */
 734         /* use the right size when copying args/return vars.  */
 735         guint32 quadsize [2] = {8, 8};
 736         ArgumentClass args [2];
 737         MonoMarshalType *info = NULL;
 738         MonoMarshalField *fields = NULL;
 739         MonoClass *klass;
 740         MonoGenericSharingContext tmp_gsctx;
 741         gboolean pass_on_stack = FALSE;
 742
 743         /*
 744          * The gsctx currently contains no data, it is only used for checking whenever
 745          * open types are allowed, some callers like mono_arch_get_argument_info ()
 746          * don't pass it to us, so work around that.
 747          */
 748         if (!gsctx)
 749                 gsctx = &tmp_gsctx;
 750
 751         klass = mono_class_from_mono_type (type);
 752         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 753 #ifndef HOST_WIN32
 754         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 755                 /* We pass and return vtypes of size 8 in a register */
 756         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 757                 pass_on_stack = TRUE;
 758         }
 759 #else
 760         if (!sig->pinvoke) {
 761                 pass_on_stack = TRUE;
 762         }
 763 #endif
 764
 765         /* If this struct can't be split up naturally into 8-byte */
 766         /* chunks (registers), pass it on the stack.              */
 767         if (sig->pinvoke && !pass_on_stack) {
 768                 guint32 align;
 769                 guint32 field_size;
 770
 771                 info = mono_marshal_load_type_info (klass);
 772                 g_assert (info);
 773
 774                 /*
 775                  * Collect field information recursively to be able to
 776                  * handle nested structures.
 777                  */
 778                 nfields = count_fields_nested (klass);
 779                 fields = g_new0 (MonoMarshalField, nfields);
 780                 collect_field_info_nested (klass, fields, 0, 0);
 781
 782                 for (i = 0; i < nfields; ++i) {
 783                         field_size = mono_marshal_type_size (fields [i].field->type,
 784                                                            fields [i].mspec,
 785                                                            &align, TRUE, klass->unicode);
 786                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 787                                 pass_on_stack = TRUE;
 788                                 break;
 789                         }
 790                 }
 791         }
 792
 793         if (pass_on_stack) {
 794                 /* Allways pass in memory */
 795                 ainfo->offset = *stack_size;
 796                 *stack_size += ALIGN_TO (size, 8);
 797                 ainfo->storage = ArgOnStack;
 798
 799                 g_free (fields);
 800                 return;
 801         }
 802
 803         /* FIXME: Handle structs smaller than 8 bytes */
 804         //if ((size % 8) != 0)
 805         //      NOT_IMPLEMENTED;
 806
 807         if (size > 8)
 808                 nquads = 2;
 809         else
 810                 nquads = 1;
 811
 812         if (!sig->pinvoke) {
 813                 /* Always pass in 1 or 2 integer registers */
 814                 args [0] = ARG_CLASS_INTEGER;
 815                 args [1] = ARG_CLASS_INTEGER;
 816                 /* Only the simplest cases are supported */
 817                 if (is_return && nquads != 1) {
 818                         args [0] = ARG_CLASS_MEMORY;
 819                         args [1] = ARG_CLASS_MEMORY;
 820                 }
 821         } else {
 822                 /*
 823                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 824                  * The X87 and SSEUP stuff is left out since there are no such types in
 825                  * the CLR.
 826                  */
 827                 g_assert (info);
 828                 g_assert (fields);
 829
 830 #ifndef HOST_WIN32
 831                 if (info->native_size > 16) {
 832                         ainfo->offset = *stack_size;
 833                         *stack_size += ALIGN_TO (info->native_size, 8);
 834                         ainfo->storage = ArgOnStack;
 835
 836                         g_free (fields);
 837                         return;
 838                 }
 839 #else
 840                 switch (info->native_size) {
 841                 case 1: case 2: case 4: case 8:
 842                         break;
 843                 default:
 844                         if (is_return) {
 845                                 ainfo->storage = ArgOnStack;
 846                                 ainfo->offset = *stack_size;
 847                                 *stack_size += ALIGN_TO (info->native_size, 8);
 848                         }
 849                         else {
 850                                 ainfo->storage = ArgValuetypeAddrInIReg;
 851
 852                                 if (*gr < PARAM_REGS) {
 853                                         ainfo->pair_storage [0] = ArgInIReg;
 854                                         ainfo->pair_regs [0] = param_regs [*gr];
 855                                         (*gr) ++;
 856                                 }
 857                                 else {
 858                                         ainfo->pair_storage [0] = ArgOnStack;
 859                                         ainfo->offset = *stack_size;
 860                                         *stack_size += 8;
 861                                 }
 862                         }
 863
 864                         g_free (fields);
 865                         return;
 866                 }
 867 #endif
 868
 869                 args [0] = ARG_CLASS_NO_CLASS;
 870                 args [1] = ARG_CLASS_NO_CLASS;
 871                 for (quad = 0; quad < nquads; ++quad) {
 872                         int size;
 873                         guint32 align;
 874                         ArgumentClass class1;
 875
 876                         if (nfields == 0)
 877                                 class1 = ARG_CLASS_MEMORY;
 878                         else
 879                                 class1 = ARG_CLASS_NO_CLASS;
 880                         for (i = 0; i < nfields; ++i) {
 881                                 size = mono_marshal_type_size (fields [i].field->type,
 882                                                                                            fields [i].mspec,
 883                                                                                            &align, TRUE, klass->unicode);
 884                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 885                                         /* Unaligned field */
 886                                         NOT_IMPLEMENTED;
 887                                 }
 888
 889                                 /* Skip fields in other quad */
 890                                 if ((quad == 0) && (fields [i].offset >= 8))
 891                                         continue;
 892                                 if ((quad == 1) && (fields [i].offset < 8))
 893                                         continue;
 894
 895                                 /* How far into this quad this data extends.*/
 896                                 /* (8 is size of quad) */
 897                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 898
 899                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 900                         }
 901                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 902                         args [quad] = class1;
 903                 }
 904         }
 905
 906         g_free (fields);
 907
 908         /* Post merger cleanup */
 909         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 910                 args [0] = args [1] = ARG_CLASS_MEMORY;
 911
 912         /* Allocate registers */
 913         {
 914                 int orig_gr = *gr;
 915                 int orig_fr = *fr;
 916
 917                 ainfo->storage = ArgValuetypeInReg;
 918                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 919                 ainfo->nregs = nquads;
 920                 for (quad = 0; quad < nquads; ++quad) {
 921                         switch (args [quad]) {
 922                         case ARG_CLASS_INTEGER:
 923                                 if (*gr >= PARAM_REGS)
 924                                         args [quad] = ARG_CLASS_MEMORY;
 925                                 else {
 926                                         ainfo->pair_storage [quad] = ArgInIReg;
 927                                         if (is_return)
 928                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 929                                         else
 930                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 931                                         (*gr) ++;
 932                                 }
 933                                 break;
 934                         case ARG_CLASS_SSE:
 935                                 if (*fr >= FLOAT_PARAM_REGS)
 936                                         args [quad] = ARG_CLASS_MEMORY;
 937                                 else {
 938                                         if (quadsize[quad] <= 4)
 939                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 940                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 941                                         ainfo->pair_regs [quad] = *fr;
 942                                         (*fr) ++;
 943                                 }
 944                                 break;
 945                         case ARG_CLASS_MEMORY:
 946                                 break;
 947                         default:
 948                                 g_assert_not_reached ();
 949                         }
 950                 }
 951
 952                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 953                         /* Revert possible register assignments */
 954                         *gr = orig_gr;
 955                         *fr = orig_fr;
 956
 957                         ainfo->offset = *stack_size;
 958                         if (sig->pinvoke)
 959                                 *stack_size += ALIGN_TO (info->native_size, 8);
 960                         else
 961                                 *stack_size += nquads * sizeof(mgreg_t);
 962                         ainfo->storage = ArgOnStack;
 963                 }
 964         }
 965 }
 966
 967 /*
 968  * get_call_info:
 969  *
 970  *  Obtain information about a call according to the calling convention.
 971  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 972  * Draft Version 0.23" document for more information.
 973  */
 974 static CallInfo*
 975 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 976 {
 977         guint32 i, gr, fr, pstart;
 978         MonoType *ret_type;
 979         int n = sig->hasthis + sig->param_count;
 980         guint32 stack_size = 0;
 981         CallInfo *cinfo;
 982         gboolean is_pinvoke = sig->pinvoke;
 983
 984         if (mp)
 985                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 986         else
 987                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 988
 989         cinfo->nargs = n;
 990
 991         gr = 0;
 992         fr = 0;
 993
 994 #ifdef HOST_WIN32
 995         /* Reserve space where the callee can save the argument registers */
 996         stack_size = 4 * sizeof (mgreg_t);
 997 #endif
 998
 999         /* return value */
1000         {
1001                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1002                 switch (ret_type->type) {
1003                 case MONO_TYPE_BOOLEAN:
1004                 case MONO_TYPE_I1:
1005                 case MONO_TYPE_U1:
1006                 case MONO_TYPE_I2:
1007                 case MONO_TYPE_U2:
1008                 case MONO_TYPE_CHAR:
1009                 case MONO_TYPE_I4:
1010                 case MONO_TYPE_U4:
1011                 case MONO_TYPE_I:
1012                 case MONO_TYPE_U:
1013                 case MONO_TYPE_PTR:
1014                 case MONO_TYPE_FNPTR:
1015                 case MONO_TYPE_CLASS:
1016                 case MONO_TYPE_OBJECT:
1017                 case MONO_TYPE_SZARRAY:
1018                 case MONO_TYPE_ARRAY:
1019                 case MONO_TYPE_STRING:
1020                         cinfo->ret.storage = ArgInIReg;
1021                         cinfo->ret.reg = AMD64_RAX;
1022                         break;
1023                 case MONO_TYPE_U8:
1024                 case MONO_TYPE_I8:
1025                         cinfo->ret.storage = ArgInIReg;
1026                         cinfo->ret.reg = AMD64_RAX;
1027                         break;
1028                 case MONO_TYPE_R4:
1029                         cinfo->ret.storage = ArgInFloatSSEReg;
1030                         cinfo->ret.reg = AMD64_XMM0;
1031                         break;
1032                 case MONO_TYPE_R8:
1033                         cinfo->ret.storage = ArgInDoubleSSEReg;
1034                         cinfo->ret.reg = AMD64_XMM0;
1035                         break;
1036                 case MONO_TYPE_GENERICINST:
1037                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1038                                 cinfo->ret.storage = ArgInIReg;
1039                                 cinfo->ret.reg = AMD64_RAX;
1040                                 break;
1041                         }
1042                         /* fall through */
1043 #if defined( __native_client_codegen__ )
1044                 case MONO_TYPE_TYPEDBYREF:
1045 #endif
1046                 case MONO_TYPE_VALUETYPE: {
1047                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1048
1049                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1050                         if (cinfo->ret.storage == ArgOnStack) {
1051                                 cinfo->vtype_retaddr = TRUE;
1052                                 /* The caller passes the address where the value is stored */
1053                         }
1054                         break;
1055                 }
1056 #if !defined( __native_client_codegen__ )
1057                 case MONO_TYPE_TYPEDBYREF:
1058                         /* Same as a valuetype with size 24 */
1059                         cinfo->vtype_retaddr = TRUE;
1060                         break;
1061 #endif
1062                 case MONO_TYPE_VOID:
1063                         break;
1064                 default:
1065                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1066                 }
1067         }
1068
1069         pstart = 0;
1070         /*
1071          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1072          * the first argument, allowing 'this' to be always passed in the first arg reg.
1073          * Also do this if the first argument is a reference type, since virtual calls
1074          * are sometimes made using calli without sig->hasthis set, like in the delegate
1075          * invoke wrappers.
1076          */
1077         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1078                 if (sig->hasthis) {
1079                         add_general (&gr, &stack_size, cinfo->args + 0);
1080                 } else {
1081                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1082                         pstart = 1;
1083                 }
1084                 add_general (&gr, &stack_size, &cinfo->ret);
1085                 cinfo->vret_arg_index = 1;
1086         } else {
1087                 /* this */
1088                 if (sig->hasthis)
1089                         add_general (&gr, &stack_size, cinfo->args + 0);
1090
1091                 if (cinfo->vtype_retaddr)
1092                         add_general (&gr, &stack_size, &cinfo->ret);
1093         }
1094
1095         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1096                 gr = PARAM_REGS;
1097                 fr = FLOAT_PARAM_REGS;
1098
1099                 /* Emit the signature cookie just before the implicit arguments */
1100                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1101         }
1102
1103         for (i = pstart; i < sig->param_count; ++i) {
1104                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1105                 MonoType *ptype;
1106
1107 #ifdef HOST_WIN32
1108                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1109                 if (gr > fr)
1110                         fr = gr;
1111                 else if (fr > gr)
1112                         gr = fr;
1113 #endif
1114
1115                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1116                         /* We allways pass the sig cookie on the stack for simplicity */
1117                         /*
1118                          * Prevent implicit arguments + the sig cookie from being passed
1119                          * in registers.
1120                          */
1121                         gr = PARAM_REGS;
1122                         fr = FLOAT_PARAM_REGS;
1123
1124                         /* Emit the signature cookie just before the implicit arguments */
1125                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1126                 }
1127
1128                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1129                 switch (ptype->type) {
1130                 case MONO_TYPE_BOOLEAN:
1131                 case MONO_TYPE_I1:
1132                 case MONO_TYPE_U1:
1133                         add_general (&gr, &stack_size, ainfo);
1134                         break;
1135                 case MONO_TYPE_I2:
1136                 case MONO_TYPE_U2:
1137                 case MONO_TYPE_CHAR:
1138                         add_general (&gr, &stack_size, ainfo);
1139                         break;
1140                 case MONO_TYPE_I4:
1141                 case MONO_TYPE_U4:
1142                         add_general (&gr, &stack_size, ainfo);
1143                         break;
1144                 case MONO_TYPE_I:
1145                 case MONO_TYPE_U:
1146                 case MONO_TYPE_PTR:
1147                 case MONO_TYPE_FNPTR:
1148                 case MONO_TYPE_CLASS:
1149                 case MONO_TYPE_OBJECT:
1150                 case MONO_TYPE_STRING:
1151                 case MONO_TYPE_SZARRAY:
1152                 case MONO_TYPE_ARRAY:
1153                         add_general (&gr, &stack_size, ainfo);
1154                         break;
1155                 case MONO_TYPE_GENERICINST:
1156                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1157                                 add_general (&gr, &stack_size, ainfo);
1158                                 break;
1159                         }
1160                         /* fall through */
1161                 case MONO_TYPE_VALUETYPE:
1162                 case MONO_TYPE_TYPEDBYREF:
1163                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1164                         break;
1165                 case MONO_TYPE_U8:
1166
1167                 case MONO_TYPE_I8:
1168                         add_general (&gr, &stack_size, ainfo);
1169                         break;
1170                 case MONO_TYPE_R4:
1171                         add_float (&fr, &stack_size, ainfo, FALSE);
1172                         break;
1173                 case MONO_TYPE_R8:
1174                         add_float (&fr, &stack_size, ainfo, TRUE);
1175                         break;
1176                 default:
1177                         g_assert_not_reached ();
1178                 }
1179         }
1180
1181         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1182                 gr = PARAM_REGS;
1183                 fr = FLOAT_PARAM_REGS;
1184
1185                 /* Emit the signature cookie just before the implicit arguments */
1186                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1187         }
1188
1189         cinfo->stack_usage = stack_size;
1190         cinfo->reg_usage = gr;
1191         cinfo->freg_usage = fr;
1192         return cinfo;
1193 }
1194
1195 /*
1196  * mono_arch_get_argument_info:
1197  * @csig:  a method signature
1198  * @param_count: the number of parameters to consider
1199  * @arg_info: an array to store the result infos
1200  *
1201  * Gathers information on parameters such as size, alignment and
1202  * padding. arg_info should be large enought to hold param_count + 1 entries.
1203  *
1204  * Returns the size of the argument area on the stack.
1205  */
1206 int
1207 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1208 {
1209         int k;
1210         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1211         guint32 args_size = cinfo->stack_usage;
1212
1213         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1214         if (csig->hasthis) {
1215                 arg_info [0].offset = 0;
1216         }
1217
1218         for (k = 0; k < param_count; k++) {
1219                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1220                 /* FIXME: */
1221                 arg_info [k + 1].size = 0;
1222         }
1223
1224         g_free (cinfo);
1225
1226         return args_size;
1227 }
1228
1229 gboolean
1230 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1231 {
1232         CallInfo *c1, *c2;
1233         gboolean res;
1234         MonoType *callee_ret;
1235
1236         c1 = get_call_info (NULL, NULL, caller_sig);
1237         c2 = get_call_info (NULL, NULL, callee_sig);
1238         res = c1->stack_usage >= c2->stack_usage;
1239         callee_ret = mini_replace_type (callee_sig->ret);
1240         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1241                 /* An address on the callee's stack is passed as the first argument */
1242                 res = FALSE;
1243
1244         g_free (c1);
1245         g_free (c2);
1246
1247         return res;
1248 }
1249
1250 /*
1251  * Initialize the cpu to execute managed code.
1252  */
1253 void
1254 mono_arch_cpu_init (void)
1255 {
1256 #ifndef _MSC_VER
1257         guint16 fpcw;
1258
1259         /* spec compliance requires running with double precision */
1260         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1261         fpcw &= ~X86_FPCW_PRECC_MASK;
1262         fpcw |= X86_FPCW_PREC_DOUBLE;
1263         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1264         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1265 #else
1266         /* TODO: This is crashing on Win64 right now.
1267         * _control87 (_PC_53, MCW_PC);
1268         */
1269 #endif
1270 }
1271
1272 /*
1273  * Initialize architecture specific code.
1274  */
1275 void
1276 mono_arch_init (void)
1277 {
1278         int flags;
1279
1280         mono_mutex_init_recursive (&mini_arch_mutex);
1281 #if defined(__native_client_codegen__)
1282         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1283         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1284         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1285         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1286 #endif
1287
1288 #ifdef MONO_ARCH_NOMAP32BIT
1289         flags = MONO_MMAP_READ;
1290         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1291         breakpoint_size = 13;
1292         breakpoint_fault_size = 3;
1293 #else
1294         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1295         /* amd64_mov_reg_mem () */
1296         breakpoint_size = 8;
1297         breakpoint_fault_size = 8;
1298 #endif
1299
1300         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1301         single_step_fault_size = 4;
1302
1303         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1304         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1305         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1306
1307         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1308         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1309         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1310 }
1311
1312 /*
1313  * Cleanup architecture specific code.
1314  */
1315 void
1316 mono_arch_cleanup (void)
1317 {
1318         mono_mutex_destroy (&mini_arch_mutex);
1319 #if defined(__native_client_codegen__)
1320         mono_native_tls_free (nacl_instruction_depth);
1321         mono_native_tls_free (nacl_rex_tag);
1322         mono_native_tls_free (nacl_legacy_prefix_tag);
1323 #endif
1324 }
1325
1326 /*
1327  * This function returns the optimizations supported on this cpu.
1328  */
1329 guint32
1330 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1331 {
1332         guint32 opts = 0;
1333
1334         *exclude_mask = 0;
1335
1336         if (mono_hwcap_x86_has_cmov) {
1337                 opts |= MONO_OPT_CMOV;
1338
1339                 if (mono_hwcap_x86_has_fcmov)
1340                         opts |= MONO_OPT_FCMOV;
1341                 else
1342                         *exclude_mask |= MONO_OPT_FCMOV;
1343         } else {
1344                 *exclude_mask |= MONO_OPT_CMOV;
1345         }
1346
1347         return opts;
1348 }
1349
1350 /*
1351  * This function test for all SSE functions supported.
1352  *
1353  * Returns a bitmask corresponding to all supported versions.
1354  *
1355  */
1356 guint32
1357 mono_arch_cpu_enumerate_simd_versions (void)
1358 {
1359         guint32 sse_opts = 0;
1360
1361         if (mono_hwcap_x86_has_sse1)
1362                 sse_opts |= SIMD_VERSION_SSE1;
1363
1364         if (mono_hwcap_x86_has_sse2)
1365                 sse_opts |= SIMD_VERSION_SSE2;
1366
1367         if (mono_hwcap_x86_has_sse3)
1368                 sse_opts |= SIMD_VERSION_SSE3;
1369
1370         if (mono_hwcap_x86_has_ssse3)
1371                 sse_opts |= SIMD_VERSION_SSSE3;
1372
1373         if (mono_hwcap_x86_has_sse41)
1374                 sse_opts |= SIMD_VERSION_SSE41;
1375
1376         if (mono_hwcap_x86_has_sse42)
1377                 sse_opts |= SIMD_VERSION_SSE42;
1378
1379         if (mono_hwcap_x86_has_sse4a)
1380                 sse_opts |= SIMD_VERSION_SSE4a;
1381
1382         return sse_opts;
1383 }
1384
1385 #ifndef DISABLE_JIT
1386
1387 GList *
1388 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1389 {
1390         GList *vars = NULL;
1391         int i;
1392
1393         for (i = 0; i < cfg->num_varinfo; i++) {
1394                 MonoInst *ins = cfg->varinfo [i];
1395                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1396
1397                 /* unused vars */
1398                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1399                         continue;
1400
1401                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1402                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1403                         continue;
1404
1405                 if (mono_is_regsize_var (ins->inst_vtype)) {
1406                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1407                         g_assert (i == vmv->idx);
1408                         vars = g_list_prepend (vars, vmv);
1409                 }
1410         }
1411
1412         vars = mono_varlist_sort (cfg, vars, 0);
1413
1414         return vars;
1415 }
1416
1417 /**
1418  * mono_arch_compute_omit_fp:
1419  *
1420  *   Determine whenever the frame pointer can be eliminated.
1421  */
1422 static void
1423 mono_arch_compute_omit_fp (MonoCompile *cfg)
1424 {
1425         MonoMethodSignature *sig;
1426         MonoMethodHeader *header;
1427         int i, locals_size;
1428         CallInfo *cinfo;
1429
1430         if (cfg->arch.omit_fp_computed)
1431                 return;
1432
1433         header = cfg->header;
1434
1435         sig = mono_method_signature (cfg->method);
1436
1437         if (!cfg->arch.cinfo)
1438                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1439         cinfo = cfg->arch.cinfo;
1440
1441         /*
1442          * FIXME: Remove some of the restrictions.
1443          */
1444         cfg->arch.omit_fp = TRUE;
1445         cfg->arch.omit_fp_computed = TRUE;
1446
1447 #ifdef __native_client_codegen__
1448         /* NaCl modules may not change the value of RBP, so it cannot be */
1449         /* used as a normal register, but it can be used as a frame pointer*/
1450         cfg->disable_omit_fp = TRUE;
1451         cfg->arch.omit_fp = FALSE;
1452 #endif
1453
1454         if (cfg->disable_omit_fp)
1455                 cfg->arch.omit_fp = FALSE;
1456
1457         if (!debug_omit_fp ())
1458                 cfg->arch.omit_fp = FALSE;
1459         /*
1460         if (cfg->method->save_lmf)
1461                 cfg->arch.omit_fp = FALSE;
1462         */
1463         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1464                 cfg->arch.omit_fp = FALSE;
1465         if (header->num_clauses)
1466                 cfg->arch.omit_fp = FALSE;
1467         if (cfg->param_area)
1468                 cfg->arch.omit_fp = FALSE;
1469         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1470                 cfg->arch.omit_fp = FALSE;
1471         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1472                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1473                 cfg->arch.omit_fp = FALSE;
1474         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1475                 ArgInfo *ainfo = &cinfo->args [i];
1476
1477                 if (ainfo->storage == ArgOnStack) {
1478                         /*
1479                          * The stack offset can only be determined when the frame
1480                          * size is known.
1481                          */
1482                         cfg->arch.omit_fp = FALSE;
1483                 }
1484         }
1485
1486         locals_size = 0;
1487         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1488                 MonoInst *ins = cfg->varinfo [i];
1489                 int ialign;
1490
1491                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1492         }
1493 }
1494
1495 GList *
1496 mono_arch_get_global_int_regs (MonoCompile *cfg)
1497 {
1498         GList *regs = NULL;
1499
1500         mono_arch_compute_omit_fp (cfg);
1501
1502         if (cfg->globalra) {
1503                 if (cfg->arch.omit_fp)
1504                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1505
1506                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1507                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1508                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1509                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1510 #ifndef __native_client_codegen__
1511                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1512 #endif
1513
1514                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1515                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1516                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1517                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1518                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1519                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1522         } else {
1523                 if (cfg->arch.omit_fp)
1524                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1525
1526                 /* We use the callee saved registers for global allocation */
1527                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1531 #ifndef __native_client_codegen__
1532                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1533 #endif
1534 #ifdef HOST_WIN32
1535                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1536                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1537 #endif
1538         }
1539
1540         return regs;
1541 }
1542
1543 GList*
1544 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1545 {
1546         GList *regs = NULL;
1547         int i;
1548
1549         /* All XMM registers */
1550         for (i = 0; i < 16; ++i)
1551                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1552
1553         return regs;
1554 }
1555
1556 GList*
1557 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1558 {
1559         static GList *r = NULL;
1560
1561         if (r == NULL) {
1562                 GList *regs = NULL;
1563
1564                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1565                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1566                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1567                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1568                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1569 #ifndef __native_client_codegen__
1570                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1571 #endif
1572
1573                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1574                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1575                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1576                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1577                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1581
1582                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1583         }
1584
1585         return r;
1586 }
1587
1588 GList*
1589 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1590 {
1591         int i;
1592         static GList *r = NULL;
1593
1594         if (r == NULL) {
1595                 GList *regs = NULL;
1596
1597                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1598                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1599
1600                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1601         }
1602
1603         return r;
1604 }
1605
1606 /*
1607  * mono_arch_regalloc_cost:
1608  *
1609  *  Return the cost, in number of memory references, of the action of
1610  * allocating the variable VMV into a register during global register
1611  * allocation.
1612  */
1613 guint32
1614 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1615 {
1616         MonoInst *ins = cfg->varinfo [vmv->idx];
1617
1618         if (cfg->method->save_lmf)
1619                 /* The register is already saved */
1620                 /* substract 1 for the invisible store in the prolog */
1621                 return (ins->opcode == OP_ARG) ? 0 : 1;
1622         else
1623                 /* push+pop */
1624                 return (ins->opcode == OP_ARG) ? 1 : 2;
1625 }
1626
1627 /*
1628  * mono_arch_fill_argument_info:
1629  *
1630  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1631  * of the method.
1632  */
1633 void
1634 mono_arch_fill_argument_info (MonoCompile *cfg)
1635 {
1636         MonoType *sig_ret;
1637         MonoMethodSignature *sig;
1638         MonoMethodHeader *header;
1639         MonoInst *ins;
1640         int i;
1641         CallInfo *cinfo;
1642
1643         header = cfg->header;
1644
1645         sig = mono_method_signature (cfg->method);
1646
1647         cinfo = cfg->arch.cinfo;
1648         sig_ret = mini_replace_type (sig->ret);
1649
1650         /*
1651          * Contrary to mono_arch_allocate_vars (), the information should describe
1652          * where the arguments are at the beginning of the method, not where they can be
1653          * accessed during the execution of the method. The later makes no sense for the
1654          * global register allocator, since a variable can be in more than one location.
1655          */
1656         if (sig_ret->type != MONO_TYPE_VOID) {
1657                 switch (cinfo->ret.storage) {
1658                 case ArgInIReg:
1659                 case ArgInFloatSSEReg:
1660                 case ArgInDoubleSSEReg:
1661                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1662                                 cfg->vret_addr->opcode = OP_REGVAR;
1663                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1664                         }
1665                         else {
1666                                 cfg->ret->opcode = OP_REGVAR;
1667                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1668                         }
1669                         break;
1670                 case ArgValuetypeInReg:
1671                         cfg->ret->opcode = OP_REGOFFSET;
1672                         cfg->ret->inst_basereg = -1;
1673                         cfg->ret->inst_offset = -1;
1674                         break;
1675                 default:
1676                         g_assert_not_reached ();
1677                 }
1678         }
1679
1680         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1681                 ArgInfo *ainfo = &cinfo->args [i];
1682                 MonoType *arg_type;
1683
1684                 ins = cfg->args [i];
1685
1686                 if (sig->hasthis && (i == 0))
1687                         arg_type = &mono_defaults.object_class->byval_arg;
1688                 else
1689                         arg_type = sig->params [i - sig->hasthis];
1690
1691                 switch (ainfo->storage) {
1692                 case ArgInIReg:
1693                 case ArgInFloatSSEReg:
1694                 case ArgInDoubleSSEReg:
1695                         ins->opcode = OP_REGVAR;
1696                         ins->inst_c0 = ainfo->reg;
1697                         break;
1698                 case ArgOnStack:
1699                         ins->opcode = OP_REGOFFSET;
1700                         ins->inst_basereg = -1;
1701                         ins->inst_offset = -1;
1702                         break;
1703                 case ArgValuetypeInReg:
1704                         /* Dummy */
1705                         ins->opcode = OP_NOP;
1706                         break;
1707                 default:
1708                         g_assert_not_reached ();
1709                 }
1710         }
1711 }
1712
1713 void
1714 mono_arch_allocate_vars (MonoCompile *cfg)
1715 {
1716         MonoType *sig_ret;
1717         MonoMethodSignature *sig;
1718         MonoMethodHeader *header;
1719         MonoInst *ins;
1720         int i, offset;
1721         guint32 locals_stack_size, locals_stack_align;
1722         gint32 *offsets;
1723         CallInfo *cinfo;
1724
1725         header = cfg->header;
1726
1727         sig = mono_method_signature (cfg->method);
1728
1729         cinfo = cfg->arch.cinfo;
1730         sig_ret = mini_replace_type (sig->ret);
1731
1732         mono_arch_compute_omit_fp (cfg);
1733
1734         /*
1735          * We use the ABI calling conventions for managed code as well.
1736          * Exception: valuetypes are only sometimes passed or returned in registers.
1737          */
1738
1739         /*
1740          * The stack looks like this:
1741          * <incoming arguments passed on the stack>
1742          * <return value>
1743          * <lmf/caller saved registers>
1744          * <locals>
1745          * <spill area>
1746          * <localloc area>  -> grows dynamically
1747          * <params area>
1748          */
1749
1750         if (cfg->arch.omit_fp) {
1751                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1752                 cfg->frame_reg = AMD64_RSP;
1753                 offset = 0;
1754         } else {
1755                 /* Locals are allocated backwards from %fp */
1756                 cfg->frame_reg = AMD64_RBP;
1757                 offset = 0;
1758         }
1759
1760         cfg->arch.saved_iregs = cfg->used_int_regs;
1761         if (cfg->method->save_lmf)
1762                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1763                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1764
1765         if (cfg->arch.omit_fp)
1766                 cfg->arch.reg_save_area_offset = offset;
1767         /* Reserve space for callee saved registers */
1768         for (i = 0; i < AMD64_NREG; ++i)
1769                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1770                         offset += sizeof(mgreg_t);
1771                 }
1772         if (!cfg->arch.omit_fp)
1773                 cfg->arch.reg_save_area_offset = -offset;
1774
1775         if (sig_ret->type != MONO_TYPE_VOID) {
1776                 switch (cinfo->ret.storage) {
1777                 case ArgInIReg:
1778                 case ArgInFloatSSEReg:
1779                 case ArgInDoubleSSEReg:
1780                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1781                                 if (cfg->globalra) {
1782                                         cfg->vret_addr->opcode = OP_REGVAR;
1783                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1784                                 } else {
1785                                         /* The register is volatile */
1786                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1787                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1788                                         if (cfg->arch.omit_fp) {
1789                                                 cfg->vret_addr->inst_offset = offset;
1790                                                 offset += 8;
1791                                         } else {
1792                                                 offset += 8;
1793                                                 cfg->vret_addr->inst_offset = -offset;
1794                                         }
1795                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1796                                                 printf ("vret_addr =");
1797                                                 mono_print_ins (cfg->vret_addr);
1798                                         }
1799                                 }
1800                         }
1801                         else {
1802                                 cfg->ret->opcode = OP_REGVAR;
1803                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1804                         }
1805                         break;
1806                 case ArgValuetypeInReg:
1807                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1808                         cfg->ret->opcode = OP_REGOFFSET;
1809                         cfg->ret->inst_basereg = cfg->frame_reg;
1810                         if (cfg->arch.omit_fp) {
1811                                 cfg->ret->inst_offset = offset;
1812                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1813                         } else {
1814                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1815                                 cfg->ret->inst_offset = - offset;
1816                         }
1817                         break;
1818                 default:
1819                         g_assert_not_reached ();
1820                 }
1821                 if (!cfg->globalra)
1822                         cfg->ret->dreg = cfg->ret->inst_c0;
1823         }
1824
1825         /* Allocate locals */
1826         if (!cfg->globalra) {
1827                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1828                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1829                         char *mname = mono_method_full_name (cfg->method, TRUE);
1830                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1831                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1832                         g_free (mname);
1833                         return;
1834                 }
1835
1836                 if (locals_stack_align) {
1837                         offset += (locals_stack_align - 1);
1838                         offset &= ~(locals_stack_align - 1);
1839                 }
1840                 if (cfg->arch.omit_fp) {
1841                         cfg->locals_min_stack_offset = offset;
1842                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1843                 } else {
1844                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1845                         cfg->locals_max_stack_offset = - offset;
1846                 }
1847
1848                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1849                         if (offsets [i] != -1) {
1850                                 MonoInst *ins = cfg->varinfo [i];
1851                                 ins->opcode = OP_REGOFFSET;
1852                                 ins->inst_basereg = cfg->frame_reg;
1853                                 if (cfg->arch.omit_fp)
1854                                         ins->inst_offset = (offset + offsets [i]);
1855                                 else
1856                                         ins->inst_offset = - (offset + offsets [i]);
1857                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1858                         }
1859                 }
1860                 offset += locals_stack_size;
1861         }
1862
1863         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1864                 g_assert (!cfg->arch.omit_fp);
1865                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1866                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1867         }
1868
1869         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1870                 ins = cfg->args [i];
1871                 if (ins->opcode != OP_REGVAR) {
1872                         ArgInfo *ainfo = &cinfo->args [i];
1873                         gboolean inreg = TRUE;
1874                         MonoType *arg_type;
1875
1876                         if (sig->hasthis && (i == 0))
1877                                 arg_type = &mono_defaults.object_class->byval_arg;
1878                         else
1879                                 arg_type = sig->params [i - sig->hasthis];
1880
1881                         if (cfg->globalra) {
1882                                 /* The new allocator needs info about the original locations of the arguments */
1883                                 switch (ainfo->storage) {
1884                                 case ArgInIReg:
1885                                 case ArgInFloatSSEReg:
1886                                 case ArgInDoubleSSEReg:
1887                                         ins->opcode = OP_REGVAR;
1888                                         ins->inst_c0 = ainfo->reg;
1889                                         break;
1890                                 case ArgOnStack:
1891                                         g_assert (!cfg->arch.omit_fp);
1892                                         ins->opcode = OP_REGOFFSET;
1893                                         ins->inst_basereg = cfg->frame_reg;
1894                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1895                                         break;
1896                                 case ArgValuetypeInReg:
1897                                         ins->opcode = OP_REGOFFSET;
1898                                         ins->inst_basereg = cfg->frame_reg;
1899                                         /* These arguments are saved to the stack in the prolog */
1900                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1901                                         if (cfg->arch.omit_fp) {
1902                                                 ins->inst_offset = offset;
1903                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1904                                         } else {
1905                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1906                                                 ins->inst_offset = - offset;
1907                                         }
1908                                         break;
1909                                 default:
1910                                         g_assert_not_reached ();
1911                                 }
1912
1913                                 continue;
1914                         }
1915
1916                         /* FIXME: Allocate volatile arguments to registers */
1917                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1918                                 inreg = FALSE;
1919
1920                         /*
1921                          * Under AMD64, all registers used to pass arguments to functions
1922                          * are volatile across calls.
1923                          * FIXME: Optimize this.
1924                          */
1925                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1926                                 inreg = FALSE;
1927
1928                         ins->opcode = OP_REGOFFSET;
1929
1930                         switch (ainfo->storage) {
1931                         case ArgInIReg:
1932                         case ArgInFloatSSEReg:
1933                         case ArgInDoubleSSEReg:
1934                                 if (inreg) {
1935                                         ins->opcode = OP_REGVAR;
1936                                         ins->dreg = ainfo->reg;
1937                                 }
1938                                 break;
1939                         case ArgOnStack:
1940                                 g_assert (!cfg->arch.omit_fp);
1941                                 ins->opcode = OP_REGOFFSET;
1942                                 ins->inst_basereg = cfg->frame_reg;
1943                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1944                                 break;
1945                         case ArgValuetypeInReg:
1946                                 break;
1947                         case ArgValuetypeAddrInIReg: {
1948                                 MonoInst *indir;
1949                                 g_assert (!cfg->arch.omit_fp);
1950
1951                                 MONO_INST_NEW (cfg, indir, 0);
1952                                 indir->opcode = OP_REGOFFSET;
1953                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1954                                         indir->inst_basereg = cfg->frame_reg;
1955                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1956                                         offset += (sizeof (gpointer));
1957                                         indir->inst_offset = - offset;
1958                                 }
1959                                 else {
1960                                         indir->inst_basereg = cfg->frame_reg;
1961                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1962                                 }
1963
1964                                 ins->opcode = OP_VTARG_ADDR;
1965                                 ins->inst_left = indir;
1966
1967                                 break;
1968                         }
1969                         default:
1970                                 NOT_IMPLEMENTED;
1971                         }
1972
1973                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1974                                 ins->opcode = OP_REGOFFSET;
1975                                 ins->inst_basereg = cfg->frame_reg;
1976                                 /* These arguments are saved to the stack in the prolog */
1977                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1978                                 if (cfg->arch.omit_fp) {
1979                                         ins->inst_offset = offset;
1980                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1981                                         // Arguments are yet supported by the stack map creation code
1982                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1983                                 } else {
1984                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1985                                         ins->inst_offset = - offset;
1986                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1987                                 }
1988                         }
1989                 }
1990         }
1991
1992         cfg->stack_offset = offset;
1993 }
1994
1995 void
1996 mono_arch_create_vars (MonoCompile *cfg)
1997 {
1998         MonoMethodSignature *sig;
1999         CallInfo *cinfo;
2000         MonoType *sig_ret;
2001
2002         sig = mono_method_signature (cfg->method);
2003
2004         if (!cfg->arch.cinfo)
2005                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2006         cinfo = cfg->arch.cinfo;
2007
2008         if (cinfo->ret.storage == ArgValuetypeInReg)
2009                 cfg->ret_var_is_local = TRUE;
2010
2011         sig_ret = mini_replace_type (sig->ret);
2012         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2013                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2014                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2015                         printf ("vret_addr = ");
2016                         mono_print_ins (cfg->vret_addr);
2017                 }
2018         }
2019
2020         if (cfg->gen_seq_points) {
2021                 MonoInst *ins;
2022
2023                 if (cfg->compile_aot) {
2024                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2025                         ins->flags |= MONO_INST_VOLATILE;
2026                         cfg->arch.seq_point_info_var = ins;
2027                 }
2028
2029             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2030                 ins->flags |= MONO_INST_VOLATILE;
2031                 cfg->arch.ss_trigger_page_var = ins;
2032         }
2033
2034         if (cfg->method->save_lmf)
2035                 cfg->create_lmf_var = TRUE;
2036
2037         if (cfg->method->save_lmf) {
2038                 cfg->lmf_ir = TRUE;
2039 #if !defined(HOST_WIN32)
2040                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2041                         cfg->lmf_ir_mono_lmf = TRUE;
2042 #endif
2043         }
2044 }
2045
2046 static void
2047 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2048 {
2049         MonoInst *ins;
2050
2051         switch (storage) {
2052         case ArgInIReg:
2053                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2054                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2055                 ins->sreg1 = tree->dreg;
2056                 MONO_ADD_INS (cfg->cbb, ins);
2057                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2058                 break;
2059         case ArgInFloatSSEReg:
2060                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2061                 ins->dreg = mono_alloc_freg (cfg);
2062                 ins->sreg1 = tree->dreg;
2063                 MONO_ADD_INS (cfg->cbb, ins);
2064
2065                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2066                 break;
2067         case ArgInDoubleSSEReg:
2068                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2069                 ins->dreg = mono_alloc_freg (cfg);
2070                 ins->sreg1 = tree->dreg;
2071                 MONO_ADD_INS (cfg->cbb, ins);
2072
2073                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2074
2075                 break;
2076         default:
2077                 g_assert_not_reached ();
2078         }
2079 }
2080
2081 static int
2082 arg_storage_to_load_membase (ArgStorage storage)
2083 {
2084         switch (storage) {
2085         case ArgInIReg:
2086 #if defined(__mono_ilp32__)
2087                 return OP_LOADI8_MEMBASE;
2088 #else
2089                 return OP_LOAD_MEMBASE;
2090 #endif
2091         case ArgInDoubleSSEReg:
2092                 return OP_LOADR8_MEMBASE;
2093         case ArgInFloatSSEReg:
2094                 return OP_LOADR4_MEMBASE;
2095         default:
2096                 g_assert_not_reached ();
2097         }
2098
2099         return -1;
2100 }
2101
2102 static void
2103 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2104 {
2105         MonoMethodSignature *tmp_sig;
2106         int sig_reg;
2107
2108         if (call->tail_call)
2109                 NOT_IMPLEMENTED;
2110
2111         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2112
2113         /*
2114          * mono_ArgIterator_Setup assumes the signature cookie is
2115          * passed first and all the arguments which were before it are
2116          * passed on the stack after the signature. So compensate by
2117          * passing a different signature.
2118          */
2119         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2120         tmp_sig->param_count -= call->signature->sentinelpos;
2121         tmp_sig->sentinelpos = 0;
2122         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2123
2124         sig_reg = mono_alloc_ireg (cfg);
2125         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2126
2127         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2128 }
2129
2130 static inline LLVMArgStorage
2131 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2132 {
2133         switch (storage) {
2134         case ArgInIReg:
2135                 return LLVMArgInIReg;
2136         case ArgNone:
2137                 return LLVMArgNone;
2138         default:
2139                 g_assert_not_reached ();
2140                 return LLVMArgNone;
2141         }
2142 }
2143
2144 #ifdef ENABLE_LLVM
2145 LLVMCallInfo*
2146 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2147 {
2148         int i, n;
2149         CallInfo *cinfo;
2150         ArgInfo *ainfo;
2151         int j;
2152         LLVMCallInfo *linfo;
2153         MonoType *t, *sig_ret;
2154
2155         n = sig->param_count + sig->hasthis;
2156         sig_ret = mini_replace_type (sig->ret);
2157
2158         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2159
2160         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2161
2162         /*
2163          * LLVM always uses the native ABI while we use our own ABI, the
2164          * only difference is the handling of vtypes:
2165          * - we only pass/receive them in registers in some cases, and only
2166          *   in 1 or 2 integer registers.
2167          */
2168         if (cinfo->ret.storage == ArgValuetypeInReg) {
2169                 if (sig->pinvoke) {
2170                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2171                         cfg->disable_llvm = TRUE;
2172                         return linfo;
2173                 }
2174
2175                 linfo->ret.storage = LLVMArgVtypeInReg;
2176                 for (j = 0; j < 2; ++j)
2177                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2178         }
2179
2180         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2181                 /* Vtype returned using a hidden argument */
2182                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2183                 linfo->vret_arg_index = cinfo->vret_arg_index;
2184         }
2185
2186         for (i = 0; i < n; ++i) {
2187                 ainfo = cinfo->args + i;
2188
2189                 if (i >= sig->hasthis)
2190                         t = sig->params [i - sig->hasthis];
2191                 else
2192                         t = &mono_defaults.int_class->byval_arg;
2193
2194                 linfo->args [i].storage = LLVMArgNone;
2195
2196                 switch (ainfo->storage) {
2197                 case ArgInIReg:
2198                         linfo->args [i].storage = LLVMArgInIReg;
2199                         break;
2200                 case ArgInDoubleSSEReg:
2201                 case ArgInFloatSSEReg:
2202                         linfo->args [i].storage = LLVMArgInFPReg;
2203                         break;
2204                 case ArgOnStack:
2205                         if (MONO_TYPE_ISSTRUCT (t)) {
2206                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2207                         } else {
2208                                 linfo->args [i].storage = LLVMArgInIReg;
2209                                 if (!t->byref) {
2210                                         if (t->type == MONO_TYPE_R4)
2211                                                 linfo->args [i].storage = LLVMArgInFPReg;
2212                                         else if (t->type == MONO_TYPE_R8)
2213                                                 linfo->args [i].storage = LLVMArgInFPReg;
2214                                 }
2215                         }
2216                         break;
2217                 case ArgValuetypeInReg:
2218                         if (sig->pinvoke) {
2219                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2220                                 cfg->disable_llvm = TRUE;
2221                                 return linfo;
2222                         }
2223
2224                         linfo->args [i].storage = LLVMArgVtypeInReg;
2225                         for (j = 0; j < 2; ++j)
2226                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2227                         break;
2228                 default:
2229                         cfg->exception_message = g_strdup ("ainfo->storage");
2230                         cfg->disable_llvm = TRUE;
2231                         break;
2232                 }
2233         }
2234
2235         return linfo;
2236 }
2237 #endif
2238
2239 void
2240 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2241 {
2242         MonoInst *arg, *in;
2243         MonoMethodSignature *sig;
2244         MonoType *sig_ret;
2245         int i, n, stack_size;
2246         CallInfo *cinfo;
2247         ArgInfo *ainfo;
2248
2249         stack_size = 0;
2250
2251         sig = call->signature;
2252         n = sig->param_count + sig->hasthis;
2253
2254         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2255
2256         sig_ret = sig->ret;
2257
2258         if (COMPILE_LLVM (cfg)) {
2259                 /* We shouldn't be called in the llvm case */
2260                 cfg->disable_llvm = TRUE;
2261                 return;
2262         }
2263
2264         /*
2265          * Emit all arguments which are passed on the stack to prevent register
2266          * allocation problems.
2267          */
2268         for (i = 0; i < n; ++i) {
2269                 MonoType *t;
2270                 ainfo = cinfo->args + i;
2271
2272                 in = call->args [i];
2273
2274                 if (sig->hasthis && i == 0)
2275                         t = &mono_defaults.object_class->byval_arg;
2276                 else
2277                         t = sig->params [i - sig->hasthis];
2278
2279                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2280                         if (!t->byref) {
2281                                 if (t->type == MONO_TYPE_R4)
2282                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2283                                 else if (t->type == MONO_TYPE_R8)
2284                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2285                                 else
2286                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2287                         } else {
2288                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2289                         }
2290                         if (cfg->compute_gc_maps) {
2291                                 MonoInst *def;
2292
2293                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2294                         }
2295                 }
2296         }
2297
2298         /*
2299          * Emit all parameters passed in registers in non-reverse order for better readability
2300          * and to help the optimization in emit_prolog ().
2301          */
2302         for (i = 0; i < n; ++i) {
2303                 ainfo = cinfo->args + i;
2304
2305                 in = call->args [i];
2306
2307                 if (ainfo->storage == ArgInIReg)
2308                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2309         }
2310
2311         for (i = n - 1; i >= 0; --i) {
2312                 ainfo = cinfo->args + i;
2313
2314                 in = call->args [i];
2315
2316                 switch (ainfo->storage) {
2317                 case ArgInIReg:
2318                         /* Already done */
2319                         break;
2320                 case ArgInFloatSSEReg:
2321                 case ArgInDoubleSSEReg:
2322                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2323                         break;
2324                 case ArgOnStack:
2325                 case ArgValuetypeInReg:
2326                 case ArgValuetypeAddrInIReg:
2327                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2328                                 MonoInst *call_inst = (MonoInst*)call;
2329                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2330                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2331                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2332                                 guint32 align;
2333                                 guint32 size;
2334
2335                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2336                                         size = sizeof (MonoTypedRef);
2337                                         align = sizeof (gpointer);
2338                                 }
2339                                 else {
2340                                         if (sig->pinvoke)
2341                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2342                                         else {
2343                                                 /*
2344                                                  * Other backends use mono_type_stack_size (), but that
2345                                                  * aligns the size to 8, which is larger than the size of
2346                                                  * the source, leading to reads of invalid memory if the
2347                                                  * source is at the end of address space.
2348                                                  */
2349                                                 size = mono_class_value_size (in->klass, &align);
2350                                         }
2351                                 }
2352                                 g_assert (in->klass);
2353
2354                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2355                                         /* Avoid asserts in emit_memcpy () */
2356                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2357                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2358                                         /* Continue normally */
2359                                 }
2360
2361                                 if (size > 0) {
2362                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2363                                         arg->sreg1 = in->dreg;
2364                                         arg->klass = in->klass;
2365                                         arg->backend.size = size;
2366                                         arg->inst_p0 = call;
2367                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2368                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2369
2370                                         MONO_ADD_INS (cfg->cbb, arg);
2371                                 }
2372                         }
2373                         break;
2374                 default:
2375                         g_assert_not_reached ();
2376                 }
2377
2378                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2379                         /* Emit the signature cookie just before the implicit arguments */
2380                         emit_sig_cookie (cfg, call, cinfo);
2381         }
2382
2383         /* Handle the case where there are no implicit arguments */
2384         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2385                 emit_sig_cookie (cfg, call, cinfo);
2386
2387         sig_ret = mini_replace_type (sig->ret);
2388         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2389                 MonoInst *vtarg;
2390
2391                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2392                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2393                                 /*
2394                                  * Tell the JIT to use a more efficient calling convention: call using
2395                                  * OP_CALL, compute the result location after the call, and save the
2396                                  * result there.
2397                                  */
2398                                 call->vret_in_reg = TRUE;
2399                                 /*
2400                                  * Nullify the instruction computing the vret addr to enable
2401                                  * future optimizations.
2402                                  */
2403                                 if (call->vret_var)
2404                                         NULLIFY_INS (call->vret_var);
2405                         } else {
2406                                 if (call->tail_call)
2407                                         NOT_IMPLEMENTED;
2408                                 /*
2409                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2410                                  * the stack. Push the address here, so the call instruction can
2411                                  * access it.
2412                                  */
2413                                 if (!cfg->arch.vret_addr_loc) {
2414                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2415                                         /* Prevent it from being register allocated or optimized away */
2416                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2417                                 }
2418
2419                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2420                         }
2421                 }
2422                 else {
2423                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2424                         vtarg->sreg1 = call->vret_var->dreg;
2425                         vtarg->dreg = mono_alloc_preg (cfg);
2426                         MONO_ADD_INS (cfg->cbb, vtarg);
2427
2428                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2429                 }
2430         }
2431
2432         if (cfg->method->save_lmf) {
2433                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2434                 MONO_ADD_INS (cfg->cbb, arg);
2435         }
2436
2437         call->stack_usage = cinfo->stack_usage;
2438 }
2439
2440 void
2441 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2442 {
2443         MonoInst *arg;
2444         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2445         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2446         int size = ins->backend.size;
2447
2448         if (ainfo->storage == ArgValuetypeInReg) {
2449                 MonoInst *load;
2450                 int part;
2451
2452                 for (part = 0; part < 2; ++part) {
2453                         if (ainfo->pair_storage [part] == ArgNone)
2454                                 continue;
2455
2456                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2457                         load->inst_basereg = src->dreg;
2458                         load->inst_offset = part * sizeof(mgreg_t);
2459
2460                         switch (ainfo->pair_storage [part]) {
2461                         case ArgInIReg:
2462                                 load->dreg = mono_alloc_ireg (cfg);
2463                                 break;
2464                         case ArgInDoubleSSEReg:
2465                         case ArgInFloatSSEReg:
2466                                 load->dreg = mono_alloc_freg (cfg);
2467                                 break;
2468                         default:
2469                                 g_assert_not_reached ();
2470                         }
2471                         MONO_ADD_INS (cfg->cbb, load);
2472
2473                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2474                 }
2475         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2476                 MonoInst *vtaddr, *load;
2477                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2478
2479                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2480                 cfg->has_indirection = TRUE;
2481                 load->inst_p0 = vtaddr;
2482                 vtaddr->flags |= MONO_INST_INDIRECT;
2483                 load->type = STACK_MP;
2484                 load->klass = vtaddr->klass;
2485                 load->dreg = mono_alloc_ireg (cfg);
2486                 MONO_ADD_INS (cfg->cbb, load);
2487                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2488
2489                 if (ainfo->pair_storage [0] == ArgInIReg) {
2490                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2491                         arg->dreg = mono_alloc_ireg (cfg);
2492                         arg->sreg1 = load->dreg;
2493                         arg->inst_imm = 0;
2494                         MONO_ADD_INS (cfg->cbb, arg);
2495                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2496                 } else {
2497                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2498                 }
2499         } else {
2500                 if (size == 8) {
2501                         int dreg = mono_alloc_ireg (cfg);
2502
2503                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2504                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2505                 } else if (size <= 40) {
2506                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2507                 } else {
2508                         // FIXME: Code growth
2509                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2510                 }
2511
2512                 if (cfg->compute_gc_maps) {
2513                         MonoInst *def;
2514                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2515                 }
2516         }
2517 }
2518
2519 void
2520 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2521 {
2522         MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2523
2524         if (ret->type == MONO_TYPE_R4) {
2525                 if (COMPILE_LLVM (cfg))
2526                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2527                 else
2528                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2529                 return;
2530         } else if (ret->type == MONO_TYPE_R8) {
2531                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2532                 return;
2533         }
2534
2535         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2536 }
2537
2538 #endif /* DISABLE_JIT */
2539
2540 #define EMIT_COND_BRANCH(ins,cond,sign) \
2541         if (ins->inst_true_bb->native_offset) { \
2542                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2543         } else { \
2544                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2545                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2546             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2547                         x86_branch8 (code, cond, 0, sign); \
2548                 else \
2549                         x86_branch32 (code, cond, 0, sign); \
2550 }
2551
2552 typedef struct {
2553         MonoMethodSignature *sig;
2554         CallInfo *cinfo;
2555 } ArchDynCallInfo;
2556
2557 static gboolean
2558 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2559 {
2560         int i;
2561
2562 #ifdef HOST_WIN32
2563         return FALSE;
2564 #endif
2565
2566         switch (cinfo->ret.storage) {
2567         case ArgNone:
2568         case ArgInIReg:
2569                 break;
2570         case ArgValuetypeInReg: {
2571                 ArgInfo *ainfo = &cinfo->ret;
2572
2573                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2574                         return FALSE;
2575                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2576                         return FALSE;
2577                 break;
2578         }
2579         default:
2580                 return FALSE;
2581         }
2582
2583         for (i = 0; i < cinfo->nargs; ++i) {
2584                 ArgInfo *ainfo = &cinfo->args [i];
2585                 switch (ainfo->storage) {
2586                 case ArgInIReg:
2587                         break;
2588                 case ArgValuetypeInReg:
2589                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2590                                 return FALSE;
2591                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2592                                 return FALSE;
2593                         break;
2594                 default:
2595                         return FALSE;
2596                 }
2597         }
2598
2599         return TRUE;
2600 }
2601
2602 /*
2603  * mono_arch_dyn_call_prepare:
2604  *
2605  *   Return a pointer to an arch-specific structure which contains information
2606  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2607  * supported for SIG.
2608  * This function is equivalent to ffi_prep_cif in libffi.
2609  */
2610 MonoDynCallInfo*
2611 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2612 {
2613         ArchDynCallInfo *info;
2614         CallInfo *cinfo;
2615
2616         cinfo = get_call_info (NULL, NULL, sig);
2617
2618         if (!dyn_call_supported (sig, cinfo)) {
2619                 g_free (cinfo);
2620                 return NULL;
2621         }
2622
2623         info = g_new0 (ArchDynCallInfo, 1);
2624         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2625         info->sig = sig;
2626         info->cinfo = cinfo;
2627
2628         return (MonoDynCallInfo*)info;
2629 }
2630
2631 /*
2632  * mono_arch_dyn_call_free:
2633  *
2634  *   Free a MonoDynCallInfo structure.
2635  */
2636 void
2637 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2638 {
2639         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2640
2641         g_free (ainfo->cinfo);
2642         g_free (ainfo);
2643 }
2644
2645 #if !defined(__native_client__)
2646 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2647 #define GREG_TO_PTR(greg) (gpointer)(greg)
2648 #else
2649 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2650 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2651 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2652 #endif
2653
2654 /*
2655  * mono_arch_get_start_dyn_call:
2656  *
2657  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2658  * store the result into BUF.
2659  * ARGS should be an array of pointers pointing to the arguments.
2660  * RET should point to a memory buffer large enought to hold the result of the
2661  * call.
2662  * This function should be as fast as possible, any work which does not depend
2663  * on the actual values of the arguments should be done in
2664  * mono_arch_dyn_call_prepare ().
2665  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2666  * libffi.
2667  */
2668 void
2669 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2670 {
2671         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2672         DynCallArgs *p = (DynCallArgs*)buf;
2673         int arg_index, greg, i, pindex;
2674         MonoMethodSignature *sig = dinfo->sig;
2675
2676         g_assert (buf_len >= sizeof (DynCallArgs));
2677
2678         p->res = 0;
2679         p->ret = ret;
2680
2681         arg_index = 0;
2682         greg = 0;
2683         pindex = 0;
2684
2685         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2686                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2687                 if (!sig->hasthis)
2688                         pindex = 1;
2689         }
2690
2691         if (dinfo->cinfo->vtype_retaddr)
2692                 p->regs [greg ++] = PTR_TO_GREG(ret);
2693
2694         for (i = pindex; i < sig->param_count; i++) {
2695                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2696                 gpointer *arg = args [arg_index ++];
2697
2698                 if (t->byref) {
2699                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2700                         continue;
2701                 }
2702
2703                 switch (t->type) {
2704                 case MONO_TYPE_STRING:
2705                 case MONO_TYPE_CLASS:
2706                 case MONO_TYPE_ARRAY:
2707                 case MONO_TYPE_SZARRAY:
2708                 case MONO_TYPE_OBJECT:
2709                 case MONO_TYPE_PTR:
2710                 case MONO_TYPE_I:
2711                 case MONO_TYPE_U:
2712 #if !defined(__mono_ilp32__)
2713                 case MONO_TYPE_I8:
2714                 case MONO_TYPE_U8:
2715 #endif
2716                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2717                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2718                         break;
2719 #if defined(__mono_ilp32__)
2720                 case MONO_TYPE_I8:
2721                 case MONO_TYPE_U8:
2722                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2723                         p->regs [greg ++] = *(guint64*)(arg);
2724                         break;
2725 #endif
2726                 case MONO_TYPE_BOOLEAN:
2727                 case MONO_TYPE_U1:
2728                         p->regs [greg ++] = *(guint8*)(arg);
2729                         break;
2730                 case MONO_TYPE_I1:
2731                         p->regs [greg ++] = *(gint8*)(arg);
2732                         break;
2733                 case MONO_TYPE_I2:
2734                         p->regs [greg ++] = *(gint16*)(arg);
2735                         break;
2736                 case MONO_TYPE_U2:
2737                 case MONO_TYPE_CHAR:
2738                         p->regs [greg ++] = *(guint16*)(arg);
2739                         break;
2740                 case MONO_TYPE_I4:
2741                         p->regs [greg ++] = *(gint32*)(arg);
2742                         break;
2743                 case MONO_TYPE_U4:
2744                         p->regs [greg ++] = *(guint32*)(arg);
2745                         break;
2746                 case MONO_TYPE_GENERICINST:
2747                     if (MONO_TYPE_IS_REFERENCE (t)) {
2748                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2749                                 break;
2750                         } else {
2751                                 /* Fall through */
2752                         }
2753                 case MONO_TYPE_VALUETYPE: {
2754                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2755
2756                         g_assert (ainfo->storage == ArgValuetypeInReg);
2757                         if (ainfo->pair_storage [0] != ArgNone) {
2758                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2759                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2760                         }
2761                         if (ainfo->pair_storage [1] != ArgNone) {
2762                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2763                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2764                         }
2765                         break;
2766                 }
2767                 default:
2768                         g_assert_not_reached ();
2769                 }
2770         }
2771
2772         g_assert (greg <= PARAM_REGS);
2773 }
2774
2775 /*
2776  * mono_arch_finish_dyn_call:
2777  *
2778  *   Store the result of a dyn call into the return value buffer passed to
2779  * start_dyn_call ().
2780  * This function should be as fast as possible, any work which does not depend
2781  * on the actual values of the arguments should be done in
2782  * mono_arch_dyn_call_prepare ().
2783  */
2784 void
2785 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2786 {
2787         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2788         MonoMethodSignature *sig = dinfo->sig;
2789         guint8 *ret = ((DynCallArgs*)buf)->ret;
2790         mgreg_t res = ((DynCallArgs*)buf)->res;
2791         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2792
2793         switch (sig_ret->type) {
2794         case MONO_TYPE_VOID:
2795                 *(gpointer*)ret = NULL;
2796                 break;
2797         case MONO_TYPE_STRING:
2798         case MONO_TYPE_CLASS:
2799         case MONO_TYPE_ARRAY:
2800         case MONO_TYPE_SZARRAY:
2801         case MONO_TYPE_OBJECT:
2802         case MONO_TYPE_I:
2803         case MONO_TYPE_U:
2804         case MONO_TYPE_PTR:
2805                 *(gpointer*)ret = GREG_TO_PTR(res);
2806                 break;
2807         case MONO_TYPE_I1:
2808                 *(gint8*)ret = res;
2809                 break;
2810         case MONO_TYPE_U1:
2811         case MONO_TYPE_BOOLEAN:
2812                 *(guint8*)ret = res;
2813                 break;
2814         case MONO_TYPE_I2:
2815                 *(gint16*)ret = res;
2816                 break;
2817         case MONO_TYPE_U2:
2818         case MONO_TYPE_CHAR:
2819                 *(guint16*)ret = res;
2820                 break;
2821         case MONO_TYPE_I4:
2822                 *(gint32*)ret = res;
2823                 break;
2824         case MONO_TYPE_U4:
2825                 *(guint32*)ret = res;
2826                 break;
2827         case MONO_TYPE_I8:
2828                 *(gint64*)ret = res;
2829                 break;
2830         case MONO_TYPE_U8:
2831                 *(guint64*)ret = res;
2832                 break;
2833         case MONO_TYPE_GENERICINST:
2834                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2835                         *(gpointer*)ret = GREG_TO_PTR(res);
2836                         break;
2837                 } else {
2838                         /* Fall through */
2839                 }
2840         case MONO_TYPE_VALUETYPE:
2841                 if (dinfo->cinfo->vtype_retaddr) {
2842                         /* Nothing to do */
2843                 } else {
2844                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2845
2846                         g_assert (ainfo->storage == ArgValuetypeInReg);
2847
2848                         if (ainfo->pair_storage [0] != ArgNone) {
2849                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2850                                 ((mgreg_t*)ret)[0] = res;
2851                         }
2852
2853                         g_assert (ainfo->pair_storage [1] == ArgNone);
2854                 }
2855                 break;
2856         default:
2857                 g_assert_not_reached ();
2858         }
2859 }
2860
2861 /* emit an exception if condition is fail */
2862 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2863         do {                                                        \
2864                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2865                 if (tins == NULL) {                                                                             \
2866                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2867                                         MONO_PATCH_INFO_EXC, exc_name);  \
2868                         x86_branch32 (code, cond, 0, signed);               \
2869                 } else {        \
2870                         EMIT_COND_BRANCH (tins, cond, signed);  \
2871                 }                       \
2872         } while (0);
2873
2874 #define EMIT_FPCOMPARE(code) do { \
2875         amd64_fcompp (code); \
2876         amd64_fnstsw (code); \
2877 } while (0);
2878
2879 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2880     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2881         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2882         amd64_ ##op (code); \
2883         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2884         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2885 } while (0);
2886
2887 static guint8*
2888 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2889 {
2890         gboolean no_patch = FALSE;
2891
2892         /*
2893          * FIXME: Add support for thunks
2894          */
2895         {
2896                 gboolean near_call = FALSE;
2897
2898                 /*
2899                  * Indirect calls are expensive so try to make a near call if possible.
2900                  * The caller memory is allocated by the code manager so it is
2901                  * guaranteed to be at a 32 bit offset.
2902                  */
2903
2904                 if (patch_type != MONO_PATCH_INFO_ABS) {
2905                         /* The target is in memory allocated using the code manager */
2906                         near_call = TRUE;
2907
2908                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2909                                 if (((MonoMethod*)data)->klass->image->aot_module)
2910                                         /* The callee might be an AOT method */
2911                                         near_call = FALSE;
2912                                 if (((MonoMethod*)data)->dynamic)
2913                                         /* The target is in malloc-ed memory */
2914                                         near_call = FALSE;
2915                         }
2916
2917                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2918                                 /*
2919                                  * The call might go directly to a native function without
2920                                  * the wrapper.
2921                                  */
2922                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2923                                 if (mi) {
2924                                         gconstpointer target = mono_icall_get_wrapper (mi);
2925                                         if ((((guint64)target) >> 32) != 0)
2926                                                 near_call = FALSE;
2927                                 }
2928                         }
2929                 }
2930                 else {
2931                         MonoJumpInfo *jinfo = NULL;
2932
2933                         if (cfg->abs_patches)
2934                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2935                         if (jinfo) {
2936                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2937                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2938                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2939                                                 near_call = TRUE;
2940                                         no_patch = TRUE;
2941                                 } else {
2942                                         /*
2943                                          * This is not really an optimization, but required because the
2944                                          * generic class init trampolines use R11 to pass the vtable.
2945                                          */
2946                                         near_call = TRUE;
2947                                 }
2948                         } else {
2949                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2950                                 if (info) {
2951                                         if (info->func == info->wrapper) {
2952                                                 /* No wrapper */
2953                                                 if ((((guint64)info->func) >> 32) == 0)
2954                                                         near_call = TRUE;
2955                                         }
2956                                         else {
2957                                                 /* See the comment in mono_codegen () */
2958                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2959                                                         near_call = TRUE;
2960                                         }
2961                                 }
2962                                 else if ((((guint64)data) >> 32) == 0) {
2963                                         near_call = TRUE;
2964                                         no_patch = TRUE;
2965                                 }
2966                         }
2967                 }
2968
2969                 if (cfg->method->dynamic)
2970                         /* These methods are allocated using malloc */
2971                         near_call = FALSE;
2972
2973 #ifdef MONO_ARCH_NOMAP32BIT
2974                 near_call = FALSE;
2975 #endif
2976 #if defined(__native_client__)
2977                 /* Always use near_call == TRUE for Native Client */
2978                 near_call = TRUE;
2979 #endif
2980                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2981                 if (optimize_for_xen)
2982                         near_call = FALSE;
2983
2984                 if (cfg->compile_aot) {
2985                         near_call = TRUE;
2986                         no_patch = TRUE;
2987                 }
2988
2989                 if (near_call) {
2990                         /*
2991                          * Align the call displacement to an address divisible by 4 so it does
2992                          * not span cache lines. This is required for code patching to work on SMP
2993                          * systems.
2994                          */
2995                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2996                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2997                                 amd64_padding (code, pad_size);
2998                         }
2999                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3000                         amd64_call_code (code, 0);
3001                 }
3002                 else {
3003                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3004                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3005                         amd64_call_reg (code, GP_SCRATCH_REG);
3006                 }
3007         }
3008
3009         return code;
3010 }
3011
3012 static inline guint8*
3013 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3014 {
3015 #ifdef HOST_WIN32
3016         if (win64_adjust_stack)
3017                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3018 #endif
3019         code = emit_call_body (cfg, code, patch_type, data);
3020 #ifdef HOST_WIN32
3021         if (win64_adjust_stack)
3022                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3023 #endif
3024
3025         return code;
3026 }
3027
3028 static inline int
3029 store_membase_imm_to_store_membase_reg (int opcode)
3030 {
3031         switch (opcode) {
3032         case OP_STORE_MEMBASE_IMM:
3033                 return OP_STORE_MEMBASE_REG;
3034         case OP_STOREI4_MEMBASE_IMM:
3035                 return OP_STOREI4_MEMBASE_REG;
3036         case OP_STOREI8_MEMBASE_IMM:
3037                 return OP_STOREI8_MEMBASE_REG;
3038         }
3039
3040         return -1;
3041 }
3042
3043 #ifndef DISABLE_JIT
3044
3045 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3046
3047 /*
3048  * mono_arch_peephole_pass_1:
3049  *
3050  *   Perform peephole opts which should/can be performed before local regalloc
3051  */
3052 void
3053 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3054 {
3055         MonoInst *ins, *n;
3056
3057         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3058                 MonoInst *last_ins = ins->prev;
3059
3060                 switch (ins->opcode) {
3061                 case OP_ADD_IMM:
3062                 case OP_IADD_IMM:
3063                 case OP_LADD_IMM:
3064                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3065                                 /*
3066                                  * X86_LEA is like ADD, but doesn't have the
3067                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3068                                  * its operand to 64 bit.
3069                                  */
3070                                 ins->opcode = OP_X86_LEA_MEMBASE;
3071                                 ins->inst_basereg = ins->sreg1;
3072                         }
3073                         break;
3074                 case OP_LXOR:
3075                 case OP_IXOR:
3076                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3077                                 MonoInst *ins2;
3078
3079                                 /*
3080                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3081                                  * the latter has length 2-3 instead of 6 (reverse constant
3082                                  * propagation). These instruction sequences are very common
3083                                  * in the initlocals bblock.
3084                                  */
3085                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3086                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3087                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3088                                                 ins2->sreg1 = ins->dreg;
3089                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3090                                                 /* Continue */
3091                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3092                                                 NULLIFY_INS (ins2);
3093                                                 /* Continue */
3094                                         } else {
3095                                                 break;
3096                                         }
3097                                 }
3098                         }
3099                         break;
3100                 case OP_COMPARE_IMM:
3101                 case OP_LCOMPARE_IMM:
3102                         /* OP_COMPARE_IMM (reg, 0)
3103                          * -->
3104                          * OP_AMD64_TEST_NULL (reg)
3105                          */
3106                         if (!ins->inst_imm)
3107                                 ins->opcode = OP_AMD64_TEST_NULL;
3108                         break;
3109                 case OP_ICOMPARE_IMM:
3110                         if (!ins->inst_imm)
3111                                 ins->opcode = OP_X86_TEST_NULL;
3112                         break;
3113                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3114                         /*
3115                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3116                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3117                          * -->
3118                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3119                          * OP_COMPARE_IMM reg, imm
3120                          *
3121                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3122                          */
3123                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3124                             ins->inst_basereg == last_ins->inst_destbasereg &&
3125                             ins->inst_offset == last_ins->inst_offset) {
3126                                         ins->opcode = OP_ICOMPARE_IMM;
3127                                         ins->sreg1 = last_ins->sreg1;
3128
3129                                         /* check if we can remove cmp reg,0 with test null */
3130                                         if (!ins->inst_imm)
3131                                                 ins->opcode = OP_X86_TEST_NULL;
3132                                 }
3133
3134                         break;
3135                 }
3136
3137                 mono_peephole_ins (bb, ins);
3138         }
3139 }
3140
3141 void
3142 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3143 {
3144         MonoInst *ins, *n;
3145
3146         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3147                 switch (ins->opcode) {
3148                 case OP_ICONST:
3149                 case OP_I8CONST: {
3150                         /* reg = 0 -> XOR (reg, reg) */
3151                         /* XOR sets cflags on x86, so we cant do it always */
3152                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3153                                 ins->opcode = OP_LXOR;
3154                                 ins->sreg1 = ins->dreg;
3155                                 ins->sreg2 = ins->dreg;
3156                                 /* Fall through */
3157                         } else {
3158                                 break;
3159                         }
3160                 }
3161                 case OP_LXOR:
3162                         /*
3163                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3164                          * 0 result into 64 bits.
3165                          */
3166                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3167                                 ins->opcode = OP_IXOR;
3168                         }
3169                         /* Fall through */
3170                 case OP_IXOR:
3171                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3172                                 MonoInst *ins2;
3173
3174                                 /*
3175                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3176                                  * the latter has length 2-3 instead of 6 (reverse constant
3177                                  * propagation). These instruction sequences are very common
3178                                  * in the initlocals bblock.
3179                                  */
3180                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3181                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3182                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3183                                                 ins2->sreg1 = ins->dreg;
3184                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3185                                                 /* Continue */
3186                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3187                                                 NULLIFY_INS (ins2);
3188                                                 /* Continue */
3189                                         } else {
3190                                                 break;
3191                                         }
3192                                 }
3193                         }
3194                         break;
3195                 case OP_IADD_IMM:
3196                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3197                                 ins->opcode = OP_X86_INC_REG;
3198                         break;
3199                 case OP_ISUB_IMM:
3200                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3201                                 ins->opcode = OP_X86_DEC_REG;
3202                         break;
3203                 }
3204
3205                 mono_peephole_ins (bb, ins);
3206         }
3207 }
3208
3209 #define NEW_INS(cfg,ins,dest,op) do {   \
3210                 MONO_INST_NEW ((cfg), (dest), (op)); \
3211         (dest)->cil_code = (ins)->cil_code; \
3212         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3213         } while (0)
3214
3215 /*
3216  * mono_arch_lowering_pass:
3217  *
3218  *  Converts complex opcodes into simpler ones so that each IR instruction
3219  * corresponds to one machine instruction.
3220  */
3221 void
3222 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3223 {
3224         MonoInst *ins, *n, *temp;
3225
3226         /*
3227          * FIXME: Need to add more instructions, but the current machine
3228          * description can't model some parts of the composite instructions like
3229          * cdq.
3230          */
3231         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3232                 switch (ins->opcode) {
3233                 case OP_DIV_IMM:
3234                 case OP_REM_IMM:
3235                 case OP_IDIV_IMM:
3236                 case OP_IDIV_UN_IMM:
3237                 case OP_IREM_UN_IMM:
3238                 case OP_LREM_IMM:
3239                 case OP_IREM_IMM:
3240                         mono_decompose_op_imm (cfg, bb, ins);
3241                         break;
3242                 case OP_COMPARE_IMM:
3243                 case OP_LCOMPARE_IMM:
3244                         if (!amd64_is_imm32 (ins->inst_imm)) {
3245                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3246                                 temp->inst_c0 = ins->inst_imm;
3247                                 temp->dreg = mono_alloc_ireg (cfg);
3248                                 ins->opcode = OP_COMPARE;
3249                                 ins->sreg2 = temp->dreg;
3250                         }
3251                         break;
3252 #ifndef __mono_ilp32__
3253                 case OP_LOAD_MEMBASE:
3254 #endif
3255                 case OP_LOADI8_MEMBASE:
3256 #ifndef __native_client_codegen__
3257                 /*  Don't generate memindex opcodes (to simplify */
3258                 /*  read sandboxing) */
3259                         if (!amd64_is_imm32 (ins->inst_offset)) {
3260                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3261                                 temp->inst_c0 = ins->inst_offset;
3262                                 temp->dreg = mono_alloc_ireg (cfg);
3263                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3264                                 ins->inst_indexreg = temp->dreg;
3265                         }
3266 #endif
3267                         break;
3268 #ifndef __mono_ilp32__
3269                 case OP_STORE_MEMBASE_IMM:
3270 #endif
3271                 case OP_STOREI8_MEMBASE_IMM:
3272                         if (!amd64_is_imm32 (ins->inst_imm)) {
3273                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3274                                 temp->inst_c0 = ins->inst_imm;
3275                                 temp->dreg = mono_alloc_ireg (cfg);
3276                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3277                                 ins->sreg1 = temp->dreg;
3278                         }
3279                         break;
3280 #ifdef MONO_ARCH_SIMD_INTRINSICS
3281                 case OP_EXPAND_I1: {
3282                                 int temp_reg1 = mono_alloc_ireg (cfg);
3283                                 int temp_reg2 = mono_alloc_ireg (cfg);
3284                                 int original_reg = ins->sreg1;
3285
3286                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3287                                 temp->sreg1 = original_reg;
3288                                 temp->dreg = temp_reg1;
3289
3290                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3291                                 temp->sreg1 = temp_reg1;
3292                                 temp->dreg = temp_reg2;
3293                                 temp->inst_imm = 8;
3294
3295                                 NEW_INS (cfg, ins, temp, OP_LOR);
3296                                 temp->sreg1 = temp->dreg = temp_reg2;
3297                                 temp->sreg2 = temp_reg1;
3298
3299                                 ins->opcode = OP_EXPAND_I2;
3300                                 ins->sreg1 = temp_reg2;
3301                         }
3302                         break;
3303 #endif
3304                 default:
3305                         break;
3306                 }
3307         }
3308
3309         bb->max_vreg = cfg->next_vreg;
3310 }
3311
3312 static const int
3313 branch_cc_table [] = {
3314         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3315         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3316         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3317 };
3318
3319 /* Maps CMP_... constants to X86_CC_... constants */
3320 static const int
3321 cc_table [] = {
3322         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3323         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3324 };
3325
3326 static const int
3327 cc_signed_table [] = {
3328         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3329         FALSE, FALSE, FALSE, FALSE
3330 };
3331
3332 /*#include "cprop.c"*/
3333
3334 static unsigned char*
3335 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3336 {
3337         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3338
3339         if (size == 1)
3340                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3341         else if (size == 2)
3342                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3343         return code;
3344 }
3345
3346 static unsigned char*
3347 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3348 {
3349         int sreg = tree->sreg1;
3350         int need_touch = FALSE;
3351
3352 #if defined(HOST_WIN32)
3353         need_touch = TRUE;
3354 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3355         if (!tree->flags & MONO_INST_INIT)
3356                 need_touch = TRUE;
3357 #endif
3358
3359         if (need_touch) {
3360                 guint8* br[5];
3361
3362                 /*
3363                  * Under Windows:
3364                  * If requested stack size is larger than one page,
3365                  * perform stack-touch operation
3366                  */
3367                 /*
3368                  * Generate stack probe code.
3369                  * Under Windows, it is necessary to allocate one page at a time,
3370                  * "touching" stack after each successful sub-allocation. This is
3371                  * because of the way stack growth is implemented - there is a
3372                  * guard page before the lowest stack page that is currently commited.
3373                  * Stack normally grows sequentially so OS traps access to the
3374                  * guard page and commits more pages when needed.
3375                  */
3376                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3377                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3378
3379                 br[2] = code; /* loop */
3380                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3381                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3382                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3383                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3384                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3385                 amd64_patch (br[3], br[2]);
3386                 amd64_test_reg_reg (code, sreg, sreg);
3387                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3388                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3389
3390                 br[1] = code; x86_jump8 (code, 0);
3391
3392                 amd64_patch (br[0], code);
3393                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3394                 amd64_patch (br[1], code);
3395                 amd64_patch (br[4], code);
3396         }
3397         else
3398                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3399
3400         if (tree->flags & MONO_INST_INIT) {
3401                 int offset = 0;
3402                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3403                         amd64_push_reg (code, AMD64_RAX);
3404                         offset += 8;
3405                 }
3406                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3407                         amd64_push_reg (code, AMD64_RCX);
3408                         offset += 8;
3409                 }
3410                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3411                         amd64_push_reg (code, AMD64_RDI);
3412                         offset += 8;
3413                 }
3414
3415                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3416                 if (sreg != AMD64_RCX)
3417                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3418                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3419
3420                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3421                 if (cfg->param_area)
3422                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3423                 amd64_cld (code);
3424 #if defined(__default_codegen__)
3425                 amd64_prefix (code, X86_REP_PREFIX);
3426                 amd64_stosl (code);
3427 #elif defined(__native_client_codegen__)
3428                 /* NaCl stos pseudo-instruction */
3429                 amd64_codegen_pre(code);
3430                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3431                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3432                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3433                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3434                 amd64_prefix (code, X86_REP_PREFIX);
3435                 amd64_stosl (code);
3436                 amd64_codegen_post(code);
3437 #endif /* __native_client_codegen__ */
3438
3439                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3440                         amd64_pop_reg (code, AMD64_RDI);
3441                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3442                         amd64_pop_reg (code, AMD64_RCX);
3443                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3444                         amd64_pop_reg (code, AMD64_RAX);
3445         }
3446         return code;
3447 }
3448
3449 static guint8*
3450 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3451 {
3452         CallInfo *cinfo;
3453         guint32 quad;
3454
3455         /* Move return value to the target register */
3456         /* FIXME: do this in the local reg allocator */
3457         switch (ins->opcode) {
3458         case OP_CALL:
3459         case OP_CALL_REG:
3460         case OP_CALL_MEMBASE:
3461         case OP_LCALL:
3462         case OP_LCALL_REG:
3463         case OP_LCALL_MEMBASE:
3464                 g_assert (ins->dreg == AMD64_RAX);
3465                 break;
3466         case OP_FCALL:
3467         case OP_FCALL_REG:
3468         case OP_FCALL_MEMBASE:
3469                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3470                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3471                 }
3472                 else {
3473                         if (ins->dreg != AMD64_XMM0)
3474                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3475                 }
3476                 break;
3477         case OP_VCALL:
3478         case OP_VCALL_REG:
3479         case OP_VCALL_MEMBASE:
3480         case OP_VCALL2:
3481         case OP_VCALL2_REG:
3482         case OP_VCALL2_MEMBASE:
3483                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3484                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3485                         MonoInst *loc = cfg->arch.vret_addr_loc;
3486
3487                         /* Load the destination address */
3488                         g_assert (loc->opcode == OP_REGOFFSET);
3489                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3490
3491                         for (quad = 0; quad < 2; quad ++) {
3492                                 switch (cinfo->ret.pair_storage [quad]) {
3493                                 case ArgInIReg:
3494                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3495                                         break;
3496                                 case ArgInFloatSSEReg:
3497                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3498                                         break;
3499                                 case ArgInDoubleSSEReg:
3500                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3501                                         break;
3502                                 case ArgNone:
3503                                         break;
3504                                 default:
3505                                         NOT_IMPLEMENTED;
3506                                 }
3507                         }
3508                 }
3509                 break;
3510         }
3511
3512         return code;
3513 }
3514
3515 #endif /* DISABLE_JIT */
3516
3517 #ifdef __APPLE__
3518 static int tls_gs_offset;
3519 #endif
3520
3521 gboolean
3522 mono_amd64_have_tls_get (void)
3523 {
3524 #ifdef __APPLE__
3525         static gboolean have_tls_get = FALSE;
3526         static gboolean inited = FALSE;
3527         guint8 *ins;
3528
3529         if (inited)
3530                 return have_tls_get;
3531
3532         ins = (guint8*)pthread_getspecific;
3533
3534         /*
3535          * We're looking for these two instructions:
3536          *
3537          * mov    %gs:[offset](,%rdi,8),%rax
3538          * retq
3539          */
3540         have_tls_get = ins [0] == 0x65 &&
3541                        ins [1] == 0x48 &&
3542                        ins [2] == 0x8b &&
3543                        ins [3] == 0x04 &&
3544                        ins [4] == 0xfd &&
3545                        ins [6] == 0x00 &&
3546                        ins [7] == 0x00 &&
3547                        ins [8] == 0x00 &&
3548                        ins [9] == 0xc3;
3549
3550         inited = TRUE;
3551
3552         tls_gs_offset = ins[5];
3553
3554         return have_tls_get;
3555 #else
3556         return TRUE;
3557 #endif
3558 }
3559
3560 int
3561 mono_amd64_get_tls_gs_offset (void)
3562 {
3563 #ifdef TARGET_OSX
3564         return tls_gs_offset;
3565 #else
3566         g_assert_not_reached ();
3567         return -1;
3568 #endif
3569 }
3570
3571 /*
3572  * mono_amd64_emit_tls_get:
3573  * @code: buffer to store code to
3574  * @dreg: hard register where to place the result
3575  * @tls_offset: offset info
3576  *
3577  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3578  * the dreg register the item in the thread local storage identified
3579  * by tls_offset.
3580  *
3581  * Returns: a pointer to the end of the stored code
3582  */
3583 guint8*
3584 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3585 {
3586 #ifdef HOST_WIN32
3587         if (tls_offset < 64) {
3588                 x86_prefix (code, X86_GS_PREFIX);
3589                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3590         } else {
3591                 guint8 *buf [16];
3592
3593                 g_assert (tls_offset < 0x440);
3594                 /* Load TEB->TlsExpansionSlots */
3595                 x86_prefix (code, X86_GS_PREFIX);
3596                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3597                 amd64_test_reg_reg (code, dreg, dreg);
3598                 buf [0] = code;
3599                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3600                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3601                 amd64_patch (buf [0], code);
3602         }
3603 #elif defined(__APPLE__)
3604         x86_prefix (code, X86_GS_PREFIX);
3605         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3606 #else
3607         if (optimize_for_xen) {
3608                 x86_prefix (code, X86_FS_PREFIX);
3609                 amd64_mov_reg_mem (code, dreg, 0, 8);
3610                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3611         } else {
3612                 x86_prefix (code, X86_FS_PREFIX);
3613                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3614         }
3615 #endif
3616         return code;
3617 }
3618
3619 static guint8*
3620 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3621 {
3622         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3623 #ifdef TARGET_OSX
3624         if (dreg != offset_reg)
3625                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3626         amd64_prefix (code, X86_GS_PREFIX);
3627         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3628 #elif defined(__linux__)
3629         int tmpreg = -1;
3630
3631         if (dreg == offset_reg) {
3632                 /* Use a temporary reg by saving it to the redzone */
3633                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3634                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3635                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3636                 offset_reg = tmpreg;
3637         }
3638         x86_prefix (code, X86_FS_PREFIX);
3639         amd64_mov_reg_mem (code, dreg, 0, 8);
3640         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3641         if (tmpreg != -1)
3642                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3643 #else
3644         g_assert_not_reached ();
3645 #endif
3646         return code;
3647 }
3648
3649 static guint8*
3650 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3651 {
3652 #ifdef HOST_WIN32
3653         g_assert_not_reached ();
3654 #elif defined(__APPLE__)
3655         x86_prefix (code, X86_GS_PREFIX);
3656         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3657 #else
3658         g_assert (!optimize_for_xen);
3659         x86_prefix (code, X86_FS_PREFIX);
3660         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3661 #endif
3662         return code;
3663 }
3664
3665 static guint8*
3666 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3667 {
3668         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3669 #ifdef HOST_WIN32
3670         g_assert_not_reached ();
3671 #elif defined(__APPLE__)
3672         x86_prefix (code, X86_GS_PREFIX);
3673         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3674 #else
3675         x86_prefix (code, X86_FS_PREFIX);
3676         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3677 #endif
3678         return code;
3679 }
3680
3681  /*
3682  * mono_arch_translate_tls_offset:
3683  *
3684  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3685  */
3686 int
3687 mono_arch_translate_tls_offset (int offset)
3688 {
3689 #ifdef __APPLE__
3690         return tls_gs_offset + (offset * 8);
3691 #else
3692         return offset;
3693 #endif
3694 }
3695
3696 /*
3697  * emit_setup_lmf:
3698  *
3699  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3700  */
3701 static guint8*
3702 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3703 {
3704         /*
3705          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3706          */
3707         /*
3708          * sp is saved right before calls but we need to save it here too so
3709          * async stack walks would work.
3710          */
3711         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3712         /* Save rbp */
3713         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3714         if (cfg->arch.omit_fp && cfa_offset != -1)
3715                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3716
3717         /* These can't contain refs */
3718         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3719         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3720         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3721         /* These are handled automatically by the stack marking code */
3722         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3723
3724         return code;
3725 }
3726
3727 #define REAL_PRINT_REG(text,reg) \
3728 mono_assert (reg >= 0); \
3729 amd64_push_reg (code, AMD64_RAX); \
3730 amd64_push_reg (code, AMD64_RDX); \
3731 amd64_push_reg (code, AMD64_RCX); \
3732 amd64_push_reg (code, reg); \
3733 amd64_push_imm (code, reg); \
3734 amd64_push_imm (code, text " %d %p\n"); \
3735 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3736 amd64_call_reg (code, AMD64_RAX); \
3737 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3738 amd64_pop_reg (code, AMD64_RCX); \
3739 amd64_pop_reg (code, AMD64_RDX); \
3740 amd64_pop_reg (code, AMD64_RAX);
3741
3742 /* benchmark and set based on cpu */
3743 #define LOOP_ALIGNMENT 8
3744 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3745
3746 #ifndef DISABLE_JIT
3747 void
3748 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3749 {
3750         MonoInst *ins;
3751         MonoCallInst *call;
3752         guint offset;
3753         guint8 *code = cfg->native_code + cfg->code_len;
3754         MonoInst *last_ins = NULL;
3755         guint last_offset = 0;
3756         int max_len;
3757
3758         /* Fix max_offset estimate for each successor bb */
3759         if (cfg->opt & MONO_OPT_BRANCH) {
3760                 int current_offset = cfg->code_len;
3761                 MonoBasicBlock *current_bb;
3762                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3763                         current_bb->max_offset = current_offset;
3764                         current_offset += current_bb->max_length;
3765                 }
3766         }
3767
3768         if (cfg->opt & MONO_OPT_LOOP) {
3769                 int pad, align = LOOP_ALIGNMENT;
3770                 /* set alignment depending on cpu */
3771                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3772                         pad = align - pad;
3773                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3774                         amd64_padding (code, pad);
3775                         cfg->code_len += pad;
3776                         bb->native_offset = cfg->code_len;
3777                 }
3778         }
3779
3780 #if defined(__native_client_codegen__)
3781         /* For Native Client, all indirect call/jump targets must be */
3782         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3783         /* indirectly as well.                                       */
3784         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3785                                       (bb->flags & BB_EXCEPTION_HANDLER);
3786
3787         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3788                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3789                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3790                 cfg->code_len += pad;
3791                 bb->native_offset = cfg->code_len;
3792         }
3793 #endif  /*__native_client_codegen__*/
3794
3795         if (cfg->verbose_level > 2)
3796                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3797
3798         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3799                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3800                 g_assert (!cfg->compile_aot);
3801
3802                 cov->data [bb->dfn].cil_code = bb->cil_code;
3803                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3804                 /* this is not thread save, but good enough */
3805                 amd64_inc_membase (code, AMD64_R11, 0);
3806         }
3807
3808         offset = code - cfg->native_code;
3809
3810         mono_debug_open_block (cfg, bb, offset);
3811
3812     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3813                 x86_breakpoint (code);
3814
3815         MONO_BB_FOR_EACH_INS (bb, ins) {
3816                 offset = code - cfg->native_code;
3817
3818                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3819
3820 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3821
3822                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3823                         cfg->code_size *= 2;
3824                         cfg->native_code = mono_realloc_native_code(cfg);
3825                         code = cfg->native_code + offset;
3826                         cfg->stat_code_reallocs++;
3827                 }
3828
3829                 if (cfg->debug_info)
3830                         mono_debug_record_line_number (cfg, ins, offset);
3831
3832                 switch (ins->opcode) {
3833                 case OP_BIGMUL:
3834                         amd64_mul_reg (code, ins->sreg2, TRUE);
3835                         break;
3836                 case OP_BIGMUL_UN:
3837                         amd64_mul_reg (code, ins->sreg2, FALSE);
3838                         break;
3839                 case OP_X86_SETEQ_MEMBASE:
3840                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3841                         break;
3842                 case OP_STOREI1_MEMBASE_IMM:
3843                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3844                         break;
3845                 case OP_STOREI2_MEMBASE_IMM:
3846                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3847                         break;
3848                 case OP_STOREI4_MEMBASE_IMM:
3849                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3850                         break;
3851                 case OP_STOREI1_MEMBASE_REG:
3852                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3853                         break;
3854                 case OP_STOREI2_MEMBASE_REG:
3855                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3856                         break;
3857                 /* In AMD64 NaCl, pointers are 4 bytes, */
3858                 /*  so STORE_* != STOREI8_*. Likewise below. */
3859                 case OP_STORE_MEMBASE_REG:
3860                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3861                         break;
3862                 case OP_STOREI8_MEMBASE_REG:
3863                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3864                         break;
3865                 case OP_STOREI4_MEMBASE_REG:
3866                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3867                         break;
3868                 case OP_STORE_MEMBASE_IMM:
3869 #ifndef __native_client_codegen__
3870                         /* In NaCl, this could be a PCONST type, which could */
3871                         /* mean a pointer type was copied directly into the  */
3872                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3873                         /* the value would be 0x00000000FFFFFFFF which is    */
3874                         /* not proper for an imm32 unless you cast it.       */
3875                         g_assert (amd64_is_imm32 (ins->inst_imm));
3876 #endif
3877                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3878                         break;
3879                 case OP_STOREI8_MEMBASE_IMM:
3880                         g_assert (amd64_is_imm32 (ins->inst_imm));
3881                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3882                         break;
3883                 case OP_LOAD_MEM:
3884 #ifdef __mono_ilp32__
3885                         /* In ILP32, pointers are 4 bytes, so separate these */
3886                         /* cases, use literal 8 below where we really want 8 */
3887                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3888                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3889                         break;
3890 #endif
3891                 case OP_LOADI8_MEM:
3892                         // FIXME: Decompose this earlier
3893                         if (amd64_is_imm32 (ins->inst_imm))
3894                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3895                         else {
3896                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3897                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3898                         }
3899                         break;
3900                 case OP_LOADI4_MEM:
3901                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3902                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3903                         break;
3904                 case OP_LOADU4_MEM:
3905                         // FIXME: Decompose this earlier
3906                         if (amd64_is_imm32 (ins->inst_imm))
3907                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3908                         else {
3909                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3910                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3911                         }
3912                         break;
3913                 case OP_LOADU1_MEM:
3914                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3915                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3916                         break;
3917                 case OP_LOADU2_MEM:
3918                         /* For NaCl, pointers are 4 bytes, so separate these */
3919                         /* cases, use literal 8 below where we really want 8 */
3920                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3921                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3922                         break;
3923                 case OP_LOAD_MEMBASE:
3924                         g_assert (amd64_is_imm32 (ins->inst_offset));
3925                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3926                         break;
3927                 case OP_LOADI8_MEMBASE:
3928                         /* Use literal 8 instead of sizeof pointer or */
3929                         /* register, we really want 8 for this opcode */
3930                         g_assert (amd64_is_imm32 (ins->inst_offset));
3931                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3932                         break;
3933                 case OP_LOADI4_MEMBASE:
3934                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3935                         break;
3936                 case OP_LOADU4_MEMBASE:
3937                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3938                         break;
3939                 case OP_LOADU1_MEMBASE:
3940                         /* The cpu zero extends the result into 64 bits */
3941                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3942                         break;
3943                 case OP_LOADI1_MEMBASE:
3944                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3945                         break;
3946                 case OP_LOADU2_MEMBASE:
3947                         /* The cpu zero extends the result into 64 bits */
3948                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3949                         break;
3950                 case OP_LOADI2_MEMBASE:
3951                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3952                         break;
3953                 case OP_AMD64_LOADI8_MEMINDEX:
3954                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3955                         break;
3956                 case OP_LCONV_TO_I1:
3957                 case OP_ICONV_TO_I1:
3958                 case OP_SEXT_I1:
3959                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3960                         break;
3961                 case OP_LCONV_TO_I2:
3962                 case OP_ICONV_TO_I2:
3963                 case OP_SEXT_I2:
3964                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3965                         break;
3966                 case OP_LCONV_TO_U1:
3967                 case OP_ICONV_TO_U1:
3968                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3969                         break;
3970                 case OP_LCONV_TO_U2:
3971                 case OP_ICONV_TO_U2:
3972                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3973                         break;
3974                 case OP_ZEXT_I4:
3975                         /* Clean out the upper word */
3976                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3977                         break;
3978                 case OP_SEXT_I4:
3979                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3980                         break;
3981                 case OP_COMPARE:
3982                 case OP_LCOMPARE:
3983                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3984                         break;
3985                 case OP_COMPARE_IMM:
3986 #if defined(__mono_ilp32__)
3987                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3988                         g_assert (amd64_is_imm32 (ins->inst_imm));
3989                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3990                         break;
3991 #endif
3992                 case OP_LCOMPARE_IMM:
3993                         g_assert (amd64_is_imm32 (ins->inst_imm));
3994                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3995                         break;
3996                 case OP_X86_COMPARE_REG_MEMBASE:
3997                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3998                         break;
3999                 case OP_X86_TEST_NULL:
4000                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4001                         break;
4002                 case OP_AMD64_TEST_NULL:
4003                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4004                         break;
4005
4006                 case OP_X86_ADD_REG_MEMBASE:
4007                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4008                         break;
4009                 case OP_X86_SUB_REG_MEMBASE:
4010                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4011                         break;
4012                 case OP_X86_AND_REG_MEMBASE:
4013                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4014                         break;
4015                 case OP_X86_OR_REG_MEMBASE:
4016                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4017                         break;
4018                 case OP_X86_XOR_REG_MEMBASE:
4019                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4020                         break;
4021
4022                 case OP_X86_ADD_MEMBASE_IMM:
4023                         /* FIXME: Make a 64 version too */
4024                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4025                         break;
4026                 case OP_X86_SUB_MEMBASE_IMM:
4027                         g_assert (amd64_is_imm32 (ins->inst_imm));
4028                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4029                         break;
4030                 case OP_X86_AND_MEMBASE_IMM:
4031                         g_assert (amd64_is_imm32 (ins->inst_imm));
4032                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4033                         break;
4034                 case OP_X86_OR_MEMBASE_IMM:
4035                         g_assert (amd64_is_imm32 (ins->inst_imm));
4036                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4037                         break;
4038                 case OP_X86_XOR_MEMBASE_IMM:
4039                         g_assert (amd64_is_imm32 (ins->inst_imm));
4040                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4041                         break;
4042                 case OP_X86_ADD_MEMBASE_REG:
4043                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4044                         break;
4045                 case OP_X86_SUB_MEMBASE_REG:
4046                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4047                         break;
4048                 case OP_X86_AND_MEMBASE_REG:
4049                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4050                         break;
4051                 case OP_X86_OR_MEMBASE_REG:
4052                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4053                         break;
4054                 case OP_X86_XOR_MEMBASE_REG:
4055                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4056                         break;
4057                 case OP_X86_INC_MEMBASE:
4058                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4059                         break;
4060                 case OP_X86_INC_REG:
4061                         amd64_inc_reg_size (code, ins->dreg, 4);
4062                         break;
4063                 case OP_X86_DEC_MEMBASE:
4064                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4065                         break;
4066                 case OP_X86_DEC_REG:
4067                         amd64_dec_reg_size (code, ins->dreg, 4);
4068                         break;
4069                 case OP_X86_MUL_REG_MEMBASE:
4070                 case OP_X86_MUL_MEMBASE_REG:
4071                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4072                         break;
4073                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4074                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4075                         break;
4076                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4077                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4078                         break;
4079                 case OP_AMD64_COMPARE_MEMBASE_REG:
4080                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4081                         break;
4082                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4083                         g_assert (amd64_is_imm32 (ins->inst_imm));
4084                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4085                         break;
4086                 case OP_X86_COMPARE_MEMBASE8_IMM:
4087                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4088                         break;
4089                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4090                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4091                         break;
4092                 case OP_AMD64_COMPARE_REG_MEMBASE:
4093                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4094                         break;
4095
4096                 case OP_AMD64_ADD_REG_MEMBASE:
4097                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4098                         break;
4099                 case OP_AMD64_SUB_REG_MEMBASE:
4100                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4101                         break;
4102                 case OP_AMD64_AND_REG_MEMBASE:
4103                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4104                         break;
4105                 case OP_AMD64_OR_REG_MEMBASE:
4106                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4107                         break;
4108                 case OP_AMD64_XOR_REG_MEMBASE:
4109                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4110                         break;
4111
4112                 case OP_AMD64_ADD_MEMBASE_REG:
4113                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4114                         break;
4115                 case OP_AMD64_SUB_MEMBASE_REG:
4116                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4117                         break;
4118                 case OP_AMD64_AND_MEMBASE_REG:
4119                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4120                         break;
4121                 case OP_AMD64_OR_MEMBASE_REG:
4122                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4123                         break;
4124                 case OP_AMD64_XOR_MEMBASE_REG:
4125                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4126                         break;
4127
4128                 case OP_AMD64_ADD_MEMBASE_IMM:
4129                         g_assert (amd64_is_imm32 (ins->inst_imm));
4130                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4131                         break;
4132                 case OP_AMD64_SUB_MEMBASE_IMM:
4133                         g_assert (amd64_is_imm32 (ins->inst_imm));
4134                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4135                         break;
4136                 case OP_AMD64_AND_MEMBASE_IMM:
4137                         g_assert (amd64_is_imm32 (ins->inst_imm));
4138                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4139                         break;
4140                 case OP_AMD64_OR_MEMBASE_IMM:
4141                         g_assert (amd64_is_imm32 (ins->inst_imm));
4142                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4143                         break;
4144                 case OP_AMD64_XOR_MEMBASE_IMM:
4145                         g_assert (amd64_is_imm32 (ins->inst_imm));
4146                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4147                         break;
4148
4149                 case OP_BREAK:
4150                         amd64_breakpoint (code);
4151                         break;
4152                 case OP_RELAXED_NOP:
4153                         x86_prefix (code, X86_REP_PREFIX);
4154                         x86_nop (code);
4155                         break;
4156                 case OP_HARD_NOP:
4157                         x86_nop (code);
4158                         break;
4159                 case OP_NOP:
4160                 case OP_DUMMY_USE:
4161                 case OP_DUMMY_STORE:
4162                 case OP_DUMMY_ICONST:
4163                 case OP_DUMMY_R8CONST:
4164                 case OP_NOT_REACHED:
4165                 case OP_NOT_NULL:
4166                         break;
4167                 case OP_IL_SEQ_POINT:
4168                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4169                         break;
4170                 case OP_SEQ_POINT: {
4171                         int i;
4172
4173                         /*
4174                          * Read from the single stepping trigger page. This will cause a
4175                          * SIGSEGV when single stepping is enabled.
4176                          * We do this _before_ the breakpoint, so single stepping after
4177                          * a breakpoint is hit will step to the next IL offset.
4178                          */
4179                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4180                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4181
4182                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4183                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4184                         }
4185
4186                         /*
4187                          * This is the address which is saved in seq points,
4188                          */
4189                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4190
4191                         if (cfg->compile_aot) {
4192                                 guint32 offset = code - cfg->native_code;
4193                                 guint32 val;
4194                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4195
4196                                 /* Load info var */
4197                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4198                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4199                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4200                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4201                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4202                         } else {
4203                                 /*
4204                                  * A placeholder for a possible breakpoint inserted by
4205                                  * mono_arch_set_breakpoint ().
4206                                  */
4207                                 for (i = 0; i < breakpoint_size; ++i)
4208                                         x86_nop (code);
4209                         }
4210                         /*
4211                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4212                          * to another IL offset.
4213                          */
4214                         x86_nop (code);
4215                         break;
4216                 }
4217                 case OP_ADDCC:
4218                 case OP_LADDCC:
4219                 case OP_LADD:
4220                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4221                         break;
4222                 case OP_ADC:
4223                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4224                         break;
4225                 case OP_ADD_IMM:
4226                 case OP_LADD_IMM:
4227                         g_assert (amd64_is_imm32 (ins->inst_imm));
4228                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4229                         break;
4230                 case OP_ADC_IMM:
4231                         g_assert (amd64_is_imm32 (ins->inst_imm));
4232                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4233                         break;
4234                 case OP_SUBCC:
4235                 case OP_LSUBCC:
4236                 case OP_LSUB:
4237                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4238                         break;
4239                 case OP_SBB:
4240                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4241                         break;
4242                 case OP_SUB_IMM:
4243                 case OP_LSUB_IMM:
4244                         g_assert (amd64_is_imm32 (ins->inst_imm));
4245                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4246                         break;
4247                 case OP_SBB_IMM:
4248                         g_assert (amd64_is_imm32 (ins->inst_imm));
4249                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4250                         break;
4251                 case OP_LAND:
4252                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4253                         break;
4254                 case OP_AND_IMM:
4255                 case OP_LAND_IMM:
4256                         g_assert (amd64_is_imm32 (ins->inst_imm));
4257                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4258                         break;
4259                 case OP_LMUL:
4260                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4261                         break;
4262                 case OP_MUL_IMM:
4263                 case OP_LMUL_IMM:
4264                 case OP_IMUL_IMM: {
4265                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4266
4267                         switch (ins->inst_imm) {
4268                         case 2:
4269                                 /* MOV r1, r2 */
4270                                 /* ADD r1, r1 */
4271                                 if (ins->dreg != ins->sreg1)
4272                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4273                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4274                                 break;
4275                         case 3:
4276                                 /* LEA r1, [r2 + r2*2] */
4277                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4278                                 break;
4279                         case 5:
4280                                 /* LEA r1, [r2 + r2*4] */
4281                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4282                                 break;
4283                         case 6:
4284                                 /* LEA r1, [r2 + r2*2] */
4285                                 /* ADD r1, r1          */
4286                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4287                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4288                                 break;
4289                         case 9:
4290                                 /* LEA r1, [r2 + r2*8] */
4291                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4292                                 break;
4293                         case 10:
4294                                 /* LEA r1, [r2 + r2*4] */
4295                                 /* ADD r1, r1          */
4296                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4297                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4298                                 break;
4299                         case 12:
4300                                 /* LEA r1, [r2 + r2*2] */
4301                                 /* SHL r1, 2           */
4302                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4303                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4304                                 break;
4305                         case 25:
4306                                 /* LEA r1, [r2 + r2*4] */
4307                                 /* LEA r1, [r1 + r1*4] */
4308                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4309                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4310                                 break;
4311                         case 100:
4312                                 /* LEA r1, [r2 + r2*4] */
4313                                 /* SHL r1, 2           */
4314                                 /* LEA r1, [r1 + r1*4] */
4315                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4316                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4317                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4318                                 break;
4319                         default:
4320                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4321                                 break;
4322                         }
4323                         break;
4324                 }
4325                 case OP_LDIV:
4326                 case OP_LREM:
4327 #if defined( __native_client_codegen__ )
4328                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4329                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4330 #endif
4331                         /* Regalloc magic makes the div/rem cases the same */
4332                         if (ins->sreg2 == AMD64_RDX) {
4333                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4334                                 amd64_cdq (code);
4335                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4336                         } else {
4337                                 amd64_cdq (code);
4338                                 amd64_div_reg (code, ins->sreg2, TRUE);
4339                         }
4340                         break;
4341                 case OP_LDIV_UN:
4342                 case OP_LREM_UN:
4343 #if defined( __native_client_codegen__ )
4344                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4345                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4346 #endif
4347                         if (ins->sreg2 == AMD64_RDX) {
4348                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4349                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4350                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4351                         } else {
4352                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4353                                 amd64_div_reg (code, ins->sreg2, FALSE);
4354                         }
4355                         break;
4356                 case OP_IDIV:
4357                 case OP_IREM:
4358 #if defined( __native_client_codegen__ )
4359                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4360                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4361 #endif
4362                         if (ins->sreg2 == AMD64_RDX) {
4363                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4364                                 amd64_cdq_size (code, 4);
4365                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4366                         } else {
4367                                 amd64_cdq_size (code, 4);
4368                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4369                         }
4370                         break;
4371                 case OP_IDIV_UN:
4372                 case OP_IREM_UN:
4373 #if defined( __native_client_codegen__ )
4374                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4375                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4376 #endif
4377                         if (ins->sreg2 == AMD64_RDX) {
4378                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4379                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4380                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4381                         } else {
4382                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4383                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4384                         }
4385                         break;
4386                 case OP_LMUL_OVF:
4387                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4388                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4389                         break;
4390                 case OP_LOR:
4391                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4392                         break;
4393                 case OP_OR_IMM:
4394                 case OP_LOR_IMM:
4395                         g_assert (amd64_is_imm32 (ins->inst_imm));
4396                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4397                         break;
4398                 case OP_LXOR:
4399                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4400                         break;
4401                 case OP_XOR_IMM:
4402                 case OP_LXOR_IMM:
4403                         g_assert (amd64_is_imm32 (ins->inst_imm));
4404                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4405                         break;
4406                 case OP_LSHL:
4407                         g_assert (ins->sreg2 == AMD64_RCX);
4408                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4409                         break;
4410                 case OP_LSHR:
4411                         g_assert (ins->sreg2 == AMD64_RCX);
4412                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4413                         break;
4414                 case OP_SHR_IMM:
4415                         g_assert (amd64_is_imm32 (ins->inst_imm));
4416                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4417                         break;
4418                 case OP_LSHR_IMM:
4419                         g_assert (amd64_is_imm32 (ins->inst_imm));
4420                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4421                         break;
4422                 case OP_SHR_UN_IMM:
4423                         g_assert (amd64_is_imm32 (ins->inst_imm));
4424                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4425                         break;
4426                 case OP_LSHR_UN_IMM:
4427                         g_assert (amd64_is_imm32 (ins->inst_imm));
4428                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4429                         break;
4430                 case OP_LSHR_UN:
4431                         g_assert (ins->sreg2 == AMD64_RCX);
4432                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4433                         break;
4434                 case OP_SHL_IMM:
4435                         g_assert (amd64_is_imm32 (ins->inst_imm));
4436                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4437                         break;
4438                 case OP_LSHL_IMM:
4439                         g_assert (amd64_is_imm32 (ins->inst_imm));
4440                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4441                         break;
4442
4443                 case OP_IADDCC:
4444                 case OP_IADD:
4445                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4446                         break;
4447                 case OP_IADC:
4448                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4449                         break;
4450                 case OP_IADD_IMM:
4451                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4452                         break;
4453                 case OP_IADC_IMM:
4454                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4455                         break;
4456                 case OP_ISUBCC:
4457                 case OP_ISUB:
4458                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4459                         break;
4460                 case OP_ISBB:
4461                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4462                         break;
4463                 case OP_ISUB_IMM:
4464                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4465                         break;
4466                 case OP_ISBB_IMM:
4467                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4468                         break;
4469                 case OP_IAND:
4470                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4471                         break;
4472                 case OP_IAND_IMM:
4473                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4474                         break;
4475                 case OP_IOR:
4476                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4477                         break;
4478                 case OP_IOR_IMM:
4479                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4480                         break;
4481                 case OP_IXOR:
4482                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4483                         break;
4484                 case OP_IXOR_IMM:
4485                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4486                         break;
4487                 case OP_INEG:
4488                         amd64_neg_reg_size (code, ins->sreg1, 4);
4489                         break;
4490                 case OP_INOT:
4491                         amd64_not_reg_size (code, ins->sreg1, 4);
4492                         break;
4493                 case OP_ISHL:
4494                         g_assert (ins->sreg2 == AMD64_RCX);
4495                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4496                         break;
4497                 case OP_ISHR:
4498                         g_assert (ins->sreg2 == AMD64_RCX);
4499                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4500                         break;
4501                 case OP_ISHR_IMM:
4502                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4503                         break;
4504                 case OP_ISHR_UN_IMM:
4505                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4506                         break;
4507                 case OP_ISHR_UN:
4508                         g_assert (ins->sreg2 == AMD64_RCX);
4509                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4510                         break;
4511                 case OP_ISHL_IMM:
4512                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4513                         break;
4514                 case OP_IMUL:
4515                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4516                         break;
4517                 case OP_IMUL_OVF:
4518                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4519                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4520                         break;
4521                 case OP_IMUL_OVF_UN:
4522                 case OP_LMUL_OVF_UN: {
4523                         /* the mul operation and the exception check should most likely be split */
4524                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4525                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4526                         /*g_assert (ins->sreg2 == X86_EAX);
4527                         g_assert (ins->dreg == X86_EAX);*/
4528                         if (ins->sreg2 == X86_EAX) {
4529                                 non_eax_reg = ins->sreg1;
4530                         } else if (ins->sreg1 == X86_EAX) {
4531                                 non_eax_reg = ins->sreg2;
4532                         } else {
4533                                 /* no need to save since we're going to store to it anyway */
4534                                 if (ins->dreg != X86_EAX) {
4535                                         saved_eax = TRUE;
4536                                         amd64_push_reg (code, X86_EAX);
4537                                 }
4538                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4539                                 non_eax_reg = ins->sreg2;
4540                         }
4541                         if (ins->dreg == X86_EDX) {
4542                                 if (!saved_eax) {
4543                                         saved_eax = TRUE;
4544                                         amd64_push_reg (code, X86_EAX);
4545                                 }
4546                         } else {
4547                                 saved_edx = TRUE;
4548                                 amd64_push_reg (code, X86_EDX);
4549                         }
4550                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4551                         /* save before the check since pop and mov don't change the flags */
4552                         if (ins->dreg != X86_EAX)
4553                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4554                         if (saved_edx)
4555                                 amd64_pop_reg (code, X86_EDX);
4556                         if (saved_eax)
4557                                 amd64_pop_reg (code, X86_EAX);
4558                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4559                         break;
4560                 }
4561                 case OP_ICOMPARE:
4562                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4563                         break;
4564                 case OP_ICOMPARE_IMM:
4565                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4566                         break;
4567                 case OP_IBEQ:
4568                 case OP_IBLT:
4569                 case OP_IBGT:
4570                 case OP_IBGE:
4571                 case OP_IBLE:
4572                 case OP_LBEQ:
4573                 case OP_LBLT:
4574                 case OP_LBGT:
4575                 case OP_LBGE:
4576                 case OP_LBLE:
4577                 case OP_IBNE_UN:
4578                 case OP_IBLT_UN:
4579                 case OP_IBGT_UN:
4580                 case OP_IBGE_UN:
4581                 case OP_IBLE_UN:
4582                 case OP_LBNE_UN:
4583                 case OP_LBLT_UN:
4584                 case OP_LBGT_UN:
4585                 case OP_LBGE_UN:
4586                 case OP_LBLE_UN:
4587                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4588                         break;
4589
4590                 case OP_CMOV_IEQ:
4591                 case OP_CMOV_IGE:
4592                 case OP_CMOV_IGT:
4593                 case OP_CMOV_ILE:
4594                 case OP_CMOV_ILT:
4595                 case OP_CMOV_INE_UN:
4596                 case OP_CMOV_IGE_UN:
4597                 case OP_CMOV_IGT_UN:
4598                 case OP_CMOV_ILE_UN:
4599                 case OP_CMOV_ILT_UN:
4600                 case OP_CMOV_LEQ:
4601                 case OP_CMOV_LGE:
4602                 case OP_CMOV_LGT:
4603                 case OP_CMOV_LLE:
4604                 case OP_CMOV_LLT:
4605                 case OP_CMOV_LNE_UN:
4606                 case OP_CMOV_LGE_UN:
4607                 case OP_CMOV_LGT_UN:
4608                 case OP_CMOV_LLE_UN:
4609                 case OP_CMOV_LLT_UN:
4610                         g_assert (ins->dreg == ins->sreg1);
4611                         /* This needs to operate on 64 bit values */
4612                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4613                         break;
4614
4615                 case OP_LNOT:
4616                         amd64_not_reg (code, ins->sreg1);
4617                         break;
4618                 case OP_LNEG:
4619                         amd64_neg_reg (code, ins->sreg1);
4620                         break;
4621
4622                 case OP_ICONST:
4623                 case OP_I8CONST:
4624                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4625                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4626                         else
4627                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4628                         break;
4629                 case OP_AOTCONST:
4630                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4631                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4632                         break;
4633                 case OP_JUMP_TABLE:
4634                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4635                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4636                         break;
4637                 case OP_MOVE:
4638                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4639                         break;
4640                 case OP_AMD64_SET_XMMREG_R4: {
4641                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4642                         break;
4643                 }
4644                 case OP_AMD64_SET_XMMREG_R8: {
4645                         if (ins->dreg != ins->sreg1)
4646                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4647                         break;
4648                 }
4649                 case OP_TAILCALL: {
4650                         MonoCallInst *call = (MonoCallInst*)ins;
4651                         int i, save_area_offset;
4652
4653                         g_assert (!cfg->method->save_lmf);
4654
4655                         /* Restore callee saved registers */
4656                         save_area_offset = cfg->arch.reg_save_area_offset;
4657                         for (i = 0; i < AMD64_NREG; ++i)
4658                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4659                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4660                                         save_area_offset += 8;
4661                                 }
4662
4663                         if (cfg->arch.omit_fp) {
4664                                 if (cfg->arch.stack_alloc_size)
4665                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4666                                 // FIXME:
4667                                 if (call->stack_usage)
4668                                         NOT_IMPLEMENTED;
4669                         } else {
4670                                 /* Copy arguments on the stack to our argument area */
4671                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4672                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4673                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4674                                 }
4675
4676                                 amd64_leave (code);
4677                         }
4678
4679                         offset = code - cfg->native_code;
4680                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4681                         if (cfg->compile_aot)
4682                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4683                         else
4684                                 amd64_set_reg_template (code, AMD64_R11);
4685                         amd64_jump_reg (code, AMD64_R11);
4686                         ins->flags |= MONO_INST_GC_CALLSITE;
4687                         ins->backend.pc_offset = code - cfg->native_code;
4688                         break;
4689                 }
4690                 case OP_CHECK_THIS:
4691                         /* ensure ins->sreg1 is not NULL */
4692                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4693                         break;
4694                 case OP_ARGLIST: {
4695                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4696                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4697                         break;
4698                 }
4699                 case OP_CALL:
4700                 case OP_FCALL:
4701                 case OP_LCALL:
4702                 case OP_VCALL:
4703                 case OP_VCALL2:
4704                 case OP_VOIDCALL:
4705                         call = (MonoCallInst*)ins;
4706                         /*
4707                          * The AMD64 ABI forces callers to know about varargs.
4708                          */
4709                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4710                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4711                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4712                                 /*
4713                                  * Since the unmanaged calling convention doesn't contain a
4714                                  * 'vararg' entry, we have to treat every pinvoke call as a
4715                                  * potential vararg call.
4716                                  */
4717                                 guint32 nregs, i;
4718                                 nregs = 0;
4719                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4720                                         if (call->used_fregs & (1 << i))
4721                                                 nregs ++;
4722                                 if (!nregs)
4723                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4724                                 else
4725                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4726                         }
4727
4728                         if (ins->flags & MONO_INST_HAS_METHOD)
4729                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4730                         else
4731                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4732                         ins->flags |= MONO_INST_GC_CALLSITE;
4733                         ins->backend.pc_offset = code - cfg->native_code;
4734                         code = emit_move_return_value (cfg, ins, code);
4735                         break;
4736                 case OP_FCALL_REG:
4737                 case OP_LCALL_REG:
4738                 case OP_VCALL_REG:
4739                 case OP_VCALL2_REG:
4740                 case OP_VOIDCALL_REG:
4741                 case OP_CALL_REG:
4742                         call = (MonoCallInst*)ins;
4743
4744                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4745                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4746                                 ins->sreg1 = AMD64_R11;
4747                         }
4748
4749                         /*
4750                          * The AMD64 ABI forces callers to know about varargs.
4751                          */
4752                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4753                                 if (ins->sreg1 == AMD64_RAX) {
4754                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4755                                         ins->sreg1 = AMD64_R11;
4756                                 }
4757                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4758                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4759                                 /*
4760                                  * Since the unmanaged calling convention doesn't contain a
4761                                  * 'vararg' entry, we have to treat every pinvoke call as a
4762                                  * potential vararg call.
4763                                  */
4764                                 guint32 nregs, i;
4765                                 nregs = 0;
4766                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4767                                         if (call->used_fregs & (1 << i))
4768                                                 nregs ++;
4769                                 if (ins->sreg1 == AMD64_RAX) {
4770                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4771                                         ins->sreg1 = AMD64_R11;
4772                                 }
4773                                 if (!nregs)
4774                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4775                                 else
4776                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4777                         }
4778
4779                         amd64_call_reg (code, ins->sreg1);
4780                         ins->flags |= MONO_INST_GC_CALLSITE;
4781                         ins->backend.pc_offset = code - cfg->native_code;
4782                         code = emit_move_return_value (cfg, ins, code);
4783                         break;
4784                 case OP_FCALL_MEMBASE:
4785                 case OP_LCALL_MEMBASE:
4786                 case OP_VCALL_MEMBASE:
4787                 case OP_VCALL2_MEMBASE:
4788                 case OP_VOIDCALL_MEMBASE:
4789                 case OP_CALL_MEMBASE:
4790                         call = (MonoCallInst*)ins;
4791
4792                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4793                         ins->flags |= MONO_INST_GC_CALLSITE;
4794                         ins->backend.pc_offset = code - cfg->native_code;
4795                         code = emit_move_return_value (cfg, ins, code);
4796                         break;
4797                 case OP_DYN_CALL: {
4798                         int i;
4799                         MonoInst *var = cfg->dyn_call_var;
4800
4801                         g_assert (var->opcode == OP_REGOFFSET);
4802
4803                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4804                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4805                         /* r10 = ftn */
4806                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4807
4808                         /* Save args buffer */
4809                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4810
4811                         /* Set argument registers */
4812                         for (i = 0; i < PARAM_REGS; ++i)
4813                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4814
4815                         /* Make the call */
4816                         amd64_call_reg (code, AMD64_R10);
4817
4818                         ins->flags |= MONO_INST_GC_CALLSITE;
4819                         ins->backend.pc_offset = code - cfg->native_code;
4820
4821                         /* Save result */
4822                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4823                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4824                         break;
4825                 }
4826                 case OP_AMD64_SAVE_SP_TO_LMF: {
4827                         MonoInst *lmf_var = cfg->lmf_var;
4828                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4829                         break;
4830                 }
4831                 case OP_X86_PUSH:
4832                         g_assert_not_reached ();
4833                         amd64_push_reg (code, ins->sreg1);
4834                         break;
4835                 case OP_X86_PUSH_IMM:
4836                         g_assert_not_reached ();
4837                         g_assert (amd64_is_imm32 (ins->inst_imm));
4838                         amd64_push_imm (code, ins->inst_imm);
4839                         break;
4840                 case OP_X86_PUSH_MEMBASE:
4841                         g_assert_not_reached ();
4842                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4843                         break;
4844                 case OP_X86_PUSH_OBJ: {
4845                         int size = ALIGN_TO (ins->inst_imm, 8);
4846
4847                         g_assert_not_reached ();
4848
4849                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4850                         amd64_push_reg (code, AMD64_RDI);
4851                         amd64_push_reg (code, AMD64_RSI);
4852                         amd64_push_reg (code, AMD64_RCX);
4853                         if (ins->inst_offset)
4854                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4855                         else
4856                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4857                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4858                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4859                         amd64_cld (code);
4860                         amd64_prefix (code, X86_REP_PREFIX);
4861                         amd64_movsd (code);
4862                         amd64_pop_reg (code, AMD64_RCX);
4863                         amd64_pop_reg (code, AMD64_RSI);
4864                         amd64_pop_reg (code, AMD64_RDI);
4865                         break;
4866                 }
4867                 case OP_X86_LEA:
4868                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4869                         break;
4870                 case OP_X86_LEA_MEMBASE:
4871                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4872                         break;
4873                 case OP_X86_XCHG:
4874                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4875                         break;
4876                 case OP_LOCALLOC:
4877                         /* keep alignment */
4878                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4879                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4880                         code = mono_emit_stack_alloc (cfg, code, ins);
4881                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4882                         if (cfg->param_area)
4883                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4884                         break;
4885                 case OP_LOCALLOC_IMM: {
4886                         guint32 size = ins->inst_imm;
4887                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4888
4889                         if (ins->flags & MONO_INST_INIT) {
4890                                 if (size < 64) {
4891                                         int i;
4892
4893                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4894                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4895
4896                                         for (i = 0; i < size; i += 8)
4897                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4898                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4899                                 } else {
4900                                         amd64_mov_reg_imm (code, ins->dreg, size);
4901                                         ins->sreg1 = ins->dreg;
4902
4903                                         code = mono_emit_stack_alloc (cfg, code, ins);
4904                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4905                                 }
4906                         } else {
4907                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4908                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4909                         }
4910                         if (cfg->param_area)
4911                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4912                         break;
4913                 }
4914                 case OP_THROW: {
4915                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4916                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4917                                              (gpointer)"mono_arch_throw_exception", FALSE);
4918                         ins->flags |= MONO_INST_GC_CALLSITE;
4919                         ins->backend.pc_offset = code - cfg->native_code;
4920                         break;
4921                 }
4922                 case OP_RETHROW: {
4923                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4924                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4925                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4926                         ins->flags |= MONO_INST_GC_CALLSITE;
4927                         ins->backend.pc_offset = code - cfg->native_code;
4928                         break;
4929                 }
4930                 case OP_CALL_HANDLER:
4931                         /* Align stack */
4932                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4933                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4934                         amd64_call_imm (code, 0);
4935                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4936                         /* Restore stack alignment */
4937                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4938                         break;
4939                 case OP_START_HANDLER: {
4940                         /* Even though we're saving RSP, use sizeof */
4941                         /* gpointer because spvar is of type IntPtr */
4942                         /* see: mono_create_spvar_for_region */
4943                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4944                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4945
4946                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4947                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4948                                 cfg->param_area) {
4949                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4950                         }
4951                         break;
4952                 }
4953                 case OP_ENDFINALLY: {
4954                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4955                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4956                         amd64_ret (code);
4957                         break;
4958                 }
4959                 case OP_ENDFILTER: {
4960                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4961                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4962                         /* The local allocator will put the result into RAX */
4963                         amd64_ret (code);
4964                         break;
4965                 }
4966
4967                 case OP_LABEL:
4968                         ins->inst_c0 = code - cfg->native_code;
4969                         break;
4970                 case OP_BR:
4971                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4972                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4973                         //break;
4974                                 if (ins->inst_target_bb->native_offset) {
4975                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4976                                 } else {
4977                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4978                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4979                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4980                                                 x86_jump8 (code, 0);
4981                                         else
4982                                                 x86_jump32 (code, 0);
4983                         }
4984                         break;
4985                 case OP_BR_REG:
4986                         amd64_jump_reg (code, ins->sreg1);
4987                         break;
4988                 case OP_ICNEQ:
4989                 case OP_ICGE:
4990                 case OP_ICLE:
4991                 case OP_ICGE_UN:
4992                 case OP_ICLE_UN:
4993
4994                 case OP_CEQ:
4995                 case OP_LCEQ:
4996                 case OP_ICEQ:
4997                 case OP_CLT:
4998                 case OP_LCLT:
4999                 case OP_ICLT:
5000                 case OP_CGT:
5001                 case OP_ICGT:
5002                 case OP_LCGT:
5003                 case OP_CLT_UN:
5004                 case OP_LCLT_UN:
5005                 case OP_ICLT_UN:
5006                 case OP_CGT_UN:
5007                 case OP_LCGT_UN:
5008                 case OP_ICGT_UN:
5009                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5010                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5011                         break;
5012                 case OP_COND_EXC_EQ:
5013                 case OP_COND_EXC_NE_UN:
5014                 case OP_COND_EXC_LT:
5015                 case OP_COND_EXC_LT_UN:
5016                 case OP_COND_EXC_GT:
5017                 case OP_COND_EXC_GT_UN:
5018                 case OP_COND_EXC_GE:
5019                 case OP_COND_EXC_GE_UN:
5020                 case OP_COND_EXC_LE:
5021                 case OP_COND_EXC_LE_UN:
5022                 case OP_COND_EXC_IEQ:
5023                 case OP_COND_EXC_INE_UN:
5024                 case OP_COND_EXC_ILT:
5025                 case OP_COND_EXC_ILT_UN:
5026                 case OP_COND_EXC_IGT:
5027                 case OP_COND_EXC_IGT_UN:
5028                 case OP_COND_EXC_IGE:
5029                 case OP_COND_EXC_IGE_UN:
5030                 case OP_COND_EXC_ILE:
5031                 case OP_COND_EXC_ILE_UN:
5032                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5033                         break;
5034                 case OP_COND_EXC_OV:
5035                 case OP_COND_EXC_NO:
5036                 case OP_COND_EXC_C:
5037                 case OP_COND_EXC_NC:
5038                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5039                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5040                         break;
5041                 case OP_COND_EXC_IOV:
5042                 case OP_COND_EXC_INO:
5043                 case OP_COND_EXC_IC:
5044                 case OP_COND_EXC_INC:
5045                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5046                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5047                         break;
5048
5049                 /* floating point opcodes */
5050                 case OP_R8CONST: {
5051                         double d = *(double *)ins->inst_p0;
5052
5053                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5054                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5055                         }
5056                         else {
5057                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5058                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5059                         }
5060                         break;
5061                 }
5062                 case OP_R4CONST: {
5063                         float f = *(float *)ins->inst_p0;
5064
5065                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5066                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5067                         }
5068                         else {
5069                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5070                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5071                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5072                         }
5073                         break;
5074                 }
5075                 case OP_STORER8_MEMBASE_REG:
5076                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5077                         break;
5078                 case OP_LOADR8_MEMBASE:
5079                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5080                         break;
5081                 case OP_STORER4_MEMBASE_REG:
5082                         /* This requires a double->single conversion */
5083                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5084                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5085                         break;
5086                 case OP_LOADR4_MEMBASE:
5087                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5088                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5089                         break;
5090                 case OP_ICONV_TO_R4:
5091                         amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5092                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5093                         break;
5094                 case OP_ICONV_TO_R8:
5095                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5096                         break;
5097                 case OP_LCONV_TO_R4:
5098                         amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5099                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5100                         break;
5101                 case OP_LCONV_TO_R8:
5102                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5103                         break;
5104                 case OP_FCONV_TO_R4:
5105                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5106                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5107                         break;
5108                 case OP_FCONV_TO_I1:
5109                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5110                         break;
5111                 case OP_FCONV_TO_U1:
5112                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5113                         break;
5114                 case OP_FCONV_TO_I2:
5115                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5116                         break;
5117                 case OP_FCONV_TO_U2:
5118                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5119                         break;
5120                 case OP_FCONV_TO_U4:
5121                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5122                         break;
5123                 case OP_FCONV_TO_I4:
5124                 case OP_FCONV_TO_I:
5125                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5126                         break;
5127                 case OP_FCONV_TO_I8:
5128                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5129                         break;
5130                 case OP_LCONV_TO_R_UN: {
5131                         guint8 *br [2];
5132
5133                         /* Based on gcc code */
5134                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5135                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5136
5137                         /* Positive case */
5138                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5139                         br [1] = code; x86_jump8 (code, 0);
5140                         amd64_patch (br [0], code);
5141
5142                         /* Negative case */
5143                         /* Save to the red zone */
5144                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5145                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5146                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5147                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5148                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5149                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5150                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5151                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5152                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5153                         /* Restore */
5154                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5155                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5156                         amd64_patch (br [1], code);
5157                         break;
5158                 }
5159                 case OP_LCONV_TO_OVF_U4:
5160                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5161                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5162                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5163                         break;
5164                 case OP_LCONV_TO_OVF_I4_UN:
5165                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5166                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5167                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5168                         break;
5169                 case OP_FMOVE:
5170                         if (ins->dreg != ins->sreg1)
5171                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5172                         break;
5173                 case OP_FADD:
5174                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5175                         break;
5176                 case OP_FSUB:
5177                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5178                         break;
5179                 case OP_FMUL:
5180                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5181                         break;
5182                 case OP_FDIV:
5183                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5184                         break;
5185                 case OP_FNEG: {
5186                         static double r8_0 = -0.0;
5187
5188                         g_assert (ins->sreg1 == ins->dreg);
5189
5190                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5191                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5192                         break;
5193                 }
5194                 case OP_SIN:
5195                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5196                         break;
5197                 case OP_COS:
5198                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5199                         break;
5200                 case OP_ABS: {
5201                         static guint64 d = 0x7fffffffffffffffUL;
5202
5203                         g_assert (ins->sreg1 == ins->dreg);
5204
5205                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5206                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5207                         break;
5208                 }
5209                 case OP_SQRT:
5210                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5211                         break;
5212                 case OP_IMIN:
5213                         g_assert (cfg->opt & MONO_OPT_CMOV);
5214                         g_assert (ins->dreg == ins->sreg1);
5215                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5216                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5217                         break;
5218                 case OP_IMIN_UN:
5219                         g_assert (cfg->opt & MONO_OPT_CMOV);
5220                         g_assert (ins->dreg == ins->sreg1);
5221                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5222                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5223                         break;
5224                 case OP_IMAX:
5225                         g_assert (cfg->opt & MONO_OPT_CMOV);
5226                         g_assert (ins->dreg == ins->sreg1);
5227                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5228                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5229                         break;
5230                 case OP_IMAX_UN:
5231                         g_assert (cfg->opt & MONO_OPT_CMOV);
5232                         g_assert (ins->dreg == ins->sreg1);
5233                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5234                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5235                         break;
5236                 case OP_LMIN:
5237                         g_assert (cfg->opt & MONO_OPT_CMOV);
5238                         g_assert (ins->dreg == ins->sreg1);
5239                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5240                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5241                         break;
5242                 case OP_LMIN_UN:
5243                         g_assert (cfg->opt & MONO_OPT_CMOV);
5244                         g_assert (ins->dreg == ins->sreg1);
5245                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5246                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5247                         break;
5248                 case OP_LMAX:
5249                         g_assert (cfg->opt & MONO_OPT_CMOV);
5250                         g_assert (ins->dreg == ins->sreg1);
5251                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5252                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5253                         break;
5254                 case OP_LMAX_UN:
5255                         g_assert (cfg->opt & MONO_OPT_CMOV);
5256                         g_assert (ins->dreg == ins->sreg1);
5257                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5258                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5259                         break;
5260                 case OP_X86_FPOP:
5261                         break;
5262                 case OP_FCOMPARE:
5263                         /*
5264                          * The two arguments are swapped because the fbranch instructions
5265                          * depend on this for the non-sse case to work.
5266                          */
5267                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5268                         break;
5269                 case OP_FCNEQ:
5270                 case OP_FCEQ: {
5271                         /* zeroing the register at the start results in
5272                          * shorter and faster code (we can also remove the widening op)
5273                          */
5274                         guchar *unordered_check;
5275                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5276                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5277                         unordered_check = code;
5278                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5279
5280                         if (ins->opcode == OP_FCEQ) {
5281                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5282                                 amd64_patch (unordered_check, code);
5283                         } else {
5284                                 guchar *jump_to_end;
5285                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5286                                 jump_to_end = code;
5287                                 x86_jump8 (code, 0);
5288                                 amd64_patch (unordered_check, code);
5289                                 amd64_inc_reg (code, ins->dreg);
5290                                 amd64_patch (jump_to_end, code);
5291                         }
5292                         break;
5293                 }
5294                 case OP_FCLT:
5295                 case OP_FCLT_UN:
5296                         /* zeroing the register at the start results in
5297                          * shorter and faster code (we can also remove the widening op)
5298                          */
5299                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5300                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5301                         if (ins->opcode == OP_FCLT_UN) {
5302                                 guchar *unordered_check = code;
5303                                 guchar *jump_to_end;
5304                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5305                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5306                                 jump_to_end = code;
5307                                 x86_jump8 (code, 0);
5308                                 amd64_patch (unordered_check, code);
5309                                 amd64_inc_reg (code, ins->dreg);
5310                                 amd64_patch (jump_to_end, code);
5311                         } else {
5312                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5313                         }
5314                         break;
5315                 case OP_FCLE: {
5316                         guchar *unordered_check;
5317                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5318                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5319                         unordered_check = code;
5320                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5321                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5322                         amd64_patch (unordered_check, code);
5323                         break;
5324                 }
5325                 case OP_FCGT:
5326                 case OP_FCGT_UN: {
5327                         /* zeroing the register at the start results in
5328                          * shorter and faster code (we can also remove the widening op)
5329                          */
5330                         guchar *unordered_check;
5331                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5332                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5333                         if (ins->opcode == OP_FCGT) {
5334                                 unordered_check = code;
5335                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5336                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5337                                 amd64_patch (unordered_check, code);
5338                         } else {
5339                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5340                         }
5341                         break;
5342                 }
5343                 case OP_FCGE: {
5344                         guchar *unordered_check;
5345                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5346                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5347                         unordered_check = code;
5348                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5349                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5350                         amd64_patch (unordered_check, code);
5351                         break;
5352                 }
5353
5354                 case OP_FCLT_MEMBASE:
5355                 case OP_FCGT_MEMBASE:
5356                 case OP_FCLT_UN_MEMBASE:
5357                 case OP_FCGT_UN_MEMBASE:
5358                 case OP_FCEQ_MEMBASE: {
5359                         guchar *unordered_check, *jump_to_end;
5360                         int x86_cond;
5361
5362                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5363                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5364
5365                         switch (ins->opcode) {
5366                         case OP_FCEQ_MEMBASE:
5367                                 x86_cond = X86_CC_EQ;
5368                                 break;
5369                         case OP_FCLT_MEMBASE:
5370                         case OP_FCLT_UN_MEMBASE:
5371                                 x86_cond = X86_CC_LT;
5372                                 break;
5373                         case OP_FCGT_MEMBASE:
5374                         case OP_FCGT_UN_MEMBASE:
5375                                 x86_cond = X86_CC_GT;
5376                                 break;
5377                         default:
5378                                 g_assert_not_reached ();
5379                         }
5380
5381                         unordered_check = code;
5382                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5383                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5384
5385                         switch (ins->opcode) {
5386                         case OP_FCEQ_MEMBASE:
5387                         case OP_FCLT_MEMBASE:
5388                         case OP_FCGT_MEMBASE:
5389                                 amd64_patch (unordered_check, code);
5390                                 break;
5391                         case OP_FCLT_UN_MEMBASE:
5392                         case OP_FCGT_UN_MEMBASE:
5393                                 jump_to_end = code;
5394                                 x86_jump8 (code, 0);
5395                                 amd64_patch (unordered_check, code);
5396                                 amd64_inc_reg (code, ins->dreg);
5397                                 amd64_patch (jump_to_end, code);
5398                                 break;
5399                         default:
5400                                 break;
5401                         }
5402                         break;
5403                 }
5404                 case OP_FBEQ: {
5405                         guchar *jump = code;
5406                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5407                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5408                         amd64_patch (jump, code);
5409                         break;
5410                 }
5411                 case OP_FBNE_UN:
5412                         /* Branch if C013 != 100 */
5413                         /* branch if !ZF or (PF|CF) */
5414                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5415                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5416                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5417                         break;
5418                 case OP_FBLT:
5419                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5420                         break;
5421                 case OP_FBLT_UN:
5422                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5423                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5424                         break;
5425                 case OP_FBGT:
5426                 case OP_FBGT_UN:
5427                         if (ins->opcode == OP_FBGT) {
5428                                 guchar *br1;
5429
5430                                 /* skip branch if C1=1 */
5431                                 br1 = code;
5432                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5433                                 /* branch if (C0 | C3) = 1 */
5434                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5435                                 amd64_patch (br1, code);
5436                                 break;
5437                         } else {
5438                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5439                         }
5440                         break;
5441                 case OP_FBGE: {
5442                         /* Branch if C013 == 100 or 001 */
5443                         guchar *br1;
5444
5445                         /* skip branch if C1=1 */
5446                         br1 = code;
5447                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5448                         /* branch if (C0 | C3) = 1 */
5449                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5450                         amd64_patch (br1, code);
5451                         break;
5452                 }
5453                 case OP_FBGE_UN:
5454                         /* Branch if C013 == 000 */
5455                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5456                         break;
5457                 case OP_FBLE: {
5458                         /* Branch if C013=000 or 100 */
5459                         guchar *br1;
5460
5461                         /* skip branch if C1=1 */
5462                         br1 = code;
5463                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5464                         /* branch if C0=0 */
5465                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5466                         amd64_patch (br1, code);
5467                         break;
5468                 }
5469                 case OP_FBLE_UN:
5470                         /* Branch if C013 != 001 */
5471                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5472                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5473                         break;
5474                 case OP_CKFINITE:
5475                         /* Transfer value to the fp stack */
5476                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5477                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5478                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5479
5480                         amd64_push_reg (code, AMD64_RAX);
5481                         amd64_fxam (code);
5482                         amd64_fnstsw (code);
5483                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5484                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5485                         amd64_pop_reg (code, AMD64_RAX);
5486                         amd64_fstp (code, 0);
5487                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5488                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5489                         break;
5490                 case OP_TLS_GET: {
5491                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5492                         break;
5493                 }
5494                 case OP_TLS_GET_REG:
5495                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5496                         break;
5497                 case OP_TLS_SET: {
5498                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5499                         break;
5500                 }
5501                 case OP_TLS_SET_REG: {
5502                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5503                         break;
5504                 }
5505                 case OP_MEMORY_BARRIER: {
5506                         switch (ins->backend.memory_barrier_kind) {
5507                         case StoreLoadBarrier:
5508                         case FullBarrier:
5509                                 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5510                                 x86_prefix (code, X86_LOCK_PREFIX);
5511                                 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5512                                 break;
5513                         }
5514                         break;
5515                 }
5516                 case OP_ATOMIC_ADD_I4:
5517                 case OP_ATOMIC_ADD_I8: {
5518                         int dreg = ins->dreg;
5519                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5520
5521                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5522                                 dreg = AMD64_R11;
5523
5524                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5525                         amd64_prefix (code, X86_LOCK_PREFIX);
5526                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5527                         /* dreg contains the old value, add with sreg2 value */
5528                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5529
5530                         if (ins->dreg != dreg)
5531                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5532
5533                         break;
5534                 }
5535                 case OP_ATOMIC_EXCHANGE_I4:
5536                 case OP_ATOMIC_EXCHANGE_I8: {
5537                         guchar *br[2];
5538                         int sreg2 = ins->sreg2;
5539                         int breg = ins->inst_basereg;
5540                         guint32 size;
5541                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5542
5543                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5544                                 size = 8;
5545                         else
5546                                 size = 4;
5547
5548                         /*
5549                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5550                          * an explanation of how this works.
5551                          */
5552
5553                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5554                          * hack to overcome limits in x86 reg allocator
5555                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5556                          */
5557                         g_assert (ins->dreg == AMD64_RAX);
5558
5559                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5560                                 /* Highly unlikely, but possible */
5561                                 need_push = TRUE;
5562
5563                         /* The pushes invalidate rsp */
5564                         if ((breg == AMD64_RAX) || need_push) {
5565                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5566                                 breg = AMD64_R11;
5567                         }
5568
5569                         /* We need the EAX reg for the comparand */
5570                         if (ins->sreg2 == AMD64_RAX) {
5571                                 if (breg != AMD64_R11) {
5572                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5573                                         sreg2 = AMD64_R11;
5574                                 } else {
5575                                         g_assert (need_push);
5576                                         amd64_push_reg (code, AMD64_RDX);
5577                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5578                                         sreg2 = AMD64_RDX;
5579                                         rdx_pushed = TRUE;
5580                                 }
5581                         }
5582
5583                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5584
5585                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5586                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5587                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5588                         amd64_patch (br [1], br [0]);
5589
5590                         if (rdx_pushed)
5591                                 amd64_pop_reg (code, AMD64_RDX);
5592
5593                         break;
5594                 }
5595                 case OP_ATOMIC_CAS_I4:
5596                 case OP_ATOMIC_CAS_I8: {
5597                         guint32 size;
5598
5599                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5600                                 size = 8;
5601                         else
5602                                 size = 4;
5603
5604                         /*
5605                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5606                          * an explanation of how this works.
5607                          */
5608                         g_assert (ins->sreg3 == AMD64_RAX);
5609                         g_assert (ins->sreg1 != AMD64_RAX);
5610                         g_assert (ins->sreg1 != ins->sreg2);
5611
5612                         amd64_prefix (code, X86_LOCK_PREFIX);
5613                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5614
5615                         if (ins->dreg != AMD64_RAX)
5616                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5617                         break;
5618                 }
5619                 case OP_CARD_TABLE_WBARRIER: {
5620                         int ptr = ins->sreg1;
5621                         int value = ins->sreg2;
5622                         guchar *br = 0;
5623                         int nursery_shift, card_table_shift;
5624                         gpointer card_table_mask;
5625                         size_t nursery_size;
5626
5627                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5628                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5629                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5630
5631                         /*If either point to the stack we can simply avoid the WB. This happens due to
5632                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5633                          */
5634                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5635                                 continue;
5636
5637                         /*
5638                          * We need one register we can clobber, we choose EDX and make sreg1
5639                          * fixed EAX to work around limitations in the local register allocator.
5640                          * sreg2 might get allocated to EDX, but that is not a problem since
5641                          * we use it before clobbering EDX.
5642                          */
5643                         g_assert (ins->sreg1 == AMD64_RAX);
5644
5645                         /*
5646                          * This is the code we produce:
5647                          *
5648                          *   edx = value
5649                          *   edx >>= nursery_shift
5650                          *   cmp edx, (nursery_start >> nursery_shift)
5651                          *   jne done
5652                          *   edx = ptr
5653                          *   edx >>= card_table_shift
5654                          *   edx += cardtable
5655                          *   [edx] = 1
5656                          * done:
5657                          */
5658
5659                         if (mono_gc_card_table_nursery_check ()) {
5660                                 if (value != AMD64_RDX)
5661                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5662                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5663                                 if (shifted_nursery_start >> 31) {
5664                                         /*
5665                                          * The value we need to compare against is 64 bits, so we need
5666                                          * another spare register.  We use RBX, which we save and
5667                                          * restore.
5668                                          */
5669                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5670                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5671                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5672                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5673                                 } else {
5674                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5675                                 }
5676                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5677                         }
5678                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5679                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5680                         if (card_table_mask)
5681                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5682
5683                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5684                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5685
5686                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5687
5688                         if (mono_gc_card_table_nursery_check ())
5689                                 x86_patch (br, code);
5690                         break;
5691                 }
5692 #ifdef MONO_ARCH_SIMD_INTRINSICS
5693                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5694                 case OP_ADDPS:
5695                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5696                         break;
5697                 case OP_DIVPS:
5698                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5699                         break;
5700                 case OP_MULPS:
5701                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5702                         break;
5703                 case OP_SUBPS:
5704                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5705                         break;
5706                 case OP_MAXPS:
5707                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5708                         break;
5709                 case OP_MINPS:
5710                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5711                         break;
5712                 case OP_COMPPS:
5713                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5714                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5715                         break;
5716                 case OP_ANDPS:
5717                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5718                         break;
5719                 case OP_ANDNPS:
5720                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5721                         break;
5722                 case OP_ORPS:
5723                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5724                         break;
5725                 case OP_XORPS:
5726                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5727                         break;
5728                 case OP_SQRTPS:
5729                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5730                         break;
5731                 case OP_RSQRTPS:
5732                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5733                         break;
5734                 case OP_RCPPS:
5735                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5736                         break;
5737                 case OP_ADDSUBPS:
5738                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5739                         break;
5740                 case OP_HADDPS:
5741                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5742                         break;
5743                 case OP_HSUBPS:
5744                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5745                         break;
5746                 case OP_DUPPS_HIGH:
5747                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5748                         break;
5749                 case OP_DUPPS_LOW:
5750                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5751                         break;
5752
5753                 case OP_PSHUFLEW_HIGH:
5754                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5755                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5756                         break;
5757                 case OP_PSHUFLEW_LOW:
5758                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5759                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5760                         break;
5761                 case OP_PSHUFLED:
5762                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5763                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5764                         break;
5765                 case OP_SHUFPS:
5766                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5767                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5768                         break;
5769                 case OP_SHUFPD:
5770                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5771                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5772                         break;
5773
5774                 case OP_ADDPD:
5775                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5776                         break;
5777                 case OP_DIVPD:
5778                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5779                         break;
5780                 case OP_MULPD:
5781                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5782                         break;
5783                 case OP_SUBPD:
5784                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5785                         break;
5786                 case OP_MAXPD:
5787                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5788                         break;
5789                 case OP_MINPD:
5790                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5791                         break;
5792                 case OP_COMPPD:
5793                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5794                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5795                         break;
5796                 case OP_ANDPD:
5797                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5798                         break;
5799                 case OP_ANDNPD:
5800                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5801                         break;
5802                 case OP_ORPD:
5803                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5804                         break;
5805                 case OP_XORPD:
5806                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5807                         break;
5808                 case OP_SQRTPD:
5809                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5810                         break;
5811                 case OP_ADDSUBPD:
5812                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5813                         break;
5814                 case OP_HADDPD:
5815                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5816                         break;
5817                 case OP_HSUBPD:
5818                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5819                         break;
5820                 case OP_DUPPD:
5821                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5822                         break;
5823
5824                 case OP_EXTRACT_MASK:
5825                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5826                         break;
5827
5828                 case OP_PAND:
5829                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5830                         break;
5831                 case OP_POR:
5832                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5833                         break;
5834                 case OP_PXOR:
5835                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5836                         break;
5837
5838                 case OP_PADDB:
5839                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5840                         break;
5841                 case OP_PADDW:
5842                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5843                         break;
5844                 case OP_PADDD:
5845                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5846                         break;
5847                 case OP_PADDQ:
5848                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5849                         break;
5850
5851                 case OP_PSUBB:
5852                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5853                         break;
5854                 case OP_PSUBW:
5855                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5856                         break;
5857                 case OP_PSUBD:
5858                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5859                         break;
5860                 case OP_PSUBQ:
5861                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5862                         break;
5863
5864                 case OP_PMAXB_UN:
5865                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5866                         break;
5867                 case OP_PMAXW_UN:
5868                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5869                         break;
5870                 case OP_PMAXD_UN:
5871                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5872                         break;
5873
5874                 case OP_PMAXB:
5875                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5876                         break;
5877                 case OP_PMAXW:
5878                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5879                         break;
5880                 case OP_PMAXD:
5881                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5882                         break;
5883
5884                 case OP_PAVGB_UN:
5885                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5886                         break;
5887                 case OP_PAVGW_UN:
5888                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5889                         break;
5890
5891                 case OP_PMINB_UN:
5892                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5893                         break;
5894                 case OP_PMINW_UN:
5895                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5896                         break;
5897                 case OP_PMIND_UN:
5898                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5899                         break;
5900
5901                 case OP_PMINB:
5902                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904                 case OP_PMINW:
5905                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5906                         break;
5907                 case OP_PMIND:
5908                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910
5911                 case OP_PCMPEQB:
5912                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5913                         break;
5914                 case OP_PCMPEQW:
5915                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5916                         break;
5917                 case OP_PCMPEQD:
5918                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_PCMPEQQ:
5921                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923
5924                 case OP_PCMPGTB:
5925                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5926                         break;
5927                 case OP_PCMPGTW:
5928                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5929                         break;
5930                 case OP_PCMPGTD:
5931                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5932                         break;
5933                 case OP_PCMPGTQ:
5934                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936
5937                 case OP_PSUM_ABS_DIFF:
5938                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5939                         break;
5940
5941                 case OP_UNPACK_LOWB:
5942                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5943                         break;
5944                 case OP_UNPACK_LOWW:
5945                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5946                         break;
5947                 case OP_UNPACK_LOWD:
5948                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5949                         break;
5950                 case OP_UNPACK_LOWQ:
5951                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5952                         break;
5953                 case OP_UNPACK_LOWPS:
5954                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5955                         break;
5956                 case OP_UNPACK_LOWPD:
5957                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5958                         break;
5959
5960                 case OP_UNPACK_HIGHB:
5961                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5962                         break;
5963                 case OP_UNPACK_HIGHW:
5964                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5965                         break;
5966                 case OP_UNPACK_HIGHD:
5967                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5968                         break;
5969                 case OP_UNPACK_HIGHQ:
5970                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_UNPACK_HIGHPS:
5973                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_UNPACK_HIGHPD:
5976                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978
5979                 case OP_PACKW:
5980                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982                 case OP_PACKD:
5983                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_PACKW_UN:
5986                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988                 case OP_PACKD_UN:
5989                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5990                         break;
5991
5992                 case OP_PADDB_SAT_UN:
5993                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995                 case OP_PSUBB_SAT_UN:
5996                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998                 case OP_PADDW_SAT_UN:
5999                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_PSUBW_SAT_UN:
6002                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6003                         break;
6004
6005                 case OP_PADDB_SAT:
6006                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6007                         break;
6008                 case OP_PSUBB_SAT:
6009                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011                 case OP_PADDW_SAT:
6012                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014                 case OP_PSUBW_SAT:
6015                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017
6018                 case OP_PMULW:
6019                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021                 case OP_PMULD:
6022                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024                 case OP_PMULQ:
6025                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027                 case OP_PMULW_HIGH_UN:
6028                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6029                         break;
6030                 case OP_PMULW_HIGH:
6031                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6032                         break;
6033
6034                 case OP_PSHRW:
6035                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6036                         break;
6037                 case OP_PSHRW_REG:
6038                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6039                         break;
6040
6041                 case OP_PSARW:
6042                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6043                         break;
6044                 case OP_PSARW_REG:
6045                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6046                         break;
6047
6048                 case OP_PSHLW:
6049                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6050                         break;
6051                 case OP_PSHLW_REG:
6052                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6053                         break;
6054
6055                 case OP_PSHRD:
6056                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6057                         break;
6058                 case OP_PSHRD_REG:
6059                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6060                         break;
6061
6062                 case OP_PSARD:
6063                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6064                         break;
6065                 case OP_PSARD_REG:
6066                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6067                         break;
6068
6069                 case OP_PSHLD:
6070                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6071                         break;
6072                 case OP_PSHLD_REG:
6073                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6074                         break;
6075
6076                 case OP_PSHRQ:
6077                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6078                         break;
6079                 case OP_PSHRQ_REG:
6080                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6081                         break;
6082
6083                 /*TODO: This is appart of the sse spec but not added
6084                 case OP_PSARQ:
6085                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6086                         break;
6087                 case OP_PSARQ_REG:
6088                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6089                         break;
6090                 */
6091
6092                 case OP_PSHLQ:
6093                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6094                         break;
6095                 case OP_PSHLQ_REG:
6096                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6097                         break;
6098                 case OP_CVTDQ2PD:
6099                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6100                         break;
6101                 case OP_CVTDQ2PS:
6102                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6103                         break;
6104                 case OP_CVTPD2DQ:
6105                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6106                         break;
6107                 case OP_CVTPD2PS:
6108                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6109                         break;
6110                 case OP_CVTPS2DQ:
6111                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6112                         break;
6113                 case OP_CVTPS2PD:
6114                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6115                         break;
6116                 case OP_CVTTPD2DQ:
6117                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6118                         break;
6119                 case OP_CVTTPS2DQ:
6120                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6121                         break;
6122
6123                 case OP_ICONV_TO_X:
6124                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6125                         break;
6126                 case OP_EXTRACT_I4:
6127                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6128                         break;
6129                 case OP_EXTRACT_I8:
6130                         if (ins->inst_c0) {
6131                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6132                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6133                         } else {
6134                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6135                         }
6136                         break;
6137                 case OP_EXTRACT_I1:
6138                 case OP_EXTRACT_U1:
6139                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6140                         if (ins->inst_c0)
6141                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6142                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6143                         break;
6144                 case OP_EXTRACT_I2:
6145                 case OP_EXTRACT_U2:
6146                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6147                         if (ins->inst_c0)
6148                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6149                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6150                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6151                         break;
6152                 case OP_EXTRACT_R8:
6153                         if (ins->inst_c0)
6154                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6155                         else
6156                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6157                         break;
6158                 case OP_INSERT_I2:
6159                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6160                         break;
6161                 case OP_EXTRACTX_U2:
6162                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6163                         break;
6164                 case OP_INSERTX_U1_SLOW:
6165                         /*sreg1 is the extracted ireg (scratch)
6166                         /sreg2 is the to be inserted ireg (scratch)
6167                         /dreg is the xreg to receive the value*/
6168
6169                         /*clear the bits from the extracted word*/
6170                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6171                         /*shift the value to insert if needed*/
6172                         if (ins->inst_c0 & 1)
6173                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6174                         /*join them together*/
6175                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6176                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6177                         break;
6178                 case OP_INSERTX_I4_SLOW:
6179                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6180                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6181                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6182                         break;
6183                 case OP_INSERTX_I8_SLOW:
6184                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6185                         if (ins->inst_c0)
6186                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6187                         else
6188                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6189                         break;
6190
6191                 case OP_INSERTX_R4_SLOW:
6192                         switch (ins->inst_c0) {
6193                         case 0:
6194                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6195                                 break;
6196                         case 1:
6197                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6198                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6199                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6200                                 break;
6201                         case 2:
6202                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6203                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6204                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6205                                 break;
6206                         case 3:
6207                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6208                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6209                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6210                                 break;
6211                         }
6212                         break;
6213                 case OP_INSERTX_R8_SLOW:
6214                         if (ins->inst_c0)
6215                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6216                         else
6217                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6218                         break;
6219                 case OP_STOREX_MEMBASE_REG:
6220                 case OP_STOREX_MEMBASE:
6221                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6222                         break;
6223                 case OP_LOADX_MEMBASE:
6224                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6225                         break;
6226                 case OP_LOADX_ALIGNED_MEMBASE:
6227                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6228                         break;
6229                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6230                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6231                         break;
6232                 case OP_STOREX_NTA_MEMBASE_REG:
6233                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6234                         break;
6235                 case OP_PREFETCH_MEMBASE:
6236                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6237                         break;
6238
6239                 case OP_XMOVE:
6240                         /*FIXME the peephole pass should have killed this*/
6241                         if (ins->dreg != ins->sreg1)
6242                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6243                         break;
6244                 case OP_XZERO:
6245                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6246                         break;
6247                 case OP_ICONV_TO_R8_RAW:
6248                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6249                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6250                         break;
6251
6252                 case OP_FCONV_TO_R8_X:
6253                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6254                         break;
6255
6256                 case OP_XCONV_R8_TO_I4:
6257                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6258                         switch (ins->backend.source_opcode) {
6259                         case OP_FCONV_TO_I1:
6260                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6261                                 break;
6262                         case OP_FCONV_TO_U1:
6263                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6264                                 break;
6265                         case OP_FCONV_TO_I2:
6266                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6267                                 break;
6268                         case OP_FCONV_TO_U2:
6269                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6270                                 break;
6271                         }
6272                         break;
6273
6274                 case OP_EXPAND_I2:
6275                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6276                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6277                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6278                         break;
6279                 case OP_EXPAND_I4:
6280                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6281                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6282                         break;
6283                 case OP_EXPAND_I8:
6284                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6285                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6286                         break;
6287                 case OP_EXPAND_R4:
6288                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6289                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6290                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6291                         break;
6292                 case OP_EXPAND_R8:
6293                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6294                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6295                         break;
6296 #endif
6297                 case OP_LIVERANGE_START: {
6298                         if (cfg->verbose_level > 1)
6299                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6300                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6301                         break;
6302                 }
6303                 case OP_LIVERANGE_END: {
6304                         if (cfg->verbose_level > 1)
6305                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6306                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6307                         break;
6308                 }
6309                 case OP_NACL_GC_SAFE_POINT: {
6310 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6311                         if (cfg->compile_aot)
6312                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6313                         else {
6314                                 guint8 *br [1];
6315
6316                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6317                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6318                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6319                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6320                                 amd64_patch (br[0], code);
6321                         }
6322 #endif
6323                         break;
6324                 }
6325                 case OP_GC_LIVENESS_DEF:
6326                 case OP_GC_LIVENESS_USE:
6327                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6328                         ins->backend.pc_offset = code - cfg->native_code;
6329                         break;
6330                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6331                         ins->backend.pc_offset = code - cfg->native_code;
6332                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6333                         break;
6334                 default:
6335                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6336                         g_assert_not_reached ();
6337                 }
6338
6339                 if ((code - cfg->native_code - offset) > max_len) {
6340 #if !defined(__native_client_codegen__)
6341                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6342                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6343                         g_assert_not_reached ();
6344 #endif
6345                 }
6346
6347                 last_ins = ins;
6348                 last_offset = offset;
6349         }
6350
6351         cfg->code_len = code - cfg->native_code;
6352 }
6353
6354 #endif /* DISABLE_JIT */
6355
6356 void
6357 mono_arch_register_lowlevel_calls (void)
6358 {
6359         /* The signature doesn't matter */
6360         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6361 }
6362
6363 void
6364 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6365 {
6366         MonoJumpInfo *patch_info;
6367         gboolean compile_aot = !run_cctors;
6368
6369         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6370                 unsigned char *ip = patch_info->ip.i + code;
6371                 unsigned char *target;
6372
6373                 if (compile_aot) {
6374                         switch (patch_info->type) {
6375                         case MONO_PATCH_INFO_BB:
6376                         case MONO_PATCH_INFO_LABEL:
6377                                 break;
6378                         default:
6379                                 /* No need to patch these */
6380                                 continue;
6381                         }
6382                 }
6383
6384                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6385
6386                 switch (patch_info->type) {
6387                 case MONO_PATCH_INFO_NONE:
6388                         continue;
6389                 case MONO_PATCH_INFO_METHOD_REL:
6390                 case MONO_PATCH_INFO_R8:
6391                 case MONO_PATCH_INFO_R4:
6392                         g_assert_not_reached ();
6393                         continue;
6394                 case MONO_PATCH_INFO_BB:
6395                         break;
6396                 default:
6397                         break;
6398                 }
6399
6400                 /*
6401                  * Debug code to help track down problems where the target of a near call is
6402                  * is not valid.
6403                  */
6404                 if (amd64_is_near_call (ip)) {
6405                         gint64 disp = (guint8*)target - (guint8*)ip;
6406
6407                         if (!amd64_is_imm32 (disp)) {
6408                                 printf ("TYPE: %d\n", patch_info->type);
6409                                 switch (patch_info->type) {
6410                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6411                                         printf ("V: %s\n", patch_info->data.name);
6412                                         break;
6413                                 case MONO_PATCH_INFO_METHOD_JUMP:
6414                                 case MONO_PATCH_INFO_METHOD:
6415                                         printf ("V: %s\n", patch_info->data.method->name);
6416                                         break;
6417                                 default:
6418                                         break;
6419                                 }
6420                         }
6421                 }
6422
6423                 amd64_patch (ip, (gpointer)target);
6424         }
6425 }
6426
6427 #ifndef DISABLE_JIT
6428
6429 static int
6430 get_max_epilog_size (MonoCompile *cfg)
6431 {
6432         int max_epilog_size = 16;
6433
6434         if (cfg->method->save_lmf)
6435                 max_epilog_size += 256;
6436
6437         if (mono_jit_trace_calls != NULL)
6438                 max_epilog_size += 50;
6439
6440         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6441                 max_epilog_size += 50;
6442
6443         max_epilog_size += (AMD64_NREG * 2);
6444
6445         return max_epilog_size;
6446 }
6447
6448 /*
6449  * This macro is used for testing whenever the unwinder works correctly at every point
6450  * where an async exception can happen.
6451  */
6452 /* This will generate a SIGSEGV at the given point in the code */
6453 #define async_exc_point(code) do { \
6454     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6455          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6456              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6457          cfg->arch.async_point_count ++; \
6458     } \
6459 } while (0)
6460
6461 guint8 *
6462 mono_arch_emit_prolog (MonoCompile *cfg)
6463 {
6464         MonoMethod *method = cfg->method;
6465         MonoBasicBlock *bb;
6466         MonoMethodSignature *sig;
6467         MonoInst *ins;
6468         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6469         guint8 *code;
6470         CallInfo *cinfo;
6471         MonoInst *lmf_var = cfg->lmf_var;
6472         gboolean args_clobbered = FALSE;
6473         gboolean trace = FALSE;
6474 #ifdef __native_client_codegen__
6475         guint alignment_check;
6476 #endif
6477
6478         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6479
6480 #if defined(__default_codegen__)
6481         code = cfg->native_code = g_malloc (cfg->code_size);
6482 #elif defined(__native_client_codegen__)
6483         /* native_code_alloc is not 32-byte aligned, native_code is. */
6484         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6485
6486         /* Align native_code to next nearest kNaclAlignment byte. */
6487         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6488         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6489
6490         code = cfg->native_code;
6491
6492         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6493         g_assert (alignment_check == 0);
6494 #endif
6495
6496         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6497                 trace = TRUE;
6498
6499         /* Amount of stack space allocated by register saving code */
6500         pos = 0;
6501
6502         /* Offset between RSP and the CFA */
6503         cfa_offset = 0;
6504
6505         /*
6506          * The prolog consists of the following parts:
6507          * FP present:
6508          * - push rbp, mov rbp, rsp
6509          * - save callee saved regs using pushes
6510          * - allocate frame
6511          * - save rgctx if needed
6512          * - save lmf if needed
6513          * FP not present:
6514          * - allocate frame
6515          * - save rgctx if needed
6516          * - save lmf if needed
6517          * - save callee saved regs using moves
6518          */
6519
6520         // CFA = sp + 8
6521         cfa_offset = 8;
6522         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6523         // IP saved at CFA - 8
6524         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6525         async_exc_point (code);
6526         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6527
6528         if (!cfg->arch.omit_fp) {
6529                 amd64_push_reg (code, AMD64_RBP);
6530                 cfa_offset += 8;
6531                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6532                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6533                 async_exc_point (code);
6534 #ifdef HOST_WIN32
6535                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6536 #endif
6537                 /* These are handled automatically by the stack marking code */
6538                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6539
6540                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6541                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6542                 async_exc_point (code);
6543 #ifdef HOST_WIN32
6544                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6545 #endif
6546         }
6547
6548         /* The param area is always at offset 0 from sp */
6549         /* This needs to be allocated here, since it has to come after the spill area */
6550         if (cfg->param_area) {
6551                 if (cfg->arch.omit_fp)
6552                         // FIXME:
6553                         g_assert_not_reached ();
6554                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6555         }
6556
6557         if (cfg->arch.omit_fp) {
6558                 /*
6559                  * On enter, the stack is misaligned by the pushing of the return
6560                  * address. It is either made aligned by the pushing of %rbp, or by
6561                  * this.
6562                  */
6563                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6564                 if ((alloc_size % 16) == 0) {
6565                         alloc_size += 8;
6566                         /* Mark the padding slot as NOREF */
6567                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6568                 }
6569         } else {
6570                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6571                 if (cfg->stack_offset != alloc_size) {
6572                         /* Mark the padding slot as NOREF */
6573                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6574                 }
6575                 cfg->arch.sp_fp_offset = alloc_size;
6576                 alloc_size -= pos;
6577         }
6578
6579         cfg->arch.stack_alloc_size = alloc_size;
6580
6581         /* Allocate stack frame */
6582         if (alloc_size) {
6583                 /* See mono_emit_stack_alloc */
6584 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6585                 guint32 remaining_size = alloc_size;
6586                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6587                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6588                 guint32 offset = code - cfg->native_code;
6589                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6590                         while (required_code_size >= (cfg->code_size - offset))
6591                                 cfg->code_size *= 2;
6592                         cfg->native_code = mono_realloc_native_code (cfg);
6593                         code = cfg->native_code + offset;
6594                         cfg->stat_code_reallocs++;
6595                 }
6596
6597                 while (remaining_size >= 0x1000) {
6598                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6599                         if (cfg->arch.omit_fp) {
6600                                 cfa_offset += 0x1000;
6601                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6602                         }
6603                         async_exc_point (code);
6604 #ifdef HOST_WIN32
6605                         if (cfg->arch.omit_fp)
6606                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6607 #endif
6608
6609                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6610                         remaining_size -= 0x1000;
6611                 }
6612                 if (remaining_size) {
6613                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6614                         if (cfg->arch.omit_fp) {
6615                                 cfa_offset += remaining_size;
6616                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6617                                 async_exc_point (code);
6618                         }
6619 #ifdef HOST_WIN32
6620                         if (cfg->arch.omit_fp)
6621                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6622 #endif
6623                 }
6624 #else
6625                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6626                 if (cfg->arch.omit_fp) {
6627                         cfa_offset += alloc_size;
6628                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6629                         async_exc_point (code);
6630                 }
6631 #endif
6632         }
6633
6634         /* Stack alignment check */
6635 #if 0
6636         {
6637                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6638                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6639                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6640                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6641                 amd64_breakpoint (code);
6642         }
6643 #endif
6644
6645         if (mini_get_debug_options ()->init_stacks) {
6646                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6647
6648                 /* Save registers to the red zone */
6649                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6650                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6651
6652                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6653                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6654                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6655
6656                 amd64_cld (code);
6657 #if defined(__default_codegen__)
6658                 amd64_prefix (code, X86_REP_PREFIX);
6659                 amd64_stosl (code);
6660 #elif defined(__native_client_codegen__)
6661                 /* NaCl stos pseudo-instruction */
6662                 amd64_codegen_pre (code);
6663                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6664                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6665                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6666                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6667                 amd64_prefix (code, X86_REP_PREFIX);
6668                 amd64_stosl (code);
6669                 amd64_codegen_post (code);
6670 #endif /* __native_client_codegen__ */
6671
6672                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6673                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6674         }
6675
6676         /* Save LMF */
6677         if (method->save_lmf)
6678                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6679
6680         /* Save callee saved registers */
6681         if (cfg->arch.omit_fp) {
6682                 save_area_offset = cfg->arch.reg_save_area_offset;
6683                 /* Save caller saved registers after sp is adjusted */
6684                 /* The registers are saved at the bottom of the frame */
6685                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6686         } else {
6687                 /* The registers are saved just below the saved rbp */
6688                 save_area_offset = cfg->arch.reg_save_area_offset;
6689         }
6690
6691         for (i = 0; i < AMD64_NREG; ++i) {
6692                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6693                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6694
6695                         if (cfg->arch.omit_fp) {
6696                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6697                                 /* These are handled automatically by the stack marking code */
6698                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6699                         } else {
6700                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6701                                 // FIXME: GC
6702                         }
6703
6704                         save_area_offset += 8;
6705                         async_exc_point (code);
6706                 }
6707         }
6708
6709         /* store runtime generic context */
6710         if (cfg->rgctx_var) {
6711                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6712                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6713
6714                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6715
6716                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6717                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6718         }
6719
6720         /* compute max_length in order to use short forward jumps */
6721         max_epilog_size = get_max_epilog_size (cfg);
6722         if (cfg->opt & MONO_OPT_BRANCH) {
6723                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6724                         MonoInst *ins;
6725                         int max_length = 0;
6726
6727                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6728                                 max_length += 6;
6729                         /* max alignment for loops */
6730                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6731                                 max_length += LOOP_ALIGNMENT;
6732 #ifdef __native_client_codegen__
6733                         /* max alignment for native client */
6734                         max_length += kNaClAlignment;
6735 #endif
6736
6737                         MONO_BB_FOR_EACH_INS (bb, ins) {
6738 #ifdef __native_client_codegen__
6739                                 {
6740                                         int space_in_block = kNaClAlignment -
6741                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6742                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6743                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6744                                                 max_length += space_in_block;
6745                                         }
6746                                 }
6747 #endif  /*__native_client_codegen__*/
6748                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6749                         }
6750
6751                         /* Take prolog and epilog instrumentation into account */
6752                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6753                                 max_length += max_epilog_size;
6754
6755                         bb->max_length = max_length;
6756                 }
6757         }
6758
6759         sig = mono_method_signature (method);
6760         pos = 0;
6761
6762         cinfo = cfg->arch.cinfo;
6763
6764         if (sig->ret->type != MONO_TYPE_VOID) {
6765                 /* Save volatile arguments to the stack */
6766                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6767                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6768         }
6769
6770         /* Keep this in sync with emit_load_volatile_arguments */
6771         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6772                 ArgInfo *ainfo = cinfo->args + i;
6773                 gint32 stack_offset;
6774                 MonoType *arg_type;
6775
6776                 ins = cfg->args [i];
6777
6778                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6779                         /* Unused arguments */
6780                         continue;
6781
6782                 if (sig->hasthis && (i == 0))
6783                         arg_type = &mono_defaults.object_class->byval_arg;
6784                 else
6785                         arg_type = sig->params [i - sig->hasthis];
6786
6787                 stack_offset = ainfo->offset + ARGS_OFFSET;
6788
6789                 if (cfg->globalra) {
6790                         /* All the other moves are done by the register allocator */
6791                         switch (ainfo->storage) {
6792                         case ArgInFloatSSEReg:
6793                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6794                                 break;
6795                         case ArgValuetypeInReg:
6796                                 for (quad = 0; quad < 2; quad ++) {
6797                                         switch (ainfo->pair_storage [quad]) {
6798                                         case ArgInIReg:
6799                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6800                                                 break;
6801                                         case ArgInFloatSSEReg:
6802                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6803                                                 break;
6804                                         case ArgInDoubleSSEReg:
6805                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6806                                                 break;
6807                                         case ArgNone:
6808                                                 break;
6809                                         default:
6810                                                 g_assert_not_reached ();
6811                                         }
6812                                 }
6813                                 break;
6814                         default:
6815                                 break;
6816                         }
6817
6818                         continue;
6819                 }
6820
6821                 /* Save volatile arguments to the stack */
6822                 if (ins->opcode != OP_REGVAR) {
6823                         switch (ainfo->storage) {
6824                         case ArgInIReg: {
6825                                 guint32 size = 8;
6826
6827                                 /* FIXME: I1 etc */
6828                                 /*
6829                                 if (stack_offset & 0x1)
6830                                         size = 1;
6831                                 else if (stack_offset & 0x2)
6832                                         size = 2;
6833                                 else if (stack_offset & 0x4)
6834                                         size = 4;
6835                                 else
6836                                         size = 8;
6837                                 */
6838                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6839
6840                                 /*
6841                                  * Save the original location of 'this',
6842                                  * get_generic_info_from_stack_frame () needs this to properly look up
6843                                  * the argument value during the handling of async exceptions.
6844                                  */
6845                                 if (ins == cfg->args [0]) {
6846                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6847                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6848                                 }
6849                                 break;
6850                         }
6851                         case ArgInFloatSSEReg:
6852                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6853                                 break;
6854                         case ArgInDoubleSSEReg:
6855                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6856                                 break;
6857                         case ArgValuetypeInReg:
6858                                 for (quad = 0; quad < 2; quad ++) {
6859                                         switch (ainfo->pair_storage [quad]) {
6860                                         case ArgInIReg:
6861                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6862                                                 break;
6863                                         case ArgInFloatSSEReg:
6864                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6865                                                 break;
6866                                         case ArgInDoubleSSEReg:
6867                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6868                                                 break;
6869                                         case ArgNone:
6870                                                 break;
6871                                         default:
6872                                                 g_assert_not_reached ();
6873                                         }
6874                                 }
6875                                 break;
6876                         case ArgValuetypeAddrInIReg:
6877                                 if (ainfo->pair_storage [0] == ArgInIReg)
6878                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6879                                 break;
6880                         default:
6881                                 break;
6882                         }
6883                 } else {
6884                         /* Argument allocated to (non-volatile) register */
6885                         switch (ainfo->storage) {
6886                         case ArgInIReg:
6887                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6888                                 break;
6889                         case ArgOnStack:
6890                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6891                                 break;
6892                         default:
6893                                 g_assert_not_reached ();
6894                         }
6895
6896                         if (ins == cfg->args [0]) {
6897                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6898                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6899                         }
6900                 }
6901         }
6902
6903         if (cfg->method->save_lmf)
6904                 args_clobbered = TRUE;
6905
6906         if (trace) {
6907                 args_clobbered = TRUE;
6908                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6909         }
6910
6911         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6912                 args_clobbered = TRUE;
6913
6914         /*
6915          * Optimize the common case of the first bblock making a call with the same
6916          * arguments as the method. This works because the arguments are still in their
6917          * original argument registers.
6918          * FIXME: Generalize this
6919          */
6920         if (!args_clobbered) {
6921                 MonoBasicBlock *first_bb = cfg->bb_entry;
6922                 MonoInst *next;
6923
6924                 next = mono_bb_first_ins (first_bb);
6925                 if (!next && first_bb->next_bb) {
6926                         first_bb = first_bb->next_bb;
6927                         next = mono_bb_first_ins (first_bb);
6928                 }
6929
6930                 if (first_bb->in_count > 1)
6931                         next = NULL;
6932
6933                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6934                         ArgInfo *ainfo = cinfo->args + i;
6935                         gboolean match = FALSE;
6936
6937                         ins = cfg->args [i];
6938                         if (ins->opcode != OP_REGVAR) {
6939                                 switch (ainfo->storage) {
6940                                 case ArgInIReg: {
6941                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6942                                                 if (next->dreg == ainfo->reg) {
6943                                                         NULLIFY_INS (next);
6944                                                         match = TRUE;
6945                                                 } else {
6946                                                         next->opcode = OP_MOVE;
6947                                                         next->sreg1 = ainfo->reg;
6948                                                         /* Only continue if the instruction doesn't change argument regs */
6949                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6950                                                                 match = TRUE;
6951                                                 }
6952                                         }
6953                                         break;
6954                                 }
6955                                 default:
6956                                         break;
6957                                 }
6958                         } else {
6959                                 /* Argument allocated to (non-volatile) register */
6960                                 switch (ainfo->storage) {
6961                                 case ArgInIReg:
6962                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6963                                                 NULLIFY_INS (next);
6964                                                 match = TRUE;
6965                                         }
6966                                         break;
6967                                 default:
6968                                         break;
6969                                 }
6970                         }
6971
6972                         if (match) {
6973                                 next = next->next;
6974                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6975                                 if (!next)
6976                                         break;
6977                         }
6978                 }
6979         }
6980
6981         if (cfg->gen_seq_points) {
6982                 MonoInst *info_var = cfg->arch.seq_point_info_var;
6983
6984                 /* Initialize seq_point_info_var */
6985                 if (cfg->compile_aot) {
6986                         /* Initialize the variable from a GOT slot */
6987                         /* Same as OP_AOTCONST */
6988                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6989                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
6990                         g_assert (info_var->opcode == OP_REGOFFSET);
6991                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
6992                 }
6993
6994                 /* Initialize ss_trigger_page_var */
6995                 ins = cfg->arch.ss_trigger_page_var;
6996
6997                 g_assert (ins->opcode == OP_REGOFFSET);
6998
6999                 if (cfg->compile_aot) {
7000                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7001                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7002                 } else {
7003                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7004                 }
7005                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7006         }
7007
7008         cfg->code_len = code - cfg->native_code;
7009
7010         g_assert (cfg->code_len < cfg->code_size);
7011
7012         return code;
7013 }
7014
7015 void
7016 mono_arch_emit_epilog (MonoCompile *cfg)
7017 {
7018         MonoMethod *method = cfg->method;
7019         int quad, pos, i;
7020         guint8 *code;
7021         int max_epilog_size;
7022         CallInfo *cinfo;
7023         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7024         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7025
7026         max_epilog_size = get_max_epilog_size (cfg);
7027
7028         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7029                 cfg->code_size *= 2;
7030                 cfg->native_code = mono_realloc_native_code (cfg);
7031                 cfg->stat_code_reallocs++;
7032         }
7033         code = cfg->native_code + cfg->code_len;
7034
7035         cfg->has_unwind_info_for_epilog = TRUE;
7036
7037         /* Mark the start of the epilog */
7038         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7039
7040         /* Save the uwind state which is needed by the out-of-line code */
7041         mono_emit_unwind_op_remember_state (cfg, code);
7042
7043         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7044                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7045
7046         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7047         pos = 0;
7048
7049         if (method->save_lmf) {
7050                 /* check if we need to restore protection of the stack after a stack overflow */
7051                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7052                         guint8 *patch;
7053                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7054                         /* we load the value in a separate instruction: this mechanism may be
7055                          * used later as a safer way to do thread interruption
7056                          */
7057                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7058                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7059                         patch = code;
7060                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7061                         /* note that the call trampoline will preserve eax/edx */
7062                         x86_call_reg (code, X86_ECX);
7063                         x86_patch (patch, code);
7064                 } else {
7065                         /* FIXME: maybe save the jit tls in the prolog */
7066                 }
7067                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7068                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7069                 }
7070         }
7071
7072         /* Restore callee saved regs */
7073         for (i = 0; i < AMD64_NREG; ++i) {
7074                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7075                         /* Restore only used_int_regs, not arch.saved_iregs */
7076                         if (cfg->used_int_regs & (1 << i)) {
7077                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7078                                 mono_emit_unwind_op_same_value (cfg, code, i);
7079                                 async_exc_point (code);
7080                         }
7081                         save_area_offset += 8;
7082                 }
7083         }
7084
7085         /* Load returned vtypes into registers if needed */
7086         cinfo = cfg->arch.cinfo;
7087         if (cinfo->ret.storage == ArgValuetypeInReg) {
7088                 ArgInfo *ainfo = &cinfo->ret;
7089                 MonoInst *inst = cfg->ret;
7090
7091                 for (quad = 0; quad < 2; quad ++) {
7092                         switch (ainfo->pair_storage [quad]) {
7093                         case ArgInIReg:
7094                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7095                                 break;
7096                         case ArgInFloatSSEReg:
7097                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7098                                 break;
7099                         case ArgInDoubleSSEReg:
7100                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7101                                 break;
7102                         case ArgNone:
7103                                 break;
7104                         default:
7105                                 g_assert_not_reached ();
7106                         }
7107                 }
7108         }
7109
7110         if (cfg->arch.omit_fp) {
7111                 if (cfg->arch.stack_alloc_size) {
7112                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7113                 }
7114         } else {
7115                 amd64_leave (code);
7116                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7117         }
7118         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7119         async_exc_point (code);
7120         amd64_ret (code);
7121
7122         /* Restore the unwind state to be the same as before the epilog */
7123         mono_emit_unwind_op_restore_state (cfg, code);
7124
7125         cfg->code_len = code - cfg->native_code;
7126
7127         g_assert (cfg->code_len < cfg->code_size);
7128 }
7129
7130 void
7131 mono_arch_emit_exceptions (MonoCompile *cfg)
7132 {
7133         MonoJumpInfo *patch_info;
7134         int nthrows, i;
7135         guint8 *code;
7136         MonoClass *exc_classes [16];
7137         guint8 *exc_throw_start [16], *exc_throw_end [16];
7138         guint32 code_size = 0;
7139
7140         /* Compute needed space */
7141         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7142                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7143                         code_size += 40;
7144                 if (patch_info->type == MONO_PATCH_INFO_R8)
7145                         code_size += 8 + 15; /* sizeof (double) + alignment */
7146                 if (patch_info->type == MONO_PATCH_INFO_R4)
7147                         code_size += 4 + 15; /* sizeof (float) + alignment */
7148                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7149                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7150         }
7151
7152 #ifdef __native_client_codegen__
7153         /* Give us extra room on Native Client.  This could be   */
7154         /* more carefully calculated, but bundle alignment makes */
7155         /* it much trickier, so *2 like other places is good.    */
7156         code_size *= 2;
7157 #endif
7158
7159         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7160                 cfg->code_size *= 2;
7161                 cfg->native_code = mono_realloc_native_code (cfg);
7162                 cfg->stat_code_reallocs++;
7163         }
7164
7165         code = cfg->native_code + cfg->code_len;
7166
7167         /* add code to raise exceptions */
7168         nthrows = 0;
7169         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7170                 switch (patch_info->type) {
7171                 case MONO_PATCH_INFO_EXC: {
7172                         MonoClass *exc_class;
7173                         guint8 *buf, *buf2;
7174                         guint32 throw_ip;
7175
7176                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7177
7178                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7179                         g_assert (exc_class);
7180                         throw_ip = patch_info->ip.i;
7181
7182                         //x86_breakpoint (code);
7183                         /* Find a throw sequence for the same exception class */
7184                         for (i = 0; i < nthrows; ++i)
7185                                 if (exc_classes [i] == exc_class)
7186                                         break;
7187                         if (i < nthrows) {
7188                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7189                                 x86_jump_code (code, exc_throw_start [i]);
7190                                 patch_info->type = MONO_PATCH_INFO_NONE;
7191                         }
7192                         else {
7193                                 buf = code;
7194                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7195                                 buf2 = code;
7196
7197                                 if (nthrows < 16) {
7198                                         exc_classes [nthrows] = exc_class;
7199                                         exc_throw_start [nthrows] = code;
7200                                 }
7201                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7202
7203                                 patch_info->type = MONO_PATCH_INFO_NONE;
7204
7205                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7206
7207                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7208                                 while (buf < buf2)
7209                                         x86_nop (buf);
7210
7211                                 if (nthrows < 16) {
7212                                         exc_throw_end [nthrows] = code;
7213                                         nthrows ++;
7214                                 }
7215                         }
7216                         break;
7217                 }
7218                 default:
7219                         /* do nothing */
7220                         break;
7221                 }
7222                 g_assert(code < cfg->native_code + cfg->code_size);
7223         }
7224
7225         /* Handle relocations with RIP relative addressing */
7226         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7227                 gboolean remove = FALSE;
7228                 guint8 *orig_code = code;
7229
7230                 switch (patch_info->type) {
7231                 case MONO_PATCH_INFO_R8:
7232                 case MONO_PATCH_INFO_R4: {
7233                         guint8 *pos, *patch_pos;
7234                         guint32 target_pos;
7235
7236                         /* The SSE opcodes require a 16 byte alignment */
7237 #if defined(__default_codegen__)
7238                         code = (guint8*)ALIGN_TO (code, 16);
7239 #elif defined(__native_client_codegen__)
7240                         {
7241                                 /* Pad this out with HLT instructions  */
7242                                 /* or we can get garbage bytes emitted */
7243                                 /* which will fail validation          */
7244                                 guint8 *aligned_code;
7245                                 /* extra align to make room for  */
7246                                 /* mov/push below                      */
7247                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7248                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7249                                 /* The technique of hiding data in an  */
7250                                 /* instruction has a problem here: we  */
7251                                 /* need the data aligned to a 16-byte  */
7252                                 /* boundary but the instruction cannot */
7253                                 /* cross the bundle boundary. so only  */
7254                                 /* odd multiples of 16 can be used     */
7255                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7256                                         aligned_code += 16;
7257                                 }
7258                                 while (code < aligned_code) {
7259                                         *(code++) = 0xf4; /* hlt */
7260                                 }
7261                         }
7262 #endif
7263
7264                         pos = cfg->native_code + patch_info->ip.i;
7265                         if (IS_REX (pos [1])) {
7266                                 patch_pos = pos + 5;
7267                                 target_pos = code - pos - 9;
7268                         }
7269                         else {
7270                                 patch_pos = pos + 4;
7271                                 target_pos = code - pos - 8;
7272                         }
7273
7274                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7275 #ifdef __native_client_codegen__
7276                                 /* Hide 64-bit data in a         */
7277                                 /* "mov imm64, r11" instruction. */
7278                                 /* write it before the start of  */
7279                                 /* the data*/
7280                                 *(code-2) = 0x49; /* prefix      */
7281                                 *(code-1) = 0xbb; /* mov X, %r11 */
7282 #endif
7283                                 *(double*)code = *(double*)patch_info->data.target;
7284                                 code += sizeof (double);
7285                         } else {
7286 #ifdef __native_client_codegen__
7287                                 /* Hide 32-bit data in a        */
7288                                 /* "push imm32" instruction.    */
7289                                 *(code-1) = 0x68; /* push */
7290 #endif
7291                                 *(float*)code = *(float*)patch_info->data.target;
7292                                 code += sizeof (float);
7293                         }
7294
7295                         *(guint32*)(patch_pos) = target_pos;
7296
7297                         remove = TRUE;
7298                         break;
7299                 }
7300                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7301                         guint8 *pos;
7302
7303                         if (cfg->compile_aot)
7304                                 continue;
7305
7306                         /*loading is faster against aligned addresses.*/
7307                         code = (guint8*)ALIGN_TO (code, 8);
7308                         memset (orig_code, 0, code - orig_code);
7309
7310                         pos = cfg->native_code + patch_info->ip.i;
7311
7312                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7313                         if (IS_REX (pos [1]))
7314                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7315                         else
7316                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7317
7318                         *(gpointer*)code = (gpointer)patch_info->data.target;
7319                         code += sizeof (gpointer);
7320
7321                         remove = TRUE;
7322                         break;
7323                 }
7324                 default:
7325                         break;
7326                 }
7327
7328                 if (remove) {
7329                         if (patch_info == cfg->patch_info)
7330                                 cfg->patch_info = patch_info->next;
7331                         else {
7332                                 MonoJumpInfo *tmp;
7333
7334                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7335                                         ;
7336                                 tmp->next = patch_info->next;
7337                         }
7338                 }
7339                 g_assert (code < cfg->native_code + cfg->code_size);
7340         }
7341
7342         cfg->code_len = code - cfg->native_code;
7343
7344         g_assert (cfg->code_len < cfg->code_size);
7345
7346 }
7347
7348 #endif /* DISABLE_JIT */
7349
7350 void*
7351 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7352 {
7353         guchar *code = p;
7354         CallInfo *cinfo = NULL;
7355         MonoMethodSignature *sig;
7356         MonoInst *inst;
7357         int i, n, stack_area = 0;
7358
7359         /* Keep this in sync with mono_arch_get_argument_info */
7360
7361         if (enable_arguments) {
7362                 /* Allocate a new area on the stack and save arguments there */
7363                 sig = mono_method_signature (cfg->method);
7364
7365                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7366
7367                 n = sig->param_count + sig->hasthis;
7368
7369                 stack_area = ALIGN_TO (n * 8, 16);
7370
7371                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7372
7373                 for (i = 0; i < n; ++i) {
7374                         inst = cfg->args [i];
7375
7376                         if (inst->opcode == OP_REGVAR)
7377                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7378                         else {
7379                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7380                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7381                         }
7382                 }
7383         }
7384
7385         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7386         amd64_set_reg_template (code, AMD64_ARG_REG1);
7387         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7388         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7389
7390         if (enable_arguments)
7391                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7392
7393         return code;
7394 }
7395
7396 enum {
7397         SAVE_NONE,
7398         SAVE_STRUCT,
7399         SAVE_EAX,
7400         SAVE_EAX_EDX,
7401         SAVE_XMM
7402 };
7403
7404 void*
7405 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7406 {
7407         guchar *code = p;
7408         int save_mode = SAVE_NONE;
7409         MonoMethod *method = cfg->method;
7410         MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7411         int i;
7412
7413         switch (ret_type->type) {
7414         case MONO_TYPE_VOID:
7415                 /* special case string .ctor icall */
7416                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7417                         save_mode = SAVE_EAX;
7418                 else
7419                         save_mode = SAVE_NONE;
7420                 break;
7421         case MONO_TYPE_I8:
7422         case MONO_TYPE_U8:
7423                 save_mode = SAVE_EAX;
7424                 break;
7425         case MONO_TYPE_R4:
7426         case MONO_TYPE_R8:
7427                 save_mode = SAVE_XMM;
7428                 break;
7429         case MONO_TYPE_GENERICINST:
7430                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7431                         save_mode = SAVE_EAX;
7432                         break;
7433                 }
7434                 /* Fall through */
7435         case MONO_TYPE_VALUETYPE:
7436                 save_mode = SAVE_STRUCT;
7437                 break;
7438         default:
7439                 save_mode = SAVE_EAX;
7440                 break;
7441         }
7442
7443         /* Save the result and copy it into the proper argument register */
7444         switch (save_mode) {
7445         case SAVE_EAX:
7446                 amd64_push_reg (code, AMD64_RAX);
7447                 /* Align stack */
7448                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7449                 if (enable_arguments)
7450                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7451                 break;
7452         case SAVE_STRUCT:
7453                 /* FIXME: */
7454                 if (enable_arguments)
7455                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7456                 break;
7457         case SAVE_XMM:
7458                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7459                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7460                 /* Align stack */
7461                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7462                 /*
7463                  * The result is already in the proper argument register so no copying
7464                  * needed.
7465                  */
7466                 break;
7467         case SAVE_NONE:
7468                 break;
7469         default:
7470                 g_assert_not_reached ();
7471         }
7472
7473         /* Set %al since this is a varargs call */
7474         if (save_mode == SAVE_XMM)
7475                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7476         else
7477                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7478
7479         if (preserve_argument_registers) {
7480                 for (i = 0; i < PARAM_REGS; ++i)
7481                         amd64_push_reg (code, param_regs [i]);
7482         }
7483
7484         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7485         amd64_set_reg_template (code, AMD64_ARG_REG1);
7486         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7487
7488         if (preserve_argument_registers) {
7489                 for (i = PARAM_REGS - 1; i >= 0; --i)
7490                         amd64_pop_reg (code, param_regs [i]);
7491         }
7492
7493         /* Restore result */
7494         switch (save_mode) {
7495         case SAVE_EAX:
7496                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7497                 amd64_pop_reg (code, AMD64_RAX);
7498                 break;
7499         case SAVE_STRUCT:
7500                 /* FIXME: */
7501                 break;
7502         case SAVE_XMM:
7503                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7504                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7505                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7506                 break;
7507         case SAVE_NONE:
7508                 break;
7509         default:
7510                 g_assert_not_reached ();
7511         }
7512
7513         return code;
7514 }
7515
7516 void
7517 mono_arch_flush_icache (guint8 *code, gint size)
7518 {
7519         /* Not needed */
7520 }
7521
7522 void
7523 mono_arch_flush_register_windows (void)
7524 {
7525 }
7526
7527 gboolean
7528 mono_arch_is_inst_imm (gint64 imm)
7529 {
7530         return amd64_is_imm32 (imm);
7531 }
7532
7533 /*
7534  * Determine whenever the trap whose info is in SIGINFO is caused by
7535  * integer overflow.
7536  */
7537 gboolean
7538 mono_arch_is_int_overflow (void *sigctx, void *info)
7539 {
7540         MonoContext ctx;
7541         guint8* rip;
7542         int reg;
7543         gint64 value;
7544
7545         mono_sigctx_to_monoctx (sigctx, &ctx);
7546
7547         rip = (guint8*)ctx.rip;
7548
7549         if (IS_REX (rip [0])) {
7550                 reg = amd64_rex_b (rip [0]);
7551                 rip ++;
7552         }
7553         else
7554                 reg = 0;
7555
7556         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7557                 /* idiv REG */
7558                 reg += x86_modrm_rm (rip [1]);
7559
7560                 switch (reg) {
7561                 case AMD64_RAX:
7562                         value = ctx.rax;
7563                         break;
7564                 case AMD64_RBX:
7565                         value = ctx.rbx;
7566                         break;
7567                 case AMD64_RCX:
7568                         value = ctx.rcx;
7569                         break;
7570                 case AMD64_RDX:
7571                         value = ctx.rdx;
7572                         break;
7573                 case AMD64_RBP:
7574                         value = ctx.rbp;
7575                         break;
7576                 case AMD64_RSP:
7577                         value = ctx.rsp;
7578                         break;
7579                 case AMD64_RSI:
7580                         value = ctx.rsi;
7581                         break;
7582                 case AMD64_RDI:
7583                         value = ctx.rdi;
7584                         break;
7585                 case AMD64_R12:
7586                         value = ctx.r12;
7587                         break;
7588                 case AMD64_R13:
7589                         value = ctx.r13;
7590                         break;
7591                 case AMD64_R14:
7592                         value = ctx.r14;
7593                         break;
7594                 case AMD64_R15:
7595                         value = ctx.r15;
7596                         break;
7597                 default:
7598                         g_assert_not_reached ();
7599                         reg = -1;
7600                 }
7601
7602                 if (value == -1)
7603                         return TRUE;
7604         }
7605
7606         return FALSE;
7607 }
7608
7609 guint32
7610 mono_arch_get_patch_offset (guint8 *code)
7611 {
7612         return 3;
7613 }
7614
7615 /**
7616  * mono_breakpoint_clean_code:
7617  *
7618  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7619  * breakpoints in the original code, they are removed in the copy.
7620  *
7621  * Returns TRUE if no sw breakpoint was present.
7622  */
7623 gboolean
7624 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7625 {
7626         int i;
7627         gboolean can_write = TRUE;
7628         /*
7629          * If method_start is non-NULL we need to perform bound checks, since we access memory
7630          * at code - offset we could go before the start of the method and end up in a different
7631          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7632          * instead.
7633          */
7634         if (!method_start || code - offset >= method_start) {
7635                 memcpy (buf, code - offset, size);
7636         } else {
7637                 int diff = code - method_start;
7638                 memset (buf, 0, size);
7639                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7640         }
7641         code -= offset;
7642         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7643                 int idx = mono_breakpoint_info_index [i];
7644                 guint8 *ptr;
7645                 if (idx < 1)
7646                         continue;
7647                 ptr = mono_breakpoint_info [idx].address;
7648                 if (ptr >= code && ptr < code + size) {
7649                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7650                         can_write = FALSE;
7651                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7652                         buf [ptr - code] = saved_byte;
7653                 }
7654         }
7655         return can_write;
7656 }
7657
7658 #if defined(__native_client_codegen__)
7659 /* For membase calls, we want the base register. for Native Client,  */
7660 /* all indirect calls have the following sequence with the given sizes: */
7661 /* mov %eXX,%eXX                                [2-3]   */
7662 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7663 /* and $0xffffffffffffffe0,%r11d                [4]     */
7664 /* add %r15,%r11                                [3]     */
7665 /* callq *%r11                                  [3]     */
7666
7667
7668 /* Determine if code points to a NaCl call-through-register sequence, */
7669 /* (i.e., the last 3 instructions listed above) */
7670 int
7671 is_nacl_call_reg_sequence(guint8* code)
7672 {
7673         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7674                                "\x4d\x03\xdf"     /* add */
7675                                "\x41\xff\xd3";   /* call */
7676         return memcmp(code, sequence, 10) == 0;
7677 }
7678
7679 /* Determine if code points to the first opcode of the mov membase component */
7680 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7681 /* (there could be a REX prefix before the opcode but it is ignored) */
7682 static int
7683 is_nacl_indirect_call_membase_sequence(guint8* code)
7684 {
7685                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7686         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7687                /* and that src reg = dest reg */
7688                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7689                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7690                IS_REX(code[2]) &&
7691                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7692                /* and has dst of r11 and base of r15 */
7693                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7694                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7695 }
7696 #endif /* __native_client_codegen__ */
7697
7698 int
7699 mono_arch_get_this_arg_reg (guint8 *code)
7700 {
7701         return AMD64_ARG_REG1;
7702 }
7703
7704 gpointer
7705 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7706 {
7707         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7708 }
7709
7710 #define MAX_ARCH_DELEGATE_PARAMS 10
7711
7712 static gpointer
7713 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7714 {
7715         guint8 *code, *start;
7716         int i;
7717
7718         if (has_target) {
7719                 start = code = mono_global_codeman_reserve (64);
7720
7721                 /* Replace the this argument with the target */
7722                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7723                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7724                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7725
7726                 g_assert ((code - start) < 64);
7727         } else {
7728                 start = code = mono_global_codeman_reserve (64);
7729
7730                 if (param_count == 0) {
7731                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7732                 } else {
7733                         /* We have to shift the arguments left */
7734                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7735                         for (i = 0; i < param_count; ++i) {
7736 #ifdef HOST_WIN32
7737                                 if (i < 3)
7738                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7739                                 else
7740                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7741 #else
7742                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7743 #endif
7744                         }
7745
7746                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7747                 }
7748                 g_assert ((code - start) < 64);
7749         }
7750
7751         nacl_global_codeman_validate (&start, 64, &code);
7752
7753         if (code_len)
7754                 *code_len = code - start;
7755
7756         if (mono_jit_map_is_enabled ()) {
7757                 char *buff;
7758                 if (has_target)
7759                         buff = (char*)"delegate_invoke_has_target";
7760                 else
7761                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7762                 mono_emit_jit_tramp (start, code - start, buff);
7763                 if (!has_target)
7764                         g_free (buff);
7765         }
7766         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7767
7768         return start;
7769 }
7770
7771 /*
7772  * mono_arch_get_delegate_invoke_impls:
7773  *
7774  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7775  * trampolines.
7776  */
7777 GSList*
7778 mono_arch_get_delegate_invoke_impls (void)
7779 {
7780         GSList *res = NULL;
7781         guint8 *code;
7782         guint32 code_len;
7783         int i;
7784         char *tramp_name;
7785
7786         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7787         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7788
7789         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7790                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7791                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7792                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7793                 g_free (tramp_name);
7794         }
7795
7796         return res;
7797 }
7798
7799 gpointer
7800 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7801 {
7802         guint8 *code, *start;
7803         int i;
7804
7805         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7806                 return NULL;
7807
7808         /* FIXME: Support more cases */
7809         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7810                 return NULL;
7811
7812         if (has_target) {
7813                 static guint8* cached = NULL;
7814
7815                 if (cached)
7816                         return cached;
7817
7818                 if (mono_aot_only)
7819                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7820                 else
7821                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7822
7823                 mono_memory_barrier ();
7824
7825                 cached = start;
7826         } else {
7827                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7828                 for (i = 0; i < sig->param_count; ++i)
7829                         if (!mono_is_regsize_var (sig->params [i]))
7830                                 return NULL;
7831                 if (sig->param_count > 4)
7832                         return NULL;
7833
7834                 code = cache [sig->param_count];
7835                 if (code)
7836                         return code;
7837
7838                 if (mono_aot_only) {
7839                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7840                         start = mono_aot_get_trampoline (name);
7841                         g_free (name);
7842                 } else {
7843                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7844                 }
7845
7846                 mono_memory_barrier ();
7847
7848                 cache [sig->param_count] = start;
7849         }
7850
7851         return start;
7852 }
7853
7854 gpointer
7855 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7856 {
7857         guint8 *code, *start;
7858         int size = 20;
7859
7860         start = code = mono_global_codeman_reserve (size);
7861
7862         /* Replace the this argument with the target */
7863         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7864         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7865
7866         if (load_imt_reg) {
7867                 /* Load the IMT reg */
7868                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7869         }
7870
7871         /* Load the vtable */
7872         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7873         amd64_jump_membase (code, AMD64_RAX, offset);
7874         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7875
7876         return start;
7877 }
7878
7879 void
7880 mono_arch_finish_init (void)
7881 {
7882 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7883         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7884 #endif
7885 }
7886
7887 void
7888 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7889 {
7890 }
7891
7892 #if defined(__default_codegen__)
7893 #define CMP_SIZE (6 + 1)
7894 #define CMP_REG_REG_SIZE (4 + 1)
7895 #define BR_SMALL_SIZE 2
7896 #define BR_LARGE_SIZE 6
7897 #define MOV_REG_IMM_SIZE 10
7898 #define MOV_REG_IMM_32BIT_SIZE 6
7899 #define JUMP_REG_SIZE (2 + 1)
7900 #elif defined(__native_client_codegen__)
7901 /* NaCl N-byte instructions can be padded up to N-1 bytes */
7902 #define CMP_SIZE ((6 + 1) * 2 - 1)
7903 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
7904 #define BR_SMALL_SIZE (2 * 2 - 1)
7905 #define BR_LARGE_SIZE (6 * 2 - 1)
7906 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
7907 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
7908 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
7909 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
7910 /* Jump membase's size is large and unpredictable    */
7911 /* in native client, just pad it out a whole bundle. */
7912 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
7913 #endif
7914
7915 static int
7916 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7917 {
7918         int i, distance = 0;
7919         for (i = start; i < target; ++i)
7920                 distance += imt_entries [i]->chunk_size;
7921         return distance;
7922 }
7923
7924 /*
7925  * LOCKING: called with the domain lock held
7926  */
7927 gpointer
7928 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7929         gpointer fail_tramp)
7930 {
7931         int i;
7932         int size = 0;
7933         guint8 *code, *start;
7934         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7935
7936         for (i = 0; i < count; ++i) {
7937                 MonoIMTCheckItem *item = imt_entries [i];
7938                 if (item->is_equals) {
7939                         if (item->check_target_idx) {
7940                                 if (!item->compare_done) {
7941                                         if (amd64_is_imm32 (item->key))
7942                                                 item->chunk_size += CMP_SIZE;
7943                                         else
7944                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7945                                 }
7946                                 if (item->has_target_code) {
7947                                         item->chunk_size += MOV_REG_IMM_SIZE;
7948                                 } else {
7949                                         if (vtable_is_32bit)
7950                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7951                                         else
7952                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7953 #ifdef __native_client_codegen__
7954                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7955 #endif
7956                                 }
7957                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7958                         } else {
7959                                 if (fail_tramp) {
7960                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7961                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7962                                 } else {
7963                                         if (vtable_is_32bit)
7964                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7965                                         else
7966                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7967                                         item->chunk_size += JUMP_REG_SIZE;
7968                                         /* with assert below:
7969                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7970                                          */
7971 #ifdef __native_client_codegen__
7972                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7973 #endif
7974                                 }
7975                         }
7976                 } else {
7977                         if (amd64_is_imm32 (item->key))
7978                                 item->chunk_size += CMP_SIZE;
7979                         else
7980                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7981                         item->chunk_size += BR_LARGE_SIZE;
7982                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7983                 }
7984                 size += item->chunk_size;
7985         }
7986 #if defined(__native_client__) && defined(__native_client_codegen__)
7987         /* In Native Client, we don't re-use thunks, allocate from the */
7988         /* normal code manager paths. */
7989         code = mono_domain_code_reserve (domain, size);
7990 #else
7991         if (fail_tramp)
7992                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7993         else
7994                 code = mono_domain_code_reserve (domain, size);
7995 #endif
7996         start = code;
7997         for (i = 0; i < count; ++i) {
7998                 MonoIMTCheckItem *item = imt_entries [i];
7999                 item->code_target = code;
8000                 if (item->is_equals) {
8001                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8002
8003                         if (item->check_target_idx || fail_case) {
8004                                 if (!item->compare_done || fail_case) {
8005                                         if (amd64_is_imm32 (item->key))
8006                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8007                                         else {
8008                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8009                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8010                                         }
8011                                 }
8012                                 item->jmp_code = code;
8013                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8014                                 if (item->has_target_code) {
8015                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8016                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8017                                 } else {
8018                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8019                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8020                                 }
8021
8022                                 if (fail_case) {
8023                                         amd64_patch (item->jmp_code, code);
8024                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8025                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8026                                         item->jmp_code = NULL;
8027                                 }
8028                         } else {
8029                                 /* enable the commented code to assert on wrong method */
8030 #if 0
8031                                 if (amd64_is_imm32 (item->key))
8032                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8033                                 else {
8034                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8035                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8036                                 }
8037                                 item->jmp_code = code;
8038                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8039                                 /* See the comment below about R10 */
8040                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8041                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8042                                 amd64_patch (item->jmp_code, code);
8043                                 amd64_breakpoint (code);
8044                                 item->jmp_code = NULL;
8045 #else
8046                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8047                                    needs to be preserved.  R10 needs
8048                                    to be preserved for calls which
8049                                    require a runtime generic context,
8050                                    but interface calls don't. */
8051                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8052                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8053 #endif
8054                         }
8055                 } else {
8056                         if (amd64_is_imm32 (item->key))
8057                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8058                         else {
8059                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8060                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8061                         }
8062                         item->jmp_code = code;
8063                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8064                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8065                         else
8066                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8067                 }
8068                 g_assert (code - item->code_target <= item->chunk_size);
8069         }
8070         /* patch the branches to get to the target items */
8071         for (i = 0; i < count; ++i) {
8072                 MonoIMTCheckItem *item = imt_entries [i];
8073                 if (item->jmp_code) {
8074                         if (item->check_target_idx) {
8075                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8076                         }
8077                 }
8078         }
8079
8080         if (!fail_tramp)
8081                 mono_stats.imt_thunks_size += code - start;
8082         g_assert (code - start <= size);
8083
8084         nacl_domain_code_validate(domain, &start, size, &code);
8085         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8086
8087         return start;
8088 }
8089
8090 MonoMethod*
8091 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8092 {
8093         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8094 }
8095
8096 MonoVTable*
8097 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8098 {
8099         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8100 }
8101
8102 GSList*
8103 mono_arch_get_cie_program (void)
8104 {
8105         GSList *l = NULL;
8106
8107         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8108         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8109
8110         return l;
8111 }
8112
8113 MonoInst*
8114 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8115 {
8116         MonoInst *ins = NULL;
8117         int opcode = 0;
8118
8119         if (cmethod->klass == mono_defaults.math_class) {
8120                 if (strcmp (cmethod->name, "Sin") == 0) {
8121                         opcode = OP_SIN;
8122                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8123                         opcode = OP_COS;
8124                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8125                         opcode = OP_SQRT;
8126                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8127                         opcode = OP_ABS;
8128                 }
8129
8130                 if (opcode) {
8131                         MONO_INST_NEW (cfg, ins, opcode);
8132                         ins->type = STACK_R8;
8133                         ins->dreg = mono_alloc_freg (cfg);
8134                         ins->sreg1 = args [0]->dreg;
8135                         MONO_ADD_INS (cfg->cbb, ins);
8136                 }
8137
8138                 opcode = 0;
8139                 if (cfg->opt & MONO_OPT_CMOV) {
8140                         if (strcmp (cmethod->name, "Min") == 0) {
8141                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8142                                         opcode = OP_IMIN;
8143                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8144                                         opcode = OP_IMIN_UN;
8145                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8146                                         opcode = OP_LMIN;
8147                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8148                                         opcode = OP_LMIN_UN;
8149                         } else if (strcmp (cmethod->name, "Max") == 0) {
8150                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8151                                         opcode = OP_IMAX;
8152                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8153                                         opcode = OP_IMAX_UN;
8154                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8155                                         opcode = OP_LMAX;
8156                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8157                                         opcode = OP_LMAX_UN;
8158                         }
8159                 }
8160
8161                 if (opcode) {
8162                         MONO_INST_NEW (cfg, ins, opcode);
8163                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8164                         ins->dreg = mono_alloc_ireg (cfg);
8165                         ins->sreg1 = args [0]->dreg;
8166                         ins->sreg2 = args [1]->dreg;
8167                         MONO_ADD_INS (cfg->cbb, ins);
8168                 }
8169
8170 #if 0
8171                 /* OP_FREM is not IEEE compatible */
8172                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8173                         MONO_INST_NEW (cfg, ins, OP_FREM);
8174                         ins->inst_i0 = args [0];
8175                         ins->inst_i1 = args [1];
8176                 }
8177 #endif
8178         }
8179
8180         /*
8181          * Can't implement CompareExchange methods this way since they have
8182          * three arguments.
8183          */
8184
8185         return ins;
8186 }
8187
8188 gboolean
8189 mono_arch_print_tree (MonoInst *tree, int arity)
8190 {
8191         return 0;
8192 }
8193
8194 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8195
8196 mgreg_t
8197 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8198 {
8199         switch (reg) {
8200         case AMD64_RCX: return ctx->rcx;
8201         case AMD64_RDX: return ctx->rdx;
8202         case AMD64_RBX: return ctx->rbx;
8203         case AMD64_RBP: return ctx->rbp;
8204         case AMD64_RSP: return ctx->rsp;
8205         default:
8206                 return _CTX_REG (ctx, rax, reg);
8207         }
8208 }
8209
8210 void
8211 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8212 {
8213         switch (reg) {
8214         case AMD64_RCX:
8215                 ctx->rcx = val;
8216                 break;
8217         case AMD64_RDX:
8218                 ctx->rdx = val;
8219                 break;
8220         case AMD64_RBX:
8221                 ctx->rbx = val;
8222                 break;
8223         case AMD64_RBP:
8224                 ctx->rbp = val;
8225                 break;
8226         case AMD64_RSP:
8227                 ctx->rsp = val;
8228                 break;
8229         default:
8230                 _CTX_REG (ctx, rax, reg) = val;
8231         }
8232 }
8233
8234 gpointer
8235 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8236 {
8237         gpointer *sp, old_value;
8238         char *bp;
8239
8240         /*Load the spvar*/
8241         bp = MONO_CONTEXT_GET_BP (ctx);
8242         sp = *(gpointer*)(bp + clause->exvar_offset);
8243
8244         old_value = *sp;
8245         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8246                 return old_value;
8247
8248         *sp = new_value;
8249
8250         return old_value;
8251 }
8252
8253 /*
8254  * mono_arch_emit_load_aotconst:
8255  *
8256  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8257  * TARGET from the mscorlib GOT in full-aot code.
8258  * On AMD64, the result is placed into R11.
8259  */
8260 guint8*
8261 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8262 {
8263         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8264         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8265
8266         return code;
8267 }
8268
8269 /*
8270  * mono_arch_get_trampolines:
8271  *
8272  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8273  * for AOT.
8274  */
8275 GSList *
8276 mono_arch_get_trampolines (gboolean aot)
8277 {
8278         return mono_amd64_get_exception_trampolines (aot);
8279 }
8280
8281 /* Soft Debug support */
8282 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8283
8284 /*
8285  * mono_arch_set_breakpoint:
8286  *
8287  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8288  * The location should contain code emitted by OP_SEQ_POINT.
8289  */
8290 void
8291 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8292 {
8293         guint8 *code = ip;
8294         guint8 *orig_code = code;
8295
8296         if (ji->from_aot) {
8297                 guint32 native_offset = ip - (guint8*)ji->code_start;
8298                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8299
8300                 g_assert (info->bp_addrs [native_offset] == 0);
8301                 info->bp_addrs [native_offset] = bp_trigger_page;
8302         } else {
8303                 /*
8304                  * In production, we will use int3 (has to fix the size in the md
8305                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8306                  * instead.
8307                  */
8308                 g_assert (code [0] == 0x90);
8309                 if (breakpoint_size == 8) {
8310                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8311                 } else {
8312                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8313                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8314                 }
8315
8316                 g_assert (code - orig_code == breakpoint_size);
8317         }
8318 }
8319
8320 /*
8321  * mono_arch_clear_breakpoint:
8322  *
8323  *   Clear the breakpoint at IP.
8324  */
8325 void
8326 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8327 {
8328         guint8 *code = ip;
8329         int i;
8330
8331         if (ji->from_aot) {
8332                 guint32 native_offset = ip - (guint8*)ji->code_start;
8333                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8334
8335                 g_assert (info->bp_addrs [native_offset] == 0);
8336                 info->bp_addrs [native_offset] = info;
8337         } else {
8338                 for (i = 0; i < breakpoint_size; ++i)
8339                         x86_nop (code);
8340         }
8341 }
8342
8343 gboolean
8344 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8345 {
8346 #ifdef HOST_WIN32
8347         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8348         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8349                 return TRUE;
8350         else
8351                 return FALSE;
8352 #else
8353         siginfo_t* sinfo = (siginfo_t*) info;
8354         /* Sometimes the address is off by 4 */
8355         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8356                 return TRUE;
8357         else
8358                 return FALSE;
8359 #endif
8360 }
8361
8362 /*
8363  * mono_arch_skip_breakpoint:
8364  *
8365  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8366  * we resume, the instruction is not executed again.
8367  */
8368 void
8369 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8370 {
8371         if (ji->from_aot) {
8372                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8373                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8374         } else {
8375                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8376         }
8377 }
8378
8379 /*
8380  * mono_arch_start_single_stepping:
8381  *
8382  *   Start single stepping.
8383  */
8384 void
8385 mono_arch_start_single_stepping (void)
8386 {
8387         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8388 }
8389
8390 /*
8391  * mono_arch_stop_single_stepping:
8392  *
8393  *   Stop single stepping.
8394  */
8395 void
8396 mono_arch_stop_single_stepping (void)
8397 {
8398         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8399 }
8400
8401 /*
8402  * mono_arch_is_single_step_event:
8403  *
8404  *   Return whenever the machine state in SIGCTX corresponds to a single
8405  * step event.
8406  */
8407 gboolean
8408 mono_arch_is_single_step_event (void *info, void *sigctx)
8409 {
8410 #ifdef HOST_WIN32
8411         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8412         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8413                 return TRUE;
8414         else
8415                 return FALSE;
8416 #else
8417         siginfo_t* sinfo = (siginfo_t*) info;
8418         /* Sometimes the address is off by 4 */
8419         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8420                 return TRUE;
8421         else
8422                 return FALSE;
8423 #endif
8424 }
8425
8426 /*
8427  * mono_arch_skip_single_step:
8428  *
8429  *   Modify CTX so the ip is placed after the single step trigger instruction,
8430  * we resume, the instruction is not executed again.
8431  */
8432 void
8433 mono_arch_skip_single_step (MonoContext *ctx)
8434 {
8435         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8436 }
8437
8438 /*
8439  * mono_arch_create_seq_point_info:
8440  *
8441  *   Return a pointer to a data structure which is used by the sequence
8442  * point implementation in AOTed code.
8443  */
8444 gpointer
8445 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8446 {
8447         SeqPointInfo *info;
8448         MonoJitInfo *ji;
8449         int i;
8450
8451         // FIXME: Add a free function
8452
8453         mono_domain_lock (domain);
8454         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8455                                                                 code);
8456         mono_domain_unlock (domain);
8457
8458         if (!info) {
8459                 ji = mono_jit_info_table_find (domain, (char*)code);
8460                 g_assert (ji);
8461
8462                 // FIXME: Optimize the size
8463                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8464
8465                 info->ss_trigger_page = ss_trigger_page;
8466                 info->bp_trigger_page = bp_trigger_page;
8467                 /* Initialize to a valid address */
8468                 for (i = 0; i < ji->code_size; ++i)
8469                         info->bp_addrs [i] = info;
8470
8471                 mono_domain_lock (domain);
8472                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8473                                                          code, info);
8474                 mono_domain_unlock (domain);
8475         }
8476
8477         return info;
8478 }
8479
8480 void
8481 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8482 {
8483         ext->lmf.previous_lmf = prev_lmf;
8484         /* Mark that this is a MonoLMFExt */
8485         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8486         ext->lmf.rsp = (gssize)ext;
8487 }
8488
8489 #endif
8490
8491 gboolean
8492 mono_arch_opcode_supported (int opcode)
8493 {
8494         switch (opcode) {
8495         case OP_ATOMIC_ADD_I4:
8496         case OP_ATOMIC_ADD_I8:
8497         case OP_ATOMIC_EXCHANGE_I4:
8498         case OP_ATOMIC_EXCHANGE_I8:
8499         case OP_ATOMIC_CAS_I4:
8500         case OP_ATOMIC_CAS_I8:
8501                 return TRUE;
8502         default:
8503                 return FALSE;
8504         }
8505 }