mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 /*
  69  * The code generated for sequence points reads from this location, which is
  70  * made read-only when single stepping is enabled.
  71  */
  72 static gpointer ss_trigger_page;
  73
  74 /* Enabled breakpoints read from this trigger page */
  75 static gpointer bp_trigger_page;
  76
  77 /* The size of the breakpoint sequence */
  78 static int breakpoint_size;
  79
  80 /* The size of the breakpoint instruction causing the actual fault */
  81 static int breakpoint_fault_size;
  82
  83 /* The size of the single step instruction causing the actual fault */
  84 static int single_step_fault_size;
  85
  86 /* The single step trampoline */
  87 static gpointer ss_trampoline;
  88
  89 /* Offset between fp and the first argument in the callee */
  90 #define ARGS_OFFSET 16
  91 #define GP_SCRATCH_REG AMD64_R11
  92
  93 /*
  94  * AMD64 register usage:
  95  * - callee saved registers are used for global register allocation
  96  * - %r11 is used for materializing 64 bit constants in opcodes
  97  * - the rest is used for local allocation
  98  */
  99
 100 /*
 101  * Floating point comparison results:
 102  *                  ZF PF CF
 103  * A > B            0  0  0
 104  * A < B            0  0  1
 105  * A = B            1  0  0
 106  * A > B            0  0  0
 107  * UNORDERED        1  1  1
 108  */
 109
 110 const char*
 111 mono_arch_regname (int reg)
 112 {
 113         switch (reg) {
 114         case AMD64_RAX: return "%rax";
 115         case AMD64_RBX: return "%rbx";
 116         case AMD64_RCX: return "%rcx";
 117         case AMD64_RDX: return "%rdx";
 118         case AMD64_RSP: return "%rsp";
 119         case AMD64_RBP: return "%rbp";
 120         case AMD64_RDI: return "%rdi";
 121         case AMD64_RSI: return "%rsi";
 122         case AMD64_R8: return "%r8";
 123         case AMD64_R9: return "%r9";
 124         case AMD64_R10: return "%r10";
 125         case AMD64_R11: return "%r11";
 126         case AMD64_R12: return "%r12";
 127         case AMD64_R13: return "%r13";
 128         case AMD64_R14: return "%r14";
 129         case AMD64_R15: return "%r15";
 130         }
 131         return "unknown";
 132 }
 133
 134 static const char * packed_xmmregs [] = {
 135         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 136         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 137 };
 138
 139 static const char * single_xmmregs [] = {
 140         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 141         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 142 };
 143
 144 const char*
 145 mono_arch_fregname (int reg)
 146 {
 147         if (reg < AMD64_XMM_NREG)
 148                 return single_xmmregs [reg];
 149         else
 150                 return "unknown";
 151 }
 152
 153 const char *
 154 mono_arch_xregname (int reg)
 155 {
 156         if (reg < AMD64_XMM_NREG)
 157                 return packed_xmmregs [reg];
 158         else
 159                 return "unknown";
 160 }
 161
 162 static gboolean
 163 debug_omit_fp (void)
 164 {
 165 #if 0
 166         return mono_debug_count ();
 167 #else
 168         return TRUE;
 169 #endif
 170 }
 171
 172 static inline gboolean
 173 amd64_is_near_call (guint8 *code)
 174 {
 175         /* Skip REX */
 176         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 177                 code += 1;
 178
 179         return code [0] == 0xe8;
 180 }
 181
 182 static inline gboolean
 183 amd64_use_imm32 (gint64 val)
 184 {
 185         if (mini_get_debug_options()->single_imm_size)
 186                 return FALSE;
 187
 188         return amd64_is_imm32 (val);
 189 }
 190
 191 #ifdef __native_client_codegen__
 192
 193 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 194 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 195 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 196 /* We only want to force bundle alignment for the top level instruction,    */
 197 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 198 static MonoNativeTlsKey nacl_instruction_depth;
 199
 200 static MonoNativeTlsKey nacl_rex_tag;
 201 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 202
 203 void
 204 amd64_nacl_clear_legacy_prefix_tag ()
 205 {
 206         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 207 }
 208
 209 void
 210 amd64_nacl_tag_legacy_prefix (guint8* code)
 211 {
 212         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 213                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 214 }
 215
 216 void
 217 amd64_nacl_tag_rex (guint8* code)
 218 {
 219         mono_native_tls_set_value (nacl_rex_tag, code);
 220 }
 221
 222 guint8*
 223 amd64_nacl_get_legacy_prefix_tag ()
 224 {
 225         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 226 }
 227
 228 guint8*
 229 amd64_nacl_get_rex_tag ()
 230 {
 231         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 232 }
 233
 234 /* Increment the instruction "depth" described above */
 235 void
 236 amd64_nacl_instruction_pre ()
 237 {
 238         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 239         depth++;
 240         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 241 }
 242
 243 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 244 /* alignment if depth == 0 (top level instruction)                          */
 245 /* IN: start, end    pointers to instruction beginning and end              */
 246 /* OUT: start, end   pointers to beginning and end after possible alignment */
 247 /* GLOBALS: nacl_instruction_depth     defined above                        */
 248 void
 249 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 250 {
 251         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 252         depth--;
 253         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 254
 255         g_assert ( depth >= 0 );
 256         if (depth == 0) {
 257                 uintptr_t space_in_block;
 258                 uintptr_t instlen;
 259                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 260                 /* if legacy prefix is present, and if it was emitted before */
 261                 /* the start of the instruction sequence, adjust the start   */
 262                 if (prefix != NULL && prefix < *start) {
 263                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 264                         *start = prefix;
 265                 }
 266                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 267                 instlen = (uintptr_t)(*end - *start);
 268                 /* Only check for instructions which are less than        */
 269                 /* kNaClAlignment. The only instructions that should ever */
 270                 /* be that long are call sequences, which are already     */
 271                 /* padded out to align the return to the next bundle.     */
 272                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 273                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 274                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 275                         const size_t length = (size_t)((*end)-(*start));
 276                         g_assert (length < MAX_NACL_INST_LENGTH);
 277
 278                         memcpy (copy_of_instruction, *start, length);
 279                         *start = mono_arch_nacl_pad (*start, space_in_block);
 280                         memcpy (*start, copy_of_instruction, length);
 281                         *end = *start + length;
 282                 }
 283                 amd64_nacl_clear_legacy_prefix_tag ();
 284                 amd64_nacl_tag_rex (NULL);
 285         }
 286 }
 287
 288 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 289 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 290 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 291 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 292 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 293 /* IN:      code                                                            */
 294 /*             pointer to current instruction stream (in the                */
 295 /*             middle of an instruction, after opcode is emitted)           */
 296 /*          basereg/offset/dreg                                             */
 297 /*             operands of normal membase address                           */
 298 /* OUT:     code                                                            */
 299 /*             pointer to the end of the membase/memindex emit              */
 300 /* GLOBALS: nacl_rex_tag                                                    */
 301 /*             position in instruction stream that rex prefix was emitted   */
 302 /*          nacl_legacy_prefix_tag                                          */
 303 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 304 void
 305 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 306 {
 307         gint8 true_basereg = basereg;
 308
 309         /* Cache these values, they might change  */
 310         /* as new instructions are emitted below. */
 311         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 312         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 313
 314         /* 'basereg' is given masked to 0x7 at this point, so check */
 315         /* the rex prefix to see if this is an extended register.   */
 316         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 317                 true_basereg |= 0x8;
 318         }
 319
 320 #define X86_LEA_OPCODE (0x8D)
 321
 322         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 323                 guint8* old_instruction_start;
 324
 325                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 326                 /* 32-bits of the old base register (new index register)     */
 327                 guint8 buf[32];
 328                 guint8* buf_ptr = buf;
 329                 size_t insert_len;
 330
 331                 g_assert (rex_tag != NULL);
 332
 333                 if (IS_REX(*rex_tag)) {
 334                         /* The old rex.B should be the new rex.X */
 335                         if (*rex_tag & AMD64_REX_B) {
 336                                 *rex_tag |= AMD64_REX_X;
 337                         }
 338                         /* Since our new base is %r15 set rex.B */
 339                         *rex_tag |= AMD64_REX_B;
 340                 } else {
 341                         /* Shift the instruction by one byte  */
 342                         /* so we can insert a rex prefix      */
 343                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 344                         *code += 1;
 345                         /* New rex prefix only needs rex.B for %r15 base */
 346                         *rex_tag = AMD64_REX(AMD64_REX_B);
 347                 }
 348
 349                 if (legacy_prefix_tag) {
 350                         old_instruction_start = legacy_prefix_tag;
 351                 } else {
 352                         old_instruction_start = rex_tag;
 353                 }
 354
 355                 /* Clears the upper 32-bits of the previous base register */
 356                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 357                 insert_len = buf_ptr - buf;
 358
 359                 /* Move the old instruction forward to make */
 360                 /* room for 'mov' stored in 'buf_ptr'       */
 361                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 362                 *code += insert_len;
 363                 memcpy (old_instruction_start, buf, insert_len);
 364
 365                 /* Sandboxed replacement for the normal membase_emit */
 366                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 367
 368         } else {
 369                 /* Normal default behavior, emit membase memory location */
 370                 x86_membase_emit_body (*code, dreg, basereg, offset);
 371         }
 372 }
 373
 374
 375 static inline unsigned char*
 376 amd64_skip_nops (unsigned char* code)
 377 {
 378         guint8 in_nop;
 379         do {
 380                 in_nop = 0;
 381                 if (   code[0] == 0x90) {
 382                         in_nop = 1;
 383                         code += 1;
 384                 }
 385                 if (   code[0] == 0x66 && code[1] == 0x90) {
 386                         in_nop = 1;
 387                         code += 2;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x00) {
 391                         in_nop = 1;
 392                         code += 3;
 393                 }
 394                 if (code[0] == 0x0f && code[1] == 0x1f
 395                  && code[2] == 0x40 && code[3] == 0x00) {
 396                         in_nop = 1;
 397                         code += 4;
 398                 }
 399                 if (code[0] == 0x0f && code[1] == 0x1f
 400                  && code[2] == 0x44 && code[3] == 0x00
 401                  && code[4] == 0x00) {
 402                         in_nop = 1;
 403                         code += 5;
 404                 }
 405                 if (code[0] == 0x66 && code[1] == 0x0f
 406                  && code[2] == 0x1f && code[3] == 0x44
 407                  && code[4] == 0x00 && code[5] == 0x00) {
 408                         in_nop = 1;
 409                         code += 6;
 410                 }
 411                 if (code[0] == 0x0f && code[1] == 0x1f
 412                  && code[2] == 0x80 && code[3] == 0x00
 413                  && code[4] == 0x00 && code[5] == 0x00
 414                  && code[6] == 0x00) {
 415                         in_nop = 1;
 416                         code += 7;
 417                 }
 418                 if (code[0] == 0x0f && code[1] == 0x1f
 419                  && code[2] == 0x84 && code[3] == 0x00
 420                  && code[4] == 0x00 && code[5] == 0x00
 421                  && code[6] == 0x00 && code[7] == 0x00) {
 422                         in_nop = 1;
 423                         code += 8;
 424                 }
 425         } while ( in_nop );
 426         return code;
 427 }
 428
 429 guint8*
 430 mono_arch_nacl_skip_nops (guint8* code)
 431 {
 432   return amd64_skip_nops(code);
 433 }
 434
 435 #endif /*__native_client_codegen__*/
 436
 437 static inline void
 438 amd64_patch (unsigned char* code, gpointer target)
 439 {
 440         guint8 rex = 0;
 441
 442 #ifdef __native_client_codegen__
 443         code = amd64_skip_nops (code);
 444 #endif
 445 #if defined(__native_client_codegen__) && defined(__native_client__)
 446         if (nacl_is_code_address (code)) {
 447                 /* For tail calls, code is patched after being installed */
 448                 /* but not through the normal "patch callsite" method.   */
 449                 unsigned char buf[kNaClAlignment];
 450                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 451                 int ret;
 452                 memcpy (buf, aligned_code, kNaClAlignment);
 453                 /* Patch a temp buffer of bundle size, */
 454                 /* then install to actual location.    */
 455                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 456                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 457                 g_assert (ret == 0);
 458                 return;
 459         }
 460         target = nacl_modify_patch_target (target);
 461 #endif
 462
 463         /* Skip REX */
 464         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 465                 rex = code [0];
 466                 code += 1;
 467         }
 468
 469         if ((code [0] & 0xf8) == 0xb8) {
 470                 /* amd64_set_reg_template */
 471                 *(guint64*)(code + 1) = (guint64)target;
 472         }
 473         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 474                 /* mov 0(%rip), %dreg */
 475                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 476         }
 477         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 478                 /* call *<OFFSET>(%rip) */
 479                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 480         }
 481         else if (code [0] == 0xe8) {
 482                 /* call <DISP> */
 483                 gint64 disp = (guint8*)target - (guint8*)code;
 484                 g_assert (amd64_is_imm32 (disp));
 485                 x86_patch (code, (unsigned char*)target);
 486         }
 487         else
 488                 x86_patch (code, (unsigned char*)target);
 489 }
 490
 491 void
 492 mono_amd64_patch (unsigned char* code, gpointer target)
 493 {
 494         amd64_patch (code, target);
 495 }
 496
 497 typedef enum {
 498         ArgInIReg,
 499         ArgInFloatSSEReg,
 500         ArgInDoubleSSEReg,
 501         ArgOnStack,
 502         ArgValuetypeInReg,
 503         ArgValuetypeAddrInIReg,
 504         /* gsharedvt argument passed by addr */
 505         ArgGSharedVtInReg,
 506         ArgGSharedVtOnStack,
 507         ArgNone /* only in pair_storage */
 508 } ArgStorage;
 509
 510 typedef struct {
 511         gint16 offset;
 512         gint8  reg;
 513         ArgStorage storage;
 514
 515         /* Only if storage == ArgValuetypeInReg */
 516         ArgStorage pair_storage [2];
 517         gint8 pair_regs [2];
 518         /* The size of each pair */
 519         int pair_size [2];
 520         int nregs;
 521 } ArgInfo;
 522
 523 typedef struct {
 524         int nargs;
 525         guint32 stack_usage;
 526         guint32 reg_usage;
 527         guint32 freg_usage;
 528         gboolean need_stack_align;
 529         /* The index of the vret arg in the argument list */
 530         int vret_arg_index;
 531         ArgInfo ret;
 532         ArgInfo sig_cookie;
 533         ArgInfo args [1];
 534 } CallInfo;
 535
 536 #define DEBUG(a) if (cfg->verbose_level > 1) a
 537
 538 #ifdef TARGET_WIN32
 539 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 540
 541 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 542 #else
 543 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 544
 545  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 546 #endif
 547
 548 static void inline
 549 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 550 {
 551     ainfo->offset = *stack_size;
 552
 553     if (*gr >= PARAM_REGS) {
 554                 ainfo->storage = ArgOnStack;
 555                 /* Since the same stack slot size is used for all arg */
 556                 /*  types, it needs to be big enough to hold them all */
 557                 (*stack_size) += sizeof(mgreg_t);
 558     }
 559     else {
 560                 ainfo->storage = ArgInIReg;
 561                 ainfo->reg = param_regs [*gr];
 562                 (*gr) ++;
 563     }
 564 }
 565
 566 #ifdef TARGET_WIN32
 567 #define FLOAT_PARAM_REGS 4
 568 #else
 569 #define FLOAT_PARAM_REGS 8
 570 #endif
 571
 572 static void inline
 573 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 574 {
 575     ainfo->offset = *stack_size;
 576
 577     if (*gr >= FLOAT_PARAM_REGS) {
 578                 ainfo->storage = ArgOnStack;
 579                 /* Since the same stack slot size is used for both float */
 580                 /*  types, it needs to be big enough to hold them both */
 581                 (*stack_size) += sizeof(mgreg_t);
 582     }
 583     else {
 584                 /* A double register */
 585                 if (is_double)
 586                         ainfo->storage = ArgInDoubleSSEReg;
 587                 else
 588                         ainfo->storage = ArgInFloatSSEReg;
 589                 ainfo->reg = *gr;
 590                 (*gr) += 1;
 591     }
 592 }
 593
 594 typedef enum ArgumentClass {
 595         ARG_CLASS_NO_CLASS,
 596         ARG_CLASS_MEMORY,
 597         ARG_CLASS_INTEGER,
 598         ARG_CLASS_SSE
 599 } ArgumentClass;
 600
 601 static ArgumentClass
 602 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 603 {
 604         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 605         MonoType *ptype;
 606
 607         ptype = mini_get_underlying_type (type);
 608         switch (ptype->type) {
 609         case MONO_TYPE_I1:
 610         case MONO_TYPE_U1:
 611         case MONO_TYPE_I2:
 612         case MONO_TYPE_U2:
 613         case MONO_TYPE_I4:
 614         case MONO_TYPE_U4:
 615         case MONO_TYPE_I:
 616         case MONO_TYPE_U:
 617         case MONO_TYPE_STRING:
 618         case MONO_TYPE_OBJECT:
 619         case MONO_TYPE_CLASS:
 620         case MONO_TYPE_SZARRAY:
 621         case MONO_TYPE_PTR:
 622         case MONO_TYPE_FNPTR:
 623         case MONO_TYPE_ARRAY:
 624         case MONO_TYPE_I8:
 625         case MONO_TYPE_U8:
 626                 class2 = ARG_CLASS_INTEGER;
 627                 break;
 628         case MONO_TYPE_R4:
 629         case MONO_TYPE_R8:
 630 #ifdef TARGET_WIN32
 631                 class2 = ARG_CLASS_INTEGER;
 632 #else
 633                 class2 = ARG_CLASS_SSE;
 634 #endif
 635                 break;
 636
 637         case MONO_TYPE_TYPEDBYREF:
 638                 g_assert_not_reached ();
 639
 640         case MONO_TYPE_GENERICINST:
 641                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 642                         class2 = ARG_CLASS_INTEGER;
 643                         break;
 644                 }
 645                 /* fall through */
 646         case MONO_TYPE_VALUETYPE: {
 647                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 648                 int i;
 649
 650                 for (i = 0; i < info->num_fields; ++i) {
 651                         class2 = class1;
 652                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 653                 }
 654                 break;
 655         }
 656         default:
 657                 g_assert_not_reached ();
 658         }
 659
 660         /* Merge */
 661         if (class1 == class2)
 662                 ;
 663         else if (class1 == ARG_CLASS_NO_CLASS)
 664                 class1 = class2;
 665         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 666                 class1 = ARG_CLASS_MEMORY;
 667         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 668                 class1 = ARG_CLASS_INTEGER;
 669         else
 670                 class1 = ARG_CLASS_SSE;
 671
 672         return class1;
 673 }
 674 #ifdef __native_client_codegen__
 675
 676 /* Default alignment for Native Client is 32-byte. */
 677 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 678
 679 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 680 /* Check that alignment doesn't cross an alignment boundary.             */
 681 guint8*
 682 mono_arch_nacl_pad(guint8 *code, int pad)
 683 {
 684         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 685
 686         if (pad == 0) return code;
 687         /* assertion: alignment cannot cross a block boundary */
 688         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 689                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 690         while (pad >= kMaxPadding) {
 691                 amd64_padding (code, kMaxPadding);
 692                 pad -= kMaxPadding;
 693         }
 694         if (pad != 0) amd64_padding (code, pad);
 695         return code;
 696 }
 697 #endif
 698
 699 static int
 700 count_fields_nested (MonoClass *klass)
 701 {
 702         MonoMarshalType *info;
 703         int i, count;
 704
 705         info = mono_marshal_load_type_info (klass);
 706         g_assert(info);
 707         count = 0;
 708         for (i = 0; i < info->num_fields; ++i) {
 709                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 710                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 711                 else
 712                         count ++;
 713         }
 714         return count;
 715 }
 716
 717 static int
 718 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 719 {
 720         MonoMarshalType *info;
 721         int i;
 722
 723         info = mono_marshal_load_type_info (klass);
 724         g_assert(info);
 725         for (i = 0; i < info->num_fields; ++i) {
 726                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 727                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 728                 } else {
 729                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 730                         fields [index].offset += offset;
 731                         index ++;
 732                 }
 733         }
 734         return index;
 735 }
 736
 737 static void
 738 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 739                            gboolean is_return,
 740                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 741 {
 742         guint32 size, quad, nquads, i, nfields;
 743         /* Keep track of the size used in each quad so we can */
 744         /* use the right size when copying args/return vars.  */
 745         guint32 quadsize [2] = {8, 8};
 746         ArgumentClass args [2];
 747         MonoMarshalType *info = NULL;
 748         MonoMarshalField *fields = NULL;
 749         MonoClass *klass;
 750         gboolean pass_on_stack = FALSE;
 751
 752         klass = mono_class_from_mono_type (type);
 753         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 754 #ifndef TARGET_WIN32
 755         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 756                 /* We pass and return vtypes of size 8 in a register */
 757         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 758                 pass_on_stack = TRUE;
 759         }
 760 #else
 761         if (!sig->pinvoke) {
 762                 pass_on_stack = TRUE;
 763         }
 764 #endif
 765
 766         /* If this struct can't be split up naturally into 8-byte */
 767         /* chunks (registers), pass it on the stack.              */
 768         if (sig->pinvoke && !pass_on_stack) {
 769                 guint32 align;
 770                 guint32 field_size;
 771
 772                 info = mono_marshal_load_type_info (klass);
 773                 g_assert (info);
 774
 775                 /*
 776                  * Collect field information recursively to be able to
 777                  * handle nested structures.
 778                  */
 779                 nfields = count_fields_nested (klass);
 780                 fields = g_new0 (MonoMarshalField, nfields);
 781                 collect_field_info_nested (klass, fields, 0, 0);
 782
 783                 for (i = 0; i < nfields; ++i) {
 784                         field_size = mono_marshal_type_size (fields [i].field->type,
 785                                                            fields [i].mspec,
 786                                                            &align, TRUE, klass->unicode);
 787                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 788                                 pass_on_stack = TRUE;
 789                                 break;
 790                         }
 791                 }
 792         }
 793
 794 #ifndef TARGET_WIN32
 795         if (size == 0) {
 796                 ainfo->storage = ArgValuetypeInReg;
 797                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 798                 return;
 799         }
 800 #endif
 801
 802         if (pass_on_stack) {
 803                 /* Allways pass in memory */
 804                 ainfo->offset = *stack_size;
 805                 *stack_size += ALIGN_TO (size, 8);
 806                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 807
 808                 g_free (fields);
 809                 return;
 810         }
 811
 812         /* FIXME: Handle structs smaller than 8 bytes */
 813         //if ((size % 8) != 0)
 814         //      NOT_IMPLEMENTED;
 815
 816         if (size > 8)
 817                 nquads = 2;
 818         else
 819                 nquads = 1;
 820
 821         if (!sig->pinvoke) {
 822                 int n = mono_class_value_size (klass, NULL);
 823
 824                 quadsize [0] = n >= 8 ? 8 : n;
 825                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 826
 827                 /* Always pass in 1 or 2 integer registers */
 828                 args [0] = ARG_CLASS_INTEGER;
 829                 args [1] = ARG_CLASS_INTEGER;
 830                 /* Only the simplest cases are supported */
 831                 if (is_return && nquads != 1) {
 832                         args [0] = ARG_CLASS_MEMORY;
 833                         args [1] = ARG_CLASS_MEMORY;
 834                 }
 835         } else {
 836                 /*
 837                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 838                  * The X87 and SSEUP stuff is left out since there are no such types in
 839                  * the CLR.
 840                  */
 841                 g_assert (info);
 842
 843                 if (!fields) {
 844                         ainfo->storage = ArgValuetypeInReg;
 845                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 846                         return;
 847                 }
 848
 849 #ifndef TARGET_WIN32
 850                 if (info->native_size > 16) {
 851                         ainfo->offset = *stack_size;
 852                         *stack_size += ALIGN_TO (info->native_size, 8);
 853                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 854
 855                         g_free (fields);
 856                         return;
 857                 }
 858 #else
 859                 switch (info->native_size) {
 860                 case 1: case 2: case 4: case 8:
 861                         break;
 862                 default:
 863                         if (is_return) {
 864                                 ainfo->storage = ArgValuetypeAddrInIReg;
 865                                 ainfo->offset = *stack_size;
 866                                 *stack_size += ALIGN_TO (info->native_size, 8);
 867                         }
 868                         else {
 869                                 ainfo->storage = ArgValuetypeAddrInIReg;
 870
 871                                 if (*gr < PARAM_REGS) {
 872                                         ainfo->pair_storage [0] = ArgInIReg;
 873                                         ainfo->pair_regs [0] = param_regs [*gr];
 874                                         (*gr) ++;
 875                                 }
 876                                 else {
 877                                         ainfo->pair_storage [0] = ArgOnStack;
 878                                         ainfo->offset = *stack_size;
 879                                         *stack_size += 8;
 880                                 }
 881                         }
 882
 883                         g_free (fields);
 884                         return;
 885                 }
 886 #endif
 887
 888                 args [0] = ARG_CLASS_NO_CLASS;
 889                 args [1] = ARG_CLASS_NO_CLASS;
 890                 for (quad = 0; quad < nquads; ++quad) {
 891                         int size;
 892                         guint32 align;
 893                         ArgumentClass class1;
 894
 895                         if (nfields == 0)
 896                                 class1 = ARG_CLASS_MEMORY;
 897                         else
 898                                 class1 = ARG_CLASS_NO_CLASS;
 899                         for (i = 0; i < nfields; ++i) {
 900                                 size = mono_marshal_type_size (fields [i].field->type,
 901                                                                                            fields [i].mspec,
 902                                                                                            &align, TRUE, klass->unicode);
 903                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 904                                         /* Unaligned field */
 905                                         NOT_IMPLEMENTED;
 906                                 }
 907
 908                                 /* Skip fields in other quad */
 909                                 if ((quad == 0) && (fields [i].offset >= 8))
 910                                         continue;
 911                                 if ((quad == 1) && (fields [i].offset < 8))
 912                                         continue;
 913
 914                                 /* How far into this quad this data extends.*/
 915                                 /* (8 is size of quad) */
 916                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 917
 918                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 919                         }
 920                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 921                         args [quad] = class1;
 922                 }
 923         }
 924
 925         g_free (fields);
 926
 927         /* Post merger cleanup */
 928         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 929                 args [0] = args [1] = ARG_CLASS_MEMORY;
 930
 931         /* Allocate registers */
 932         {
 933                 int orig_gr = *gr;
 934                 int orig_fr = *fr;
 935
 936                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 937                         quadsize [0] ++;
 938                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 939                         quadsize [1] ++;
 940
 941                 ainfo->storage = ArgValuetypeInReg;
 942                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 943                 g_assert (quadsize [0] <= 8);
 944                 g_assert (quadsize [1] <= 8);
 945                 ainfo->pair_size [0] = quadsize [0];
 946                 ainfo->pair_size [1] = quadsize [1];
 947                 ainfo->nregs = nquads;
 948                 for (quad = 0; quad < nquads; ++quad) {
 949                         switch (args [quad]) {
 950                         case ARG_CLASS_INTEGER:
 951                                 if (*gr >= PARAM_REGS)
 952                                         args [quad] = ARG_CLASS_MEMORY;
 953                                 else {
 954                                         ainfo->pair_storage [quad] = ArgInIReg;
 955                                         if (is_return)
 956                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 957                                         else
 958                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 959                                         (*gr) ++;
 960                                 }
 961                                 break;
 962                         case ARG_CLASS_SSE:
 963                                 if (*fr >= FLOAT_PARAM_REGS)
 964                                         args [quad] = ARG_CLASS_MEMORY;
 965                                 else {
 966                                         if (quadsize[quad] <= 4)
 967                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 968                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 969                                         ainfo->pair_regs [quad] = *fr;
 970                                         (*fr) ++;
 971                                 }
 972                                 break;
 973                         case ARG_CLASS_MEMORY:
 974                                 break;
 975                         default:
 976                                 g_assert_not_reached ();
 977                         }
 978                 }
 979
 980                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 981                         /* Revert possible register assignments */
 982                         *gr = orig_gr;
 983                         *fr = orig_fr;
 984
 985                         ainfo->offset = *stack_size;
 986                         if (sig->pinvoke)
 987                                 *stack_size += ALIGN_TO (info->native_size, 8);
 988                         else
 989                                 *stack_size += nquads * sizeof(mgreg_t);
 990                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 991                 }
 992         }
 993 }
 994
 995 /*
 996  * get_call_info:
 997  *
 998  *  Obtain information about a call according to the calling convention.
 999  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1000  * Draft Version 0.23" document for more information.
1001  */
1002 static CallInfo*
1003 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1004 {
1005         guint32 i, gr, fr, pstart;
1006         MonoType *ret_type;
1007         int n = sig->hasthis + sig->param_count;
1008         guint32 stack_size = 0;
1009         CallInfo *cinfo;
1010         gboolean is_pinvoke = sig->pinvoke;
1011
1012         if (mp)
1013                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1014         else
1015                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1016
1017         cinfo->nargs = n;
1018
1019         gr = 0;
1020         fr = 0;
1021
1022 #ifdef TARGET_WIN32
1023         /* Reserve space where the callee can save the argument registers */
1024         stack_size = 4 * sizeof (mgreg_t);
1025 #endif
1026
1027         /* return value */
1028         ret_type = mini_get_underlying_type (sig->ret);
1029         switch (ret_type->type) {
1030         case MONO_TYPE_I1:
1031         case MONO_TYPE_U1:
1032         case MONO_TYPE_I2:
1033         case MONO_TYPE_U2:
1034         case MONO_TYPE_I4:
1035         case MONO_TYPE_U4:
1036         case MONO_TYPE_I:
1037         case MONO_TYPE_U:
1038         case MONO_TYPE_PTR:
1039         case MONO_TYPE_FNPTR:
1040         case MONO_TYPE_CLASS:
1041         case MONO_TYPE_OBJECT:
1042         case MONO_TYPE_SZARRAY:
1043         case MONO_TYPE_ARRAY:
1044         case MONO_TYPE_STRING:
1045                 cinfo->ret.storage = ArgInIReg;
1046                 cinfo->ret.reg = AMD64_RAX;
1047                 break;
1048         case MONO_TYPE_U8:
1049         case MONO_TYPE_I8:
1050                 cinfo->ret.storage = ArgInIReg;
1051                 cinfo->ret.reg = AMD64_RAX;
1052                 break;
1053         case MONO_TYPE_R4:
1054                 cinfo->ret.storage = ArgInFloatSSEReg;
1055                 cinfo->ret.reg = AMD64_XMM0;
1056                 break;
1057         case MONO_TYPE_R8:
1058                 cinfo->ret.storage = ArgInDoubleSSEReg;
1059                 cinfo->ret.reg = AMD64_XMM0;
1060                 break;
1061         case MONO_TYPE_GENERICINST:
1062                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1063                         cinfo->ret.storage = ArgInIReg;
1064                         cinfo->ret.reg = AMD64_RAX;
1065                         break;
1066                 }
1067                 if (mini_is_gsharedvt_type (ret_type)) {
1068                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1069                         break;
1070                 }
1071                 /* fall through */
1072 #if defined( __native_client_codegen__ )
1073         case MONO_TYPE_TYPEDBYREF:
1074 #endif
1075         case MONO_TYPE_VALUETYPE: {
1076                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1077
1078                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1079                 g_assert (cinfo->ret.storage != ArgInIReg);
1080                 break;
1081         }
1082 #if !defined( __native_client_codegen__ )
1083         case MONO_TYPE_TYPEDBYREF:
1084                 /* Same as a valuetype with size 24 */
1085                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1086                 break;
1087 #endif
1088         case MONO_TYPE_VAR:
1089         case MONO_TYPE_MVAR:
1090                 g_assert (mini_is_gsharedvt_type (ret_type));
1091                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1092                 break;
1093         case MONO_TYPE_VOID:
1094                 break;
1095         default:
1096                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1097         }
1098
1099         pstart = 0;
1100         /*
1101          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1102          * the first argument, allowing 'this' to be always passed in the first arg reg.
1103          * Also do this if the first argument is a reference type, since virtual calls
1104          * are sometimes made using calli without sig->hasthis set, like in the delegate
1105          * invoke wrappers.
1106          */
1107         if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1108                 if (sig->hasthis) {
1109                         add_general (&gr, &stack_size, cinfo->args + 0);
1110                 } else {
1111                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1112                         pstart = 1;
1113                 }
1114                 add_general (&gr, &stack_size, &cinfo->ret);
1115                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1116                 cinfo->vret_arg_index = 1;
1117         } else {
1118                 /* this */
1119                 if (sig->hasthis)
1120                         add_general (&gr, &stack_size, cinfo->args + 0);
1121
1122                 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1123                         add_general (&gr, &stack_size, &cinfo->ret);
1124                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1125                 }
1126         }
1127
1128         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1129                 gr = PARAM_REGS;
1130                 fr = FLOAT_PARAM_REGS;
1131
1132                 /* Emit the signature cookie just before the implicit arguments */
1133                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1134         }
1135
1136         for (i = pstart; i < sig->param_count; ++i) {
1137                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1138                 MonoType *ptype;
1139
1140 #ifdef TARGET_WIN32
1141                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1142                 if (gr > fr)
1143                         fr = gr;
1144                 else if (fr > gr)
1145                         gr = fr;
1146 #endif
1147
1148                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1149                         /* We allways pass the sig cookie on the stack for simplicity */
1150                         /*
1151                          * Prevent implicit arguments + the sig cookie from being passed
1152                          * in registers.
1153                          */
1154                         gr = PARAM_REGS;
1155                         fr = FLOAT_PARAM_REGS;
1156
1157                         /* Emit the signature cookie just before the implicit arguments */
1158                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1159                 }
1160
1161                 ptype = mini_get_underlying_type (sig->params [i]);
1162                 switch (ptype->type) {
1163                 case MONO_TYPE_I1:
1164                 case MONO_TYPE_U1:
1165                         add_general (&gr, &stack_size, ainfo);
1166                         break;
1167                 case MONO_TYPE_I2:
1168                 case MONO_TYPE_U2:
1169                         add_general (&gr, &stack_size, ainfo);
1170                         break;
1171                 case MONO_TYPE_I4:
1172                 case MONO_TYPE_U4:
1173                         add_general (&gr, &stack_size, ainfo);
1174                         break;
1175                 case MONO_TYPE_I:
1176                 case MONO_TYPE_U:
1177                 case MONO_TYPE_PTR:
1178                 case MONO_TYPE_FNPTR:
1179                 case MONO_TYPE_CLASS:
1180                 case MONO_TYPE_OBJECT:
1181                 case MONO_TYPE_STRING:
1182                 case MONO_TYPE_SZARRAY:
1183                 case MONO_TYPE_ARRAY:
1184                         add_general (&gr, &stack_size, ainfo);
1185                         break;
1186                 case MONO_TYPE_GENERICINST:
1187                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1188                                 add_general (&gr, &stack_size, ainfo);
1189                                 break;
1190                         }
1191                         if (mini_is_gsharedvt_type (ptype)) {
1192                                 /* gsharedvt arguments are passed by ref */
1193                                 add_general (&gr, &stack_size, ainfo);
1194                                 if (ainfo->storage == ArgInIReg)
1195                                         ainfo->storage = ArgGSharedVtInReg;
1196                                 else
1197                                         ainfo->storage = ArgGSharedVtOnStack;
1198                                 break;
1199                         }
1200                         /* fall through */
1201                 case MONO_TYPE_VALUETYPE:
1202                 case MONO_TYPE_TYPEDBYREF:
1203                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1204                         break;
1205                 case MONO_TYPE_U8:
1206
1207                 case MONO_TYPE_I8:
1208                         add_general (&gr, &stack_size, ainfo);
1209                         break;
1210                 case MONO_TYPE_R4:
1211                         add_float (&fr, &stack_size, ainfo, FALSE);
1212                         break;
1213                 case MONO_TYPE_R8:
1214                         add_float (&fr, &stack_size, ainfo, TRUE);
1215                         break;
1216                 case MONO_TYPE_VAR:
1217                 case MONO_TYPE_MVAR:
1218                         /* gsharedvt arguments are passed by ref */
1219                         g_assert (mini_is_gsharedvt_type (ptype));
1220                         add_general (&gr, &stack_size, ainfo);
1221                         if (ainfo->storage == ArgInIReg)
1222                                 ainfo->storage = ArgGSharedVtInReg;
1223                         else
1224                                 ainfo->storage = ArgGSharedVtOnStack;
1225                         break;
1226                 default:
1227                         g_assert_not_reached ();
1228                 }
1229         }
1230
1231         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1232                 gr = PARAM_REGS;
1233                 fr = FLOAT_PARAM_REGS;
1234
1235                 /* Emit the signature cookie just before the implicit arguments */
1236                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1237         }
1238
1239         cinfo->stack_usage = stack_size;
1240         cinfo->reg_usage = gr;
1241         cinfo->freg_usage = fr;
1242         return cinfo;
1243 }
1244
1245 /*
1246  * mono_arch_get_argument_info:
1247  * @csig:  a method signature
1248  * @param_count: the number of parameters to consider
1249  * @arg_info: an array to store the result infos
1250  *
1251  * Gathers information on parameters such as size, alignment and
1252  * padding. arg_info should be large enought to hold param_count + 1 entries.
1253  *
1254  * Returns the size of the argument area on the stack.
1255  */
1256 int
1257 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1258 {
1259         int k;
1260         CallInfo *cinfo = get_call_info (NULL, csig);
1261         guint32 args_size = cinfo->stack_usage;
1262
1263         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1264         if (csig->hasthis) {
1265                 arg_info [0].offset = 0;
1266         }
1267
1268         for (k = 0; k < param_count; k++) {
1269                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1270                 /* FIXME: */
1271                 arg_info [k + 1].size = 0;
1272         }
1273
1274         g_free (cinfo);
1275
1276         return args_size;
1277 }
1278
1279 gboolean
1280 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1281 {
1282         CallInfo *c1, *c2;
1283         gboolean res;
1284         MonoType *callee_ret;
1285
1286         c1 = get_call_info (NULL, caller_sig);
1287         c2 = get_call_info (NULL, callee_sig);
1288         res = c1->stack_usage >= c2->stack_usage;
1289         callee_ret = mini_get_underlying_type (callee_sig->ret);
1290         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1291                 /* An address on the callee's stack is passed as the first argument */
1292                 res = FALSE;
1293
1294         g_free (c1);
1295         g_free (c2);
1296
1297         return res;
1298 }
1299
1300 /*
1301  * Initialize the cpu to execute managed code.
1302  */
1303 void
1304 mono_arch_cpu_init (void)
1305 {
1306 #ifndef _MSC_VER
1307         guint16 fpcw;
1308
1309         /* spec compliance requires running with double precision */
1310         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1311         fpcw &= ~X86_FPCW_PRECC_MASK;
1312         fpcw |= X86_FPCW_PREC_DOUBLE;
1313         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1314         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1315 #else
1316         /* TODO: This is crashing on Win64 right now.
1317         * _control87 (_PC_53, MCW_PC);
1318         */
1319 #endif
1320 }
1321
1322 /*
1323  * Initialize architecture specific code.
1324  */
1325 void
1326 mono_arch_init (void)
1327 {
1328         int flags;
1329
1330         mono_mutex_init_recursive (&mini_arch_mutex);
1331 #if defined(__native_client_codegen__)
1332         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1333         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1334         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1335         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1336 #endif
1337
1338 #ifdef MONO_ARCH_NOMAP32BIT
1339         flags = MONO_MMAP_READ;
1340         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1341         breakpoint_size = 13;
1342         breakpoint_fault_size = 3;
1343 #else
1344         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1345         /* amd64_mov_reg_mem () */
1346         breakpoint_size = 8;
1347         breakpoint_fault_size = 8;
1348 #endif
1349
1350         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1351         single_step_fault_size = 4;
1352
1353         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1354         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1355         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1356
1357         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1358         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1359         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1360         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1361 }
1362
1363 /*
1364  * Cleanup architecture specific code.
1365  */
1366 void
1367 mono_arch_cleanup (void)
1368 {
1369         mono_mutex_destroy (&mini_arch_mutex);
1370 #if defined(__native_client_codegen__)
1371         mono_native_tls_free (nacl_instruction_depth);
1372         mono_native_tls_free (nacl_rex_tag);
1373         mono_native_tls_free (nacl_legacy_prefix_tag);
1374 #endif
1375 }
1376
1377 /*
1378  * This function returns the optimizations supported on this cpu.
1379  */
1380 guint32
1381 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1382 {
1383         guint32 opts = 0;
1384
1385         *exclude_mask = 0;
1386
1387         if (mono_hwcap_x86_has_cmov) {
1388                 opts |= MONO_OPT_CMOV;
1389
1390                 if (mono_hwcap_x86_has_fcmov)
1391                         opts |= MONO_OPT_FCMOV;
1392                 else
1393                         *exclude_mask |= MONO_OPT_FCMOV;
1394         } else {
1395                 *exclude_mask |= MONO_OPT_CMOV;
1396         }
1397
1398         return opts;
1399 }
1400
1401 /*
1402  * This function test for all SSE functions supported.
1403  *
1404  * Returns a bitmask corresponding to all supported versions.
1405  *
1406  */
1407 guint32
1408 mono_arch_cpu_enumerate_simd_versions (void)
1409 {
1410         guint32 sse_opts = 0;
1411
1412         if (mono_hwcap_x86_has_sse1)
1413                 sse_opts |= SIMD_VERSION_SSE1;
1414
1415         if (mono_hwcap_x86_has_sse2)
1416                 sse_opts |= SIMD_VERSION_SSE2;
1417
1418         if (mono_hwcap_x86_has_sse3)
1419                 sse_opts |= SIMD_VERSION_SSE3;
1420
1421         if (mono_hwcap_x86_has_ssse3)
1422                 sse_opts |= SIMD_VERSION_SSSE3;
1423
1424         if (mono_hwcap_x86_has_sse41)
1425                 sse_opts |= SIMD_VERSION_SSE41;
1426
1427         if (mono_hwcap_x86_has_sse42)
1428                 sse_opts |= SIMD_VERSION_SSE42;
1429
1430         if (mono_hwcap_x86_has_sse4a)
1431                 sse_opts |= SIMD_VERSION_SSE4a;
1432
1433         return sse_opts;
1434 }
1435
1436 #ifndef DISABLE_JIT
1437
1438 GList *
1439 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1440 {
1441         GList *vars = NULL;
1442         int i;
1443
1444         for (i = 0; i < cfg->num_varinfo; i++) {
1445                 MonoInst *ins = cfg->varinfo [i];
1446                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1447
1448                 /* unused vars */
1449                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1450                         continue;
1451
1452                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1453                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1454                         continue;
1455
1456                 if (mono_is_regsize_var (ins->inst_vtype)) {
1457                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1458                         g_assert (i == vmv->idx);
1459                         vars = g_list_prepend (vars, vmv);
1460                 }
1461         }
1462
1463         vars = mono_varlist_sort (cfg, vars, 0);
1464
1465         return vars;
1466 }
1467
1468 /**
1469  * mono_arch_compute_omit_fp:
1470  *
1471  *   Determine whenever the frame pointer can be eliminated.
1472  */
1473 static void
1474 mono_arch_compute_omit_fp (MonoCompile *cfg)
1475 {
1476         MonoMethodSignature *sig;
1477         MonoMethodHeader *header;
1478         int i, locals_size;
1479         CallInfo *cinfo;
1480
1481         if (cfg->arch.omit_fp_computed)
1482                 return;
1483
1484         header = cfg->header;
1485
1486         sig = mono_method_signature (cfg->method);
1487
1488         if (!cfg->arch.cinfo)
1489                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1490         cinfo = cfg->arch.cinfo;
1491
1492         /*
1493          * FIXME: Remove some of the restrictions.
1494          */
1495         cfg->arch.omit_fp = TRUE;
1496         cfg->arch.omit_fp_computed = TRUE;
1497
1498 #ifdef __native_client_codegen__
1499         /* NaCl modules may not change the value of RBP, so it cannot be */
1500         /* used as a normal register, but it can be used as a frame pointer*/
1501         cfg->disable_omit_fp = TRUE;
1502         cfg->arch.omit_fp = FALSE;
1503 #endif
1504
1505         if (cfg->disable_omit_fp)
1506                 cfg->arch.omit_fp = FALSE;
1507
1508         if (!debug_omit_fp ())
1509                 cfg->arch.omit_fp = FALSE;
1510         /*
1511         if (cfg->method->save_lmf)
1512                 cfg->arch.omit_fp = FALSE;
1513         */
1514         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1515                 cfg->arch.omit_fp = FALSE;
1516         if (header->num_clauses)
1517                 cfg->arch.omit_fp = FALSE;
1518         if (cfg->param_area)
1519                 cfg->arch.omit_fp = FALSE;
1520         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1521                 cfg->arch.omit_fp = FALSE;
1522         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1523                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1524                 cfg->arch.omit_fp = FALSE;
1525         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1526                 ArgInfo *ainfo = &cinfo->args [i];
1527
1528                 if (ainfo->storage == ArgOnStack) {
1529                         /*
1530                          * The stack offset can only be determined when the frame
1531                          * size is known.
1532                          */
1533                         cfg->arch.omit_fp = FALSE;
1534                 }
1535         }
1536
1537         locals_size = 0;
1538         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1539                 MonoInst *ins = cfg->varinfo [i];
1540                 int ialign;
1541
1542                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1543         }
1544 }
1545
1546 GList *
1547 mono_arch_get_global_int_regs (MonoCompile *cfg)
1548 {
1549         GList *regs = NULL;
1550
1551         mono_arch_compute_omit_fp (cfg);
1552
1553         if (cfg->arch.omit_fp)
1554                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1555
1556         /* We use the callee saved registers for global allocation */
1557         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1558         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1559         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1560         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1561 #ifndef __native_client_codegen__
1562         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1563 #endif
1564 #ifdef TARGET_WIN32
1565         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1566         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1567 #endif
1568
1569         return regs;
1570 }
1571
1572 GList*
1573 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1574 {
1575         GList *regs = NULL;
1576         int i;
1577
1578         /* All XMM registers */
1579         for (i = 0; i < 16; ++i)
1580                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1581
1582         return regs;
1583 }
1584
1585 GList*
1586 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1587 {
1588         static GList *r = NULL;
1589
1590         if (r == NULL) {
1591                 GList *regs = NULL;
1592
1593                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1594                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1595                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1596                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1597                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1598 #ifndef __native_client_codegen__
1599                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1600 #endif
1601
1602                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1603                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1604                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1605                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1606                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1607                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1608                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1609                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1610
1611                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1612         }
1613
1614         return r;
1615 }
1616
1617 GList*
1618 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1619 {
1620         int i;
1621         static GList *r = NULL;
1622
1623         if (r == NULL) {
1624                 GList *regs = NULL;
1625
1626                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1627                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1628
1629                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1630         }
1631
1632         return r;
1633 }
1634
1635 /*
1636  * mono_arch_regalloc_cost:
1637  *
1638  *  Return the cost, in number of memory references, of the action of
1639  * allocating the variable VMV into a register during global register
1640  * allocation.
1641  */
1642 guint32
1643 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1644 {
1645         MonoInst *ins = cfg->varinfo [vmv->idx];
1646
1647         if (cfg->method->save_lmf)
1648                 /* The register is already saved */
1649                 /* substract 1 for the invisible store in the prolog */
1650                 return (ins->opcode == OP_ARG) ? 0 : 1;
1651         else
1652                 /* push+pop */
1653                 return (ins->opcode == OP_ARG) ? 1 : 2;
1654 }
1655
1656 /*
1657  * mono_arch_fill_argument_info:
1658  *
1659  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1660  * of the method.
1661  */
1662 void
1663 mono_arch_fill_argument_info (MonoCompile *cfg)
1664 {
1665         MonoType *sig_ret;
1666         MonoMethodSignature *sig;
1667         MonoInst *ins;
1668         int i;
1669         CallInfo *cinfo;
1670
1671         sig = mono_method_signature (cfg->method);
1672
1673         cinfo = cfg->arch.cinfo;
1674         sig_ret = mini_get_underlying_type (sig->ret);
1675
1676         /*
1677          * Contrary to mono_arch_allocate_vars (), the information should describe
1678          * where the arguments are at the beginning of the method, not where they can be
1679          * accessed during the execution of the method. The later makes no sense for the
1680          * global register allocator, since a variable can be in more than one location.
1681          */
1682         if (sig_ret->type != MONO_TYPE_VOID) {
1683                 switch (cinfo->ret.storage) {
1684                 case ArgInIReg:
1685                 case ArgInFloatSSEReg:
1686                 case ArgInDoubleSSEReg:
1687                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->ret.storage == ArgValuetypeAddrInIReg)) {
1688                                 cfg->vret_addr->opcode = OP_REGVAR;
1689                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1690                         }
1691                         else {
1692                                 cfg->ret->opcode = OP_REGVAR;
1693                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1694                         }
1695                         break;
1696                 case ArgValuetypeInReg:
1697                         cfg->ret->opcode = OP_REGOFFSET;
1698                         cfg->ret->inst_basereg = -1;
1699                         cfg->ret->inst_offset = -1;
1700                         break;
1701                 default:
1702                         g_assert_not_reached ();
1703                 }
1704         }
1705
1706         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1707                 ArgInfo *ainfo = &cinfo->args [i];
1708
1709                 ins = cfg->args [i];
1710
1711                 switch (ainfo->storage) {
1712                 case ArgInIReg:
1713                 case ArgInFloatSSEReg:
1714                 case ArgInDoubleSSEReg:
1715                         ins->opcode = OP_REGVAR;
1716                         ins->inst_c0 = ainfo->reg;
1717                         break;
1718                 case ArgOnStack:
1719                         ins->opcode = OP_REGOFFSET;
1720                         ins->inst_basereg = -1;
1721                         ins->inst_offset = -1;
1722                         break;
1723                 case ArgValuetypeInReg:
1724                         /* Dummy */
1725                         ins->opcode = OP_NOP;
1726                         break;
1727                 default:
1728                         g_assert_not_reached ();
1729                 }
1730         }
1731 }
1732
1733 /*
1734  * mono_arch_init_compile:
1735  *
1736  *   Set architecture specific flags in CFG.
1737  */
1738 void
1739 mono_arch_init_compile (MonoCompile *cfg)
1740 {
1741         cfg->have_card_table_wb = 1;
1742         cfg->have_op_generic_class_init = 1;
1743         cfg->have_generalized_imt_thunk = 1;
1744         cfg->gshared_supported = 1;
1745         cfg->have_tls_get = mono_amd64_have_tls_get ();
1746         cfg->have_liverange_ops = 1;
1747 }
1748
1749 void
1750 mono_arch_allocate_vars (MonoCompile *cfg)
1751 {
1752         MonoType *sig_ret;
1753         MonoMethodSignature *sig;
1754         MonoInst *ins;
1755         int i, offset;
1756         guint32 locals_stack_size, locals_stack_align;
1757         gint32 *offsets;
1758         CallInfo *cinfo;
1759
1760         sig = mono_method_signature (cfg->method);
1761
1762         cinfo = cfg->arch.cinfo;
1763         sig_ret = mini_get_underlying_type (sig->ret);
1764
1765         mono_arch_compute_omit_fp (cfg);
1766
1767         /*
1768          * We use the ABI calling conventions for managed code as well.
1769          * Exception: valuetypes are only sometimes passed or returned in registers.
1770          */
1771
1772         /*
1773          * The stack looks like this:
1774          * <incoming arguments passed on the stack>
1775          * <return value>
1776          * <lmf/caller saved registers>
1777          * <locals>
1778          * <spill area>
1779          * <localloc area>  -> grows dynamically
1780          * <params area>
1781          */
1782
1783         if (cfg->arch.omit_fp) {
1784                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1785                 cfg->frame_reg = AMD64_RSP;
1786                 offset = 0;
1787         } else {
1788                 /* Locals are allocated backwards from %fp */
1789                 cfg->frame_reg = AMD64_RBP;
1790                 offset = 0;
1791         }
1792
1793         cfg->arch.saved_iregs = cfg->used_int_regs;
1794         if (cfg->method->save_lmf)
1795                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1796                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1797
1798         if (cfg->arch.omit_fp)
1799                 cfg->arch.reg_save_area_offset = offset;
1800         /* Reserve space for callee saved registers */
1801         for (i = 0; i < AMD64_NREG; ++i)
1802                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1803                         offset += sizeof(mgreg_t);
1804                 }
1805         if (!cfg->arch.omit_fp)
1806                 cfg->arch.reg_save_area_offset = -offset;
1807
1808         if (sig_ret->type != MONO_TYPE_VOID) {
1809                 switch (cinfo->ret.storage) {
1810                 case ArgInIReg:
1811                 case ArgInFloatSSEReg:
1812                 case ArgInDoubleSSEReg:
1813                         cfg->ret->opcode = OP_REGVAR;
1814                         cfg->ret->inst_c0 = cinfo->ret.reg;
1815                         break;
1816                 case ArgValuetypeAddrInIReg:
1817                         /* The register is volatile */
1818                         cfg->vret_addr->opcode = OP_REGOFFSET;
1819                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1820                         if (cfg->arch.omit_fp) {
1821                                 cfg->vret_addr->inst_offset = offset;
1822                                 offset += 8;
1823                         } else {
1824                                 offset += 8;
1825                                 cfg->vret_addr->inst_offset = -offset;
1826                         }
1827                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1828                                 printf ("vret_addr =");
1829                                 mono_print_ins (cfg->vret_addr);
1830                         }
1831                         break;
1832                 case ArgValuetypeInReg:
1833                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1834                         cfg->ret->opcode = OP_REGOFFSET;
1835                         cfg->ret->inst_basereg = cfg->frame_reg;
1836                         if (cfg->arch.omit_fp) {
1837                                 cfg->ret->inst_offset = offset;
1838                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1839                         } else {
1840                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1841                                 cfg->ret->inst_offset = - offset;
1842                         }
1843                         break;
1844                 default:
1845                         g_assert_not_reached ();
1846                 }
1847                 cfg->ret->dreg = cfg->ret->inst_c0;
1848         }
1849
1850         /* Allocate locals */
1851         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1852         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1853                 char *mname = mono_method_full_name (cfg->method, TRUE);
1854                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1855                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1856                 g_free (mname);
1857                 return;
1858         }
1859
1860         if (locals_stack_align) {
1861                 offset += (locals_stack_align - 1);
1862                 offset &= ~(locals_stack_align - 1);
1863         }
1864         if (cfg->arch.omit_fp) {
1865                 cfg->locals_min_stack_offset = offset;
1866                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1867         } else {
1868                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1869                 cfg->locals_max_stack_offset = - offset;
1870         }
1871
1872         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1873                 if (offsets [i] != -1) {
1874                         MonoInst *ins = cfg->varinfo [i];
1875                         ins->opcode = OP_REGOFFSET;
1876                         ins->inst_basereg = cfg->frame_reg;
1877                         if (cfg->arch.omit_fp)
1878                                 ins->inst_offset = (offset + offsets [i]);
1879                         else
1880                                 ins->inst_offset = - (offset + offsets [i]);
1881                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1882                 }
1883         }
1884         offset += locals_stack_size;
1885
1886         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1887                 g_assert (!cfg->arch.omit_fp);
1888                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1889                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1890         }
1891
1892         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1893                 ins = cfg->args [i];
1894                 if (ins->opcode != OP_REGVAR) {
1895                         ArgInfo *ainfo = &cinfo->args [i];
1896                         gboolean inreg = TRUE;
1897
1898                         /* FIXME: Allocate volatile arguments to registers */
1899                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1900                                 inreg = FALSE;
1901
1902                         /*
1903                          * Under AMD64, all registers used to pass arguments to functions
1904                          * are volatile across calls.
1905                          * FIXME: Optimize this.
1906                          */
1907                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1908                                 inreg = FALSE;
1909
1910                         ins->opcode = OP_REGOFFSET;
1911
1912                         switch (ainfo->storage) {
1913                         case ArgInIReg:
1914                         case ArgInFloatSSEReg:
1915                         case ArgInDoubleSSEReg:
1916                         case ArgGSharedVtInReg:
1917                                 if (inreg) {
1918                                         ins->opcode = OP_REGVAR;
1919                                         ins->dreg = ainfo->reg;
1920                                 }
1921                                 break;
1922                         case ArgOnStack:
1923                         case ArgGSharedVtOnStack:
1924                                 g_assert (!cfg->arch.omit_fp);
1925                                 ins->opcode = OP_REGOFFSET;
1926                                 ins->inst_basereg = cfg->frame_reg;
1927                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1928                                 break;
1929                         case ArgValuetypeInReg:
1930                                 break;
1931                         case ArgValuetypeAddrInIReg: {
1932                                 MonoInst *indir;
1933                                 g_assert (!cfg->arch.omit_fp);
1934
1935                                 MONO_INST_NEW (cfg, indir, 0);
1936                                 indir->opcode = OP_REGOFFSET;
1937                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1938                                         indir->inst_basereg = cfg->frame_reg;
1939                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1940                                         offset += (sizeof (gpointer));
1941                                         indir->inst_offset = - offset;
1942                                 }
1943                                 else {
1944                                         indir->inst_basereg = cfg->frame_reg;
1945                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1946                                 }
1947
1948                                 ins->opcode = OP_VTARG_ADDR;
1949                                 ins->inst_left = indir;
1950
1951                                 break;
1952                         }
1953                         default:
1954                                 NOT_IMPLEMENTED;
1955                         }
1956
1957                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1958                                 ins->opcode = OP_REGOFFSET;
1959                                 ins->inst_basereg = cfg->frame_reg;
1960                                 /* These arguments are saved to the stack in the prolog */
1961                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1962                                 if (cfg->arch.omit_fp) {
1963                                         ins->inst_offset = offset;
1964                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1965                                         // Arguments are yet supported by the stack map creation code
1966                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1967                                 } else {
1968                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1969                                         ins->inst_offset = - offset;
1970                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1971                                 }
1972                         }
1973                 }
1974         }
1975
1976         cfg->stack_offset = offset;
1977 }
1978
1979 void
1980 mono_arch_create_vars (MonoCompile *cfg)
1981 {
1982         MonoMethodSignature *sig;
1983         CallInfo *cinfo;
1984         MonoType *sig_ret;
1985
1986         sig = mono_method_signature (cfg->method);
1987
1988         if (!cfg->arch.cinfo)
1989                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1990         cinfo = cfg->arch.cinfo;
1991
1992         if (cinfo->ret.storage == ArgValuetypeInReg)
1993                 cfg->ret_var_is_local = TRUE;
1994
1995         sig_ret = mini_get_underlying_type (sig->ret);
1996         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1997                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1998                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1999                         printf ("vret_addr = ");
2000                         mono_print_ins (cfg->vret_addr);
2001                 }
2002         }
2003
2004         if (cfg->gen_sdb_seq_points) {
2005                 MonoInst *ins;
2006
2007                 if (cfg->compile_aot) {
2008                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2009                         ins->flags |= MONO_INST_VOLATILE;
2010                         cfg->arch.seq_point_info_var = ins;
2011
2012                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2013                         ins->flags |= MONO_INST_VOLATILE;
2014                         cfg->arch.ss_tramp_var = ins;
2015                 }
2016
2017             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2018                 ins->flags |= MONO_INST_VOLATILE;
2019                 cfg->arch.ss_trigger_page_var = ins;
2020         }
2021
2022         if (cfg->method->save_lmf)
2023                 cfg->create_lmf_var = TRUE;
2024
2025         if (cfg->method->save_lmf) {
2026                 cfg->lmf_ir = TRUE;
2027 #if !defined(TARGET_WIN32)
2028                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2029                         cfg->lmf_ir_mono_lmf = TRUE;
2030 #endif
2031         }
2032 }
2033
2034 static void
2035 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2036 {
2037         MonoInst *ins;
2038
2039         switch (storage) {
2040         case ArgInIReg:
2041                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2042                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2043                 ins->sreg1 = tree->dreg;
2044                 MONO_ADD_INS (cfg->cbb, ins);
2045                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2046                 break;
2047         case ArgInFloatSSEReg:
2048                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2049                 ins->dreg = mono_alloc_freg (cfg);
2050                 ins->sreg1 = tree->dreg;
2051                 MONO_ADD_INS (cfg->cbb, ins);
2052
2053                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2054                 break;
2055         case ArgInDoubleSSEReg:
2056                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2057                 ins->dreg = mono_alloc_freg (cfg);
2058                 ins->sreg1 = tree->dreg;
2059                 MONO_ADD_INS (cfg->cbb, ins);
2060
2061                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2062
2063                 break;
2064         default:
2065                 g_assert_not_reached ();
2066         }
2067 }
2068
2069 static int
2070 arg_storage_to_load_membase (ArgStorage storage)
2071 {
2072         switch (storage) {
2073         case ArgInIReg:
2074 #if defined(__mono_ilp32__)
2075                 return OP_LOADI8_MEMBASE;
2076 #else
2077                 return OP_LOAD_MEMBASE;
2078 #endif
2079         case ArgInDoubleSSEReg:
2080                 return OP_LOADR8_MEMBASE;
2081         case ArgInFloatSSEReg:
2082                 return OP_LOADR4_MEMBASE;
2083         default:
2084                 g_assert_not_reached ();
2085         }
2086
2087         return -1;
2088 }
2089
2090 static void
2091 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2092 {
2093         MonoMethodSignature *tmp_sig;
2094         int sig_reg;
2095
2096         if (call->tail_call)
2097                 NOT_IMPLEMENTED;
2098
2099         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2100
2101         /*
2102          * mono_ArgIterator_Setup assumes the signature cookie is
2103          * passed first and all the arguments which were before it are
2104          * passed on the stack after the signature. So compensate by
2105          * passing a different signature.
2106          */
2107         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2108         tmp_sig->param_count -= call->signature->sentinelpos;
2109         tmp_sig->sentinelpos = 0;
2110         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2111
2112         sig_reg = mono_alloc_ireg (cfg);
2113         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2114
2115         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2116 }
2117
2118 #ifdef ENABLE_LLVM
2119 static inline LLVMArgStorage
2120 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2121 {
2122         switch (storage) {
2123         case ArgInIReg:
2124                 return LLVMArgInIReg;
2125         case ArgNone:
2126                 return LLVMArgNone;
2127         case ArgGSharedVtInReg:
2128         case ArgGSharedVtOnStack:
2129                 return LLVMArgGSharedVt;
2130         default:
2131                 g_assert_not_reached ();
2132                 return LLVMArgNone;
2133         }
2134 }
2135
2136 LLVMCallInfo*
2137 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2138 {
2139         int i, n;
2140         CallInfo *cinfo;
2141         ArgInfo *ainfo;
2142         int j;
2143         LLVMCallInfo *linfo;
2144         MonoType *t, *sig_ret;
2145
2146         n = sig->param_count + sig->hasthis;
2147         sig_ret = mini_get_underlying_type (sig->ret);
2148
2149         cinfo = get_call_info (cfg->mempool, sig);
2150
2151         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2152
2153         /*
2154          * LLVM always uses the native ABI while we use our own ABI, the
2155          * only difference is the handling of vtypes:
2156          * - we only pass/receive them in registers in some cases, and only
2157          *   in 1 or 2 integer registers.
2158          */
2159         if (cinfo->ret.storage == ArgValuetypeInReg) {
2160                 if (sig->pinvoke) {
2161                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2162                         cfg->disable_llvm = TRUE;
2163                         return linfo;
2164                 }
2165
2166                 linfo->ret.storage = LLVMArgVtypeInReg;
2167                 for (j = 0; j < 2; ++j)
2168                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2169         }
2170
2171         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2172                 /* Vtype returned using a hidden argument */
2173                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2174                 linfo->vret_arg_index = cinfo->vret_arg_index;
2175         }
2176
2177         for (i = 0; i < n; ++i) {
2178                 ainfo = cinfo->args + i;
2179
2180                 if (i >= sig->hasthis)
2181                         t = sig->params [i - sig->hasthis];
2182                 else
2183                         t = &mono_defaults.int_class->byval_arg;
2184
2185                 linfo->args [i].storage = LLVMArgNone;
2186
2187                 switch (ainfo->storage) {
2188                 case ArgInIReg:
2189                         linfo->args [i].storage = LLVMArgInIReg;
2190                         break;
2191                 case ArgInDoubleSSEReg:
2192                 case ArgInFloatSSEReg:
2193                         linfo->args [i].storage = LLVMArgInFPReg;
2194                         break;
2195                 case ArgOnStack:
2196                         if (MONO_TYPE_ISSTRUCT (t)) {
2197                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2198                         } else {
2199                                 linfo->args [i].storage = LLVMArgInIReg;
2200                                 if (!t->byref) {
2201                                         if (t->type == MONO_TYPE_R4)
2202                                                 linfo->args [i].storage = LLVMArgInFPReg;
2203                                         else if (t->type == MONO_TYPE_R8)
2204                                                 linfo->args [i].storage = LLVMArgInFPReg;
2205                                 }
2206                         }
2207                         break;
2208                 case ArgValuetypeInReg:
2209                         if (sig->pinvoke) {
2210                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2211                                 cfg->disable_llvm = TRUE;
2212                                 return linfo;
2213                         }
2214
2215                         linfo->args [i].storage = LLVMArgVtypeInReg;
2216                         for (j = 0; j < 2; ++j)
2217                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2218                         break;
2219                 case ArgGSharedVtInReg:
2220                 case ArgGSharedVtOnStack:
2221                         linfo->args [i].storage = LLVMArgGSharedVt;
2222                         break;
2223                 default:
2224                         cfg->exception_message = g_strdup ("ainfo->storage");
2225                         cfg->disable_llvm = TRUE;
2226                         break;
2227                 }
2228         }
2229
2230         return linfo;
2231 }
2232 #endif
2233
2234 void
2235 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2236 {
2237         MonoInst *arg, *in;
2238         MonoMethodSignature *sig;
2239         MonoType *sig_ret;
2240         int i, n;
2241         CallInfo *cinfo;
2242         ArgInfo *ainfo;
2243
2244         sig = call->signature;
2245         n = sig->param_count + sig->hasthis;
2246
2247         cinfo = get_call_info (cfg->mempool, sig);
2248
2249         sig_ret = sig->ret;
2250
2251         if (COMPILE_LLVM (cfg)) {
2252                 /* We shouldn't be called in the llvm case */
2253                 cfg->disable_llvm = TRUE;
2254                 return;
2255         }
2256
2257         /*
2258          * Emit all arguments which are passed on the stack to prevent register
2259          * allocation problems.
2260          */
2261         for (i = 0; i < n; ++i) {
2262                 MonoType *t;
2263                 ainfo = cinfo->args + i;
2264
2265                 in = call->args [i];
2266
2267                 if (sig->hasthis && i == 0)
2268                         t = &mono_defaults.object_class->byval_arg;
2269                 else
2270                         t = sig->params [i - sig->hasthis];
2271
2272                 t = mini_get_underlying_type (t);
2273                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2274                         if (!t->byref) {
2275                                 if (t->type == MONO_TYPE_R4)
2276                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2277                                 else if (t->type == MONO_TYPE_R8)
2278                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2279                                 else
2280                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2281                         } else {
2282                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2283                         }
2284                         if (cfg->compute_gc_maps) {
2285                                 MonoInst *def;
2286
2287                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2288                         }
2289                 }
2290         }
2291
2292         /*
2293          * Emit all parameters passed in registers in non-reverse order for better readability
2294          * and to help the optimization in emit_prolog ().
2295          */
2296         for (i = 0; i < n; ++i) {
2297                 ainfo = cinfo->args + i;
2298
2299                 in = call->args [i];
2300
2301                 if (ainfo->storage == ArgInIReg)
2302                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2303         }
2304
2305         for (i = n - 1; i >= 0; --i) {
2306                 MonoType *t;
2307
2308                 ainfo = cinfo->args + i;
2309
2310                 in = call->args [i];
2311
2312                 if (sig->hasthis && i == 0)
2313                         t = &mono_defaults.object_class->byval_arg;
2314                 else
2315                         t = sig->params [i - sig->hasthis];
2316                 t = mini_get_underlying_type (t);
2317
2318                 switch (ainfo->storage) {
2319                 case ArgInIReg:
2320                         /* Already done */
2321                         break;
2322                 case ArgInFloatSSEReg:
2323                 case ArgInDoubleSSEReg:
2324                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2325                         break;
2326                 case ArgOnStack:
2327                 case ArgValuetypeInReg:
2328                 case ArgValuetypeAddrInIReg:
2329                 case ArgGSharedVtInReg:
2330                 case ArgGSharedVtOnStack: {
2331                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2332                                 /* Already emitted above */
2333                                 break;
2334                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2335                                 MonoInst *call_inst = (MonoInst*)call;
2336                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2337                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2338                                 break;
2339                         }
2340
2341                         guint32 align;
2342                         guint32 size;
2343
2344                         if (t->type == MONO_TYPE_TYPEDBYREF) {
2345                                 size = sizeof (MonoTypedRef);
2346                                 align = sizeof (gpointer);
2347                         }
2348                         else {
2349                                 if (sig->pinvoke)
2350                                         size = mono_type_native_stack_size (t, &align);
2351                                 else {
2352                                         /*
2353                                          * Other backends use mono_type_stack_size (), but that
2354                                          * aligns the size to 8, which is larger than the size of
2355                                          * the source, leading to reads of invalid memory if the
2356                                          * source is at the end of address space.
2357                                          */
2358                                         size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2359                                 }
2360                         }
2361
2362                         if (size >= 10000) {
2363                                 /* Avoid asserts in emit_memcpy () */
2364                                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2365                                 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2366                                 /* Continue normally */
2367                         }
2368
2369                         if (size > 0) {
2370                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2371                                 arg->sreg1 = in->dreg;
2372                                 arg->klass = mono_class_from_mono_type (t);
2373                                 arg->backend.size = size;
2374                                 arg->inst_p0 = call;
2375                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2376                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2377
2378                                 MONO_ADD_INS (cfg->cbb, arg);
2379                         }
2380                         break;
2381                 }
2382                 default:
2383                         g_assert_not_reached ();
2384                 }
2385
2386                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2387                         /* Emit the signature cookie just before the implicit arguments */
2388                         emit_sig_cookie (cfg, call, cinfo);
2389         }
2390
2391         /* Handle the case where there are no implicit arguments */
2392         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2393                 emit_sig_cookie (cfg, call, cinfo);
2394
2395         switch (cinfo->ret.storage) {
2396         case ArgValuetypeInReg:
2397                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2398                         /*
2399                          * Tell the JIT to use a more efficient calling convention: call using
2400                          * OP_CALL, compute the result location after the call, and save the
2401                          * result there.
2402                          */
2403                         call->vret_in_reg = TRUE;
2404                         /*
2405                          * Nullify the instruction computing the vret addr to enable
2406                          * future optimizations.
2407                          */
2408                         if (call->vret_var)
2409                                 NULLIFY_INS (call->vret_var);
2410                 } else {
2411                         if (call->tail_call)
2412                                 NOT_IMPLEMENTED;
2413                         /*
2414                          * The valuetype is in RAX:RDX after the call, need to be copied to
2415                          * the stack. Push the address here, so the call instruction can
2416                          * access it.
2417                          */
2418                         if (!cfg->arch.vret_addr_loc) {
2419                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2420                                 /* Prevent it from being register allocated or optimized away */
2421                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2422                         }
2423
2424                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2425                 }
2426                 break;
2427         case ArgValuetypeAddrInIReg: {
2428                 MonoInst *vtarg;
2429                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2430                 vtarg->sreg1 = call->vret_var->dreg;
2431                 vtarg->dreg = mono_alloc_preg (cfg);
2432                 MONO_ADD_INS (cfg->cbb, vtarg);
2433
2434                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2435                 break;
2436         }
2437         default:
2438                 break;
2439         }
2440
2441         if (cfg->method->save_lmf) {
2442                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2443                 MONO_ADD_INS (cfg->cbb, arg);
2444         }
2445
2446         call->stack_usage = cinfo->stack_usage;
2447 }
2448
2449 void
2450 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2451 {
2452         MonoInst *arg;
2453         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2454         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2455         int size = ins->backend.size;
2456
2457         switch (ainfo->storage) {
2458         case ArgValuetypeInReg: {
2459                 MonoInst *load;
2460                 int part;
2461
2462                 for (part = 0; part < 2; ++part) {
2463                         if (ainfo->pair_storage [part] == ArgNone)
2464                                 continue;
2465
2466                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2467                         load->inst_basereg = src->dreg;
2468                         load->inst_offset = part * sizeof(mgreg_t);
2469
2470                         switch (ainfo->pair_storage [part]) {
2471                         case ArgInIReg:
2472                                 load->dreg = mono_alloc_ireg (cfg);
2473                                 break;
2474                         case ArgInDoubleSSEReg:
2475                         case ArgInFloatSSEReg:
2476                                 load->dreg = mono_alloc_freg (cfg);
2477                                 break;
2478                         default:
2479                                 g_assert_not_reached ();
2480                         }
2481                         MONO_ADD_INS (cfg->cbb, load);
2482
2483                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2484                 }
2485                 break;
2486         }
2487         case ArgValuetypeAddrInIReg: {
2488                 MonoInst *vtaddr, *load;
2489                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2490
2491                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2492                 cfg->has_indirection = TRUE;
2493                 load->inst_p0 = vtaddr;
2494                 vtaddr->flags |= MONO_INST_INDIRECT;
2495                 load->type = STACK_MP;
2496                 load->klass = vtaddr->klass;
2497                 load->dreg = mono_alloc_ireg (cfg);
2498                 MONO_ADD_INS (cfg->cbb, load);
2499                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2500
2501                 if (ainfo->pair_storage [0] == ArgInIReg) {
2502                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2503                         arg->dreg = mono_alloc_ireg (cfg);
2504                         arg->sreg1 = load->dreg;
2505                         arg->inst_imm = 0;
2506                         MONO_ADD_INS (cfg->cbb, arg);
2507                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2508                 } else {
2509                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2510                 }
2511                 break;
2512         }
2513         case ArgGSharedVtInReg:
2514                 /* Pass by addr */
2515                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2516                 break;
2517         case ArgGSharedVtOnStack:
2518                 g_assert_not_reached ();
2519                 break;
2520         default:
2521                 if (size == 8) {
2522                         int dreg = mono_alloc_ireg (cfg);
2523
2524                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2525                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2526                 } else if (size <= 40) {
2527                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2528                 } else {
2529                         // FIXME: Code growth
2530                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2531                 }
2532
2533                 if (cfg->compute_gc_maps) {
2534                         MonoInst *def;
2535                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2536                 }
2537         }
2538 }
2539
2540 void
2541 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2542 {
2543         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2544
2545         if (ret->type == MONO_TYPE_R4) {
2546                 if (COMPILE_LLVM (cfg))
2547                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2548                 else
2549                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2550                 return;
2551         } else if (ret->type == MONO_TYPE_R8) {
2552                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2553                 return;
2554         }
2555
2556         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2557 }
2558
2559 #endif /* DISABLE_JIT */
2560
2561 #define EMIT_COND_BRANCH(ins,cond,sign) \
2562         if (ins->inst_true_bb->native_offset) { \
2563                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2564         } else { \
2565                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2566                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2567             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2568                         x86_branch8 (code, cond, 0, sign); \
2569                 else \
2570                         x86_branch32 (code, cond, 0, sign); \
2571 }
2572
2573 typedef struct {
2574         MonoMethodSignature *sig;
2575         CallInfo *cinfo;
2576 } ArchDynCallInfo;
2577
2578 static gboolean
2579 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2580 {
2581         int i;
2582
2583 #ifdef HOST_WIN32
2584         return FALSE;
2585 #endif
2586
2587         switch (cinfo->ret.storage) {
2588         case ArgNone:
2589         case ArgInIReg:
2590                 break;
2591         case ArgValuetypeInReg: {
2592                 ArgInfo *ainfo = &cinfo->ret;
2593
2594                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2595                         return FALSE;
2596                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2597                         return FALSE;
2598                 break;
2599         }
2600         default:
2601                 return FALSE;
2602         }
2603
2604         for (i = 0; i < cinfo->nargs; ++i) {
2605                 ArgInfo *ainfo = &cinfo->args [i];
2606                 switch (ainfo->storage) {
2607                 case ArgInIReg:
2608                         break;
2609                 case ArgValuetypeInReg:
2610                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2611                                 return FALSE;
2612                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2613                                 return FALSE;
2614                         break;
2615                 default:
2616                         return FALSE;
2617                 }
2618         }
2619
2620         return TRUE;
2621 }
2622
2623 /*
2624  * mono_arch_dyn_call_prepare:
2625  *
2626  *   Return a pointer to an arch-specific structure which contains information
2627  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2628  * supported for SIG.
2629  * This function is equivalent to ffi_prep_cif in libffi.
2630  */
2631 MonoDynCallInfo*
2632 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2633 {
2634         ArchDynCallInfo *info;
2635         CallInfo *cinfo;
2636
2637         cinfo = get_call_info (NULL, sig);
2638
2639         if (!dyn_call_supported (sig, cinfo)) {
2640                 g_free (cinfo);
2641                 return NULL;
2642         }
2643
2644         info = g_new0 (ArchDynCallInfo, 1);
2645         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2646         info->sig = sig;
2647         info->cinfo = cinfo;
2648
2649         return (MonoDynCallInfo*)info;
2650 }
2651
2652 /*
2653  * mono_arch_dyn_call_free:
2654  *
2655  *   Free a MonoDynCallInfo structure.
2656  */
2657 void
2658 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2659 {
2660         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2661
2662         g_free (ainfo->cinfo);
2663         g_free (ainfo);
2664 }
2665
2666 #if !defined(__native_client__)
2667 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2668 #define GREG_TO_PTR(greg) (gpointer)(greg)
2669 #else
2670 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2671 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2672 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2673 #endif
2674
2675 /*
2676  * mono_arch_get_start_dyn_call:
2677  *
2678  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2679  * store the result into BUF.
2680  * ARGS should be an array of pointers pointing to the arguments.
2681  * RET should point to a memory buffer large enought to hold the result of the
2682  * call.
2683  * This function should be as fast as possible, any work which does not depend
2684  * on the actual values of the arguments should be done in
2685  * mono_arch_dyn_call_prepare ().
2686  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2687  * libffi.
2688  */
2689 void
2690 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2691 {
2692         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2693         DynCallArgs *p = (DynCallArgs*)buf;
2694         int arg_index, greg, i, pindex;
2695         MonoMethodSignature *sig = dinfo->sig;
2696
2697         g_assert (buf_len >= sizeof (DynCallArgs));
2698
2699         p->res = 0;
2700         p->ret = ret;
2701
2702         arg_index = 0;
2703         greg = 0;
2704         pindex = 0;
2705
2706         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2707                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2708                 if (!sig->hasthis)
2709                         pindex = 1;
2710         }
2711
2712         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg)
2713                 p->regs [greg ++] = PTR_TO_GREG(ret);
2714
2715         for (i = pindex; i < sig->param_count; i++) {
2716                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2717                 gpointer *arg = args [arg_index ++];
2718
2719                 if (t->byref) {
2720                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2721                         continue;
2722                 }
2723
2724                 switch (t->type) {
2725                 case MONO_TYPE_STRING:
2726                 case MONO_TYPE_CLASS:
2727                 case MONO_TYPE_ARRAY:
2728                 case MONO_TYPE_SZARRAY:
2729                 case MONO_TYPE_OBJECT:
2730                 case MONO_TYPE_PTR:
2731                 case MONO_TYPE_I:
2732                 case MONO_TYPE_U:
2733 #if !defined(__mono_ilp32__)
2734                 case MONO_TYPE_I8:
2735                 case MONO_TYPE_U8:
2736 #endif
2737                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2738                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2739                         break;
2740 #if defined(__mono_ilp32__)
2741                 case MONO_TYPE_I8:
2742                 case MONO_TYPE_U8:
2743                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2744                         p->regs [greg ++] = *(guint64*)(arg);
2745                         break;
2746 #endif
2747                 case MONO_TYPE_U1:
2748                         p->regs [greg ++] = *(guint8*)(arg);
2749                         break;
2750                 case MONO_TYPE_I1:
2751                         p->regs [greg ++] = *(gint8*)(arg);
2752                         break;
2753                 case MONO_TYPE_I2:
2754                         p->regs [greg ++] = *(gint16*)(arg);
2755                         break;
2756                 case MONO_TYPE_U2:
2757                         p->regs [greg ++] = *(guint16*)(arg);
2758                         break;
2759                 case MONO_TYPE_I4:
2760                         p->regs [greg ++] = *(gint32*)(arg);
2761                         break;
2762                 case MONO_TYPE_U4:
2763                         p->regs [greg ++] = *(guint32*)(arg);
2764                         break;
2765                 case MONO_TYPE_GENERICINST:
2766                     if (MONO_TYPE_IS_REFERENCE (t)) {
2767                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2768                                 break;
2769                         } else {
2770                                 /* Fall through */
2771                         }
2772                 case MONO_TYPE_VALUETYPE: {
2773                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2774
2775                         g_assert (ainfo->storage == ArgValuetypeInReg);
2776                         if (ainfo->pair_storage [0] != ArgNone) {
2777                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2778                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2779                         }
2780                         if (ainfo->pair_storage [1] != ArgNone) {
2781                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2782                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2783                         }
2784                         break;
2785                 }
2786                 default:
2787                         g_assert_not_reached ();
2788                 }
2789         }
2790
2791         g_assert (greg <= PARAM_REGS);
2792 }
2793
2794 /*
2795  * mono_arch_finish_dyn_call:
2796  *
2797  *   Store the result of a dyn call into the return value buffer passed to
2798  * start_dyn_call ().
2799  * This function should be as fast as possible, any work which does not depend
2800  * on the actual values of the arguments should be done in
2801  * mono_arch_dyn_call_prepare ().
2802  */
2803 void
2804 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2805 {
2806         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2807         MonoMethodSignature *sig = dinfo->sig;
2808         guint8 *ret = ((DynCallArgs*)buf)->ret;
2809         mgreg_t res = ((DynCallArgs*)buf)->res;
2810         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2811
2812         switch (sig_ret->type) {
2813         case MONO_TYPE_VOID:
2814                 *(gpointer*)ret = NULL;
2815                 break;
2816         case MONO_TYPE_STRING:
2817         case MONO_TYPE_CLASS:
2818         case MONO_TYPE_ARRAY:
2819         case MONO_TYPE_SZARRAY:
2820         case MONO_TYPE_OBJECT:
2821         case MONO_TYPE_I:
2822         case MONO_TYPE_U:
2823         case MONO_TYPE_PTR:
2824                 *(gpointer*)ret = GREG_TO_PTR(res);
2825                 break;
2826         case MONO_TYPE_I1:
2827                 *(gint8*)ret = res;
2828                 break;
2829         case MONO_TYPE_U1:
2830                 *(guint8*)ret = res;
2831                 break;
2832         case MONO_TYPE_I2:
2833                 *(gint16*)ret = res;
2834                 break;
2835         case MONO_TYPE_U2:
2836                 *(guint16*)ret = res;
2837                 break;
2838         case MONO_TYPE_I4:
2839                 *(gint32*)ret = res;
2840                 break;
2841         case MONO_TYPE_U4:
2842                 *(guint32*)ret = res;
2843                 break;
2844         case MONO_TYPE_I8:
2845                 *(gint64*)ret = res;
2846                 break;
2847         case MONO_TYPE_U8:
2848                 *(guint64*)ret = res;
2849                 break;
2850         case MONO_TYPE_GENERICINST:
2851                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2852                         *(gpointer*)ret = GREG_TO_PTR(res);
2853                         break;
2854                 } else {
2855                         /* Fall through */
2856                 }
2857         case MONO_TYPE_VALUETYPE:
2858                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2859                         /* Nothing to do */
2860                 } else {
2861                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2862
2863                         g_assert (ainfo->storage == ArgValuetypeInReg);
2864
2865                         if (ainfo->pair_storage [0] != ArgNone) {
2866                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2867                                 ((mgreg_t*)ret)[0] = res;
2868                         }
2869
2870                         g_assert (ainfo->pair_storage [1] == ArgNone);
2871                 }
2872                 break;
2873         default:
2874                 g_assert_not_reached ();
2875         }
2876 }
2877
2878 /* emit an exception if condition is fail */
2879 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2880         do {                                                        \
2881                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2882                 if (tins == NULL) {                                                                             \
2883                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2884                                         MONO_PATCH_INFO_EXC, exc_name);  \
2885                         x86_branch32 (code, cond, 0, signed);               \
2886                 } else {        \
2887                         EMIT_COND_BRANCH (tins, cond, signed);  \
2888                 }                       \
2889         } while (0);
2890
2891 #define EMIT_FPCOMPARE(code) do { \
2892         amd64_fcompp (code); \
2893         amd64_fnstsw (code); \
2894 } while (0);
2895
2896 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2897     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2898         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2899         amd64_ ##op (code); \
2900         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2901         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2902 } while (0);
2903
2904 static guint8*
2905 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2906 {
2907         gboolean no_patch = FALSE;
2908
2909         /*
2910          * FIXME: Add support for thunks
2911          */
2912         {
2913                 gboolean near_call = FALSE;
2914
2915                 /*
2916                  * Indirect calls are expensive so try to make a near call if possible.
2917                  * The caller memory is allocated by the code manager so it is
2918                  * guaranteed to be at a 32 bit offset.
2919                  */
2920
2921                 if (patch_type != MONO_PATCH_INFO_ABS) {
2922                         /* The target is in memory allocated using the code manager */
2923                         near_call = TRUE;
2924
2925                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2926                                 if (((MonoMethod*)data)->klass->image->aot_module)
2927                                         /* The callee might be an AOT method */
2928                                         near_call = FALSE;
2929                                 if (((MonoMethod*)data)->dynamic)
2930                                         /* The target is in malloc-ed memory */
2931                                         near_call = FALSE;
2932                         }
2933
2934                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2935                                 /*
2936                                  * The call might go directly to a native function without
2937                                  * the wrapper.
2938                                  */
2939                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2940                                 if (mi) {
2941                                         gconstpointer target = mono_icall_get_wrapper (mi);
2942                                         if ((((guint64)target) >> 32) != 0)
2943                                                 near_call = FALSE;
2944                                 }
2945                         }
2946                 }
2947                 else {
2948                         MonoJumpInfo *jinfo = NULL;
2949
2950                         if (cfg->abs_patches)
2951                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2952                         if (jinfo) {
2953                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2954                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2955                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2956                                                 near_call = TRUE;
2957                                         no_patch = TRUE;
2958                                 } else {
2959                                         /*
2960                                          * This is not really an optimization, but required because the
2961                                          * generic class init trampolines use R11 to pass the vtable.
2962                                          */
2963                                         near_call = TRUE;
2964                                 }
2965                         } else {
2966                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2967                                 if (info) {
2968                                         if (info->func == info->wrapper) {
2969                                                 /* No wrapper */
2970                                                 if ((((guint64)info->func) >> 32) == 0)
2971                                                         near_call = TRUE;
2972                                         }
2973                                         else {
2974                                                 /* See the comment in mono_codegen () */
2975                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2976                                                         near_call = TRUE;
2977                                         }
2978                                 }
2979                                 else if ((((guint64)data) >> 32) == 0) {
2980                                         near_call = TRUE;
2981                                         no_patch = TRUE;
2982                                 }
2983                         }
2984                 }
2985
2986                 if (cfg->method->dynamic)
2987                         /* These methods are allocated using malloc */
2988                         near_call = FALSE;
2989
2990 #ifdef MONO_ARCH_NOMAP32BIT
2991                 near_call = FALSE;
2992 #endif
2993 #if defined(__native_client__)
2994                 /* Always use near_call == TRUE for Native Client */
2995                 near_call = TRUE;
2996 #endif
2997                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2998                 if (optimize_for_xen)
2999                         near_call = FALSE;
3000
3001                 if (cfg->compile_aot) {
3002                         near_call = TRUE;
3003                         no_patch = TRUE;
3004                 }
3005
3006                 if (near_call) {
3007                         /*
3008                          * Align the call displacement to an address divisible by 4 so it does
3009                          * not span cache lines. This is required for code patching to work on SMP
3010                          * systems.
3011                          */
3012                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3013                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3014                                 amd64_padding (code, pad_size);
3015                         }
3016                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3017                         amd64_call_code (code, 0);
3018                 }
3019                 else {
3020                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3021                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3022                         amd64_call_reg (code, GP_SCRATCH_REG);
3023                 }
3024         }
3025
3026         return code;
3027 }
3028
3029 static inline guint8*
3030 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3031 {
3032 #ifdef TARGET_WIN32
3033         if (win64_adjust_stack)
3034                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3035 #endif
3036         code = emit_call_body (cfg, code, patch_type, data);
3037 #ifdef TARGET_WIN32
3038         if (win64_adjust_stack)
3039                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3040 #endif
3041
3042         return code;
3043 }
3044
3045 static inline int
3046 store_membase_imm_to_store_membase_reg (int opcode)
3047 {
3048         switch (opcode) {
3049         case OP_STORE_MEMBASE_IMM:
3050                 return OP_STORE_MEMBASE_REG;
3051         case OP_STOREI4_MEMBASE_IMM:
3052                 return OP_STOREI4_MEMBASE_REG;
3053         case OP_STOREI8_MEMBASE_IMM:
3054                 return OP_STOREI8_MEMBASE_REG;
3055         }
3056
3057         return -1;
3058 }
3059
3060 #ifndef DISABLE_JIT
3061
3062 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3063
3064 /*
3065  * mono_arch_peephole_pass_1:
3066  *
3067  *   Perform peephole opts which should/can be performed before local regalloc
3068  */
3069 void
3070 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3071 {
3072         MonoInst *ins, *n;
3073
3074         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3075                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3076
3077                 switch (ins->opcode) {
3078                 case OP_ADD_IMM:
3079                 case OP_IADD_IMM:
3080                 case OP_LADD_IMM:
3081                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3082                                 /*
3083                                  * X86_LEA is like ADD, but doesn't have the
3084                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3085                                  * its operand to 64 bit.
3086                                  */
3087                                 ins->opcode = OP_X86_LEA_MEMBASE;
3088                                 ins->inst_basereg = ins->sreg1;
3089                         }
3090                         break;
3091                 case OP_LXOR:
3092                 case OP_IXOR:
3093                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3094                                 MonoInst *ins2;
3095
3096                                 /*
3097                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3098                                  * the latter has length 2-3 instead of 6 (reverse constant
3099                                  * propagation). These instruction sequences are very common
3100                                  * in the initlocals bblock.
3101                                  */
3102                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3103                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3104                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3105                                                 ins2->sreg1 = ins->dreg;
3106                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3107                                                 /* Continue */
3108                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3109                                                 NULLIFY_INS (ins2);
3110                                                 /* Continue */
3111                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3112                                                 /* Continue */
3113                                         } else {
3114                                                 break;
3115                                         }
3116                                 }
3117                         }
3118                         break;
3119                 case OP_COMPARE_IMM:
3120                 case OP_LCOMPARE_IMM:
3121                         /* OP_COMPARE_IMM (reg, 0)
3122                          * -->
3123                          * OP_AMD64_TEST_NULL (reg)
3124                          */
3125                         if (!ins->inst_imm)
3126                                 ins->opcode = OP_AMD64_TEST_NULL;
3127                         break;
3128                 case OP_ICOMPARE_IMM:
3129                         if (!ins->inst_imm)
3130                                 ins->opcode = OP_X86_TEST_NULL;
3131                         break;
3132                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3133                         /*
3134                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3135                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3136                          * -->
3137                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3138                          * OP_COMPARE_IMM reg, imm
3139                          *
3140                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3141                          */
3142                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3143                             ins->inst_basereg == last_ins->inst_destbasereg &&
3144                             ins->inst_offset == last_ins->inst_offset) {
3145                                         ins->opcode = OP_ICOMPARE_IMM;
3146                                         ins->sreg1 = last_ins->sreg1;
3147
3148                                         /* check if we can remove cmp reg,0 with test null */
3149                                         if (!ins->inst_imm)
3150                                                 ins->opcode = OP_X86_TEST_NULL;
3151                                 }
3152
3153                         break;
3154                 }
3155
3156                 mono_peephole_ins (bb, ins);
3157         }
3158 }
3159
3160 void
3161 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3162 {
3163         MonoInst *ins, *n;
3164
3165         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3166                 switch (ins->opcode) {
3167                 case OP_ICONST:
3168                 case OP_I8CONST: {
3169                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3170                         /* reg = 0 -> XOR (reg, reg) */
3171                         /* XOR sets cflags on x86, so we cant do it always */
3172                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3173                                 ins->opcode = OP_LXOR;
3174                                 ins->sreg1 = ins->dreg;
3175                                 ins->sreg2 = ins->dreg;
3176                                 /* Fall through */
3177                         } else {
3178                                 break;
3179                         }
3180                 }
3181                 case OP_LXOR:
3182                         /*
3183                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3184                          * 0 result into 64 bits.
3185                          */
3186                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3187                                 ins->opcode = OP_IXOR;
3188                         }
3189                         /* Fall through */
3190                 case OP_IXOR:
3191                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3192                                 MonoInst *ins2;
3193
3194                                 /*
3195                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3196                                  * the latter has length 2-3 instead of 6 (reverse constant
3197                                  * propagation). These instruction sequences are very common
3198                                  * in the initlocals bblock.
3199                                  */
3200                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3201                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3202                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3203                                                 ins2->sreg1 = ins->dreg;
3204                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3205                                                 /* Continue */
3206                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3207                                                 NULLIFY_INS (ins2);
3208                                                 /* Continue */
3209                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3210                                                 /* Continue */
3211                                         } else {
3212                                                 break;
3213                                         }
3214                                 }
3215                         }
3216                         break;
3217                 case OP_IADD_IMM:
3218                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3219                                 ins->opcode = OP_X86_INC_REG;
3220                         break;
3221                 case OP_ISUB_IMM:
3222                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3223                                 ins->opcode = OP_X86_DEC_REG;
3224                         break;
3225                 }
3226
3227                 mono_peephole_ins (bb, ins);
3228         }
3229 }
3230
3231 #define NEW_INS(cfg,ins,dest,op) do {   \
3232                 MONO_INST_NEW ((cfg), (dest), (op)); \
3233         (dest)->cil_code = (ins)->cil_code; \
3234         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3235         } while (0)
3236
3237 /*
3238  * mono_arch_lowering_pass:
3239  *
3240  *  Converts complex opcodes into simpler ones so that each IR instruction
3241  * corresponds to one machine instruction.
3242  */
3243 void
3244 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3245 {
3246         MonoInst *ins, *n, *temp;
3247
3248         /*
3249          * FIXME: Need to add more instructions, but the current machine
3250          * description can't model some parts of the composite instructions like
3251          * cdq.
3252          */
3253         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3254                 switch (ins->opcode) {
3255                 case OP_DIV_IMM:
3256                 case OP_REM_IMM:
3257                 case OP_IDIV_IMM:
3258                 case OP_IDIV_UN_IMM:
3259                 case OP_IREM_UN_IMM:
3260                 case OP_LREM_IMM:
3261                 case OP_IREM_IMM:
3262                         mono_decompose_op_imm (cfg, bb, ins);
3263                         break;
3264                 case OP_COMPARE_IMM:
3265                 case OP_LCOMPARE_IMM:
3266                         if (!amd64_use_imm32 (ins->inst_imm)) {
3267                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3268                                 temp->inst_c0 = ins->inst_imm;
3269                                 temp->dreg = mono_alloc_ireg (cfg);
3270                                 ins->opcode = OP_COMPARE;
3271                                 ins->sreg2 = temp->dreg;
3272                         }
3273                         break;
3274 #ifndef __mono_ilp32__
3275                 case OP_LOAD_MEMBASE:
3276 #endif
3277                 case OP_LOADI8_MEMBASE:
3278 #ifndef __native_client_codegen__
3279                 /*  Don't generate memindex opcodes (to simplify */
3280                 /*  read sandboxing) */
3281                         if (!amd64_use_imm32 (ins->inst_offset)) {
3282                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3283                                 temp->inst_c0 = ins->inst_offset;
3284                                 temp->dreg = mono_alloc_ireg (cfg);
3285                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3286                                 ins->inst_indexreg = temp->dreg;
3287                         }
3288 #endif
3289                         break;
3290 #ifndef __mono_ilp32__
3291                 case OP_STORE_MEMBASE_IMM:
3292 #endif
3293                 case OP_STOREI8_MEMBASE_IMM:
3294                         if (!amd64_use_imm32 (ins->inst_imm)) {
3295                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3296                                 temp->inst_c0 = ins->inst_imm;
3297                                 temp->dreg = mono_alloc_ireg (cfg);
3298                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3299                                 ins->sreg1 = temp->dreg;
3300                         }
3301                         break;
3302 #ifdef MONO_ARCH_SIMD_INTRINSICS
3303                 case OP_EXPAND_I1: {
3304                                 int temp_reg1 = mono_alloc_ireg (cfg);
3305                                 int temp_reg2 = mono_alloc_ireg (cfg);
3306                                 int original_reg = ins->sreg1;
3307
3308                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3309                                 temp->sreg1 = original_reg;
3310                                 temp->dreg = temp_reg1;
3311
3312                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3313                                 temp->sreg1 = temp_reg1;
3314                                 temp->dreg = temp_reg2;
3315                                 temp->inst_imm = 8;
3316
3317                                 NEW_INS (cfg, ins, temp, OP_LOR);
3318                                 temp->sreg1 = temp->dreg = temp_reg2;
3319                                 temp->sreg2 = temp_reg1;
3320
3321                                 ins->opcode = OP_EXPAND_I2;
3322                                 ins->sreg1 = temp_reg2;
3323                         }
3324                         break;
3325 #endif
3326                 default:
3327                         break;
3328                 }
3329         }
3330
3331         bb->max_vreg = cfg->next_vreg;
3332 }
3333
3334 static const int
3335 branch_cc_table [] = {
3336         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3337         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3338         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3339 };
3340
3341 /* Maps CMP_... constants to X86_CC_... constants */
3342 static const int
3343 cc_table [] = {
3344         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3345         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3346 };
3347
3348 static const int
3349 cc_signed_table [] = {
3350         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3351         FALSE, FALSE, FALSE, FALSE
3352 };
3353
3354 /*#include "cprop.c"*/
3355
3356 static unsigned char*
3357 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3358 {
3359         if (size == 8)
3360                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3361         else
3362                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3363
3364         if (size == 1)
3365                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3366         else if (size == 2)
3367                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3368         return code;
3369 }
3370
3371 static unsigned char*
3372 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3373 {
3374         int sreg = tree->sreg1;
3375         int need_touch = FALSE;
3376
3377 #if defined(TARGET_WIN32)
3378         need_touch = TRUE;
3379 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3380         if (!tree->flags & MONO_INST_INIT)
3381                 need_touch = TRUE;
3382 #endif
3383
3384         if (need_touch) {
3385                 guint8* br[5];
3386
3387                 /*
3388                  * Under Windows:
3389                  * If requested stack size is larger than one page,
3390                  * perform stack-touch operation
3391                  */
3392                 /*
3393                  * Generate stack probe code.
3394                  * Under Windows, it is necessary to allocate one page at a time,
3395                  * "touching" stack after each successful sub-allocation. This is
3396                  * because of the way stack growth is implemented - there is a
3397                  * guard page before the lowest stack page that is currently commited.
3398                  * Stack normally grows sequentially so OS traps access to the
3399                  * guard page and commits more pages when needed.
3400                  */
3401                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3402                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3403
3404                 br[2] = code; /* loop */
3405                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3406                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3407                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3408                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3409                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3410                 amd64_patch (br[3], br[2]);
3411                 amd64_test_reg_reg (code, sreg, sreg);
3412                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3413                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3414
3415                 br[1] = code; x86_jump8 (code, 0);
3416
3417                 amd64_patch (br[0], code);
3418                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3419                 amd64_patch (br[1], code);
3420                 amd64_patch (br[4], code);
3421         }
3422         else
3423                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3424
3425         if (tree->flags & MONO_INST_INIT) {
3426                 int offset = 0;
3427                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3428                         amd64_push_reg (code, AMD64_RAX);
3429                         offset += 8;
3430                 }
3431                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3432                         amd64_push_reg (code, AMD64_RCX);
3433                         offset += 8;
3434                 }
3435                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3436                         amd64_push_reg (code, AMD64_RDI);
3437                         offset += 8;
3438                 }
3439
3440                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3441                 if (sreg != AMD64_RCX)
3442                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3443                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3444
3445                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3446                 if (cfg->param_area)
3447                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3448                 amd64_cld (code);
3449 #if defined(__default_codegen__)
3450                 amd64_prefix (code, X86_REP_PREFIX);
3451                 amd64_stosl (code);
3452 #elif defined(__native_client_codegen__)
3453                 /* NaCl stos pseudo-instruction */
3454                 amd64_codegen_pre(code);
3455                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3456                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3457                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3458                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3459                 amd64_prefix (code, X86_REP_PREFIX);
3460                 amd64_stosl (code);
3461                 amd64_codegen_post(code);
3462 #endif /* __native_client_codegen__ */
3463
3464                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3465                         amd64_pop_reg (code, AMD64_RDI);
3466                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3467                         amd64_pop_reg (code, AMD64_RCX);
3468                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3469                         amd64_pop_reg (code, AMD64_RAX);
3470         }
3471         return code;
3472 }
3473
3474 static guint8*
3475 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3476 {
3477         CallInfo *cinfo;
3478         guint32 quad;
3479
3480         /* Move return value to the target register */
3481         /* FIXME: do this in the local reg allocator */
3482         switch (ins->opcode) {
3483         case OP_CALL:
3484         case OP_CALL_REG:
3485         case OP_CALL_MEMBASE:
3486         case OP_LCALL:
3487         case OP_LCALL_REG:
3488         case OP_LCALL_MEMBASE:
3489                 g_assert (ins->dreg == AMD64_RAX);
3490                 break;
3491         case OP_FCALL:
3492         case OP_FCALL_REG:
3493         case OP_FCALL_MEMBASE: {
3494                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3495                 if (rtype->type == MONO_TYPE_R4) {
3496                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3497                 }
3498                 else {
3499                         if (ins->dreg != AMD64_XMM0)
3500                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3501                 }
3502                 break;
3503         }
3504         case OP_RCALL:
3505         case OP_RCALL_REG:
3506         case OP_RCALL_MEMBASE:
3507                 if (ins->dreg != AMD64_XMM0)
3508                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3509                 break;
3510         case OP_VCALL:
3511         case OP_VCALL_REG:
3512         case OP_VCALL_MEMBASE:
3513         case OP_VCALL2:
3514         case OP_VCALL2_REG:
3515         case OP_VCALL2_MEMBASE:
3516                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3517                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3518                         MonoInst *loc = cfg->arch.vret_addr_loc;
3519
3520                         /* Load the destination address */
3521                         g_assert (loc->opcode == OP_REGOFFSET);
3522                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3523
3524                         for (quad = 0; quad < 2; quad ++) {
3525                                 switch (cinfo->ret.pair_storage [quad]) {
3526                                 case ArgInIReg:
3527                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3528                                         break;
3529                                 case ArgInFloatSSEReg:
3530                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3531                                         break;
3532                                 case ArgInDoubleSSEReg:
3533                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3534                                         break;
3535                                 case ArgNone:
3536                                         break;
3537                                 default:
3538                                         NOT_IMPLEMENTED;
3539                                 }
3540                         }
3541                 }
3542                 break;
3543         }
3544
3545         return code;
3546 }
3547
3548 #endif /* DISABLE_JIT */
3549
3550 #ifdef __APPLE__
3551 static int tls_gs_offset;
3552 #endif
3553
3554 gboolean
3555 mono_amd64_have_tls_get (void)
3556 {
3557 #ifdef TARGET_MACH
3558         static gboolean have_tls_get = FALSE;
3559         static gboolean inited = FALSE;
3560
3561         if (inited)
3562                 return have_tls_get;
3563
3564 #if MONO_HAVE_FAST_TLS
3565         guint8 *ins = (guint8*)pthread_getspecific;
3566
3567         /*
3568          * We're looking for these two instructions:
3569          *
3570          * mov    %gs:[offset](,%rdi,8),%rax
3571          * retq
3572          */
3573         have_tls_get = ins [0] == 0x65 &&
3574                        ins [1] == 0x48 &&
3575                        ins [2] == 0x8b &&
3576                        ins [3] == 0x04 &&
3577                        ins [4] == 0xfd &&
3578                        ins [6] == 0x00 &&
3579                        ins [7] == 0x00 &&
3580                        ins [8] == 0x00 &&
3581                        ins [9] == 0xc3;
3582
3583         tls_gs_offset = ins[5];
3584 #endif
3585
3586         inited = TRUE;
3587
3588         return have_tls_get;
3589 #elif defined(TARGET_ANDROID)
3590         return FALSE;
3591 #else
3592         return TRUE;
3593 #endif
3594 }
3595
3596 int
3597 mono_amd64_get_tls_gs_offset (void)
3598 {
3599 #ifdef TARGET_OSX
3600         return tls_gs_offset;
3601 #else
3602         g_assert_not_reached ();
3603         return -1;
3604 #endif
3605 }
3606
3607 /*
3608  * mono_amd64_emit_tls_get:
3609  * @code: buffer to store code to
3610  * @dreg: hard register where to place the result
3611  * @tls_offset: offset info
3612  *
3613  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3614  * the dreg register the item in the thread local storage identified
3615  * by tls_offset.
3616  *
3617  * Returns: a pointer to the end of the stored code
3618  */
3619 guint8*
3620 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3621 {
3622 #ifdef TARGET_WIN32
3623         if (tls_offset < 64) {
3624                 x86_prefix (code, X86_GS_PREFIX);
3625                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3626         } else {
3627                 guint8 *buf [16];
3628
3629                 g_assert (tls_offset < 0x440);
3630                 /* Load TEB->TlsExpansionSlots */
3631                 x86_prefix (code, X86_GS_PREFIX);
3632                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3633                 amd64_test_reg_reg (code, dreg, dreg);
3634                 buf [0] = code;
3635                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3636                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3637                 amd64_patch (buf [0], code);
3638         }
3639 #elif defined(__APPLE__)
3640         x86_prefix (code, X86_GS_PREFIX);
3641         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3642 #else
3643         if (optimize_for_xen) {
3644                 x86_prefix (code, X86_FS_PREFIX);
3645                 amd64_mov_reg_mem (code, dreg, 0, 8);
3646                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3647         } else {
3648                 x86_prefix (code, X86_FS_PREFIX);
3649                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3650         }
3651 #endif
3652         return code;
3653 }
3654
3655 static guint8*
3656 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3657 {
3658         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3659 #ifdef TARGET_OSX
3660         if (dreg != offset_reg)
3661                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3662         amd64_prefix (code, X86_GS_PREFIX);
3663         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3664 #elif defined(__linux__)
3665         int tmpreg = -1;
3666
3667         if (dreg == offset_reg) {
3668                 /* Use a temporary reg by saving it to the redzone */
3669                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3670                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3671                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3672                 offset_reg = tmpreg;
3673         }
3674         x86_prefix (code, X86_FS_PREFIX);
3675         amd64_mov_reg_mem (code, dreg, 0, 8);
3676         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3677         if (tmpreg != -1)
3678                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3679 #else
3680         g_assert_not_reached ();
3681 #endif
3682         return code;
3683 }
3684
3685 static guint8*
3686 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3687 {
3688 #ifdef TARGET_WIN32
3689         g_assert_not_reached ();
3690 #elif defined(__APPLE__)
3691         x86_prefix (code, X86_GS_PREFIX);
3692         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3693 #else
3694         g_assert (!optimize_for_xen);
3695         x86_prefix (code, X86_FS_PREFIX);
3696         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3697 #endif
3698         return code;
3699 }
3700
3701 static guint8*
3702 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3703 {
3704         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3705 #ifdef TARGET_WIN32
3706         g_assert_not_reached ();
3707 #elif defined(__APPLE__)
3708         x86_prefix (code, X86_GS_PREFIX);
3709         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3710 #else
3711         x86_prefix (code, X86_FS_PREFIX);
3712         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3713 #endif
3714         return code;
3715 }
3716
3717  /*
3718  * mono_arch_translate_tls_offset:
3719  *
3720  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3721  */
3722 int
3723 mono_arch_translate_tls_offset (int offset)
3724 {
3725 #ifdef __APPLE__
3726         return tls_gs_offset + (offset * 8);
3727 #else
3728         return offset;
3729 #endif
3730 }
3731
3732 /*
3733  * emit_setup_lmf:
3734  *
3735  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3736  */
3737 static guint8*
3738 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3739 {
3740         /*
3741          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3742          */
3743         /*
3744          * sp is saved right before calls but we need to save it here too so
3745          * async stack walks would work.
3746          */
3747         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3748         /* Save rbp */
3749         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3750         if (cfg->arch.omit_fp && cfa_offset != -1)
3751                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3752
3753         /* These can't contain refs */
3754         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3755         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3756         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3757         /* These are handled automatically by the stack marking code */
3758         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3759
3760         return code;
3761 }
3762
3763 #define REAL_PRINT_REG(text,reg) \
3764 mono_assert (reg >= 0); \
3765 amd64_push_reg (code, AMD64_RAX); \
3766 amd64_push_reg (code, AMD64_RDX); \
3767 amd64_push_reg (code, AMD64_RCX); \
3768 amd64_push_reg (code, reg); \
3769 amd64_push_imm (code, reg); \
3770 amd64_push_imm (code, text " %d %p\n"); \
3771 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3772 amd64_call_reg (code, AMD64_RAX); \
3773 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3774 amd64_pop_reg (code, AMD64_RCX); \
3775 amd64_pop_reg (code, AMD64_RDX); \
3776 amd64_pop_reg (code, AMD64_RAX);
3777
3778 /* benchmark and set based on cpu */
3779 #define LOOP_ALIGNMENT 8
3780 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3781
3782 #ifndef DISABLE_JIT
3783 void
3784 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3785 {
3786         MonoInst *ins;
3787         MonoCallInst *call;
3788         guint offset;
3789         guint8 *code = cfg->native_code + cfg->code_len;
3790         int max_len;
3791
3792         /* Fix max_offset estimate for each successor bb */
3793         if (cfg->opt & MONO_OPT_BRANCH) {
3794                 int current_offset = cfg->code_len;
3795                 MonoBasicBlock *current_bb;
3796                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3797                         current_bb->max_offset = current_offset;
3798                         current_offset += current_bb->max_length;
3799                 }
3800         }
3801
3802         if (cfg->opt & MONO_OPT_LOOP) {
3803                 int pad, align = LOOP_ALIGNMENT;
3804                 /* set alignment depending on cpu */
3805                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3806                         pad = align - pad;
3807                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3808                         amd64_padding (code, pad);
3809                         cfg->code_len += pad;
3810                         bb->native_offset = cfg->code_len;
3811                 }
3812         }
3813
3814 #if defined(__native_client_codegen__)
3815         /* For Native Client, all indirect call/jump targets must be */
3816         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3817         /* indirectly as well.                                       */
3818         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3819                                       (bb->flags & BB_EXCEPTION_HANDLER);
3820
3821         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3822                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3823                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3824                 cfg->code_len += pad;
3825                 bb->native_offset = cfg->code_len;
3826         }
3827 #endif  /*__native_client_codegen__*/
3828
3829         if (cfg->verbose_level > 2)
3830                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3831
3832         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3833                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3834                 g_assert (!cfg->compile_aot);
3835
3836                 cov->data [bb->dfn].cil_code = bb->cil_code;
3837                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3838                 /* this is not thread save, but good enough */
3839                 amd64_inc_membase (code, AMD64_R11, 0);
3840         }
3841
3842         offset = code - cfg->native_code;
3843
3844         mono_debug_open_block (cfg, bb, offset);
3845
3846     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3847                 x86_breakpoint (code);
3848
3849         MONO_BB_FOR_EACH_INS (bb, ins) {
3850                 offset = code - cfg->native_code;
3851
3852                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3853
3854 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3855
3856                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3857                         cfg->code_size *= 2;
3858                         cfg->native_code = mono_realloc_native_code(cfg);
3859                         code = cfg->native_code + offset;
3860                         cfg->stat_code_reallocs++;
3861                 }
3862
3863                 if (cfg->debug_info)
3864                         mono_debug_record_line_number (cfg, ins, offset);
3865
3866                 switch (ins->opcode) {
3867                 case OP_BIGMUL:
3868                         amd64_mul_reg (code, ins->sreg2, TRUE);
3869                         break;
3870                 case OP_BIGMUL_UN:
3871                         amd64_mul_reg (code, ins->sreg2, FALSE);
3872                         break;
3873                 case OP_X86_SETEQ_MEMBASE:
3874                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3875                         break;
3876                 case OP_STOREI1_MEMBASE_IMM:
3877                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3878                         break;
3879                 case OP_STOREI2_MEMBASE_IMM:
3880                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3881                         break;
3882                 case OP_STOREI4_MEMBASE_IMM:
3883                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3884                         break;
3885                 case OP_STOREI1_MEMBASE_REG:
3886                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3887                         break;
3888                 case OP_STOREI2_MEMBASE_REG:
3889                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3890                         break;
3891                 /* In AMD64 NaCl, pointers are 4 bytes, */
3892                 /*  so STORE_* != STOREI8_*. Likewise below. */
3893                 case OP_STORE_MEMBASE_REG:
3894                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3895                         break;
3896                 case OP_STOREI8_MEMBASE_REG:
3897                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3898                         break;
3899                 case OP_STOREI4_MEMBASE_REG:
3900                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3901                         break;
3902                 case OP_STORE_MEMBASE_IMM:
3903 #ifndef __native_client_codegen__
3904                         /* In NaCl, this could be a PCONST type, which could */
3905                         /* mean a pointer type was copied directly into the  */
3906                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3907                         /* the value would be 0x00000000FFFFFFFF which is    */
3908                         /* not proper for an imm32 unless you cast it.       */
3909                         g_assert (amd64_is_imm32 (ins->inst_imm));
3910 #endif
3911                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3912                         break;
3913                 case OP_STOREI8_MEMBASE_IMM:
3914                         g_assert (amd64_is_imm32 (ins->inst_imm));
3915                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3916                         break;
3917                 case OP_LOAD_MEM:
3918 #ifdef __mono_ilp32__
3919                         /* In ILP32, pointers are 4 bytes, so separate these */
3920                         /* cases, use literal 8 below where we really want 8 */
3921                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3922                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3923                         break;
3924 #endif
3925                 case OP_LOADI8_MEM:
3926                         // FIXME: Decompose this earlier
3927                         if (amd64_use_imm32 (ins->inst_imm))
3928                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3929                         else {
3930                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3931                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3932                         }
3933                         break;
3934                 case OP_LOADI4_MEM:
3935                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3936                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3937                         break;
3938                 case OP_LOADU4_MEM:
3939                         // FIXME: Decompose this earlier
3940                         if (amd64_use_imm32 (ins->inst_imm))
3941                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3942                         else {
3943                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3944                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3945                         }
3946                         break;
3947                 case OP_LOADU1_MEM:
3948                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3949                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3950                         break;
3951                 case OP_LOADU2_MEM:
3952                         /* For NaCl, pointers are 4 bytes, so separate these */
3953                         /* cases, use literal 8 below where we really want 8 */
3954                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3955                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3956                         break;
3957                 case OP_LOAD_MEMBASE:
3958                         g_assert (amd64_is_imm32 (ins->inst_offset));
3959                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3960                         break;
3961                 case OP_LOADI8_MEMBASE:
3962                         /* Use literal 8 instead of sizeof pointer or */
3963                         /* register, we really want 8 for this opcode */
3964                         g_assert (amd64_is_imm32 (ins->inst_offset));
3965                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3966                         break;
3967                 case OP_LOADI4_MEMBASE:
3968                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3969                         break;
3970                 case OP_LOADU4_MEMBASE:
3971                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3972                         break;
3973                 case OP_LOADU1_MEMBASE:
3974                         /* The cpu zero extends the result into 64 bits */
3975                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3976                         break;
3977                 case OP_LOADI1_MEMBASE:
3978                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3979                         break;
3980                 case OP_LOADU2_MEMBASE:
3981                         /* The cpu zero extends the result into 64 bits */
3982                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3983                         break;
3984                 case OP_LOADI2_MEMBASE:
3985                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3986                         break;
3987                 case OP_AMD64_LOADI8_MEMINDEX:
3988                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3989                         break;
3990                 case OP_LCONV_TO_I1:
3991                 case OP_ICONV_TO_I1:
3992                 case OP_SEXT_I1:
3993                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3994                         break;
3995                 case OP_LCONV_TO_I2:
3996                 case OP_ICONV_TO_I2:
3997                 case OP_SEXT_I2:
3998                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3999                         break;
4000                 case OP_LCONV_TO_U1:
4001                 case OP_ICONV_TO_U1:
4002                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4003                         break;
4004                 case OP_LCONV_TO_U2:
4005                 case OP_ICONV_TO_U2:
4006                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4007                         break;
4008                 case OP_ZEXT_I4:
4009                         /* Clean out the upper word */
4010                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4011                         break;
4012                 case OP_SEXT_I4:
4013                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4014                         break;
4015                 case OP_COMPARE:
4016                 case OP_LCOMPARE:
4017                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4018                         break;
4019                 case OP_COMPARE_IMM:
4020 #if defined(__mono_ilp32__)
4021                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4022                         g_assert (amd64_is_imm32 (ins->inst_imm));
4023                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4024                         break;
4025 #endif
4026                 case OP_LCOMPARE_IMM:
4027                         g_assert (amd64_is_imm32 (ins->inst_imm));
4028                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4029                         break;
4030                 case OP_X86_COMPARE_REG_MEMBASE:
4031                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4032                         break;
4033                 case OP_X86_TEST_NULL:
4034                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4035                         break;
4036                 case OP_AMD64_TEST_NULL:
4037                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4038                         break;
4039
4040                 case OP_X86_ADD_REG_MEMBASE:
4041                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4042                         break;
4043                 case OP_X86_SUB_REG_MEMBASE:
4044                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4045                         break;
4046                 case OP_X86_AND_REG_MEMBASE:
4047                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4048                         break;
4049                 case OP_X86_OR_REG_MEMBASE:
4050                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4051                         break;
4052                 case OP_X86_XOR_REG_MEMBASE:
4053                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4054                         break;
4055
4056                 case OP_X86_ADD_MEMBASE_IMM:
4057                         /* FIXME: Make a 64 version too */
4058                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4059                         break;
4060                 case OP_X86_SUB_MEMBASE_IMM:
4061                         g_assert (amd64_is_imm32 (ins->inst_imm));
4062                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4063                         break;
4064                 case OP_X86_AND_MEMBASE_IMM:
4065                         g_assert (amd64_is_imm32 (ins->inst_imm));
4066                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4067                         break;
4068                 case OP_X86_OR_MEMBASE_IMM:
4069                         g_assert (amd64_is_imm32 (ins->inst_imm));
4070                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4071                         break;
4072                 case OP_X86_XOR_MEMBASE_IMM:
4073                         g_assert (amd64_is_imm32 (ins->inst_imm));
4074                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4075                         break;
4076                 case OP_X86_ADD_MEMBASE_REG:
4077                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4078                         break;
4079                 case OP_X86_SUB_MEMBASE_REG:
4080                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4081                         break;
4082                 case OP_X86_AND_MEMBASE_REG:
4083                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4084                         break;
4085                 case OP_X86_OR_MEMBASE_REG:
4086                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4087                         break;
4088                 case OP_X86_XOR_MEMBASE_REG:
4089                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4090                         break;
4091                 case OP_X86_INC_MEMBASE:
4092                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4093                         break;
4094                 case OP_X86_INC_REG:
4095                         amd64_inc_reg_size (code, ins->dreg, 4);
4096                         break;
4097                 case OP_X86_DEC_MEMBASE:
4098                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4099                         break;
4100                 case OP_X86_DEC_REG:
4101                         amd64_dec_reg_size (code, ins->dreg, 4);
4102                         break;
4103                 case OP_X86_MUL_REG_MEMBASE:
4104                 case OP_X86_MUL_MEMBASE_REG:
4105                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4106                         break;
4107                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4108                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4109                         break;
4110                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4111                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4112                         break;
4113                 case OP_AMD64_COMPARE_MEMBASE_REG:
4114                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4115                         break;
4116                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4117                         g_assert (amd64_is_imm32 (ins->inst_imm));
4118                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4119                         break;
4120                 case OP_X86_COMPARE_MEMBASE8_IMM:
4121                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4122                         break;
4123                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4124                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4125                         break;
4126                 case OP_AMD64_COMPARE_REG_MEMBASE:
4127                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4128                         break;
4129
4130                 case OP_AMD64_ADD_REG_MEMBASE:
4131                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4132                         break;
4133                 case OP_AMD64_SUB_REG_MEMBASE:
4134                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4135                         break;
4136                 case OP_AMD64_AND_REG_MEMBASE:
4137                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4138                         break;
4139                 case OP_AMD64_OR_REG_MEMBASE:
4140                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4141                         break;
4142                 case OP_AMD64_XOR_REG_MEMBASE:
4143                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4144                         break;
4145
4146                 case OP_AMD64_ADD_MEMBASE_REG:
4147                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4148                         break;
4149                 case OP_AMD64_SUB_MEMBASE_REG:
4150                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4151                         break;
4152                 case OP_AMD64_AND_MEMBASE_REG:
4153                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4154                         break;
4155                 case OP_AMD64_OR_MEMBASE_REG:
4156                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4157                         break;
4158                 case OP_AMD64_XOR_MEMBASE_REG:
4159                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4160                         break;
4161
4162                 case OP_AMD64_ADD_MEMBASE_IMM:
4163                         g_assert (amd64_is_imm32 (ins->inst_imm));
4164                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4165                         break;
4166                 case OP_AMD64_SUB_MEMBASE_IMM:
4167                         g_assert (amd64_is_imm32 (ins->inst_imm));
4168                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4169                         break;
4170                 case OP_AMD64_AND_MEMBASE_IMM:
4171                         g_assert (amd64_is_imm32 (ins->inst_imm));
4172                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4173                         break;
4174                 case OP_AMD64_OR_MEMBASE_IMM:
4175                         g_assert (amd64_is_imm32 (ins->inst_imm));
4176                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4177                         break;
4178                 case OP_AMD64_XOR_MEMBASE_IMM:
4179                         g_assert (amd64_is_imm32 (ins->inst_imm));
4180                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4181                         break;
4182
4183                 case OP_BREAK:
4184                         amd64_breakpoint (code);
4185                         break;
4186                 case OP_RELAXED_NOP:
4187                         x86_prefix (code, X86_REP_PREFIX);
4188                         x86_nop (code);
4189                         break;
4190                 case OP_HARD_NOP:
4191                         x86_nop (code);
4192                         break;
4193                 case OP_NOP:
4194                 case OP_DUMMY_USE:
4195                 case OP_DUMMY_STORE:
4196                 case OP_DUMMY_ICONST:
4197                 case OP_DUMMY_R8CONST:
4198                 case OP_NOT_REACHED:
4199                 case OP_NOT_NULL:
4200                         break;
4201                 case OP_IL_SEQ_POINT:
4202                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4203                         break;
4204                 case OP_SEQ_POINT: {
4205                         int i;
4206
4207                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4208                                 if (cfg->compile_aot) {
4209                                         MonoInst *var = cfg->arch.ss_tramp_var;
4210                                         guint8 *label;
4211
4212                                         /* Load ss_tramp_var */
4213                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4214                                         /* Load the trampoline address */
4215                                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4216                                         /* Call it if it is non-null */
4217                                         amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4218                                         label = code;
4219                                         amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4220                                         amd64_call_reg (code, AMD64_R11);
4221                                         amd64_patch (label, code);
4222                                 } else {
4223                                         /*
4224                                          * Read from the single stepping trigger page. This will cause a
4225                                          * SIGSEGV when single stepping is enabled.
4226                                          * We do this _before_ the breakpoint, so single stepping after
4227                                          * a breakpoint is hit will step to the next IL offset.
4228                                          */
4229                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
4230
4231                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4232                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4233                                 }
4234                         }
4235
4236                         /*
4237                          * This is the address which is saved in seq points,
4238                          */
4239                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4240
4241                         if (cfg->compile_aot) {
4242                                 guint32 offset = code - cfg->native_code;
4243                                 guint32 val;
4244                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4245                                 guint8 *label;
4246
4247                                 /* Load info var */
4248                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4249                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4250                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4251                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4252                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4253                                 label = code;
4254                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4255                                 /* Call the trampoline */
4256                                 amd64_call_reg (code, AMD64_R11);
4257                                 amd64_patch (label, code);
4258                         } else {
4259                                 /*
4260                                  * A placeholder for a possible breakpoint inserted by
4261                                  * mono_arch_set_breakpoint ().
4262                                  */
4263                                 for (i = 0; i < breakpoint_size; ++i)
4264                                         x86_nop (code);
4265                         }
4266                         /*
4267                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4268                          * to another IL offset.
4269                          */
4270                         x86_nop (code);
4271                         break;
4272                 }
4273                 case OP_ADDCC:
4274                 case OP_LADDCC:
4275                 case OP_LADD:
4276                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4277                         break;
4278                 case OP_ADC:
4279                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4280                         break;
4281                 case OP_ADD_IMM:
4282                 case OP_LADD_IMM:
4283                         g_assert (amd64_is_imm32 (ins->inst_imm));
4284                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4285                         break;
4286                 case OP_ADC_IMM:
4287                         g_assert (amd64_is_imm32 (ins->inst_imm));
4288                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4289                         break;
4290                 case OP_SUBCC:
4291                 case OP_LSUBCC:
4292                 case OP_LSUB:
4293                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4294                         break;
4295                 case OP_SBB:
4296                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4297                         break;
4298                 case OP_SUB_IMM:
4299                 case OP_LSUB_IMM:
4300                         g_assert (amd64_is_imm32 (ins->inst_imm));
4301                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4302                         break;
4303                 case OP_SBB_IMM:
4304                         g_assert (amd64_is_imm32 (ins->inst_imm));
4305                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4306                         break;
4307                 case OP_LAND:
4308                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4309                         break;
4310                 case OP_AND_IMM:
4311                 case OP_LAND_IMM:
4312                         g_assert (amd64_is_imm32 (ins->inst_imm));
4313                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4314                         break;
4315                 case OP_LMUL:
4316                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4317                         break;
4318                 case OP_MUL_IMM:
4319                 case OP_LMUL_IMM:
4320                 case OP_IMUL_IMM: {
4321                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4322
4323                         switch (ins->inst_imm) {
4324                         case 2:
4325                                 /* MOV r1, r2 */
4326                                 /* ADD r1, r1 */
4327                                 if (ins->dreg != ins->sreg1)
4328                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4329                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4330                                 break;
4331                         case 3:
4332                                 /* LEA r1, [r2 + r2*2] */
4333                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4334                                 break;
4335                         case 5:
4336                                 /* LEA r1, [r2 + r2*4] */
4337                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4338                                 break;
4339                         case 6:
4340                                 /* LEA r1, [r2 + r2*2] */
4341                                 /* ADD r1, r1          */
4342                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4343                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4344                                 break;
4345                         case 9:
4346                                 /* LEA r1, [r2 + r2*8] */
4347                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4348                                 break;
4349                         case 10:
4350                                 /* LEA r1, [r2 + r2*4] */
4351                                 /* ADD r1, r1          */
4352                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4353                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4354                                 break;
4355                         case 12:
4356                                 /* LEA r1, [r2 + r2*2] */
4357                                 /* SHL r1, 2           */
4358                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4359                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4360                                 break;
4361                         case 25:
4362                                 /* LEA r1, [r2 + r2*4] */
4363                                 /* LEA r1, [r1 + r1*4] */
4364                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4365                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4366                                 break;
4367                         case 100:
4368                                 /* LEA r1, [r2 + r2*4] */
4369                                 /* SHL r1, 2           */
4370                                 /* LEA r1, [r1 + r1*4] */
4371                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4372                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4373                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4374                                 break;
4375                         default:
4376                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4377                                 break;
4378                         }
4379                         break;
4380                 }
4381                 case OP_LDIV:
4382                 case OP_LREM:
4383 #if defined( __native_client_codegen__ )
4384                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4385                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4386 #endif
4387                         /* Regalloc magic makes the div/rem cases the same */
4388                         if (ins->sreg2 == AMD64_RDX) {
4389                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4390                                 amd64_cdq (code);
4391                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4392                         } else {
4393                                 amd64_cdq (code);
4394                                 amd64_div_reg (code, ins->sreg2, TRUE);
4395                         }
4396                         break;
4397                 case OP_LDIV_UN:
4398                 case OP_LREM_UN:
4399 #if defined( __native_client_codegen__ )
4400                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4401                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4402 #endif
4403                         if (ins->sreg2 == AMD64_RDX) {
4404                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4405                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4406                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4407                         } else {
4408                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4409                                 amd64_div_reg (code, ins->sreg2, FALSE);
4410                         }
4411                         break;
4412                 case OP_IDIV:
4413                 case OP_IREM:
4414 #if defined( __native_client_codegen__ )
4415                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4416                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4417 #endif
4418                         if (ins->sreg2 == AMD64_RDX) {
4419                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4420                                 amd64_cdq_size (code, 4);
4421                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4422                         } else {
4423                                 amd64_cdq_size (code, 4);
4424                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4425                         }
4426                         break;
4427                 case OP_IDIV_UN:
4428                 case OP_IREM_UN:
4429 #if defined( __native_client_codegen__ )
4430                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4431                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4432 #endif
4433                         if (ins->sreg2 == AMD64_RDX) {
4434                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4435                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4436                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4437                         } else {
4438                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4439                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4440                         }
4441                         break;
4442                 case OP_LMUL_OVF:
4443                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4444                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4445                         break;
4446                 case OP_LOR:
4447                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4448                         break;
4449                 case OP_OR_IMM:
4450                 case OP_LOR_IMM:
4451                         g_assert (amd64_is_imm32 (ins->inst_imm));
4452                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4453                         break;
4454                 case OP_LXOR:
4455                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4456                         break;
4457                 case OP_XOR_IMM:
4458                 case OP_LXOR_IMM:
4459                         g_assert (amd64_is_imm32 (ins->inst_imm));
4460                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4461                         break;
4462                 case OP_LSHL:
4463                         g_assert (ins->sreg2 == AMD64_RCX);
4464                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4465                         break;
4466                 case OP_LSHR:
4467                         g_assert (ins->sreg2 == AMD64_RCX);
4468                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4469                         break;
4470                 case OP_SHR_IMM:
4471                 case OP_LSHR_IMM:
4472                         g_assert (amd64_is_imm32 (ins->inst_imm));
4473                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4474                         break;
4475                 case OP_SHR_UN_IMM:
4476                         g_assert (amd64_is_imm32 (ins->inst_imm));
4477                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4478                         break;
4479                 case OP_LSHR_UN_IMM:
4480                         g_assert (amd64_is_imm32 (ins->inst_imm));
4481                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4482                         break;
4483                 case OP_LSHR_UN:
4484                         g_assert (ins->sreg2 == AMD64_RCX);
4485                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4486                         break;
4487                 case OP_SHL_IMM:
4488                 case OP_LSHL_IMM:
4489                         g_assert (amd64_is_imm32 (ins->inst_imm));
4490                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4491                         break;
4492
4493                 case OP_IADDCC:
4494                 case OP_IADD:
4495                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4496                         break;
4497                 case OP_IADC:
4498                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4499                         break;
4500                 case OP_IADD_IMM:
4501                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4502                         break;
4503                 case OP_IADC_IMM:
4504                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4505                         break;
4506                 case OP_ISUBCC:
4507                 case OP_ISUB:
4508                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4509                         break;
4510                 case OP_ISBB:
4511                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4512                         break;
4513                 case OP_ISUB_IMM:
4514                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4515                         break;
4516                 case OP_ISBB_IMM:
4517                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4518                         break;
4519                 case OP_IAND:
4520                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4521                         break;
4522                 case OP_IAND_IMM:
4523                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4524                         break;
4525                 case OP_IOR:
4526                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4527                         break;
4528                 case OP_IOR_IMM:
4529                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4530                         break;
4531                 case OP_IXOR:
4532                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4533                         break;
4534                 case OP_IXOR_IMM:
4535                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4536                         break;
4537                 case OP_INEG:
4538                         amd64_neg_reg_size (code, ins->sreg1, 4);
4539                         break;
4540                 case OP_INOT:
4541                         amd64_not_reg_size (code, ins->sreg1, 4);
4542                         break;
4543                 case OP_ISHL:
4544                         g_assert (ins->sreg2 == AMD64_RCX);
4545                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4546                         break;
4547                 case OP_ISHR:
4548                         g_assert (ins->sreg2 == AMD64_RCX);
4549                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4550                         break;
4551                 case OP_ISHR_IMM:
4552                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4553                         break;
4554                 case OP_ISHR_UN_IMM:
4555                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4556                         break;
4557                 case OP_ISHR_UN:
4558                         g_assert (ins->sreg2 == AMD64_RCX);
4559                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4560                         break;
4561                 case OP_ISHL_IMM:
4562                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4563                         break;
4564                 case OP_IMUL:
4565                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4566                         break;
4567                 case OP_IMUL_OVF:
4568                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4569                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4570                         break;
4571                 case OP_IMUL_OVF_UN:
4572                 case OP_LMUL_OVF_UN: {
4573                         /* the mul operation and the exception check should most likely be split */
4574                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4575                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4576                         /*g_assert (ins->sreg2 == X86_EAX);
4577                         g_assert (ins->dreg == X86_EAX);*/
4578                         if (ins->sreg2 == X86_EAX) {
4579                                 non_eax_reg = ins->sreg1;
4580                         } else if (ins->sreg1 == X86_EAX) {
4581                                 non_eax_reg = ins->sreg2;
4582                         } else {
4583                                 /* no need to save since we're going to store to it anyway */
4584                                 if (ins->dreg != X86_EAX) {
4585                                         saved_eax = TRUE;
4586                                         amd64_push_reg (code, X86_EAX);
4587                                 }
4588                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4589                                 non_eax_reg = ins->sreg2;
4590                         }
4591                         if (ins->dreg == X86_EDX) {
4592                                 if (!saved_eax) {
4593                                         saved_eax = TRUE;
4594                                         amd64_push_reg (code, X86_EAX);
4595                                 }
4596                         } else {
4597                                 saved_edx = TRUE;
4598                                 amd64_push_reg (code, X86_EDX);
4599                         }
4600                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4601                         /* save before the check since pop and mov don't change the flags */
4602                         if (ins->dreg != X86_EAX)
4603                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4604                         if (saved_edx)
4605                                 amd64_pop_reg (code, X86_EDX);
4606                         if (saved_eax)
4607                                 amd64_pop_reg (code, X86_EAX);
4608                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4609                         break;
4610                 }
4611                 case OP_ICOMPARE:
4612                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4613                         break;
4614                 case OP_ICOMPARE_IMM:
4615                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4616                         break;
4617                 case OP_IBEQ:
4618                 case OP_IBLT:
4619                 case OP_IBGT:
4620                 case OP_IBGE:
4621                 case OP_IBLE:
4622                 case OP_LBEQ:
4623                 case OP_LBLT:
4624                 case OP_LBGT:
4625                 case OP_LBGE:
4626                 case OP_LBLE:
4627                 case OP_IBNE_UN:
4628                 case OP_IBLT_UN:
4629                 case OP_IBGT_UN:
4630                 case OP_IBGE_UN:
4631                 case OP_IBLE_UN:
4632                 case OP_LBNE_UN:
4633                 case OP_LBLT_UN:
4634                 case OP_LBGT_UN:
4635                 case OP_LBGE_UN:
4636                 case OP_LBLE_UN:
4637                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4638                         break;
4639
4640                 case OP_CMOV_IEQ:
4641                 case OP_CMOV_IGE:
4642                 case OP_CMOV_IGT:
4643                 case OP_CMOV_ILE:
4644                 case OP_CMOV_ILT:
4645                 case OP_CMOV_INE_UN:
4646                 case OP_CMOV_IGE_UN:
4647                 case OP_CMOV_IGT_UN:
4648                 case OP_CMOV_ILE_UN:
4649                 case OP_CMOV_ILT_UN:
4650                 case OP_CMOV_LEQ:
4651                 case OP_CMOV_LGE:
4652                 case OP_CMOV_LGT:
4653                 case OP_CMOV_LLE:
4654                 case OP_CMOV_LLT:
4655                 case OP_CMOV_LNE_UN:
4656                 case OP_CMOV_LGE_UN:
4657                 case OP_CMOV_LGT_UN:
4658                 case OP_CMOV_LLE_UN:
4659                 case OP_CMOV_LLT_UN:
4660                         g_assert (ins->dreg == ins->sreg1);
4661                         /* This needs to operate on 64 bit values */
4662                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4663                         break;
4664
4665                 case OP_LNOT:
4666                         amd64_not_reg (code, ins->sreg1);
4667                         break;
4668                 case OP_LNEG:
4669                         amd64_neg_reg (code, ins->sreg1);
4670                         break;
4671
4672                 case OP_ICONST:
4673                 case OP_I8CONST:
4674                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4675                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4676                         else
4677                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4678                         break;
4679                 case OP_AOTCONST:
4680                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4681                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4682                         break;
4683                 case OP_JUMP_TABLE:
4684                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4685                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4686                         break;
4687                 case OP_MOVE:
4688                         if (ins->dreg != ins->sreg1)
4689                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4690                         break;
4691                 case OP_AMD64_SET_XMMREG_R4: {
4692                         if (cfg->r4fp) {
4693                                 if (ins->dreg != ins->sreg1)
4694                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4695                         } else {
4696                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4697                         }
4698                         break;
4699                 }
4700                 case OP_AMD64_SET_XMMREG_R8: {
4701                         if (ins->dreg != ins->sreg1)
4702                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4703                         break;
4704                 }
4705                 case OP_TAILCALL: {
4706                         MonoCallInst *call = (MonoCallInst*)ins;
4707                         int i, save_area_offset;
4708
4709                         g_assert (!cfg->method->save_lmf);
4710
4711                         /* Restore callee saved registers */
4712                         save_area_offset = cfg->arch.reg_save_area_offset;
4713                         for (i = 0; i < AMD64_NREG; ++i)
4714                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4715                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4716                                         save_area_offset += 8;
4717                                 }
4718
4719                         if (cfg->arch.omit_fp) {
4720                                 if (cfg->arch.stack_alloc_size)
4721                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4722                                 // FIXME:
4723                                 if (call->stack_usage)
4724                                         NOT_IMPLEMENTED;
4725                         } else {
4726                                 /* Copy arguments on the stack to our argument area */
4727                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4728                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4729                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4730                                 }
4731
4732                                 amd64_leave (code);
4733                         }
4734
4735                         offset = code - cfg->native_code;
4736                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4737                         if (cfg->compile_aot)
4738                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4739                         else
4740                                 amd64_set_reg_template (code, AMD64_R11);
4741                         amd64_jump_reg (code, AMD64_R11);
4742                         ins->flags |= MONO_INST_GC_CALLSITE;
4743                         ins->backend.pc_offset = code - cfg->native_code;
4744                         break;
4745                 }
4746                 case OP_CHECK_THIS:
4747                         /* ensure ins->sreg1 is not NULL */
4748                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4749                         break;
4750                 case OP_ARGLIST: {
4751                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4752                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4753                         break;
4754                 }
4755                 case OP_CALL:
4756                 case OP_FCALL:
4757                 case OP_RCALL:
4758                 case OP_LCALL:
4759                 case OP_VCALL:
4760                 case OP_VCALL2:
4761                 case OP_VOIDCALL:
4762                         call = (MonoCallInst*)ins;
4763                         /*
4764                          * The AMD64 ABI forces callers to know about varargs.
4765                          */
4766                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4767                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4768                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4769                                 /*
4770                                  * Since the unmanaged calling convention doesn't contain a
4771                                  * 'vararg' entry, we have to treat every pinvoke call as a
4772                                  * potential vararg call.
4773                                  */
4774                                 guint32 nregs, i;
4775                                 nregs = 0;
4776                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4777                                         if (call->used_fregs & (1 << i))
4778                                                 nregs ++;
4779                                 if (!nregs)
4780                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4781                                 else
4782                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4783                         }
4784
4785                         if (ins->flags & MONO_INST_HAS_METHOD)
4786                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4787                         else
4788                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4789                         ins->flags |= MONO_INST_GC_CALLSITE;
4790                         ins->backend.pc_offset = code - cfg->native_code;
4791                         code = emit_move_return_value (cfg, ins, code);
4792                         break;
4793                 case OP_FCALL_REG:
4794                 case OP_RCALL_REG:
4795                 case OP_LCALL_REG:
4796                 case OP_VCALL_REG:
4797                 case OP_VCALL2_REG:
4798                 case OP_VOIDCALL_REG:
4799                 case OP_CALL_REG:
4800                         call = (MonoCallInst*)ins;
4801
4802                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4803                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4804                                 ins->sreg1 = AMD64_R11;
4805                         }
4806
4807                         /*
4808                          * The AMD64 ABI forces callers to know about varargs.
4809                          */
4810                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4811                                 if (ins->sreg1 == AMD64_RAX) {
4812                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4813                                         ins->sreg1 = AMD64_R11;
4814                                 }
4815                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4816                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4817                                 /*
4818                                  * Since the unmanaged calling convention doesn't contain a
4819                                  * 'vararg' entry, we have to treat every pinvoke call as a
4820                                  * potential vararg call.
4821                                  */
4822                                 guint32 nregs, i;
4823                                 nregs = 0;
4824                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4825                                         if (call->used_fregs & (1 << i))
4826                                                 nregs ++;
4827                                 if (ins->sreg1 == AMD64_RAX) {
4828                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4829                                         ins->sreg1 = AMD64_R11;
4830                                 }
4831                                 if (!nregs)
4832                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4833                                 else
4834                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4835                         }
4836
4837                         amd64_call_reg (code, ins->sreg1);
4838                         ins->flags |= MONO_INST_GC_CALLSITE;
4839                         ins->backend.pc_offset = code - cfg->native_code;
4840                         code = emit_move_return_value (cfg, ins, code);
4841                         break;
4842                 case OP_FCALL_MEMBASE:
4843                 case OP_RCALL_MEMBASE:
4844                 case OP_LCALL_MEMBASE:
4845                 case OP_VCALL_MEMBASE:
4846                 case OP_VCALL2_MEMBASE:
4847                 case OP_VOIDCALL_MEMBASE:
4848                 case OP_CALL_MEMBASE:
4849                         call = (MonoCallInst*)ins;
4850
4851                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4852                         ins->flags |= MONO_INST_GC_CALLSITE;
4853                         ins->backend.pc_offset = code - cfg->native_code;
4854                         code = emit_move_return_value (cfg, ins, code);
4855                         break;
4856                 case OP_DYN_CALL: {
4857                         int i;
4858                         MonoInst *var = cfg->dyn_call_var;
4859
4860                         g_assert (var->opcode == OP_REGOFFSET);
4861
4862                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4863                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4864                         /* r10 = ftn */
4865                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4866
4867                         /* Save args buffer */
4868                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4869
4870                         /* Set argument registers */
4871                         for (i = 0; i < PARAM_REGS; ++i)
4872                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4873
4874                         /* Make the call */
4875                         amd64_call_reg (code, AMD64_R10);
4876
4877                         ins->flags |= MONO_INST_GC_CALLSITE;
4878                         ins->backend.pc_offset = code - cfg->native_code;
4879
4880                         /* Save result */
4881                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4882                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4883                         break;
4884                 }
4885                 case OP_AMD64_SAVE_SP_TO_LMF: {
4886                         MonoInst *lmf_var = cfg->lmf_var;
4887                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4888                         break;
4889                 }
4890                 case OP_X86_PUSH:
4891                         g_assert_not_reached ();
4892                         amd64_push_reg (code, ins->sreg1);
4893                         break;
4894                 case OP_X86_PUSH_IMM:
4895                         g_assert_not_reached ();
4896                         g_assert (amd64_is_imm32 (ins->inst_imm));
4897                         amd64_push_imm (code, ins->inst_imm);
4898                         break;
4899                 case OP_X86_PUSH_MEMBASE:
4900                         g_assert_not_reached ();
4901                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4902                         break;
4903                 case OP_X86_PUSH_OBJ: {
4904                         int size = ALIGN_TO (ins->inst_imm, 8);
4905
4906                         g_assert_not_reached ();
4907
4908                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4909                         amd64_push_reg (code, AMD64_RDI);
4910                         amd64_push_reg (code, AMD64_RSI);
4911                         amd64_push_reg (code, AMD64_RCX);
4912                         if (ins->inst_offset)
4913                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4914                         else
4915                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4916                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4917                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4918                         amd64_cld (code);
4919                         amd64_prefix (code, X86_REP_PREFIX);
4920                         amd64_movsd (code);
4921                         amd64_pop_reg (code, AMD64_RCX);
4922                         amd64_pop_reg (code, AMD64_RSI);
4923                         amd64_pop_reg (code, AMD64_RDI);
4924                         break;
4925                 }
4926                 case OP_GENERIC_CLASS_INIT: {
4927                         static int byte_offset = -1;
4928                         static guint8 bitmask;
4929                         guint8 *jump;
4930
4931                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4932
4933                         if (byte_offset < 0)
4934                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4935
4936                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4937                         jump = code;
4938                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4939
4940                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4941                         ins->flags |= MONO_INST_GC_CALLSITE;
4942                         ins->backend.pc_offset = code - cfg->native_code;
4943
4944                         x86_patch (jump, code);
4945                         break;
4946                 }
4947
4948                 case OP_X86_LEA:
4949                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4950                         break;
4951                 case OP_X86_LEA_MEMBASE:
4952                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4953                         break;
4954                 case OP_X86_XCHG:
4955                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4956                         break;
4957                 case OP_LOCALLOC:
4958                         /* keep alignment */
4959                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4960                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4961                         code = mono_emit_stack_alloc (cfg, code, ins);
4962                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4963                         if (cfg->param_area)
4964                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4965                         break;
4966                 case OP_LOCALLOC_IMM: {
4967                         guint32 size = ins->inst_imm;
4968                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4969
4970                         if (ins->flags & MONO_INST_INIT) {
4971                                 if (size < 64) {
4972                                         int i;
4973
4974                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4975                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4976
4977                                         for (i = 0; i < size; i += 8)
4978                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4979                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4980                                 } else {
4981                                         amd64_mov_reg_imm (code, ins->dreg, size);
4982                                         ins->sreg1 = ins->dreg;
4983
4984                                         code = mono_emit_stack_alloc (cfg, code, ins);
4985                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4986                                 }
4987                         } else {
4988                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4989                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4990                         }
4991                         if (cfg->param_area)
4992                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4993                         break;
4994                 }
4995                 case OP_THROW: {
4996                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4997                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4998                                              (gpointer)"mono_arch_throw_exception", FALSE);
4999                         ins->flags |= MONO_INST_GC_CALLSITE;
5000                         ins->backend.pc_offset = code - cfg->native_code;
5001                         break;
5002                 }
5003                 case OP_RETHROW: {
5004                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5005                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5006                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5007                         ins->flags |= MONO_INST_GC_CALLSITE;
5008                         ins->backend.pc_offset = code - cfg->native_code;
5009                         break;
5010                 }
5011                 case OP_CALL_HANDLER:
5012                         /* Align stack */
5013                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5014                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5015                         amd64_call_imm (code, 0);
5016                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5017                         /* Restore stack alignment */
5018                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5019                         break;
5020                 case OP_START_HANDLER: {
5021                         /* Even though we're saving RSP, use sizeof */
5022                         /* gpointer because spvar is of type IntPtr */
5023                         /* see: mono_create_spvar_for_region */
5024                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5025                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5026
5027                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5028                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5029                                 cfg->param_area) {
5030                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5031                         }
5032                         break;
5033                 }
5034                 case OP_ENDFINALLY: {
5035                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5036                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5037                         amd64_ret (code);
5038                         break;
5039                 }
5040                 case OP_ENDFILTER: {
5041                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5042                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5043                         /* The local allocator will put the result into RAX */
5044                         amd64_ret (code);
5045                         break;
5046                 }
5047                 case OP_GET_EX_OBJ:
5048                         if (ins->dreg != AMD64_RAX)
5049                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5050                         break;
5051                 case OP_LABEL:
5052                         ins->inst_c0 = code - cfg->native_code;
5053                         break;
5054                 case OP_BR:
5055                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5056                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5057                         //break;
5058                                 if (ins->inst_target_bb->native_offset) {
5059                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5060                                 } else {
5061                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5062                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5063                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5064                                                 x86_jump8 (code, 0);
5065                                         else
5066                                                 x86_jump32 (code, 0);
5067                         }
5068                         break;
5069                 case OP_BR_REG:
5070                         amd64_jump_reg (code, ins->sreg1);
5071                         break;
5072                 case OP_ICNEQ:
5073                 case OP_ICGE:
5074                 case OP_ICLE:
5075                 case OP_ICGE_UN:
5076                 case OP_ICLE_UN:
5077
5078                 case OP_CEQ:
5079                 case OP_LCEQ:
5080                 case OP_ICEQ:
5081                 case OP_CLT:
5082                 case OP_LCLT:
5083                 case OP_ICLT:
5084                 case OP_CGT:
5085                 case OP_ICGT:
5086                 case OP_LCGT:
5087                 case OP_CLT_UN:
5088                 case OP_LCLT_UN:
5089                 case OP_ICLT_UN:
5090                 case OP_CGT_UN:
5091                 case OP_LCGT_UN:
5092                 case OP_ICGT_UN:
5093                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5094                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5095                         break;
5096                 case OP_COND_EXC_EQ:
5097                 case OP_COND_EXC_NE_UN:
5098                 case OP_COND_EXC_LT:
5099                 case OP_COND_EXC_LT_UN:
5100                 case OP_COND_EXC_GT:
5101                 case OP_COND_EXC_GT_UN:
5102                 case OP_COND_EXC_GE:
5103                 case OP_COND_EXC_GE_UN:
5104                 case OP_COND_EXC_LE:
5105                 case OP_COND_EXC_LE_UN:
5106                 case OP_COND_EXC_IEQ:
5107                 case OP_COND_EXC_INE_UN:
5108                 case OP_COND_EXC_ILT:
5109                 case OP_COND_EXC_ILT_UN:
5110                 case OP_COND_EXC_IGT:
5111                 case OP_COND_EXC_IGT_UN:
5112                 case OP_COND_EXC_IGE:
5113                 case OP_COND_EXC_IGE_UN:
5114                 case OP_COND_EXC_ILE:
5115                 case OP_COND_EXC_ILE_UN:
5116                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5117                         break;
5118                 case OP_COND_EXC_OV:
5119                 case OP_COND_EXC_NO:
5120                 case OP_COND_EXC_C:
5121                 case OP_COND_EXC_NC:
5122                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5123                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5124                         break;
5125                 case OP_COND_EXC_IOV:
5126                 case OP_COND_EXC_INO:
5127                 case OP_COND_EXC_IC:
5128                 case OP_COND_EXC_INC:
5129                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5130                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5131                         break;
5132
5133                 /* floating point opcodes */
5134                 case OP_R8CONST: {
5135                         double d = *(double *)ins->inst_p0;
5136
5137                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5138                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5139                         }
5140                         else {
5141                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5142                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5143                         }
5144                         break;
5145                 }
5146                 case OP_R4CONST: {
5147                         float f = *(float *)ins->inst_p0;
5148
5149                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5150                                 if (cfg->r4fp)
5151                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5152                                 else
5153                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5154                         }
5155                         else {
5156                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5157                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5158                                 if (!cfg->r4fp)
5159                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5160                         }
5161                         break;
5162                 }
5163                 case OP_STORER8_MEMBASE_REG:
5164                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5165                         break;
5166                 case OP_LOADR8_MEMBASE:
5167                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5168                         break;
5169                 case OP_STORER4_MEMBASE_REG:
5170                         if (cfg->r4fp) {
5171                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5172                         } else {
5173                                 /* This requires a double->single conversion */
5174                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5175                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5176                         }
5177                         break;
5178                 case OP_LOADR4_MEMBASE:
5179                         if (cfg->r4fp) {
5180                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5181                         } else {
5182                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5183                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5184                         }
5185                         break;
5186                 case OP_ICONV_TO_R4:
5187                         if (cfg->r4fp) {
5188                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5189                         } else {
5190                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5191                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5192                         }
5193                         break;
5194                 case OP_ICONV_TO_R8:
5195                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5196                         break;
5197                 case OP_LCONV_TO_R4:
5198                         if (cfg->r4fp) {
5199                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5200                         } else {
5201                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5202                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5203                         }
5204                         break;
5205                 case OP_LCONV_TO_R8:
5206                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5207                         break;
5208                 case OP_FCONV_TO_R4:
5209                         if (cfg->r4fp) {
5210                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5211                         } else {
5212                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5213                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5214                         }
5215                         break;
5216                 case OP_FCONV_TO_I1:
5217                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5218                         break;
5219                 case OP_FCONV_TO_U1:
5220                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5221                         break;
5222                 case OP_FCONV_TO_I2:
5223                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5224                         break;
5225                 case OP_FCONV_TO_U2:
5226                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5227                         break;
5228                 case OP_FCONV_TO_U4:
5229                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5230                         break;
5231                 case OP_FCONV_TO_I4:
5232                 case OP_FCONV_TO_I:
5233                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5234                         break;
5235                 case OP_FCONV_TO_I8:
5236                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5237                         break;
5238
5239                 case OP_RCONV_TO_I1:
5240                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5241                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5242                         break;
5243                 case OP_RCONV_TO_U1:
5244                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5245                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5246                         break;
5247                 case OP_RCONV_TO_I2:
5248                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5249                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5250                         break;
5251                 case OP_RCONV_TO_U2:
5252                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5253                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5254                         break;
5255                 case OP_RCONV_TO_I4:
5256                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5257                         break;
5258                 case OP_RCONV_TO_U4:
5259                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5260                         break;
5261                 case OP_RCONV_TO_I8:
5262                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5263                         break;
5264                 case OP_RCONV_TO_R8:
5265                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5266                         break;
5267                 case OP_RCONV_TO_R4:
5268                         if (ins->dreg != ins->sreg1)
5269                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5270                         break;
5271
5272                 case OP_LCONV_TO_R_UN: {
5273                         guint8 *br [2];
5274
5275                         /* Based on gcc code */
5276                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5277                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5278
5279                         /* Positive case */
5280                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5281                         br [1] = code; x86_jump8 (code, 0);
5282                         amd64_patch (br [0], code);
5283
5284                         /* Negative case */
5285                         /* Save to the red zone */
5286                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5287                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5288                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5289                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5290                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5291                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5292                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5293                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5294                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5295                         /* Restore */
5296                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5297                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5298                         amd64_patch (br [1], code);
5299                         break;
5300                 }
5301                 case OP_LCONV_TO_OVF_U4:
5302                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5303                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5304                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5305                         break;
5306                 case OP_LCONV_TO_OVF_I4_UN:
5307                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5308                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5309                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5310                         break;
5311                 case OP_FMOVE:
5312                         if (ins->dreg != ins->sreg1)
5313                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5314                         break;
5315                 case OP_RMOVE:
5316                         if (ins->dreg != ins->sreg1)
5317                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5318                         break;
5319                 case OP_MOVE_F_TO_I4:
5320                         if (cfg->r4fp) {
5321                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5322                         } else {
5323                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5324                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5325                         }
5326                         break;
5327                 case OP_MOVE_I4_TO_F:
5328                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5329                         if (!cfg->r4fp)
5330                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5331                         break;
5332                 case OP_MOVE_F_TO_I8:
5333                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5334                         break;
5335                 case OP_MOVE_I8_TO_F:
5336                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5337                         break;
5338                 case OP_FADD:
5339                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5340                         break;
5341                 case OP_FSUB:
5342                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5343                         break;
5344                 case OP_FMUL:
5345                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5346                         break;
5347                 case OP_FDIV:
5348                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5349                         break;
5350                 case OP_FNEG: {
5351                         static double r8_0 = -0.0;
5352
5353                         g_assert (ins->sreg1 == ins->dreg);
5354
5355                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5356                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5357                         break;
5358                 }
5359                 case OP_SIN:
5360                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5361                         break;
5362                 case OP_COS:
5363                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5364                         break;
5365                 case OP_ABS: {
5366                         static guint64 d = 0x7fffffffffffffffUL;
5367
5368                         g_assert (ins->sreg1 == ins->dreg);
5369
5370                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5371                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5372                         break;
5373                 }
5374                 case OP_SQRT:
5375                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5376                         break;
5377
5378                 case OP_RADD:
5379                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5380                         break;
5381                 case OP_RSUB:
5382                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5383                         break;
5384                 case OP_RMUL:
5385                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5386                         break;
5387                 case OP_RDIV:
5388                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5389                         break;
5390                 case OP_RNEG: {
5391                         static float r4_0 = -0.0;
5392
5393                         g_assert (ins->sreg1 == ins->dreg);
5394
5395                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5396                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5397                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5398                         break;
5399                 }
5400
5401                 case OP_IMIN:
5402                         g_assert (cfg->opt & MONO_OPT_CMOV);
5403                         g_assert (ins->dreg == ins->sreg1);
5404                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5405                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5406                         break;
5407                 case OP_IMIN_UN:
5408                         g_assert (cfg->opt & MONO_OPT_CMOV);
5409                         g_assert (ins->dreg == ins->sreg1);
5410                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5411                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5412                         break;
5413                 case OP_IMAX:
5414                         g_assert (cfg->opt & MONO_OPT_CMOV);
5415                         g_assert (ins->dreg == ins->sreg1);
5416                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5417                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5418                         break;
5419                 case OP_IMAX_UN:
5420                         g_assert (cfg->opt & MONO_OPT_CMOV);
5421                         g_assert (ins->dreg == ins->sreg1);
5422                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5423                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5424                         break;
5425                 case OP_LMIN:
5426                         g_assert (cfg->opt & MONO_OPT_CMOV);
5427                         g_assert (ins->dreg == ins->sreg1);
5428                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5429                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5430                         break;
5431                 case OP_LMIN_UN:
5432                         g_assert (cfg->opt & MONO_OPT_CMOV);
5433                         g_assert (ins->dreg == ins->sreg1);
5434                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5435                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5436                         break;
5437                 case OP_LMAX:
5438                         g_assert (cfg->opt & MONO_OPT_CMOV);
5439                         g_assert (ins->dreg == ins->sreg1);
5440                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5441                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5442                         break;
5443                 case OP_LMAX_UN:
5444                         g_assert (cfg->opt & MONO_OPT_CMOV);
5445                         g_assert (ins->dreg == ins->sreg1);
5446                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5447                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5448                         break;
5449                 case OP_X86_FPOP:
5450                         break;
5451                 case OP_FCOMPARE:
5452                         /*
5453                          * The two arguments are swapped because the fbranch instructions
5454                          * depend on this for the non-sse case to work.
5455                          */
5456                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5457                         break;
5458                 case OP_RCOMPARE:
5459                         /*
5460                          * FIXME: Get rid of this.
5461                          * The two arguments are swapped because the fbranch instructions
5462                          * depend on this for the non-sse case to work.
5463                          */
5464                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5465                         break;
5466                 case OP_FCNEQ:
5467                 case OP_FCEQ: {
5468                         /* zeroing the register at the start results in
5469                          * shorter and faster code (we can also remove the widening op)
5470                          */
5471                         guchar *unordered_check;
5472
5473                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5474                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5475                         unordered_check = code;
5476                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5477
5478                         if (ins->opcode == OP_FCEQ) {
5479                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5480                                 amd64_patch (unordered_check, code);
5481                         } else {
5482                                 guchar *jump_to_end;
5483                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5484                                 jump_to_end = code;
5485                                 x86_jump8 (code, 0);
5486                                 amd64_patch (unordered_check, code);
5487                                 amd64_inc_reg (code, ins->dreg);
5488                                 amd64_patch (jump_to_end, code);
5489                         }
5490                         break;
5491                 }
5492                 case OP_FCLT:
5493                 case OP_FCLT_UN: {
5494                         /* zeroing the register at the start results in
5495                          * shorter and faster code (we can also remove the widening op)
5496                          */
5497                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5498                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5499                         if (ins->opcode == OP_FCLT_UN) {
5500                                 guchar *unordered_check = code;
5501                                 guchar *jump_to_end;
5502                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5503                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5504                                 jump_to_end = code;
5505                                 x86_jump8 (code, 0);
5506                                 amd64_patch (unordered_check, code);
5507                                 amd64_inc_reg (code, ins->dreg);
5508                                 amd64_patch (jump_to_end, code);
5509                         } else {
5510                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5511                         }
5512                         break;
5513                 }
5514                 case OP_FCLE: {
5515                         guchar *unordered_check;
5516                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5517                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5518                         unordered_check = code;
5519                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5520                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5521                         amd64_patch (unordered_check, code);
5522                         break;
5523                 }
5524                 case OP_FCGT:
5525                 case OP_FCGT_UN: {
5526                         /* zeroing the register at the start results in
5527                          * shorter and faster code (we can also remove the widening op)
5528                          */
5529                         guchar *unordered_check;
5530
5531                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5532                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5533                         if (ins->opcode == OP_FCGT) {
5534                                 unordered_check = code;
5535                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5536                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5537                                 amd64_patch (unordered_check, code);
5538                         } else {
5539                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5540                         }
5541                         break;
5542                 }
5543                 case OP_FCGE: {
5544                         guchar *unordered_check;
5545                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5546                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5547                         unordered_check = code;
5548                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5549                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5550                         amd64_patch (unordered_check, code);
5551                         break;
5552                 }
5553
5554                 case OP_RCEQ:
5555                 case OP_RCGT:
5556                 case OP_RCLT:
5557                 case OP_RCLT_UN:
5558                 case OP_RCGT_UN: {
5559                         int x86_cond;
5560                         gboolean unordered = FALSE;
5561
5562                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5563                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5564
5565                         switch (ins->opcode) {
5566                         case OP_RCEQ:
5567                                 x86_cond = X86_CC_EQ;
5568                                 break;
5569                         case OP_RCGT:
5570                                 x86_cond = X86_CC_LT;
5571                                 break;
5572                         case OP_RCLT:
5573                                 x86_cond = X86_CC_GT;
5574                                 break;
5575                         case OP_RCLT_UN:
5576                                 x86_cond = X86_CC_GT;
5577                                 unordered = TRUE;
5578                                 break;
5579                         case OP_RCGT_UN:
5580                                 x86_cond = X86_CC_LT;
5581                                 unordered = TRUE;
5582                                 break;
5583                         default:
5584                                 g_assert_not_reached ();
5585                                 break;
5586                         }
5587
5588                         if (unordered) {
5589                                 guchar *unordered_check;
5590                                 guchar *jump_to_end;
5591
5592                                 unordered_check = code;
5593                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5594                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5595                                 jump_to_end = code;
5596                                 x86_jump8 (code, 0);
5597                                 amd64_patch (unordered_check, code);
5598                                 amd64_inc_reg (code, ins->dreg);
5599                                 amd64_patch (jump_to_end, code);
5600                         } else {
5601                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5602                         }
5603                         break;
5604                 }
5605                 case OP_FCLT_MEMBASE:
5606                 case OP_FCGT_MEMBASE:
5607                 case OP_FCLT_UN_MEMBASE:
5608                 case OP_FCGT_UN_MEMBASE:
5609                 case OP_FCEQ_MEMBASE: {
5610                         guchar *unordered_check, *jump_to_end;
5611                         int x86_cond;
5612
5613                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5614                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5615
5616                         switch (ins->opcode) {
5617                         case OP_FCEQ_MEMBASE:
5618                                 x86_cond = X86_CC_EQ;
5619                                 break;
5620                         case OP_FCLT_MEMBASE:
5621                         case OP_FCLT_UN_MEMBASE:
5622                                 x86_cond = X86_CC_LT;
5623                                 break;
5624                         case OP_FCGT_MEMBASE:
5625                         case OP_FCGT_UN_MEMBASE:
5626                                 x86_cond = X86_CC_GT;
5627                                 break;
5628                         default:
5629                                 g_assert_not_reached ();
5630                         }
5631
5632                         unordered_check = code;
5633                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5634                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5635
5636                         switch (ins->opcode) {
5637                         case OP_FCEQ_MEMBASE:
5638                         case OP_FCLT_MEMBASE:
5639                         case OP_FCGT_MEMBASE:
5640                                 amd64_patch (unordered_check, code);
5641                                 break;
5642                         case OP_FCLT_UN_MEMBASE:
5643                         case OP_FCGT_UN_MEMBASE:
5644                                 jump_to_end = code;
5645                                 x86_jump8 (code, 0);
5646                                 amd64_patch (unordered_check, code);
5647                                 amd64_inc_reg (code, ins->dreg);
5648                                 amd64_patch (jump_to_end, code);
5649                                 break;
5650                         default:
5651                                 break;
5652                         }
5653                         break;
5654                 }
5655                 case OP_FBEQ: {
5656                         guchar *jump = code;
5657                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5658                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5659                         amd64_patch (jump, code);
5660                         break;
5661                 }
5662                 case OP_FBNE_UN:
5663                         /* Branch if C013 != 100 */
5664                         /* branch if !ZF or (PF|CF) */
5665                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5666                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5667                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5668                         break;
5669                 case OP_FBLT:
5670                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5671                         break;
5672                 case OP_FBLT_UN:
5673                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5674                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5675                         break;
5676                 case OP_FBGT:
5677                 case OP_FBGT_UN:
5678                         if (ins->opcode == OP_FBGT) {
5679                                 guchar *br1;
5680
5681                                 /* skip branch if C1=1 */
5682                                 br1 = code;
5683                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5684                                 /* branch if (C0 | C3) = 1 */
5685                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5686                                 amd64_patch (br1, code);
5687                                 break;
5688                         } else {
5689                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5690                         }
5691                         break;
5692                 case OP_FBGE: {
5693                         /* Branch if C013 == 100 or 001 */
5694                         guchar *br1;
5695
5696                         /* skip branch if C1=1 */
5697                         br1 = code;
5698                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5699                         /* branch if (C0 | C3) = 1 */
5700                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5701                         amd64_patch (br1, code);
5702                         break;
5703                 }
5704                 case OP_FBGE_UN:
5705                         /* Branch if C013 == 000 */
5706                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5707                         break;
5708                 case OP_FBLE: {
5709                         /* Branch if C013=000 or 100 */
5710                         guchar *br1;
5711
5712                         /* skip branch if C1=1 */
5713                         br1 = code;
5714                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5715                         /* branch if C0=0 */
5716                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5717                         amd64_patch (br1, code);
5718                         break;
5719                 }
5720                 case OP_FBLE_UN:
5721                         /* Branch if C013 != 001 */
5722                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5723                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5724                         break;
5725                 case OP_CKFINITE:
5726                         /* Transfer value to the fp stack */
5727                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5728                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5729                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5730
5731                         amd64_push_reg (code, AMD64_RAX);
5732                         amd64_fxam (code);
5733                         amd64_fnstsw (code);
5734                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5735                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5736                         amd64_pop_reg (code, AMD64_RAX);
5737                         amd64_fstp (code, 0);
5738                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5739                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5740                         break;
5741                 case OP_TLS_GET: {
5742                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5743                         break;
5744                 }
5745                 case OP_TLS_GET_REG:
5746                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5747                         break;
5748                 case OP_TLS_SET: {
5749                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5750                         break;
5751                 }
5752                 case OP_TLS_SET_REG: {
5753                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5754                         break;
5755                 }
5756                 case OP_MEMORY_BARRIER: {
5757                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5758                                 x86_mfence (code);
5759                         break;
5760                 }
5761                 case OP_ATOMIC_ADD_I4:
5762                 case OP_ATOMIC_ADD_I8: {
5763                         int dreg = ins->dreg;
5764                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5765
5766                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5767                                 dreg = AMD64_R11;
5768
5769                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5770                         amd64_prefix (code, X86_LOCK_PREFIX);
5771                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5772                         /* dreg contains the old value, add with sreg2 value */
5773                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5774
5775                         if (ins->dreg != dreg)
5776                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5777
5778                         break;
5779                 }
5780                 case OP_ATOMIC_EXCHANGE_I4:
5781                 case OP_ATOMIC_EXCHANGE_I8: {
5782                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5783
5784                         /* LOCK prefix is implied. */
5785                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5786                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5787                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5788                         break;
5789                 }
5790                 case OP_ATOMIC_CAS_I4:
5791                 case OP_ATOMIC_CAS_I8: {
5792                         guint32 size;
5793
5794                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5795                                 size = 8;
5796                         else
5797                                 size = 4;
5798
5799                         /*
5800                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5801                          * an explanation of how this works.
5802                          */
5803                         g_assert (ins->sreg3 == AMD64_RAX);
5804                         g_assert (ins->sreg1 != AMD64_RAX);
5805                         g_assert (ins->sreg1 != ins->sreg2);
5806
5807                         amd64_prefix (code, X86_LOCK_PREFIX);
5808                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5809
5810                         if (ins->dreg != AMD64_RAX)
5811                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5812                         break;
5813                 }
5814                 case OP_ATOMIC_LOAD_I1: {
5815                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5816                         break;
5817                 }
5818                 case OP_ATOMIC_LOAD_U1: {
5819                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5820                         break;
5821                 }
5822                 case OP_ATOMIC_LOAD_I2: {
5823                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5824                         break;
5825                 }
5826                 case OP_ATOMIC_LOAD_U2: {
5827                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5828                         break;
5829                 }
5830                 case OP_ATOMIC_LOAD_I4: {
5831                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5832                         break;
5833                 }
5834                 case OP_ATOMIC_LOAD_U4:
5835                 case OP_ATOMIC_LOAD_I8:
5836                 case OP_ATOMIC_LOAD_U8: {
5837                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5838                         break;
5839                 }
5840                 case OP_ATOMIC_LOAD_R4: {
5841                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5842                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5843                         break;
5844                 }
5845                 case OP_ATOMIC_LOAD_R8: {
5846                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5847                         break;
5848                 }
5849                 case OP_ATOMIC_STORE_I1:
5850                 case OP_ATOMIC_STORE_U1:
5851                 case OP_ATOMIC_STORE_I2:
5852                 case OP_ATOMIC_STORE_U2:
5853                 case OP_ATOMIC_STORE_I4:
5854                 case OP_ATOMIC_STORE_U4:
5855                 case OP_ATOMIC_STORE_I8:
5856                 case OP_ATOMIC_STORE_U8: {
5857                         int size;
5858
5859                         switch (ins->opcode) {
5860                         case OP_ATOMIC_STORE_I1:
5861                         case OP_ATOMIC_STORE_U1:
5862                                 size = 1;
5863                                 break;
5864                         case OP_ATOMIC_STORE_I2:
5865                         case OP_ATOMIC_STORE_U2:
5866                                 size = 2;
5867                                 break;
5868                         case OP_ATOMIC_STORE_I4:
5869                         case OP_ATOMIC_STORE_U4:
5870                                 size = 4;
5871                                 break;
5872                         case OP_ATOMIC_STORE_I8:
5873                         case OP_ATOMIC_STORE_U8:
5874                                 size = 8;
5875                                 break;
5876                         }
5877
5878                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5879
5880                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5881                                 x86_mfence (code);
5882                         break;
5883                 }
5884                 case OP_ATOMIC_STORE_R4: {
5885                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5886                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5887
5888                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5889                                 x86_mfence (code);
5890                         break;
5891                 }
5892                 case OP_ATOMIC_STORE_R8: {
5893                         x86_nop (code);
5894                         x86_nop (code);
5895                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5896                         x86_nop (code);
5897                         x86_nop (code);
5898
5899                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5900                                 x86_mfence (code);
5901                         break;
5902                 }
5903                 case OP_CARD_TABLE_WBARRIER: {
5904                         int ptr = ins->sreg1;
5905                         int value = ins->sreg2;
5906                         guchar *br = 0;
5907                         int nursery_shift, card_table_shift;
5908                         gpointer card_table_mask;
5909                         size_t nursery_size;
5910
5911                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5912                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5913                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5914
5915                         /*If either point to the stack we can simply avoid the WB. This happens due to
5916                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5917                          */
5918                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5919                                 continue;
5920
5921                         /*
5922                          * We need one register we can clobber, we choose EDX and make sreg1
5923                          * fixed EAX to work around limitations in the local register allocator.
5924                          * sreg2 might get allocated to EDX, but that is not a problem since
5925                          * we use it before clobbering EDX.
5926                          */
5927                         g_assert (ins->sreg1 == AMD64_RAX);
5928
5929                         /*
5930                          * This is the code we produce:
5931                          *
5932                          *   edx = value
5933                          *   edx >>= nursery_shift
5934                          *   cmp edx, (nursery_start >> nursery_shift)
5935                          *   jne done
5936                          *   edx = ptr
5937                          *   edx >>= card_table_shift
5938                          *   edx += cardtable
5939                          *   [edx] = 1
5940                          * done:
5941                          */
5942
5943                         if (mono_gc_card_table_nursery_check ()) {
5944                                 if (value != AMD64_RDX)
5945                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5946                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5947                                 if (shifted_nursery_start >> 31) {
5948                                         /*
5949                                          * The value we need to compare against is 64 bits, so we need
5950                                          * another spare register.  We use RBX, which we save and
5951                                          * restore.
5952                                          */
5953                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5954                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5955                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5956                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5957                                 } else {
5958                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5959                                 }
5960                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5961                         }
5962                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5963                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5964                         if (card_table_mask)
5965                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5966
5967                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5968                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5969
5970                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5971
5972                         if (mono_gc_card_table_nursery_check ())
5973                                 x86_patch (br, code);
5974                         break;
5975                 }
5976 #ifdef MONO_ARCH_SIMD_INTRINSICS
5977                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5978                 case OP_ADDPS:
5979                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981                 case OP_DIVPS:
5982                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984                 case OP_MULPS:
5985                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5986                         break;
5987                 case OP_SUBPS:
5988                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5989                         break;
5990                 case OP_MAXPS:
5991                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5992                         break;
5993                 case OP_MINPS:
5994                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5995                         break;
5996                 case OP_COMPPS:
5997                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5998                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5999                         break;
6000                 case OP_ANDPS:
6001                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6002                         break;
6003                 case OP_ANDNPS:
6004                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6005                         break;
6006                 case OP_ORPS:
6007                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009                 case OP_XORPS:
6010                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_SQRTPS:
6013                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6014                         break;
6015                 case OP_RSQRTPS:
6016                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6017                         break;
6018                 case OP_RCPPS:
6019                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6020                         break;
6021                 case OP_ADDSUBPS:
6022                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024                 case OP_HADDPS:
6025                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027                 case OP_HSUBPS:
6028                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6029                         break;
6030                 case OP_DUPPS_HIGH:
6031                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6032                         break;
6033                 case OP_DUPPS_LOW:
6034                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6035                         break;
6036
6037                 case OP_PSHUFLEW_HIGH:
6038                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6039                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6040                         break;
6041                 case OP_PSHUFLEW_LOW:
6042                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6043                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6044                         break;
6045                 case OP_PSHUFLED:
6046                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6047                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6048                         break;
6049                 case OP_SHUFPS:
6050                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6051                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6052                         break;
6053                 case OP_SHUFPD:
6054                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6055                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6056                         break;
6057
6058                 case OP_ADDPD:
6059                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6060                         break;
6061                 case OP_DIVPD:
6062                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6063                         break;
6064                 case OP_MULPD:
6065                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067                 case OP_SUBPD:
6068                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_MAXPD:
6071                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_MINPD:
6074                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076                 case OP_COMPPD:
6077                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6078                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6079                         break;
6080                 case OP_ANDPD:
6081                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083                 case OP_ANDNPD:
6084                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6085                         break;
6086                 case OP_ORPD:
6087                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089                 case OP_XORPD:
6090                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_SQRTPD:
6093                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6094                         break;
6095                 case OP_ADDSUBPD:
6096                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098                 case OP_HADDPD:
6099                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6100                         break;
6101                 case OP_HSUBPD:
6102                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6103                         break;
6104                 case OP_DUPPD:
6105                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6106                         break;
6107
6108                 case OP_EXTRACT_MASK:
6109                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6110                         break;
6111
6112                 case OP_PAND:
6113                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_POR:
6116                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118                 case OP_PXOR:
6119                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121
6122                 case OP_PADDB:
6123                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6124                         break;
6125                 case OP_PADDW:
6126                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6127                         break;
6128                 case OP_PADDD:
6129                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131                 case OP_PADDQ:
6132                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6133                         break;
6134
6135                 case OP_PSUBB:
6136                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6137                         break;
6138                 case OP_PSUBW:
6139                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6140                         break;
6141                 case OP_PSUBD:
6142                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6143                         break;
6144                 case OP_PSUBQ:
6145                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6146                         break;
6147
6148                 case OP_PMAXB_UN:
6149                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6150                         break;
6151                 case OP_PMAXW_UN:
6152                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6153                         break;
6154                 case OP_PMAXD_UN:
6155                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6156                         break;
6157
6158                 case OP_PMAXB:
6159                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6160                         break;
6161                 case OP_PMAXW:
6162                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6163                         break;
6164                 case OP_PMAXD:
6165                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6166                         break;
6167
6168                 case OP_PAVGB_UN:
6169                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6170                         break;
6171                 case OP_PAVGW_UN:
6172                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6173                         break;
6174
6175                 case OP_PMINB_UN:
6176                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6177                         break;
6178                 case OP_PMINW_UN:
6179                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6180                         break;
6181                 case OP_PMIND_UN:
6182                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6183                         break;
6184
6185                 case OP_PMINB:
6186                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6187                         break;
6188                 case OP_PMINW:
6189                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6190                         break;
6191                 case OP_PMIND:
6192                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194
6195                 case OP_PCMPEQB:
6196                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6197                         break;
6198                 case OP_PCMPEQW:
6199                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6200                         break;
6201                 case OP_PCMPEQD:
6202                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6203                         break;
6204                 case OP_PCMPEQQ:
6205                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6206                         break;
6207
6208                 case OP_PCMPGTB:
6209                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6210                         break;
6211                 case OP_PCMPGTW:
6212                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6213                         break;
6214                 case OP_PCMPGTD:
6215                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6216                         break;
6217                 case OP_PCMPGTQ:
6218                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6219                         break;
6220
6221                 case OP_PSUM_ABS_DIFF:
6222                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6223                         break;
6224
6225                 case OP_UNPACK_LOWB:
6226                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6227                         break;
6228                 case OP_UNPACK_LOWW:
6229                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6230                         break;
6231                 case OP_UNPACK_LOWD:
6232                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6233                         break;
6234                 case OP_UNPACK_LOWQ:
6235                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6236                         break;
6237                 case OP_UNPACK_LOWPS:
6238                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6239                         break;
6240                 case OP_UNPACK_LOWPD:
6241                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6242                         break;
6243
6244                 case OP_UNPACK_HIGHB:
6245                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6246                         break;
6247                 case OP_UNPACK_HIGHW:
6248                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6249                         break;
6250                 case OP_UNPACK_HIGHD:
6251                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6252                         break;
6253                 case OP_UNPACK_HIGHQ:
6254                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6255                         break;
6256                 case OP_UNPACK_HIGHPS:
6257                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6258                         break;
6259                 case OP_UNPACK_HIGHPD:
6260                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6261                         break;
6262
6263                 case OP_PACKW:
6264                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6265                         break;
6266                 case OP_PACKD:
6267                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6268                         break;
6269                 case OP_PACKW_UN:
6270                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6271                         break;
6272                 case OP_PACKD_UN:
6273                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6274                         break;
6275
6276                 case OP_PADDB_SAT_UN:
6277                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6278                         break;
6279                 case OP_PSUBB_SAT_UN:
6280                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6281                         break;
6282                 case OP_PADDW_SAT_UN:
6283                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6284                         break;
6285                 case OP_PSUBW_SAT_UN:
6286                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6287                         break;
6288
6289                 case OP_PADDB_SAT:
6290                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6291                         break;
6292                 case OP_PSUBB_SAT:
6293                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6294                         break;
6295                 case OP_PADDW_SAT:
6296                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6297                         break;
6298                 case OP_PSUBW_SAT:
6299                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6300                         break;
6301
6302                 case OP_PMULW:
6303                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6304                         break;
6305                 case OP_PMULD:
6306                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6307                         break;
6308                 case OP_PMULQ:
6309                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6310                         break;
6311                 case OP_PMULW_HIGH_UN:
6312                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6313                         break;
6314                 case OP_PMULW_HIGH:
6315                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6316                         break;
6317
6318                 case OP_PSHRW:
6319                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6320                         break;
6321                 case OP_PSHRW_REG:
6322                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6323                         break;
6324
6325                 case OP_PSARW:
6326                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6327                         break;
6328                 case OP_PSARW_REG:
6329                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6330                         break;
6331
6332                 case OP_PSHLW:
6333                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6334                         break;
6335                 case OP_PSHLW_REG:
6336                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6337                         break;
6338
6339                 case OP_PSHRD:
6340                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6341                         break;
6342                 case OP_PSHRD_REG:
6343                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6344                         break;
6345
6346                 case OP_PSARD:
6347                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6348                         break;
6349                 case OP_PSARD_REG:
6350                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6351                         break;
6352
6353                 case OP_PSHLD:
6354                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6355                         break;
6356                 case OP_PSHLD_REG:
6357                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6358                         break;
6359
6360                 case OP_PSHRQ:
6361                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6362                         break;
6363                 case OP_PSHRQ_REG:
6364                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6365                         break;
6366
6367                 /*TODO: This is appart of the sse spec but not added
6368                 case OP_PSARQ:
6369                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6370                         break;
6371                 case OP_PSARQ_REG:
6372                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6373                         break;
6374                 */
6375
6376                 case OP_PSHLQ:
6377                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6378                         break;
6379                 case OP_PSHLQ_REG:
6380                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6381                         break;
6382                 case OP_CVTDQ2PD:
6383                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6384                         break;
6385                 case OP_CVTDQ2PS:
6386                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6387                         break;
6388                 case OP_CVTPD2DQ:
6389                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6390                         break;
6391                 case OP_CVTPD2PS:
6392                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6393                         break;
6394                 case OP_CVTPS2DQ:
6395                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6396                         break;
6397                 case OP_CVTPS2PD:
6398                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6399                         break;
6400                 case OP_CVTTPD2DQ:
6401                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6402                         break;
6403                 case OP_CVTTPS2DQ:
6404                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6405                         break;
6406
6407                 case OP_ICONV_TO_X:
6408                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6409                         break;
6410                 case OP_EXTRACT_I4:
6411                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6412                         break;
6413                 case OP_EXTRACT_I8:
6414                         if (ins->inst_c0) {
6415                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6416                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6417                         } else {
6418                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6419                         }
6420                         break;
6421                 case OP_EXTRACT_I1:
6422                 case OP_EXTRACT_U1:
6423                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6424                         if (ins->inst_c0)
6425                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6426                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6427                         break;
6428                 case OP_EXTRACT_I2:
6429                 case OP_EXTRACT_U2:
6430                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6431                         if (ins->inst_c0)
6432                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6433                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6434                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6435                         break;
6436                 case OP_EXTRACT_R8:
6437                         if (ins->inst_c0)
6438                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6439                         else
6440                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6441                         break;
6442                 case OP_INSERT_I2:
6443                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6444                         break;
6445                 case OP_EXTRACTX_U2:
6446                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6447                         break;
6448                 case OP_INSERTX_U1_SLOW:
6449                         /*sreg1 is the extracted ireg (scratch)
6450                         /sreg2 is the to be inserted ireg (scratch)
6451                         /dreg is the xreg to receive the value*/
6452
6453                         /*clear the bits from the extracted word*/
6454                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6455                         /*shift the value to insert if needed*/
6456                         if (ins->inst_c0 & 1)
6457                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6458                         /*join them together*/
6459                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6460                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6461                         break;
6462                 case OP_INSERTX_I4_SLOW:
6463                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6464                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6465                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6466                         break;
6467                 case OP_INSERTX_I8_SLOW:
6468                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6469                         if (ins->inst_c0)
6470                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6471                         else
6472                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6473                         break;
6474
6475                 case OP_INSERTX_R4_SLOW:
6476                         switch (ins->inst_c0) {
6477                         case 0:
6478                                 if (cfg->r4fp)
6479                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6480                                 else
6481                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6482                                 break;
6483                         case 1:
6484                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6485                                 if (cfg->r4fp)
6486                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6487                                 else
6488                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6489                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6490                                 break;
6491                         case 2:
6492                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6493                                 if (cfg->r4fp)
6494                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6495                                 else
6496                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6497                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6498                                 break;
6499                         case 3:
6500                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6501                                 if (cfg->r4fp)
6502                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6503                                 else
6504                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6505                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6506                                 break;
6507                         }
6508                         break;
6509                 case OP_INSERTX_R8_SLOW:
6510                         if (ins->inst_c0)
6511                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6512                         else
6513                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6514                         break;
6515                 case OP_STOREX_MEMBASE_REG:
6516                 case OP_STOREX_MEMBASE:
6517                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6518                         break;
6519                 case OP_LOADX_MEMBASE:
6520                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6521                         break;
6522                 case OP_LOADX_ALIGNED_MEMBASE:
6523                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6524                         break;
6525                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6526                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6527                         break;
6528                 case OP_STOREX_NTA_MEMBASE_REG:
6529                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6530                         break;
6531                 case OP_PREFETCH_MEMBASE:
6532                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6533                         break;
6534
6535                 case OP_XMOVE:
6536                         /*FIXME the peephole pass should have killed this*/
6537                         if (ins->dreg != ins->sreg1)
6538                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6539                         break;
6540                 case OP_XZERO:
6541                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6542                         break;
6543                 case OP_ICONV_TO_R4_RAW:
6544                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6545                         break;
6546
6547                 case OP_FCONV_TO_R8_X:
6548                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6549                         break;
6550
6551                 case OP_XCONV_R8_TO_I4:
6552                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6553                         switch (ins->backend.source_opcode) {
6554                         case OP_FCONV_TO_I1:
6555                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6556                                 break;
6557                         case OP_FCONV_TO_U1:
6558                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6559                                 break;
6560                         case OP_FCONV_TO_I2:
6561                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6562                                 break;
6563                         case OP_FCONV_TO_U2:
6564                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6565                                 break;
6566                         }
6567                         break;
6568
6569                 case OP_EXPAND_I2:
6570                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6571                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6572                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6573                         break;
6574                 case OP_EXPAND_I4:
6575                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6576                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6577                         break;
6578                 case OP_EXPAND_I8:
6579                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6580                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6581                         break;
6582                 case OP_EXPAND_R4:
6583                         if (cfg->r4fp) {
6584                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6585                         } else {
6586                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6587                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6588                         }
6589                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6590                         break;
6591                 case OP_EXPAND_R8:
6592                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6593                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6594                         break;
6595 #endif
6596                 case OP_LIVERANGE_START: {
6597                         if (cfg->verbose_level > 1)
6598                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6599                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6600                         break;
6601                 }
6602                 case OP_LIVERANGE_END: {
6603                         if (cfg->verbose_level > 1)
6604                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6605                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6606                         break;
6607                 }
6608                 case OP_GC_SAFE_POINT: {
6609                         const char *polling_func = NULL;
6610                         int compare_val = 0;
6611                         guint8 *br [1];
6612
6613 #if defined (USE_COOP_GC)
6614                         polling_func = "mono_threads_state_poll";
6615                         compare_val = 1;
6616 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6617                         polling_func = "mono_nacl_gc";
6618                         compare_val = 0xFFFFFFFF;
6619 #endif
6620                         if (!polling_func)
6621                                 break;
6622
6623                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6624                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6625                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6626                         amd64_patch (br[0], code);
6627                         break;
6628                 }
6629
6630                 case OP_GC_LIVENESS_DEF:
6631                 case OP_GC_LIVENESS_USE:
6632                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6633                         ins->backend.pc_offset = code - cfg->native_code;
6634                         break;
6635                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6636                         ins->backend.pc_offset = code - cfg->native_code;
6637                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6638                         break;
6639                 default:
6640                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6641                         g_assert_not_reached ();
6642                 }
6643
6644                 if ((code - cfg->native_code - offset) > max_len) {
6645 #if !defined(__native_client_codegen__)
6646                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6647                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6648                         g_assert_not_reached ();
6649 #endif
6650                 }
6651         }
6652
6653         cfg->code_len = code - cfg->native_code;
6654 }
6655
6656 #endif /* DISABLE_JIT */
6657
6658 void
6659 mono_arch_register_lowlevel_calls (void)
6660 {
6661         /* The signature doesn't matter */
6662         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6663 }
6664
6665 void
6666 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6667 {
6668         unsigned char *ip = ji->ip.i + code;
6669
6670         /*
6671          * Debug code to help track down problems where the target of a near call is
6672          * is not valid.
6673          */
6674         if (amd64_is_near_call (ip)) {
6675                 gint64 disp = (guint8*)target - (guint8*)ip;
6676
6677                 if (!amd64_is_imm32 (disp)) {
6678                         printf ("TYPE: %d\n", ji->type);
6679                         switch (ji->type) {
6680                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6681                                 printf ("V: %s\n", ji->data.name);
6682                                 break;
6683                         case MONO_PATCH_INFO_METHOD_JUMP:
6684                         case MONO_PATCH_INFO_METHOD:
6685                                 printf ("V: %s\n", ji->data.method->name);
6686                                 break;
6687                         default:
6688                                 break;
6689                         }
6690                 }
6691         }
6692
6693         amd64_patch (ip, (gpointer)target);
6694 }
6695
6696 #ifndef DISABLE_JIT
6697
6698 static int
6699 get_max_epilog_size (MonoCompile *cfg)
6700 {
6701         int max_epilog_size = 16;
6702
6703         if (cfg->method->save_lmf)
6704                 max_epilog_size += 256;
6705
6706         if (mono_jit_trace_calls != NULL)
6707                 max_epilog_size += 50;
6708
6709         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6710                 max_epilog_size += 50;
6711
6712         max_epilog_size += (AMD64_NREG * 2);
6713
6714         return max_epilog_size;
6715 }
6716
6717 /*
6718  * This macro is used for testing whenever the unwinder works correctly at every point
6719  * where an async exception can happen.
6720  */
6721 /* This will generate a SIGSEGV at the given point in the code */
6722 #define async_exc_point(code) do { \
6723     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6724          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6725              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6726          cfg->arch.async_point_count ++; \
6727     } \
6728 } while (0)
6729
6730 guint8 *
6731 mono_arch_emit_prolog (MonoCompile *cfg)
6732 {
6733         MonoMethod *method = cfg->method;
6734         MonoBasicBlock *bb;
6735         MonoMethodSignature *sig;
6736         MonoInst *ins;
6737         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6738         guint8 *code;
6739         CallInfo *cinfo;
6740         MonoInst *lmf_var = cfg->lmf_var;
6741         gboolean args_clobbered = FALSE;
6742         gboolean trace = FALSE;
6743 #ifdef __native_client_codegen__
6744         guint alignment_check;
6745 #endif
6746
6747         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6748
6749 #if defined(__default_codegen__)
6750         code = cfg->native_code = g_malloc (cfg->code_size);
6751 #elif defined(__native_client_codegen__)
6752         /* native_code_alloc is not 32-byte aligned, native_code is. */
6753         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6754
6755         /* Align native_code to next nearest kNaclAlignment byte. */
6756         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6757         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6758
6759         code = cfg->native_code;
6760
6761         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6762         g_assert (alignment_check == 0);
6763 #endif
6764
6765         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6766                 trace = TRUE;
6767
6768         /* Amount of stack space allocated by register saving code */
6769         pos = 0;
6770
6771         /* Offset between RSP and the CFA */
6772         cfa_offset = 0;
6773
6774         /*
6775          * The prolog consists of the following parts:
6776          * FP present:
6777          * - push rbp, mov rbp, rsp
6778          * - save callee saved regs using pushes
6779          * - allocate frame
6780          * - save rgctx if needed
6781          * - save lmf if needed
6782          * FP not present:
6783          * - allocate frame
6784          * - save rgctx if needed
6785          * - save lmf if needed
6786          * - save callee saved regs using moves
6787          */
6788
6789         // CFA = sp + 8
6790         cfa_offset = 8;
6791         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6792         // IP saved at CFA - 8
6793         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6794         async_exc_point (code);
6795         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6796
6797         if (!cfg->arch.omit_fp) {
6798                 amd64_push_reg (code, AMD64_RBP);
6799                 cfa_offset += 8;
6800                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6801                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6802                 async_exc_point (code);
6803 #ifdef TARGET_WIN32
6804                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6805 #endif
6806                 /* These are handled automatically by the stack marking code */
6807                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6808
6809                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6810                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6811                 async_exc_point (code);
6812 #ifdef TARGET_WIN32
6813                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6814 #endif
6815         }
6816
6817         /* The param area is always at offset 0 from sp */
6818         /* This needs to be allocated here, since it has to come after the spill area */
6819         if (cfg->param_area) {
6820                 if (cfg->arch.omit_fp)
6821                         // FIXME:
6822                         g_assert_not_reached ();
6823                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6824         }
6825
6826         if (cfg->arch.omit_fp) {
6827                 /*
6828                  * On enter, the stack is misaligned by the pushing of the return
6829                  * address. It is either made aligned by the pushing of %rbp, or by
6830                  * this.
6831                  */
6832                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6833                 if ((alloc_size % 16) == 0) {
6834                         alloc_size += 8;
6835                         /* Mark the padding slot as NOREF */
6836                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6837                 }
6838         } else {
6839                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6840                 if (cfg->stack_offset != alloc_size) {
6841                         /* Mark the padding slot as NOREF */
6842                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6843                 }
6844                 cfg->arch.sp_fp_offset = alloc_size;
6845                 alloc_size -= pos;
6846         }
6847
6848         cfg->arch.stack_alloc_size = alloc_size;
6849
6850         /* Allocate stack frame */
6851         if (alloc_size) {
6852                 /* See mono_emit_stack_alloc */
6853 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6854                 guint32 remaining_size = alloc_size;
6855                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6856                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6857                 guint32 offset = code - cfg->native_code;
6858                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6859                         while (required_code_size >= (cfg->code_size - offset))
6860                                 cfg->code_size *= 2;
6861                         cfg->native_code = mono_realloc_native_code (cfg);
6862                         code = cfg->native_code + offset;
6863                         cfg->stat_code_reallocs++;
6864                 }
6865
6866                 while (remaining_size >= 0x1000) {
6867                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6868                         if (cfg->arch.omit_fp) {
6869                                 cfa_offset += 0x1000;
6870                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6871                         }
6872                         async_exc_point (code);
6873 #ifdef TARGET_WIN32
6874                         if (cfg->arch.omit_fp)
6875                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6876 #endif
6877
6878                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6879                         remaining_size -= 0x1000;
6880                 }
6881                 if (remaining_size) {
6882                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6883                         if (cfg->arch.omit_fp) {
6884                                 cfa_offset += remaining_size;
6885                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6886                                 async_exc_point (code);
6887                         }
6888 #ifdef TARGET_WIN32
6889                         if (cfg->arch.omit_fp)
6890                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6891 #endif
6892                 }
6893 #else
6894                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6895                 if (cfg->arch.omit_fp) {
6896                         cfa_offset += alloc_size;
6897                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6898                         async_exc_point (code);
6899                 }
6900 #endif
6901         }
6902
6903         /* Stack alignment check */
6904 #if 0
6905         {
6906                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6907                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6908                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6909                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6910                 amd64_breakpoint (code);
6911         }
6912 #endif
6913
6914         if (mini_get_debug_options ()->init_stacks) {
6915                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6916
6917                 /* Save registers to the red zone */
6918                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6919                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6920
6921                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6922                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6923                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6924
6925                 amd64_cld (code);
6926 #if defined(__default_codegen__)
6927                 amd64_prefix (code, X86_REP_PREFIX);
6928                 amd64_stosl (code);
6929 #elif defined(__native_client_codegen__)
6930                 /* NaCl stos pseudo-instruction */
6931                 amd64_codegen_pre (code);
6932                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6933                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6934                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6935                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6936                 amd64_prefix (code, X86_REP_PREFIX);
6937                 amd64_stosl (code);
6938                 amd64_codegen_post (code);
6939 #endif /* __native_client_codegen__ */
6940
6941                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6942                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6943         }
6944
6945         /* Save LMF */
6946         if (method->save_lmf)
6947                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6948
6949         /* Save callee saved registers */
6950         if (cfg->arch.omit_fp) {
6951                 save_area_offset = cfg->arch.reg_save_area_offset;
6952                 /* Save caller saved registers after sp is adjusted */
6953                 /* The registers are saved at the bottom of the frame */
6954                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6955         } else {
6956                 /* The registers are saved just below the saved rbp */
6957                 save_area_offset = cfg->arch.reg_save_area_offset;
6958         }
6959
6960         for (i = 0; i < AMD64_NREG; ++i) {
6961                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6962                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6963
6964                         if (cfg->arch.omit_fp) {
6965                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6966                                 /* These are handled automatically by the stack marking code */
6967                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6968                         } else {
6969                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6970                                 // FIXME: GC
6971                         }
6972
6973                         save_area_offset += 8;
6974                         async_exc_point (code);
6975                 }
6976         }
6977
6978         /* store runtime generic context */
6979         if (cfg->rgctx_var) {
6980                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6981                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6982
6983                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6984
6985                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6986                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6987         }
6988
6989         /* compute max_length in order to use short forward jumps */
6990         max_epilog_size = get_max_epilog_size (cfg);
6991         if (cfg->opt & MONO_OPT_BRANCH) {
6992                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6993                         MonoInst *ins;
6994                         int max_length = 0;
6995
6996                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6997                                 max_length += 6;
6998                         /* max alignment for loops */
6999                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7000                                 max_length += LOOP_ALIGNMENT;
7001 #ifdef __native_client_codegen__
7002                         /* max alignment for native client */
7003                         max_length += kNaClAlignment;
7004 #endif
7005
7006                         MONO_BB_FOR_EACH_INS (bb, ins) {
7007 #ifdef __native_client_codegen__
7008                                 {
7009                                         int space_in_block = kNaClAlignment -
7010                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7011                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7012                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
7013                                                 max_length += space_in_block;
7014                                         }
7015                                 }
7016 #endif  /*__native_client_codegen__*/
7017                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7018                         }
7019
7020                         /* Take prolog and epilog instrumentation into account */
7021                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7022                                 max_length += max_epilog_size;
7023
7024                         bb->max_length = max_length;
7025                 }
7026         }
7027
7028         sig = mono_method_signature (method);
7029         pos = 0;
7030
7031         cinfo = cfg->arch.cinfo;
7032
7033         if (sig->ret->type != MONO_TYPE_VOID) {
7034                 /* Save volatile arguments to the stack */
7035                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7036                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7037         }
7038
7039         /* Keep this in sync with emit_load_volatile_arguments */
7040         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7041                 ArgInfo *ainfo = cinfo->args + i;
7042
7043                 ins = cfg->args [i];
7044
7045                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7046                         /* Unused arguments */
7047                         continue;
7048
7049                 /* Save volatile arguments to the stack */
7050                 if (ins->opcode != OP_REGVAR) {
7051                         switch (ainfo->storage) {
7052                         case ArgInIReg: {
7053                                 guint32 size = 8;
7054
7055                                 /* FIXME: I1 etc */
7056                                 /*
7057                                 if (stack_offset & 0x1)
7058                                         size = 1;
7059                                 else if (stack_offset & 0x2)
7060                                         size = 2;
7061                                 else if (stack_offset & 0x4)
7062                                         size = 4;
7063                                 else
7064                                         size = 8;
7065                                 */
7066                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7067
7068                                 /*
7069                                  * Save the original location of 'this',
7070                                  * get_generic_info_from_stack_frame () needs this to properly look up
7071                                  * the argument value during the handling of async exceptions.
7072                                  */
7073                                 if (ins == cfg->args [0]) {
7074                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7075                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7076                                 }
7077                                 break;
7078                         }
7079                         case ArgInFloatSSEReg:
7080                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7081                                 break;
7082                         case ArgInDoubleSSEReg:
7083                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7084                                 break;
7085                         case ArgValuetypeInReg:
7086                                 for (quad = 0; quad < 2; quad ++) {
7087                                         switch (ainfo->pair_storage [quad]) {
7088                                         case ArgInIReg:
7089                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7090                                                 break;
7091                                         case ArgInFloatSSEReg:
7092                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7093                                                 break;
7094                                         case ArgInDoubleSSEReg:
7095                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7096                                                 break;
7097                                         case ArgNone:
7098                                                 break;
7099                                         default:
7100                                                 g_assert_not_reached ();
7101                                         }
7102                                 }
7103                                 break;
7104                         case ArgValuetypeAddrInIReg:
7105                                 if (ainfo->pair_storage [0] == ArgInIReg)
7106                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7107                                 break;
7108                         default:
7109                                 break;
7110                         }
7111                 } else {
7112                         /* Argument allocated to (non-volatile) register */
7113                         switch (ainfo->storage) {
7114                         case ArgInIReg:
7115                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7116                                 break;
7117                         case ArgOnStack:
7118                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7119                                 break;
7120                         default:
7121                                 g_assert_not_reached ();
7122                         }
7123
7124                         if (ins == cfg->args [0]) {
7125                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7126                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7127                         }
7128                 }
7129         }
7130
7131         if (cfg->method->save_lmf)
7132                 args_clobbered = TRUE;
7133
7134         if (trace) {
7135                 args_clobbered = TRUE;
7136                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7137         }
7138
7139         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7140                 args_clobbered = TRUE;
7141
7142         /*
7143          * Optimize the common case of the first bblock making a call with the same
7144          * arguments as the method. This works because the arguments are still in their
7145          * original argument registers.
7146          * FIXME: Generalize this
7147          */
7148         if (!args_clobbered) {
7149                 MonoBasicBlock *first_bb = cfg->bb_entry;
7150                 MonoInst *next;
7151                 int filter = FILTER_IL_SEQ_POINT;
7152
7153                 next = mono_bb_first_inst (first_bb, filter);
7154                 if (!next && first_bb->next_bb) {
7155                         first_bb = first_bb->next_bb;
7156                         next = mono_bb_first_inst (first_bb, filter);
7157                 }
7158
7159                 if (first_bb->in_count > 1)
7160                         next = NULL;
7161
7162                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7163                         ArgInfo *ainfo = cinfo->args + i;
7164                         gboolean match = FALSE;
7165
7166                         ins = cfg->args [i];
7167                         if (ins->opcode != OP_REGVAR) {
7168                                 switch (ainfo->storage) {
7169                                 case ArgInIReg: {
7170                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7171                                                 if (next->dreg == ainfo->reg) {
7172                                                         NULLIFY_INS (next);
7173                                                         match = TRUE;
7174                                                 } else {
7175                                                         next->opcode = OP_MOVE;
7176                                                         next->sreg1 = ainfo->reg;
7177                                                         /* Only continue if the instruction doesn't change argument regs */
7178                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7179                                                                 match = TRUE;
7180                                                 }
7181                                         }
7182                                         break;
7183                                 }
7184                                 default:
7185                                         break;
7186                                 }
7187                         } else {
7188                                 /* Argument allocated to (non-volatile) register */
7189                                 switch (ainfo->storage) {
7190                                 case ArgInIReg:
7191                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7192                                                 NULLIFY_INS (next);
7193                                                 match = TRUE;
7194                                         }
7195                                         break;
7196                                 default:
7197                                         break;
7198                                 }
7199                         }
7200
7201                         if (match) {
7202                                 next = mono_inst_next (next, filter);
7203                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7204                                 if (!next)
7205                                         break;
7206                         }
7207                 }
7208         }
7209
7210         if (cfg->gen_sdb_seq_points) {
7211                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7212
7213                 /* Initialize seq_point_info_var */
7214                 if (cfg->compile_aot) {
7215                         /* Initialize the variable from a GOT slot */
7216                         /* Same as OP_AOTCONST */
7217                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7218                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7219                         g_assert (info_var->opcode == OP_REGOFFSET);
7220                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7221                 }
7222
7223                 if (cfg->compile_aot) {
7224                         /* Initialize ss_tramp_var */
7225                         ins = cfg->arch.ss_tramp_var;
7226                         g_assert (ins->opcode == OP_REGOFFSET);
7227
7228                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7229                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7230                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7231                 } else {
7232                         /* Initialize ss_trigger_page_var */
7233                         ins = cfg->arch.ss_trigger_page_var;
7234
7235                         g_assert (ins->opcode == OP_REGOFFSET);
7236
7237                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7238                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7239                 }
7240         }
7241
7242         cfg->code_len = code - cfg->native_code;
7243
7244         g_assert (cfg->code_len < cfg->code_size);
7245
7246         return code;
7247 }
7248
7249 void
7250 mono_arch_emit_epilog (MonoCompile *cfg)
7251 {
7252         MonoMethod *method = cfg->method;
7253         int quad, i;
7254         guint8 *code;
7255         int max_epilog_size;
7256         CallInfo *cinfo;
7257         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7258         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7259
7260         max_epilog_size = get_max_epilog_size (cfg);
7261
7262         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7263                 cfg->code_size *= 2;
7264                 cfg->native_code = mono_realloc_native_code (cfg);
7265                 cfg->stat_code_reallocs++;
7266         }
7267         code = cfg->native_code + cfg->code_len;
7268
7269         cfg->has_unwind_info_for_epilog = TRUE;
7270
7271         /* Mark the start of the epilog */
7272         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7273
7274         /* Save the uwind state which is needed by the out-of-line code */
7275         mono_emit_unwind_op_remember_state (cfg, code);
7276
7277         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7278                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7279
7280         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7281
7282         if (method->save_lmf) {
7283                 /* check if we need to restore protection of the stack after a stack overflow */
7284                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7285                         guint8 *patch;
7286                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7287                         /* we load the value in a separate instruction: this mechanism may be
7288                          * used later as a safer way to do thread interruption
7289                          */
7290                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7291                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7292                         patch = code;
7293                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7294                         /* note that the call trampoline will preserve eax/edx */
7295                         x86_call_reg (code, X86_ECX);
7296                         x86_patch (patch, code);
7297                 } else {
7298                         /* FIXME: maybe save the jit tls in the prolog */
7299                 }
7300                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7301                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7302                 }
7303         }
7304
7305         /* Restore callee saved regs */
7306         for (i = 0; i < AMD64_NREG; ++i) {
7307                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7308                         /* Restore only used_int_regs, not arch.saved_iregs */
7309                         if (cfg->used_int_regs & (1 << i)) {
7310                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7311                                 mono_emit_unwind_op_same_value (cfg, code, i);
7312                                 async_exc_point (code);
7313                         }
7314                         save_area_offset += 8;
7315                 }
7316         }
7317
7318         /* Load returned vtypes into registers if needed */
7319         cinfo = cfg->arch.cinfo;
7320         if (cinfo->ret.storage == ArgValuetypeInReg) {
7321                 ArgInfo *ainfo = &cinfo->ret;
7322                 MonoInst *inst = cfg->ret;
7323
7324                 for (quad = 0; quad < 2; quad ++) {
7325                         switch (ainfo->pair_storage [quad]) {
7326                         case ArgInIReg:
7327                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7328                                 break;
7329                         case ArgInFloatSSEReg:
7330                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7331                                 break;
7332                         case ArgInDoubleSSEReg:
7333                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7334                                 break;
7335                         case ArgNone:
7336                                 break;
7337                         default:
7338                                 g_assert_not_reached ();
7339                         }
7340                 }
7341         }
7342
7343         if (cfg->arch.omit_fp) {
7344                 if (cfg->arch.stack_alloc_size) {
7345                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7346                 }
7347         } else {
7348                 amd64_leave (code);
7349                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7350         }
7351         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7352         async_exc_point (code);
7353         amd64_ret (code);
7354
7355         /* Restore the unwind state to be the same as before the epilog */
7356         mono_emit_unwind_op_restore_state (cfg, code);
7357
7358         cfg->code_len = code - cfg->native_code;
7359
7360         g_assert (cfg->code_len < cfg->code_size);
7361 }
7362
7363 void
7364 mono_arch_emit_exceptions (MonoCompile *cfg)
7365 {
7366         MonoJumpInfo *patch_info;
7367         int nthrows, i;
7368         guint8 *code;
7369         MonoClass *exc_classes [16];
7370         guint8 *exc_throw_start [16], *exc_throw_end [16];
7371         guint32 code_size = 0;
7372
7373         /* Compute needed space */
7374         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7375                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7376                         code_size += 40;
7377                 if (patch_info->type == MONO_PATCH_INFO_R8)
7378                         code_size += 8 + 15; /* sizeof (double) + alignment */
7379                 if (patch_info->type == MONO_PATCH_INFO_R4)
7380                         code_size += 4 + 15; /* sizeof (float) + alignment */
7381                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7382                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7383         }
7384
7385 #ifdef __native_client_codegen__
7386         /* Give us extra room on Native Client.  This could be   */
7387         /* more carefully calculated, but bundle alignment makes */
7388         /* it much trickier, so *2 like other places is good.    */
7389         code_size *= 2;
7390 #endif
7391
7392         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7393                 cfg->code_size *= 2;
7394                 cfg->native_code = mono_realloc_native_code (cfg);
7395                 cfg->stat_code_reallocs++;
7396         }
7397
7398         code = cfg->native_code + cfg->code_len;
7399
7400         /* add code to raise exceptions */
7401         nthrows = 0;
7402         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7403                 switch (patch_info->type) {
7404                 case MONO_PATCH_INFO_EXC: {
7405                         MonoClass *exc_class;
7406                         guint8 *buf, *buf2;
7407                         guint32 throw_ip;
7408
7409                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7410
7411                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7412                         g_assert (exc_class);
7413                         throw_ip = patch_info->ip.i;
7414
7415                         //x86_breakpoint (code);
7416                         /* Find a throw sequence for the same exception class */
7417                         for (i = 0; i < nthrows; ++i)
7418                                 if (exc_classes [i] == exc_class)
7419                                         break;
7420                         if (i < nthrows) {
7421                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7422                                 x86_jump_code (code, exc_throw_start [i]);
7423                                 patch_info->type = MONO_PATCH_INFO_NONE;
7424                         }
7425                         else {
7426                                 buf = code;
7427                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7428                                 buf2 = code;
7429
7430                                 if (nthrows < 16) {
7431                                         exc_classes [nthrows] = exc_class;
7432                                         exc_throw_start [nthrows] = code;
7433                                 }
7434                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7435
7436                                 patch_info->type = MONO_PATCH_INFO_NONE;
7437
7438                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7439
7440                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7441                                 while (buf < buf2)
7442                                         x86_nop (buf);
7443
7444                                 if (nthrows < 16) {
7445                                         exc_throw_end [nthrows] = code;
7446                                         nthrows ++;
7447                                 }
7448                         }
7449                         break;
7450                 }
7451                 default:
7452                         /* do nothing */
7453                         break;
7454                 }
7455                 g_assert(code < cfg->native_code + cfg->code_size);
7456         }
7457
7458         /* Handle relocations with RIP relative addressing */
7459         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7460                 gboolean remove = FALSE;
7461                 guint8 *orig_code = code;
7462
7463                 switch (patch_info->type) {
7464                 case MONO_PATCH_INFO_R8:
7465                 case MONO_PATCH_INFO_R4: {
7466                         guint8 *pos, *patch_pos;
7467                         guint32 target_pos;
7468
7469                         /* The SSE opcodes require a 16 byte alignment */
7470 #if defined(__default_codegen__)
7471                         code = (guint8*)ALIGN_TO (code, 16);
7472 #elif defined(__native_client_codegen__)
7473                         {
7474                                 /* Pad this out with HLT instructions  */
7475                                 /* or we can get garbage bytes emitted */
7476                                 /* which will fail validation          */
7477                                 guint8 *aligned_code;
7478                                 /* extra align to make room for  */
7479                                 /* mov/push below                      */
7480                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7481                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7482                                 /* The technique of hiding data in an  */
7483                                 /* instruction has a problem here: we  */
7484                                 /* need the data aligned to a 16-byte  */
7485                                 /* boundary but the instruction cannot */
7486                                 /* cross the bundle boundary. so only  */
7487                                 /* odd multiples of 16 can be used     */
7488                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7489                                         aligned_code += 16;
7490                                 }
7491                                 while (code < aligned_code) {
7492                                         *(code++) = 0xf4; /* hlt */
7493                                 }
7494                         }
7495 #endif
7496
7497                         pos = cfg->native_code + patch_info->ip.i;
7498                         if (IS_REX (pos [1])) {
7499                                 patch_pos = pos + 5;
7500                                 target_pos = code - pos - 9;
7501                         }
7502                         else {
7503                                 patch_pos = pos + 4;
7504                                 target_pos = code - pos - 8;
7505                         }
7506
7507                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7508 #ifdef __native_client_codegen__
7509                                 /* Hide 64-bit data in a         */
7510                                 /* "mov imm64, r11" instruction. */
7511                                 /* write it before the start of  */
7512                                 /* the data*/
7513                                 *(code-2) = 0x49; /* prefix      */
7514                                 *(code-1) = 0xbb; /* mov X, %r11 */
7515 #endif
7516                                 *(double*)code = *(double*)patch_info->data.target;
7517                                 code += sizeof (double);
7518                         } else {
7519 #ifdef __native_client_codegen__
7520                                 /* Hide 32-bit data in a        */
7521                                 /* "push imm32" instruction.    */
7522                                 *(code-1) = 0x68; /* push */
7523 #endif
7524                                 *(float*)code = *(float*)patch_info->data.target;
7525                                 code += sizeof (float);
7526                         }
7527
7528                         *(guint32*)(patch_pos) = target_pos;
7529
7530                         remove = TRUE;
7531                         break;
7532                 }
7533                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7534                         guint8 *pos;
7535
7536                         if (cfg->compile_aot)
7537                                 continue;
7538
7539                         /*loading is faster against aligned addresses.*/
7540                         code = (guint8*)ALIGN_TO (code, 8);
7541                         memset (orig_code, 0, code - orig_code);
7542
7543                         pos = cfg->native_code + patch_info->ip.i;
7544
7545                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7546                         if (IS_REX (pos [1]))
7547                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7548                         else
7549                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7550
7551                         *(gpointer*)code = (gpointer)patch_info->data.target;
7552                         code += sizeof (gpointer);
7553
7554                         remove = TRUE;
7555                         break;
7556                 }
7557                 default:
7558                         break;
7559                 }
7560
7561                 if (remove) {
7562                         if (patch_info == cfg->patch_info)
7563                                 cfg->patch_info = patch_info->next;
7564                         else {
7565                                 MonoJumpInfo *tmp;
7566
7567                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7568                                         ;
7569                                 tmp->next = patch_info->next;
7570                         }
7571                 }
7572                 g_assert (code < cfg->native_code + cfg->code_size);
7573         }
7574
7575         cfg->code_len = code - cfg->native_code;
7576
7577         g_assert (cfg->code_len < cfg->code_size);
7578
7579 }
7580
7581 #endif /* DISABLE_JIT */
7582
7583 void*
7584 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7585 {
7586         guchar *code = p;
7587         MonoMethodSignature *sig;
7588         MonoInst *inst;
7589         int i, n, stack_area = 0;
7590
7591         /* Keep this in sync with mono_arch_get_argument_info */
7592
7593         if (enable_arguments) {
7594                 /* Allocate a new area on the stack and save arguments there */
7595                 sig = mono_method_signature (cfg->method);
7596
7597                 n = sig->param_count + sig->hasthis;
7598
7599                 stack_area = ALIGN_TO (n * 8, 16);
7600
7601                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7602
7603                 for (i = 0; i < n; ++i) {
7604                         inst = cfg->args [i];
7605
7606                         if (inst->opcode == OP_REGVAR)
7607                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7608                         else {
7609                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7610                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7611                         }
7612                 }
7613         }
7614
7615         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7616         amd64_set_reg_template (code, AMD64_ARG_REG1);
7617         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7618         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7619
7620         if (enable_arguments)
7621                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7622
7623         return code;
7624 }
7625
7626 enum {
7627         SAVE_NONE,
7628         SAVE_STRUCT,
7629         SAVE_EAX,
7630         SAVE_EAX_EDX,
7631         SAVE_XMM
7632 };
7633
7634 void*
7635 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7636 {
7637         guchar *code = p;
7638         int save_mode = SAVE_NONE;
7639         MonoMethod *method = cfg->method;
7640         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7641         int i;
7642
7643         switch (ret_type->type) {
7644         case MONO_TYPE_VOID:
7645                 /* special case string .ctor icall */
7646                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7647                         save_mode = SAVE_EAX;
7648                 else
7649                         save_mode = SAVE_NONE;
7650                 break;
7651         case MONO_TYPE_I8:
7652         case MONO_TYPE_U8:
7653                 save_mode = SAVE_EAX;
7654                 break;
7655         case MONO_TYPE_R4:
7656         case MONO_TYPE_R8:
7657                 save_mode = SAVE_XMM;
7658                 break;
7659         case MONO_TYPE_GENERICINST:
7660                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7661                         save_mode = SAVE_EAX;
7662                         break;
7663                 }
7664                 /* Fall through */
7665         case MONO_TYPE_VALUETYPE:
7666                 save_mode = SAVE_STRUCT;
7667                 break;
7668         default:
7669                 save_mode = SAVE_EAX;
7670                 break;
7671         }
7672
7673         /* Save the result and copy it into the proper argument register */
7674         switch (save_mode) {
7675         case SAVE_EAX:
7676                 amd64_push_reg (code, AMD64_RAX);
7677                 /* Align stack */
7678                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7679                 if (enable_arguments)
7680                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7681                 break;
7682         case SAVE_STRUCT:
7683                 /* FIXME: */
7684                 if (enable_arguments)
7685                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7686                 break;
7687         case SAVE_XMM:
7688                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7689                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7690                 /* Align stack */
7691                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7692                 /*
7693                  * The result is already in the proper argument register so no copying
7694                  * needed.
7695                  */
7696                 break;
7697         case SAVE_NONE:
7698                 break;
7699         default:
7700                 g_assert_not_reached ();
7701         }
7702
7703         /* Set %al since this is a varargs call */
7704         if (save_mode == SAVE_XMM)
7705                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7706         else
7707                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7708
7709         if (preserve_argument_registers) {
7710                 for (i = 0; i < PARAM_REGS; ++i)
7711                         amd64_push_reg (code, param_regs [i]);
7712         }
7713
7714         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7715         amd64_set_reg_template (code, AMD64_ARG_REG1);
7716         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7717
7718         if (preserve_argument_registers) {
7719                 for (i = PARAM_REGS - 1; i >= 0; --i)
7720                         amd64_pop_reg (code, param_regs [i]);
7721         }
7722
7723         /* Restore result */
7724         switch (save_mode) {
7725         case SAVE_EAX:
7726                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7727                 amd64_pop_reg (code, AMD64_RAX);
7728                 break;
7729         case SAVE_STRUCT:
7730                 /* FIXME: */
7731                 break;
7732         case SAVE_XMM:
7733                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7734                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7735                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7736                 break;
7737         case SAVE_NONE:
7738                 break;
7739         default:
7740                 g_assert_not_reached ();
7741         }
7742
7743         return code;
7744 }
7745
7746 void
7747 mono_arch_flush_icache (guint8 *code, gint size)
7748 {
7749         /* Not needed */
7750 }
7751
7752 void
7753 mono_arch_flush_register_windows (void)
7754 {
7755 }
7756
7757 gboolean
7758 mono_arch_is_inst_imm (gint64 imm)
7759 {
7760         return amd64_use_imm32 (imm);
7761 }
7762
7763 /*
7764  * Determine whenever the trap whose info is in SIGINFO is caused by
7765  * integer overflow.
7766  */
7767 gboolean
7768 mono_arch_is_int_overflow (void *sigctx, void *info)
7769 {
7770         MonoContext ctx;
7771         guint8* rip;
7772         int reg;
7773         gint64 value;
7774
7775         mono_sigctx_to_monoctx (sigctx, &ctx);
7776
7777         rip = (guint8*)ctx.gregs [AMD64_RIP];
7778
7779         if (IS_REX (rip [0])) {
7780                 reg = amd64_rex_b (rip [0]);
7781                 rip ++;
7782         }
7783         else
7784                 reg = 0;
7785
7786         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7787                 /* idiv REG */
7788                 reg += x86_modrm_rm (rip [1]);
7789
7790                 value = ctx.gregs [reg];
7791
7792                 if (value == -1)
7793                         return TRUE;
7794         }
7795
7796         return FALSE;
7797 }
7798
7799 guint32
7800 mono_arch_get_patch_offset (guint8 *code)
7801 {
7802         return 3;
7803 }
7804
7805 /**
7806  * mono_breakpoint_clean_code:
7807  *
7808  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7809  * breakpoints in the original code, they are removed in the copy.
7810  *
7811  * Returns TRUE if no sw breakpoint was present.
7812  */
7813 gboolean
7814 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7815 {
7816         /*
7817          * If method_start is non-NULL we need to perform bound checks, since we access memory
7818          * at code - offset we could go before the start of the method and end up in a different
7819          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7820          * instead.
7821          */
7822         if (!method_start || code - offset >= method_start) {
7823                 memcpy (buf, code - offset, size);
7824         } else {
7825                 int diff = code - method_start;
7826                 memset (buf, 0, size);
7827                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7828         }
7829         return TRUE;
7830 }
7831
7832 #if defined(__native_client_codegen__)
7833 /* For membase calls, we want the base register. for Native Client,  */
7834 /* all indirect calls have the following sequence with the given sizes: */
7835 /* mov %eXX,%eXX                                [2-3]   */
7836 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7837 /* and $0xffffffffffffffe0,%r11d                [4]     */
7838 /* add %r15,%r11                                [3]     */
7839 /* callq *%r11                                  [3]     */
7840
7841
7842 /* Determine if code points to a NaCl call-through-register sequence, */
7843 /* (i.e., the last 3 instructions listed above) */
7844 int
7845 is_nacl_call_reg_sequence(guint8* code)
7846 {
7847         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7848                                "\x4d\x03\xdf"     /* add */
7849                                "\x41\xff\xd3";   /* call */
7850         return memcmp(code, sequence, 10) == 0;
7851 }
7852
7853 /* Determine if code points to the first opcode of the mov membase component */
7854 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7855 /* (there could be a REX prefix before the opcode but it is ignored) */
7856 static int
7857 is_nacl_indirect_call_membase_sequence(guint8* code)
7858 {
7859                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7860         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7861                /* and that src reg = dest reg */
7862                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7863                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7864                IS_REX(code[2]) &&
7865                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7866                /* and has dst of r11 and base of r15 */
7867                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7868                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7869 }
7870 #endif /* __native_client_codegen__ */
7871
7872 int
7873 mono_arch_get_this_arg_reg (guint8 *code)
7874 {
7875         return AMD64_ARG_REG1;
7876 }
7877
7878 gpointer
7879 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7880 {
7881         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7882 }
7883
7884 #define MAX_ARCH_DELEGATE_PARAMS 10
7885
7886 static gpointer
7887 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7888 {
7889         guint8 *code, *start;
7890         GSList *unwind_ops = NULL;
7891         int i;
7892
7893         unwind_ops = mono_arch_get_cie_program ();
7894
7895         if (has_target) {
7896                 start = code = mono_global_codeman_reserve (64);
7897
7898                 /* Replace the this argument with the target */
7899                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7900                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7901                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7902
7903                 g_assert ((code - start) < 64);
7904         } else {
7905                 start = code = mono_global_codeman_reserve (64);
7906
7907                 if (param_count == 0) {
7908                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7909                 } else {
7910                         /* We have to shift the arguments left */
7911                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7912                         for (i = 0; i < param_count; ++i) {
7913 #ifdef TARGET_WIN32
7914                                 if (i < 3)
7915                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7916                                 else
7917                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7918 #else
7919                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7920 #endif
7921                         }
7922
7923                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7924                 }
7925                 g_assert ((code - start) < 64);
7926         }
7927
7928         nacl_global_codeman_validate (&start, 64, &code);
7929         mono_arch_flush_icache (start, code - start);
7930
7931         if (has_target) {
7932                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7933         } else {
7934                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7935                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7936                 g_free (name);
7937         }
7938
7939         if (mono_jit_map_is_enabled ()) {
7940                 char *buff;
7941                 if (has_target)
7942                         buff = (char*)"delegate_invoke_has_target";
7943                 else
7944                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7945                 mono_emit_jit_tramp (start, code - start, buff);
7946                 if (!has_target)
7947                         g_free (buff);
7948         }
7949         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7950
7951         return start;
7952 }
7953
7954 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7955
7956 static gpointer
7957 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7958 {
7959         guint8 *code, *start;
7960         int size = 20;
7961         char *tramp_name;
7962         GSList *unwind_ops;
7963
7964         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7965                 return NULL;
7966
7967         start = code = mono_global_codeman_reserve (size);
7968
7969         unwind_ops = mono_arch_get_cie_program ();
7970
7971         /* Replace the this argument with the target */
7972         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7973         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7974
7975         if (load_imt_reg) {
7976                 /* Load the IMT reg */
7977                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7978         }
7979
7980         /* Load the vtable */
7981         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7982         amd64_jump_membase (code, AMD64_RAX, offset);
7983         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7984
7985         if (load_imt_reg)
7986                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
7987         else
7988                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
7989         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7990         g_free (tramp_name);
7991
7992         return start;
7993 }
7994
7995 /*
7996  * mono_arch_get_delegate_invoke_impls:
7997  *
7998  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7999  * trampolines.
8000  */
8001 GSList*
8002 mono_arch_get_delegate_invoke_impls (void)
8003 {
8004         GSList *res = NULL;
8005         MonoTrampInfo *info;
8006         int i;
8007
8008         get_delegate_invoke_impl (&info, TRUE, 0);
8009         res = g_slist_prepend (res, info);
8010
8011         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8012                 get_delegate_invoke_impl (&info, FALSE, i);
8013                 res = g_slist_prepend (res, info);
8014         }
8015
8016         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8017                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8018                 res = g_slist_prepend (res, info);
8019
8020                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8021                 res = g_slist_prepend (res, info);
8022         }
8023
8024         return res;
8025 }
8026
8027 gpointer
8028 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8029 {
8030         guint8 *code, *start;
8031         int i;
8032
8033         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8034                 return NULL;
8035
8036         /* FIXME: Support more cases */
8037         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8038                 return NULL;
8039
8040         if (has_target) {
8041                 static guint8* cached = NULL;
8042
8043                 if (cached)
8044                         return cached;
8045
8046                 if (mono_aot_only) {
8047                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8048                 } else {
8049                         MonoTrampInfo *info;
8050                         start = get_delegate_invoke_impl (&info, TRUE, 0);
8051                         mono_tramp_info_register (info, NULL);
8052                 }
8053
8054                 mono_memory_barrier ();
8055
8056                 cached = start;
8057         } else {
8058                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8059                 for (i = 0; i < sig->param_count; ++i)
8060                         if (!mono_is_regsize_var (sig->params [i]))
8061                                 return NULL;
8062                 if (sig->param_count > 4)
8063                         return NULL;
8064
8065                 code = cache [sig->param_count];
8066                 if (code)
8067                         return code;
8068
8069                 if (mono_aot_only) {
8070                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8071                         start = mono_aot_get_trampoline (name);
8072                         g_free (name);
8073                 } else {
8074                         MonoTrampInfo *info;
8075                         start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8076                         mono_tramp_info_register (info, NULL);
8077                 }
8078
8079                 mono_memory_barrier ();
8080
8081                 cache [sig->param_count] = start;
8082         }
8083
8084         return start;
8085 }
8086
8087 gpointer
8088 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8089 {
8090         MonoTrampInfo *info;
8091         gpointer code;
8092
8093         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8094         if (code)
8095                 mono_tramp_info_register (info, NULL);
8096         return code;
8097 }
8098
8099 void
8100 mono_arch_finish_init (void)
8101 {
8102 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8103         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8104 #endif
8105 }
8106
8107 void
8108 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8109 {
8110 }
8111
8112 #if defined(__default_codegen__)
8113 #define CMP_SIZE (6 + 1)
8114 #define CMP_REG_REG_SIZE (4 + 1)
8115 #define BR_SMALL_SIZE 2
8116 #define BR_LARGE_SIZE 6
8117 #define MOV_REG_IMM_SIZE 10
8118 #define MOV_REG_IMM_32BIT_SIZE 6
8119 #define JUMP_REG_SIZE (2 + 1)
8120 #elif defined(__native_client_codegen__)
8121 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8122 #define CMP_SIZE ((6 + 1) * 2 - 1)
8123 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8124 #define BR_SMALL_SIZE (2 * 2 - 1)
8125 #define BR_LARGE_SIZE (6 * 2 - 1)
8126 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8127 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8128 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8129 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8130 /* Jump membase's size is large and unpredictable    */
8131 /* in native client, just pad it out a whole bundle. */
8132 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8133 #endif
8134
8135 static int
8136 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8137 {
8138         int i, distance = 0;
8139         for (i = start; i < target; ++i)
8140                 distance += imt_entries [i]->chunk_size;
8141         return distance;
8142 }
8143
8144 /*
8145  * LOCKING: called with the domain lock held
8146  */
8147 gpointer
8148 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8149         gpointer fail_tramp)
8150 {
8151         int i;
8152         int size = 0;
8153         guint8 *code, *start;
8154         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8155         GSList *unwind_ops;
8156
8157         for (i = 0; i < count; ++i) {
8158                 MonoIMTCheckItem *item = imt_entries [i];
8159                 if (item->is_equals) {
8160                         if (item->check_target_idx) {
8161                                 if (!item->compare_done) {
8162                                         if (amd64_use_imm32 ((gint64)item->key))
8163                                                 item->chunk_size += CMP_SIZE;
8164                                         else
8165                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8166                                 }
8167                                 if (item->has_target_code) {
8168                                         item->chunk_size += MOV_REG_IMM_SIZE;
8169                                 } else {
8170                                         if (vtable_is_32bit)
8171                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8172                                         else
8173                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8174 #ifdef __native_client_codegen__
8175                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8176 #endif
8177                                 }
8178                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8179                         } else {
8180                                 if (fail_tramp) {
8181                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8182                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8183                                 } else {
8184                                         if (vtable_is_32bit)
8185                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8186                                         else
8187                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8188                                         item->chunk_size += JUMP_REG_SIZE;
8189                                         /* with assert below:
8190                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8191                                          */
8192 #ifdef __native_client_codegen__
8193                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8194 #endif
8195                                 }
8196                         }
8197                 } else {
8198                         if (amd64_use_imm32 ((gint64)item->key))
8199                                 item->chunk_size += CMP_SIZE;
8200                         else
8201                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8202                         item->chunk_size += BR_LARGE_SIZE;
8203                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8204                 }
8205                 size += item->chunk_size;
8206         }
8207 #if defined(__native_client__) && defined(__native_client_codegen__)
8208         /* In Native Client, we don't re-use thunks, allocate from the */
8209         /* normal code manager paths. */
8210         code = mono_domain_code_reserve (domain, size);
8211 #else
8212         if (fail_tramp)
8213                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8214         else
8215                 code = mono_domain_code_reserve (domain, size);
8216 #endif
8217         start = code;
8218
8219         unwind_ops = mono_arch_get_cie_program ();
8220
8221         for (i = 0; i < count; ++i) {
8222                 MonoIMTCheckItem *item = imt_entries [i];
8223                 item->code_target = code;
8224                 if (item->is_equals) {
8225                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8226
8227                         if (item->check_target_idx || fail_case) {
8228                                 if (!item->compare_done || fail_case) {
8229                                         if (amd64_use_imm32 ((gint64)item->key))
8230                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8231                                         else {
8232                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8233                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8234                                         }
8235                                 }
8236                                 item->jmp_code = code;
8237                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8238                                 if (item->has_target_code) {
8239                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8240                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8241                                 } else {
8242                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8243                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8244                                 }
8245
8246                                 if (fail_case) {
8247                                         amd64_patch (item->jmp_code, code);
8248                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8249                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8250                                         item->jmp_code = NULL;
8251                                 }
8252                         } else {
8253                                 /* enable the commented code to assert on wrong method */
8254 #if 0
8255                                 if (amd64_is_imm32 (item->key))
8256                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8257                                 else {
8258                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8259                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8260                                 }
8261                                 item->jmp_code = code;
8262                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8263                                 /* See the comment below about R10 */
8264                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8265                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8266                                 amd64_patch (item->jmp_code, code);
8267                                 amd64_breakpoint (code);
8268                                 item->jmp_code = NULL;
8269 #else
8270                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8271                                    needs to be preserved.  R10 needs
8272                                    to be preserved for calls which
8273                                    require a runtime generic context,
8274                                    but interface calls don't. */
8275                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8276                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8277 #endif
8278                         }
8279                 } else {
8280                         if (amd64_use_imm32 ((gint64)item->key))
8281                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8282                         else {
8283                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8284                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8285                         }
8286                         item->jmp_code = code;
8287                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8288                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8289                         else
8290                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8291                 }
8292                 g_assert (code - item->code_target <= item->chunk_size);
8293         }
8294         /* patch the branches to get to the target items */
8295         for (i = 0; i < count; ++i) {
8296                 MonoIMTCheckItem *item = imt_entries [i];
8297                 if (item->jmp_code) {
8298                         if (item->check_target_idx) {
8299                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8300                         }
8301                 }
8302         }
8303
8304         if (!fail_tramp)
8305                 mono_stats.imt_thunks_size += code - start;
8306         g_assert (code - start <= size);
8307
8308         nacl_domain_code_validate(domain, &start, size, &code);
8309         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8310
8311         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8312
8313         return start;
8314 }
8315
8316 MonoMethod*
8317 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8318 {
8319         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8320 }
8321
8322 MonoVTable*
8323 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8324 {
8325         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8326 }
8327
8328 GSList*
8329 mono_arch_get_cie_program (void)
8330 {
8331         GSList *l = NULL;
8332
8333         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8334         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8335
8336         return l;
8337 }
8338
8339 #ifndef DISABLE_JIT
8340
8341 MonoInst*
8342 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8343 {
8344         MonoInst *ins = NULL;
8345         int opcode = 0;
8346
8347         if (cmethod->klass == mono_defaults.math_class) {
8348                 if (strcmp (cmethod->name, "Sin") == 0) {
8349                         opcode = OP_SIN;
8350                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8351                         opcode = OP_COS;
8352                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8353                         opcode = OP_SQRT;
8354                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8355                         opcode = OP_ABS;
8356                 }
8357
8358                 if (opcode && fsig->param_count == 1) {
8359                         MONO_INST_NEW (cfg, ins, opcode);
8360                         ins->type = STACK_R8;
8361                         ins->dreg = mono_alloc_freg (cfg);
8362                         ins->sreg1 = args [0]->dreg;
8363                         MONO_ADD_INS (cfg->cbb, ins);
8364                 }
8365
8366                 opcode = 0;
8367                 if (cfg->opt & MONO_OPT_CMOV) {
8368                         if (strcmp (cmethod->name, "Min") == 0) {
8369                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8370                                         opcode = OP_IMIN;
8371                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8372                                         opcode = OP_IMIN_UN;
8373                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8374                                         opcode = OP_LMIN;
8375                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8376                                         opcode = OP_LMIN_UN;
8377                         } else if (strcmp (cmethod->name, "Max") == 0) {
8378                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8379                                         opcode = OP_IMAX;
8380                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8381                                         opcode = OP_IMAX_UN;
8382                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8383                                         opcode = OP_LMAX;
8384                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8385                                         opcode = OP_LMAX_UN;
8386                         }
8387                 }
8388
8389                 if (opcode && fsig->param_count == 2) {
8390                         MONO_INST_NEW (cfg, ins, opcode);
8391                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8392                         ins->dreg = mono_alloc_ireg (cfg);
8393                         ins->sreg1 = args [0]->dreg;
8394                         ins->sreg2 = args [1]->dreg;
8395                         MONO_ADD_INS (cfg->cbb, ins);
8396                 }
8397
8398 #if 0
8399                 /* OP_FREM is not IEEE compatible */
8400                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8401                         MONO_INST_NEW (cfg, ins, OP_FREM);
8402                         ins->inst_i0 = args [0];
8403                         ins->inst_i1 = args [1];
8404                 }
8405 #endif
8406         }
8407
8408         return ins;
8409 }
8410 #endif
8411
8412 gboolean
8413 mono_arch_print_tree (MonoInst *tree, int arity)
8414 {
8415         return 0;
8416 }
8417
8418 mgreg_t
8419 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8420 {
8421         return ctx->gregs [reg];
8422 }
8423
8424 void
8425 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8426 {
8427         ctx->gregs [reg] = val;
8428 }
8429
8430 gpointer
8431 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8432 {
8433         gpointer *sp, old_value;
8434         char *bp;
8435
8436         /*Load the spvar*/
8437         bp = MONO_CONTEXT_GET_BP (ctx);
8438         sp = *(gpointer*)(bp + clause->exvar_offset);
8439
8440         old_value = *sp;
8441         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8442                 return old_value;
8443
8444         *sp = new_value;
8445
8446         return old_value;
8447 }
8448
8449 /*
8450  * mono_arch_emit_load_aotconst:
8451  *
8452  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8453  * TARGET from the mscorlib GOT in full-aot code.
8454  * On AMD64, the result is placed into R11.
8455  */
8456 guint8*
8457 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8458 {
8459         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8460         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8461
8462         return code;
8463 }
8464
8465 /*
8466  * mono_arch_get_trampolines:
8467  *
8468  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8469  * for AOT.
8470  */
8471 GSList *
8472 mono_arch_get_trampolines (gboolean aot)
8473 {
8474         return mono_amd64_get_exception_trampolines (aot);
8475 }
8476
8477 /* Soft Debug support */
8478 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8479
8480 /*
8481  * mono_arch_set_breakpoint:
8482  *
8483  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8484  * The location should contain code emitted by OP_SEQ_POINT.
8485  */
8486 void
8487 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8488 {
8489         guint8 *code = ip;
8490         guint8 *orig_code = code;
8491
8492         if (ji->from_aot) {
8493                 guint32 native_offset = ip - (guint8*)ji->code_start;
8494                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8495
8496                 g_assert (info->bp_addrs [native_offset] == 0);
8497                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8498         } else {
8499                 /*
8500                  * In production, we will use int3 (has to fix the size in the md
8501                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8502                  * instead.
8503                  */
8504                 g_assert (code [0] == 0x90);
8505                 if (breakpoint_size == 8) {
8506                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8507                 } else {
8508                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8509                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8510                 }
8511
8512                 g_assert (code - orig_code == breakpoint_size);
8513         }
8514 }
8515
8516 /*
8517  * mono_arch_clear_breakpoint:
8518  *
8519  *   Clear the breakpoint at IP.
8520  */
8521 void
8522 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8523 {
8524         guint8 *code = ip;
8525         int i;
8526
8527         if (ji->from_aot) {
8528                 guint32 native_offset = ip - (guint8*)ji->code_start;
8529                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8530
8531                 info->bp_addrs [native_offset] = NULL;
8532         } else {
8533                 for (i = 0; i < breakpoint_size; ++i)
8534                         x86_nop (code);
8535         }
8536 }
8537
8538 gboolean
8539 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8540 {
8541 #ifdef HOST_WIN32
8542         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8543         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8544                 return TRUE;
8545         else
8546                 return FALSE;
8547 #else
8548         siginfo_t* sinfo = (siginfo_t*) info;
8549         /* Sometimes the address is off by 4 */
8550         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8551                 return TRUE;
8552         else
8553                 return FALSE;
8554 #endif
8555 }
8556
8557 /*
8558  * mono_arch_skip_breakpoint:
8559  *
8560  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8561  * we resume, the instruction is not executed again.
8562  */
8563 void
8564 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8565 {
8566         if (ji->from_aot) {
8567                 /* The breakpoint instruction is a call */
8568         } else {
8569                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8570         }
8571 }
8572
8573 /*
8574  * mono_arch_start_single_stepping:
8575  *
8576  *   Start single stepping.
8577  */
8578 void
8579 mono_arch_start_single_stepping (void)
8580 {
8581         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8582         ss_trampoline = mini_get_single_step_trampoline ();
8583 }
8584
8585 /*
8586  * mono_arch_stop_single_stepping:
8587  *
8588  *   Stop single stepping.
8589  */
8590 void
8591 mono_arch_stop_single_stepping (void)
8592 {
8593         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8594         ss_trampoline = NULL;
8595 }
8596
8597 /*
8598  * mono_arch_is_single_step_event:
8599  *
8600  *   Return whenever the machine state in SIGCTX corresponds to a single
8601  * step event.
8602  */
8603 gboolean
8604 mono_arch_is_single_step_event (void *info, void *sigctx)
8605 {
8606 #ifdef HOST_WIN32
8607         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8608         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8609                 return TRUE;
8610         else
8611                 return FALSE;
8612 #else
8613         siginfo_t* sinfo = (siginfo_t*) info;
8614         /* Sometimes the address is off by 4 */
8615         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8616                 return TRUE;
8617         else
8618                 return FALSE;
8619 #endif
8620 }
8621
8622 /*
8623  * mono_arch_skip_single_step:
8624  *
8625  *   Modify CTX so the ip is placed after the single step trigger instruction,
8626  * we resume, the instruction is not executed again.
8627  */
8628 void
8629 mono_arch_skip_single_step (MonoContext *ctx)
8630 {
8631         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8632 }
8633
8634 /*
8635  * mono_arch_create_seq_point_info:
8636  *
8637  *   Return a pointer to a data structure which is used by the sequence
8638  * point implementation in AOTed code.
8639  */
8640 gpointer
8641 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8642 {
8643         SeqPointInfo *info;
8644         MonoJitInfo *ji;
8645
8646         // FIXME: Add a free function
8647
8648         mono_domain_lock (domain);
8649         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8650                                                                 code);
8651         mono_domain_unlock (domain);
8652
8653         if (!info) {
8654                 ji = mono_jit_info_table_find (domain, (char*)code);
8655                 g_assert (ji);
8656
8657                 // FIXME: Optimize the size
8658                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8659
8660                 info->ss_tramp_addr = &ss_trampoline;
8661
8662                 mono_domain_lock (domain);
8663                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8664                                                          code, info);
8665                 mono_domain_unlock (domain);
8666         }
8667
8668         return info;
8669 }
8670
8671 void
8672 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8673 {
8674         ext->lmf.previous_lmf = prev_lmf;
8675         /* Mark that this is a MonoLMFExt */
8676         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8677         ext->lmf.rsp = (gssize)ext;
8678 }
8679
8680 #endif
8681
8682 gboolean
8683 mono_arch_opcode_supported (int opcode)
8684 {
8685         switch (opcode) {
8686         case OP_ATOMIC_ADD_I4:
8687         case OP_ATOMIC_ADD_I8:
8688         case OP_ATOMIC_EXCHANGE_I4:
8689         case OP_ATOMIC_EXCHANGE_I8:
8690         case OP_ATOMIC_CAS_I4:
8691         case OP_ATOMIC_CAS_I8:
8692         case OP_ATOMIC_LOAD_I1:
8693         case OP_ATOMIC_LOAD_I2:
8694         case OP_ATOMIC_LOAD_I4:
8695         case OP_ATOMIC_LOAD_I8:
8696         case OP_ATOMIC_LOAD_U1:
8697         case OP_ATOMIC_LOAD_U2:
8698         case OP_ATOMIC_LOAD_U4:
8699         case OP_ATOMIC_LOAD_U8:
8700         case OP_ATOMIC_LOAD_R4:
8701         case OP_ATOMIC_LOAD_R8:
8702         case OP_ATOMIC_STORE_I1:
8703         case OP_ATOMIC_STORE_I2:
8704         case OP_ATOMIC_STORE_I4:
8705         case OP_ATOMIC_STORE_I8:
8706         case OP_ATOMIC_STORE_U1:
8707         case OP_ATOMIC_STORE_U2:
8708         case OP_ATOMIC_STORE_U4:
8709         case OP_ATOMIC_STORE_U8:
8710         case OP_ATOMIC_STORE_R4:
8711         case OP_ATOMIC_STORE_R8:
8712                 return TRUE;
8713         default:
8714                 return FALSE;
8715         }
8716 }
8717
8718 #if defined(ENABLE_GSHAREDVT)
8719
8720 #include "../../../mono-extensions/mono/mini/mini-amd64-gsharedvt.c"
8721
8722 #endif /* !MONOTOUCH */