2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internal.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-mmap.h>
31 #include <mono/utils/mono-memory-model.h>
32 #include <mono/utils/mono-tls.h>
36 #include "mini-amd64.h"
37 #include "cpu-amd64.h"
38 #include "debugger-agent.h"
41 static gint lmf_tls_offset = -1;
42 static gint lmf_addr_tls_offset = -1;
43 static gint appdomain_tls_offset = -1;
46 static gboolean optimize_for_xen = TRUE;
48 #define optimize_for_xen 0
51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
58 /* Under windows, the calling convention is never stdcall */
59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
64 /* This mutex protects architecture specific caches */
65 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
66 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
67 static CRITICAL_SECTION mini_arch_mutex;
70 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
72 /* Structure used by the sequence points in AOTed code */
74 gpointer ss_trigger_page;
75 gpointer bp_trigger_page;
76 gpointer bp_addrs [MONO_ZERO_LEN_ARRAY];
80 * The code generated for sequence points reads from this location, which is
81 * made read-only when single stepping is enabled.
83 static gpointer ss_trigger_page;
85 /* Enabled breakpoints read from this trigger page */
86 static gpointer bp_trigger_page;
88 /* The size of the breakpoint sequence */
89 static int breakpoint_size;
91 /* The size of the breakpoint instruction causing the actual fault */
92 static int breakpoint_fault_size;
94 /* The size of the single step instruction causing the actual fault */
95 static int single_step_fault_size;
98 /* On Win64 always reserve first 32 bytes for first four arguments */
99 #define ARGS_OFFSET 48
101 #define ARGS_OFFSET 16
103 #define GP_SCRATCH_REG AMD64_R11
106 * AMD64 register usage:
107 * - callee saved registers are used for global register allocation
108 * - %r11 is used for materializing 64 bit constants in opcodes
109 * - the rest is used for local allocation
113 * Floating point comparison results:
123 mono_arch_regname (int reg)
126 case AMD64_RAX: return "%rax";
127 case AMD64_RBX: return "%rbx";
128 case AMD64_RCX: return "%rcx";
129 case AMD64_RDX: return "%rdx";
130 case AMD64_RSP: return "%rsp";
131 case AMD64_RBP: return "%rbp";
132 case AMD64_RDI: return "%rdi";
133 case AMD64_RSI: return "%rsi";
134 case AMD64_R8: return "%r8";
135 case AMD64_R9: return "%r9";
136 case AMD64_R10: return "%r10";
137 case AMD64_R11: return "%r11";
138 case AMD64_R12: return "%r12";
139 case AMD64_R13: return "%r13";
140 case AMD64_R14: return "%r14";
141 case AMD64_R15: return "%r15";
146 static const char * packed_xmmregs [] = {
147 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
148 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
151 static const char * single_xmmregs [] = {
152 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
153 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
157 mono_arch_fregname (int reg)
159 if (reg < AMD64_XMM_NREG)
160 return single_xmmregs [reg];
166 mono_arch_xregname (int reg)
168 if (reg < AMD64_XMM_NREG)
169 return packed_xmmregs [reg];
174 G_GNUC_UNUSED static void
179 G_GNUC_UNUSED static gboolean
182 static int count = 0;
185 if (!getenv ("COUNT"))
188 if (count == atoi (getenv ("COUNT"))) {
192 if (count > atoi (getenv ("COUNT"))) {
203 return debug_count ();
209 static inline gboolean
210 amd64_is_near_call (guint8 *code)
213 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
216 return code [0] == 0xe8;
219 #ifdef __native_client_codegen__
221 /* Keep track of instruction "depth", that is, the level of sub-instruction */
222 /* for any given instruction. For instance, amd64_call_reg resolves to */
223 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
224 /* We only want to force bundle alignment for the top level instruction, */
225 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
226 static MonoNativeTlsKey nacl_instruction_depth;
228 static MonoNativeTlsKey nacl_rex_tag;
229 static MonoNativeTlsKey nacl_legacy_prefix_tag;
232 amd64_nacl_clear_legacy_prefix_tag ()
234 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
238 amd64_nacl_tag_legacy_prefix (guint8* code)
240 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
241 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
245 amd64_nacl_tag_rex (guint8* code)
247 mono_native_tls_set_value (nacl_rex_tag, code);
251 amd64_nacl_get_legacy_prefix_tag ()
253 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
257 amd64_nacl_get_rex_tag ()
259 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
262 /* Increment the instruction "depth" described above */
264 amd64_nacl_instruction_pre ()
266 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
268 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
271 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
272 /* alignment if depth == 0 (top level instruction) */
273 /* IN: start, end pointers to instruction beginning and end */
274 /* OUT: start, end pointers to beginning and end after possible alignment */
275 /* GLOBALS: nacl_instruction_depth defined above */
277 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
279 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
281 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
283 g_assert ( depth >= 0 );
285 uintptr_t space_in_block;
287 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
288 /* if legacy prefix is present, and if it was emitted before */
289 /* the start of the instruction sequence, adjust the start */
290 if (prefix != NULL && prefix < *start) {
291 g_assert (*start - prefix <= 3);/* only 3 are allowed */
294 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
295 instlen = (uintptr_t)(*end - *start);
296 /* Only check for instructions which are less than */
297 /* kNaClAlignment. The only instructions that should ever */
298 /* be that long are call sequences, which are already */
299 /* padded out to align the return to the next bundle. */
300 if (instlen > space_in_block && instlen < kNaClAlignment) {
301 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
302 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
303 const size_t length = (size_t)((*end)-(*start));
304 g_assert (length < MAX_NACL_INST_LENGTH);
306 memcpy (copy_of_instruction, *start, length);
307 *start = mono_arch_nacl_pad (*start, space_in_block);
308 memcpy (*start, copy_of_instruction, length);
309 *end = *start + length;
311 amd64_nacl_clear_legacy_prefix_tag ();
312 amd64_nacl_tag_rex (NULL);
316 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
317 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
318 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
319 /* make sure the upper 32-bits are cleared, and use that register in the */
320 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
322 /* pointer to current instruction stream (in the */
323 /* middle of an instruction, after opcode is emitted) */
324 /* basereg/offset/dreg */
325 /* operands of normal membase address */
327 /* pointer to the end of the membase/memindex emit */
328 /* GLOBALS: nacl_rex_tag */
329 /* position in instruction stream that rex prefix was emitted */
330 /* nacl_legacy_prefix_tag */
331 /* (possibly NULL) position in instruction of legacy x86 prefix */
333 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
335 gint8 true_basereg = basereg;
337 /* Cache these values, they might change */
338 /* as new instructions are emitted below. */
339 guint8* rex_tag = amd64_nacl_get_rex_tag ();
340 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
342 /* 'basereg' is given masked to 0x7 at this point, so check */
343 /* the rex prefix to see if this is an extended register. */
344 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
348 #define X86_LEA_OPCODE (0x8D)
350 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
351 guint8* old_instruction_start;
353 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
354 /* 32-bits of the old base register (new index register) */
356 guint8* buf_ptr = buf;
359 g_assert (rex_tag != NULL);
361 if (IS_REX(*rex_tag)) {
362 /* The old rex.B should be the new rex.X */
363 if (*rex_tag & AMD64_REX_B) {
364 *rex_tag |= AMD64_REX_X;
366 /* Since our new base is %r15 set rex.B */
367 *rex_tag |= AMD64_REX_B;
369 /* Shift the instruction by one byte */
370 /* so we can insert a rex prefix */
371 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
373 /* New rex prefix only needs rex.B for %r15 base */
374 *rex_tag = AMD64_REX(AMD64_REX_B);
377 if (legacy_prefix_tag) {
378 old_instruction_start = legacy_prefix_tag;
380 old_instruction_start = rex_tag;
383 /* Clears the upper 32-bits of the previous base register */
384 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
385 insert_len = buf_ptr - buf;
387 /* Move the old instruction forward to make */
388 /* room for 'mov' stored in 'buf_ptr' */
389 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
391 memcpy (old_instruction_start, buf, insert_len);
393 /* Sandboxed replacement for the normal membase_emit */
394 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
397 /* Normal default behavior, emit membase memory location */
398 x86_membase_emit_body (*code, dreg, basereg, offset);
403 static inline unsigned char*
404 amd64_skip_nops (unsigned char* code)
409 if ( code[0] == 0x90) {
413 if ( code[0] == 0x66 && code[1] == 0x90) {
417 if (code[0] == 0x0f && code[1] == 0x1f
418 && code[2] == 0x00) {
422 if (code[0] == 0x0f && code[1] == 0x1f
423 && code[2] == 0x40 && code[3] == 0x00) {
427 if (code[0] == 0x0f && code[1] == 0x1f
428 && code[2] == 0x44 && code[3] == 0x00
429 && code[4] == 0x00) {
433 if (code[0] == 0x66 && code[1] == 0x0f
434 && code[2] == 0x1f && code[3] == 0x44
435 && code[4] == 0x00 && code[5] == 0x00) {
439 if (code[0] == 0x0f && code[1] == 0x1f
440 && code[2] == 0x80 && code[3] == 0x00
441 && code[4] == 0x00 && code[5] == 0x00
442 && code[6] == 0x00) {
446 if (code[0] == 0x0f && code[1] == 0x1f
447 && code[2] == 0x84 && code[3] == 0x00
448 && code[4] == 0x00 && code[5] == 0x00
449 && code[6] == 0x00 && code[7] == 0x00) {
458 mono_arch_nacl_skip_nops (guint8* code)
460 return amd64_skip_nops(code);
463 #endif /*__native_client_codegen__*/
466 amd64_patch (unsigned char* code, gpointer target)
470 #ifdef __native_client_codegen__
471 code = amd64_skip_nops (code);
473 #if defined(__native_client_codegen__) && defined(__native_client__)
474 if (nacl_is_code_address (code)) {
475 /* For tail calls, code is patched after being installed */
476 /* but not through the normal "patch callsite" method. */
477 unsigned char buf[kNaClAlignment];
478 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
480 memcpy (buf, aligned_code, kNaClAlignment);
481 /* Patch a temp buffer of bundle size, */
482 /* then install to actual location. */
483 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
484 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
488 target = nacl_modify_patch_target (target);
492 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
497 if ((code [0] & 0xf8) == 0xb8) {
498 /* amd64_set_reg_template */
499 *(guint64*)(code + 1) = (guint64)target;
501 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
502 /* mov 0(%rip), %dreg */
503 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
505 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
506 /* call *<OFFSET>(%rip) */
507 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
509 else if (code [0] == 0xe8) {
511 gint64 disp = (guint8*)target - (guint8*)code;
512 g_assert (amd64_is_imm32 (disp));
513 x86_patch (code, (unsigned char*)target);
516 x86_patch (code, (unsigned char*)target);
520 mono_amd64_patch (unsigned char* code, gpointer target)
522 amd64_patch (code, target);
531 ArgValuetypeAddrInIReg,
532 ArgNone /* only in pair_storage */
540 /* Only if storage == ArgValuetypeInReg */
541 ArgStorage pair_storage [2];
551 gboolean need_stack_align;
552 gboolean vtype_retaddr;
553 /* The index of the vret arg in the argument list */
560 #define DEBUG(a) if (cfg->verbose_level > 1) a
565 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
567 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
571 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
573 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
577 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
579 ainfo->offset = *stack_size;
581 if (*gr >= PARAM_REGS) {
582 ainfo->storage = ArgOnStack;
583 /* Since the same stack slot size is used for all arg */
584 /* types, it needs to be big enough to hold them all */
585 (*stack_size) += sizeof(mgreg_t);
588 ainfo->storage = ArgInIReg;
589 ainfo->reg = param_regs [*gr];
595 #define FLOAT_PARAM_REGS 4
597 #define FLOAT_PARAM_REGS 8
601 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
603 ainfo->offset = *stack_size;
605 if (*gr >= FLOAT_PARAM_REGS) {
606 ainfo->storage = ArgOnStack;
607 /* Since the same stack slot size is used for both float */
608 /* types, it needs to be big enough to hold them both */
609 (*stack_size) += sizeof(mgreg_t);
612 /* A double register */
614 ainfo->storage = ArgInDoubleSSEReg;
616 ainfo->storage = ArgInFloatSSEReg;
622 typedef enum ArgumentClass {
630 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
632 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
635 ptype = mini_type_get_underlying_type (NULL, type);
636 switch (ptype->type) {
637 case MONO_TYPE_BOOLEAN:
647 case MONO_TYPE_STRING:
648 case MONO_TYPE_OBJECT:
649 case MONO_TYPE_CLASS:
650 case MONO_TYPE_SZARRAY:
652 case MONO_TYPE_FNPTR:
653 case MONO_TYPE_ARRAY:
656 class2 = ARG_CLASS_INTEGER;
661 class2 = ARG_CLASS_INTEGER;
663 class2 = ARG_CLASS_SSE;
667 case MONO_TYPE_TYPEDBYREF:
668 g_assert_not_reached ();
670 case MONO_TYPE_GENERICINST:
671 if (!mono_type_generic_inst_is_valuetype (ptype)) {
672 class2 = ARG_CLASS_INTEGER;
676 case MONO_TYPE_VALUETYPE: {
677 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
680 for (i = 0; i < info->num_fields; ++i) {
682 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
687 g_assert_not_reached ();
691 if (class1 == class2)
693 else if (class1 == ARG_CLASS_NO_CLASS)
695 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
696 class1 = ARG_CLASS_MEMORY;
697 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
698 class1 = ARG_CLASS_INTEGER;
700 class1 = ARG_CLASS_SSE;
704 #ifdef __native_client_codegen__
705 const guint kNaClAlignment = kNaClAlignmentAMD64;
706 const guint kNaClAlignmentMask = kNaClAlignmentMaskAMD64;
708 /* Default alignment for Native Client is 32-byte. */
709 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
711 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
712 /* Check that alignment doesn't cross an alignment boundary. */
714 mono_arch_nacl_pad(guint8 *code, int pad)
716 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
718 if (pad == 0) return code;
719 /* assertion: alignment cannot cross a block boundary */
720 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
721 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
722 while (pad >= kMaxPadding) {
723 amd64_padding (code, kMaxPadding);
726 if (pad != 0) amd64_padding (code, pad);
732 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
734 guint32 *gr, guint32 *fr, guint32 *stack_size)
736 guint32 size, quad, nquads, i;
737 /* Keep track of the size used in each quad so we can */
738 /* use the right size when copying args/return vars. */
739 guint32 quadsize [2] = {8, 8};
740 ArgumentClass args [2];
741 MonoMarshalType *info = NULL;
743 MonoGenericSharingContext tmp_gsctx;
744 gboolean pass_on_stack = FALSE;
747 * The gsctx currently contains no data, it is only used for checking whenever
748 * open types are allowed, some callers like mono_arch_get_argument_info ()
749 * don't pass it to us, so work around that.
754 klass = mono_class_from_mono_type (type);
755 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
757 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
758 /* We pass and return vtypes of size 8 in a register */
759 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
760 pass_on_stack = TRUE;
764 pass_on_stack = TRUE;
768 /* If this struct can't be split up naturally into 8-byte */
769 /* chunks (registers), pass it on the stack. */
770 if (sig->pinvoke && !pass_on_stack) {
774 info = mono_marshal_load_type_info (klass);
776 for (i = 0; i < info->num_fields; ++i) {
777 field_size = mono_marshal_type_size (info->fields [i].field->type,
778 info->fields [i].mspec,
779 &align, TRUE, klass->unicode);
780 if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
781 pass_on_stack = TRUE;
788 /* Allways pass in memory */
789 ainfo->offset = *stack_size;
790 *stack_size += ALIGN_TO (size, 8);
791 ainfo->storage = ArgOnStack;
796 /* FIXME: Handle structs smaller than 8 bytes */
797 //if ((size % 8) != 0)
806 /* Always pass in 1 or 2 integer registers */
807 args [0] = ARG_CLASS_INTEGER;
808 args [1] = ARG_CLASS_INTEGER;
809 /* Only the simplest cases are supported */
810 if (is_return && nquads != 1) {
811 args [0] = ARG_CLASS_MEMORY;
812 args [1] = ARG_CLASS_MEMORY;
816 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
817 * The X87 and SSEUP stuff is left out since there are no such types in
820 info = mono_marshal_load_type_info (klass);
824 if (info->native_size > 16) {
825 ainfo->offset = *stack_size;
826 *stack_size += ALIGN_TO (info->native_size, 8);
827 ainfo->storage = ArgOnStack;
832 switch (info->native_size) {
833 case 1: case 2: case 4: case 8:
837 ainfo->storage = ArgOnStack;
838 ainfo->offset = *stack_size;
839 *stack_size += ALIGN_TO (info->native_size, 8);
842 ainfo->storage = ArgValuetypeAddrInIReg;
844 if (*gr < PARAM_REGS) {
845 ainfo->pair_storage [0] = ArgInIReg;
846 ainfo->pair_regs [0] = param_regs [*gr];
850 ainfo->pair_storage [0] = ArgOnStack;
851 ainfo->offset = *stack_size;
860 args [0] = ARG_CLASS_NO_CLASS;
861 args [1] = ARG_CLASS_NO_CLASS;
862 for (quad = 0; quad < nquads; ++quad) {
865 ArgumentClass class1;
867 if (info->num_fields == 0)
868 class1 = ARG_CLASS_MEMORY;
870 class1 = ARG_CLASS_NO_CLASS;
871 for (i = 0; i < info->num_fields; ++i) {
872 size = mono_marshal_type_size (info->fields [i].field->type,
873 info->fields [i].mspec,
874 &align, TRUE, klass->unicode);
875 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
876 /* Unaligned field */
880 /* Skip fields in other quad */
881 if ((quad == 0) && (info->fields [i].offset >= 8))
883 if ((quad == 1) && (info->fields [i].offset < 8))
886 /* How far into this quad this data extends.*/
887 /* (8 is size of quad) */
888 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
890 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
892 g_assert (class1 != ARG_CLASS_NO_CLASS);
893 args [quad] = class1;
897 /* Post merger cleanup */
898 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
899 args [0] = args [1] = ARG_CLASS_MEMORY;
901 /* Allocate registers */
906 ainfo->storage = ArgValuetypeInReg;
907 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
908 ainfo->nregs = nquads;
909 for (quad = 0; quad < nquads; ++quad) {
910 switch (args [quad]) {
911 case ARG_CLASS_INTEGER:
912 if (*gr >= PARAM_REGS)
913 args [quad] = ARG_CLASS_MEMORY;
915 ainfo->pair_storage [quad] = ArgInIReg;
917 ainfo->pair_regs [quad] = return_regs [*gr];
919 ainfo->pair_regs [quad] = param_regs [*gr];
924 if (*fr >= FLOAT_PARAM_REGS)
925 args [quad] = ARG_CLASS_MEMORY;
927 if (quadsize[quad] <= 4)
928 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
929 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
930 ainfo->pair_regs [quad] = *fr;
934 case ARG_CLASS_MEMORY:
937 g_assert_not_reached ();
941 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
942 /* Revert possible register assignments */
946 ainfo->offset = *stack_size;
948 *stack_size += ALIGN_TO (info->native_size, 8);
950 *stack_size += nquads * sizeof(mgreg_t);
951 ainfo->storage = ArgOnStack;
959 * Obtain information about a call according to the calling convention.
960 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
961 * Draft Version 0.23" document for more information.
964 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
966 guint32 i, gr, fr, pstart;
968 int n = sig->hasthis + sig->param_count;
969 guint32 stack_size = 0;
971 gboolean is_pinvoke = sig->pinvoke;
974 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
976 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
985 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
986 switch (ret_type->type) {
987 case MONO_TYPE_BOOLEAN:
998 case MONO_TYPE_FNPTR:
999 case MONO_TYPE_CLASS:
1000 case MONO_TYPE_OBJECT:
1001 case MONO_TYPE_SZARRAY:
1002 case MONO_TYPE_ARRAY:
1003 case MONO_TYPE_STRING:
1004 cinfo->ret.storage = ArgInIReg;
1005 cinfo->ret.reg = AMD64_RAX;
1009 cinfo->ret.storage = ArgInIReg;
1010 cinfo->ret.reg = AMD64_RAX;
1013 cinfo->ret.storage = ArgInFloatSSEReg;
1014 cinfo->ret.reg = AMD64_XMM0;
1017 cinfo->ret.storage = ArgInDoubleSSEReg;
1018 cinfo->ret.reg = AMD64_XMM0;
1020 case MONO_TYPE_GENERICINST:
1021 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1022 cinfo->ret.storage = ArgInIReg;
1023 cinfo->ret.reg = AMD64_RAX;
1027 case MONO_TYPE_VALUETYPE: {
1028 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1030 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1031 if (cinfo->ret.storage == ArgOnStack) {
1032 cinfo->vtype_retaddr = TRUE;
1033 /* The caller passes the address where the value is stored */
1037 case MONO_TYPE_TYPEDBYREF:
1038 /* Same as a valuetype with size 24 */
1039 cinfo->vtype_retaddr = TRUE;
1041 case MONO_TYPE_VOID:
1044 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1050 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1051 * the first argument, allowing 'this' to be always passed in the first arg reg.
1052 * Also do this if the first argument is a reference type, since virtual calls
1053 * are sometimes made using calli without sig->hasthis set, like in the delegate
1056 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1058 add_general (&gr, &stack_size, cinfo->args + 0);
1060 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1063 add_general (&gr, &stack_size, &cinfo->ret);
1064 cinfo->vret_arg_index = 1;
1068 add_general (&gr, &stack_size, cinfo->args + 0);
1070 if (cinfo->vtype_retaddr)
1071 add_general (&gr, &stack_size, &cinfo->ret);
1074 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1076 fr = FLOAT_PARAM_REGS;
1078 /* Emit the signature cookie just before the implicit arguments */
1079 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1082 for (i = pstart; i < sig->param_count; ++i) {
1083 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1087 /* The float param registers and other param registers must be the same index on Windows x64.*/
1094 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1095 /* We allways pass the sig cookie on the stack for simplicity */
1097 * Prevent implicit arguments + the sig cookie from being passed
1101 fr = FLOAT_PARAM_REGS;
1103 /* Emit the signature cookie just before the implicit arguments */
1104 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1107 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1108 switch (ptype->type) {
1109 case MONO_TYPE_BOOLEAN:
1112 add_general (&gr, &stack_size, ainfo);
1116 case MONO_TYPE_CHAR:
1117 add_general (&gr, &stack_size, ainfo);
1121 add_general (&gr, &stack_size, ainfo);
1126 case MONO_TYPE_FNPTR:
1127 case MONO_TYPE_CLASS:
1128 case MONO_TYPE_OBJECT:
1129 case MONO_TYPE_STRING:
1130 case MONO_TYPE_SZARRAY:
1131 case MONO_TYPE_ARRAY:
1132 add_general (&gr, &stack_size, ainfo);
1134 case MONO_TYPE_GENERICINST:
1135 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1136 add_general (&gr, &stack_size, ainfo);
1140 case MONO_TYPE_VALUETYPE:
1141 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1143 case MONO_TYPE_TYPEDBYREF:
1145 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1147 stack_size += sizeof (MonoTypedRef);
1148 ainfo->storage = ArgOnStack;
1153 add_general (&gr, &stack_size, ainfo);
1156 add_float (&fr, &stack_size, ainfo, FALSE);
1159 add_float (&fr, &stack_size, ainfo, TRUE);
1162 g_assert_not_reached ();
1166 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1168 fr = FLOAT_PARAM_REGS;
1170 /* Emit the signature cookie just before the implicit arguments */
1171 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1175 // There always is 32 bytes reserved on the stack when calling on Winx64
1179 #ifndef MONO_AMD64_NO_PUSHES
1180 if (stack_size & 0x8) {
1181 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1182 cinfo->need_stack_align = TRUE;
1187 cinfo->stack_usage = stack_size;
1188 cinfo->reg_usage = gr;
1189 cinfo->freg_usage = fr;
1194 * mono_arch_get_argument_info:
1195 * @csig: a method signature
1196 * @param_count: the number of parameters to consider
1197 * @arg_info: an array to store the result infos
1199 * Gathers information on parameters such as size, alignment and
1200 * padding. arg_info should be large enought to hold param_count + 1 entries.
1202 * Returns the size of the argument area on the stack.
1205 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1208 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1209 guint32 args_size = cinfo->stack_usage;
1211 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1212 if (csig->hasthis) {
1213 arg_info [0].offset = 0;
1216 for (k = 0; k < param_count; k++) {
1217 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1219 arg_info [k + 1].size = 0;
1228 mono_amd64_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1233 c1 = get_call_info (NULL, NULL, caller_sig);
1234 c2 = get_call_info (NULL, NULL, callee_sig);
1235 res = c1->stack_usage >= c2->stack_usage;
1236 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
1237 /* An address on the callee's stack is passed as the first argument */
1247 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
1249 #if defined(MONO_CROSS_COMPILE)
1253 __asm__ __volatile__ ("cpuid"
1254 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
1269 * Initialize the cpu to execute managed code.
1272 mono_arch_cpu_init (void)
1277 /* spec compliance requires running with double precision */
1278 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1279 fpcw &= ~X86_FPCW_PRECC_MASK;
1280 fpcw |= X86_FPCW_PREC_DOUBLE;
1281 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1282 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1284 /* TODO: This is crashing on Win64 right now.
1285 * _control87 (_PC_53, MCW_PC);
1291 * Initialize architecture specific code.
1294 mono_arch_init (void)
1298 InitializeCriticalSection (&mini_arch_mutex);
1299 #if defined(__native_client_codegen__)
1300 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1301 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1302 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1303 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1306 #ifdef MONO_ARCH_NOMAP32BIT
1307 flags = MONO_MMAP_READ;
1308 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1309 breakpoint_size = 13;
1310 breakpoint_fault_size = 3;
1312 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1313 /* amd64_mov_reg_mem () */
1314 breakpoint_size = 8;
1315 breakpoint_fault_size = 8;
1318 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1319 single_step_fault_size = 4;
1321 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1322 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1323 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1325 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1326 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1327 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1331 * Cleanup architecture specific code.
1334 mono_arch_cleanup (void)
1336 DeleteCriticalSection (&mini_arch_mutex);
1337 #if defined(__native_client_codegen__)
1338 mono_native_tls_free (nacl_instruction_depth);
1339 mono_native_tls_free (nacl_rex_tag);
1340 mono_native_tls_free (nacl_legacy_prefix_tag);
1345 * This function returns the optimizations supported on this cpu.
1348 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
1350 int eax, ebx, ecx, edx;
1354 /* Feature Flags function, flags returned in EDX. */
1355 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1356 if (edx & (1 << 15)) {
1357 opts |= MONO_OPT_CMOV;
1359 opts |= MONO_OPT_FCMOV;
1361 *exclude_mask |= MONO_OPT_FCMOV;
1363 *exclude_mask |= MONO_OPT_CMOV;
1370 * This function test for all SSE functions supported.
1372 * Returns a bitmask corresponding to all supported versions.
1376 mono_arch_cpu_enumerate_simd_versions (void)
1378 int eax, ebx, ecx, edx;
1379 guint32 sse_opts = 0;
1381 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1382 if (edx & (1 << 25))
1383 sse_opts |= SIMD_VERSION_SSE1;
1384 if (edx & (1 << 26))
1385 sse_opts |= SIMD_VERSION_SSE2;
1387 sse_opts |= SIMD_VERSION_SSE3;
1389 sse_opts |= SIMD_VERSION_SSSE3;
1390 if (ecx & (1 << 19))
1391 sse_opts |= SIMD_VERSION_SSE41;
1392 if (ecx & (1 << 20))
1393 sse_opts |= SIMD_VERSION_SSE42;
1396 /* Yes, all this needs to be done to check for sse4a.
1397 See: "Amd: CPUID Specification"
1399 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1400 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1401 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1402 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1404 sse_opts |= SIMD_VERSION_SSE4a;
1414 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1419 for (i = 0; i < cfg->num_varinfo; i++) {
1420 MonoInst *ins = cfg->varinfo [i];
1421 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1424 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1427 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1428 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1431 if (mono_is_regsize_var (ins->inst_vtype)) {
1432 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1433 g_assert (i == vmv->idx);
1434 vars = g_list_prepend (vars, vmv);
1438 vars = mono_varlist_sort (cfg, vars, 0);
1444 * mono_arch_compute_omit_fp:
1446 * Determine whenever the frame pointer can be eliminated.
1449 mono_arch_compute_omit_fp (MonoCompile *cfg)
1451 MonoMethodSignature *sig;
1452 MonoMethodHeader *header;
1456 if (cfg->arch.omit_fp_computed)
1459 header = cfg->header;
1461 sig = mono_method_signature (cfg->method);
1463 if (!cfg->arch.cinfo)
1464 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1465 cinfo = cfg->arch.cinfo;
1468 * FIXME: Remove some of the restrictions.
1470 cfg->arch.omit_fp = TRUE;
1471 cfg->arch.omit_fp_computed = TRUE;
1473 #ifdef __native_client_codegen__
1474 /* NaCl modules may not change the value of RBP, so it cannot be */
1475 /* used as a normal register, but it can be used as a frame pointer*/
1476 cfg->disable_omit_fp = TRUE;
1477 cfg->arch.omit_fp = FALSE;
1480 if (cfg->disable_omit_fp)
1481 cfg->arch.omit_fp = FALSE;
1483 if (!debug_omit_fp ())
1484 cfg->arch.omit_fp = FALSE;
1486 if (cfg->method->save_lmf)
1487 cfg->arch.omit_fp = FALSE;
1489 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1490 cfg->arch.omit_fp = FALSE;
1491 if (header->num_clauses)
1492 cfg->arch.omit_fp = FALSE;
1493 if (cfg->param_area)
1494 cfg->arch.omit_fp = FALSE;
1495 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1496 cfg->arch.omit_fp = FALSE;
1497 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1498 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1499 cfg->arch.omit_fp = FALSE;
1500 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1501 ArgInfo *ainfo = &cinfo->args [i];
1503 if (ainfo->storage == ArgOnStack) {
1505 * The stack offset can only be determined when the frame
1508 cfg->arch.omit_fp = FALSE;
1513 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1514 MonoInst *ins = cfg->varinfo [i];
1517 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1522 mono_arch_get_global_int_regs (MonoCompile *cfg)
1526 mono_arch_compute_omit_fp (cfg);
1528 if (cfg->globalra) {
1529 if (cfg->arch.omit_fp)
1530 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1532 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1533 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1534 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1535 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1536 #ifndef __native_client_codegen__
1537 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1540 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1541 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1542 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1543 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1544 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1545 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1546 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1547 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1549 if (cfg->arch.omit_fp)
1550 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1552 /* We use the callee saved registers for global allocation */
1553 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1554 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1555 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1556 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1557 #ifndef __native_client_codegen__
1558 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1561 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1562 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1570 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1575 /* All XMM registers */
1576 for (i = 0; i < 16; ++i)
1577 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1583 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1585 static GList *r = NULL;
1590 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1591 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1592 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1593 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1594 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1595 #ifndef __native_client_codegen__
1596 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1599 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1600 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1601 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1602 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1603 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1604 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1605 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1606 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1608 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1615 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1618 static GList *r = NULL;
1623 for (i = 0; i < AMD64_XMM_NREG; ++i)
1624 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1626 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1633 * mono_arch_regalloc_cost:
1635 * Return the cost, in number of memory references, of the action of
1636 * allocating the variable VMV into a register during global register
1640 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1642 MonoInst *ins = cfg->varinfo [vmv->idx];
1644 if (cfg->method->save_lmf)
1645 /* The register is already saved */
1646 /* substract 1 for the invisible store in the prolog */
1647 return (ins->opcode == OP_ARG) ? 0 : 1;
1650 return (ins->opcode == OP_ARG) ? 1 : 2;
1654 * mono_arch_fill_argument_info:
1656 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1660 mono_arch_fill_argument_info (MonoCompile *cfg)
1662 MonoMethodSignature *sig;
1663 MonoMethodHeader *header;
1668 header = cfg->header;
1670 sig = mono_method_signature (cfg->method);
1672 cinfo = cfg->arch.cinfo;
1675 * Contrary to mono_arch_allocate_vars (), the information should describe
1676 * where the arguments are at the beginning of the method, not where they can be
1677 * accessed during the execution of the method. The later makes no sense for the
1678 * global register allocator, since a variable can be in more than one location.
1680 if (sig->ret->type != MONO_TYPE_VOID) {
1681 switch (cinfo->ret.storage) {
1683 case ArgInFloatSSEReg:
1684 case ArgInDoubleSSEReg:
1685 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1686 cfg->vret_addr->opcode = OP_REGVAR;
1687 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1690 cfg->ret->opcode = OP_REGVAR;
1691 cfg->ret->inst_c0 = cinfo->ret.reg;
1694 case ArgValuetypeInReg:
1695 cfg->ret->opcode = OP_REGOFFSET;
1696 cfg->ret->inst_basereg = -1;
1697 cfg->ret->inst_offset = -1;
1700 g_assert_not_reached ();
1704 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1705 ArgInfo *ainfo = &cinfo->args [i];
1708 ins = cfg->args [i];
1710 if (sig->hasthis && (i == 0))
1711 arg_type = &mono_defaults.object_class->byval_arg;
1713 arg_type = sig->params [i - sig->hasthis];
1715 switch (ainfo->storage) {
1717 case ArgInFloatSSEReg:
1718 case ArgInDoubleSSEReg:
1719 ins->opcode = OP_REGVAR;
1720 ins->inst_c0 = ainfo->reg;
1723 ins->opcode = OP_REGOFFSET;
1724 ins->inst_basereg = -1;
1725 ins->inst_offset = -1;
1727 case ArgValuetypeInReg:
1729 ins->opcode = OP_NOP;
1732 g_assert_not_reached ();
1738 mono_arch_allocate_vars (MonoCompile *cfg)
1740 MonoMethodSignature *sig;
1741 MonoMethodHeader *header;
1744 guint32 locals_stack_size, locals_stack_align;
1748 header = cfg->header;
1750 sig = mono_method_signature (cfg->method);
1752 cinfo = cfg->arch.cinfo;
1754 mono_arch_compute_omit_fp (cfg);
1757 * We use the ABI calling conventions for managed code as well.
1758 * Exception: valuetypes are only sometimes passed or returned in registers.
1762 * The stack looks like this:
1763 * <incoming arguments passed on the stack>
1765 * <lmf/caller saved registers>
1768 * <localloc area> -> grows dynamically
1772 if (cfg->arch.omit_fp) {
1773 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1774 cfg->frame_reg = AMD64_RSP;
1777 /* Locals are allocated backwards from %fp */
1778 cfg->frame_reg = AMD64_RBP;
1782 if (cfg->method->save_lmf) {
1783 /* The LMF var is allocated normally */
1785 if (cfg->arch.omit_fp)
1786 cfg->arch.reg_save_area_offset = offset;
1787 /* Reserve space for caller saved registers */
1788 for (i = 0; i < AMD64_NREG; ++i)
1789 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1790 offset += sizeof(mgreg_t);
1794 if (sig->ret->type != MONO_TYPE_VOID) {
1795 switch (cinfo->ret.storage) {
1797 case ArgInFloatSSEReg:
1798 case ArgInDoubleSSEReg:
1799 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1800 if (cfg->globalra) {
1801 cfg->vret_addr->opcode = OP_REGVAR;
1802 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1804 /* The register is volatile */
1805 cfg->vret_addr->opcode = OP_REGOFFSET;
1806 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1807 if (cfg->arch.omit_fp) {
1808 cfg->vret_addr->inst_offset = offset;
1812 cfg->vret_addr->inst_offset = -offset;
1814 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1815 printf ("vret_addr =");
1816 mono_print_ins (cfg->vret_addr);
1821 cfg->ret->opcode = OP_REGVAR;
1822 cfg->ret->inst_c0 = cinfo->ret.reg;
1825 case ArgValuetypeInReg:
1826 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1827 cfg->ret->opcode = OP_REGOFFSET;
1828 cfg->ret->inst_basereg = cfg->frame_reg;
1829 if (cfg->arch.omit_fp) {
1830 cfg->ret->inst_offset = offset;
1831 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1833 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1834 cfg->ret->inst_offset = - offset;
1838 g_assert_not_reached ();
1841 cfg->ret->dreg = cfg->ret->inst_c0;
1844 /* Allocate locals */
1845 if (!cfg->globalra) {
1846 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1847 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1848 char *mname = mono_method_full_name (cfg->method, TRUE);
1849 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1850 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1855 if (locals_stack_align) {
1856 offset += (locals_stack_align - 1);
1857 offset &= ~(locals_stack_align - 1);
1859 if (cfg->arch.omit_fp) {
1860 cfg->locals_min_stack_offset = offset;
1861 cfg->locals_max_stack_offset = offset + locals_stack_size;
1863 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1864 cfg->locals_max_stack_offset = - offset;
1867 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1868 if (offsets [i] != -1) {
1869 MonoInst *ins = cfg->varinfo [i];
1870 ins->opcode = OP_REGOFFSET;
1871 ins->inst_basereg = cfg->frame_reg;
1872 if (cfg->arch.omit_fp)
1873 ins->inst_offset = (offset + offsets [i]);
1875 ins->inst_offset = - (offset + offsets [i]);
1876 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1879 offset += locals_stack_size;
1882 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1883 g_assert (!cfg->arch.omit_fp);
1884 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1885 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1888 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1889 ins = cfg->args [i];
1890 if (ins->opcode != OP_REGVAR) {
1891 ArgInfo *ainfo = &cinfo->args [i];
1892 gboolean inreg = TRUE;
1895 if (sig->hasthis && (i == 0))
1896 arg_type = &mono_defaults.object_class->byval_arg;
1898 arg_type = sig->params [i - sig->hasthis];
1900 if (cfg->globalra) {
1901 /* The new allocator needs info about the original locations of the arguments */
1902 switch (ainfo->storage) {
1904 case ArgInFloatSSEReg:
1905 case ArgInDoubleSSEReg:
1906 ins->opcode = OP_REGVAR;
1907 ins->inst_c0 = ainfo->reg;
1910 g_assert (!cfg->arch.omit_fp);
1911 ins->opcode = OP_REGOFFSET;
1912 ins->inst_basereg = cfg->frame_reg;
1913 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1915 case ArgValuetypeInReg:
1916 ins->opcode = OP_REGOFFSET;
1917 ins->inst_basereg = cfg->frame_reg;
1918 /* These arguments are saved to the stack in the prolog */
1919 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1920 if (cfg->arch.omit_fp) {
1921 ins->inst_offset = offset;
1922 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1924 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1925 ins->inst_offset = - offset;
1929 g_assert_not_reached ();
1935 /* FIXME: Allocate volatile arguments to registers */
1936 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1940 * Under AMD64, all registers used to pass arguments to functions
1941 * are volatile across calls.
1942 * FIXME: Optimize this.
1944 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1947 ins->opcode = OP_REGOFFSET;
1949 switch (ainfo->storage) {
1951 case ArgInFloatSSEReg:
1952 case ArgInDoubleSSEReg:
1954 ins->opcode = OP_REGVAR;
1955 ins->dreg = ainfo->reg;
1959 g_assert (!cfg->arch.omit_fp);
1960 ins->opcode = OP_REGOFFSET;
1961 ins->inst_basereg = cfg->frame_reg;
1962 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1964 case ArgValuetypeInReg:
1966 case ArgValuetypeAddrInIReg: {
1968 g_assert (!cfg->arch.omit_fp);
1970 MONO_INST_NEW (cfg, indir, 0);
1971 indir->opcode = OP_REGOFFSET;
1972 if (ainfo->pair_storage [0] == ArgInIReg) {
1973 indir->inst_basereg = cfg->frame_reg;
1974 offset = ALIGN_TO (offset, sizeof (gpointer));
1975 offset += (sizeof (gpointer));
1976 indir->inst_offset = - offset;
1979 indir->inst_basereg = cfg->frame_reg;
1980 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1983 ins->opcode = OP_VTARG_ADDR;
1984 ins->inst_left = indir;
1992 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1993 ins->opcode = OP_REGOFFSET;
1994 ins->inst_basereg = cfg->frame_reg;
1995 /* These arguments are saved to the stack in the prolog */
1996 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1997 if (cfg->arch.omit_fp) {
1998 ins->inst_offset = offset;
1999 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2000 // Arguments are yet supported by the stack map creation code
2001 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2003 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2004 ins->inst_offset = - offset;
2005 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2011 cfg->stack_offset = offset;
2015 mono_arch_create_vars (MonoCompile *cfg)
2017 MonoMethodSignature *sig;
2020 sig = mono_method_signature (cfg->method);
2022 if (!cfg->arch.cinfo)
2023 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2024 cinfo = cfg->arch.cinfo;
2026 if (cinfo->ret.storage == ArgValuetypeInReg)
2027 cfg->ret_var_is_local = TRUE;
2029 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
2030 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2031 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2032 printf ("vret_addr = ");
2033 mono_print_ins (cfg->vret_addr);
2037 if (cfg->gen_seq_points) {
2040 if (cfg->compile_aot) {
2041 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2042 ins->flags |= MONO_INST_VOLATILE;
2043 cfg->arch.seq_point_info_var = ins;
2046 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2047 ins->flags |= MONO_INST_VOLATILE;
2048 cfg->arch.ss_trigger_page_var = ins;
2051 #ifdef MONO_AMD64_NO_PUSHES
2053 * When this is set, we pass arguments on the stack by moves, and by allocating
2054 * a bigger stack frame, instead of pushes.
2055 * Pushes complicate exception handling because the arguments on the stack have
2056 * to be popped each time a frame is unwound. They also make fp elimination
2058 * FIXME: This doesn't work inside filter/finally clauses, since those execute
2059 * on a new frame which doesn't include a param area.
2061 cfg->arch.no_pushes = TRUE;
2064 if (cfg->method->save_lmf) {
2065 MonoInst *lmf_var = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2066 lmf_var->flags |= MONO_INST_VOLATILE;
2067 lmf_var->flags |= MONO_INST_LMF;
2068 cfg->arch.lmf_var = lmf_var;
2071 #ifndef MONO_AMD64_NO_PUSHES
2072 cfg->arch_eh_jit_info = 1;
2077 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2083 MONO_INST_NEW (cfg, ins, OP_MOVE);
2084 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2085 ins->sreg1 = tree->dreg;
2086 MONO_ADD_INS (cfg->cbb, ins);
2087 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2089 case ArgInFloatSSEReg:
2090 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2091 ins->dreg = mono_alloc_freg (cfg);
2092 ins->sreg1 = tree->dreg;
2093 MONO_ADD_INS (cfg->cbb, ins);
2095 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2097 case ArgInDoubleSSEReg:
2098 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2099 ins->dreg = mono_alloc_freg (cfg);
2100 ins->sreg1 = tree->dreg;
2101 MONO_ADD_INS (cfg->cbb, ins);
2103 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2107 g_assert_not_reached ();
2112 arg_storage_to_load_membase (ArgStorage storage)
2116 #if defined(__mono_ilp32__)
2117 return OP_LOADI8_MEMBASE;
2119 return OP_LOAD_MEMBASE;
2121 case ArgInDoubleSSEReg:
2122 return OP_LOADR8_MEMBASE;
2123 case ArgInFloatSSEReg:
2124 return OP_LOADR4_MEMBASE;
2126 g_assert_not_reached ();
2133 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2136 MonoMethodSignature *tmp_sig;
2139 if (call->tail_call)
2142 /* FIXME: Add support for signature tokens to AOT */
2143 cfg->disable_aot = TRUE;
2145 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2148 * mono_ArgIterator_Setup assumes the signature cookie is
2149 * passed first and all the arguments which were before it are
2150 * passed on the stack after the signature. So compensate by
2151 * passing a different signature.
2153 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2154 tmp_sig->param_count -= call->signature->sentinelpos;
2155 tmp_sig->sentinelpos = 0;
2156 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2158 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
2159 sig_arg->dreg = mono_alloc_ireg (cfg);
2160 sig_arg->inst_p0 = tmp_sig;
2161 MONO_ADD_INS (cfg->cbb, sig_arg);
2163 if (cfg->arch.no_pushes) {
2164 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
2166 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2167 arg->sreg1 = sig_arg->dreg;
2168 MONO_ADD_INS (cfg->cbb, arg);
2172 static inline LLVMArgStorage
2173 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2177 return LLVMArgInIReg;
2181 g_assert_not_reached ();
2188 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2194 LLVMCallInfo *linfo;
2197 n = sig->param_count + sig->hasthis;
2199 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2201 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2204 * LLVM always uses the native ABI while we use our own ABI, the
2205 * only difference is the handling of vtypes:
2206 * - we only pass/receive them in registers in some cases, and only
2207 * in 1 or 2 integer registers.
2209 if (cinfo->ret.storage == ArgValuetypeInReg) {
2211 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2212 cfg->disable_llvm = TRUE;
2216 linfo->ret.storage = LLVMArgVtypeInReg;
2217 for (j = 0; j < 2; ++j)
2218 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2221 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
2222 /* Vtype returned using a hidden argument */
2223 linfo->ret.storage = LLVMArgVtypeRetAddr;
2224 linfo->vret_arg_index = cinfo->vret_arg_index;
2227 for (i = 0; i < n; ++i) {
2228 ainfo = cinfo->args + i;
2230 if (i >= sig->hasthis)
2231 t = sig->params [i - sig->hasthis];
2233 t = &mono_defaults.int_class->byval_arg;
2235 linfo->args [i].storage = LLVMArgNone;
2237 switch (ainfo->storage) {
2239 linfo->args [i].storage = LLVMArgInIReg;
2241 case ArgInDoubleSSEReg:
2242 case ArgInFloatSSEReg:
2243 linfo->args [i].storage = LLVMArgInFPReg;
2246 if (MONO_TYPE_ISSTRUCT (t)) {
2247 linfo->args [i].storage = LLVMArgVtypeByVal;
2249 linfo->args [i].storage = LLVMArgInIReg;
2251 if (t->type == MONO_TYPE_R4)
2252 linfo->args [i].storage = LLVMArgInFPReg;
2253 else if (t->type == MONO_TYPE_R8)
2254 linfo->args [i].storage = LLVMArgInFPReg;
2258 case ArgValuetypeInReg:
2260 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2261 cfg->disable_llvm = TRUE;
2265 linfo->args [i].storage = LLVMArgVtypeInReg;
2266 for (j = 0; j < 2; ++j)
2267 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2270 cfg->exception_message = g_strdup ("ainfo->storage");
2271 cfg->disable_llvm = TRUE;
2281 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2284 MonoMethodSignature *sig;
2285 int i, n, stack_size;
2291 sig = call->signature;
2292 n = sig->param_count + sig->hasthis;
2294 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2296 if (COMPILE_LLVM (cfg)) {
2297 /* We shouldn't be called in the llvm case */
2298 cfg->disable_llvm = TRUE;
2302 if (cinfo->need_stack_align) {
2303 if (!cfg->arch.no_pushes)
2304 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2308 * Emit all arguments which are passed on the stack to prevent register
2309 * allocation problems.
2311 if (cfg->arch.no_pushes) {
2312 for (i = 0; i < n; ++i) {
2314 ainfo = cinfo->args + i;
2316 in = call->args [i];
2318 if (sig->hasthis && i == 0)
2319 t = &mono_defaults.object_class->byval_arg;
2321 t = sig->params [i - sig->hasthis];
2323 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2325 if (t->type == MONO_TYPE_R4)
2326 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2327 else if (t->type == MONO_TYPE_R8)
2328 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2330 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2332 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2334 if (cfg->compute_gc_maps) {
2337 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2344 * Emit all parameters passed in registers in non-reverse order for better readability
2345 * and to help the optimization in emit_prolog ().
2347 for (i = 0; i < n; ++i) {
2348 ainfo = cinfo->args + i;
2350 in = call->args [i];
2352 if (ainfo->storage == ArgInIReg)
2353 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2356 for (i = n - 1; i >= 0; --i) {
2357 ainfo = cinfo->args + i;
2359 in = call->args [i];
2361 switch (ainfo->storage) {
2365 case ArgInFloatSSEReg:
2366 case ArgInDoubleSSEReg:
2367 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2370 case ArgValuetypeInReg:
2371 case ArgValuetypeAddrInIReg:
2372 if (ainfo->storage == ArgOnStack && call->tail_call) {
2373 MonoInst *call_inst = (MonoInst*)call;
2374 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2375 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2376 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2380 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2381 size = sizeof (MonoTypedRef);
2382 align = sizeof (gpointer);
2386 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2389 * Other backends use mono_type_stack_size (), but that
2390 * aligns the size to 8, which is larger than the size of
2391 * the source, leading to reads of invalid memory if the
2392 * source is at the end of address space.
2394 size = mono_class_value_size (in->klass, &align);
2397 g_assert (in->klass);
2399 if (ainfo->storage == ArgOnStack && size >= 10000) {
2400 /* Avoid asserts in emit_memcpy () */
2401 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2402 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2403 /* Continue normally */
2407 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2408 arg->sreg1 = in->dreg;
2409 arg->klass = in->klass;
2410 arg->backend.size = size;
2411 arg->inst_p0 = call;
2412 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2413 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2415 MONO_ADD_INS (cfg->cbb, arg);
2418 if (cfg->arch.no_pushes) {
2421 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2422 arg->sreg1 = in->dreg;
2423 if (!sig->params [i - sig->hasthis]->byref) {
2424 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2425 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2426 arg->opcode = OP_STORER4_MEMBASE_REG;
2427 arg->inst_destbasereg = X86_ESP;
2428 arg->inst_offset = 0;
2429 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2430 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2431 arg->opcode = OP_STORER8_MEMBASE_REG;
2432 arg->inst_destbasereg = X86_ESP;
2433 arg->inst_offset = 0;
2436 MONO_ADD_INS (cfg->cbb, arg);
2441 g_assert_not_reached ();
2444 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2445 /* Emit the signature cookie just before the implicit arguments */
2446 emit_sig_cookie (cfg, call, cinfo);
2449 /* Handle the case where there are no implicit arguments */
2450 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2451 emit_sig_cookie (cfg, call, cinfo);
2453 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2456 if (cinfo->ret.storage == ArgValuetypeInReg) {
2457 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2459 * Tell the JIT to use a more efficient calling convention: call using
2460 * OP_CALL, compute the result location after the call, and save the
2463 call->vret_in_reg = TRUE;
2465 * Nullify the instruction computing the vret addr to enable
2466 * future optimizations.
2469 NULLIFY_INS (call->vret_var);
2471 if (call->tail_call)
2474 * The valuetype is in RAX:RDX after the call, need to be copied to
2475 * the stack. Push the address here, so the call instruction can
2478 if (!cfg->arch.vret_addr_loc) {
2479 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2480 /* Prevent it from being register allocated or optimized away */
2481 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2484 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2488 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2489 vtarg->sreg1 = call->vret_var->dreg;
2490 vtarg->dreg = mono_alloc_preg (cfg);
2491 MONO_ADD_INS (cfg->cbb, vtarg);
2493 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2498 if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2499 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2503 if (cfg->method->save_lmf) {
2504 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2505 MONO_ADD_INS (cfg->cbb, arg);
2508 call->stack_usage = cinfo->stack_usage;
2512 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2515 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2516 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2517 int size = ins->backend.size;
2519 if (ainfo->storage == ArgValuetypeInReg) {
2523 for (part = 0; part < 2; ++part) {
2524 if (ainfo->pair_storage [part] == ArgNone)
2527 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2528 load->inst_basereg = src->dreg;
2529 load->inst_offset = part * sizeof(mgreg_t);
2531 switch (ainfo->pair_storage [part]) {
2533 load->dreg = mono_alloc_ireg (cfg);
2535 case ArgInDoubleSSEReg:
2536 case ArgInFloatSSEReg:
2537 load->dreg = mono_alloc_freg (cfg);
2540 g_assert_not_reached ();
2542 MONO_ADD_INS (cfg->cbb, load);
2544 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2546 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2547 MonoInst *vtaddr, *load;
2548 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2550 g_assert (!cfg->arch.no_pushes);
2552 MONO_INST_NEW (cfg, load, OP_LDADDR);
2553 load->inst_p0 = vtaddr;
2554 vtaddr->flags |= MONO_INST_INDIRECT;
2555 load->type = STACK_MP;
2556 load->klass = vtaddr->klass;
2557 load->dreg = mono_alloc_ireg (cfg);
2558 MONO_ADD_INS (cfg->cbb, load);
2559 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2561 if (ainfo->pair_storage [0] == ArgInIReg) {
2562 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2563 arg->dreg = mono_alloc_ireg (cfg);
2564 arg->sreg1 = load->dreg;
2566 MONO_ADD_INS (cfg->cbb, arg);
2567 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2569 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2570 arg->sreg1 = load->dreg;
2571 MONO_ADD_INS (cfg->cbb, arg);
2575 if (cfg->arch.no_pushes) {
2576 int dreg = mono_alloc_ireg (cfg);
2578 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2579 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2581 /* Can't use this for < 8 since it does an 8 byte memory load */
2582 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2583 arg->inst_basereg = src->dreg;
2584 arg->inst_offset = 0;
2585 MONO_ADD_INS (cfg->cbb, arg);
2587 } else if (size <= 40) {
2588 if (cfg->arch.no_pushes) {
2589 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2591 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2592 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2595 if (cfg->arch.no_pushes) {
2596 // FIXME: Code growth
2597 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2599 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2600 arg->inst_basereg = src->dreg;
2601 arg->inst_offset = 0;
2602 arg->inst_imm = size;
2603 MONO_ADD_INS (cfg->cbb, arg);
2607 if (cfg->compute_gc_maps) {
2609 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2615 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2617 MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2619 if (ret->type == MONO_TYPE_R4) {
2620 if (COMPILE_LLVM (cfg))
2621 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2623 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2625 } else if (ret->type == MONO_TYPE_R8) {
2626 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2630 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2633 #endif /* DISABLE_JIT */
2635 #define EMIT_COND_BRANCH(ins,cond,sign) \
2636 if (ins->inst_true_bb->native_offset) { \
2637 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2639 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2640 if ((cfg->opt & MONO_OPT_BRANCH) && \
2641 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2642 x86_branch8 (code, cond, 0, sign); \
2644 x86_branch32 (code, cond, 0, sign); \
2648 MonoMethodSignature *sig;
2653 mgreg_t regs [PARAM_REGS];
2659 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2667 switch (cinfo->ret.storage) {
2671 case ArgValuetypeInReg: {
2672 ArgInfo *ainfo = &cinfo->ret;
2674 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2676 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2684 for (i = 0; i < cinfo->nargs; ++i) {
2685 ArgInfo *ainfo = &cinfo->args [i];
2686 switch (ainfo->storage) {
2689 case ArgValuetypeInReg:
2690 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2692 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2704 * mono_arch_dyn_call_prepare:
2706 * Return a pointer to an arch-specific structure which contains information
2707 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2708 * supported for SIG.
2709 * This function is equivalent to ffi_prep_cif in libffi.
2712 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2714 ArchDynCallInfo *info;
2717 cinfo = get_call_info (NULL, NULL, sig);
2719 if (!dyn_call_supported (sig, cinfo)) {
2724 info = g_new0 (ArchDynCallInfo, 1);
2725 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2727 info->cinfo = cinfo;
2729 return (MonoDynCallInfo*)info;
2733 * mono_arch_dyn_call_free:
2735 * Free a MonoDynCallInfo structure.
2738 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2740 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2742 g_free (ainfo->cinfo);
2746 #if !defined(__native_client__)
2747 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2748 #define GREG_TO_PTR(greg) (gpointer)(greg)
2750 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2751 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2752 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2756 * mono_arch_get_start_dyn_call:
2758 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2759 * store the result into BUF.
2760 * ARGS should be an array of pointers pointing to the arguments.
2761 * RET should point to a memory buffer large enought to hold the result of the
2763 * This function should be as fast as possible, any work which does not depend
2764 * on the actual values of the arguments should be done in
2765 * mono_arch_dyn_call_prepare ().
2766 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2770 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2772 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2773 DynCallArgs *p = (DynCallArgs*)buf;
2774 int arg_index, greg, i, pindex;
2775 MonoMethodSignature *sig = dinfo->sig;
2777 g_assert (buf_len >= sizeof (DynCallArgs));
2786 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2787 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2792 if (dinfo->cinfo->vtype_retaddr)
2793 p->regs [greg ++] = PTR_TO_GREG(ret);
2795 for (i = pindex; i < sig->param_count; i++) {
2796 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2797 gpointer *arg = args [arg_index ++];
2800 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2805 case MONO_TYPE_STRING:
2806 case MONO_TYPE_CLASS:
2807 case MONO_TYPE_ARRAY:
2808 case MONO_TYPE_SZARRAY:
2809 case MONO_TYPE_OBJECT:
2813 #if !defined(__mono_ilp32__)
2817 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2818 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2820 #if defined(__mono_ilp32__)
2823 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2824 p->regs [greg ++] = *(guint64*)(arg);
2827 case MONO_TYPE_BOOLEAN:
2829 p->regs [greg ++] = *(guint8*)(arg);
2832 p->regs [greg ++] = *(gint8*)(arg);
2835 p->regs [greg ++] = *(gint16*)(arg);
2838 case MONO_TYPE_CHAR:
2839 p->regs [greg ++] = *(guint16*)(arg);
2842 p->regs [greg ++] = *(gint32*)(arg);
2845 p->regs [greg ++] = *(guint32*)(arg);
2847 case MONO_TYPE_GENERICINST:
2848 if (MONO_TYPE_IS_REFERENCE (t)) {
2849 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2854 case MONO_TYPE_VALUETYPE: {
2855 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2857 g_assert (ainfo->storage == ArgValuetypeInReg);
2858 if (ainfo->pair_storage [0] != ArgNone) {
2859 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2860 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2862 if (ainfo->pair_storage [1] != ArgNone) {
2863 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2864 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2869 g_assert_not_reached ();
2873 g_assert (greg <= PARAM_REGS);
2877 * mono_arch_finish_dyn_call:
2879 * Store the result of a dyn call into the return value buffer passed to
2880 * start_dyn_call ().
2881 * This function should be as fast as possible, any work which does not depend
2882 * on the actual values of the arguments should be done in
2883 * mono_arch_dyn_call_prepare ().
2886 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2888 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2889 MonoMethodSignature *sig = dinfo->sig;
2890 guint8 *ret = ((DynCallArgs*)buf)->ret;
2891 mgreg_t res = ((DynCallArgs*)buf)->res;
2893 switch (mono_type_get_underlying_type (sig->ret)->type) {
2894 case MONO_TYPE_VOID:
2895 *(gpointer*)ret = NULL;
2897 case MONO_TYPE_STRING:
2898 case MONO_TYPE_CLASS:
2899 case MONO_TYPE_ARRAY:
2900 case MONO_TYPE_SZARRAY:
2901 case MONO_TYPE_OBJECT:
2905 *(gpointer*)ret = GREG_TO_PTR(res);
2911 case MONO_TYPE_BOOLEAN:
2912 *(guint8*)ret = res;
2915 *(gint16*)ret = res;
2918 case MONO_TYPE_CHAR:
2919 *(guint16*)ret = res;
2922 *(gint32*)ret = res;
2925 *(guint32*)ret = res;
2928 *(gint64*)ret = res;
2931 *(guint64*)ret = res;
2933 case MONO_TYPE_GENERICINST:
2934 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2935 *(gpointer*)ret = GREG_TO_PTR(res);
2940 case MONO_TYPE_VALUETYPE:
2941 if (dinfo->cinfo->vtype_retaddr) {
2944 ArgInfo *ainfo = &dinfo->cinfo->ret;
2946 g_assert (ainfo->storage == ArgValuetypeInReg);
2948 if (ainfo->pair_storage [0] != ArgNone) {
2949 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2950 ((mgreg_t*)ret)[0] = res;
2953 g_assert (ainfo->pair_storage [1] == ArgNone);
2957 g_assert_not_reached ();
2961 /* emit an exception if condition is fail */
2962 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2964 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2965 if (tins == NULL) { \
2966 mono_add_patch_info (cfg, code - cfg->native_code, \
2967 MONO_PATCH_INFO_EXC, exc_name); \
2968 x86_branch32 (code, cond, 0, signed); \
2970 EMIT_COND_BRANCH (tins, cond, signed); \
2974 #define EMIT_FPCOMPARE(code) do { \
2975 amd64_fcompp (code); \
2976 amd64_fnstsw (code); \
2979 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2980 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2981 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2982 amd64_ ##op (code); \
2983 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2984 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2988 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2990 gboolean no_patch = FALSE;
2993 * FIXME: Add support for thunks
2996 gboolean near_call = FALSE;
2999 * Indirect calls are expensive so try to make a near call if possible.
3000 * The caller memory is allocated by the code manager so it is
3001 * guaranteed to be at a 32 bit offset.
3004 if (patch_type != MONO_PATCH_INFO_ABS) {
3005 /* The target is in memory allocated using the code manager */
3008 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3009 if (((MonoMethod*)data)->klass->image->aot_module)
3010 /* The callee might be an AOT method */
3012 if (((MonoMethod*)data)->dynamic)
3013 /* The target is in malloc-ed memory */
3017 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3019 * The call might go directly to a native function without
3022 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
3024 gconstpointer target = mono_icall_get_wrapper (mi);
3025 if ((((guint64)target) >> 32) != 0)
3031 if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
3033 * This is not really an optimization, but required because the
3034 * generic class init trampolines use R11 to pass the vtable.
3038 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3040 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
3041 strstr (cfg->method->name, info->name)) {
3042 /* A call to the wrapped function */
3043 if ((((guint64)data) >> 32) == 0)
3047 else if (info->func == info->wrapper) {
3049 if ((((guint64)info->func) >> 32) == 0)
3053 /* See the comment in mono_codegen () */
3054 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3058 else if ((((guint64)data) >> 32) == 0) {
3065 if (cfg->method->dynamic)
3066 /* These methods are allocated using malloc */
3069 #ifdef MONO_ARCH_NOMAP32BIT
3073 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3074 if (optimize_for_xen)
3077 if (cfg->compile_aot) {
3084 * Align the call displacement to an address divisible by 4 so it does
3085 * not span cache lines. This is required for code patching to work on SMP
3088 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3089 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3090 amd64_padding (code, pad_size);
3092 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3093 amd64_call_code (code, 0);
3096 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3097 amd64_set_reg_template (code, GP_SCRATCH_REG);
3098 amd64_call_reg (code, GP_SCRATCH_REG);
3105 static inline guint8*
3106 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3109 if (win64_adjust_stack)
3110 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3112 code = emit_call_body (cfg, code, patch_type, data);
3114 if (win64_adjust_stack)
3115 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3122 store_membase_imm_to_store_membase_reg (int opcode)
3125 case OP_STORE_MEMBASE_IMM:
3126 return OP_STORE_MEMBASE_REG;
3127 case OP_STOREI4_MEMBASE_IMM:
3128 return OP_STOREI4_MEMBASE_REG;
3129 case OP_STOREI8_MEMBASE_IMM:
3130 return OP_STOREI8_MEMBASE_REG;
3138 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3141 * mono_arch_peephole_pass_1:
3143 * Perform peephole opts which should/can be performed before local regalloc
3146 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3150 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3151 MonoInst *last_ins = ins->prev;
3153 switch (ins->opcode) {
3157 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3159 * X86_LEA is like ADD, but doesn't have the
3160 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3161 * its operand to 64 bit.
3163 ins->opcode = OP_X86_LEA_MEMBASE;
3164 ins->inst_basereg = ins->sreg1;
3169 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3173 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3174 * the latter has length 2-3 instead of 6 (reverse constant
3175 * propagation). These instruction sequences are very common
3176 * in the initlocals bblock.
3178 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3179 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3180 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3181 ins2->sreg1 = ins->dreg;
3182 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3184 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3193 case OP_COMPARE_IMM:
3194 case OP_LCOMPARE_IMM:
3195 /* OP_COMPARE_IMM (reg, 0)
3197 * OP_AMD64_TEST_NULL (reg)
3200 ins->opcode = OP_AMD64_TEST_NULL;
3202 case OP_ICOMPARE_IMM:
3204 ins->opcode = OP_X86_TEST_NULL;
3206 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3208 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3209 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3211 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3212 * OP_COMPARE_IMM reg, imm
3214 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3216 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3217 ins->inst_basereg == last_ins->inst_destbasereg &&
3218 ins->inst_offset == last_ins->inst_offset) {
3219 ins->opcode = OP_ICOMPARE_IMM;
3220 ins->sreg1 = last_ins->sreg1;
3222 /* check if we can remove cmp reg,0 with test null */
3224 ins->opcode = OP_X86_TEST_NULL;
3230 mono_peephole_ins (bb, ins);
3235 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3239 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3240 switch (ins->opcode) {
3243 /* reg = 0 -> XOR (reg, reg) */
3244 /* XOR sets cflags on x86, so we cant do it always */
3245 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3246 ins->opcode = OP_LXOR;
3247 ins->sreg1 = ins->dreg;
3248 ins->sreg2 = ins->dreg;
3256 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3257 * 0 result into 64 bits.
3259 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3260 ins->opcode = OP_IXOR;
3264 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3268 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3269 * the latter has length 2-3 instead of 6 (reverse constant
3270 * propagation). These instruction sequences are very common
3271 * in the initlocals bblock.
3273 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3274 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3275 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3276 ins2->sreg1 = ins->dreg;
3277 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3279 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3289 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3290 ins->opcode = OP_X86_INC_REG;
3293 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3294 ins->opcode = OP_X86_DEC_REG;
3298 mono_peephole_ins (bb, ins);
3302 #define NEW_INS(cfg,ins,dest,op) do { \
3303 MONO_INST_NEW ((cfg), (dest), (op)); \
3304 (dest)->cil_code = (ins)->cil_code; \
3305 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3309 * mono_arch_lowering_pass:
3311 * Converts complex opcodes into simpler ones so that each IR instruction
3312 * corresponds to one machine instruction.
3315 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3317 MonoInst *ins, *n, *temp;
3320 * FIXME: Need to add more instructions, but the current machine
3321 * description can't model some parts of the composite instructions like
3324 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3325 switch (ins->opcode) {
3329 case OP_IDIV_UN_IMM:
3330 case OP_IREM_UN_IMM:
3331 mono_decompose_op_imm (cfg, bb, ins);
3334 /* Keep the opcode if we can implement it efficiently */
3335 if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
3336 mono_decompose_op_imm (cfg, bb, ins);
3338 case OP_COMPARE_IMM:
3339 case OP_LCOMPARE_IMM:
3340 if (!amd64_is_imm32 (ins->inst_imm)) {
3341 NEW_INS (cfg, ins, temp, OP_I8CONST);
3342 temp->inst_c0 = ins->inst_imm;
3343 temp->dreg = mono_alloc_ireg (cfg);
3344 ins->opcode = OP_COMPARE;
3345 ins->sreg2 = temp->dreg;
3348 #ifndef __mono_ilp32__
3349 case OP_LOAD_MEMBASE:
3351 case OP_LOADI8_MEMBASE:
3352 #ifndef __native_client_codegen__
3353 /* Don't generate memindex opcodes (to simplify */
3354 /* read sandboxing) */
3355 if (!amd64_is_imm32 (ins->inst_offset)) {
3356 NEW_INS (cfg, ins, temp, OP_I8CONST);
3357 temp->inst_c0 = ins->inst_offset;
3358 temp->dreg = mono_alloc_ireg (cfg);
3359 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3360 ins->inst_indexreg = temp->dreg;
3364 #ifndef __mono_ilp32__
3365 case OP_STORE_MEMBASE_IMM:
3367 case OP_STOREI8_MEMBASE_IMM:
3368 if (!amd64_is_imm32 (ins->inst_imm)) {
3369 NEW_INS (cfg, ins, temp, OP_I8CONST);
3370 temp->inst_c0 = ins->inst_imm;
3371 temp->dreg = mono_alloc_ireg (cfg);
3372 ins->opcode = OP_STOREI8_MEMBASE_REG;
3373 ins->sreg1 = temp->dreg;
3376 #ifdef MONO_ARCH_SIMD_INTRINSICS
3377 case OP_EXPAND_I1: {
3378 int temp_reg1 = mono_alloc_ireg (cfg);
3379 int temp_reg2 = mono_alloc_ireg (cfg);
3380 int original_reg = ins->sreg1;
3382 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3383 temp->sreg1 = original_reg;
3384 temp->dreg = temp_reg1;
3386 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3387 temp->sreg1 = temp_reg1;
3388 temp->dreg = temp_reg2;
3391 NEW_INS (cfg, ins, temp, OP_LOR);
3392 temp->sreg1 = temp->dreg = temp_reg2;
3393 temp->sreg2 = temp_reg1;
3395 ins->opcode = OP_EXPAND_I2;
3396 ins->sreg1 = temp_reg2;
3405 bb->max_vreg = cfg->next_vreg;
3409 branch_cc_table [] = {
3410 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3411 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3412 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3415 /* Maps CMP_... constants to X86_CC_... constants */
3418 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3419 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3423 cc_signed_table [] = {
3424 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3425 FALSE, FALSE, FALSE, FALSE
3428 /*#include "cprop.c"*/
3430 static unsigned char*
3431 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3433 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3436 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3438 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3442 static unsigned char*
3443 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3445 int sreg = tree->sreg1;
3446 int need_touch = FALSE;
3448 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3449 if (!tree->flags & MONO_INST_INIT)
3458 * If requested stack size is larger than one page,
3459 * perform stack-touch operation
3462 * Generate stack probe code.
3463 * Under Windows, it is necessary to allocate one page at a time,
3464 * "touching" stack after each successful sub-allocation. This is
3465 * because of the way stack growth is implemented - there is a
3466 * guard page before the lowest stack page that is currently commited.
3467 * Stack normally grows sequentially so OS traps access to the
3468 * guard page and commits more pages when needed.
3470 amd64_test_reg_imm (code, sreg, ~0xFFF);
3471 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3473 br[2] = code; /* loop */
3474 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3475 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3476 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3477 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3478 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3479 amd64_patch (br[3], br[2]);
3480 amd64_test_reg_reg (code, sreg, sreg);
3481 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3482 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3484 br[1] = code; x86_jump8 (code, 0);
3486 amd64_patch (br[0], code);
3487 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3488 amd64_patch (br[1], code);
3489 amd64_patch (br[4], code);
3492 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3494 if (tree->flags & MONO_INST_INIT) {
3496 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3497 amd64_push_reg (code, AMD64_RAX);
3500 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3501 amd64_push_reg (code, AMD64_RCX);
3504 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3505 amd64_push_reg (code, AMD64_RDI);
3509 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3510 if (sreg != AMD64_RCX)
3511 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3512 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3514 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3515 if (cfg->param_area && cfg->arch.no_pushes)
3516 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3518 #if defined(__default_codegen__)
3519 amd64_prefix (code, X86_REP_PREFIX);
3521 #elif defined(__native_client_codegen__)
3522 /* NaCl stos pseudo-instruction */
3523 amd64_codegen_pre(code);
3524 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3525 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3526 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3527 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3528 amd64_prefix (code, X86_REP_PREFIX);
3530 amd64_codegen_post(code);
3531 #endif /* __native_client_codegen__ */
3533 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3534 amd64_pop_reg (code, AMD64_RDI);
3535 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3536 amd64_pop_reg (code, AMD64_RCX);
3537 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3538 amd64_pop_reg (code, AMD64_RAX);
3544 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3549 /* Move return value to the target register */
3550 /* FIXME: do this in the local reg allocator */
3551 switch (ins->opcode) {
3554 case OP_CALL_MEMBASE:
3557 case OP_LCALL_MEMBASE:
3558 g_assert (ins->dreg == AMD64_RAX);
3562 case OP_FCALL_MEMBASE:
3563 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3564 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3567 if (ins->dreg != AMD64_XMM0)
3568 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3573 case OP_VCALL_MEMBASE:
3576 case OP_VCALL2_MEMBASE:
3577 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3578 if (cinfo->ret.storage == ArgValuetypeInReg) {
3579 MonoInst *loc = cfg->arch.vret_addr_loc;
3581 /* Load the destination address */
3582 g_assert (loc->opcode == OP_REGOFFSET);
3583 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3585 for (quad = 0; quad < 2; quad ++) {
3586 switch (cinfo->ret.pair_storage [quad]) {
3588 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3590 case ArgInFloatSSEReg:
3591 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3593 case ArgInDoubleSSEReg:
3594 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3609 #endif /* DISABLE_JIT */
3612 static int tls_gs_offset;
3616 mono_amd64_have_tls_get (void)
3619 static gboolean have_tls_get = FALSE;
3620 static gboolean inited = FALSE;
3623 return have_tls_get;
3625 guint8 *ins = (guint8*)pthread_getspecific;
3628 * We're looking for these two instructions:
3630 * mov %gs:[offset](,%rdi,8),%rax
3633 have_tls_get = ins [0] == 0x65 &&
3645 tls_gs_offset = ins[5];
3647 return have_tls_get;
3654 * mono_amd64_emit_tls_get:
3655 * @code: buffer to store code to
3656 * @dreg: hard register where to place the result
3657 * @tls_offset: offset info
3659 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3660 * the dreg register the item in the thread local storage identified
3663 * Returns: a pointer to the end of the stored code
3666 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3669 g_assert (tls_offset < 64);
3670 x86_prefix (code, X86_GS_PREFIX);
3671 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3672 #elif defined(__APPLE__)
3673 x86_prefix (code, X86_GS_PREFIX);
3674 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3676 if (optimize_for_xen) {
3677 x86_prefix (code, X86_FS_PREFIX);
3678 amd64_mov_reg_mem (code, dreg, 0, 8);
3679 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3681 x86_prefix (code, X86_FS_PREFIX);
3682 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3691 * Emit code to initialize an LMF structure at LMF_OFFSET.
3694 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3699 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3702 * sp is saved right before calls but we need to save it here too so
3703 * async stack walks would work.
3705 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3706 /* Skip method (only needed for trampoline LMF frames) */
3707 /* Save callee saved regs */
3708 for (i = 0; i < MONO_MAX_IREGS; ++i) {
3712 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
3713 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
3714 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
3715 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
3716 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
3717 #ifndef __native_client_codegen__
3718 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
3721 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
3722 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
3730 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
3731 if ((cfg->arch.omit_fp || (i != AMD64_RBP)) && cfa_offset != -1)
3732 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
3736 /* These can't contain refs */
3737 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3738 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3739 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
3740 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3741 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3743 /* These are handled automatically by the stack marking code */
3744 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), SLOT_NOREF);
3745 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3746 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), SLOT_NOREF);
3747 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), SLOT_NOREF);
3748 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), SLOT_NOREF);
3749 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), SLOT_NOREF);
3751 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), SLOT_NOREF);
3752 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), SLOT_NOREF);
3761 * Emit code to push an LMF structure on the LMF stack.
3764 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, gboolean *args_clobbered)
3766 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
3768 * Optimized version which uses the mono_lmf TLS variable instead of
3769 * indirection through the mono_lmf_addr TLS variable.
3771 /* %rax = previous_lmf */
3772 x86_prefix (code, X86_FS_PREFIX);
3773 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
3775 /* Save previous_lmf */
3776 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
3778 if (lmf_offset == 0) {
3779 x86_prefix (code, X86_FS_PREFIX);
3780 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
3782 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3783 x86_prefix (code, X86_FS_PREFIX);
3784 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
3787 if (lmf_addr_tls_offset != -1) {
3788 /* Load lmf quicky using the FS register */
3789 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
3791 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
3792 /* FIXME: Add a separate key for LMF to avoid this */
3793 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
3798 * The call might clobber argument registers, but they are already
3799 * saved to the stack/global regs.
3802 *args_clobbered = TRUE;
3803 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3804 (gpointer)"mono_get_lmf_addr", TRUE);
3808 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3809 /* Save previous_lmf */
3810 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
3811 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3813 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3814 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
3823 * Emit code to pop an LMF structure from the LMF stack.
3826 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
3828 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
3830 * Optimized version which uses the mono_lmf TLS variable instead of indirection
3831 * through the mono_lmf_addr TLS variable.
3833 /* reg = previous_lmf */
3834 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3835 x86_prefix (code, X86_FS_PREFIX);
3836 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
3838 /* Restore previous lmf */
3839 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3840 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3841 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
3847 #define REAL_PRINT_REG(text,reg) \
3848 mono_assert (reg >= 0); \
3849 amd64_push_reg (code, AMD64_RAX); \
3850 amd64_push_reg (code, AMD64_RDX); \
3851 amd64_push_reg (code, AMD64_RCX); \
3852 amd64_push_reg (code, reg); \
3853 amd64_push_imm (code, reg); \
3854 amd64_push_imm (code, text " %d %p\n"); \
3855 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3856 amd64_call_reg (code, AMD64_RAX); \
3857 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3858 amd64_pop_reg (code, AMD64_RCX); \
3859 amd64_pop_reg (code, AMD64_RDX); \
3860 amd64_pop_reg (code, AMD64_RAX);
3862 /* benchmark and set based on cpu */
3863 #define LOOP_ALIGNMENT 8
3864 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3868 #if defined(__native_client__) || defined(__native_client_codegen__)
3871 #ifdef __native_client_gc__
3872 __nacl_suspend_thread_if_needed();
3878 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3883 guint8 *code = cfg->native_code + cfg->code_len;
3884 MonoInst *last_ins = NULL;
3885 guint last_offset = 0;
3888 /* Fix max_offset estimate for each successor bb */
3889 if (cfg->opt & MONO_OPT_BRANCH) {
3890 int current_offset = cfg->code_len;
3891 MonoBasicBlock *current_bb;
3892 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3893 current_bb->max_offset = current_offset;
3894 current_offset += current_bb->max_length;
3898 if (cfg->opt & MONO_OPT_LOOP) {
3899 int pad, align = LOOP_ALIGNMENT;
3900 /* set alignment depending on cpu */
3901 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3903 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3904 amd64_padding (code, pad);
3905 cfg->code_len += pad;
3906 bb->native_offset = cfg->code_len;
3910 #if defined(__native_client_codegen__)
3911 /* For Native Client, all indirect call/jump targets must be */
3912 /* 32-byte aligned. Exception handler blocks are jumped to */
3913 /* indirectly as well. */
3914 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3915 (bb->flags & BB_EXCEPTION_HANDLER);
3917 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3918 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3919 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3920 cfg->code_len += pad;
3921 bb->native_offset = cfg->code_len;
3923 #endif /*__native_client_codegen__*/
3925 if (cfg->verbose_level > 2)
3926 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3928 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3929 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3930 g_assert (!cfg->compile_aot);
3932 cov->data [bb->dfn].cil_code = bb->cil_code;
3933 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3934 /* this is not thread save, but good enough */
3935 amd64_inc_membase (code, AMD64_R11, 0);
3938 offset = code - cfg->native_code;
3940 mono_debug_open_block (cfg, bb, offset);
3942 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3943 x86_breakpoint (code);
3945 MONO_BB_FOR_EACH_INS (bb, ins) {
3946 offset = code - cfg->native_code;
3948 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3950 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3952 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3953 cfg->code_size *= 2;
3954 cfg->native_code = mono_realloc_native_code(cfg);
3955 code = cfg->native_code + offset;
3956 cfg->stat_code_reallocs++;
3959 if (cfg->debug_info)
3960 mono_debug_record_line_number (cfg, ins, offset);
3962 switch (ins->opcode) {
3964 amd64_mul_reg (code, ins->sreg2, TRUE);
3967 amd64_mul_reg (code, ins->sreg2, FALSE);
3969 case OP_X86_SETEQ_MEMBASE:
3970 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3972 case OP_STOREI1_MEMBASE_IMM:
3973 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3975 case OP_STOREI2_MEMBASE_IMM:
3976 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3978 case OP_STOREI4_MEMBASE_IMM:
3979 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3981 case OP_STOREI1_MEMBASE_REG:
3982 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3984 case OP_STOREI2_MEMBASE_REG:
3985 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3987 /* In AMD64 NaCl, pointers are 4 bytes, */
3988 /* so STORE_* != STOREI8_*. Likewise below. */
3989 case OP_STORE_MEMBASE_REG:
3990 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3992 case OP_STOREI8_MEMBASE_REG:
3993 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3995 case OP_STOREI4_MEMBASE_REG:
3996 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3998 case OP_STORE_MEMBASE_IMM:
3999 #ifndef __native_client_codegen__
4000 /* In NaCl, this could be a PCONST type, which could */
4001 /* mean a pointer type was copied directly into the */
4002 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
4003 /* the value would be 0x00000000FFFFFFFF which is */
4004 /* not proper for an imm32 unless you cast it. */
4005 g_assert (amd64_is_imm32 (ins->inst_imm));
4007 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4009 case OP_STOREI8_MEMBASE_IMM:
4010 g_assert (amd64_is_imm32 (ins->inst_imm));
4011 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4014 #ifdef __mono_ilp32__
4015 /* In ILP32, pointers are 4 bytes, so separate these */
4016 /* cases, use literal 8 below where we really want 8 */
4017 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4018 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4022 // FIXME: Decompose this earlier
4023 if (amd64_is_imm32 (ins->inst_imm))
4024 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4026 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4027 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4031 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4032 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4035 // FIXME: Decompose this earlier
4036 if (amd64_is_imm32 (ins->inst_imm))
4037 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4039 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4040 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4044 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4045 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4048 /* For NaCl, pointers are 4 bytes, so separate these */
4049 /* cases, use literal 8 below where we really want 8 */
4050 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4051 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4053 case OP_LOAD_MEMBASE:
4054 g_assert (amd64_is_imm32 (ins->inst_offset));
4055 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4057 case OP_LOADI8_MEMBASE:
4058 /* Use literal 8 instead of sizeof pointer or */
4059 /* register, we really want 8 for this opcode */
4060 g_assert (amd64_is_imm32 (ins->inst_offset));
4061 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4063 case OP_LOADI4_MEMBASE:
4064 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4066 case OP_LOADU4_MEMBASE:
4067 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4069 case OP_LOADU1_MEMBASE:
4070 /* The cpu zero extends the result into 64 bits */
4071 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4073 case OP_LOADI1_MEMBASE:
4074 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4076 case OP_LOADU2_MEMBASE:
4077 /* The cpu zero extends the result into 64 bits */
4078 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4080 case OP_LOADI2_MEMBASE:
4081 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4083 case OP_AMD64_LOADI8_MEMINDEX:
4084 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4086 case OP_LCONV_TO_I1:
4087 case OP_ICONV_TO_I1:
4089 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4091 case OP_LCONV_TO_I2:
4092 case OP_ICONV_TO_I2:
4094 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4096 case OP_LCONV_TO_U1:
4097 case OP_ICONV_TO_U1:
4098 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4100 case OP_LCONV_TO_U2:
4101 case OP_ICONV_TO_U2:
4102 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4105 /* Clean out the upper word */
4106 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4109 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4113 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4115 case OP_COMPARE_IMM:
4116 case OP_LCOMPARE_IMM:
4117 g_assert (amd64_is_imm32 (ins->inst_imm));
4118 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4120 case OP_X86_COMPARE_REG_MEMBASE:
4121 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4123 case OP_X86_TEST_NULL:
4124 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4126 case OP_AMD64_TEST_NULL:
4127 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4130 case OP_X86_ADD_REG_MEMBASE:
4131 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4133 case OP_X86_SUB_REG_MEMBASE:
4134 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4136 case OP_X86_AND_REG_MEMBASE:
4137 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4139 case OP_X86_OR_REG_MEMBASE:
4140 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4142 case OP_X86_XOR_REG_MEMBASE:
4143 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4146 case OP_X86_ADD_MEMBASE_IMM:
4147 /* FIXME: Make a 64 version too */
4148 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4150 case OP_X86_SUB_MEMBASE_IMM:
4151 g_assert (amd64_is_imm32 (ins->inst_imm));
4152 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4154 case OP_X86_AND_MEMBASE_IMM:
4155 g_assert (amd64_is_imm32 (ins->inst_imm));
4156 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4158 case OP_X86_OR_MEMBASE_IMM:
4159 g_assert (amd64_is_imm32 (ins->inst_imm));
4160 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4162 case OP_X86_XOR_MEMBASE_IMM:
4163 g_assert (amd64_is_imm32 (ins->inst_imm));
4164 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4166 case OP_X86_ADD_MEMBASE_REG:
4167 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4169 case OP_X86_SUB_MEMBASE_REG:
4170 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4172 case OP_X86_AND_MEMBASE_REG:
4173 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4175 case OP_X86_OR_MEMBASE_REG:
4176 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4178 case OP_X86_XOR_MEMBASE_REG:
4179 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4181 case OP_X86_INC_MEMBASE:
4182 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4184 case OP_X86_INC_REG:
4185 amd64_inc_reg_size (code, ins->dreg, 4);
4187 case OP_X86_DEC_MEMBASE:
4188 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4190 case OP_X86_DEC_REG:
4191 amd64_dec_reg_size (code, ins->dreg, 4);
4193 case OP_X86_MUL_REG_MEMBASE:
4194 case OP_X86_MUL_MEMBASE_REG:
4195 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4197 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4198 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4200 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4201 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4203 case OP_AMD64_COMPARE_MEMBASE_REG:
4204 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4206 case OP_AMD64_COMPARE_MEMBASE_IMM:
4207 g_assert (amd64_is_imm32 (ins->inst_imm));
4208 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4210 case OP_X86_COMPARE_MEMBASE8_IMM:
4211 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4213 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4214 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4216 case OP_AMD64_COMPARE_REG_MEMBASE:
4217 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4220 case OP_AMD64_ADD_REG_MEMBASE:
4221 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4223 case OP_AMD64_SUB_REG_MEMBASE:
4224 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4226 case OP_AMD64_AND_REG_MEMBASE:
4227 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4229 case OP_AMD64_OR_REG_MEMBASE:
4230 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4232 case OP_AMD64_XOR_REG_MEMBASE:
4233 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4236 case OP_AMD64_ADD_MEMBASE_REG:
4237 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4239 case OP_AMD64_SUB_MEMBASE_REG:
4240 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4242 case OP_AMD64_AND_MEMBASE_REG:
4243 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4245 case OP_AMD64_OR_MEMBASE_REG:
4246 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4248 case OP_AMD64_XOR_MEMBASE_REG:
4249 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4252 case OP_AMD64_ADD_MEMBASE_IMM:
4253 g_assert (amd64_is_imm32 (ins->inst_imm));
4254 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4256 case OP_AMD64_SUB_MEMBASE_IMM:
4257 g_assert (amd64_is_imm32 (ins->inst_imm));
4258 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4260 case OP_AMD64_AND_MEMBASE_IMM:
4261 g_assert (amd64_is_imm32 (ins->inst_imm));
4262 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4264 case OP_AMD64_OR_MEMBASE_IMM:
4265 g_assert (amd64_is_imm32 (ins->inst_imm));
4266 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4268 case OP_AMD64_XOR_MEMBASE_IMM:
4269 g_assert (amd64_is_imm32 (ins->inst_imm));
4270 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4274 amd64_breakpoint (code);
4276 case OP_RELAXED_NOP:
4277 x86_prefix (code, X86_REP_PREFIX);
4285 case OP_DUMMY_STORE:
4286 case OP_NOT_REACHED:
4289 case OP_SEQ_POINT: {
4293 * Read from the single stepping trigger page. This will cause a
4294 * SIGSEGV when single stepping is enabled.
4295 * We do this _before_ the breakpoint, so single stepping after
4296 * a breakpoint is hit will step to the next IL offset.
4298 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4299 MonoInst *var = cfg->arch.ss_trigger_page_var;
4301 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4302 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4306 * This is the address which is saved in seq points,
4308 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4310 if (cfg->compile_aot) {
4311 guint32 offset = code - cfg->native_code;
4313 MonoInst *info_var = cfg->arch.seq_point_info_var;
4316 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4317 val = ((offset) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4318 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4319 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4320 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4323 * A placeholder for a possible breakpoint inserted by
4324 * mono_arch_set_breakpoint ().
4326 for (i = 0; i < breakpoint_size; ++i)
4333 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4336 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4340 g_assert (amd64_is_imm32 (ins->inst_imm));
4341 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4344 g_assert (amd64_is_imm32 (ins->inst_imm));
4345 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4349 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4352 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4356 g_assert (amd64_is_imm32 (ins->inst_imm));
4357 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4360 g_assert (amd64_is_imm32 (ins->inst_imm));
4361 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4364 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4368 g_assert (amd64_is_imm32 (ins->inst_imm));
4369 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4372 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4377 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4379 switch (ins->inst_imm) {
4383 if (ins->dreg != ins->sreg1)
4384 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4385 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4388 /* LEA r1, [r2 + r2*2] */
4389 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4392 /* LEA r1, [r2 + r2*4] */
4393 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4396 /* LEA r1, [r2 + r2*2] */
4398 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4399 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4402 /* LEA r1, [r2 + r2*8] */
4403 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4406 /* LEA r1, [r2 + r2*4] */
4408 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4409 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4412 /* LEA r1, [r2 + r2*2] */
4414 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4415 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4418 /* LEA r1, [r2 + r2*4] */
4419 /* LEA r1, [r1 + r1*4] */
4420 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4421 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4424 /* LEA r1, [r2 + r2*4] */
4426 /* LEA r1, [r1 + r1*4] */
4427 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4428 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4429 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4432 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4439 /* Regalloc magic makes the div/rem cases the same */
4440 if (ins->sreg2 == AMD64_RDX) {
4441 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4443 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4446 amd64_div_reg (code, ins->sreg2, TRUE);
4451 if (ins->sreg2 == AMD64_RDX) {
4452 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4453 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4454 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4456 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4457 amd64_div_reg (code, ins->sreg2, FALSE);
4462 if (ins->sreg2 == AMD64_RDX) {
4463 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4464 amd64_cdq_size (code, 4);
4465 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4467 amd64_cdq_size (code, 4);
4468 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4473 if (ins->sreg2 == AMD64_RDX) {
4474 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4475 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4476 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4478 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4479 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4483 int power = mono_is_power_of_two (ins->inst_imm);
4485 g_assert (ins->sreg1 == X86_EAX);
4486 g_assert (ins->dreg == X86_EAX);
4487 g_assert (power >= 0);
4490 amd64_mov_reg_imm (code, ins->dreg, 0);
4494 /* Based on gcc code */
4496 /* Add compensation for negative dividents */
4497 amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
4499 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
4500 amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
4501 amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
4502 /* Compute remainder */
4503 amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
4504 /* Remove compensation */
4505 amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
4509 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4510 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4513 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4517 g_assert (amd64_is_imm32 (ins->inst_imm));
4518 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4521 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4525 g_assert (amd64_is_imm32 (ins->inst_imm));
4526 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4529 g_assert (ins->sreg2 == AMD64_RCX);
4530 amd64_shift_reg (code, X86_SHL, ins->dreg);
4533 g_assert (ins->sreg2 == AMD64_RCX);
4534 amd64_shift_reg (code, X86_SAR, ins->dreg);
4537 g_assert (amd64_is_imm32 (ins->inst_imm));
4538 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4541 g_assert (amd64_is_imm32 (ins->inst_imm));
4542 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4545 g_assert (amd64_is_imm32 (ins->inst_imm));
4546 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4548 case OP_LSHR_UN_IMM:
4549 g_assert (amd64_is_imm32 (ins->inst_imm));
4550 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4553 g_assert (ins->sreg2 == AMD64_RCX);
4554 amd64_shift_reg (code, X86_SHR, ins->dreg);
4557 g_assert (amd64_is_imm32 (ins->inst_imm));
4558 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4561 g_assert (amd64_is_imm32 (ins->inst_imm));
4562 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4567 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4570 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4573 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4576 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4580 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4583 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4586 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4589 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4592 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4595 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4598 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4601 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4604 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4607 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4610 amd64_neg_reg_size (code, ins->sreg1, 4);
4613 amd64_not_reg_size (code, ins->sreg1, 4);
4616 g_assert (ins->sreg2 == AMD64_RCX);
4617 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4620 g_assert (ins->sreg2 == AMD64_RCX);
4621 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4624 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4626 case OP_ISHR_UN_IMM:
4627 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4630 g_assert (ins->sreg2 == AMD64_RCX);
4631 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4634 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4637 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4640 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4641 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4643 case OP_IMUL_OVF_UN:
4644 case OP_LMUL_OVF_UN: {
4645 /* the mul operation and the exception check should most likely be split */
4646 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4647 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4648 /*g_assert (ins->sreg2 == X86_EAX);
4649 g_assert (ins->dreg == X86_EAX);*/
4650 if (ins->sreg2 == X86_EAX) {
4651 non_eax_reg = ins->sreg1;
4652 } else if (ins->sreg1 == X86_EAX) {
4653 non_eax_reg = ins->sreg2;
4655 /* no need to save since we're going to store to it anyway */
4656 if (ins->dreg != X86_EAX) {
4658 amd64_push_reg (code, X86_EAX);
4660 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4661 non_eax_reg = ins->sreg2;
4663 if (ins->dreg == X86_EDX) {
4666 amd64_push_reg (code, X86_EAX);
4670 amd64_push_reg (code, X86_EDX);
4672 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4673 /* save before the check since pop and mov don't change the flags */
4674 if (ins->dreg != X86_EAX)
4675 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4677 amd64_pop_reg (code, X86_EDX);
4679 amd64_pop_reg (code, X86_EAX);
4680 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4684 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4686 case OP_ICOMPARE_IMM:
4687 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4709 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4717 case OP_CMOV_INE_UN:
4718 case OP_CMOV_IGE_UN:
4719 case OP_CMOV_IGT_UN:
4720 case OP_CMOV_ILE_UN:
4721 case OP_CMOV_ILT_UN:
4727 case OP_CMOV_LNE_UN:
4728 case OP_CMOV_LGE_UN:
4729 case OP_CMOV_LGT_UN:
4730 case OP_CMOV_LLE_UN:
4731 case OP_CMOV_LLT_UN:
4732 g_assert (ins->dreg == ins->sreg1);
4733 /* This needs to operate on 64 bit values */
4734 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4738 amd64_not_reg (code, ins->sreg1);
4741 amd64_neg_reg (code, ins->sreg1);
4746 if ((((guint64)ins->inst_c0) >> 32) == 0)
4747 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4749 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4752 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4753 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4756 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4757 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4760 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4762 case OP_AMD64_SET_XMMREG_R4: {
4763 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4766 case OP_AMD64_SET_XMMREG_R8: {
4767 if (ins->dreg != ins->sreg1)
4768 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4772 MonoCallInst *call = (MonoCallInst*)ins;
4775 /* FIXME: no tracing support... */
4776 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4777 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, TRUE);
4779 g_assert (!cfg->method->save_lmf);
4781 if (cfg->arch.omit_fp) {
4782 guint32 save_offset = 0;
4783 /* Pop callee-saved registers */
4784 for (i = 0; i < AMD64_NREG; ++i)
4785 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4786 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4789 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4792 if (call->stack_usage)
4796 for (i = 0; i < AMD64_NREG; ++i)
4797 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4798 pos -= sizeof(mgreg_t);
4800 /* Restore callee-saved registers */
4801 for (i = AMD64_NREG - 1; i > 0; --i) {
4802 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4803 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, sizeof(mgreg_t));
4804 pos += sizeof(mgreg_t);
4808 /* Copy arguments on the stack to our argument area */
4809 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4810 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4811 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4815 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4820 offset = code - cfg->native_code;
4821 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4822 if (cfg->compile_aot)
4823 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4825 amd64_set_reg_template (code, AMD64_R11);
4826 amd64_jump_reg (code, AMD64_R11);
4827 ins->flags |= MONO_INST_GC_CALLSITE;
4828 ins->backend.pc_offset = code - cfg->native_code;
4832 /* ensure ins->sreg1 is not NULL */
4833 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4836 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4837 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4846 call = (MonoCallInst*)ins;
4848 * The AMD64 ABI forces callers to know about varargs.
4850 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4851 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4852 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4854 * Since the unmanaged calling convention doesn't contain a
4855 * 'vararg' entry, we have to treat every pinvoke call as a
4856 * potential vararg call.
4860 for (i = 0; i < AMD64_XMM_NREG; ++i)
4861 if (call->used_fregs & (1 << i))
4864 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4866 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4869 if (ins->flags & MONO_INST_HAS_METHOD)
4870 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4872 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4873 ins->flags |= MONO_INST_GC_CALLSITE;
4874 ins->backend.pc_offset = code - cfg->native_code;
4875 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4876 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4877 code = emit_move_return_value (cfg, ins, code);
4883 case OP_VOIDCALL_REG:
4885 call = (MonoCallInst*)ins;
4887 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4888 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4889 ins->sreg1 = AMD64_R11;
4893 * The AMD64 ABI forces callers to know about varargs.
4895 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4896 if (ins->sreg1 == AMD64_RAX) {
4897 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4898 ins->sreg1 = AMD64_R11;
4900 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4901 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4903 * Since the unmanaged calling convention doesn't contain a
4904 * 'vararg' entry, we have to treat every pinvoke call as a
4905 * potential vararg call.
4909 for (i = 0; i < AMD64_XMM_NREG; ++i)
4910 if (call->used_fregs & (1 << i))
4912 if (ins->sreg1 == AMD64_RAX) {
4913 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4914 ins->sreg1 = AMD64_R11;
4917 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4919 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4922 amd64_call_reg (code, ins->sreg1);
4923 ins->flags |= MONO_INST_GC_CALLSITE;
4924 ins->backend.pc_offset = code - cfg->native_code;
4925 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4926 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4927 code = emit_move_return_value (cfg, ins, code);
4929 case OP_FCALL_MEMBASE:
4930 case OP_LCALL_MEMBASE:
4931 case OP_VCALL_MEMBASE:
4932 case OP_VCALL2_MEMBASE:
4933 case OP_VOIDCALL_MEMBASE:
4934 case OP_CALL_MEMBASE:
4935 call = (MonoCallInst*)ins;
4937 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4938 ins->flags |= MONO_INST_GC_CALLSITE;
4939 ins->backend.pc_offset = code - cfg->native_code;
4940 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4941 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4942 code = emit_move_return_value (cfg, ins, code);
4946 MonoInst *var = cfg->dyn_call_var;
4948 g_assert (var->opcode == OP_REGOFFSET);
4950 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4951 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4953 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4955 /* Save args buffer */
4956 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4958 /* Set argument registers */
4959 for (i = 0; i < PARAM_REGS; ++i)
4960 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4963 amd64_call_reg (code, AMD64_R10);
4965 ins->flags |= MONO_INST_GC_CALLSITE;
4966 ins->backend.pc_offset = code - cfg->native_code;
4969 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4970 amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4973 case OP_AMD64_SAVE_SP_TO_LMF: {
4974 MonoInst *lmf_var = cfg->arch.lmf_var;
4975 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4979 g_assert (!cfg->arch.no_pushes);
4980 amd64_push_reg (code, ins->sreg1);
4982 case OP_X86_PUSH_IMM:
4983 g_assert (!cfg->arch.no_pushes);
4984 g_assert (amd64_is_imm32 (ins->inst_imm));
4985 amd64_push_imm (code, ins->inst_imm);
4987 case OP_X86_PUSH_MEMBASE:
4988 g_assert (!cfg->arch.no_pushes);
4989 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4991 case OP_X86_PUSH_OBJ: {
4992 int size = ALIGN_TO (ins->inst_imm, 8);
4994 g_assert (!cfg->arch.no_pushes);
4996 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4997 amd64_push_reg (code, AMD64_RDI);
4998 amd64_push_reg (code, AMD64_RSI);
4999 amd64_push_reg (code, AMD64_RCX);
5000 if (ins->inst_offset)
5001 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5003 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5004 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5005 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5007 amd64_prefix (code, X86_REP_PREFIX);
5009 amd64_pop_reg (code, AMD64_RCX);
5010 amd64_pop_reg (code, AMD64_RSI);
5011 amd64_pop_reg (code, AMD64_RDI);
5015 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5017 case OP_X86_LEA_MEMBASE:
5018 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5021 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5024 /* keep alignment */
5025 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5026 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5027 code = mono_emit_stack_alloc (cfg, code, ins);
5028 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5029 if (cfg->param_area && cfg->arch.no_pushes)
5030 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5032 case OP_LOCALLOC_IMM: {
5033 guint32 size = ins->inst_imm;
5034 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5036 if (ins->flags & MONO_INST_INIT) {
5040 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5041 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5043 for (i = 0; i < size; i += 8)
5044 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5045 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5047 amd64_mov_reg_imm (code, ins->dreg, size);
5048 ins->sreg1 = ins->dreg;
5050 code = mono_emit_stack_alloc (cfg, code, ins);
5051 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5054 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5055 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5057 if (cfg->param_area && cfg->arch.no_pushes)
5058 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5062 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5063 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5064 (gpointer)"mono_arch_throw_exception", FALSE);
5065 ins->flags |= MONO_INST_GC_CALLSITE;
5066 ins->backend.pc_offset = code - cfg->native_code;
5070 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5071 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5072 (gpointer)"mono_arch_rethrow_exception", FALSE);
5073 ins->flags |= MONO_INST_GC_CALLSITE;
5074 ins->backend.pc_offset = code - cfg->native_code;
5077 case OP_CALL_HANDLER:
5079 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5080 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5081 amd64_call_imm (code, 0);
5082 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5083 /* Restore stack alignment */
5084 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5086 case OP_START_HANDLER: {
5087 /* Even though we're saving RSP, use sizeof */
5088 /* gpointer because spvar is of type IntPtr */
5089 /* see: mono_create_spvar_for_region */
5090 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5091 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5093 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5094 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5095 cfg->param_area && cfg->arch.no_pushes) {
5096 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5100 case OP_ENDFINALLY: {
5101 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5102 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5106 case OP_ENDFILTER: {
5107 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5108 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5109 /* The local allocator will put the result into RAX */
5115 ins->inst_c0 = code - cfg->native_code;
5118 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5119 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5121 if (ins->inst_target_bb->native_offset) {
5122 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5124 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5125 if ((cfg->opt & MONO_OPT_BRANCH) &&
5126 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5127 x86_jump8 (code, 0);
5129 x86_jump32 (code, 0);
5133 amd64_jump_reg (code, ins->sreg1);
5150 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5151 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5153 case OP_COND_EXC_EQ:
5154 case OP_COND_EXC_NE_UN:
5155 case OP_COND_EXC_LT:
5156 case OP_COND_EXC_LT_UN:
5157 case OP_COND_EXC_GT:
5158 case OP_COND_EXC_GT_UN:
5159 case OP_COND_EXC_GE:
5160 case OP_COND_EXC_GE_UN:
5161 case OP_COND_EXC_LE:
5162 case OP_COND_EXC_LE_UN:
5163 case OP_COND_EXC_IEQ:
5164 case OP_COND_EXC_INE_UN:
5165 case OP_COND_EXC_ILT:
5166 case OP_COND_EXC_ILT_UN:
5167 case OP_COND_EXC_IGT:
5168 case OP_COND_EXC_IGT_UN:
5169 case OP_COND_EXC_IGE:
5170 case OP_COND_EXC_IGE_UN:
5171 case OP_COND_EXC_ILE:
5172 case OP_COND_EXC_ILE_UN:
5173 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5175 case OP_COND_EXC_OV:
5176 case OP_COND_EXC_NO:
5178 case OP_COND_EXC_NC:
5179 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5180 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5182 case OP_COND_EXC_IOV:
5183 case OP_COND_EXC_INO:
5184 case OP_COND_EXC_IC:
5185 case OP_COND_EXC_INC:
5186 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5187 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5190 /* floating point opcodes */
5192 double d = *(double *)ins->inst_p0;
5194 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5195 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5198 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5199 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5204 float f = *(float *)ins->inst_p0;
5206 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5207 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5210 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5211 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5212 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5216 case OP_STORER8_MEMBASE_REG:
5217 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5219 case OP_LOADR8_MEMBASE:
5220 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5222 case OP_STORER4_MEMBASE_REG:
5223 /* This requires a double->single conversion */
5224 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5225 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5227 case OP_LOADR4_MEMBASE:
5228 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5229 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5231 case OP_ICONV_TO_R4: /* FIXME: change precision */
5232 case OP_ICONV_TO_R8:
5233 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5235 case OP_LCONV_TO_R4: /* FIXME: change precision */
5236 case OP_LCONV_TO_R8:
5237 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5239 case OP_FCONV_TO_R4:
5240 /* FIXME: nothing to do ?? */
5242 case OP_FCONV_TO_I1:
5243 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5245 case OP_FCONV_TO_U1:
5246 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5248 case OP_FCONV_TO_I2:
5249 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5251 case OP_FCONV_TO_U2:
5252 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5254 case OP_FCONV_TO_U4:
5255 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5257 case OP_FCONV_TO_I4:
5259 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5261 case OP_FCONV_TO_I8:
5262 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5264 case OP_LCONV_TO_R_UN: {
5267 /* Based on gcc code */
5268 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5269 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5272 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5273 br [1] = code; x86_jump8 (code, 0);
5274 amd64_patch (br [0], code);
5277 /* Save to the red zone */
5278 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5279 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5280 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5281 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5282 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5283 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5284 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5285 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5286 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5288 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5289 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5290 amd64_patch (br [1], code);
5293 case OP_LCONV_TO_OVF_U4:
5294 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5295 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5296 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5298 case OP_LCONV_TO_OVF_I4_UN:
5299 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5300 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5301 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5304 if (ins->dreg != ins->sreg1)
5305 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5308 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5311 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5314 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5317 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5320 static double r8_0 = -0.0;
5322 g_assert (ins->sreg1 == ins->dreg);
5324 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5325 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5329 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5332 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5335 static guint64 d = 0x7fffffffffffffffUL;
5337 g_assert (ins->sreg1 == ins->dreg);
5339 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5340 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5344 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5347 g_assert (cfg->opt & MONO_OPT_CMOV);
5348 g_assert (ins->dreg == ins->sreg1);
5349 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5350 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5353 g_assert (cfg->opt & MONO_OPT_CMOV);
5354 g_assert (ins->dreg == ins->sreg1);
5355 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5356 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5359 g_assert (cfg->opt & MONO_OPT_CMOV);
5360 g_assert (ins->dreg == ins->sreg1);
5361 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5362 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5365 g_assert (cfg->opt & MONO_OPT_CMOV);
5366 g_assert (ins->dreg == ins->sreg1);
5367 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5368 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5371 g_assert (cfg->opt & MONO_OPT_CMOV);
5372 g_assert (ins->dreg == ins->sreg1);
5373 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5374 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5377 g_assert (cfg->opt & MONO_OPT_CMOV);
5378 g_assert (ins->dreg == ins->sreg1);
5379 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5380 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5383 g_assert (cfg->opt & MONO_OPT_CMOV);
5384 g_assert (ins->dreg == ins->sreg1);
5385 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5386 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5389 g_assert (cfg->opt & MONO_OPT_CMOV);
5390 g_assert (ins->dreg == ins->sreg1);
5391 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5392 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5398 * The two arguments are swapped because the fbranch instructions
5399 * depend on this for the non-sse case to work.
5401 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5404 /* zeroing the register at the start results in
5405 * shorter and faster code (we can also remove the widening op)
5407 guchar *unordered_check;
5408 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5409 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5410 unordered_check = code;
5411 x86_branch8 (code, X86_CC_P, 0, FALSE);
5412 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5413 amd64_patch (unordered_check, code);
5418 /* zeroing the register at the start results in
5419 * shorter and faster code (we can also remove the widening op)
5421 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5422 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5423 if (ins->opcode == OP_FCLT_UN) {
5424 guchar *unordered_check = code;
5425 guchar *jump_to_end;
5426 x86_branch8 (code, X86_CC_P, 0, FALSE);
5427 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5429 x86_jump8 (code, 0);
5430 amd64_patch (unordered_check, code);
5431 amd64_inc_reg (code, ins->dreg);
5432 amd64_patch (jump_to_end, code);
5434 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5439 /* zeroing the register at the start results in
5440 * shorter and faster code (we can also remove the widening op)
5442 guchar *unordered_check;
5443 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5444 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5445 if (ins->opcode == OP_FCGT) {
5446 unordered_check = code;
5447 x86_branch8 (code, X86_CC_P, 0, FALSE);
5448 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5449 amd64_patch (unordered_check, code);
5451 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5455 case OP_FCLT_MEMBASE:
5456 case OP_FCGT_MEMBASE:
5457 case OP_FCLT_UN_MEMBASE:
5458 case OP_FCGT_UN_MEMBASE:
5459 case OP_FCEQ_MEMBASE: {
5460 guchar *unordered_check, *jump_to_end;
5463 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5464 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5466 switch (ins->opcode) {
5467 case OP_FCEQ_MEMBASE:
5468 x86_cond = X86_CC_EQ;
5470 case OP_FCLT_MEMBASE:
5471 case OP_FCLT_UN_MEMBASE:
5472 x86_cond = X86_CC_LT;
5474 case OP_FCGT_MEMBASE:
5475 case OP_FCGT_UN_MEMBASE:
5476 x86_cond = X86_CC_GT;
5479 g_assert_not_reached ();
5482 unordered_check = code;
5483 x86_branch8 (code, X86_CC_P, 0, FALSE);
5484 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5486 switch (ins->opcode) {
5487 case OP_FCEQ_MEMBASE:
5488 case OP_FCLT_MEMBASE:
5489 case OP_FCGT_MEMBASE:
5490 amd64_patch (unordered_check, code);
5492 case OP_FCLT_UN_MEMBASE:
5493 case OP_FCGT_UN_MEMBASE:
5495 x86_jump8 (code, 0);
5496 amd64_patch (unordered_check, code);
5497 amd64_inc_reg (code, ins->dreg);
5498 amd64_patch (jump_to_end, code);
5506 guchar *jump = code;
5507 x86_branch8 (code, X86_CC_P, 0, TRUE);
5508 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5509 amd64_patch (jump, code);
5513 /* Branch if C013 != 100 */
5514 /* branch if !ZF or (PF|CF) */
5515 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5516 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5517 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5520 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5523 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5524 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5528 if (ins->opcode == OP_FBGT) {
5531 /* skip branch if C1=1 */
5533 x86_branch8 (code, X86_CC_P, 0, FALSE);
5534 /* branch if (C0 | C3) = 1 */
5535 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5536 amd64_patch (br1, code);
5539 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5543 /* Branch if C013 == 100 or 001 */
5546 /* skip branch if C1=1 */
5548 x86_branch8 (code, X86_CC_P, 0, FALSE);
5549 /* branch if (C0 | C3) = 1 */
5550 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5551 amd64_patch (br1, code);
5555 /* Branch if C013 == 000 */
5556 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5559 /* Branch if C013=000 or 100 */
5562 /* skip branch if C1=1 */
5564 x86_branch8 (code, X86_CC_P, 0, FALSE);
5565 /* branch if C0=0 */
5566 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5567 amd64_patch (br1, code);
5571 /* Branch if C013 != 001 */
5572 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5573 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5576 /* Transfer value to the fp stack */
5577 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5578 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5579 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5581 amd64_push_reg (code, AMD64_RAX);
5583 amd64_fnstsw (code);
5584 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5585 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5586 amd64_pop_reg (code, AMD64_RAX);
5587 amd64_fstp (code, 0);
5588 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5589 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5592 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5595 case OP_MEMORY_BARRIER: {
5596 switch (ins->backend.memory_barrier_kind) {
5597 case StoreLoadBarrier:
5599 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5600 x86_prefix (code, X86_LOCK_PREFIX);
5601 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5606 case OP_ATOMIC_ADD_I4:
5607 case OP_ATOMIC_ADD_I8: {
5608 int dreg = ins->dreg;
5609 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5611 if (dreg == ins->inst_basereg)
5614 if (dreg != ins->sreg2)
5615 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5617 x86_prefix (code, X86_LOCK_PREFIX);
5618 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5620 if (dreg != ins->dreg)
5621 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5625 case OP_ATOMIC_ADD_NEW_I4:
5626 case OP_ATOMIC_ADD_NEW_I8: {
5627 int dreg = ins->dreg;
5628 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
5630 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5633 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5634 amd64_prefix (code, X86_LOCK_PREFIX);
5635 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5636 /* dreg contains the old value, add with sreg2 value */
5637 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5639 if (ins->dreg != dreg)
5640 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5644 case OP_ATOMIC_EXCHANGE_I4:
5645 case OP_ATOMIC_EXCHANGE_I8: {
5647 int sreg2 = ins->sreg2;
5648 int breg = ins->inst_basereg;
5650 gboolean need_push = FALSE, rdx_pushed = FALSE;
5652 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5658 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5659 * an explanation of how this works.
5662 /* cmpxchg uses eax as comperand, need to make sure we can use it
5663 * hack to overcome limits in x86 reg allocator
5664 * (req: dreg == eax and sreg2 != eax and breg != eax)
5666 g_assert (ins->dreg == AMD64_RAX);
5668 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5669 /* Highly unlikely, but possible */
5672 /* The pushes invalidate rsp */
5673 if ((breg == AMD64_RAX) || need_push) {
5674 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5678 /* We need the EAX reg for the comparand */
5679 if (ins->sreg2 == AMD64_RAX) {
5680 if (breg != AMD64_R11) {
5681 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5684 g_assert (need_push);
5685 amd64_push_reg (code, AMD64_RDX);
5686 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5692 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5694 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5695 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5696 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5697 amd64_patch (br [1], br [0]);
5700 amd64_pop_reg (code, AMD64_RDX);
5704 case OP_ATOMIC_CAS_I4:
5705 case OP_ATOMIC_CAS_I8: {
5708 if (ins->opcode == OP_ATOMIC_CAS_I8)
5714 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5715 * an explanation of how this works.
5717 g_assert (ins->sreg3 == AMD64_RAX);
5718 g_assert (ins->sreg1 != AMD64_RAX);
5719 g_assert (ins->sreg1 != ins->sreg2);
5721 amd64_prefix (code, X86_LOCK_PREFIX);
5722 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5724 if (ins->dreg != AMD64_RAX)
5725 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5728 case OP_CARD_TABLE_WBARRIER: {
5729 int ptr = ins->sreg1;
5730 int value = ins->sreg2;
5732 int nursery_shift, card_table_shift;
5733 gpointer card_table_mask;
5734 size_t nursery_size;
5736 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5737 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5738 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5740 /*If either point to the stack we can simply avoid the WB. This happens due to
5741 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5743 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5747 * We need one register we can clobber, we choose EDX and make sreg1
5748 * fixed EAX to work around limitations in the local register allocator.
5749 * sreg2 might get allocated to EDX, but that is not a problem since
5750 * we use it before clobbering EDX.
5752 g_assert (ins->sreg1 == AMD64_RAX);
5755 * This is the code we produce:
5758 * edx >>= nursery_shift
5759 * cmp edx, (nursery_start >> nursery_shift)
5762 * edx >>= card_table_shift
5768 if (value != AMD64_RDX)
5769 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5770 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5771 if (shifted_nursery_start >> 31) {
5773 * The value we need to compare against is 64 bits, so we need
5774 * another spare register. We use RBX, which we save and
5777 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5778 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5779 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5780 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5782 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5784 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5785 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5786 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5787 if (card_table_mask)
5788 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5790 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5791 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5793 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5794 x86_patch (br, code);
5797 #ifdef MONO_ARCH_SIMD_INTRINSICS
5798 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5800 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5803 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5806 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5809 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5812 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5815 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5818 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5819 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5822 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5825 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5828 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5831 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5834 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5837 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5840 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5843 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5846 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5849 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5852 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5855 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5858 case OP_PSHUFLEW_HIGH:
5859 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5860 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5862 case OP_PSHUFLEW_LOW:
5863 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5864 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5867 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5868 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5871 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5872 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5875 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5876 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5880 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5883 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5886 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5889 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5892 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5895 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5898 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5899 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5902 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5905 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5908 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5911 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5914 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5917 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5920 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5923 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5926 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5929 case OP_EXTRACT_MASK:
5930 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5934 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5937 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5940 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5944 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5947 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5950 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5953 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5957 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5960 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5963 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5966 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5970 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5973 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5976 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5980 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5983 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5986 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5990 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5993 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5997 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6000 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6003 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6007 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6010 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6013 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6017 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6020 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6023 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6026 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6030 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6033 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6036 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6039 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6042 case OP_PSUM_ABS_DIFF:
6043 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6046 case OP_UNPACK_LOWB:
6047 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6049 case OP_UNPACK_LOWW:
6050 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6052 case OP_UNPACK_LOWD:
6053 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6055 case OP_UNPACK_LOWQ:
6056 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6058 case OP_UNPACK_LOWPS:
6059 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6061 case OP_UNPACK_LOWPD:
6062 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6065 case OP_UNPACK_HIGHB:
6066 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6068 case OP_UNPACK_HIGHW:
6069 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6071 case OP_UNPACK_HIGHD:
6072 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6074 case OP_UNPACK_HIGHQ:
6075 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6077 case OP_UNPACK_HIGHPS:
6078 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6080 case OP_UNPACK_HIGHPD:
6081 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6085 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6088 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6091 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6094 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6097 case OP_PADDB_SAT_UN:
6098 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6100 case OP_PSUBB_SAT_UN:
6101 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6103 case OP_PADDW_SAT_UN:
6104 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6106 case OP_PSUBW_SAT_UN:
6107 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6111 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6114 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6117 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6120 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6124 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6127 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6130 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6132 case OP_PMULW_HIGH_UN:
6133 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6136 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6140 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6143 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6147 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6150 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6154 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6157 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6161 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6164 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6168 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6171 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6175 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6178 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6182 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6185 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6188 /*TODO: This is appart of the sse spec but not added
6190 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6193 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6198 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6201 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6204 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6207 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6210 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6213 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6216 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6219 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6222 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6225 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6229 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6232 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6236 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6237 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6239 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6244 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6246 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6247 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6251 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6253 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6254 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6255 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6259 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6261 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6264 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6266 case OP_EXTRACTX_U2:
6267 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6269 case OP_INSERTX_U1_SLOW:
6270 /*sreg1 is the extracted ireg (scratch)
6271 /sreg2 is the to be inserted ireg (scratch)
6272 /dreg is the xreg to receive the value*/
6274 /*clear the bits from the extracted word*/
6275 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6276 /*shift the value to insert if needed*/
6277 if (ins->inst_c0 & 1)
6278 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6279 /*join them together*/
6280 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6281 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6283 case OP_INSERTX_I4_SLOW:
6284 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6285 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6286 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6288 case OP_INSERTX_I8_SLOW:
6289 amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6291 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6293 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6296 case OP_INSERTX_R4_SLOW:
6297 switch (ins->inst_c0) {
6299 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6302 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6303 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6304 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6307 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6308 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6309 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6312 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6313 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6314 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6318 case OP_INSERTX_R8_SLOW:
6320 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6322 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6324 case OP_STOREX_MEMBASE_REG:
6325 case OP_STOREX_MEMBASE:
6326 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6328 case OP_LOADX_MEMBASE:
6329 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6331 case OP_LOADX_ALIGNED_MEMBASE:
6332 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6334 case OP_STOREX_ALIGNED_MEMBASE_REG:
6335 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6337 case OP_STOREX_NTA_MEMBASE_REG:
6338 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6340 case OP_PREFETCH_MEMBASE:
6341 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6345 /*FIXME the peephole pass should have killed this*/
6346 if (ins->dreg != ins->sreg1)
6347 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6350 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6352 case OP_ICONV_TO_R8_RAW:
6353 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6354 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6357 case OP_FCONV_TO_R8_X:
6358 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6361 case OP_XCONV_R8_TO_I4:
6362 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6363 switch (ins->backend.source_opcode) {
6364 case OP_FCONV_TO_I1:
6365 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6367 case OP_FCONV_TO_U1:
6368 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6370 case OP_FCONV_TO_I2:
6371 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6373 case OP_FCONV_TO_U2:
6374 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6380 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6381 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6382 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6385 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6386 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6389 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6390 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6393 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6394 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6395 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6398 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6399 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6402 case OP_LIVERANGE_START: {
6403 if (cfg->verbose_level > 1)
6404 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6405 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6408 case OP_LIVERANGE_END: {
6409 if (cfg->verbose_level > 1)
6410 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6411 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6414 case OP_NACL_GC_SAFE_POINT: {
6415 #if defined(__native_client_codegen__)
6416 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6420 case OP_GC_LIVENESS_DEF:
6421 case OP_GC_LIVENESS_USE:
6422 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6423 ins->backend.pc_offset = code - cfg->native_code;
6425 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6426 ins->backend.pc_offset = code - cfg->native_code;
6427 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6430 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6431 g_assert_not_reached ();
6434 if ((code - cfg->native_code - offset) > max_len) {
6435 #if !defined(__native_client_codegen__)
6436 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6437 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6438 g_assert_not_reached ();
6443 last_offset = offset;
6446 cfg->code_len = code - cfg->native_code;
6449 #endif /* DISABLE_JIT */
6452 mono_arch_register_lowlevel_calls (void)
6454 /* The signature doesn't matter */
6455 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6459 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6461 MonoJumpInfo *patch_info;
6462 gboolean compile_aot = !run_cctors;
6464 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6465 unsigned char *ip = patch_info->ip.i + code;
6466 unsigned char *target;
6468 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6471 switch (patch_info->type) {
6472 case MONO_PATCH_INFO_BB:
6473 case MONO_PATCH_INFO_LABEL:
6476 /* No need to patch these */
6481 switch (patch_info->type) {
6482 case MONO_PATCH_INFO_NONE:
6484 case MONO_PATCH_INFO_METHOD_REL:
6485 case MONO_PATCH_INFO_R8:
6486 case MONO_PATCH_INFO_R4:
6487 g_assert_not_reached ();
6489 case MONO_PATCH_INFO_BB:
6496 * Debug code to help track down problems where the target of a near call is
6499 if (amd64_is_near_call (ip)) {
6500 gint64 disp = (guint8*)target - (guint8*)ip;
6502 if (!amd64_is_imm32 (disp)) {
6503 printf ("TYPE: %d\n", patch_info->type);
6504 switch (patch_info->type) {
6505 case MONO_PATCH_INFO_INTERNAL_METHOD:
6506 printf ("V: %s\n", patch_info->data.name);
6508 case MONO_PATCH_INFO_METHOD_JUMP:
6509 case MONO_PATCH_INFO_METHOD:
6510 printf ("V: %s\n", patch_info->data.method->name);
6518 amd64_patch (ip, (gpointer)target);
6525 get_max_epilog_size (MonoCompile *cfg)
6527 int max_epilog_size = 16;
6529 if (cfg->method->save_lmf)
6530 max_epilog_size += 256;
6532 if (mono_jit_trace_calls != NULL)
6533 max_epilog_size += 50;
6535 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6536 max_epilog_size += 50;
6538 max_epilog_size += (AMD64_NREG * 2);
6540 return max_epilog_size;
6544 * This macro is used for testing whenever the unwinder works correctly at every point
6545 * where an async exception can happen.
6547 /* This will generate a SIGSEGV at the given point in the code */
6548 #define async_exc_point(code) do { \
6549 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6550 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6551 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6552 cfg->arch.async_point_count ++; \
6557 mono_arch_emit_prolog (MonoCompile *cfg)
6559 MonoMethod *method = cfg->method;
6561 MonoMethodSignature *sig;
6563 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6566 MonoInst *lmf_var = cfg->arch.lmf_var;
6567 gboolean args_clobbered = FALSE;
6568 gboolean trace = FALSE;
6569 #ifdef __native_client_codegen__
6570 guint alignment_check;
6573 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
6575 #if defined(__default_codegen__)
6576 code = cfg->native_code = g_malloc (cfg->code_size);
6577 #elif defined(__native_client_codegen__)
6578 /* native_code_alloc is not 32-byte aligned, native_code is. */
6579 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6581 /* Align native_code to next nearest kNaclAlignment byte. */
6582 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6583 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6585 code = cfg->native_code;
6587 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6588 g_assert (alignment_check == 0);
6591 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6594 /* Amount of stack space allocated by register saving code */
6597 /* Offset between RSP and the CFA */
6601 * The prolog consists of the following parts:
6603 * - push rbp, mov rbp, rsp
6604 * - save callee saved regs using pushes
6606 * - save rgctx if needed
6607 * - save lmf if needed
6610 * - save rgctx if needed
6611 * - save lmf if needed
6612 * - save callee saved regs using moves
6617 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6618 // IP saved at CFA - 8
6619 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6620 async_exc_point (code);
6621 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6623 if (!cfg->arch.omit_fp) {
6624 amd64_push_reg (code, AMD64_RBP);
6626 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6627 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6628 async_exc_point (code);
6630 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6632 /* These are handled automatically by the stack marking code */
6633 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6635 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6636 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6637 async_exc_point (code);
6639 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6643 /* Save callee saved registers */
6644 if (!cfg->arch.omit_fp && !method->save_lmf) {
6645 int offset = cfa_offset;
6647 for (i = 0; i < AMD64_NREG; ++i)
6648 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6649 amd64_push_reg (code, i);
6650 pos += 8; /* AMD64 push inst is always 8 bytes, no way to change it */
6652 mono_emit_unwind_op_offset (cfg, code, i, - offset);
6653 async_exc_point (code);
6655 /* These are handled automatically by the stack marking code */
6656 mini_gc_set_slot_type_from_cfa (cfg, - offset, SLOT_NOREF);
6660 /* The param area is always at offset 0 from sp */
6661 /* This needs to be allocated here, since it has to come after the spill area */
6662 if (cfg->arch.no_pushes && cfg->param_area) {
6663 if (cfg->arch.omit_fp)
6665 g_assert_not_reached ();
6666 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6669 if (cfg->arch.omit_fp) {
6671 * On enter, the stack is misaligned by the pushing of the return
6672 * address. It is either made aligned by the pushing of %rbp, or by
6675 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6676 if ((alloc_size % 16) == 0) {
6678 /* Mark the padding slot as NOREF */
6679 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6682 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6683 if (cfg->stack_offset != alloc_size) {
6684 /* Mark the padding slot as NOREF */
6685 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6687 cfg->arch.sp_fp_offset = alloc_size;
6691 cfg->arch.stack_alloc_size = alloc_size;
6693 /* Allocate stack frame */
6695 /* See mono_emit_stack_alloc */
6696 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6697 guint32 remaining_size = alloc_size;
6698 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6699 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6700 guint32 offset = code - cfg->native_code;
6701 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6702 while (required_code_size >= (cfg->code_size - offset))
6703 cfg->code_size *= 2;
6704 cfg->native_code = mono_realloc_native_code (cfg);
6705 code = cfg->native_code + offset;
6706 cfg->stat_code_reallocs++;
6709 while (remaining_size >= 0x1000) {
6710 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6711 if (cfg->arch.omit_fp) {
6712 cfa_offset += 0x1000;
6713 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6715 async_exc_point (code);
6717 if (cfg->arch.omit_fp)
6718 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6721 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6722 remaining_size -= 0x1000;
6724 if (remaining_size) {
6725 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6726 if (cfg->arch.omit_fp) {
6727 cfa_offset += remaining_size;
6728 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6729 async_exc_point (code);
6732 if (cfg->arch.omit_fp)
6733 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6737 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6738 if (cfg->arch.omit_fp) {
6739 cfa_offset += alloc_size;
6740 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6741 async_exc_point (code);
6746 /* Stack alignment check */
6749 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6750 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6751 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6752 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6753 amd64_breakpoint (code);
6757 #ifndef TARGET_WIN32
6758 if (mini_get_debug_options ()->init_stacks) {
6759 /* Fill the stack frame with a dummy value to force deterministic behavior */
6761 /* Save registers to the red zone */
6762 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6763 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6765 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6766 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6767 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6770 #if defined(__default_codegen__)
6771 amd64_prefix (code, X86_REP_PREFIX);
6773 #elif defined(__native_client_codegen__)
6774 /* NaCl stos pseudo-instruction */
6775 amd64_codegen_pre (code);
6776 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6777 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6778 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6779 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6780 amd64_prefix (code, X86_REP_PREFIX);
6782 amd64_codegen_post (code);
6783 #endif /* __native_client_codegen__ */
6785 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6786 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6791 if (method->save_lmf) {
6792 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6795 /* Save callee saved registers */
6796 if (cfg->arch.omit_fp && !method->save_lmf) {
6797 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6799 /* Save caller saved registers after sp is adjusted */
6800 /* The registers are saved at the bottom of the frame */
6801 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6802 for (i = 0; i < AMD64_NREG; ++i)
6803 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6804 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
6805 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6807 /* These are handled automatically by the stack marking code */
6808 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6810 save_area_offset += 8;
6811 async_exc_point (code);
6815 /* store runtime generic context */
6816 if (cfg->rgctx_var) {
6817 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6818 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6820 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6823 /* compute max_length in order to use short forward jumps */
6824 max_epilog_size = get_max_epilog_size (cfg);
6825 if (cfg->opt & MONO_OPT_BRANCH) {
6826 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6830 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6832 /* max alignment for loops */
6833 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6834 max_length += LOOP_ALIGNMENT;
6835 #ifdef __native_client_codegen__
6836 /* max alignment for native client */
6837 max_length += kNaClAlignment;
6840 MONO_BB_FOR_EACH_INS (bb, ins) {
6841 #ifdef __native_client_codegen__
6843 int space_in_block = kNaClAlignment -
6844 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6845 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6846 if (space_in_block < max_len && max_len < kNaClAlignment) {
6847 max_length += space_in_block;
6850 #endif /*__native_client_codegen__*/
6851 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6854 /* Take prolog and epilog instrumentation into account */
6855 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6856 max_length += max_epilog_size;
6858 bb->max_length = max_length;
6862 sig = mono_method_signature (method);
6865 cinfo = cfg->arch.cinfo;
6867 if (sig->ret->type != MONO_TYPE_VOID) {
6868 /* Save volatile arguments to the stack */
6869 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6870 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6873 /* Keep this in sync with emit_load_volatile_arguments */
6874 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6875 ArgInfo *ainfo = cinfo->args + i;
6876 gint32 stack_offset;
6879 ins = cfg->args [i];
6881 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6882 /* Unused arguments */
6885 if (sig->hasthis && (i == 0))
6886 arg_type = &mono_defaults.object_class->byval_arg;
6888 arg_type = sig->params [i - sig->hasthis];
6890 stack_offset = ainfo->offset + ARGS_OFFSET;
6892 if (cfg->globalra) {
6893 /* All the other moves are done by the register allocator */
6894 switch (ainfo->storage) {
6895 case ArgInFloatSSEReg:
6896 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6898 case ArgValuetypeInReg:
6899 for (quad = 0; quad < 2; quad ++) {
6900 switch (ainfo->pair_storage [quad]) {
6902 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6904 case ArgInFloatSSEReg:
6905 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6907 case ArgInDoubleSSEReg:
6908 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6913 g_assert_not_reached ();
6924 /* Save volatile arguments to the stack */
6925 if (ins->opcode != OP_REGVAR) {
6926 switch (ainfo->storage) {
6932 if (stack_offset & 0x1)
6934 else if (stack_offset & 0x2)
6936 else if (stack_offset & 0x4)
6941 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6944 case ArgInFloatSSEReg:
6945 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6947 case ArgInDoubleSSEReg:
6948 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6950 case ArgValuetypeInReg:
6951 for (quad = 0; quad < 2; quad ++) {
6952 switch (ainfo->pair_storage [quad]) {
6954 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6956 case ArgInFloatSSEReg:
6957 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6959 case ArgInDoubleSSEReg:
6960 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6965 g_assert_not_reached ();
6969 case ArgValuetypeAddrInIReg:
6970 if (ainfo->pair_storage [0] == ArgInIReg)
6971 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6977 /* Argument allocated to (non-volatile) register */
6978 switch (ainfo->storage) {
6980 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6983 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6986 g_assert_not_reached ();
6991 /* Might need to attach the thread to the JIT or change the domain for the callback */
6992 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6993 guint64 domain = (guint64)cfg->domain;
6995 args_clobbered = TRUE;
6998 * The call might clobber argument registers, but they are already
6999 * saved to the stack/global regs.
7001 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
7002 guint8 *buf, *no_domain_branch;
7004 code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
7005 if (cfg->compile_aot) {
7006 /* AOT code is only used in the root domain */
7007 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
7009 if ((domain >> 32) == 0)
7010 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
7012 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
7014 amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
7015 no_domain_branch = code;
7016 x86_branch8 (code, X86_CC_NE, 0, 0);
7017 code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
7018 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
7020 x86_branch8 (code, X86_CC_NE, 0, 0);
7021 amd64_patch (no_domain_branch, code);
7022 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
7023 (gpointer)"mono_jit_thread_attach", TRUE);
7024 amd64_patch (buf, code);
7026 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
7027 /* FIXME: Add a separate key for LMF to avoid this */
7028 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
7031 g_assert (!cfg->compile_aot);
7032 if (cfg->compile_aot) {
7033 /* AOT code is only used in the root domain */
7034 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
7036 if ((domain >> 32) == 0)
7037 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
7039 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
7041 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
7042 (gpointer)"mono_jit_thread_attach", TRUE);
7046 if (method->save_lmf) {
7047 code = emit_save_lmf (cfg, code, lmf_var->inst_offset, &args_clobbered);
7051 args_clobbered = TRUE;
7052 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7055 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7056 args_clobbered = TRUE;
7059 * Optimize the common case of the first bblock making a call with the same
7060 * arguments as the method. This works because the arguments are still in their
7061 * original argument registers.
7062 * FIXME: Generalize this
7064 if (!args_clobbered) {
7065 MonoBasicBlock *first_bb = cfg->bb_entry;
7068 next = mono_bb_first_ins (first_bb);
7069 if (!next && first_bb->next_bb) {
7070 first_bb = first_bb->next_bb;
7071 next = mono_bb_first_ins (first_bb);
7074 if (first_bb->in_count > 1)
7077 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7078 ArgInfo *ainfo = cinfo->args + i;
7079 gboolean match = FALSE;
7081 ins = cfg->args [i];
7082 if (ins->opcode != OP_REGVAR) {
7083 switch (ainfo->storage) {
7085 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7086 if (next->dreg == ainfo->reg) {
7090 next->opcode = OP_MOVE;
7091 next->sreg1 = ainfo->reg;
7092 /* Only continue if the instruction doesn't change argument regs */
7093 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7103 /* Argument allocated to (non-volatile) register */
7104 switch (ainfo->storage) {
7106 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7118 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7125 if (cfg->gen_seq_points) {
7126 MonoInst *info_var = cfg->arch.seq_point_info_var;
7128 /* Initialize seq_point_info_var */
7129 if (cfg->compile_aot) {
7130 /* Initialize the variable from a GOT slot */
7131 /* Same as OP_AOTCONST */
7132 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7133 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7134 g_assert (info_var->opcode == OP_REGOFFSET);
7135 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7138 /* Initialize ss_trigger_page_var */
7139 ins = cfg->arch.ss_trigger_page_var;
7141 g_assert (ins->opcode == OP_REGOFFSET);
7143 if (cfg->compile_aot) {
7144 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7145 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7147 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7149 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7152 cfg->code_len = code - cfg->native_code;
7154 g_assert (cfg->code_len < cfg->code_size);
7160 mono_arch_emit_epilog (MonoCompile *cfg)
7162 MonoMethod *method = cfg->method;
7165 int max_epilog_size;
7167 gint32 lmf_offset = cfg->arch.lmf_var ? ((MonoInst*)cfg->arch.lmf_var)->inst_offset : -1;
7169 max_epilog_size = get_max_epilog_size (cfg);
7171 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7172 cfg->code_size *= 2;
7173 cfg->native_code = mono_realloc_native_code (cfg);
7174 cfg->stat_code_reallocs++;
7177 code = cfg->native_code + cfg->code_len;
7179 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7180 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7182 /* the code restoring the registers must be kept in sync with OP_JMP */
7185 if (method->save_lmf) {
7186 /* check if we need to restore protection of the stack after a stack overflow */
7187 if (mono_get_jit_tls_offset () != -1) {
7189 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7190 /* we load the value in a separate instruction: this mechanism may be
7191 * used later as a safer way to do thread interruption
7193 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7194 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7196 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7197 /* note that the call trampoline will preserve eax/edx */
7198 x86_call_reg (code, X86_ECX);
7199 x86_patch (patch, code);
7201 /* FIXME: maybe save the jit tls in the prolog */
7204 code = emit_restore_lmf (cfg, code, lmf_offset);
7206 /* Restore caller saved regs */
7207 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7208 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7210 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
7211 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
7213 if (cfg->used_int_regs & (1 << AMD64_R12)) {
7214 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
7216 if (cfg->used_int_regs & (1 << AMD64_R13)) {
7217 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
7219 if (cfg->used_int_regs & (1 << AMD64_R14)) {
7220 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
7222 if (cfg->used_int_regs & (1 << AMD64_R15)) {
7223 #if defined(__default_codegen__)
7224 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
7225 #elif defined(__native_client_codegen__)
7226 g_assert_not_reached();
7230 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
7231 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
7233 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
7234 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
7239 if (cfg->arch.omit_fp) {
7240 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7242 for (i = 0; i < AMD64_NREG; ++i)
7243 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7244 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
7245 save_area_offset += 8;
7249 for (i = 0; i < AMD64_NREG; ++i)
7250 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
7251 pos -= sizeof(mgreg_t);
7254 if (pos == - sizeof(mgreg_t)) {
7255 /* Only one register, so avoid lea */
7256 for (i = AMD64_NREG - 1; i > 0; --i)
7257 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7258 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
7262 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
7264 /* Pop registers in reverse order */
7265 for (i = AMD64_NREG - 1; i > 0; --i)
7266 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7267 amd64_pop_reg (code, i);
7274 /* Load returned vtypes into registers if needed */
7275 cinfo = cfg->arch.cinfo;
7276 if (cinfo->ret.storage == ArgValuetypeInReg) {
7277 ArgInfo *ainfo = &cinfo->ret;
7278 MonoInst *inst = cfg->ret;
7280 for (quad = 0; quad < 2; quad ++) {
7281 switch (ainfo->pair_storage [quad]) {
7283 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7285 case ArgInFloatSSEReg:
7286 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7288 case ArgInDoubleSSEReg:
7289 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7294 g_assert_not_reached ();
7299 if (cfg->arch.omit_fp) {
7300 if (cfg->arch.stack_alloc_size)
7301 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7305 async_exc_point (code);
7308 cfg->code_len = code - cfg->native_code;
7310 g_assert (cfg->code_len < cfg->code_size);
7314 mono_arch_emit_exceptions (MonoCompile *cfg)
7316 MonoJumpInfo *patch_info;
7319 MonoClass *exc_classes [16];
7320 guint8 *exc_throw_start [16], *exc_throw_end [16];
7321 guint32 code_size = 0;
7323 /* Compute needed space */
7324 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7325 if (patch_info->type == MONO_PATCH_INFO_EXC)
7327 if (patch_info->type == MONO_PATCH_INFO_R8)
7328 code_size += 8 + 15; /* sizeof (double) + alignment */
7329 if (patch_info->type == MONO_PATCH_INFO_R4)
7330 code_size += 4 + 15; /* sizeof (float) + alignment */
7331 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7332 code_size += 8 + 7; /*sizeof (void*) + alignment */
7335 #ifdef __native_client_codegen__
7336 /* Give us extra room on Native Client. This could be */
7337 /* more carefully calculated, but bundle alignment makes */
7338 /* it much trickier, so *2 like other places is good. */
7342 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7343 cfg->code_size *= 2;
7344 cfg->native_code = mono_realloc_native_code (cfg);
7345 cfg->stat_code_reallocs++;
7348 code = cfg->native_code + cfg->code_len;
7350 /* add code to raise exceptions */
7352 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7353 switch (patch_info->type) {
7354 case MONO_PATCH_INFO_EXC: {
7355 MonoClass *exc_class;
7359 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7361 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7362 g_assert (exc_class);
7363 throw_ip = patch_info->ip.i;
7365 //x86_breakpoint (code);
7366 /* Find a throw sequence for the same exception class */
7367 for (i = 0; i < nthrows; ++i)
7368 if (exc_classes [i] == exc_class)
7371 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7372 x86_jump_code (code, exc_throw_start [i]);
7373 patch_info->type = MONO_PATCH_INFO_NONE;
7377 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7381 exc_classes [nthrows] = exc_class;
7382 exc_throw_start [nthrows] = code;
7384 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7386 patch_info->type = MONO_PATCH_INFO_NONE;
7388 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7390 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7395 exc_throw_end [nthrows] = code;
7405 g_assert(code < cfg->native_code + cfg->code_size);
7408 /* Handle relocations with RIP relative addressing */
7409 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7410 gboolean remove = FALSE;
7411 guint8 *orig_code = code;
7413 switch (patch_info->type) {
7414 case MONO_PATCH_INFO_R8:
7415 case MONO_PATCH_INFO_R4: {
7416 guint8 *pos, *patch_pos;
7419 /* The SSE opcodes require a 16 byte alignment */
7420 #if defined(__default_codegen__)
7421 code = (guint8*)ALIGN_TO (code, 16);
7422 #elif defined(__native_client_codegen__)
7424 /* Pad this out with HLT instructions */
7425 /* or we can get garbage bytes emitted */
7426 /* which will fail validation */
7427 guint8 *aligned_code;
7428 /* extra align to make room for */
7429 /* mov/push below */
7430 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7431 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7432 /* The technique of hiding data in an */
7433 /* instruction has a problem here: we */
7434 /* need the data aligned to a 16-byte */
7435 /* boundary but the instruction cannot */
7436 /* cross the bundle boundary. so only */
7437 /* odd multiples of 16 can be used */
7438 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7441 while (code < aligned_code) {
7442 *(code++) = 0xf4; /* hlt */
7447 pos = cfg->native_code + patch_info->ip.i;
7448 if (IS_REX (pos [1])) {
7449 patch_pos = pos + 5;
7450 target_pos = code - pos - 9;
7453 patch_pos = pos + 4;
7454 target_pos = code - pos - 8;
7457 if (patch_info->type == MONO_PATCH_INFO_R8) {
7458 #ifdef __native_client_codegen__
7459 /* Hide 64-bit data in a */
7460 /* "mov imm64, r11" instruction. */
7461 /* write it before the start of */
7463 *(code-2) = 0x49; /* prefix */
7464 *(code-1) = 0xbb; /* mov X, %r11 */
7466 *(double*)code = *(double*)patch_info->data.target;
7467 code += sizeof (double);
7469 #ifdef __native_client_codegen__
7470 /* Hide 32-bit data in a */
7471 /* "push imm32" instruction. */
7472 *(code-1) = 0x68; /* push */
7474 *(float*)code = *(float*)patch_info->data.target;
7475 code += sizeof (float);
7478 *(guint32*)(patch_pos) = target_pos;
7483 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7486 if (cfg->compile_aot)
7489 /*loading is faster against aligned addresses.*/
7490 code = (guint8*)ALIGN_TO (code, 8);
7491 memset (orig_code, 0, code - orig_code);
7493 pos = cfg->native_code + patch_info->ip.i;
7495 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7496 if (IS_REX (pos [1]))
7497 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7499 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7501 *(gpointer*)code = (gpointer)patch_info->data.target;
7502 code += sizeof (gpointer);
7512 if (patch_info == cfg->patch_info)
7513 cfg->patch_info = patch_info->next;
7517 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7519 tmp->next = patch_info->next;
7522 g_assert (code < cfg->native_code + cfg->code_size);
7525 cfg->code_len = code - cfg->native_code;
7527 g_assert (cfg->code_len < cfg->code_size);
7531 #endif /* DISABLE_JIT */
7534 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7537 CallInfo *cinfo = NULL;
7538 MonoMethodSignature *sig;
7540 int i, n, stack_area = 0;
7542 /* Keep this in sync with mono_arch_get_argument_info */
7544 if (enable_arguments) {
7545 /* Allocate a new area on the stack and save arguments there */
7546 sig = mono_method_signature (cfg->method);
7548 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7550 n = sig->param_count + sig->hasthis;
7552 stack_area = ALIGN_TO (n * 8, 16);
7554 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7556 for (i = 0; i < n; ++i) {
7557 inst = cfg->args [i];
7559 if (inst->opcode == OP_REGVAR)
7560 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7562 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7563 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7568 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7569 amd64_set_reg_template (code, AMD64_ARG_REG1);
7570 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7571 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7573 if (enable_arguments)
7574 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7588 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7591 int save_mode = SAVE_NONE;
7592 MonoMethod *method = cfg->method;
7593 MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
7596 switch (ret_type->type) {
7597 case MONO_TYPE_VOID:
7598 /* special case string .ctor icall */
7599 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7600 save_mode = SAVE_EAX;
7602 save_mode = SAVE_NONE;
7606 save_mode = SAVE_EAX;
7610 save_mode = SAVE_XMM;
7612 case MONO_TYPE_GENERICINST:
7613 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7614 save_mode = SAVE_EAX;
7618 case MONO_TYPE_VALUETYPE:
7619 save_mode = SAVE_STRUCT;
7622 save_mode = SAVE_EAX;
7626 /* Save the result and copy it into the proper argument register */
7627 switch (save_mode) {
7629 amd64_push_reg (code, AMD64_RAX);
7631 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7632 if (enable_arguments)
7633 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7637 if (enable_arguments)
7638 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7641 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7642 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7644 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7646 * The result is already in the proper argument register so no copying
7653 g_assert_not_reached ();
7656 /* Set %al since this is a varargs call */
7657 if (save_mode == SAVE_XMM)
7658 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7660 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7662 if (preserve_argument_registers) {
7663 for (i = 0; i < PARAM_REGS; ++i)
7664 amd64_push_reg (code, param_regs [i]);
7667 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7668 amd64_set_reg_template (code, AMD64_ARG_REG1);
7669 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7671 if (preserve_argument_registers) {
7672 for (i = PARAM_REGS - 1; i >= 0; --i)
7673 amd64_pop_reg (code, param_regs [i]);
7676 /* Restore result */
7677 switch (save_mode) {
7679 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7680 amd64_pop_reg (code, AMD64_RAX);
7686 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7687 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7688 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7693 g_assert_not_reached ();
7700 mono_arch_flush_icache (guint8 *code, gint size)
7706 mono_arch_flush_register_windows (void)
7711 mono_arch_is_inst_imm (gint64 imm)
7713 return amd64_is_imm32 (imm);
7717 * Determine whenever the trap whose info is in SIGINFO is caused by
7721 mono_arch_is_int_overflow (void *sigctx, void *info)
7728 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7730 rip = (guint8*)ctx.rip;
7732 if (IS_REX (rip [0])) {
7733 reg = amd64_rex_b (rip [0]);
7739 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7741 reg += x86_modrm_rm (rip [1]);
7781 g_assert_not_reached ();
7793 mono_arch_get_patch_offset (guint8 *code)
7799 * mono_breakpoint_clean_code:
7801 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7802 * breakpoints in the original code, they are removed in the copy.
7804 * Returns TRUE if no sw breakpoint was present.
7807 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7810 gboolean can_write = TRUE;
7812 * If method_start is non-NULL we need to perform bound checks, since we access memory
7813 * at code - offset we could go before the start of the method and end up in a different
7814 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7817 if (!method_start || code - offset >= method_start) {
7818 memcpy (buf, code - offset, size);
7820 int diff = code - method_start;
7821 memset (buf, 0, size);
7822 memcpy (buf + offset - diff, method_start, diff + size - offset);
7825 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7826 int idx = mono_breakpoint_info_index [i];
7830 ptr = mono_breakpoint_info [idx].address;
7831 if (ptr >= code && ptr < code + size) {
7832 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7834 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7835 buf [ptr - code] = saved_byte;
7841 #if defined(__native_client_codegen__)
7842 /* For membase calls, we want the base register. for Native Client, */
7843 /* all indirect calls have the following sequence with the given sizes: */
7844 /* mov %eXX,%eXX [2-3] */
7845 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7846 /* and $0xffffffffffffffe0,%r11d [4] */
7847 /* add %r15,%r11 [3] */
7848 /* callq *%r11 [3] */
7851 /* Determine if code points to a NaCl call-through-register sequence, */
7852 /* (i.e., the last 3 instructions listed above) */
7854 is_nacl_call_reg_sequence(guint8* code)
7856 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7857 "\x4d\x03\xdf" /* add */
7858 "\x41\xff\xd3"; /* call */
7859 return memcmp(code, sequence, 10) == 0;
7862 /* Determine if code points to the first opcode of the mov membase component */
7863 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7864 /* (there could be a REX prefix before the opcode but it is ignored) */
7866 is_nacl_indirect_call_membase_sequence(guint8* code)
7868 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7869 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7870 /* and that src reg = dest reg */
7871 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7872 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7874 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7875 /* and has dst of r11 and base of r15 */
7876 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7877 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7879 #endif /* __native_client_codegen__ */
7882 mono_arch_get_this_arg_reg (guint8 *code)
7884 return AMD64_ARG_REG1;
7888 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7890 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7893 #define MAX_ARCH_DELEGATE_PARAMS 10
7896 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7898 guint8 *code, *start;
7902 start = code = mono_global_codeman_reserve (64);
7904 /* Replace the this argument with the target */
7905 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7906 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7907 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7909 g_assert ((code - start) < 64);
7911 start = code = mono_global_codeman_reserve (64);
7913 if (param_count == 0) {
7914 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7916 /* We have to shift the arguments left */
7917 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7918 for (i = 0; i < param_count; ++i) {
7921 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7923 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7925 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7929 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7931 g_assert ((code - start) < 64);
7934 nacl_global_codeman_validate(&start, 64, &code);
7936 mono_debug_add_delegate_trampoline (start, code - start);
7939 *code_len = code - start;
7942 if (mono_jit_map_is_enabled ()) {
7945 buff = (char*)"delegate_invoke_has_target";
7947 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7948 mono_emit_jit_tramp (start, code - start, buff);
7957 * mono_arch_get_delegate_invoke_impls:
7959 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7963 mono_arch_get_delegate_invoke_impls (void)
7970 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7971 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7973 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7974 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7975 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7982 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7984 guint8 *code, *start;
7987 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7990 /* FIXME: Support more cases */
7991 if (MONO_TYPE_ISSTRUCT (sig->ret))
7995 static guint8* cached = NULL;
8001 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8003 start = get_delegate_invoke_impl (TRUE, 0, NULL);
8005 mono_memory_barrier ();
8009 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8010 for (i = 0; i < sig->param_count; ++i)
8011 if (!mono_is_regsize_var (sig->params [i]))
8013 if (sig->param_count > 4)
8016 code = cache [sig->param_count];
8020 if (mono_aot_only) {
8021 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8022 start = mono_aot_get_trampoline (name);
8025 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8028 mono_memory_barrier ();
8030 cache [sig->param_count] = start;
8037 * Support for fast access to the thread-local lmf structure using the GS
8038 * segment register on NPTL + kernel 2.6.x.
8041 static gboolean tls_offset_inited = FALSE;
8044 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
8046 if (!tls_offset_inited) {
8049 * We need to init this multiple times, since when we are first called, the key might not
8050 * be initialized yet.
8052 appdomain_tls_offset = mono_domain_get_tls_key ();
8053 lmf_tls_offset = mono_get_jit_tls_key ();
8054 lmf_addr_tls_offset = mono_get_jit_tls_key ();
8056 /* Only 64 tls entries can be accessed using inline code */
8057 if (appdomain_tls_offset >= 64)
8058 appdomain_tls_offset = -1;
8059 if (lmf_tls_offset >= 64)
8060 lmf_tls_offset = -1;
8062 tls_offset_inited = TRUE;
8064 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8066 appdomain_tls_offset = mono_domain_get_tls_offset ();
8067 lmf_tls_offset = mono_get_lmf_tls_offset ();
8068 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
8074 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8078 #ifdef MONO_ARCH_HAVE_IMT
8080 #if defined(__default_codegen__)
8081 #define CMP_SIZE (6 + 1)
8082 #define CMP_REG_REG_SIZE (4 + 1)
8083 #define BR_SMALL_SIZE 2
8084 #define BR_LARGE_SIZE 6
8085 #define MOV_REG_IMM_SIZE 10
8086 #define MOV_REG_IMM_32BIT_SIZE 6
8087 #define JUMP_REG_SIZE (2 + 1)
8088 #elif defined(__native_client_codegen__)
8089 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8090 #define CMP_SIZE ((6 + 1) * 2 - 1)
8091 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8092 #define BR_SMALL_SIZE (2 * 2 - 1)
8093 #define BR_LARGE_SIZE (6 * 2 - 1)
8094 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8095 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8096 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8097 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8098 /* Jump membase's size is large and unpredictable */
8099 /* in native client, just pad it out a whole bundle. */
8100 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8104 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8106 int i, distance = 0;
8107 for (i = start; i < target; ++i)
8108 distance += imt_entries [i]->chunk_size;
8113 * LOCKING: called with the domain lock held
8116 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8117 gpointer fail_tramp)
8121 guint8 *code, *start;
8122 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8124 for (i = 0; i < count; ++i) {
8125 MonoIMTCheckItem *item = imt_entries [i];
8126 if (item->is_equals) {
8127 if (item->check_target_idx) {
8128 if (!item->compare_done) {
8129 if (amd64_is_imm32 (item->key))
8130 item->chunk_size += CMP_SIZE;
8132 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8134 if (item->has_target_code) {
8135 item->chunk_size += MOV_REG_IMM_SIZE;
8137 if (vtable_is_32bit)
8138 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8140 item->chunk_size += MOV_REG_IMM_SIZE;
8141 #ifdef __native_client_codegen__
8142 item->chunk_size += JUMP_MEMBASE_SIZE;
8145 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8148 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8149 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8151 if (vtable_is_32bit)
8152 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8154 item->chunk_size += MOV_REG_IMM_SIZE;
8155 item->chunk_size += JUMP_REG_SIZE;
8156 /* with assert below:
8157 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8159 #ifdef __native_client_codegen__
8160 item->chunk_size += JUMP_MEMBASE_SIZE;
8165 if (amd64_is_imm32 (item->key))
8166 item->chunk_size += CMP_SIZE;
8168 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8169 item->chunk_size += BR_LARGE_SIZE;
8170 imt_entries [item->check_target_idx]->compare_done = TRUE;
8172 size += item->chunk_size;
8174 #if defined(__native_client__) && defined(__native_client_codegen__)
8175 /* In Native Client, we don't re-use thunks, allocate from the */
8176 /* normal code manager paths. */
8177 code = mono_domain_code_reserve (domain, size);
8180 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8182 code = mono_domain_code_reserve (domain, size);
8185 for (i = 0; i < count; ++i) {
8186 MonoIMTCheckItem *item = imt_entries [i];
8187 item->code_target = code;
8188 if (item->is_equals) {
8189 gboolean fail_case = !item->check_target_idx && fail_tramp;
8191 if (item->check_target_idx || fail_case) {
8192 if (!item->compare_done || fail_case) {
8193 if (amd64_is_imm32 (item->key))
8194 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
8196 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8197 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8200 item->jmp_code = code;
8201 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8202 if (item->has_target_code) {
8203 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8204 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8206 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8207 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8211 amd64_patch (item->jmp_code, code);
8212 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8213 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8214 item->jmp_code = NULL;
8217 /* enable the commented code to assert on wrong method */
8219 if (amd64_is_imm32 (item->key))
8220 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
8222 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8223 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8225 item->jmp_code = code;
8226 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8227 /* See the comment below about R10 */
8228 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8229 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8230 amd64_patch (item->jmp_code, code);
8231 amd64_breakpoint (code);
8232 item->jmp_code = NULL;
8234 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8235 needs to be preserved. R10 needs
8236 to be preserved for calls which
8237 require a runtime generic context,
8238 but interface calls don't. */
8239 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8240 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8244 if (amd64_is_imm32 (item->key))
8245 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
8247 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8248 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8250 item->jmp_code = code;
8251 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8252 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8254 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8256 g_assert (code - item->code_target <= item->chunk_size);
8258 /* patch the branches to get to the target items */
8259 for (i = 0; i < count; ++i) {
8260 MonoIMTCheckItem *item = imt_entries [i];
8261 if (item->jmp_code) {
8262 if (item->check_target_idx) {
8263 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8269 mono_stats.imt_thunks_size += code - start;
8270 g_assert (code - start <= size);
8272 nacl_domain_code_validate(domain, &start, size, &code);
8278 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8280 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8285 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8287 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8291 mono_arch_get_cie_program (void)
8295 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8296 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8302 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8304 MonoInst *ins = NULL;
8307 if (cmethod->klass == mono_defaults.math_class) {
8308 if (strcmp (cmethod->name, "Sin") == 0) {
8310 } else if (strcmp (cmethod->name, "Cos") == 0) {
8312 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8314 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8319 MONO_INST_NEW (cfg, ins, opcode);
8320 ins->type = STACK_R8;
8321 ins->dreg = mono_alloc_freg (cfg);
8322 ins->sreg1 = args [0]->dreg;
8323 MONO_ADD_INS (cfg->cbb, ins);
8327 if (cfg->opt & MONO_OPT_CMOV) {
8328 if (strcmp (cmethod->name, "Min") == 0) {
8329 if (fsig->params [0]->type == MONO_TYPE_I4)
8331 if (fsig->params [0]->type == MONO_TYPE_U4)
8332 opcode = OP_IMIN_UN;
8333 else if (fsig->params [0]->type == MONO_TYPE_I8)
8335 else if (fsig->params [0]->type == MONO_TYPE_U8)
8336 opcode = OP_LMIN_UN;
8337 } else if (strcmp (cmethod->name, "Max") == 0) {
8338 if (fsig->params [0]->type == MONO_TYPE_I4)
8340 if (fsig->params [0]->type == MONO_TYPE_U4)
8341 opcode = OP_IMAX_UN;
8342 else if (fsig->params [0]->type == MONO_TYPE_I8)
8344 else if (fsig->params [0]->type == MONO_TYPE_U8)
8345 opcode = OP_LMAX_UN;
8350 MONO_INST_NEW (cfg, ins, opcode);
8351 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8352 ins->dreg = mono_alloc_ireg (cfg);
8353 ins->sreg1 = args [0]->dreg;
8354 ins->sreg2 = args [1]->dreg;
8355 MONO_ADD_INS (cfg->cbb, ins);
8359 /* OP_FREM is not IEEE compatible */
8360 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8361 MONO_INST_NEW (cfg, ins, OP_FREM);
8362 ins->inst_i0 = args [0];
8363 ins->inst_i1 = args [1];
8369 * Can't implement CompareExchange methods this way since they have
8377 mono_arch_print_tree (MonoInst *tree, int arity)
8382 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
8386 if (appdomain_tls_offset == -1)
8389 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
8390 ins->inst_offset = appdomain_tls_offset;
8394 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8397 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8400 case AMD64_RCX: return ctx->rcx;
8401 case AMD64_RDX: return ctx->rdx;
8402 case AMD64_RBX: return ctx->rbx;
8403 case AMD64_RBP: return ctx->rbp;
8404 case AMD64_RSP: return ctx->rsp;
8407 return _CTX_REG (ctx, rax, reg);
8409 return _CTX_REG (ctx, r12, reg - 12);
8411 g_assert_not_reached ();
8416 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8436 _CTX_REG (ctx, rax, reg) = val;
8438 _CTX_REG (ctx, r12, reg - 12) = val;
8440 g_assert_not_reached ();
8444 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8446 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8449 gpointer *sp, old_value;
8451 const unsigned char *handler;
8453 /*Decode the first instruction to figure out where did we store the spvar*/
8454 /*Our jit MUST generate the following:
8457 Which is encoded as: REX.W 0x89 mod_rm
8458 mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8459 mod (reg + imm8): 01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8460 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8462 FIXME can we generate frameless methods on this case?
8465 handler = clause->handler_start;
8468 if (*handler != 0x48)
8473 if (*handler != 0x89)
8477 if (*handler == 0x65)
8478 offset = *(signed char*)(handler + 1);
8479 else if (*handler == 0xA5)
8480 offset = *(int*)(handler + 1);
8485 bp = MONO_CONTEXT_GET_BP (ctx);
8486 sp = *(gpointer*)(bp + offset);
8489 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8498 * mono_arch_emit_load_aotconst:
8500 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8501 * TARGET from the mscorlib GOT in full-aot code.
8502 * On AMD64, the result is placed into R11.
8505 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8507 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8508 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8514 * mono_arch_get_trampolines:
8516 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8520 mono_arch_get_trampolines (gboolean aot)
8522 return mono_amd64_get_exception_trampolines (aot);
8525 /* Soft Debug support */
8526 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8529 * mono_arch_set_breakpoint:
8531 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8532 * The location should contain code emitted by OP_SEQ_POINT.
8535 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8538 guint8 *orig_code = code;
8541 guint32 native_offset = ip - (guint8*)ji->code_start;
8542 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8544 g_assert (info->bp_addrs [native_offset] == 0);
8545 info->bp_addrs [native_offset] = bp_trigger_page;
8548 * In production, we will use int3 (has to fix the size in the md
8549 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8552 g_assert (code [0] == 0x90);
8553 if (breakpoint_size == 8) {
8554 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8556 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8557 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8560 g_assert (code - orig_code == breakpoint_size);
8565 * mono_arch_clear_breakpoint:
8567 * Clear the breakpoint at IP.
8570 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8576 guint32 native_offset = ip - (guint8*)ji->code_start;
8577 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8579 g_assert (info->bp_addrs [native_offset] == 0);
8580 info->bp_addrs [native_offset] = info;
8582 for (i = 0; i < breakpoint_size; ++i)
8588 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8591 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8594 siginfo_t* sinfo = (siginfo_t*) info;
8595 /* Sometimes the address is off by 4 */
8596 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8604 * mono_arch_skip_breakpoint:
8606 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8607 * we resume, the instruction is not executed again.
8610 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8613 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8614 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8616 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8621 * mono_arch_start_single_stepping:
8623 * Start single stepping.
8626 mono_arch_start_single_stepping (void)
8628 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8632 * mono_arch_stop_single_stepping:
8634 * Stop single stepping.
8637 mono_arch_stop_single_stepping (void)
8639 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8643 * mono_arch_is_single_step_event:
8645 * Return whenever the machine state in SIGCTX corresponds to a single
8649 mono_arch_is_single_step_event (void *info, void *sigctx)
8652 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8655 siginfo_t* sinfo = (siginfo_t*) info;
8656 /* Sometimes the address is off by 4 */
8657 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8665 * mono_arch_skip_single_step:
8667 * Modify CTX so the ip is placed after the single step trigger instruction,
8668 * we resume, the instruction is not executed again.
8671 mono_arch_skip_single_step (MonoContext *ctx)
8673 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8677 * mono_arch_create_seq_point_info:
8679 * Return a pointer to a data structure which is used by the sequence
8680 * point implementation in AOTed code.
8683 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8689 // FIXME: Add a free function
8691 mono_domain_lock (domain);
8692 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8694 mono_domain_unlock (domain);
8697 ji = mono_jit_info_table_find (domain, (char*)code);
8700 // FIXME: Optimize the size
8701 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8703 info->ss_trigger_page = ss_trigger_page;
8704 info->bp_trigger_page = bp_trigger_page;
8705 /* Initialize to a valid address */
8706 for (i = 0; i < ji->code_size; ++i)
8707 info->bp_addrs [i] = info;
8709 mono_domain_lock (domain);
8710 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8712 mono_domain_unlock (domain);