2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/abi-details.h>
24 #include <mono/metadata/appdomain.h>
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/threads.h>
27 #include <mono/metadata/profiler-private.h>
28 #include <mono/metadata/mono-debug.h>
29 #include <mono/metadata/gc-internal.h>
30 #include <mono/utils/mono-math.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-tls.h>
34 #include <mono/utils/mono-hwcap-x86.h>
38 #include "mini-amd64.h"
39 #include "cpu-amd64.h"
40 #include "debugger-agent.h"
44 static gboolean optimize_for_xen = TRUE;
46 #define optimize_for_xen 0
49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
56 /* Under windows, the calling convention is never stdcall */
57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
62 /* This mutex protects architecture specific caches */
63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
65 static mono_mutex_t mini_arch_mutex;
68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
71 * The code generated for sequence points reads from this location, which is
72 * made read-only when single stepping is enabled.
74 static gpointer ss_trigger_page;
76 /* Enabled breakpoints read from this trigger page */
77 static gpointer bp_trigger_page;
79 /* The size of the breakpoint sequence */
80 static int breakpoint_size;
82 /* The size of the breakpoint instruction causing the actual fault */
83 static int breakpoint_fault_size;
85 /* The size of the single step instruction causing the actual fault */
86 static int single_step_fault_size;
88 /* Offset between fp and the first argument in the callee */
89 #define ARGS_OFFSET 16
90 #define GP_SCRATCH_REG AMD64_R11
93 * AMD64 register usage:
94 * - callee saved registers are used for global register allocation
95 * - %r11 is used for materializing 64 bit constants in opcodes
96 * - the rest is used for local allocation
100 * Floating point comparison results:
110 mono_arch_regname (int reg)
113 case AMD64_RAX: return "%rax";
114 case AMD64_RBX: return "%rbx";
115 case AMD64_RCX: return "%rcx";
116 case AMD64_RDX: return "%rdx";
117 case AMD64_RSP: return "%rsp";
118 case AMD64_RBP: return "%rbp";
119 case AMD64_RDI: return "%rdi";
120 case AMD64_RSI: return "%rsi";
121 case AMD64_R8: return "%r8";
122 case AMD64_R9: return "%r9";
123 case AMD64_R10: return "%r10";
124 case AMD64_R11: return "%r11";
125 case AMD64_R12: return "%r12";
126 case AMD64_R13: return "%r13";
127 case AMD64_R14: return "%r14";
128 case AMD64_R15: return "%r15";
133 static const char * packed_xmmregs [] = {
134 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
135 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
138 static const char * single_xmmregs [] = {
139 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
140 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
144 mono_arch_fregname (int reg)
146 if (reg < AMD64_XMM_NREG)
147 return single_xmmregs [reg];
153 mono_arch_xregname (int reg)
155 if (reg < AMD64_XMM_NREG)
156 return packed_xmmregs [reg];
165 return mono_debug_count ();
171 static inline gboolean
172 amd64_is_near_call (guint8 *code)
175 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
178 return code [0] == 0xe8;
181 #ifdef __native_client_codegen__
183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
184 /* for any given instruction. For instance, amd64_call_reg resolves to */
185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
186 /* We only want to force bundle alignment for the top level instruction, */
187 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
188 static MonoNativeTlsKey nacl_instruction_depth;
190 static MonoNativeTlsKey nacl_rex_tag;
191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
194 amd64_nacl_clear_legacy_prefix_tag ()
196 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
200 amd64_nacl_tag_legacy_prefix (guint8* code)
202 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
203 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
207 amd64_nacl_tag_rex (guint8* code)
209 mono_native_tls_set_value (nacl_rex_tag, code);
213 amd64_nacl_get_legacy_prefix_tag ()
215 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
219 amd64_nacl_get_rex_tag ()
221 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
224 /* Increment the instruction "depth" described above */
226 amd64_nacl_instruction_pre ()
228 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
230 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
234 /* alignment if depth == 0 (top level instruction) */
235 /* IN: start, end pointers to instruction beginning and end */
236 /* OUT: start, end pointers to beginning and end after possible alignment */
237 /* GLOBALS: nacl_instruction_depth defined above */
239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
241 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
243 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
245 g_assert ( depth >= 0 );
247 uintptr_t space_in_block;
249 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
250 /* if legacy prefix is present, and if it was emitted before */
251 /* the start of the instruction sequence, adjust the start */
252 if (prefix != NULL && prefix < *start) {
253 g_assert (*start - prefix <= 3);/* only 3 are allowed */
256 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
257 instlen = (uintptr_t)(*end - *start);
258 /* Only check for instructions which are less than */
259 /* kNaClAlignment. The only instructions that should ever */
260 /* be that long are call sequences, which are already */
261 /* padded out to align the return to the next bundle. */
262 if (instlen > space_in_block && instlen < kNaClAlignment) {
263 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
264 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
265 const size_t length = (size_t)((*end)-(*start));
266 g_assert (length < MAX_NACL_INST_LENGTH);
268 memcpy (copy_of_instruction, *start, length);
269 *start = mono_arch_nacl_pad (*start, space_in_block);
270 memcpy (*start, copy_of_instruction, length);
271 *end = *start + length;
273 amd64_nacl_clear_legacy_prefix_tag ();
274 amd64_nacl_tag_rex (NULL);
278 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
279 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
280 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
281 /* make sure the upper 32-bits are cleared, and use that register in the */
282 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
284 /* pointer to current instruction stream (in the */
285 /* middle of an instruction, after opcode is emitted) */
286 /* basereg/offset/dreg */
287 /* operands of normal membase address */
289 /* pointer to the end of the membase/memindex emit */
290 /* GLOBALS: nacl_rex_tag */
291 /* position in instruction stream that rex prefix was emitted */
292 /* nacl_legacy_prefix_tag */
293 /* (possibly NULL) position in instruction of legacy x86 prefix */
295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
297 gint8 true_basereg = basereg;
299 /* Cache these values, they might change */
300 /* as new instructions are emitted below. */
301 guint8* rex_tag = amd64_nacl_get_rex_tag ();
302 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
304 /* 'basereg' is given masked to 0x7 at this point, so check */
305 /* the rex prefix to see if this is an extended register. */
306 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
310 #define X86_LEA_OPCODE (0x8D)
312 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
313 guint8* old_instruction_start;
315 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
316 /* 32-bits of the old base register (new index register) */
318 guint8* buf_ptr = buf;
321 g_assert (rex_tag != NULL);
323 if (IS_REX(*rex_tag)) {
324 /* The old rex.B should be the new rex.X */
325 if (*rex_tag & AMD64_REX_B) {
326 *rex_tag |= AMD64_REX_X;
328 /* Since our new base is %r15 set rex.B */
329 *rex_tag |= AMD64_REX_B;
331 /* Shift the instruction by one byte */
332 /* so we can insert a rex prefix */
333 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
335 /* New rex prefix only needs rex.B for %r15 base */
336 *rex_tag = AMD64_REX(AMD64_REX_B);
339 if (legacy_prefix_tag) {
340 old_instruction_start = legacy_prefix_tag;
342 old_instruction_start = rex_tag;
345 /* Clears the upper 32-bits of the previous base register */
346 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
347 insert_len = buf_ptr - buf;
349 /* Move the old instruction forward to make */
350 /* room for 'mov' stored in 'buf_ptr' */
351 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
353 memcpy (old_instruction_start, buf, insert_len);
355 /* Sandboxed replacement for the normal membase_emit */
356 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
359 /* Normal default behavior, emit membase memory location */
360 x86_membase_emit_body (*code, dreg, basereg, offset);
365 static inline unsigned char*
366 amd64_skip_nops (unsigned char* code)
371 if ( code[0] == 0x90) {
375 if ( code[0] == 0x66 && code[1] == 0x90) {
379 if (code[0] == 0x0f && code[1] == 0x1f
380 && code[2] == 0x00) {
384 if (code[0] == 0x0f && code[1] == 0x1f
385 && code[2] == 0x40 && code[3] == 0x00) {
389 if (code[0] == 0x0f && code[1] == 0x1f
390 && code[2] == 0x44 && code[3] == 0x00
391 && code[4] == 0x00) {
395 if (code[0] == 0x66 && code[1] == 0x0f
396 && code[2] == 0x1f && code[3] == 0x44
397 && code[4] == 0x00 && code[5] == 0x00) {
401 if (code[0] == 0x0f && code[1] == 0x1f
402 && code[2] == 0x80 && code[3] == 0x00
403 && code[4] == 0x00 && code[5] == 0x00
404 && code[6] == 0x00) {
408 if (code[0] == 0x0f && code[1] == 0x1f
409 && code[2] == 0x84 && code[3] == 0x00
410 && code[4] == 0x00 && code[5] == 0x00
411 && code[6] == 0x00 && code[7] == 0x00) {
420 mono_arch_nacl_skip_nops (guint8* code)
422 return amd64_skip_nops(code);
425 #endif /*__native_client_codegen__*/
428 amd64_patch (unsigned char* code, gpointer target)
432 #ifdef __native_client_codegen__
433 code = amd64_skip_nops (code);
435 #if defined(__native_client_codegen__) && defined(__native_client__)
436 if (nacl_is_code_address (code)) {
437 /* For tail calls, code is patched after being installed */
438 /* but not through the normal "patch callsite" method. */
439 unsigned char buf[kNaClAlignment];
440 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
442 memcpy (buf, aligned_code, kNaClAlignment);
443 /* Patch a temp buffer of bundle size, */
444 /* then install to actual location. */
445 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
446 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
450 target = nacl_modify_patch_target (target);
454 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
459 if ((code [0] & 0xf8) == 0xb8) {
460 /* amd64_set_reg_template */
461 *(guint64*)(code + 1) = (guint64)target;
463 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
464 /* mov 0(%rip), %dreg */
465 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
467 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
468 /* call *<OFFSET>(%rip) */
469 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
471 else if (code [0] == 0xe8) {
473 gint64 disp = (guint8*)target - (guint8*)code;
474 g_assert (amd64_is_imm32 (disp));
475 x86_patch (code, (unsigned char*)target);
478 x86_patch (code, (unsigned char*)target);
482 mono_amd64_patch (unsigned char* code, gpointer target)
484 amd64_patch (code, target);
493 ArgValuetypeAddrInIReg,
494 ArgNone /* only in pair_storage */
502 /* Only if storage == ArgValuetypeInReg */
503 ArgStorage pair_storage [2];
513 gboolean need_stack_align;
514 gboolean vtype_retaddr;
515 /* The index of the vret arg in the argument list */
522 #define DEBUG(a) if (cfg->verbose_level > 1) a
525 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
527 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
529 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
531 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
535 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
537 ainfo->offset = *stack_size;
539 if (*gr >= PARAM_REGS) {
540 ainfo->storage = ArgOnStack;
541 /* Since the same stack slot size is used for all arg */
542 /* types, it needs to be big enough to hold them all */
543 (*stack_size) += sizeof(mgreg_t);
546 ainfo->storage = ArgInIReg;
547 ainfo->reg = param_regs [*gr];
553 #define FLOAT_PARAM_REGS 4
555 #define FLOAT_PARAM_REGS 8
559 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
561 ainfo->offset = *stack_size;
563 if (*gr >= FLOAT_PARAM_REGS) {
564 ainfo->storage = ArgOnStack;
565 /* Since the same stack slot size is used for both float */
566 /* types, it needs to be big enough to hold them both */
567 (*stack_size) += sizeof(mgreg_t);
570 /* A double register */
572 ainfo->storage = ArgInDoubleSSEReg;
574 ainfo->storage = ArgInFloatSSEReg;
580 typedef enum ArgumentClass {
588 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
590 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
593 ptype = mini_type_get_underlying_type (gsctx, type);
594 switch (ptype->type) {
595 case MONO_TYPE_BOOLEAN:
605 case MONO_TYPE_STRING:
606 case MONO_TYPE_OBJECT:
607 case MONO_TYPE_CLASS:
608 case MONO_TYPE_SZARRAY:
610 case MONO_TYPE_FNPTR:
611 case MONO_TYPE_ARRAY:
614 class2 = ARG_CLASS_INTEGER;
619 class2 = ARG_CLASS_INTEGER;
621 class2 = ARG_CLASS_SSE;
625 case MONO_TYPE_TYPEDBYREF:
626 g_assert_not_reached ();
628 case MONO_TYPE_GENERICINST:
629 if (!mono_type_generic_inst_is_valuetype (ptype)) {
630 class2 = ARG_CLASS_INTEGER;
634 case MONO_TYPE_VALUETYPE: {
635 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
638 for (i = 0; i < info->num_fields; ++i) {
640 class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
645 g_assert_not_reached ();
649 if (class1 == class2)
651 else if (class1 == ARG_CLASS_NO_CLASS)
653 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
654 class1 = ARG_CLASS_MEMORY;
655 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
656 class1 = ARG_CLASS_INTEGER;
658 class1 = ARG_CLASS_SSE;
662 #ifdef __native_client_codegen__
664 /* Default alignment for Native Client is 32-byte. */
665 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
667 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
668 /* Check that alignment doesn't cross an alignment boundary. */
670 mono_arch_nacl_pad(guint8 *code, int pad)
672 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
674 if (pad == 0) return code;
675 /* assertion: alignment cannot cross a block boundary */
676 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
677 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
678 while (pad >= kMaxPadding) {
679 amd64_padding (code, kMaxPadding);
682 if (pad != 0) amd64_padding (code, pad);
688 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
690 guint32 *gr, guint32 *fr, guint32 *stack_size)
692 guint32 size, quad, nquads, i;
693 /* Keep track of the size used in each quad so we can */
694 /* use the right size when copying args/return vars. */
695 guint32 quadsize [2] = {8, 8};
696 ArgumentClass args [2];
697 MonoMarshalType *info = NULL;
699 MonoGenericSharingContext tmp_gsctx;
700 gboolean pass_on_stack = FALSE;
703 * The gsctx currently contains no data, it is only used for checking whenever
704 * open types are allowed, some callers like mono_arch_get_argument_info ()
705 * don't pass it to us, so work around that.
710 klass = mono_class_from_mono_type (type);
711 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
713 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
714 /* We pass and return vtypes of size 8 in a register */
715 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
716 pass_on_stack = TRUE;
720 pass_on_stack = TRUE;
724 /* If this struct can't be split up naturally into 8-byte */
725 /* chunks (registers), pass it on the stack. */
726 if (sig->pinvoke && !pass_on_stack) {
730 info = mono_marshal_load_type_info (klass);
732 for (i = 0; i < info->num_fields; ++i) {
733 field_size = mono_marshal_type_size (info->fields [i].field->type,
734 info->fields [i].mspec,
735 &align, TRUE, klass->unicode);
736 if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
737 pass_on_stack = TRUE;
744 /* Allways pass in memory */
745 ainfo->offset = *stack_size;
746 *stack_size += ALIGN_TO (size, 8);
747 ainfo->storage = ArgOnStack;
752 /* FIXME: Handle structs smaller than 8 bytes */
753 //if ((size % 8) != 0)
762 /* Always pass in 1 or 2 integer registers */
763 args [0] = ARG_CLASS_INTEGER;
764 args [1] = ARG_CLASS_INTEGER;
765 /* Only the simplest cases are supported */
766 if (is_return && nquads != 1) {
767 args [0] = ARG_CLASS_MEMORY;
768 args [1] = ARG_CLASS_MEMORY;
772 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
773 * The X87 and SSEUP stuff is left out since there are no such types in
776 info = mono_marshal_load_type_info (klass);
780 if (info->native_size > 16) {
781 ainfo->offset = *stack_size;
782 *stack_size += ALIGN_TO (info->native_size, 8);
783 ainfo->storage = ArgOnStack;
788 switch (info->native_size) {
789 case 1: case 2: case 4: case 8:
793 ainfo->storage = ArgOnStack;
794 ainfo->offset = *stack_size;
795 *stack_size += ALIGN_TO (info->native_size, 8);
798 ainfo->storage = ArgValuetypeAddrInIReg;
800 if (*gr < PARAM_REGS) {
801 ainfo->pair_storage [0] = ArgInIReg;
802 ainfo->pair_regs [0] = param_regs [*gr];
806 ainfo->pair_storage [0] = ArgOnStack;
807 ainfo->offset = *stack_size;
816 args [0] = ARG_CLASS_NO_CLASS;
817 args [1] = ARG_CLASS_NO_CLASS;
818 for (quad = 0; quad < nquads; ++quad) {
821 ArgumentClass class1;
823 if (info->num_fields == 0)
824 class1 = ARG_CLASS_MEMORY;
826 class1 = ARG_CLASS_NO_CLASS;
827 for (i = 0; i < info->num_fields; ++i) {
828 size = mono_marshal_type_size (info->fields [i].field->type,
829 info->fields [i].mspec,
830 &align, TRUE, klass->unicode);
831 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
832 /* Unaligned field */
836 /* Skip fields in other quad */
837 if ((quad == 0) && (info->fields [i].offset >= 8))
839 if ((quad == 1) && (info->fields [i].offset < 8))
842 /* How far into this quad this data extends.*/
843 /* (8 is size of quad) */
844 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
846 class1 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class1);
848 g_assert (class1 != ARG_CLASS_NO_CLASS);
849 args [quad] = class1;
853 /* Post merger cleanup */
854 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
855 args [0] = args [1] = ARG_CLASS_MEMORY;
857 /* Allocate registers */
862 ainfo->storage = ArgValuetypeInReg;
863 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
864 ainfo->nregs = nquads;
865 for (quad = 0; quad < nquads; ++quad) {
866 switch (args [quad]) {
867 case ARG_CLASS_INTEGER:
868 if (*gr >= PARAM_REGS)
869 args [quad] = ARG_CLASS_MEMORY;
871 ainfo->pair_storage [quad] = ArgInIReg;
873 ainfo->pair_regs [quad] = return_regs [*gr];
875 ainfo->pair_regs [quad] = param_regs [*gr];
880 if (*fr >= FLOAT_PARAM_REGS)
881 args [quad] = ARG_CLASS_MEMORY;
883 if (quadsize[quad] <= 4)
884 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
885 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
886 ainfo->pair_regs [quad] = *fr;
890 case ARG_CLASS_MEMORY:
893 g_assert_not_reached ();
897 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
898 /* Revert possible register assignments */
902 ainfo->offset = *stack_size;
904 *stack_size += ALIGN_TO (info->native_size, 8);
906 *stack_size += nquads * sizeof(mgreg_t);
907 ainfo->storage = ArgOnStack;
915 * Obtain information about a call according to the calling convention.
916 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
917 * Draft Version 0.23" document for more information.
920 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
922 guint32 i, gr, fr, pstart;
924 int n = sig->hasthis + sig->param_count;
925 guint32 stack_size = 0;
927 gboolean is_pinvoke = sig->pinvoke;
930 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
932 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
940 /* Reserve space where the callee can save the argument registers */
941 stack_size = 4 * sizeof (mgreg_t);
946 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
947 switch (ret_type->type) {
948 case MONO_TYPE_BOOLEAN:
959 case MONO_TYPE_FNPTR:
960 case MONO_TYPE_CLASS:
961 case MONO_TYPE_OBJECT:
962 case MONO_TYPE_SZARRAY:
963 case MONO_TYPE_ARRAY:
964 case MONO_TYPE_STRING:
965 cinfo->ret.storage = ArgInIReg;
966 cinfo->ret.reg = AMD64_RAX;
970 cinfo->ret.storage = ArgInIReg;
971 cinfo->ret.reg = AMD64_RAX;
974 cinfo->ret.storage = ArgInFloatSSEReg;
975 cinfo->ret.reg = AMD64_XMM0;
978 cinfo->ret.storage = ArgInDoubleSSEReg;
979 cinfo->ret.reg = AMD64_XMM0;
981 case MONO_TYPE_GENERICINST:
982 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
983 cinfo->ret.storage = ArgInIReg;
984 cinfo->ret.reg = AMD64_RAX;
988 #if defined( __native_client_codegen__ )
989 case MONO_TYPE_TYPEDBYREF:
991 case MONO_TYPE_VALUETYPE: {
992 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
994 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
995 if (cinfo->ret.storage == ArgOnStack) {
996 cinfo->vtype_retaddr = TRUE;
997 /* The caller passes the address where the value is stored */
1001 #if !defined( __native_client_codegen__ )
1002 case MONO_TYPE_TYPEDBYREF:
1003 /* Same as a valuetype with size 24 */
1004 cinfo->vtype_retaddr = TRUE;
1007 case MONO_TYPE_VOID:
1010 g_error ("Can't handle as return value 0x%x", ret_type->type);
1016 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1017 * the first argument, allowing 'this' to be always passed in the first arg reg.
1018 * Also do this if the first argument is a reference type, since virtual calls
1019 * are sometimes made using calli without sig->hasthis set, like in the delegate
1022 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1024 add_general (&gr, &stack_size, cinfo->args + 0);
1026 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1029 add_general (&gr, &stack_size, &cinfo->ret);
1030 cinfo->vret_arg_index = 1;
1034 add_general (&gr, &stack_size, cinfo->args + 0);
1036 if (cinfo->vtype_retaddr)
1037 add_general (&gr, &stack_size, &cinfo->ret);
1040 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1042 fr = FLOAT_PARAM_REGS;
1044 /* Emit the signature cookie just before the implicit arguments */
1045 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1048 for (i = pstart; i < sig->param_count; ++i) {
1049 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1053 /* The float param registers and other param registers must be the same index on Windows x64.*/
1060 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1061 /* We allways pass the sig cookie on the stack for simplicity */
1063 * Prevent implicit arguments + the sig cookie from being passed
1067 fr = FLOAT_PARAM_REGS;
1069 /* Emit the signature cookie just before the implicit arguments */
1070 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1073 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1074 switch (ptype->type) {
1075 case MONO_TYPE_BOOLEAN:
1078 add_general (&gr, &stack_size, ainfo);
1082 case MONO_TYPE_CHAR:
1083 add_general (&gr, &stack_size, ainfo);
1087 add_general (&gr, &stack_size, ainfo);
1092 case MONO_TYPE_FNPTR:
1093 case MONO_TYPE_CLASS:
1094 case MONO_TYPE_OBJECT:
1095 case MONO_TYPE_STRING:
1096 case MONO_TYPE_SZARRAY:
1097 case MONO_TYPE_ARRAY:
1098 add_general (&gr, &stack_size, ainfo);
1100 case MONO_TYPE_GENERICINST:
1101 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1102 add_general (&gr, &stack_size, ainfo);
1106 case MONO_TYPE_VALUETYPE:
1107 case MONO_TYPE_TYPEDBYREF:
1108 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1113 add_general (&gr, &stack_size, ainfo);
1116 add_float (&fr, &stack_size, ainfo, FALSE);
1119 add_float (&fr, &stack_size, ainfo, TRUE);
1122 g_assert_not_reached ();
1126 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1128 fr = FLOAT_PARAM_REGS;
1130 /* Emit the signature cookie just before the implicit arguments */
1131 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1134 cinfo->stack_usage = stack_size;
1135 cinfo->reg_usage = gr;
1136 cinfo->freg_usage = fr;
1141 * mono_arch_get_argument_info:
1142 * @csig: a method signature
1143 * @param_count: the number of parameters to consider
1144 * @arg_info: an array to store the result infos
1146 * Gathers information on parameters such as size, alignment and
1147 * padding. arg_info should be large enought to hold param_count + 1 entries.
1149 * Returns the size of the argument area on the stack.
1152 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1155 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1156 guint32 args_size = cinfo->stack_usage;
1158 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1159 if (csig->hasthis) {
1160 arg_info [0].offset = 0;
1163 for (k = 0; k < param_count; k++) {
1164 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1166 arg_info [k + 1].size = 0;
1175 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1179 MonoType *callee_ret;
1181 c1 = get_call_info (NULL, NULL, caller_sig);
1182 c2 = get_call_info (NULL, NULL, callee_sig);
1183 res = c1->stack_usage >= c2->stack_usage;
1184 callee_ret = mini_replace_type (callee_sig->ret);
1185 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1186 /* An address on the callee's stack is passed as the first argument */
1196 * Initialize the cpu to execute managed code.
1199 mono_arch_cpu_init (void)
1204 /* spec compliance requires running with double precision */
1205 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1206 fpcw &= ~X86_FPCW_PRECC_MASK;
1207 fpcw |= X86_FPCW_PREC_DOUBLE;
1208 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1209 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1211 /* TODO: This is crashing on Win64 right now.
1212 * _control87 (_PC_53, MCW_PC);
1218 * Initialize architecture specific code.
1221 mono_arch_init (void)
1225 mono_mutex_init_recursive (&mini_arch_mutex);
1226 #if defined(__native_client_codegen__)
1227 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1228 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1229 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1230 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1233 #ifdef MONO_ARCH_NOMAP32BIT
1234 flags = MONO_MMAP_READ;
1235 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1236 breakpoint_size = 13;
1237 breakpoint_fault_size = 3;
1239 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1240 /* amd64_mov_reg_mem () */
1241 breakpoint_size = 8;
1242 breakpoint_fault_size = 8;
1245 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1246 single_step_fault_size = 4;
1248 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1249 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1250 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1252 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1253 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1254 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1258 * Cleanup architecture specific code.
1261 mono_arch_cleanup (void)
1263 mono_mutex_destroy (&mini_arch_mutex);
1264 #if defined(__native_client_codegen__)
1265 mono_native_tls_free (nacl_instruction_depth);
1266 mono_native_tls_free (nacl_rex_tag);
1267 mono_native_tls_free (nacl_legacy_prefix_tag);
1272 * This function returns the optimizations supported on this cpu.
1275 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1281 if (mono_hwcap_x86_has_cmov) {
1282 opts |= MONO_OPT_CMOV;
1284 if (mono_hwcap_x86_has_fcmov)
1285 opts |= MONO_OPT_FCMOV;
1287 *exclude_mask |= MONO_OPT_FCMOV;
1289 *exclude_mask |= MONO_OPT_CMOV;
1296 * This function test for all SSE functions supported.
1298 * Returns a bitmask corresponding to all supported versions.
1302 mono_arch_cpu_enumerate_simd_versions (void)
1304 guint32 sse_opts = 0;
1306 if (mono_hwcap_x86_has_sse1)
1307 sse_opts |= SIMD_VERSION_SSE1;
1309 if (mono_hwcap_x86_has_sse2)
1310 sse_opts |= SIMD_VERSION_SSE2;
1312 if (mono_hwcap_x86_has_sse3)
1313 sse_opts |= SIMD_VERSION_SSE3;
1315 if (mono_hwcap_x86_has_ssse3)
1316 sse_opts |= SIMD_VERSION_SSSE3;
1318 if (mono_hwcap_x86_has_sse41)
1319 sse_opts |= SIMD_VERSION_SSE41;
1321 if (mono_hwcap_x86_has_sse42)
1322 sse_opts |= SIMD_VERSION_SSE42;
1324 if (mono_hwcap_x86_has_sse4a)
1325 sse_opts |= SIMD_VERSION_SSE4a;
1333 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1338 for (i = 0; i < cfg->num_varinfo; i++) {
1339 MonoInst *ins = cfg->varinfo [i];
1340 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1343 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1346 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1347 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1350 if (mono_is_regsize_var (ins->inst_vtype)) {
1351 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1352 g_assert (i == vmv->idx);
1353 vars = g_list_prepend (vars, vmv);
1357 vars = mono_varlist_sort (cfg, vars, 0);
1363 * mono_arch_compute_omit_fp:
1365 * Determine whenever the frame pointer can be eliminated.
1368 mono_arch_compute_omit_fp (MonoCompile *cfg)
1370 MonoMethodSignature *sig;
1371 MonoMethodHeader *header;
1375 if (cfg->arch.omit_fp_computed)
1378 header = cfg->header;
1380 sig = mono_method_signature (cfg->method);
1382 if (!cfg->arch.cinfo)
1383 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1384 cinfo = cfg->arch.cinfo;
1387 * FIXME: Remove some of the restrictions.
1389 cfg->arch.omit_fp = TRUE;
1390 cfg->arch.omit_fp_computed = TRUE;
1392 #ifdef __native_client_codegen__
1393 /* NaCl modules may not change the value of RBP, so it cannot be */
1394 /* used as a normal register, but it can be used as a frame pointer*/
1395 cfg->disable_omit_fp = TRUE;
1396 cfg->arch.omit_fp = FALSE;
1399 if (cfg->disable_omit_fp)
1400 cfg->arch.omit_fp = FALSE;
1402 if (!debug_omit_fp ())
1403 cfg->arch.omit_fp = FALSE;
1405 if (cfg->method->save_lmf)
1406 cfg->arch.omit_fp = FALSE;
1408 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1409 cfg->arch.omit_fp = FALSE;
1410 if (header->num_clauses)
1411 cfg->arch.omit_fp = FALSE;
1412 if (cfg->param_area)
1413 cfg->arch.omit_fp = FALSE;
1414 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1415 cfg->arch.omit_fp = FALSE;
1416 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1417 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1418 cfg->arch.omit_fp = FALSE;
1419 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1420 ArgInfo *ainfo = &cinfo->args [i];
1422 if (ainfo->storage == ArgOnStack) {
1424 * The stack offset can only be determined when the frame
1427 cfg->arch.omit_fp = FALSE;
1432 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1433 MonoInst *ins = cfg->varinfo [i];
1436 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1441 mono_arch_get_global_int_regs (MonoCompile *cfg)
1445 mono_arch_compute_omit_fp (cfg);
1447 if (cfg->globalra) {
1448 if (cfg->arch.omit_fp)
1449 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1451 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1452 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1453 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1454 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1455 #ifndef __native_client_codegen__
1456 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1459 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1460 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1461 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1462 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1463 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1464 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1465 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1466 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1468 if (cfg->arch.omit_fp)
1469 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1471 /* We use the callee saved registers for global allocation */
1472 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1473 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1474 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1475 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1476 #ifndef __native_client_codegen__
1477 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1480 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1481 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1489 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1494 /* All XMM registers */
1495 for (i = 0; i < 16; ++i)
1496 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1502 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1504 static GList *r = NULL;
1509 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1510 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1511 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1512 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1513 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1514 #ifndef __native_client_codegen__
1515 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1518 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1519 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1520 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1521 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1522 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1523 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1524 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1525 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1527 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1534 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1537 static GList *r = NULL;
1542 for (i = 0; i < AMD64_XMM_NREG; ++i)
1543 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1545 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1552 * mono_arch_regalloc_cost:
1554 * Return the cost, in number of memory references, of the action of
1555 * allocating the variable VMV into a register during global register
1559 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1561 MonoInst *ins = cfg->varinfo [vmv->idx];
1563 if (cfg->method->save_lmf)
1564 /* The register is already saved */
1565 /* substract 1 for the invisible store in the prolog */
1566 return (ins->opcode == OP_ARG) ? 0 : 1;
1569 return (ins->opcode == OP_ARG) ? 1 : 2;
1573 * mono_arch_fill_argument_info:
1575 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1579 mono_arch_fill_argument_info (MonoCompile *cfg)
1582 MonoMethodSignature *sig;
1583 MonoMethodHeader *header;
1588 header = cfg->header;
1590 sig = mono_method_signature (cfg->method);
1592 cinfo = cfg->arch.cinfo;
1593 sig_ret = mini_replace_type (sig->ret);
1596 * Contrary to mono_arch_allocate_vars (), the information should describe
1597 * where the arguments are at the beginning of the method, not where they can be
1598 * accessed during the execution of the method. The later makes no sense for the
1599 * global register allocator, since a variable can be in more than one location.
1601 if (sig_ret->type != MONO_TYPE_VOID) {
1602 switch (cinfo->ret.storage) {
1604 case ArgInFloatSSEReg:
1605 case ArgInDoubleSSEReg:
1606 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1607 cfg->vret_addr->opcode = OP_REGVAR;
1608 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1611 cfg->ret->opcode = OP_REGVAR;
1612 cfg->ret->inst_c0 = cinfo->ret.reg;
1615 case ArgValuetypeInReg:
1616 cfg->ret->opcode = OP_REGOFFSET;
1617 cfg->ret->inst_basereg = -1;
1618 cfg->ret->inst_offset = -1;
1621 g_assert_not_reached ();
1625 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1626 ArgInfo *ainfo = &cinfo->args [i];
1629 ins = cfg->args [i];
1631 if (sig->hasthis && (i == 0))
1632 arg_type = &mono_defaults.object_class->byval_arg;
1634 arg_type = sig->params [i - sig->hasthis];
1636 switch (ainfo->storage) {
1638 case ArgInFloatSSEReg:
1639 case ArgInDoubleSSEReg:
1640 ins->opcode = OP_REGVAR;
1641 ins->inst_c0 = ainfo->reg;
1644 ins->opcode = OP_REGOFFSET;
1645 ins->inst_basereg = -1;
1646 ins->inst_offset = -1;
1648 case ArgValuetypeInReg:
1650 ins->opcode = OP_NOP;
1653 g_assert_not_reached ();
1659 mono_arch_allocate_vars (MonoCompile *cfg)
1662 MonoMethodSignature *sig;
1663 MonoMethodHeader *header;
1666 guint32 locals_stack_size, locals_stack_align;
1670 header = cfg->header;
1672 sig = mono_method_signature (cfg->method);
1674 cinfo = cfg->arch.cinfo;
1675 sig_ret = mini_replace_type (sig->ret);
1677 mono_arch_compute_omit_fp (cfg);
1680 * We use the ABI calling conventions for managed code as well.
1681 * Exception: valuetypes are only sometimes passed or returned in registers.
1685 * The stack looks like this:
1686 * <incoming arguments passed on the stack>
1688 * <lmf/caller saved registers>
1691 * <localloc area> -> grows dynamically
1695 if (cfg->arch.omit_fp) {
1696 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1697 cfg->frame_reg = AMD64_RSP;
1700 /* Locals are allocated backwards from %fp */
1701 cfg->frame_reg = AMD64_RBP;
1705 cfg->arch.saved_iregs = cfg->used_int_regs;
1706 if (cfg->method->save_lmf)
1707 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1708 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1710 if (cfg->arch.omit_fp)
1711 cfg->arch.reg_save_area_offset = offset;
1712 /* Reserve space for callee saved registers */
1713 for (i = 0; i < AMD64_NREG; ++i)
1714 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1715 offset += sizeof(mgreg_t);
1717 if (!cfg->arch.omit_fp)
1718 cfg->arch.reg_save_area_offset = -offset;
1720 if (sig_ret->type != MONO_TYPE_VOID) {
1721 switch (cinfo->ret.storage) {
1723 case ArgInFloatSSEReg:
1724 case ArgInDoubleSSEReg:
1725 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1726 if (cfg->globalra) {
1727 cfg->vret_addr->opcode = OP_REGVAR;
1728 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1730 /* The register is volatile */
1731 cfg->vret_addr->opcode = OP_REGOFFSET;
1732 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1733 if (cfg->arch.omit_fp) {
1734 cfg->vret_addr->inst_offset = offset;
1738 cfg->vret_addr->inst_offset = -offset;
1740 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1741 printf ("vret_addr =");
1742 mono_print_ins (cfg->vret_addr);
1747 cfg->ret->opcode = OP_REGVAR;
1748 cfg->ret->inst_c0 = cinfo->ret.reg;
1751 case ArgValuetypeInReg:
1752 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1753 cfg->ret->opcode = OP_REGOFFSET;
1754 cfg->ret->inst_basereg = cfg->frame_reg;
1755 if (cfg->arch.omit_fp) {
1756 cfg->ret->inst_offset = offset;
1757 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1759 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1760 cfg->ret->inst_offset = - offset;
1764 g_assert_not_reached ();
1767 cfg->ret->dreg = cfg->ret->inst_c0;
1770 /* Allocate locals */
1771 if (!cfg->globalra) {
1772 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1773 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1774 char *mname = mono_method_full_name (cfg->method, TRUE);
1775 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1776 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1781 if (locals_stack_align) {
1782 offset += (locals_stack_align - 1);
1783 offset &= ~(locals_stack_align - 1);
1785 if (cfg->arch.omit_fp) {
1786 cfg->locals_min_stack_offset = offset;
1787 cfg->locals_max_stack_offset = offset + locals_stack_size;
1789 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1790 cfg->locals_max_stack_offset = - offset;
1793 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1794 if (offsets [i] != -1) {
1795 MonoInst *ins = cfg->varinfo [i];
1796 ins->opcode = OP_REGOFFSET;
1797 ins->inst_basereg = cfg->frame_reg;
1798 if (cfg->arch.omit_fp)
1799 ins->inst_offset = (offset + offsets [i]);
1801 ins->inst_offset = - (offset + offsets [i]);
1802 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1805 offset += locals_stack_size;
1808 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1809 g_assert (!cfg->arch.omit_fp);
1810 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1811 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1814 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1815 ins = cfg->args [i];
1816 if (ins->opcode != OP_REGVAR) {
1817 ArgInfo *ainfo = &cinfo->args [i];
1818 gboolean inreg = TRUE;
1821 if (sig->hasthis && (i == 0))
1822 arg_type = &mono_defaults.object_class->byval_arg;
1824 arg_type = sig->params [i - sig->hasthis];
1826 if (cfg->globalra) {
1827 /* The new allocator needs info about the original locations of the arguments */
1828 switch (ainfo->storage) {
1830 case ArgInFloatSSEReg:
1831 case ArgInDoubleSSEReg:
1832 ins->opcode = OP_REGVAR;
1833 ins->inst_c0 = ainfo->reg;
1836 g_assert (!cfg->arch.omit_fp);
1837 ins->opcode = OP_REGOFFSET;
1838 ins->inst_basereg = cfg->frame_reg;
1839 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1841 case ArgValuetypeInReg:
1842 ins->opcode = OP_REGOFFSET;
1843 ins->inst_basereg = cfg->frame_reg;
1844 /* These arguments are saved to the stack in the prolog */
1845 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1846 if (cfg->arch.omit_fp) {
1847 ins->inst_offset = offset;
1848 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1850 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1851 ins->inst_offset = - offset;
1855 g_assert_not_reached ();
1861 /* FIXME: Allocate volatile arguments to registers */
1862 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1866 * Under AMD64, all registers used to pass arguments to functions
1867 * are volatile across calls.
1868 * FIXME: Optimize this.
1870 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1873 ins->opcode = OP_REGOFFSET;
1875 switch (ainfo->storage) {
1877 case ArgInFloatSSEReg:
1878 case ArgInDoubleSSEReg:
1880 ins->opcode = OP_REGVAR;
1881 ins->dreg = ainfo->reg;
1885 g_assert (!cfg->arch.omit_fp);
1886 ins->opcode = OP_REGOFFSET;
1887 ins->inst_basereg = cfg->frame_reg;
1888 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1890 case ArgValuetypeInReg:
1892 case ArgValuetypeAddrInIReg: {
1894 g_assert (!cfg->arch.omit_fp);
1896 MONO_INST_NEW (cfg, indir, 0);
1897 indir->opcode = OP_REGOFFSET;
1898 if (ainfo->pair_storage [0] == ArgInIReg) {
1899 indir->inst_basereg = cfg->frame_reg;
1900 offset = ALIGN_TO (offset, sizeof (gpointer));
1901 offset += (sizeof (gpointer));
1902 indir->inst_offset = - offset;
1905 indir->inst_basereg = cfg->frame_reg;
1906 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1909 ins->opcode = OP_VTARG_ADDR;
1910 ins->inst_left = indir;
1918 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1919 ins->opcode = OP_REGOFFSET;
1920 ins->inst_basereg = cfg->frame_reg;
1921 /* These arguments are saved to the stack in the prolog */
1922 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1923 if (cfg->arch.omit_fp) {
1924 ins->inst_offset = offset;
1925 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1926 // Arguments are yet supported by the stack map creation code
1927 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1929 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1930 ins->inst_offset = - offset;
1931 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1937 cfg->stack_offset = offset;
1941 mono_arch_create_vars (MonoCompile *cfg)
1943 MonoMethodSignature *sig;
1947 sig = mono_method_signature (cfg->method);
1949 if (!cfg->arch.cinfo)
1950 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1951 cinfo = cfg->arch.cinfo;
1953 if (cinfo->ret.storage == ArgValuetypeInReg)
1954 cfg->ret_var_is_local = TRUE;
1956 sig_ret = mini_replace_type (sig->ret);
1957 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1958 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1959 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1960 printf ("vret_addr = ");
1961 mono_print_ins (cfg->vret_addr);
1965 if (cfg->gen_seq_points) {
1968 if (cfg->compile_aot) {
1969 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1970 ins->flags |= MONO_INST_VOLATILE;
1971 cfg->arch.seq_point_info_var = ins;
1974 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1975 ins->flags |= MONO_INST_VOLATILE;
1976 cfg->arch.ss_trigger_page_var = ins;
1979 if (cfg->method->save_lmf)
1980 cfg->create_lmf_var = TRUE;
1982 if (cfg->method->save_lmf) {
1984 #if !defined(HOST_WIN32)
1985 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1986 cfg->lmf_ir_mono_lmf = TRUE;
1992 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1998 MONO_INST_NEW (cfg, ins, OP_MOVE);
1999 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2000 ins->sreg1 = tree->dreg;
2001 MONO_ADD_INS (cfg->cbb, ins);
2002 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2004 case ArgInFloatSSEReg:
2005 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2006 ins->dreg = mono_alloc_freg (cfg);
2007 ins->sreg1 = tree->dreg;
2008 MONO_ADD_INS (cfg->cbb, ins);
2010 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2012 case ArgInDoubleSSEReg:
2013 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2014 ins->dreg = mono_alloc_freg (cfg);
2015 ins->sreg1 = tree->dreg;
2016 MONO_ADD_INS (cfg->cbb, ins);
2018 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2022 g_assert_not_reached ();
2027 arg_storage_to_load_membase (ArgStorage storage)
2031 #if defined(__mono_ilp32__)
2032 return OP_LOADI8_MEMBASE;
2034 return OP_LOAD_MEMBASE;
2036 case ArgInDoubleSSEReg:
2037 return OP_LOADR8_MEMBASE;
2038 case ArgInFloatSSEReg:
2039 return OP_LOADR4_MEMBASE;
2041 g_assert_not_reached ();
2048 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2050 MonoMethodSignature *tmp_sig;
2053 if (call->tail_call)
2056 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2059 * mono_ArgIterator_Setup assumes the signature cookie is
2060 * passed first and all the arguments which were before it are
2061 * passed on the stack after the signature. So compensate by
2062 * passing a different signature.
2064 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2065 tmp_sig->param_count -= call->signature->sentinelpos;
2066 tmp_sig->sentinelpos = 0;
2067 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2069 sig_reg = mono_alloc_ireg (cfg);
2070 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2072 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2075 static inline LLVMArgStorage
2076 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2080 return LLVMArgInIReg;
2084 g_assert_not_reached ();
2091 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2097 LLVMCallInfo *linfo;
2098 MonoType *t, *sig_ret;
2100 n = sig->param_count + sig->hasthis;
2101 sig_ret = mini_replace_type (sig->ret);
2103 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2105 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2108 * LLVM always uses the native ABI while we use our own ABI, the
2109 * only difference is the handling of vtypes:
2110 * - we only pass/receive them in registers in some cases, and only
2111 * in 1 or 2 integer registers.
2113 if (cinfo->ret.storage == ArgValuetypeInReg) {
2115 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2116 cfg->disable_llvm = TRUE;
2120 linfo->ret.storage = LLVMArgVtypeInReg;
2121 for (j = 0; j < 2; ++j)
2122 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2125 if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2126 /* Vtype returned using a hidden argument */
2127 linfo->ret.storage = LLVMArgVtypeRetAddr;
2128 linfo->vret_arg_index = cinfo->vret_arg_index;
2131 for (i = 0; i < n; ++i) {
2132 ainfo = cinfo->args + i;
2134 if (i >= sig->hasthis)
2135 t = sig->params [i - sig->hasthis];
2137 t = &mono_defaults.int_class->byval_arg;
2139 linfo->args [i].storage = LLVMArgNone;
2141 switch (ainfo->storage) {
2143 linfo->args [i].storage = LLVMArgInIReg;
2145 case ArgInDoubleSSEReg:
2146 case ArgInFloatSSEReg:
2147 linfo->args [i].storage = LLVMArgInFPReg;
2150 if (MONO_TYPE_ISSTRUCT (t)) {
2151 linfo->args [i].storage = LLVMArgVtypeByVal;
2153 linfo->args [i].storage = LLVMArgInIReg;
2155 if (t->type == MONO_TYPE_R4)
2156 linfo->args [i].storage = LLVMArgInFPReg;
2157 else if (t->type == MONO_TYPE_R8)
2158 linfo->args [i].storage = LLVMArgInFPReg;
2162 case ArgValuetypeInReg:
2164 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2165 cfg->disable_llvm = TRUE;
2169 linfo->args [i].storage = LLVMArgVtypeInReg;
2170 for (j = 0; j < 2; ++j)
2171 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2174 cfg->exception_message = g_strdup ("ainfo->storage");
2175 cfg->disable_llvm = TRUE;
2185 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2188 MonoMethodSignature *sig;
2190 int i, n, stack_size;
2196 sig = call->signature;
2197 n = sig->param_count + sig->hasthis;
2199 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2203 if (COMPILE_LLVM (cfg)) {
2204 /* We shouldn't be called in the llvm case */
2205 cfg->disable_llvm = TRUE;
2210 * Emit all arguments which are passed on the stack to prevent register
2211 * allocation problems.
2213 for (i = 0; i < n; ++i) {
2215 ainfo = cinfo->args + i;
2217 in = call->args [i];
2219 if (sig->hasthis && i == 0)
2220 t = &mono_defaults.object_class->byval_arg;
2222 t = sig->params [i - sig->hasthis];
2224 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2226 if (t->type == MONO_TYPE_R4)
2227 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2228 else if (t->type == MONO_TYPE_R8)
2229 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2231 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2233 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2235 if (cfg->compute_gc_maps) {
2238 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2244 * Emit all parameters passed in registers in non-reverse order for better readability
2245 * and to help the optimization in emit_prolog ().
2247 for (i = 0; i < n; ++i) {
2248 ainfo = cinfo->args + i;
2250 in = call->args [i];
2252 if (ainfo->storage == ArgInIReg)
2253 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2256 for (i = n - 1; i >= 0; --i) {
2257 ainfo = cinfo->args + i;
2259 in = call->args [i];
2261 switch (ainfo->storage) {
2265 case ArgInFloatSSEReg:
2266 case ArgInDoubleSSEReg:
2267 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2270 case ArgValuetypeInReg:
2271 case ArgValuetypeAddrInIReg:
2272 if (ainfo->storage == ArgOnStack && call->tail_call) {
2273 MonoInst *call_inst = (MonoInst*)call;
2274 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2275 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2276 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2280 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2281 size = sizeof (MonoTypedRef);
2282 align = sizeof (gpointer);
2286 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2289 * Other backends use mono_type_stack_size (), but that
2290 * aligns the size to 8, which is larger than the size of
2291 * the source, leading to reads of invalid memory if the
2292 * source is at the end of address space.
2294 size = mono_class_value_size (in->klass, &align);
2297 g_assert (in->klass);
2299 if (ainfo->storage == ArgOnStack && size >= 10000) {
2300 /* Avoid asserts in emit_memcpy () */
2301 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2302 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2303 /* Continue normally */
2307 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2308 arg->sreg1 = in->dreg;
2309 arg->klass = in->klass;
2310 arg->backend.size = size;
2311 arg->inst_p0 = call;
2312 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2313 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2315 MONO_ADD_INS (cfg->cbb, arg);
2320 g_assert_not_reached ();
2323 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2324 /* Emit the signature cookie just before the implicit arguments */
2325 emit_sig_cookie (cfg, call, cinfo);
2328 /* Handle the case where there are no implicit arguments */
2329 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2330 emit_sig_cookie (cfg, call, cinfo);
2332 sig_ret = mini_replace_type (sig->ret);
2333 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2336 if (cinfo->ret.storage == ArgValuetypeInReg) {
2337 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2339 * Tell the JIT to use a more efficient calling convention: call using
2340 * OP_CALL, compute the result location after the call, and save the
2343 call->vret_in_reg = TRUE;
2345 * Nullify the instruction computing the vret addr to enable
2346 * future optimizations.
2349 NULLIFY_INS (call->vret_var);
2351 if (call->tail_call)
2354 * The valuetype is in RAX:RDX after the call, need to be copied to
2355 * the stack. Push the address here, so the call instruction can
2358 if (!cfg->arch.vret_addr_loc) {
2359 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2360 /* Prevent it from being register allocated or optimized away */
2361 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2364 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2368 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2369 vtarg->sreg1 = call->vret_var->dreg;
2370 vtarg->dreg = mono_alloc_preg (cfg);
2371 MONO_ADD_INS (cfg->cbb, vtarg);
2373 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2377 if (cfg->method->save_lmf) {
2378 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2379 MONO_ADD_INS (cfg->cbb, arg);
2382 call->stack_usage = cinfo->stack_usage;
2386 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2389 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2390 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2391 int size = ins->backend.size;
2393 if (ainfo->storage == ArgValuetypeInReg) {
2397 for (part = 0; part < 2; ++part) {
2398 if (ainfo->pair_storage [part] == ArgNone)
2401 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2402 load->inst_basereg = src->dreg;
2403 load->inst_offset = part * sizeof(mgreg_t);
2405 switch (ainfo->pair_storage [part]) {
2407 load->dreg = mono_alloc_ireg (cfg);
2409 case ArgInDoubleSSEReg:
2410 case ArgInFloatSSEReg:
2411 load->dreg = mono_alloc_freg (cfg);
2414 g_assert_not_reached ();
2416 MONO_ADD_INS (cfg->cbb, load);
2418 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2420 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2421 MonoInst *vtaddr, *load;
2422 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2424 MONO_INST_NEW (cfg, load, OP_LDADDR);
2425 cfg->has_indirection = TRUE;
2426 load->inst_p0 = vtaddr;
2427 vtaddr->flags |= MONO_INST_INDIRECT;
2428 load->type = STACK_MP;
2429 load->klass = vtaddr->klass;
2430 load->dreg = mono_alloc_ireg (cfg);
2431 MONO_ADD_INS (cfg->cbb, load);
2432 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2434 if (ainfo->pair_storage [0] == ArgInIReg) {
2435 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2436 arg->dreg = mono_alloc_ireg (cfg);
2437 arg->sreg1 = load->dreg;
2439 MONO_ADD_INS (cfg->cbb, arg);
2440 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2442 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2446 int dreg = mono_alloc_ireg (cfg);
2448 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2449 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2450 } else if (size <= 40) {
2451 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2453 // FIXME: Code growth
2454 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2457 if (cfg->compute_gc_maps) {
2459 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2465 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2467 MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2469 if (ret->type == MONO_TYPE_R4) {
2470 if (COMPILE_LLVM (cfg))
2471 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2473 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2475 } else if (ret->type == MONO_TYPE_R8) {
2476 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2480 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2483 #endif /* DISABLE_JIT */
2485 #define EMIT_COND_BRANCH(ins,cond,sign) \
2486 if (ins->inst_true_bb->native_offset) { \
2487 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2489 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2490 if ((cfg->opt & MONO_OPT_BRANCH) && \
2491 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2492 x86_branch8 (code, cond, 0, sign); \
2494 x86_branch32 (code, cond, 0, sign); \
2498 MonoMethodSignature *sig;
2503 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2511 switch (cinfo->ret.storage) {
2515 case ArgValuetypeInReg: {
2516 ArgInfo *ainfo = &cinfo->ret;
2518 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2520 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2528 for (i = 0; i < cinfo->nargs; ++i) {
2529 ArgInfo *ainfo = &cinfo->args [i];
2530 switch (ainfo->storage) {
2533 case ArgValuetypeInReg:
2534 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2536 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2548 * mono_arch_dyn_call_prepare:
2550 * Return a pointer to an arch-specific structure which contains information
2551 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2552 * supported for SIG.
2553 * This function is equivalent to ffi_prep_cif in libffi.
2556 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2558 ArchDynCallInfo *info;
2561 cinfo = get_call_info (NULL, NULL, sig);
2563 if (!dyn_call_supported (sig, cinfo)) {
2568 info = g_new0 (ArchDynCallInfo, 1);
2569 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2571 info->cinfo = cinfo;
2573 return (MonoDynCallInfo*)info;
2577 * mono_arch_dyn_call_free:
2579 * Free a MonoDynCallInfo structure.
2582 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2584 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2586 g_free (ainfo->cinfo);
2590 #if !defined(__native_client__)
2591 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2592 #define GREG_TO_PTR(greg) (gpointer)(greg)
2594 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2595 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2596 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2600 * mono_arch_get_start_dyn_call:
2602 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2603 * store the result into BUF.
2604 * ARGS should be an array of pointers pointing to the arguments.
2605 * RET should point to a memory buffer large enought to hold the result of the
2607 * This function should be as fast as possible, any work which does not depend
2608 * on the actual values of the arguments should be done in
2609 * mono_arch_dyn_call_prepare ().
2610 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2614 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2616 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2617 DynCallArgs *p = (DynCallArgs*)buf;
2618 int arg_index, greg, i, pindex;
2619 MonoMethodSignature *sig = dinfo->sig;
2621 g_assert (buf_len >= sizeof (DynCallArgs));
2630 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2631 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2636 if (dinfo->cinfo->vtype_retaddr)
2637 p->regs [greg ++] = PTR_TO_GREG(ret);
2639 for (i = pindex; i < sig->param_count; i++) {
2640 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2641 gpointer *arg = args [arg_index ++];
2644 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2649 case MONO_TYPE_STRING:
2650 case MONO_TYPE_CLASS:
2651 case MONO_TYPE_ARRAY:
2652 case MONO_TYPE_SZARRAY:
2653 case MONO_TYPE_OBJECT:
2657 #if !defined(__mono_ilp32__)
2661 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2662 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2664 #if defined(__mono_ilp32__)
2667 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2668 p->regs [greg ++] = *(guint64*)(arg);
2671 case MONO_TYPE_BOOLEAN:
2673 p->regs [greg ++] = *(guint8*)(arg);
2676 p->regs [greg ++] = *(gint8*)(arg);
2679 p->regs [greg ++] = *(gint16*)(arg);
2682 case MONO_TYPE_CHAR:
2683 p->regs [greg ++] = *(guint16*)(arg);
2686 p->regs [greg ++] = *(gint32*)(arg);
2689 p->regs [greg ++] = *(guint32*)(arg);
2691 case MONO_TYPE_GENERICINST:
2692 if (MONO_TYPE_IS_REFERENCE (t)) {
2693 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2698 case MONO_TYPE_VALUETYPE: {
2699 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2701 g_assert (ainfo->storage == ArgValuetypeInReg);
2702 if (ainfo->pair_storage [0] != ArgNone) {
2703 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2704 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2706 if (ainfo->pair_storage [1] != ArgNone) {
2707 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2708 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2713 g_assert_not_reached ();
2717 g_assert (greg <= PARAM_REGS);
2721 * mono_arch_finish_dyn_call:
2723 * Store the result of a dyn call into the return value buffer passed to
2724 * start_dyn_call ().
2725 * This function should be as fast as possible, any work which does not depend
2726 * on the actual values of the arguments should be done in
2727 * mono_arch_dyn_call_prepare ().
2730 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2732 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2733 MonoMethodSignature *sig = dinfo->sig;
2734 guint8 *ret = ((DynCallArgs*)buf)->ret;
2735 mgreg_t res = ((DynCallArgs*)buf)->res;
2736 MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2738 switch (sig_ret->type) {
2739 case MONO_TYPE_VOID:
2740 *(gpointer*)ret = NULL;
2742 case MONO_TYPE_STRING:
2743 case MONO_TYPE_CLASS:
2744 case MONO_TYPE_ARRAY:
2745 case MONO_TYPE_SZARRAY:
2746 case MONO_TYPE_OBJECT:
2750 *(gpointer*)ret = GREG_TO_PTR(res);
2756 case MONO_TYPE_BOOLEAN:
2757 *(guint8*)ret = res;
2760 *(gint16*)ret = res;
2763 case MONO_TYPE_CHAR:
2764 *(guint16*)ret = res;
2767 *(gint32*)ret = res;
2770 *(guint32*)ret = res;
2773 *(gint64*)ret = res;
2776 *(guint64*)ret = res;
2778 case MONO_TYPE_GENERICINST:
2779 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2780 *(gpointer*)ret = GREG_TO_PTR(res);
2785 case MONO_TYPE_VALUETYPE:
2786 if (dinfo->cinfo->vtype_retaddr) {
2789 ArgInfo *ainfo = &dinfo->cinfo->ret;
2791 g_assert (ainfo->storage == ArgValuetypeInReg);
2793 if (ainfo->pair_storage [0] != ArgNone) {
2794 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2795 ((mgreg_t*)ret)[0] = res;
2798 g_assert (ainfo->pair_storage [1] == ArgNone);
2802 g_assert_not_reached ();
2806 /* emit an exception if condition is fail */
2807 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2809 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2810 if (tins == NULL) { \
2811 mono_add_patch_info (cfg, code - cfg->native_code, \
2812 MONO_PATCH_INFO_EXC, exc_name); \
2813 x86_branch32 (code, cond, 0, signed); \
2815 EMIT_COND_BRANCH (tins, cond, signed); \
2819 #define EMIT_FPCOMPARE(code) do { \
2820 amd64_fcompp (code); \
2821 amd64_fnstsw (code); \
2824 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2825 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2826 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2827 amd64_ ##op (code); \
2828 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2829 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2833 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2835 gboolean no_patch = FALSE;
2838 * FIXME: Add support for thunks
2841 gboolean near_call = FALSE;
2844 * Indirect calls are expensive so try to make a near call if possible.
2845 * The caller memory is allocated by the code manager so it is
2846 * guaranteed to be at a 32 bit offset.
2849 if (patch_type != MONO_PATCH_INFO_ABS) {
2850 /* The target is in memory allocated using the code manager */
2853 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2854 if (((MonoMethod*)data)->klass->image->aot_module)
2855 /* The callee might be an AOT method */
2857 if (((MonoMethod*)data)->dynamic)
2858 /* The target is in malloc-ed memory */
2862 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2864 * The call might go directly to a native function without
2867 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2869 gconstpointer target = mono_icall_get_wrapper (mi);
2870 if ((((guint64)target) >> 32) != 0)
2876 MonoJumpInfo *jinfo = NULL;
2878 if (cfg->abs_patches)
2879 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2881 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2882 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2883 if (mi && (((guint64)mi->func) >> 32) == 0)
2888 * This is not really an optimization, but required because the
2889 * generic class init trampolines use R11 to pass the vtable.
2894 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2896 if (info->func == info->wrapper) {
2898 if ((((guint64)info->func) >> 32) == 0)
2902 /* See the comment in mono_codegen () */
2903 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2907 else if ((((guint64)data) >> 32) == 0) {
2914 if (cfg->method->dynamic)
2915 /* These methods are allocated using malloc */
2918 #ifdef MONO_ARCH_NOMAP32BIT
2921 #if defined(__native_client__)
2922 /* Always use near_call == TRUE for Native Client */
2925 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2926 if (optimize_for_xen)
2929 if (cfg->compile_aot) {
2936 * Align the call displacement to an address divisible by 4 so it does
2937 * not span cache lines. This is required for code patching to work on SMP
2940 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2941 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2942 amd64_padding (code, pad_size);
2944 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2945 amd64_call_code (code, 0);
2948 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2949 amd64_set_reg_template (code, GP_SCRATCH_REG);
2950 amd64_call_reg (code, GP_SCRATCH_REG);
2957 static inline guint8*
2958 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2961 if (win64_adjust_stack)
2962 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2964 code = emit_call_body (cfg, code, patch_type, data);
2966 if (win64_adjust_stack)
2967 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2974 store_membase_imm_to_store_membase_reg (int opcode)
2977 case OP_STORE_MEMBASE_IMM:
2978 return OP_STORE_MEMBASE_REG;
2979 case OP_STOREI4_MEMBASE_IMM:
2980 return OP_STOREI4_MEMBASE_REG;
2981 case OP_STOREI8_MEMBASE_IMM:
2982 return OP_STOREI8_MEMBASE_REG;
2990 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2993 * mono_arch_peephole_pass_1:
2995 * Perform peephole opts which should/can be performed before local regalloc
2998 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3002 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3003 MonoInst *last_ins = ins->prev;
3005 switch (ins->opcode) {
3009 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3011 * X86_LEA is like ADD, but doesn't have the
3012 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3013 * its operand to 64 bit.
3015 ins->opcode = OP_X86_LEA_MEMBASE;
3016 ins->inst_basereg = ins->sreg1;
3021 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3025 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3026 * the latter has length 2-3 instead of 6 (reverse constant
3027 * propagation). These instruction sequences are very common
3028 * in the initlocals bblock.
3030 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3031 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3032 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3033 ins2->sreg1 = ins->dreg;
3034 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3036 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3045 case OP_COMPARE_IMM:
3046 case OP_LCOMPARE_IMM:
3047 /* OP_COMPARE_IMM (reg, 0)
3049 * OP_AMD64_TEST_NULL (reg)
3052 ins->opcode = OP_AMD64_TEST_NULL;
3054 case OP_ICOMPARE_IMM:
3056 ins->opcode = OP_X86_TEST_NULL;
3058 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3060 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3061 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3063 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3064 * OP_COMPARE_IMM reg, imm
3066 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3068 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3069 ins->inst_basereg == last_ins->inst_destbasereg &&
3070 ins->inst_offset == last_ins->inst_offset) {
3071 ins->opcode = OP_ICOMPARE_IMM;
3072 ins->sreg1 = last_ins->sreg1;
3074 /* check if we can remove cmp reg,0 with test null */
3076 ins->opcode = OP_X86_TEST_NULL;
3082 mono_peephole_ins (bb, ins);
3087 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3091 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3092 switch (ins->opcode) {
3095 /* reg = 0 -> XOR (reg, reg) */
3096 /* XOR sets cflags on x86, so we cant do it always */
3097 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3098 ins->opcode = OP_LXOR;
3099 ins->sreg1 = ins->dreg;
3100 ins->sreg2 = ins->dreg;
3108 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3109 * 0 result into 64 bits.
3111 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3112 ins->opcode = OP_IXOR;
3116 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3120 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3121 * the latter has length 2-3 instead of 6 (reverse constant
3122 * propagation). These instruction sequences are very common
3123 * in the initlocals bblock.
3125 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3126 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3127 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3128 ins2->sreg1 = ins->dreg;
3129 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3131 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3141 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3142 ins->opcode = OP_X86_INC_REG;
3145 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3146 ins->opcode = OP_X86_DEC_REG;
3150 mono_peephole_ins (bb, ins);
3154 #define NEW_INS(cfg,ins,dest,op) do { \
3155 MONO_INST_NEW ((cfg), (dest), (op)); \
3156 (dest)->cil_code = (ins)->cil_code; \
3157 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3161 * mono_arch_lowering_pass:
3163 * Converts complex opcodes into simpler ones so that each IR instruction
3164 * corresponds to one machine instruction.
3167 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3169 MonoInst *ins, *n, *temp;
3172 * FIXME: Need to add more instructions, but the current machine
3173 * description can't model some parts of the composite instructions like
3176 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3177 switch (ins->opcode) {
3181 case OP_IDIV_UN_IMM:
3182 case OP_IREM_UN_IMM:
3185 mono_decompose_op_imm (cfg, bb, ins);
3187 case OP_COMPARE_IMM:
3188 case OP_LCOMPARE_IMM:
3189 if (!amd64_is_imm32 (ins->inst_imm)) {
3190 NEW_INS (cfg, ins, temp, OP_I8CONST);
3191 temp->inst_c0 = ins->inst_imm;
3192 temp->dreg = mono_alloc_ireg (cfg);
3193 ins->opcode = OP_COMPARE;
3194 ins->sreg2 = temp->dreg;
3197 #ifndef __mono_ilp32__
3198 case OP_LOAD_MEMBASE:
3200 case OP_LOADI8_MEMBASE:
3201 #ifndef __native_client_codegen__
3202 /* Don't generate memindex opcodes (to simplify */
3203 /* read sandboxing) */
3204 if (!amd64_is_imm32 (ins->inst_offset)) {
3205 NEW_INS (cfg, ins, temp, OP_I8CONST);
3206 temp->inst_c0 = ins->inst_offset;
3207 temp->dreg = mono_alloc_ireg (cfg);
3208 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3209 ins->inst_indexreg = temp->dreg;
3213 #ifndef __mono_ilp32__
3214 case OP_STORE_MEMBASE_IMM:
3216 case OP_STOREI8_MEMBASE_IMM:
3217 if (!amd64_is_imm32 (ins->inst_imm)) {
3218 NEW_INS (cfg, ins, temp, OP_I8CONST);
3219 temp->inst_c0 = ins->inst_imm;
3220 temp->dreg = mono_alloc_ireg (cfg);
3221 ins->opcode = OP_STOREI8_MEMBASE_REG;
3222 ins->sreg1 = temp->dreg;
3225 #ifdef MONO_ARCH_SIMD_INTRINSICS
3226 case OP_EXPAND_I1: {
3227 int temp_reg1 = mono_alloc_ireg (cfg);
3228 int temp_reg2 = mono_alloc_ireg (cfg);
3229 int original_reg = ins->sreg1;
3231 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3232 temp->sreg1 = original_reg;
3233 temp->dreg = temp_reg1;
3235 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3236 temp->sreg1 = temp_reg1;
3237 temp->dreg = temp_reg2;
3240 NEW_INS (cfg, ins, temp, OP_LOR);
3241 temp->sreg1 = temp->dreg = temp_reg2;
3242 temp->sreg2 = temp_reg1;
3244 ins->opcode = OP_EXPAND_I2;
3245 ins->sreg1 = temp_reg2;
3254 bb->max_vreg = cfg->next_vreg;
3258 branch_cc_table [] = {
3259 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3260 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3261 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3264 /* Maps CMP_... constants to X86_CC_... constants */
3267 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3268 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3272 cc_signed_table [] = {
3273 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3274 FALSE, FALSE, FALSE, FALSE
3277 /*#include "cprop.c"*/
3279 static unsigned char*
3280 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3282 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3285 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3287 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3291 static unsigned char*
3292 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3294 int sreg = tree->sreg1;
3295 int need_touch = FALSE;
3297 #if defined(HOST_WIN32)
3299 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3300 if (!tree->flags & MONO_INST_INIT)
3309 * If requested stack size is larger than one page,
3310 * perform stack-touch operation
3313 * Generate stack probe code.
3314 * Under Windows, it is necessary to allocate one page at a time,
3315 * "touching" stack after each successful sub-allocation. This is
3316 * because of the way stack growth is implemented - there is a
3317 * guard page before the lowest stack page that is currently commited.
3318 * Stack normally grows sequentially so OS traps access to the
3319 * guard page and commits more pages when needed.
3321 amd64_test_reg_imm (code, sreg, ~0xFFF);
3322 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3324 br[2] = code; /* loop */
3325 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3326 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3327 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3328 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3329 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3330 amd64_patch (br[3], br[2]);
3331 amd64_test_reg_reg (code, sreg, sreg);
3332 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3333 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3335 br[1] = code; x86_jump8 (code, 0);
3337 amd64_patch (br[0], code);
3338 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3339 amd64_patch (br[1], code);
3340 amd64_patch (br[4], code);
3343 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3345 if (tree->flags & MONO_INST_INIT) {
3347 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3348 amd64_push_reg (code, AMD64_RAX);
3351 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3352 amd64_push_reg (code, AMD64_RCX);
3355 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3356 amd64_push_reg (code, AMD64_RDI);
3360 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3361 if (sreg != AMD64_RCX)
3362 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3363 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3365 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3366 if (cfg->param_area)
3367 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3369 #if defined(__default_codegen__)
3370 amd64_prefix (code, X86_REP_PREFIX);
3372 #elif defined(__native_client_codegen__)
3373 /* NaCl stos pseudo-instruction */
3374 amd64_codegen_pre(code);
3375 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3376 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3377 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3378 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3379 amd64_prefix (code, X86_REP_PREFIX);
3381 amd64_codegen_post(code);
3382 #endif /* __native_client_codegen__ */
3384 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3385 amd64_pop_reg (code, AMD64_RDI);
3386 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3387 amd64_pop_reg (code, AMD64_RCX);
3388 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3389 amd64_pop_reg (code, AMD64_RAX);
3395 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3400 /* Move return value to the target register */
3401 /* FIXME: do this in the local reg allocator */
3402 switch (ins->opcode) {
3405 case OP_CALL_MEMBASE:
3408 case OP_LCALL_MEMBASE:
3409 g_assert (ins->dreg == AMD64_RAX);
3413 case OP_FCALL_MEMBASE:
3414 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3415 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3418 if (ins->dreg != AMD64_XMM0)
3419 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3424 case OP_VCALL_MEMBASE:
3427 case OP_VCALL2_MEMBASE:
3428 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3429 if (cinfo->ret.storage == ArgValuetypeInReg) {
3430 MonoInst *loc = cfg->arch.vret_addr_loc;
3432 /* Load the destination address */
3433 g_assert (loc->opcode == OP_REGOFFSET);
3434 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3436 for (quad = 0; quad < 2; quad ++) {
3437 switch (cinfo->ret.pair_storage [quad]) {
3439 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3441 case ArgInFloatSSEReg:
3442 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3444 case ArgInDoubleSSEReg:
3445 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3460 #endif /* DISABLE_JIT */
3463 static int tls_gs_offset;
3467 mono_amd64_have_tls_get (void)
3470 static gboolean have_tls_get = FALSE;
3471 static gboolean inited = FALSE;
3475 return have_tls_get;
3477 ins = (guint8*)pthread_getspecific;
3480 * We're looking for these two instructions:
3482 * mov %gs:[offset](,%rdi,8),%rax
3485 have_tls_get = ins [0] == 0x65 &&
3497 tls_gs_offset = ins[5];
3499 return have_tls_get;
3506 mono_amd64_get_tls_gs_offset (void)
3509 return tls_gs_offset;
3511 g_assert_not_reached ();
3517 * mono_amd64_emit_tls_get:
3518 * @code: buffer to store code to
3519 * @dreg: hard register where to place the result
3520 * @tls_offset: offset info
3522 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3523 * the dreg register the item in the thread local storage identified
3526 * Returns: a pointer to the end of the stored code
3529 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3532 if (tls_offset < 64) {
3533 x86_prefix (code, X86_GS_PREFIX);
3534 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3538 g_assert (tls_offset < 0x440);
3539 /* Load TEB->TlsExpansionSlots */
3540 x86_prefix (code, X86_GS_PREFIX);
3541 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3542 amd64_test_reg_reg (code, dreg, dreg);
3544 amd64_branch (code, X86_CC_EQ, code, TRUE);
3545 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3546 amd64_patch (buf [0], code);
3548 #elif defined(__APPLE__)
3549 x86_prefix (code, X86_GS_PREFIX);
3550 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3552 if (optimize_for_xen) {
3553 x86_prefix (code, X86_FS_PREFIX);
3554 amd64_mov_reg_mem (code, dreg, 0, 8);
3555 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3557 x86_prefix (code, X86_FS_PREFIX);
3558 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3565 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3567 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3569 if (dreg != offset_reg)
3570 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3571 amd64_prefix (code, X86_GS_PREFIX);
3572 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3573 #elif defined(__linux__)
3576 if (dreg == offset_reg) {
3577 /* Use a temporary reg by saving it to the redzone */
3578 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3579 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3580 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3581 offset_reg = tmpreg;
3583 x86_prefix (code, X86_FS_PREFIX);
3584 amd64_mov_reg_mem (code, dreg, 0, 8);
3585 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3587 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3589 g_assert_not_reached ();
3595 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3598 g_assert_not_reached ();
3599 #elif defined(__APPLE__)
3600 x86_prefix (code, X86_GS_PREFIX);
3601 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3603 g_assert (!optimize_for_xen);
3604 x86_prefix (code, X86_FS_PREFIX);
3605 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3611 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3613 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3615 g_assert_not_reached ();
3616 #elif defined(__APPLE__)
3617 x86_prefix (code, X86_GS_PREFIX);
3618 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3620 x86_prefix (code, X86_FS_PREFIX);
3621 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3627 * mono_arch_translate_tls_offset:
3629 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3632 mono_arch_translate_tls_offset (int offset)
3635 return tls_gs_offset + (offset * 8);
3644 * Emit code to initialize an LMF structure at LMF_OFFSET.
3647 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3650 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3653 * sp is saved right before calls but we need to save it here too so
3654 * async stack walks would work.
3656 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3658 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3659 if (cfg->arch.omit_fp && cfa_offset != -1)
3660 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3662 /* These can't contain refs */
3663 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3664 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3665 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3666 /* These are handled automatically by the stack marking code */
3667 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3672 #define REAL_PRINT_REG(text,reg) \
3673 mono_assert (reg >= 0); \
3674 amd64_push_reg (code, AMD64_RAX); \
3675 amd64_push_reg (code, AMD64_RDX); \
3676 amd64_push_reg (code, AMD64_RCX); \
3677 amd64_push_reg (code, reg); \
3678 amd64_push_imm (code, reg); \
3679 amd64_push_imm (code, text " %d %p\n"); \
3680 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3681 amd64_call_reg (code, AMD64_RAX); \
3682 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3683 amd64_pop_reg (code, AMD64_RCX); \
3684 amd64_pop_reg (code, AMD64_RDX); \
3685 amd64_pop_reg (code, AMD64_RAX);
3687 /* benchmark and set based on cpu */
3688 #define LOOP_ALIGNMENT 8
3689 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3693 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3698 guint8 *code = cfg->native_code + cfg->code_len;
3699 MonoInst *last_ins = NULL;
3700 guint last_offset = 0;
3703 /* Fix max_offset estimate for each successor bb */
3704 if (cfg->opt & MONO_OPT_BRANCH) {
3705 int current_offset = cfg->code_len;
3706 MonoBasicBlock *current_bb;
3707 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3708 current_bb->max_offset = current_offset;
3709 current_offset += current_bb->max_length;
3713 if (cfg->opt & MONO_OPT_LOOP) {
3714 int pad, align = LOOP_ALIGNMENT;
3715 /* set alignment depending on cpu */
3716 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3718 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3719 amd64_padding (code, pad);
3720 cfg->code_len += pad;
3721 bb->native_offset = cfg->code_len;
3725 #if defined(__native_client_codegen__)
3726 /* For Native Client, all indirect call/jump targets must be */
3727 /* 32-byte aligned. Exception handler blocks are jumped to */
3728 /* indirectly as well. */
3729 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3730 (bb->flags & BB_EXCEPTION_HANDLER);
3732 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3733 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3734 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3735 cfg->code_len += pad;
3736 bb->native_offset = cfg->code_len;
3738 #endif /*__native_client_codegen__*/
3740 if (cfg->verbose_level > 2)
3741 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3743 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3744 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3745 g_assert (!cfg->compile_aot);
3747 cov->data [bb->dfn].cil_code = bb->cil_code;
3748 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3749 /* this is not thread save, but good enough */
3750 amd64_inc_membase (code, AMD64_R11, 0);
3753 offset = code - cfg->native_code;
3755 mono_debug_open_block (cfg, bb, offset);
3757 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3758 x86_breakpoint (code);
3760 MONO_BB_FOR_EACH_INS (bb, ins) {
3761 offset = code - cfg->native_code;
3763 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3765 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3767 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3768 cfg->code_size *= 2;
3769 cfg->native_code = mono_realloc_native_code(cfg);
3770 code = cfg->native_code + offset;
3771 cfg->stat_code_reallocs++;
3774 if (cfg->debug_info)
3775 mono_debug_record_line_number (cfg, ins, offset);
3777 switch (ins->opcode) {
3779 amd64_mul_reg (code, ins->sreg2, TRUE);
3782 amd64_mul_reg (code, ins->sreg2, FALSE);
3784 case OP_X86_SETEQ_MEMBASE:
3785 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3787 case OP_STOREI1_MEMBASE_IMM:
3788 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3790 case OP_STOREI2_MEMBASE_IMM:
3791 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3793 case OP_STOREI4_MEMBASE_IMM:
3794 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3796 case OP_STOREI1_MEMBASE_REG:
3797 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3799 case OP_STOREI2_MEMBASE_REG:
3800 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3802 /* In AMD64 NaCl, pointers are 4 bytes, */
3803 /* so STORE_* != STOREI8_*. Likewise below. */
3804 case OP_STORE_MEMBASE_REG:
3805 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3807 case OP_STOREI8_MEMBASE_REG:
3808 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3810 case OP_STOREI4_MEMBASE_REG:
3811 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3813 case OP_STORE_MEMBASE_IMM:
3814 #ifndef __native_client_codegen__
3815 /* In NaCl, this could be a PCONST type, which could */
3816 /* mean a pointer type was copied directly into the */
3817 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3818 /* the value would be 0x00000000FFFFFFFF which is */
3819 /* not proper for an imm32 unless you cast it. */
3820 g_assert (amd64_is_imm32 (ins->inst_imm));
3822 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3824 case OP_STOREI8_MEMBASE_IMM:
3825 g_assert (amd64_is_imm32 (ins->inst_imm));
3826 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3829 #ifdef __mono_ilp32__
3830 /* In ILP32, pointers are 4 bytes, so separate these */
3831 /* cases, use literal 8 below where we really want 8 */
3832 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3833 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3837 // FIXME: Decompose this earlier
3838 if (amd64_is_imm32 (ins->inst_imm))
3839 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3841 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3842 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3846 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3847 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3850 // FIXME: Decompose this earlier
3851 if (amd64_is_imm32 (ins->inst_imm))
3852 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3854 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3855 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3859 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3860 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3863 /* For NaCl, pointers are 4 bytes, so separate these */
3864 /* cases, use literal 8 below where we really want 8 */
3865 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3866 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3868 case OP_LOAD_MEMBASE:
3869 g_assert (amd64_is_imm32 (ins->inst_offset));
3870 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3872 case OP_LOADI8_MEMBASE:
3873 /* Use literal 8 instead of sizeof pointer or */
3874 /* register, we really want 8 for this opcode */
3875 g_assert (amd64_is_imm32 (ins->inst_offset));
3876 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3878 case OP_LOADI4_MEMBASE:
3879 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3881 case OP_LOADU4_MEMBASE:
3882 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3884 case OP_LOADU1_MEMBASE:
3885 /* The cpu zero extends the result into 64 bits */
3886 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3888 case OP_LOADI1_MEMBASE:
3889 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3891 case OP_LOADU2_MEMBASE:
3892 /* The cpu zero extends the result into 64 bits */
3893 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3895 case OP_LOADI2_MEMBASE:
3896 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3898 case OP_AMD64_LOADI8_MEMINDEX:
3899 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3901 case OP_LCONV_TO_I1:
3902 case OP_ICONV_TO_I1:
3904 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3906 case OP_LCONV_TO_I2:
3907 case OP_ICONV_TO_I2:
3909 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3911 case OP_LCONV_TO_U1:
3912 case OP_ICONV_TO_U1:
3913 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3915 case OP_LCONV_TO_U2:
3916 case OP_ICONV_TO_U2:
3917 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3920 /* Clean out the upper word */
3921 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3924 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3928 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3930 case OP_COMPARE_IMM:
3931 #if defined(__mono_ilp32__)
3932 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3933 g_assert (amd64_is_imm32 (ins->inst_imm));
3934 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3937 case OP_LCOMPARE_IMM:
3938 g_assert (amd64_is_imm32 (ins->inst_imm));
3939 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3941 case OP_X86_COMPARE_REG_MEMBASE:
3942 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3944 case OP_X86_TEST_NULL:
3945 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3947 case OP_AMD64_TEST_NULL:
3948 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3951 case OP_X86_ADD_REG_MEMBASE:
3952 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3954 case OP_X86_SUB_REG_MEMBASE:
3955 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3957 case OP_X86_AND_REG_MEMBASE:
3958 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3960 case OP_X86_OR_REG_MEMBASE:
3961 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3963 case OP_X86_XOR_REG_MEMBASE:
3964 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3967 case OP_X86_ADD_MEMBASE_IMM:
3968 /* FIXME: Make a 64 version too */
3969 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3971 case OP_X86_SUB_MEMBASE_IMM:
3972 g_assert (amd64_is_imm32 (ins->inst_imm));
3973 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3975 case OP_X86_AND_MEMBASE_IMM:
3976 g_assert (amd64_is_imm32 (ins->inst_imm));
3977 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3979 case OP_X86_OR_MEMBASE_IMM:
3980 g_assert (amd64_is_imm32 (ins->inst_imm));
3981 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3983 case OP_X86_XOR_MEMBASE_IMM:
3984 g_assert (amd64_is_imm32 (ins->inst_imm));
3985 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3987 case OP_X86_ADD_MEMBASE_REG:
3988 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3990 case OP_X86_SUB_MEMBASE_REG:
3991 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3993 case OP_X86_AND_MEMBASE_REG:
3994 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3996 case OP_X86_OR_MEMBASE_REG:
3997 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3999 case OP_X86_XOR_MEMBASE_REG:
4000 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4002 case OP_X86_INC_MEMBASE:
4003 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4005 case OP_X86_INC_REG:
4006 amd64_inc_reg_size (code, ins->dreg, 4);
4008 case OP_X86_DEC_MEMBASE:
4009 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4011 case OP_X86_DEC_REG:
4012 amd64_dec_reg_size (code, ins->dreg, 4);
4014 case OP_X86_MUL_REG_MEMBASE:
4015 case OP_X86_MUL_MEMBASE_REG:
4016 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4018 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4019 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4021 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4022 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4024 case OP_AMD64_COMPARE_MEMBASE_REG:
4025 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4027 case OP_AMD64_COMPARE_MEMBASE_IMM:
4028 g_assert (amd64_is_imm32 (ins->inst_imm));
4029 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4031 case OP_X86_COMPARE_MEMBASE8_IMM:
4032 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4034 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4035 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4037 case OP_AMD64_COMPARE_REG_MEMBASE:
4038 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4041 case OP_AMD64_ADD_REG_MEMBASE:
4042 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4044 case OP_AMD64_SUB_REG_MEMBASE:
4045 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4047 case OP_AMD64_AND_REG_MEMBASE:
4048 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4050 case OP_AMD64_OR_REG_MEMBASE:
4051 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4053 case OP_AMD64_XOR_REG_MEMBASE:
4054 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4057 case OP_AMD64_ADD_MEMBASE_REG:
4058 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4060 case OP_AMD64_SUB_MEMBASE_REG:
4061 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4063 case OP_AMD64_AND_MEMBASE_REG:
4064 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4066 case OP_AMD64_OR_MEMBASE_REG:
4067 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4069 case OP_AMD64_XOR_MEMBASE_REG:
4070 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4073 case OP_AMD64_ADD_MEMBASE_IMM:
4074 g_assert (amd64_is_imm32 (ins->inst_imm));
4075 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4077 case OP_AMD64_SUB_MEMBASE_IMM:
4078 g_assert (amd64_is_imm32 (ins->inst_imm));
4079 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4081 case OP_AMD64_AND_MEMBASE_IMM:
4082 g_assert (amd64_is_imm32 (ins->inst_imm));
4083 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4085 case OP_AMD64_OR_MEMBASE_IMM:
4086 g_assert (amd64_is_imm32 (ins->inst_imm));
4087 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4089 case OP_AMD64_XOR_MEMBASE_IMM:
4090 g_assert (amd64_is_imm32 (ins->inst_imm));
4091 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4095 amd64_breakpoint (code);
4097 case OP_RELAXED_NOP:
4098 x86_prefix (code, X86_REP_PREFIX);
4106 case OP_DUMMY_STORE:
4107 case OP_DUMMY_ICONST:
4108 case OP_DUMMY_R8CONST:
4109 case OP_NOT_REACHED:
4112 case OP_IL_SEQ_POINT:
4113 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4115 case OP_SEQ_POINT: {
4119 * Read from the single stepping trigger page. This will cause a
4120 * SIGSEGV when single stepping is enabled.
4121 * We do this _before_ the breakpoint, so single stepping after
4122 * a breakpoint is hit will step to the next IL offset.
4124 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4125 MonoInst *var = cfg->arch.ss_trigger_page_var;
4127 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4128 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4132 * This is the address which is saved in seq points,
4134 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4136 if (cfg->compile_aot) {
4137 guint32 offset = code - cfg->native_code;
4139 MonoInst *info_var = cfg->arch.seq_point_info_var;
4142 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4143 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4144 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4145 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4146 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4149 * A placeholder for a possible breakpoint inserted by
4150 * mono_arch_set_breakpoint ().
4152 for (i = 0; i < breakpoint_size; ++i)
4156 * Add an additional nop so skipping the bp doesn't cause the ip to point
4157 * to another IL offset.
4165 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4168 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4172 g_assert (amd64_is_imm32 (ins->inst_imm));
4173 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4176 g_assert (amd64_is_imm32 (ins->inst_imm));
4177 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4182 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4185 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4189 g_assert (amd64_is_imm32 (ins->inst_imm));
4190 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4193 g_assert (amd64_is_imm32 (ins->inst_imm));
4194 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4197 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4201 g_assert (amd64_is_imm32 (ins->inst_imm));
4202 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4205 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4210 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4212 switch (ins->inst_imm) {
4216 if (ins->dreg != ins->sreg1)
4217 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4218 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4221 /* LEA r1, [r2 + r2*2] */
4222 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4225 /* LEA r1, [r2 + r2*4] */
4226 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4229 /* LEA r1, [r2 + r2*2] */
4231 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4232 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4235 /* LEA r1, [r2 + r2*8] */
4236 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4239 /* LEA r1, [r2 + r2*4] */
4241 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4242 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4245 /* LEA r1, [r2 + r2*2] */
4247 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4248 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4251 /* LEA r1, [r2 + r2*4] */
4252 /* LEA r1, [r1 + r1*4] */
4253 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4254 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4257 /* LEA r1, [r2 + r2*4] */
4259 /* LEA r1, [r1 + r1*4] */
4260 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4261 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4262 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4265 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4272 #if defined( __native_client_codegen__ )
4273 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4274 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4276 /* Regalloc magic makes the div/rem cases the same */
4277 if (ins->sreg2 == AMD64_RDX) {
4278 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4280 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4283 amd64_div_reg (code, ins->sreg2, TRUE);
4288 #if defined( __native_client_codegen__ )
4289 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4290 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4292 if (ins->sreg2 == AMD64_RDX) {
4293 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4294 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4295 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4297 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4298 amd64_div_reg (code, ins->sreg2, FALSE);
4303 #if defined( __native_client_codegen__ )
4304 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4305 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4307 if (ins->sreg2 == AMD64_RDX) {
4308 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4309 amd64_cdq_size (code, 4);
4310 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4312 amd64_cdq_size (code, 4);
4313 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4318 #if defined( __native_client_codegen__ )
4319 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4320 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4322 if (ins->sreg2 == AMD64_RDX) {
4323 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4324 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4325 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4327 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4328 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4332 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4333 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4336 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4340 g_assert (amd64_is_imm32 (ins->inst_imm));
4341 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4344 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4348 g_assert (amd64_is_imm32 (ins->inst_imm));
4349 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4352 g_assert (ins->sreg2 == AMD64_RCX);
4353 amd64_shift_reg (code, X86_SHL, ins->dreg);
4356 g_assert (ins->sreg2 == AMD64_RCX);
4357 amd64_shift_reg (code, X86_SAR, ins->dreg);
4360 g_assert (amd64_is_imm32 (ins->inst_imm));
4361 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4364 g_assert (amd64_is_imm32 (ins->inst_imm));
4365 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4368 g_assert (amd64_is_imm32 (ins->inst_imm));
4369 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4371 case OP_LSHR_UN_IMM:
4372 g_assert (amd64_is_imm32 (ins->inst_imm));
4373 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4376 g_assert (ins->sreg2 == AMD64_RCX);
4377 amd64_shift_reg (code, X86_SHR, ins->dreg);
4380 g_assert (amd64_is_imm32 (ins->inst_imm));
4381 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4384 g_assert (amd64_is_imm32 (ins->inst_imm));
4385 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4390 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4393 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4396 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4399 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4403 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4406 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4409 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4412 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4415 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4418 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4421 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4424 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4427 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4430 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4433 amd64_neg_reg_size (code, ins->sreg1, 4);
4436 amd64_not_reg_size (code, ins->sreg1, 4);
4439 g_assert (ins->sreg2 == AMD64_RCX);
4440 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4443 g_assert (ins->sreg2 == AMD64_RCX);
4444 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4447 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4449 case OP_ISHR_UN_IMM:
4450 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4453 g_assert (ins->sreg2 == AMD64_RCX);
4454 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4457 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4460 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4463 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4464 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4466 case OP_IMUL_OVF_UN:
4467 case OP_LMUL_OVF_UN: {
4468 /* the mul operation and the exception check should most likely be split */
4469 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4470 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4471 /*g_assert (ins->sreg2 == X86_EAX);
4472 g_assert (ins->dreg == X86_EAX);*/
4473 if (ins->sreg2 == X86_EAX) {
4474 non_eax_reg = ins->sreg1;
4475 } else if (ins->sreg1 == X86_EAX) {
4476 non_eax_reg = ins->sreg2;
4478 /* no need to save since we're going to store to it anyway */
4479 if (ins->dreg != X86_EAX) {
4481 amd64_push_reg (code, X86_EAX);
4483 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4484 non_eax_reg = ins->sreg2;
4486 if (ins->dreg == X86_EDX) {
4489 amd64_push_reg (code, X86_EAX);
4493 amd64_push_reg (code, X86_EDX);
4495 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4496 /* save before the check since pop and mov don't change the flags */
4497 if (ins->dreg != X86_EAX)
4498 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4500 amd64_pop_reg (code, X86_EDX);
4502 amd64_pop_reg (code, X86_EAX);
4503 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4507 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4509 case OP_ICOMPARE_IMM:
4510 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4532 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4540 case OP_CMOV_INE_UN:
4541 case OP_CMOV_IGE_UN:
4542 case OP_CMOV_IGT_UN:
4543 case OP_CMOV_ILE_UN:
4544 case OP_CMOV_ILT_UN:
4550 case OP_CMOV_LNE_UN:
4551 case OP_CMOV_LGE_UN:
4552 case OP_CMOV_LGT_UN:
4553 case OP_CMOV_LLE_UN:
4554 case OP_CMOV_LLT_UN:
4555 g_assert (ins->dreg == ins->sreg1);
4556 /* This needs to operate on 64 bit values */
4557 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4561 amd64_not_reg (code, ins->sreg1);
4564 amd64_neg_reg (code, ins->sreg1);
4569 if ((((guint64)ins->inst_c0) >> 32) == 0)
4570 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4572 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4575 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4576 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4579 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4580 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4583 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4585 case OP_AMD64_SET_XMMREG_R4: {
4586 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4589 case OP_AMD64_SET_XMMREG_R8: {
4590 if (ins->dreg != ins->sreg1)
4591 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4595 MonoCallInst *call = (MonoCallInst*)ins;
4596 int i, save_area_offset;
4598 g_assert (!cfg->method->save_lmf);
4600 /* Restore callee saved registers */
4601 save_area_offset = cfg->arch.reg_save_area_offset;
4602 for (i = 0; i < AMD64_NREG; ++i)
4603 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4604 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4605 save_area_offset += 8;
4608 if (cfg->arch.omit_fp) {
4609 if (cfg->arch.stack_alloc_size)
4610 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4612 if (call->stack_usage)
4615 /* Copy arguments on the stack to our argument area */
4616 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4617 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4618 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4624 offset = code - cfg->native_code;
4625 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4626 if (cfg->compile_aot)
4627 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4629 amd64_set_reg_template (code, AMD64_R11);
4630 amd64_jump_reg (code, AMD64_R11);
4631 ins->flags |= MONO_INST_GC_CALLSITE;
4632 ins->backend.pc_offset = code - cfg->native_code;
4636 /* ensure ins->sreg1 is not NULL */
4637 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4640 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4641 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4650 call = (MonoCallInst*)ins;
4652 * The AMD64 ABI forces callers to know about varargs.
4654 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4655 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4656 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4658 * Since the unmanaged calling convention doesn't contain a
4659 * 'vararg' entry, we have to treat every pinvoke call as a
4660 * potential vararg call.
4664 for (i = 0; i < AMD64_XMM_NREG; ++i)
4665 if (call->used_fregs & (1 << i))
4668 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4670 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4673 if (ins->flags & MONO_INST_HAS_METHOD)
4674 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4676 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4677 ins->flags |= MONO_INST_GC_CALLSITE;
4678 ins->backend.pc_offset = code - cfg->native_code;
4679 code = emit_move_return_value (cfg, ins, code);
4685 case OP_VOIDCALL_REG:
4687 call = (MonoCallInst*)ins;
4689 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4690 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4691 ins->sreg1 = AMD64_R11;
4695 * The AMD64 ABI forces callers to know about varargs.
4697 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4698 if (ins->sreg1 == AMD64_RAX) {
4699 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4700 ins->sreg1 = AMD64_R11;
4702 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4703 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4705 * Since the unmanaged calling convention doesn't contain a
4706 * 'vararg' entry, we have to treat every pinvoke call as a
4707 * potential vararg call.
4711 for (i = 0; i < AMD64_XMM_NREG; ++i)
4712 if (call->used_fregs & (1 << i))
4714 if (ins->sreg1 == AMD64_RAX) {
4715 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4716 ins->sreg1 = AMD64_R11;
4719 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4721 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4724 amd64_call_reg (code, ins->sreg1);
4725 ins->flags |= MONO_INST_GC_CALLSITE;
4726 ins->backend.pc_offset = code - cfg->native_code;
4727 code = emit_move_return_value (cfg, ins, code);
4729 case OP_FCALL_MEMBASE:
4730 case OP_LCALL_MEMBASE:
4731 case OP_VCALL_MEMBASE:
4732 case OP_VCALL2_MEMBASE:
4733 case OP_VOIDCALL_MEMBASE:
4734 case OP_CALL_MEMBASE:
4735 call = (MonoCallInst*)ins;
4737 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4738 ins->flags |= MONO_INST_GC_CALLSITE;
4739 ins->backend.pc_offset = code - cfg->native_code;
4740 code = emit_move_return_value (cfg, ins, code);
4744 MonoInst *var = cfg->dyn_call_var;
4746 g_assert (var->opcode == OP_REGOFFSET);
4748 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4749 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4751 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4753 /* Save args buffer */
4754 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4756 /* Set argument registers */
4757 for (i = 0; i < PARAM_REGS; ++i)
4758 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4761 amd64_call_reg (code, AMD64_R10);
4763 ins->flags |= MONO_INST_GC_CALLSITE;
4764 ins->backend.pc_offset = code - cfg->native_code;
4767 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4768 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4771 case OP_AMD64_SAVE_SP_TO_LMF: {
4772 MonoInst *lmf_var = cfg->lmf_var;
4773 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4777 g_assert_not_reached ();
4778 amd64_push_reg (code, ins->sreg1);
4780 case OP_X86_PUSH_IMM:
4781 g_assert_not_reached ();
4782 g_assert (amd64_is_imm32 (ins->inst_imm));
4783 amd64_push_imm (code, ins->inst_imm);
4785 case OP_X86_PUSH_MEMBASE:
4786 g_assert_not_reached ();
4787 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4789 case OP_X86_PUSH_OBJ: {
4790 int size = ALIGN_TO (ins->inst_imm, 8);
4792 g_assert_not_reached ();
4794 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4795 amd64_push_reg (code, AMD64_RDI);
4796 amd64_push_reg (code, AMD64_RSI);
4797 amd64_push_reg (code, AMD64_RCX);
4798 if (ins->inst_offset)
4799 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4801 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4802 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4803 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4805 amd64_prefix (code, X86_REP_PREFIX);
4807 amd64_pop_reg (code, AMD64_RCX);
4808 amd64_pop_reg (code, AMD64_RSI);
4809 amd64_pop_reg (code, AMD64_RDI);
4813 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4815 case OP_X86_LEA_MEMBASE:
4816 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4819 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4822 /* keep alignment */
4823 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4824 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4825 code = mono_emit_stack_alloc (cfg, code, ins);
4826 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4827 if (cfg->param_area)
4828 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4830 case OP_LOCALLOC_IMM: {
4831 guint32 size = ins->inst_imm;
4832 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4834 if (ins->flags & MONO_INST_INIT) {
4838 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4839 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4841 for (i = 0; i < size; i += 8)
4842 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4843 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4845 amd64_mov_reg_imm (code, ins->dreg, size);
4846 ins->sreg1 = ins->dreg;
4848 code = mono_emit_stack_alloc (cfg, code, ins);
4849 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4852 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4853 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4855 if (cfg->param_area)
4856 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4860 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4861 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4862 (gpointer)"mono_arch_throw_exception", FALSE);
4863 ins->flags |= MONO_INST_GC_CALLSITE;
4864 ins->backend.pc_offset = code - cfg->native_code;
4868 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4869 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4870 (gpointer)"mono_arch_rethrow_exception", FALSE);
4871 ins->flags |= MONO_INST_GC_CALLSITE;
4872 ins->backend.pc_offset = code - cfg->native_code;
4875 case OP_CALL_HANDLER:
4877 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4878 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4879 amd64_call_imm (code, 0);
4880 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4881 /* Restore stack alignment */
4882 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4884 case OP_START_HANDLER: {
4885 /* Even though we're saving RSP, use sizeof */
4886 /* gpointer because spvar is of type IntPtr */
4887 /* see: mono_create_spvar_for_region */
4888 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4889 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4891 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4892 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4894 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4898 case OP_ENDFINALLY: {
4899 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4900 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4904 case OP_ENDFILTER: {
4905 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4906 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4907 /* The local allocator will put the result into RAX */
4913 ins->inst_c0 = code - cfg->native_code;
4916 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4917 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4919 if (ins->inst_target_bb->native_offset) {
4920 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4922 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4923 if ((cfg->opt & MONO_OPT_BRANCH) &&
4924 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4925 x86_jump8 (code, 0);
4927 x86_jump32 (code, 0);
4931 amd64_jump_reg (code, ins->sreg1);
4954 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4955 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4957 case OP_COND_EXC_EQ:
4958 case OP_COND_EXC_NE_UN:
4959 case OP_COND_EXC_LT:
4960 case OP_COND_EXC_LT_UN:
4961 case OP_COND_EXC_GT:
4962 case OP_COND_EXC_GT_UN:
4963 case OP_COND_EXC_GE:
4964 case OP_COND_EXC_GE_UN:
4965 case OP_COND_EXC_LE:
4966 case OP_COND_EXC_LE_UN:
4967 case OP_COND_EXC_IEQ:
4968 case OP_COND_EXC_INE_UN:
4969 case OP_COND_EXC_ILT:
4970 case OP_COND_EXC_ILT_UN:
4971 case OP_COND_EXC_IGT:
4972 case OP_COND_EXC_IGT_UN:
4973 case OP_COND_EXC_IGE:
4974 case OP_COND_EXC_IGE_UN:
4975 case OP_COND_EXC_ILE:
4976 case OP_COND_EXC_ILE_UN:
4977 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4979 case OP_COND_EXC_OV:
4980 case OP_COND_EXC_NO:
4982 case OP_COND_EXC_NC:
4983 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4984 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4986 case OP_COND_EXC_IOV:
4987 case OP_COND_EXC_INO:
4988 case OP_COND_EXC_IC:
4989 case OP_COND_EXC_INC:
4990 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4991 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4994 /* floating point opcodes */
4996 double d = *(double *)ins->inst_p0;
4998 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4999 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5002 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5003 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5008 float f = *(float *)ins->inst_p0;
5010 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5011 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5014 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5015 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5016 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5020 case OP_STORER8_MEMBASE_REG:
5021 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5023 case OP_LOADR8_MEMBASE:
5024 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5026 case OP_STORER4_MEMBASE_REG:
5027 /* This requires a double->single conversion */
5028 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5029 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5031 case OP_LOADR4_MEMBASE:
5032 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5033 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5035 case OP_ICONV_TO_R4:
5036 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5037 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5039 case OP_ICONV_TO_R8:
5040 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5042 case OP_LCONV_TO_R4:
5043 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5044 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5046 case OP_LCONV_TO_R8:
5047 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5049 case OP_FCONV_TO_R4:
5050 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5051 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5053 case OP_FCONV_TO_I1:
5054 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5056 case OP_FCONV_TO_U1:
5057 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5059 case OP_FCONV_TO_I2:
5060 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5062 case OP_FCONV_TO_U2:
5063 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5065 case OP_FCONV_TO_U4:
5066 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5068 case OP_FCONV_TO_I4:
5070 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5072 case OP_FCONV_TO_I8:
5073 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5075 case OP_LCONV_TO_R_UN: {
5078 /* Based on gcc code */
5079 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5080 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5083 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5084 br [1] = code; x86_jump8 (code, 0);
5085 amd64_patch (br [0], code);
5088 /* Save to the red zone */
5089 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5090 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5091 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5092 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5093 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5094 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5095 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5096 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5097 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5099 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5100 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5101 amd64_patch (br [1], code);
5104 case OP_LCONV_TO_OVF_U4:
5105 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5106 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5107 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5109 case OP_LCONV_TO_OVF_I4_UN:
5110 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5111 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5112 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5115 if (ins->dreg != ins->sreg1)
5116 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5119 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5122 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5125 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5128 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5131 static double r8_0 = -0.0;
5133 g_assert (ins->sreg1 == ins->dreg);
5135 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5136 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5140 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5143 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5146 static guint64 d = 0x7fffffffffffffffUL;
5148 g_assert (ins->sreg1 == ins->dreg);
5150 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5151 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5155 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5158 g_assert (cfg->opt & MONO_OPT_CMOV);
5159 g_assert (ins->dreg == ins->sreg1);
5160 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5161 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5164 g_assert (cfg->opt & MONO_OPT_CMOV);
5165 g_assert (ins->dreg == ins->sreg1);
5166 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5167 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5170 g_assert (cfg->opt & MONO_OPT_CMOV);
5171 g_assert (ins->dreg == ins->sreg1);
5172 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5173 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5176 g_assert (cfg->opt & MONO_OPT_CMOV);
5177 g_assert (ins->dreg == ins->sreg1);
5178 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5179 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5182 g_assert (cfg->opt & MONO_OPT_CMOV);
5183 g_assert (ins->dreg == ins->sreg1);
5184 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5185 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5188 g_assert (cfg->opt & MONO_OPT_CMOV);
5189 g_assert (ins->dreg == ins->sreg1);
5190 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5191 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5194 g_assert (cfg->opt & MONO_OPT_CMOV);
5195 g_assert (ins->dreg == ins->sreg1);
5196 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5197 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5200 g_assert (cfg->opt & MONO_OPT_CMOV);
5201 g_assert (ins->dreg == ins->sreg1);
5202 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5203 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5209 * The two arguments are swapped because the fbranch instructions
5210 * depend on this for the non-sse case to work.
5212 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5216 /* zeroing the register at the start results in
5217 * shorter and faster code (we can also remove the widening op)
5219 guchar *unordered_check;
5220 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5221 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5222 unordered_check = code;
5223 x86_branch8 (code, X86_CC_P, 0, FALSE);
5225 if (ins->opcode == OP_FCEQ) {
5226 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5227 amd64_patch (unordered_check, code);
5229 guchar *jump_to_end;
5230 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5232 x86_jump8 (code, 0);
5233 amd64_patch (unordered_check, code);
5234 amd64_inc_reg (code, ins->dreg);
5235 amd64_patch (jump_to_end, code);
5241 /* zeroing the register at the start results in
5242 * shorter and faster code (we can also remove the widening op)
5244 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5245 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5246 if (ins->opcode == OP_FCLT_UN) {
5247 guchar *unordered_check = code;
5248 guchar *jump_to_end;
5249 x86_branch8 (code, X86_CC_P, 0, FALSE);
5250 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5252 x86_jump8 (code, 0);
5253 amd64_patch (unordered_check, code);
5254 amd64_inc_reg (code, ins->dreg);
5255 amd64_patch (jump_to_end, code);
5257 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5261 guchar *unordered_check;
5262 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5263 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5264 unordered_check = code;
5265 x86_branch8 (code, X86_CC_P, 0, FALSE);
5266 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5267 amd64_patch (unordered_check, code);
5272 /* zeroing the register at the start results in
5273 * shorter and faster code (we can also remove the widening op)
5275 guchar *unordered_check;
5276 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5277 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5278 if (ins->opcode == OP_FCGT) {
5279 unordered_check = code;
5280 x86_branch8 (code, X86_CC_P, 0, FALSE);
5281 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5282 amd64_patch (unordered_check, code);
5284 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5289 guchar *unordered_check;
5290 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5291 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5292 unordered_check = code;
5293 x86_branch8 (code, X86_CC_P, 0, FALSE);
5294 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5295 amd64_patch (unordered_check, code);
5299 case OP_FCLT_MEMBASE:
5300 case OP_FCGT_MEMBASE:
5301 case OP_FCLT_UN_MEMBASE:
5302 case OP_FCGT_UN_MEMBASE:
5303 case OP_FCEQ_MEMBASE: {
5304 guchar *unordered_check, *jump_to_end;
5307 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5308 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5310 switch (ins->opcode) {
5311 case OP_FCEQ_MEMBASE:
5312 x86_cond = X86_CC_EQ;
5314 case OP_FCLT_MEMBASE:
5315 case OP_FCLT_UN_MEMBASE:
5316 x86_cond = X86_CC_LT;
5318 case OP_FCGT_MEMBASE:
5319 case OP_FCGT_UN_MEMBASE:
5320 x86_cond = X86_CC_GT;
5323 g_assert_not_reached ();
5326 unordered_check = code;
5327 x86_branch8 (code, X86_CC_P, 0, FALSE);
5328 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5330 switch (ins->opcode) {
5331 case OP_FCEQ_MEMBASE:
5332 case OP_FCLT_MEMBASE:
5333 case OP_FCGT_MEMBASE:
5334 amd64_patch (unordered_check, code);
5336 case OP_FCLT_UN_MEMBASE:
5337 case OP_FCGT_UN_MEMBASE:
5339 x86_jump8 (code, 0);
5340 amd64_patch (unordered_check, code);
5341 amd64_inc_reg (code, ins->dreg);
5342 amd64_patch (jump_to_end, code);
5350 guchar *jump = code;
5351 x86_branch8 (code, X86_CC_P, 0, TRUE);
5352 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5353 amd64_patch (jump, code);
5357 /* Branch if C013 != 100 */
5358 /* branch if !ZF or (PF|CF) */
5359 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5360 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5361 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5364 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5367 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5368 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5372 if (ins->opcode == OP_FBGT) {
5375 /* skip branch if C1=1 */
5377 x86_branch8 (code, X86_CC_P, 0, FALSE);
5378 /* branch if (C0 | C3) = 1 */
5379 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5380 amd64_patch (br1, code);
5383 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5387 /* Branch if C013 == 100 or 001 */
5390 /* skip branch if C1=1 */
5392 x86_branch8 (code, X86_CC_P, 0, FALSE);
5393 /* branch if (C0 | C3) = 1 */
5394 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5395 amd64_patch (br1, code);
5399 /* Branch if C013 == 000 */
5400 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5403 /* Branch if C013=000 or 100 */
5406 /* skip branch if C1=1 */
5408 x86_branch8 (code, X86_CC_P, 0, FALSE);
5409 /* branch if C0=0 */
5410 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5411 amd64_patch (br1, code);
5415 /* Branch if C013 != 001 */
5416 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5417 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5420 /* Transfer value to the fp stack */
5421 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5422 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5423 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5425 amd64_push_reg (code, AMD64_RAX);
5427 amd64_fnstsw (code);
5428 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5429 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5430 amd64_pop_reg (code, AMD64_RAX);
5431 amd64_fstp (code, 0);
5432 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5433 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5436 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5439 case OP_TLS_GET_REG:
5440 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5443 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5446 case OP_TLS_SET_REG: {
5447 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5450 case OP_MEMORY_BARRIER: {
5451 switch (ins->backend.memory_barrier_kind) {
5452 case StoreLoadBarrier:
5454 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5455 x86_prefix (code, X86_LOCK_PREFIX);
5456 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5461 case OP_ATOMIC_ADD_I4:
5462 case OP_ATOMIC_ADD_I8: {
5463 int dreg = ins->dreg;
5464 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5466 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5469 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5470 amd64_prefix (code, X86_LOCK_PREFIX);
5471 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5472 /* dreg contains the old value, add with sreg2 value */
5473 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5475 if (ins->dreg != dreg)
5476 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5480 case OP_ATOMIC_EXCHANGE_I4:
5481 case OP_ATOMIC_EXCHANGE_I8: {
5483 int sreg2 = ins->sreg2;
5484 int breg = ins->inst_basereg;
5486 gboolean need_push = FALSE, rdx_pushed = FALSE;
5488 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5494 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5495 * an explanation of how this works.
5498 /* cmpxchg uses eax as comperand, need to make sure we can use it
5499 * hack to overcome limits in x86 reg allocator
5500 * (req: dreg == eax and sreg2 != eax and breg != eax)
5502 g_assert (ins->dreg == AMD64_RAX);
5504 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5505 /* Highly unlikely, but possible */
5508 /* The pushes invalidate rsp */
5509 if ((breg == AMD64_RAX) || need_push) {
5510 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5514 /* We need the EAX reg for the comparand */
5515 if (ins->sreg2 == AMD64_RAX) {
5516 if (breg != AMD64_R11) {
5517 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5520 g_assert (need_push);
5521 amd64_push_reg (code, AMD64_RDX);
5522 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5528 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5530 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5531 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5532 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5533 amd64_patch (br [1], br [0]);
5536 amd64_pop_reg (code, AMD64_RDX);
5540 case OP_ATOMIC_CAS_I4:
5541 case OP_ATOMIC_CAS_I8: {
5544 if (ins->opcode == OP_ATOMIC_CAS_I8)
5550 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5551 * an explanation of how this works.
5553 g_assert (ins->sreg3 == AMD64_RAX);
5554 g_assert (ins->sreg1 != AMD64_RAX);
5555 g_assert (ins->sreg1 != ins->sreg2);
5557 amd64_prefix (code, X86_LOCK_PREFIX);
5558 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5560 if (ins->dreg != AMD64_RAX)
5561 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5564 case OP_CARD_TABLE_WBARRIER: {
5565 int ptr = ins->sreg1;
5566 int value = ins->sreg2;
5568 int nursery_shift, card_table_shift;
5569 gpointer card_table_mask;
5570 size_t nursery_size;
5572 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5573 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5574 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5576 /*If either point to the stack we can simply avoid the WB. This happens due to
5577 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5579 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5583 * We need one register we can clobber, we choose EDX and make sreg1
5584 * fixed EAX to work around limitations in the local register allocator.
5585 * sreg2 might get allocated to EDX, but that is not a problem since
5586 * we use it before clobbering EDX.
5588 g_assert (ins->sreg1 == AMD64_RAX);
5591 * This is the code we produce:
5594 * edx >>= nursery_shift
5595 * cmp edx, (nursery_start >> nursery_shift)
5598 * edx >>= card_table_shift
5604 if (mono_gc_card_table_nursery_check ()) {
5605 if (value != AMD64_RDX)
5606 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5607 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5608 if (shifted_nursery_start >> 31) {
5610 * The value we need to compare against is 64 bits, so we need
5611 * another spare register. We use RBX, which we save and
5614 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5615 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5616 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5617 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5619 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5621 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5623 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5624 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5625 if (card_table_mask)
5626 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5628 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5629 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5631 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5633 if (mono_gc_card_table_nursery_check ())
5634 x86_patch (br, code);
5637 #ifdef MONO_ARCH_SIMD_INTRINSICS
5638 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5640 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5643 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5646 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5649 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5652 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5655 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5658 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5659 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5662 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5665 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5668 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5671 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5674 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5677 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5680 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5683 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5686 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5689 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5692 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5695 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5698 case OP_PSHUFLEW_HIGH:
5699 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5700 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5702 case OP_PSHUFLEW_LOW:
5703 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5704 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5707 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5708 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5711 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5712 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5715 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5716 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5720 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5723 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5726 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5729 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5732 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5735 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5738 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5739 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5742 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5745 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5748 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5751 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5754 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5757 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5760 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5763 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5766 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5769 case OP_EXTRACT_MASK:
5770 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5774 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5777 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5780 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5784 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5787 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5790 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5793 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5797 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5800 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5803 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5806 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5810 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5813 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5816 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5820 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5823 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5826 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5830 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5833 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5837 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5840 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5843 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5847 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5850 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5853 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5857 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5860 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5863 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5866 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5870 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5873 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5876 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5879 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5882 case OP_PSUM_ABS_DIFF:
5883 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5886 case OP_UNPACK_LOWB:
5887 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5889 case OP_UNPACK_LOWW:
5890 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5892 case OP_UNPACK_LOWD:
5893 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5895 case OP_UNPACK_LOWQ:
5896 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5898 case OP_UNPACK_LOWPS:
5899 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5901 case OP_UNPACK_LOWPD:
5902 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5905 case OP_UNPACK_HIGHB:
5906 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5908 case OP_UNPACK_HIGHW:
5909 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5911 case OP_UNPACK_HIGHD:
5912 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5914 case OP_UNPACK_HIGHQ:
5915 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5917 case OP_UNPACK_HIGHPS:
5918 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5920 case OP_UNPACK_HIGHPD:
5921 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5925 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5928 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5931 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5934 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5937 case OP_PADDB_SAT_UN:
5938 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5940 case OP_PSUBB_SAT_UN:
5941 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5943 case OP_PADDW_SAT_UN:
5944 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5946 case OP_PSUBW_SAT_UN:
5947 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5951 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5954 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5957 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5960 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5964 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5967 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5970 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5972 case OP_PMULW_HIGH_UN:
5973 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5976 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5980 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5983 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5987 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5990 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5994 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5997 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6001 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6004 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6008 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6011 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6015 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6018 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6022 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6025 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6028 /*TODO: This is appart of the sse spec but not added
6030 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6033 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6038 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6041 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6044 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6047 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6050 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6053 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6056 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6059 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6062 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6065 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6069 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6072 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6076 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6077 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6079 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6084 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6086 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6087 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6091 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6093 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6094 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6095 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6099 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6101 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6104 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6106 case OP_EXTRACTX_U2:
6107 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6109 case OP_INSERTX_U1_SLOW:
6110 /*sreg1 is the extracted ireg (scratch)
6111 /sreg2 is the to be inserted ireg (scratch)
6112 /dreg is the xreg to receive the value*/
6114 /*clear the bits from the extracted word*/
6115 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6116 /*shift the value to insert if needed*/
6117 if (ins->inst_c0 & 1)
6118 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6119 /*join them together*/
6120 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6121 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6123 case OP_INSERTX_I4_SLOW:
6124 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6125 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6126 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6128 case OP_INSERTX_I8_SLOW:
6129 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6131 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6133 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6136 case OP_INSERTX_R4_SLOW:
6137 switch (ins->inst_c0) {
6139 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6142 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6143 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6144 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6147 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6148 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6149 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6152 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6153 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6154 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6158 case OP_INSERTX_R8_SLOW:
6160 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6162 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6164 case OP_STOREX_MEMBASE_REG:
6165 case OP_STOREX_MEMBASE:
6166 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6168 case OP_LOADX_MEMBASE:
6169 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6171 case OP_LOADX_ALIGNED_MEMBASE:
6172 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6174 case OP_STOREX_ALIGNED_MEMBASE_REG:
6175 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6177 case OP_STOREX_NTA_MEMBASE_REG:
6178 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6180 case OP_PREFETCH_MEMBASE:
6181 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6185 /*FIXME the peephole pass should have killed this*/
6186 if (ins->dreg != ins->sreg1)
6187 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6190 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6192 case OP_ICONV_TO_R8_RAW:
6193 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6194 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6197 case OP_FCONV_TO_R8_X:
6198 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6201 case OP_XCONV_R8_TO_I4:
6202 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6203 switch (ins->backend.source_opcode) {
6204 case OP_FCONV_TO_I1:
6205 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6207 case OP_FCONV_TO_U1:
6208 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6210 case OP_FCONV_TO_I2:
6211 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6213 case OP_FCONV_TO_U2:
6214 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6220 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6221 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6222 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6225 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6226 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6229 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6230 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6233 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6234 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6235 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6238 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6239 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6242 case OP_LIVERANGE_START: {
6243 if (cfg->verbose_level > 1)
6244 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6245 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6248 case OP_LIVERANGE_END: {
6249 if (cfg->verbose_level > 1)
6250 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6251 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6254 case OP_NACL_GC_SAFE_POINT: {
6255 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6256 if (cfg->compile_aot)
6257 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6261 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6262 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6263 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6264 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6265 amd64_patch (br[0], code);
6270 case OP_GC_LIVENESS_DEF:
6271 case OP_GC_LIVENESS_USE:
6272 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6273 ins->backend.pc_offset = code - cfg->native_code;
6275 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6276 ins->backend.pc_offset = code - cfg->native_code;
6277 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6280 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6281 g_assert_not_reached ();
6284 if ((code - cfg->native_code - offset) > max_len) {
6285 #if !defined(__native_client_codegen__)
6286 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6287 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6288 g_assert_not_reached ();
6293 last_offset = offset;
6296 cfg->code_len = code - cfg->native_code;
6299 #endif /* DISABLE_JIT */
6302 mono_arch_register_lowlevel_calls (void)
6304 /* The signature doesn't matter */
6305 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6309 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6311 MonoJumpInfo *patch_info;
6312 gboolean compile_aot = !run_cctors;
6314 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6315 unsigned char *ip = patch_info->ip.i + code;
6316 unsigned char *target;
6319 switch (patch_info->type) {
6320 case MONO_PATCH_INFO_BB:
6321 case MONO_PATCH_INFO_LABEL:
6324 /* No need to patch these */
6329 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6331 switch (patch_info->type) {
6332 case MONO_PATCH_INFO_NONE:
6334 case MONO_PATCH_INFO_METHOD_REL:
6335 case MONO_PATCH_INFO_R8:
6336 case MONO_PATCH_INFO_R4:
6337 g_assert_not_reached ();
6339 case MONO_PATCH_INFO_BB:
6346 * Debug code to help track down problems where the target of a near call is
6349 if (amd64_is_near_call (ip)) {
6350 gint64 disp = (guint8*)target - (guint8*)ip;
6352 if (!amd64_is_imm32 (disp)) {
6353 printf ("TYPE: %d\n", patch_info->type);
6354 switch (patch_info->type) {
6355 case MONO_PATCH_INFO_INTERNAL_METHOD:
6356 printf ("V: %s\n", patch_info->data.name);
6358 case MONO_PATCH_INFO_METHOD_JUMP:
6359 case MONO_PATCH_INFO_METHOD:
6360 printf ("V: %s\n", patch_info->data.method->name);
6368 amd64_patch (ip, (gpointer)target);
6375 get_max_epilog_size (MonoCompile *cfg)
6377 int max_epilog_size = 16;
6379 if (cfg->method->save_lmf)
6380 max_epilog_size += 256;
6382 if (mono_jit_trace_calls != NULL)
6383 max_epilog_size += 50;
6385 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6386 max_epilog_size += 50;
6388 max_epilog_size += (AMD64_NREG * 2);
6390 return max_epilog_size;
6394 * This macro is used for testing whenever the unwinder works correctly at every point
6395 * where an async exception can happen.
6397 /* This will generate a SIGSEGV at the given point in the code */
6398 #define async_exc_point(code) do { \
6399 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6400 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6401 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6402 cfg->arch.async_point_count ++; \
6407 mono_arch_emit_prolog (MonoCompile *cfg)
6409 MonoMethod *method = cfg->method;
6411 MonoMethodSignature *sig;
6413 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6416 MonoInst *lmf_var = cfg->lmf_var;
6417 gboolean args_clobbered = FALSE;
6418 gboolean trace = FALSE;
6419 #ifdef __native_client_codegen__
6420 guint alignment_check;
6423 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6425 #if defined(__default_codegen__)
6426 code = cfg->native_code = g_malloc (cfg->code_size);
6427 #elif defined(__native_client_codegen__)
6428 /* native_code_alloc is not 32-byte aligned, native_code is. */
6429 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6431 /* Align native_code to next nearest kNaclAlignment byte. */
6432 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6433 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6435 code = cfg->native_code;
6437 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6438 g_assert (alignment_check == 0);
6441 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6444 /* Amount of stack space allocated by register saving code */
6447 /* Offset between RSP and the CFA */
6451 * The prolog consists of the following parts:
6453 * - push rbp, mov rbp, rsp
6454 * - save callee saved regs using pushes
6456 * - save rgctx if needed
6457 * - save lmf if needed
6460 * - save rgctx if needed
6461 * - save lmf if needed
6462 * - save callee saved regs using moves
6467 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6468 // IP saved at CFA - 8
6469 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6470 async_exc_point (code);
6471 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6473 if (!cfg->arch.omit_fp) {
6474 amd64_push_reg (code, AMD64_RBP);
6476 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6477 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6478 async_exc_point (code);
6480 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6482 /* These are handled automatically by the stack marking code */
6483 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6485 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6486 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6487 async_exc_point (code);
6489 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6493 /* The param area is always at offset 0 from sp */
6494 /* This needs to be allocated here, since it has to come after the spill area */
6495 if (cfg->param_area) {
6496 if (cfg->arch.omit_fp)
6498 g_assert_not_reached ();
6499 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6502 if (cfg->arch.omit_fp) {
6504 * On enter, the stack is misaligned by the pushing of the return
6505 * address. It is either made aligned by the pushing of %rbp, or by
6508 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6509 if ((alloc_size % 16) == 0) {
6511 /* Mark the padding slot as NOREF */
6512 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6515 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6516 if (cfg->stack_offset != alloc_size) {
6517 /* Mark the padding slot as NOREF */
6518 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6520 cfg->arch.sp_fp_offset = alloc_size;
6524 cfg->arch.stack_alloc_size = alloc_size;
6526 /* Allocate stack frame */
6528 /* See mono_emit_stack_alloc */
6529 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6530 guint32 remaining_size = alloc_size;
6531 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6532 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6533 guint32 offset = code - cfg->native_code;
6534 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6535 while (required_code_size >= (cfg->code_size - offset))
6536 cfg->code_size *= 2;
6537 cfg->native_code = mono_realloc_native_code (cfg);
6538 code = cfg->native_code + offset;
6539 cfg->stat_code_reallocs++;
6542 while (remaining_size >= 0x1000) {
6543 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6544 if (cfg->arch.omit_fp) {
6545 cfa_offset += 0x1000;
6546 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6548 async_exc_point (code);
6550 if (cfg->arch.omit_fp)
6551 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6554 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6555 remaining_size -= 0x1000;
6557 if (remaining_size) {
6558 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6559 if (cfg->arch.omit_fp) {
6560 cfa_offset += remaining_size;
6561 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6562 async_exc_point (code);
6565 if (cfg->arch.omit_fp)
6566 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6570 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6571 if (cfg->arch.omit_fp) {
6572 cfa_offset += alloc_size;
6573 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6574 async_exc_point (code);
6579 /* Stack alignment check */
6582 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6583 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6584 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6585 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6586 amd64_breakpoint (code);
6590 if (mini_get_debug_options ()->init_stacks) {
6591 /* Fill the stack frame with a dummy value to force deterministic behavior */
6593 /* Save registers to the red zone */
6594 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6595 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6597 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6598 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6599 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6602 #if defined(__default_codegen__)
6603 amd64_prefix (code, X86_REP_PREFIX);
6605 #elif defined(__native_client_codegen__)
6606 /* NaCl stos pseudo-instruction */
6607 amd64_codegen_pre (code);
6608 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6609 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6610 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6611 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6612 amd64_prefix (code, X86_REP_PREFIX);
6614 amd64_codegen_post (code);
6615 #endif /* __native_client_codegen__ */
6617 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6618 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6622 if (method->save_lmf)
6623 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6625 /* Save callee saved registers */
6626 if (cfg->arch.omit_fp) {
6627 save_area_offset = cfg->arch.reg_save_area_offset;
6628 /* Save caller saved registers after sp is adjusted */
6629 /* The registers are saved at the bottom of the frame */
6630 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6632 /* The registers are saved just below the saved rbp */
6633 save_area_offset = cfg->arch.reg_save_area_offset;
6636 for (i = 0; i < AMD64_NREG; ++i) {
6637 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6638 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6640 if (cfg->arch.omit_fp) {
6641 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6642 /* These are handled automatically by the stack marking code */
6643 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6645 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6649 save_area_offset += 8;
6650 async_exc_point (code);
6654 /* store runtime generic context */
6655 if (cfg->rgctx_var) {
6656 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6657 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6659 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6661 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6662 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6665 /* compute max_length in order to use short forward jumps */
6666 max_epilog_size = get_max_epilog_size (cfg);
6667 if (cfg->opt & MONO_OPT_BRANCH) {
6668 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6672 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6674 /* max alignment for loops */
6675 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6676 max_length += LOOP_ALIGNMENT;
6677 #ifdef __native_client_codegen__
6678 /* max alignment for native client */
6679 max_length += kNaClAlignment;
6682 MONO_BB_FOR_EACH_INS (bb, ins) {
6683 #ifdef __native_client_codegen__
6685 int space_in_block = kNaClAlignment -
6686 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6687 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6688 if (space_in_block < max_len && max_len < kNaClAlignment) {
6689 max_length += space_in_block;
6692 #endif /*__native_client_codegen__*/
6693 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6696 /* Take prolog and epilog instrumentation into account */
6697 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6698 max_length += max_epilog_size;
6700 bb->max_length = max_length;
6704 sig = mono_method_signature (method);
6707 cinfo = cfg->arch.cinfo;
6709 if (sig->ret->type != MONO_TYPE_VOID) {
6710 /* Save volatile arguments to the stack */
6711 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6712 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6715 /* Keep this in sync with emit_load_volatile_arguments */
6716 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6717 ArgInfo *ainfo = cinfo->args + i;
6718 gint32 stack_offset;
6721 ins = cfg->args [i];
6723 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6724 /* Unused arguments */
6727 if (sig->hasthis && (i == 0))
6728 arg_type = &mono_defaults.object_class->byval_arg;
6730 arg_type = sig->params [i - sig->hasthis];
6732 stack_offset = ainfo->offset + ARGS_OFFSET;
6734 if (cfg->globalra) {
6735 /* All the other moves are done by the register allocator */
6736 switch (ainfo->storage) {
6737 case ArgInFloatSSEReg:
6738 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6740 case ArgValuetypeInReg:
6741 for (quad = 0; quad < 2; quad ++) {
6742 switch (ainfo->pair_storage [quad]) {
6744 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6746 case ArgInFloatSSEReg:
6747 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6749 case ArgInDoubleSSEReg:
6750 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6755 g_assert_not_reached ();
6766 /* Save volatile arguments to the stack */
6767 if (ins->opcode != OP_REGVAR) {
6768 switch (ainfo->storage) {
6774 if (stack_offset & 0x1)
6776 else if (stack_offset & 0x2)
6778 else if (stack_offset & 0x4)
6783 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6786 * Save the original location of 'this',
6787 * get_generic_info_from_stack_frame () needs this to properly look up
6788 * the argument value during the handling of async exceptions.
6790 if (ins == cfg->args [0]) {
6791 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6792 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6796 case ArgInFloatSSEReg:
6797 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6799 case ArgInDoubleSSEReg:
6800 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6802 case ArgValuetypeInReg:
6803 for (quad = 0; quad < 2; quad ++) {
6804 switch (ainfo->pair_storage [quad]) {
6806 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6808 case ArgInFloatSSEReg:
6809 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6811 case ArgInDoubleSSEReg:
6812 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6817 g_assert_not_reached ();
6821 case ArgValuetypeAddrInIReg:
6822 if (ainfo->pair_storage [0] == ArgInIReg)
6823 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6829 /* Argument allocated to (non-volatile) register */
6830 switch (ainfo->storage) {
6832 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6835 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6838 g_assert_not_reached ();
6841 if (ins == cfg->args [0]) {
6842 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6843 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6848 if (cfg->method->save_lmf)
6849 args_clobbered = TRUE;
6852 args_clobbered = TRUE;
6853 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6856 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6857 args_clobbered = TRUE;
6860 * Optimize the common case of the first bblock making a call with the same
6861 * arguments as the method. This works because the arguments are still in their
6862 * original argument registers.
6863 * FIXME: Generalize this
6865 if (!args_clobbered) {
6866 MonoBasicBlock *first_bb = cfg->bb_entry;
6869 next = mono_bb_first_ins (first_bb);
6870 if (!next && first_bb->next_bb) {
6871 first_bb = first_bb->next_bb;
6872 next = mono_bb_first_ins (first_bb);
6875 if (first_bb->in_count > 1)
6878 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6879 ArgInfo *ainfo = cinfo->args + i;
6880 gboolean match = FALSE;
6882 ins = cfg->args [i];
6883 if (ins->opcode != OP_REGVAR) {
6884 switch (ainfo->storage) {
6886 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6887 if (next->dreg == ainfo->reg) {
6891 next->opcode = OP_MOVE;
6892 next->sreg1 = ainfo->reg;
6893 /* Only continue if the instruction doesn't change argument regs */
6894 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6904 /* Argument allocated to (non-volatile) register */
6905 switch (ainfo->storage) {
6907 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6919 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6926 if (cfg->gen_seq_points) {
6927 MonoInst *info_var = cfg->arch.seq_point_info_var;
6929 /* Initialize seq_point_info_var */
6930 if (cfg->compile_aot) {
6931 /* Initialize the variable from a GOT slot */
6932 /* Same as OP_AOTCONST */
6933 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6934 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
6935 g_assert (info_var->opcode == OP_REGOFFSET);
6936 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
6939 /* Initialize ss_trigger_page_var */
6940 ins = cfg->arch.ss_trigger_page_var;
6942 g_assert (ins->opcode == OP_REGOFFSET);
6944 if (cfg->compile_aot) {
6945 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
6946 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
6948 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6950 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
6953 cfg->code_len = code - cfg->native_code;
6955 g_assert (cfg->code_len < cfg->code_size);
6961 mono_arch_emit_epilog (MonoCompile *cfg)
6963 MonoMethod *method = cfg->method;
6966 int max_epilog_size;
6968 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
6969 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6971 max_epilog_size = get_max_epilog_size (cfg);
6973 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6974 cfg->code_size *= 2;
6975 cfg->native_code = mono_realloc_native_code (cfg);
6976 cfg->stat_code_reallocs++;
6978 code = cfg->native_code + cfg->code_len;
6980 cfg->has_unwind_info_for_epilog = TRUE;
6982 /* Mark the start of the epilog */
6983 mono_emit_unwind_op_mark_loc (cfg, code, 0);
6985 /* Save the uwind state which is needed by the out-of-line code */
6986 mono_emit_unwind_op_remember_state (cfg, code);
6988 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6989 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6991 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
6994 if (method->save_lmf) {
6995 /* check if we need to restore protection of the stack after a stack overflow */
6996 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
6998 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
6999 /* we load the value in a separate instruction: this mechanism may be
7000 * used later as a safer way to do thread interruption
7002 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7003 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7005 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7006 /* note that the call trampoline will preserve eax/edx */
7007 x86_call_reg (code, X86_ECX);
7008 x86_patch (patch, code);
7010 /* FIXME: maybe save the jit tls in the prolog */
7012 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7013 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7017 /* Restore callee saved regs */
7018 for (i = 0; i < AMD64_NREG; ++i) {
7019 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7020 /* Restore only used_int_regs, not arch.saved_iregs */
7021 if (cfg->used_int_regs & (1 << i)) {
7022 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7023 mono_emit_unwind_op_same_value (cfg, code, i);
7024 async_exc_point (code);
7026 save_area_offset += 8;
7030 /* Load returned vtypes into registers if needed */
7031 cinfo = cfg->arch.cinfo;
7032 if (cinfo->ret.storage == ArgValuetypeInReg) {
7033 ArgInfo *ainfo = &cinfo->ret;
7034 MonoInst *inst = cfg->ret;
7036 for (quad = 0; quad < 2; quad ++) {
7037 switch (ainfo->pair_storage [quad]) {
7039 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7041 case ArgInFloatSSEReg:
7042 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7044 case ArgInDoubleSSEReg:
7045 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7050 g_assert_not_reached ();
7055 if (cfg->arch.omit_fp) {
7056 if (cfg->arch.stack_alloc_size) {
7057 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7061 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7063 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7064 async_exc_point (code);
7067 /* Restore the unwind state to be the same as before the epilog */
7068 mono_emit_unwind_op_restore_state (cfg, code);
7070 cfg->code_len = code - cfg->native_code;
7072 g_assert (cfg->code_len < cfg->code_size);
7076 mono_arch_emit_exceptions (MonoCompile *cfg)
7078 MonoJumpInfo *patch_info;
7081 MonoClass *exc_classes [16];
7082 guint8 *exc_throw_start [16], *exc_throw_end [16];
7083 guint32 code_size = 0;
7085 /* Compute needed space */
7086 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7087 if (patch_info->type == MONO_PATCH_INFO_EXC)
7089 if (patch_info->type == MONO_PATCH_INFO_R8)
7090 code_size += 8 + 15; /* sizeof (double) + alignment */
7091 if (patch_info->type == MONO_PATCH_INFO_R4)
7092 code_size += 4 + 15; /* sizeof (float) + alignment */
7093 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7094 code_size += 8 + 7; /*sizeof (void*) + alignment */
7097 #ifdef __native_client_codegen__
7098 /* Give us extra room on Native Client. This could be */
7099 /* more carefully calculated, but bundle alignment makes */
7100 /* it much trickier, so *2 like other places is good. */
7104 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7105 cfg->code_size *= 2;
7106 cfg->native_code = mono_realloc_native_code (cfg);
7107 cfg->stat_code_reallocs++;
7110 code = cfg->native_code + cfg->code_len;
7112 /* add code to raise exceptions */
7114 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7115 switch (patch_info->type) {
7116 case MONO_PATCH_INFO_EXC: {
7117 MonoClass *exc_class;
7121 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7123 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7124 g_assert (exc_class);
7125 throw_ip = patch_info->ip.i;
7127 //x86_breakpoint (code);
7128 /* Find a throw sequence for the same exception class */
7129 for (i = 0; i < nthrows; ++i)
7130 if (exc_classes [i] == exc_class)
7133 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7134 x86_jump_code (code, exc_throw_start [i]);
7135 patch_info->type = MONO_PATCH_INFO_NONE;
7139 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7143 exc_classes [nthrows] = exc_class;
7144 exc_throw_start [nthrows] = code;
7146 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7148 patch_info->type = MONO_PATCH_INFO_NONE;
7150 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7152 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7157 exc_throw_end [nthrows] = code;
7167 g_assert(code < cfg->native_code + cfg->code_size);
7170 /* Handle relocations with RIP relative addressing */
7171 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7172 gboolean remove = FALSE;
7173 guint8 *orig_code = code;
7175 switch (patch_info->type) {
7176 case MONO_PATCH_INFO_R8:
7177 case MONO_PATCH_INFO_R4: {
7178 guint8 *pos, *patch_pos;
7181 /* The SSE opcodes require a 16 byte alignment */
7182 #if defined(__default_codegen__)
7183 code = (guint8*)ALIGN_TO (code, 16);
7184 #elif defined(__native_client_codegen__)
7186 /* Pad this out with HLT instructions */
7187 /* or we can get garbage bytes emitted */
7188 /* which will fail validation */
7189 guint8 *aligned_code;
7190 /* extra align to make room for */
7191 /* mov/push below */
7192 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7193 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7194 /* The technique of hiding data in an */
7195 /* instruction has a problem here: we */
7196 /* need the data aligned to a 16-byte */
7197 /* boundary but the instruction cannot */
7198 /* cross the bundle boundary. so only */
7199 /* odd multiples of 16 can be used */
7200 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7203 while (code < aligned_code) {
7204 *(code++) = 0xf4; /* hlt */
7209 pos = cfg->native_code + patch_info->ip.i;
7210 if (IS_REX (pos [1])) {
7211 patch_pos = pos + 5;
7212 target_pos = code - pos - 9;
7215 patch_pos = pos + 4;
7216 target_pos = code - pos - 8;
7219 if (patch_info->type == MONO_PATCH_INFO_R8) {
7220 #ifdef __native_client_codegen__
7221 /* Hide 64-bit data in a */
7222 /* "mov imm64, r11" instruction. */
7223 /* write it before the start of */
7225 *(code-2) = 0x49; /* prefix */
7226 *(code-1) = 0xbb; /* mov X, %r11 */
7228 *(double*)code = *(double*)patch_info->data.target;
7229 code += sizeof (double);
7231 #ifdef __native_client_codegen__
7232 /* Hide 32-bit data in a */
7233 /* "push imm32" instruction. */
7234 *(code-1) = 0x68; /* push */
7236 *(float*)code = *(float*)patch_info->data.target;
7237 code += sizeof (float);
7240 *(guint32*)(patch_pos) = target_pos;
7245 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7248 if (cfg->compile_aot)
7251 /*loading is faster against aligned addresses.*/
7252 code = (guint8*)ALIGN_TO (code, 8);
7253 memset (orig_code, 0, code - orig_code);
7255 pos = cfg->native_code + patch_info->ip.i;
7257 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7258 if (IS_REX (pos [1]))
7259 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7261 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7263 *(gpointer*)code = (gpointer)patch_info->data.target;
7264 code += sizeof (gpointer);
7274 if (patch_info == cfg->patch_info)
7275 cfg->patch_info = patch_info->next;
7279 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7281 tmp->next = patch_info->next;
7284 g_assert (code < cfg->native_code + cfg->code_size);
7287 cfg->code_len = code - cfg->native_code;
7289 g_assert (cfg->code_len < cfg->code_size);
7293 #endif /* DISABLE_JIT */
7296 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7299 CallInfo *cinfo = NULL;
7300 MonoMethodSignature *sig;
7302 int i, n, stack_area = 0;
7304 /* Keep this in sync with mono_arch_get_argument_info */
7306 if (enable_arguments) {
7307 /* Allocate a new area on the stack and save arguments there */
7308 sig = mono_method_signature (cfg->method);
7310 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7312 n = sig->param_count + sig->hasthis;
7314 stack_area = ALIGN_TO (n * 8, 16);
7316 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7318 for (i = 0; i < n; ++i) {
7319 inst = cfg->args [i];
7321 if (inst->opcode == OP_REGVAR)
7322 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7324 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7325 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7330 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7331 amd64_set_reg_template (code, AMD64_ARG_REG1);
7332 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7333 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7335 if (enable_arguments)
7336 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7350 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7353 int save_mode = SAVE_NONE;
7354 MonoMethod *method = cfg->method;
7355 MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7358 switch (ret_type->type) {
7359 case MONO_TYPE_VOID:
7360 /* special case string .ctor icall */
7361 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7362 save_mode = SAVE_EAX;
7364 save_mode = SAVE_NONE;
7368 save_mode = SAVE_EAX;
7372 save_mode = SAVE_XMM;
7374 case MONO_TYPE_GENERICINST:
7375 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7376 save_mode = SAVE_EAX;
7380 case MONO_TYPE_VALUETYPE:
7381 save_mode = SAVE_STRUCT;
7384 save_mode = SAVE_EAX;
7388 /* Save the result and copy it into the proper argument register */
7389 switch (save_mode) {
7391 amd64_push_reg (code, AMD64_RAX);
7393 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7394 if (enable_arguments)
7395 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7399 if (enable_arguments)
7400 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7403 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7404 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7406 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7408 * The result is already in the proper argument register so no copying
7415 g_assert_not_reached ();
7418 /* Set %al since this is a varargs call */
7419 if (save_mode == SAVE_XMM)
7420 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7422 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7424 if (preserve_argument_registers) {
7425 for (i = 0; i < PARAM_REGS; ++i)
7426 amd64_push_reg (code, param_regs [i]);
7429 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7430 amd64_set_reg_template (code, AMD64_ARG_REG1);
7431 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7433 if (preserve_argument_registers) {
7434 for (i = PARAM_REGS - 1; i >= 0; --i)
7435 amd64_pop_reg (code, param_regs [i]);
7438 /* Restore result */
7439 switch (save_mode) {
7441 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7442 amd64_pop_reg (code, AMD64_RAX);
7448 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7449 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7450 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7455 g_assert_not_reached ();
7462 mono_arch_flush_icache (guint8 *code, gint size)
7468 mono_arch_flush_register_windows (void)
7473 mono_arch_is_inst_imm (gint64 imm)
7475 return amd64_is_imm32 (imm);
7479 * Determine whenever the trap whose info is in SIGINFO is caused by
7483 mono_arch_is_int_overflow (void *sigctx, void *info)
7490 mono_sigctx_to_monoctx (sigctx, &ctx);
7492 rip = (guint8*)ctx.rip;
7494 if (IS_REX (rip [0])) {
7495 reg = amd64_rex_b (rip [0]);
7501 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7503 reg += x86_modrm_rm (rip [1]);
7543 g_assert_not_reached ();
7555 mono_arch_get_patch_offset (guint8 *code)
7561 * mono_breakpoint_clean_code:
7563 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7564 * breakpoints in the original code, they are removed in the copy.
7566 * Returns TRUE if no sw breakpoint was present.
7569 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7572 gboolean can_write = TRUE;
7574 * If method_start is non-NULL we need to perform bound checks, since we access memory
7575 * at code - offset we could go before the start of the method and end up in a different
7576 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7579 if (!method_start || code - offset >= method_start) {
7580 memcpy (buf, code - offset, size);
7582 int diff = code - method_start;
7583 memset (buf, 0, size);
7584 memcpy (buf + offset - diff, method_start, diff + size - offset);
7587 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7588 int idx = mono_breakpoint_info_index [i];
7592 ptr = mono_breakpoint_info [idx].address;
7593 if (ptr >= code && ptr < code + size) {
7594 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7596 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7597 buf [ptr - code] = saved_byte;
7603 #if defined(__native_client_codegen__)
7604 /* For membase calls, we want the base register. for Native Client, */
7605 /* all indirect calls have the following sequence with the given sizes: */
7606 /* mov %eXX,%eXX [2-3] */
7607 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7608 /* and $0xffffffffffffffe0,%r11d [4] */
7609 /* add %r15,%r11 [3] */
7610 /* callq *%r11 [3] */
7613 /* Determine if code points to a NaCl call-through-register sequence, */
7614 /* (i.e., the last 3 instructions listed above) */
7616 is_nacl_call_reg_sequence(guint8* code)
7618 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7619 "\x4d\x03\xdf" /* add */
7620 "\x41\xff\xd3"; /* call */
7621 return memcmp(code, sequence, 10) == 0;
7624 /* Determine if code points to the first opcode of the mov membase component */
7625 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7626 /* (there could be a REX prefix before the opcode but it is ignored) */
7628 is_nacl_indirect_call_membase_sequence(guint8* code)
7630 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7631 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7632 /* and that src reg = dest reg */
7633 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7634 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7636 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7637 /* and has dst of r11 and base of r15 */
7638 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7639 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7641 #endif /* __native_client_codegen__ */
7644 mono_arch_get_this_arg_reg (guint8 *code)
7646 return AMD64_ARG_REG1;
7650 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7652 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7655 #define MAX_ARCH_DELEGATE_PARAMS 10
7658 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7660 guint8 *code, *start;
7664 start = code = mono_global_codeman_reserve (64);
7666 /* Replace the this argument with the target */
7667 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7668 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7669 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7671 g_assert ((code - start) < 64);
7673 start = code = mono_global_codeman_reserve (64);
7675 if (param_count == 0) {
7676 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7678 /* We have to shift the arguments left */
7679 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7680 for (i = 0; i < param_count; ++i) {
7683 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7685 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7687 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7691 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7693 g_assert ((code - start) < 64);
7696 nacl_global_codeman_validate (&start, 64, &code);
7699 *code_len = code - start;
7701 if (mono_jit_map_is_enabled ()) {
7704 buff = (char*)"delegate_invoke_has_target";
7706 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7707 mono_emit_jit_tramp (start, code - start, buff);
7716 * mono_arch_get_delegate_invoke_impls:
7718 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7722 mono_arch_get_delegate_invoke_impls (void)
7730 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7731 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7733 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7734 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7735 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7736 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7737 g_free (tramp_name);
7744 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7746 guint8 *code, *start;
7749 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7752 /* FIXME: Support more cases */
7753 if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7757 static guint8* cached = NULL;
7763 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7765 start = get_delegate_invoke_impl (TRUE, 0, NULL);
7767 mono_memory_barrier ();
7771 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7772 for (i = 0; i < sig->param_count; ++i)
7773 if (!mono_is_regsize_var (sig->params [i]))
7775 if (sig->param_count > 4)
7778 code = cache [sig->param_count];
7782 if (mono_aot_only) {
7783 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7784 start = mono_aot_get_trampoline (name);
7787 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7790 mono_memory_barrier ();
7792 cache [sig->param_count] = start;
7799 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7801 guint8 *code, *start;
7804 start = code = mono_global_codeman_reserve (size);
7806 /* Replace the this argument with the target */
7807 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7808 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7811 /* Load the IMT reg */
7812 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7815 /* Load the vtable */
7816 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7817 amd64_jump_membase (code, AMD64_RAX, offset);
7823 mono_arch_finish_init (void)
7825 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7826 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7831 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7835 #if defined(__default_codegen__)
7836 #define CMP_SIZE (6 + 1)
7837 #define CMP_REG_REG_SIZE (4 + 1)
7838 #define BR_SMALL_SIZE 2
7839 #define BR_LARGE_SIZE 6
7840 #define MOV_REG_IMM_SIZE 10
7841 #define MOV_REG_IMM_32BIT_SIZE 6
7842 #define JUMP_REG_SIZE (2 + 1)
7843 #elif defined(__native_client_codegen__)
7844 /* NaCl N-byte instructions can be padded up to N-1 bytes */
7845 #define CMP_SIZE ((6 + 1) * 2 - 1)
7846 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
7847 #define BR_SMALL_SIZE (2 * 2 - 1)
7848 #define BR_LARGE_SIZE (6 * 2 - 1)
7849 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
7850 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
7851 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
7852 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
7853 /* Jump membase's size is large and unpredictable */
7854 /* in native client, just pad it out a whole bundle. */
7855 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
7859 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7861 int i, distance = 0;
7862 for (i = start; i < target; ++i)
7863 distance += imt_entries [i]->chunk_size;
7868 * LOCKING: called with the domain lock held
7871 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7872 gpointer fail_tramp)
7876 guint8 *code, *start;
7877 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7879 for (i = 0; i < count; ++i) {
7880 MonoIMTCheckItem *item = imt_entries [i];
7881 if (item->is_equals) {
7882 if (item->check_target_idx) {
7883 if (!item->compare_done) {
7884 if (amd64_is_imm32 (item->key))
7885 item->chunk_size += CMP_SIZE;
7887 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7889 if (item->has_target_code) {
7890 item->chunk_size += MOV_REG_IMM_SIZE;
7892 if (vtable_is_32bit)
7893 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7895 item->chunk_size += MOV_REG_IMM_SIZE;
7896 #ifdef __native_client_codegen__
7897 item->chunk_size += JUMP_MEMBASE_SIZE;
7900 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7903 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7904 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7906 if (vtable_is_32bit)
7907 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7909 item->chunk_size += MOV_REG_IMM_SIZE;
7910 item->chunk_size += JUMP_REG_SIZE;
7911 /* with assert below:
7912 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7914 #ifdef __native_client_codegen__
7915 item->chunk_size += JUMP_MEMBASE_SIZE;
7920 if (amd64_is_imm32 (item->key))
7921 item->chunk_size += CMP_SIZE;
7923 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7924 item->chunk_size += BR_LARGE_SIZE;
7925 imt_entries [item->check_target_idx]->compare_done = TRUE;
7927 size += item->chunk_size;
7929 #if defined(__native_client__) && defined(__native_client_codegen__)
7930 /* In Native Client, we don't re-use thunks, allocate from the */
7931 /* normal code manager paths. */
7932 code = mono_domain_code_reserve (domain, size);
7935 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7937 code = mono_domain_code_reserve (domain, size);
7940 for (i = 0; i < count; ++i) {
7941 MonoIMTCheckItem *item = imt_entries [i];
7942 item->code_target = code;
7943 if (item->is_equals) {
7944 gboolean fail_case = !item->check_target_idx && fail_tramp;
7946 if (item->check_target_idx || fail_case) {
7947 if (!item->compare_done || fail_case) {
7948 if (amd64_is_imm32 (item->key))
7949 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7951 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7952 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7955 item->jmp_code = code;
7956 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7957 if (item->has_target_code) {
7958 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7959 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7961 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7962 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7966 amd64_patch (item->jmp_code, code);
7967 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7968 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7969 item->jmp_code = NULL;
7972 /* enable the commented code to assert on wrong method */
7974 if (amd64_is_imm32 (item->key))
7975 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7977 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7978 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7980 item->jmp_code = code;
7981 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7982 /* See the comment below about R10 */
7983 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7984 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7985 amd64_patch (item->jmp_code, code);
7986 amd64_breakpoint (code);
7987 item->jmp_code = NULL;
7989 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7990 needs to be preserved. R10 needs
7991 to be preserved for calls which
7992 require a runtime generic context,
7993 but interface calls don't. */
7994 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7995 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7999 if (amd64_is_imm32 (item->key))
8000 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8002 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8003 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8005 item->jmp_code = code;
8006 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8007 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8009 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8011 g_assert (code - item->code_target <= item->chunk_size);
8013 /* patch the branches to get to the target items */
8014 for (i = 0; i < count; ++i) {
8015 MonoIMTCheckItem *item = imt_entries [i];
8016 if (item->jmp_code) {
8017 if (item->check_target_idx) {
8018 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8024 mono_stats.imt_thunks_size += code - start;
8025 g_assert (code - start <= size);
8027 nacl_domain_code_validate(domain, &start, size, &code);
8033 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8035 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8039 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8041 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8045 mono_arch_get_cie_program (void)
8049 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8050 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8056 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8058 MonoInst *ins = NULL;
8061 if (cmethod->klass == mono_defaults.math_class) {
8062 if (strcmp (cmethod->name, "Sin") == 0) {
8064 } else if (strcmp (cmethod->name, "Cos") == 0) {
8066 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8068 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8073 MONO_INST_NEW (cfg, ins, opcode);
8074 ins->type = STACK_R8;
8075 ins->dreg = mono_alloc_freg (cfg);
8076 ins->sreg1 = args [0]->dreg;
8077 MONO_ADD_INS (cfg->cbb, ins);
8081 if (cfg->opt & MONO_OPT_CMOV) {
8082 if (strcmp (cmethod->name, "Min") == 0) {
8083 if (fsig->params [0]->type == MONO_TYPE_I4)
8085 if (fsig->params [0]->type == MONO_TYPE_U4)
8086 opcode = OP_IMIN_UN;
8087 else if (fsig->params [0]->type == MONO_TYPE_I8)
8089 else if (fsig->params [0]->type == MONO_TYPE_U8)
8090 opcode = OP_LMIN_UN;
8091 } else if (strcmp (cmethod->name, "Max") == 0) {
8092 if (fsig->params [0]->type == MONO_TYPE_I4)
8094 if (fsig->params [0]->type == MONO_TYPE_U4)
8095 opcode = OP_IMAX_UN;
8096 else if (fsig->params [0]->type == MONO_TYPE_I8)
8098 else if (fsig->params [0]->type == MONO_TYPE_U8)
8099 opcode = OP_LMAX_UN;
8104 MONO_INST_NEW (cfg, ins, opcode);
8105 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8106 ins->dreg = mono_alloc_ireg (cfg);
8107 ins->sreg1 = args [0]->dreg;
8108 ins->sreg2 = args [1]->dreg;
8109 MONO_ADD_INS (cfg->cbb, ins);
8113 /* OP_FREM is not IEEE compatible */
8114 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8115 MONO_INST_NEW (cfg, ins, OP_FREM);
8116 ins->inst_i0 = args [0];
8117 ins->inst_i1 = args [1];
8123 * Can't implement CompareExchange methods this way since they have
8131 mono_arch_print_tree (MonoInst *tree, int arity)
8136 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8139 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8142 case AMD64_RCX: return ctx->rcx;
8143 case AMD64_RDX: return ctx->rdx;
8144 case AMD64_RBX: return ctx->rbx;
8145 case AMD64_RBP: return ctx->rbp;
8146 case AMD64_RSP: return ctx->rsp;
8148 return _CTX_REG (ctx, rax, reg);
8153 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8172 _CTX_REG (ctx, rax, reg) = val;
8177 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8179 gpointer *sp, old_value;
8183 bp = MONO_CONTEXT_GET_BP (ctx);
8184 sp = *(gpointer*)(bp + clause->exvar_offset);
8187 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8196 * mono_arch_emit_load_aotconst:
8198 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8199 * TARGET from the mscorlib GOT in full-aot code.
8200 * On AMD64, the result is placed into R11.
8203 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8205 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8206 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8212 * mono_arch_get_trampolines:
8214 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8218 mono_arch_get_trampolines (gboolean aot)
8220 return mono_amd64_get_exception_trampolines (aot);
8223 /* Soft Debug support */
8224 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8227 * mono_arch_set_breakpoint:
8229 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8230 * The location should contain code emitted by OP_SEQ_POINT.
8233 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8236 guint8 *orig_code = code;
8239 guint32 native_offset = ip - (guint8*)ji->code_start;
8240 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8242 g_assert (info->bp_addrs [native_offset] == 0);
8243 info->bp_addrs [native_offset] = bp_trigger_page;
8246 * In production, we will use int3 (has to fix the size in the md
8247 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8250 g_assert (code [0] == 0x90);
8251 if (breakpoint_size == 8) {
8252 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8254 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8255 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8258 g_assert (code - orig_code == breakpoint_size);
8263 * mono_arch_clear_breakpoint:
8265 * Clear the breakpoint at IP.
8268 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8274 guint32 native_offset = ip - (guint8*)ji->code_start;
8275 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8277 g_assert (info->bp_addrs [native_offset] == 0);
8278 info->bp_addrs [native_offset] = info;
8280 for (i = 0; i < breakpoint_size; ++i)
8286 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8289 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8290 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8295 siginfo_t* sinfo = (siginfo_t*) info;
8296 /* Sometimes the address is off by 4 */
8297 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8305 * mono_arch_skip_breakpoint:
8307 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8308 * we resume, the instruction is not executed again.
8311 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8314 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8315 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8317 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8322 * mono_arch_start_single_stepping:
8324 * Start single stepping.
8327 mono_arch_start_single_stepping (void)
8329 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8333 * mono_arch_stop_single_stepping:
8335 * Stop single stepping.
8338 mono_arch_stop_single_stepping (void)
8340 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8344 * mono_arch_is_single_step_event:
8346 * Return whenever the machine state in SIGCTX corresponds to a single
8350 mono_arch_is_single_step_event (void *info, void *sigctx)
8353 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8354 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8359 siginfo_t* sinfo = (siginfo_t*) info;
8360 /* Sometimes the address is off by 4 */
8361 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8369 * mono_arch_skip_single_step:
8371 * Modify CTX so the ip is placed after the single step trigger instruction,
8372 * we resume, the instruction is not executed again.
8375 mono_arch_skip_single_step (MonoContext *ctx)
8377 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8381 * mono_arch_create_seq_point_info:
8383 * Return a pointer to a data structure which is used by the sequence
8384 * point implementation in AOTed code.
8387 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8393 // FIXME: Add a free function
8395 mono_domain_lock (domain);
8396 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8398 mono_domain_unlock (domain);
8401 ji = mono_jit_info_table_find (domain, (char*)code);
8404 // FIXME: Optimize the size
8405 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8407 info->ss_trigger_page = ss_trigger_page;
8408 info->bp_trigger_page = bp_trigger_page;
8409 /* Initialize to a valid address */
8410 for (i = 0; i < ji->code_size; ++i)
8411 info->bp_addrs [i] = info;
8413 mono_domain_lock (domain);
8414 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8416 mono_domain_unlock (domain);
8423 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8425 ext->lmf.previous_lmf = prev_lmf;
8426 /* Mark that this is a MonoLMFExt */
8427 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8428 ext->lmf.rsp = (gssize)ext;
8434 mono_arch_opcode_supported (int opcode)
8437 case OP_ATOMIC_ADD_I4:
8438 case OP_ATOMIC_ADD_I8:
8439 case OP_ATOMIC_EXCHANGE_I4:
8440 case OP_ATOMIC_EXCHANGE_I8:
8441 case OP_ATOMIC_CAS_I4:
8442 case OP_ATOMIC_CAS_I8: