mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "mini-amd64.h"
  30 #include "inssel.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 void mini_emit_memcpy2 (MonoCompile *cfg, int destreg, int doffset, int srcreg, int soffset, int size, int align);
  97
  98 const char*
  99 mono_arch_regname (int reg)
 100 {
 101         switch (reg) {
 102         case AMD64_RAX: return "%rax";
 103         case AMD64_RBX: return "%rbx";
 104         case AMD64_RCX: return "%rcx";
 105         case AMD64_RDX: return "%rdx";
 106         case AMD64_RSP: return "%rsp";
 107         case AMD64_RBP: return "%rbp";
 108         case AMD64_RDI: return "%rdi";
 109         case AMD64_RSI: return "%rsi";
 110         case AMD64_R8: return "%r8";
 111         case AMD64_R9: return "%r9";
 112         case AMD64_R10: return "%r10";
 113         case AMD64_R11: return "%r11";
 114         case AMD64_R12: return "%r12";
 115         case AMD64_R13: return "%r13";
 116         case AMD64_R14: return "%r14";
 117         case AMD64_R15: return "%r15";
 118         }
 119         return "unknown";
 120 }
 121
 122 static const char * xmmregs [] = {
 123         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 124         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 125 };
 126
 127 const char*
 128 mono_arch_fregname (int reg)
 129 {
 130         if (reg < AMD64_XMM_NREG)
 131                 return xmmregs [reg];
 132         else
 133                 return "unknown";
 134 }
 135
 136 G_GNUC_UNUSED static void
 137 break_count (void)
 138 {
 139 }
 140
 141 G_GNUC_UNUSED static gboolean
 142 debug_count (void)
 143 {
 144         static int count = 0;
 145         count ++;
 146
 147         if (!getenv ("COUNT"))
 148                 return TRUE;
 149
 150         if (count == atoi (getenv ("COUNT"))) {
 151                 break_count ();
 152         }
 153
 154         if (count > atoi (getenv ("COUNT"))) {
 155                 return FALSE;
 156         }
 157
 158         return TRUE;
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 static inline void
 182 amd64_patch (unsigned char* code, gpointer target)
 183 {
 184         guint8 rex = 0;
 185
 186         /* Skip REX */
 187         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 188                 rex = code [0];
 189                 code += 1;
 190         }
 191
 192         if ((code [0] & 0xf8) == 0xb8) {
 193                 /* amd64_set_reg_template */
 194                 *(guint64*)(code + 1) = (guint64)target;
 195         }
 196         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 197                 /* mov 0(%rip), %dreg */
 198                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 199         }
 200         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 201                 /* call *<OFFSET>(%rip) */
 202                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 203         }
 204         else if ((code [0] == 0xe8)) {
 205                 /* call <DISP> */
 206                 gint64 disp = (guint8*)target - (guint8*)code;
 207                 g_assert (amd64_is_imm32 (disp));
 208                 x86_patch (code, (unsigned char*)target);
 209         }
 210         else
 211                 x86_patch (code, (unsigned char*)target);
 212 }
 213
 214 void
 215 mono_amd64_patch (unsigned char* code, gpointer target)
 216 {
 217         amd64_patch (code, target);
 218 }
 219
 220 typedef enum {
 221         ArgInIReg,
 222         ArgInFloatSSEReg,
 223         ArgInDoubleSSEReg,
 224         ArgOnStack,
 225         ArgValuetypeInReg,
 226         ArgValuetypeAddrInIReg,
 227         ArgNone /* only in pair_storage */
 228 } ArgStorage;
 229
 230 typedef struct {
 231         gint16 offset;
 232         gint8  reg;
 233         ArgStorage storage;
 234
 235         /* Only if storage == ArgValuetypeInReg */
 236         ArgStorage pair_storage [2];
 237         gint8 pair_regs [2];
 238 } ArgInfo;
 239
 240 typedef struct {
 241         int nargs;
 242         guint32 stack_usage;
 243         guint32 reg_usage;
 244         guint32 freg_usage;
 245         gboolean need_stack_align;
 246         ArgInfo ret;
 247         ArgInfo sig_cookie;
 248         ArgInfo args [1];
 249 } CallInfo;
 250
 251 #define DEBUG(a) if (cfg->verbose_level > 1) a
 252
 253 #define NEW_ICONST(cfg,dest,val) do {   \
 254                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 255                 (dest)->opcode = OP_ICONST;     \
 256                 (dest)->inst_c0 = (val);        \
 257                 (dest)->type = STACK_I4;        \
 258         } while (0)
 259
 260 #ifdef PLATFORM_WIN32
 261 #define PARAM_REGS 4
 262
 263 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 264
 265 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 266 #else
 267 #define PARAM_REGS 6
 268
 269 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 270
 271  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 272 #endif
 273
 274 static void inline
 275 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 276 {
 277     ainfo->offset = *stack_size;
 278
 279     if (*gr >= PARAM_REGS) {
 280                 ainfo->storage = ArgOnStack;
 281                 (*stack_size) += sizeof (gpointer);
 282     }
 283     else {
 284                 ainfo->storage = ArgInIReg;
 285                 ainfo->reg = param_regs [*gr];
 286                 (*gr) ++;
 287     }
 288 }
 289
 290 #ifdef PLATFORM_WIN32
 291 #define FLOAT_PARAM_REGS 4
 292 #else
 293 #define FLOAT_PARAM_REGS 8
 294 #endif
 295
 296 static void inline
 297 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 298 {
 299     ainfo->offset = *stack_size;
 300
 301     if (*gr >= FLOAT_PARAM_REGS) {
 302                 ainfo->storage = ArgOnStack;
 303                 (*stack_size) += sizeof (gpointer);
 304     }
 305     else {
 306                 /* A double register */
 307                 if (is_double)
 308                         ainfo->storage = ArgInDoubleSSEReg;
 309                 else
 310                         ainfo->storage = ArgInFloatSSEReg;
 311                 ainfo->reg = *gr;
 312                 (*gr) += 1;
 313     }
 314 }
 315
 316 typedef enum ArgumentClass {
 317         ARG_CLASS_NO_CLASS,
 318         ARG_CLASS_MEMORY,
 319         ARG_CLASS_INTEGER,
 320         ARG_CLASS_SSE
 321 } ArgumentClass;
 322
 323 static ArgumentClass
 324 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 325 {
 326         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 327         MonoType *ptype;
 328
 329         ptype = mini_type_get_underlying_type (NULL, type);
 330         switch (ptype->type) {
 331         case MONO_TYPE_BOOLEAN:
 332         case MONO_TYPE_CHAR:
 333         case MONO_TYPE_I1:
 334         case MONO_TYPE_U1:
 335         case MONO_TYPE_I2:
 336         case MONO_TYPE_U2:
 337         case MONO_TYPE_I4:
 338         case MONO_TYPE_U4:
 339         case MONO_TYPE_I:
 340         case MONO_TYPE_U:
 341         case MONO_TYPE_STRING:
 342         case MONO_TYPE_OBJECT:
 343         case MONO_TYPE_CLASS:
 344         case MONO_TYPE_SZARRAY:
 345         case MONO_TYPE_PTR:
 346         case MONO_TYPE_FNPTR:
 347         case MONO_TYPE_ARRAY:
 348         case MONO_TYPE_I8:
 349         case MONO_TYPE_U8:
 350                 class2 = ARG_CLASS_INTEGER;
 351                 break;
 352         case MONO_TYPE_R4:
 353         case MONO_TYPE_R8:
 354 #ifdef PLATFORM_WIN32
 355                 class2 = ARG_CLASS_INTEGER;
 356 #else
 357                 class2 = ARG_CLASS_SSE;
 358 #endif
 359                 break;
 360
 361         case MONO_TYPE_TYPEDBYREF:
 362                 g_assert_not_reached ();
 363
 364         case MONO_TYPE_GENERICINST:
 365                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 366                         class2 = ARG_CLASS_INTEGER;
 367                         break;
 368                 }
 369                 /* fall through */
 370         case MONO_TYPE_VALUETYPE: {
 371                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 372                 int i;
 373
 374                 for (i = 0; i < info->num_fields; ++i) {
 375                         class2 = class1;
 376                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 377                 }
 378                 break;
 379         }
 380         default:
 381                 g_assert_not_reached ();
 382         }
 383
 384         /* Merge */
 385         if (class1 == class2)
 386                 ;
 387         else if (class1 == ARG_CLASS_NO_CLASS)
 388                 class1 = class2;
 389         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 390                 class1 = ARG_CLASS_MEMORY;
 391         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 392                 class1 = ARG_CLASS_INTEGER;
 393         else
 394                 class1 = ARG_CLASS_SSE;
 395
 396         return class1;
 397 }
 398
 399 static void
 400 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 401                gboolean is_return,
 402                guint32 *gr, guint32 *fr, guint32 *stack_size)
 403 {
 404         guint32 size, quad, nquads, i;
 405         ArgumentClass args [2];
 406         MonoMarshalType *info;
 407         MonoClass *klass;
 408         MonoGenericSharingContext tmp_gsctx;
 409
 410         /*
 411          * The gsctx currently contains no data, it is only used for checking whenever
 412          * open types are allowed, some callers like mono_arch_get_argument_info ()
 413          * don't pass it to us, so work around that.
 414          */
 415         if (!gsctx)
 416                 gsctx = &tmp_gsctx;
 417
 418         klass = mono_class_from_mono_type (type);
 419         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 420 #ifndef PLATFORM_WIN32
 421         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 422                 /* We pass and return vtypes of size 8 in a register */
 423         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 424 #else
 425         if (!sig->pinvoke) {
 426 #endif
 427                 /* Allways pass in memory */
 428                 ainfo->offset = *stack_size;
 429                 *stack_size += ALIGN_TO (size, 8);
 430                 ainfo->storage = ArgOnStack;
 431
 432                 return;
 433         }
 434
 435         /* FIXME: Handle structs smaller than 8 bytes */
 436         //if ((size % 8) != 0)
 437         //      NOT_IMPLEMENTED;
 438
 439         if (size > 8)
 440                 nquads = 2;
 441         else
 442                 nquads = 1;
 443
 444         if (!sig->pinvoke) {
 445                 /* Always pass in 1 or 2 integer registers */
 446                 args [0] = ARG_CLASS_INTEGER;
 447                 args [1] = ARG_CLASS_INTEGER;
 448                 /* Only the simplest cases are supported */
 449                 if (is_return && nquads != 1) {
 450                         args [0] = ARG_CLASS_MEMORY;
 451                         args [1] = ARG_CLASS_MEMORY;
 452                 }
 453         } else {
 454                 /*
 455                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 456                  * The X87 and SSEUP stuff is left out since there are no such types in
 457                  * the CLR.
 458                  */
 459                 info = mono_marshal_load_type_info (klass);
 460                 g_assert (info);
 461
 462 #ifndef PLATFORM_WIN32
 463                 if (info->native_size > 16) {
 464                         ainfo->offset = *stack_size;
 465                         *stack_size += ALIGN_TO (info->native_size, 8);
 466                         ainfo->storage = ArgOnStack;
 467
 468                         return;
 469                 }
 470 #else
 471                 switch (info->native_size) {
 472                 case 1: case 2: case 4: case 8:
 473                         break;
 474                 default:
 475                         if (is_return) {
 476                                 ainfo->storage = ArgOnStack;
 477                                 ainfo->offset = *stack_size;
 478                                 *stack_size += ALIGN_TO (info->native_size, 8);
 479                         }
 480                         else {
 481                                 ainfo->storage = ArgValuetypeAddrInIReg;
 482
 483                                 if (*gr < PARAM_REGS) {
 484                                         ainfo->pair_storage [0] = ArgInIReg;
 485                                         ainfo->pair_regs [0] = param_regs [*gr];
 486                                         (*gr) ++;
 487                                 }
 488                                 else {
 489                                         ainfo->pair_storage [0] = ArgOnStack;
 490                                         ainfo->offset = *stack_size;
 491                                         *stack_size += 8;
 492                                 }
 493                         }
 494
 495                         return;
 496                 }
 497 #endif
 498
 499                 args [0] = ARG_CLASS_NO_CLASS;
 500                 args [1] = ARG_CLASS_NO_CLASS;
 501                 for (quad = 0; quad < nquads; ++quad) {
 502                         int size;
 503                         guint32 align;
 504                         ArgumentClass class1;
 505
 506                         if (info->num_fields == 0)
 507                                 class1 = ARG_CLASS_MEMORY;
 508                         else
 509                                 class1 = ARG_CLASS_NO_CLASS;
 510                         for (i = 0; i < info->num_fields; ++i) {
 511                                 size = mono_marshal_type_size (info->fields [i].field->type,
 512                                                                                            info->fields [i].mspec,
 513                                                                                            &align, TRUE, klass->unicode);
 514                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 515                                         /* Unaligned field */
 516                                         NOT_IMPLEMENTED;
 517                                 }
 518
 519                                 /* Skip fields in other quad */
 520                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 521                                         continue;
 522                                 if ((quad == 1) && (info->fields [i].offset < 8))
 523                                         continue;
 524
 525                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 526                         }
 527                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 528                         args [quad] = class1;
 529                 }
 530         }
 531
 532         /* Post merger cleanup */
 533         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 534                 args [0] = args [1] = ARG_CLASS_MEMORY;
 535
 536         /* Allocate registers */
 537         {
 538                 int orig_gr = *gr;
 539                 int orig_fr = *fr;
 540
 541                 ainfo->storage = ArgValuetypeInReg;
 542                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 543                 for (quad = 0; quad < nquads; ++quad) {
 544                         switch (args [quad]) {
 545                         case ARG_CLASS_INTEGER:
 546                                 if (*gr >= PARAM_REGS)
 547                                         args [quad] = ARG_CLASS_MEMORY;
 548                                 else {
 549                                         ainfo->pair_storage [quad] = ArgInIReg;
 550                                         if (is_return)
 551                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 552                                         else
 553                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 554                                         (*gr) ++;
 555                                 }
 556                                 break;
 557                         case ARG_CLASS_SSE:
 558                                 if (*fr >= FLOAT_PARAM_REGS)
 559                                         args [quad] = ARG_CLASS_MEMORY;
 560                                 else {
 561                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 562                                         ainfo->pair_regs [quad] = *fr;
 563                                         (*fr) ++;
 564                                 }
 565                                 break;
 566                         case ARG_CLASS_MEMORY:
 567                                 break;
 568                         default:
 569                                 g_assert_not_reached ();
 570                         }
 571                 }
 572
 573                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 574                         /* Revert possible register assignments */
 575                         *gr = orig_gr;
 576                         *fr = orig_fr;
 577
 578                         ainfo->offset = *stack_size;
 579                         if (sig->pinvoke)
 580                                 *stack_size += ALIGN_TO (info->native_size, 8);
 581                         else
 582                                 *stack_size += nquads * sizeof (gpointer);
 583                         ainfo->storage = ArgOnStack;
 584                 }
 585         }
 586 }
 587
 588 /*
 589  * get_call_info:
 590  *
 591  *  Obtain information about a call according to the calling convention.
 592  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 593  * Draft Version 0.23" document for more information.
 594  */
 595 static CallInfo*
 596 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 597 {
 598         guint32 i, gr, fr;
 599         MonoType *ret_type;
 600         int n = sig->hasthis + sig->param_count;
 601         guint32 stack_size = 0;
 602         CallInfo *cinfo;
 603
 604         if (mp)
 605                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 606         else
 607                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 608
 609         gr = 0;
 610         fr = 0;
 611
 612         /* return value */
 613         {
 614                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 615                 switch (ret_type->type) {
 616                 case MONO_TYPE_BOOLEAN:
 617                 case MONO_TYPE_I1:
 618                 case MONO_TYPE_U1:
 619                 case MONO_TYPE_I2:
 620                 case MONO_TYPE_U2:
 621                 case MONO_TYPE_CHAR:
 622                 case MONO_TYPE_I4:
 623                 case MONO_TYPE_U4:
 624                 case MONO_TYPE_I:
 625                 case MONO_TYPE_U:
 626                 case MONO_TYPE_PTR:
 627                 case MONO_TYPE_FNPTR:
 628                 case MONO_TYPE_CLASS:
 629                 case MONO_TYPE_OBJECT:
 630                 case MONO_TYPE_SZARRAY:
 631                 case MONO_TYPE_ARRAY:
 632                 case MONO_TYPE_STRING:
 633                         cinfo->ret.storage = ArgInIReg;
 634                         cinfo->ret.reg = AMD64_RAX;
 635                         break;
 636                 case MONO_TYPE_U8:
 637                 case MONO_TYPE_I8:
 638                         cinfo->ret.storage = ArgInIReg;
 639                         cinfo->ret.reg = AMD64_RAX;
 640                         break;
 641                 case MONO_TYPE_R4:
 642                         cinfo->ret.storage = ArgInFloatSSEReg;
 643                         cinfo->ret.reg = AMD64_XMM0;
 644                         break;
 645                 case MONO_TYPE_R8:
 646                         cinfo->ret.storage = ArgInDoubleSSEReg;
 647                         cinfo->ret.reg = AMD64_XMM0;
 648                         break;
 649                 case MONO_TYPE_GENERICINST:
 650                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 651                                 cinfo->ret.storage = ArgInIReg;
 652                                 cinfo->ret.reg = AMD64_RAX;
 653                                 break;
 654                         }
 655                         /* fall through */
 656                 case MONO_TYPE_VALUETYPE: {
 657                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 658
 659                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 660                         if (cinfo->ret.storage == ArgOnStack)
 661                                 /* The caller passes the address where the value is stored */
 662                                 add_general (&gr, &stack_size, &cinfo->ret);
 663                         break;
 664                 }
 665                 case MONO_TYPE_TYPEDBYREF:
 666                         /* Same as a valuetype with size 24 */
 667                         add_general (&gr, &stack_size, &cinfo->ret);
 668                         ;
 669                         break;
 670                 case MONO_TYPE_VOID:
 671                         break;
 672                 default:
 673                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 674                 }
 675         }
 676
 677         /* this */
 678         if (sig->hasthis)
 679                 add_general (&gr, &stack_size, cinfo->args + 0);
 680
 681         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 682                 gr = PARAM_REGS;
 683                 fr = FLOAT_PARAM_REGS;
 684
 685                 /* Emit the signature cookie just before the implicit arguments */
 686                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 687         }
 688
 689         for (i = 0; i < sig->param_count; ++i) {
 690                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 691                 MonoType *ptype;
 692
 693 #ifdef PLATFORM_WIN32
 694                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 695                 if (gr > fr)
 696                         fr = gr;
 697                 else if (fr > gr)
 698                         gr = fr;
 699 #endif
 700
 701                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 702                         /* We allways pass the sig cookie on the stack for simplicity */
 703                         /*
 704                          * Prevent implicit arguments + the sig cookie from being passed
 705                          * in registers.
 706                          */
 707                         gr = PARAM_REGS;
 708                         fr = FLOAT_PARAM_REGS;
 709
 710                         /* Emit the signature cookie just before the implicit arguments */
 711                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 712                 }
 713
 714                 if (sig->params [i]->byref) {
 715                         add_general (&gr, &stack_size, ainfo);
 716                         continue;
 717                 }
 718                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 719                 switch (ptype->type) {
 720                 case MONO_TYPE_BOOLEAN:
 721                 case MONO_TYPE_I1:
 722                 case MONO_TYPE_U1:
 723                         add_general (&gr, &stack_size, ainfo);
 724                         break;
 725                 case MONO_TYPE_I2:
 726                 case MONO_TYPE_U2:
 727                 case MONO_TYPE_CHAR:
 728                         add_general (&gr, &stack_size, ainfo);
 729                         break;
 730                 case MONO_TYPE_I4:
 731                 case MONO_TYPE_U4:
 732                         add_general (&gr, &stack_size, ainfo);
 733                         break;
 734                 case MONO_TYPE_I:
 735                 case MONO_TYPE_U:
 736                 case MONO_TYPE_PTR:
 737                 case MONO_TYPE_FNPTR:
 738                 case MONO_TYPE_CLASS:
 739                 case MONO_TYPE_OBJECT:
 740                 case MONO_TYPE_STRING:
 741                 case MONO_TYPE_SZARRAY:
 742                 case MONO_TYPE_ARRAY:
 743                         add_general (&gr, &stack_size, ainfo);
 744                         break;
 745                 case MONO_TYPE_GENERICINST:
 746                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 747                                 add_general (&gr, &stack_size, ainfo);
 748                                 break;
 749                         }
 750                         /* fall through */
 751                 case MONO_TYPE_VALUETYPE:
 752                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 753                         break;
 754                 case MONO_TYPE_TYPEDBYREF:
 755 #ifdef PLATFORM_WIN32
 756                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 757 #else
 758                         stack_size += sizeof (MonoTypedRef);
 759                         ainfo->storage = ArgOnStack;
 760 #endif
 761                         break;
 762                 case MONO_TYPE_U8:
 763                 case MONO_TYPE_I8:
 764                         add_general (&gr, &stack_size, ainfo);
 765                         break;
 766                 case MONO_TYPE_R4:
 767                         add_float (&fr, &stack_size, ainfo, FALSE);
 768                         break;
 769                 case MONO_TYPE_R8:
 770                         add_float (&fr, &stack_size, ainfo, TRUE);
 771                         break;
 772                 default:
 773                         g_assert_not_reached ();
 774                 }
 775         }
 776
 777         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 778                 gr = PARAM_REGS;
 779                 fr = FLOAT_PARAM_REGS;
 780
 781                 /* Emit the signature cookie just before the implicit arguments */
 782                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 783         }
 784
 785 #ifdef PLATFORM_WIN32
 786         // There always is 32 bytes reserved on the stack when calling on Winx64
 787         stack_size += 0x20;
 788 #endif
 789
 790         if (stack_size & 0x8) {
 791                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 792                 cinfo->need_stack_align = TRUE;
 793                 stack_size += 8;
 794         }
 795
 796         cinfo->stack_usage = stack_size;
 797         cinfo->reg_usage = gr;
 798         cinfo->freg_usage = fr;
 799         return cinfo;
 800 }
 801
 802 /*
 803  * mono_arch_get_argument_info:
 804  * @csig:  a method signature
 805  * @param_count: the number of parameters to consider
 806  * @arg_info: an array to store the result infos
 807  *
 808  * Gathers information on parameters such as size, alignment and
 809  * padding. arg_info should be large enought to hold param_count + 1 entries.
 810  *
 811  * Returns the size of the argument area on the stack.
 812  */
 813 int
 814 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 815 {
 816         int k;
 817         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 818         guint32 args_size = cinfo->stack_usage;
 819
 820         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 821         if (csig->hasthis) {
 822                 arg_info [0].offset = 0;
 823         }
 824
 825         for (k = 0; k < param_count; k++) {
 826                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 827                 /* FIXME: */
 828                 arg_info [k + 1].size = 0;
 829         }
 830
 831         g_free (cinfo);
 832
 833         return args_size;
 834 }
 835
 836 static int
 837 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 838 {
 839 #ifndef _MSC_VER
 840         __asm__ __volatile__ ("cpuid"
 841                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 842                 : "a" (id));
 843 #else
 844         int info[4];
 845         __cpuid(info, id);
 846         *p_eax = info[0];
 847         *p_ebx = info[1];
 848         *p_ecx = info[2];
 849         *p_edx = info[3];
 850 #endif
 851         return 1;
 852 }
 853
 854 /*
 855  * Initialize the cpu to execute managed code.
 856  */
 857 void
 858 mono_arch_cpu_init (void)
 859 {
 860 #ifndef _MSC_VER
 861         guint16 fpcw;
 862
 863         /* spec compliance requires running with double precision */
 864         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 865         fpcw &= ~X86_FPCW_PRECC_MASK;
 866         fpcw |= X86_FPCW_PREC_DOUBLE;
 867         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 868         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 869 #else
 870         /* TODO: This is crashing on Win64 right now.
 871         * _control87 (_PC_53, MCW_PC);
 872         */
 873 #endif
 874 }
 875
 876 /*
 877  * Initialize architecture specific code.
 878  */
 879 void
 880 mono_arch_init (void)
 881 {
 882         InitializeCriticalSection (&mini_arch_mutex);
 883 }
 884
 885 /*
 886  * Cleanup architecture specific code.
 887  */
 888 void
 889 mono_arch_cleanup (void)
 890 {
 891         DeleteCriticalSection (&mini_arch_mutex);
 892 }
 893
 894 /*
 895  * This function returns the optimizations supported on this cpu.
 896  */
 897 guint32
 898 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 899 {
 900         int eax, ebx, ecx, edx;
 901         guint32 opts = 0;
 902
 903         /* FIXME: AMD64 */
 904
 905         *exclude_mask = 0;
 906         /* Feature Flags function, flags returned in EDX. */
 907         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 908                 if (edx & (1 << 15)) {
 909                         opts |= MONO_OPT_CMOV;
 910                         if (edx & 1)
 911                                 opts |= MONO_OPT_FCMOV;
 912                         else
 913                                 *exclude_mask |= MONO_OPT_FCMOV;
 914                 } else
 915                         *exclude_mask |= MONO_OPT_CMOV;
 916         }
 917
 918         return opts;
 919 }
 920
 921 GList *
 922 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 923 {
 924         GList *vars = NULL;
 925         int i;
 926
 927         for (i = 0; i < cfg->num_varinfo; i++) {
 928                 MonoInst *ins = cfg->varinfo [i];
 929                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 930
 931                 /* unused vars */
 932                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 933                         continue;
 934
 935                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 936                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 937                         continue;
 938
 939                 if (mono_is_regsize_var (ins->inst_vtype)) {
 940                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 941                         g_assert (i == vmv->idx);
 942                         vars = g_list_prepend (vars, vmv);
 943                 }
 944         }
 945
 946         vars = mono_varlist_sort (cfg, vars, 0);
 947
 948         return vars;
 949 }
 950
 951 /**
 952  * mono_arch_compute_omit_fp:
 953  *
 954  *   Determine whenever the frame pointer can be eliminated.
 955  */
 956 static void
 957 mono_arch_compute_omit_fp (MonoCompile *cfg)
 958 {
 959         MonoMethodSignature *sig;
 960         MonoMethodHeader *header;
 961         int i, locals_size;
 962         CallInfo *cinfo;
 963
 964         if (cfg->arch.omit_fp_computed)
 965                 return;
 966
 967         header = mono_method_get_header (cfg->method);
 968
 969         sig = mono_method_signature (cfg->method);
 970
 971         if (!cfg->arch.cinfo)
 972                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 973         cinfo = cfg->arch.cinfo;
 974
 975         /*
 976          * FIXME: Remove some of the restrictions.
 977          */
 978         cfg->arch.omit_fp = TRUE;
 979         cfg->arch.omit_fp_computed = TRUE;
 980
 981         if (cfg->disable_omit_fp)
 982                 cfg->arch.omit_fp = FALSE;
 983
 984         if (!debug_omit_fp ())
 985                 cfg->arch.omit_fp = FALSE;
 986         /*
 987         if (cfg->method->save_lmf)
 988                 cfg->arch.omit_fp = FALSE;
 989         */
 990         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 991                 cfg->arch.omit_fp = FALSE;
 992         if (header->num_clauses)
 993                 cfg->arch.omit_fp = FALSE;
 994         if (cfg->param_area)
 995                 cfg->arch.omit_fp = FALSE;
 996         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 997                 cfg->arch.omit_fp = FALSE;
 998         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 999                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1000                 cfg->arch.omit_fp = FALSE;
1001         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1002                 ArgInfo *ainfo = &cinfo->args [i];
1003
1004                 if (ainfo->storage == ArgOnStack) {
1005                         /*
1006                          * The stack offset can only be determined when the frame
1007                          * size is known.
1008                          */
1009                         cfg->arch.omit_fp = FALSE;
1010                 }
1011         }
1012
1013         locals_size = 0;
1014         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1015                 MonoInst *ins = cfg->varinfo [i];
1016                 int ialign;
1017
1018                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1019         }
1020
1021         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1022                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1023                 cfg->arch.omit_fp = FALSE;
1024         }
1025 }
1026
1027 GList *
1028 mono_arch_get_global_int_regs (MonoCompile *cfg)
1029 {
1030         GList *regs = NULL;
1031
1032         mono_arch_compute_omit_fp (cfg);
1033
1034         if (cfg->globalra) {
1035                 if (cfg->arch.omit_fp)
1036                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1037
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1041                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1042                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1043
1044                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1045                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1046                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1047                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1051                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1052         } else {
1053                 if (cfg->arch.omit_fp)
1054                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1055
1056                 /* We use the callee saved registers for global allocation */
1057                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1058                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1059                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1060                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1061                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1062         }
1063
1064         return regs;
1065 }
1066
1067 GList*
1068 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1069 {
1070         GList *regs = NULL;
1071         int i;
1072
1073         /* All XMM registers */
1074         for (i = 0; i < 16; ++i)
1075                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1076
1077         return regs;
1078 }
1079
1080 GList*
1081 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1082 {
1083         static GList *r = NULL;
1084
1085         if (r == NULL) {
1086                 GList *regs = NULL;
1087
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1093                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1094
1095                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1096                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1097                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1098                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1099                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1100                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1101                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1102                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1103
1104                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1105         }
1106
1107         return r;
1108 }
1109
1110 GList*
1111 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1112 {
1113         int i;
1114         static GList *r = NULL;
1115
1116         if (r == NULL) {
1117                 GList *regs = NULL;
1118
1119                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1120                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1121
1122                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1123         }
1124
1125         return r;
1126 }
1127
1128 /*
1129  * mono_arch_regalloc_cost:
1130  *
1131  *  Return the cost, in number of memory references, of the action of
1132  * allocating the variable VMV into a register during global register
1133  * allocation.
1134  */
1135 guint32
1136 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1137 {
1138         MonoInst *ins = cfg->varinfo [vmv->idx];
1139
1140         if (cfg->method->save_lmf)
1141                 /* The register is already saved */
1142                 /* substract 1 for the invisible store in the prolog */
1143                 return (ins->opcode == OP_ARG) ? 0 : 1;
1144         else
1145                 /* push+pop */
1146                 return (ins->opcode == OP_ARG) ? 1 : 2;
1147 }
1148
1149 /*
1150  * mono_arch_fill_argument_info:
1151  *
1152  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1153  * of the method.
1154  */
1155 void
1156 mono_arch_fill_argument_info (MonoCompile *cfg)
1157 {
1158         MonoMethodSignature *sig;
1159         MonoMethodHeader *header;
1160         MonoInst *ins;
1161         int i;
1162         CallInfo *cinfo;
1163
1164         header = mono_method_get_header (cfg->method);
1165
1166         sig = mono_method_signature (cfg->method);
1167
1168         cinfo = cfg->arch.cinfo;
1169
1170         /*
1171          * Contrary to mono_arch_allocate_vars (), the information should describe
1172          * where the arguments are at the beginning of the method, not where they can be
1173          * accessed during the execution of the method. The later makes no sense for the
1174          * global register allocator, since a variable can be in more than one location.
1175          */
1176         if (sig->ret->type != MONO_TYPE_VOID) {
1177                 switch (cinfo->ret.storage) {
1178                 case ArgInIReg:
1179                 case ArgInFloatSSEReg:
1180                 case ArgInDoubleSSEReg:
1181                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1182                                 cfg->vret_addr->opcode = OP_REGVAR;
1183                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1184                         }
1185                         else {
1186                                 cfg->ret->opcode = OP_REGVAR;
1187                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1188                         }
1189                         break;
1190                 case ArgValuetypeInReg:
1191                         cfg->ret->opcode = OP_REGOFFSET;
1192                         cfg->ret->inst_basereg = -1;
1193                         cfg->ret->inst_offset = -1;
1194                         break;
1195                 default:
1196                         g_assert_not_reached ();
1197                 }
1198         }
1199
1200         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1201                 ArgInfo *ainfo = &cinfo->args [i];
1202                 MonoType *arg_type;
1203
1204                 ins = cfg->args [i];
1205
1206                 if (sig->hasthis && (i == 0))
1207                         arg_type = &mono_defaults.object_class->byval_arg;
1208                 else
1209                         arg_type = sig->params [i - sig->hasthis];
1210
1211                 switch (ainfo->storage) {
1212                 case ArgInIReg:
1213                 case ArgInFloatSSEReg:
1214                 case ArgInDoubleSSEReg:
1215                         ins->opcode = OP_REGVAR;
1216                         ins->inst_c0 = ainfo->reg;
1217                         break;
1218                 case ArgOnStack:
1219                         ins->opcode = OP_REGOFFSET;
1220                         ins->inst_basereg = -1;
1221                         ins->inst_offset = -1;
1222                         break;
1223                 case ArgValuetypeInReg:
1224                         /* Dummy */
1225                         ins->opcode = OP_NOP;
1226                         break;
1227                 default:
1228                         g_assert_not_reached ();
1229                 }
1230         }
1231 }
1232
1233 void
1234 mono_arch_allocate_vars (MonoCompile *cfg)
1235 {
1236         MonoMethodSignature *sig;
1237         MonoMethodHeader *header;
1238         MonoInst *ins;
1239         int i, offset;
1240         guint32 locals_stack_size, locals_stack_align;
1241         gint32 *offsets;
1242         CallInfo *cinfo;
1243
1244         header = mono_method_get_header (cfg->method);
1245
1246         sig = mono_method_signature (cfg->method);
1247
1248         cinfo = cfg->arch.cinfo;
1249
1250         mono_arch_compute_omit_fp (cfg);
1251
1252         /*
1253          * We use the ABI calling conventions for managed code as well.
1254          * Exception: valuetypes are never passed or returned in registers.
1255          */
1256
1257         if (cfg->arch.omit_fp) {
1258                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1259                 cfg->frame_reg = AMD64_RSP;
1260                 offset = 0;
1261         } else {
1262                 /* Locals are allocated backwards from %fp */
1263                 cfg->frame_reg = AMD64_RBP;
1264                 offset = 0;
1265         }
1266
1267         if (cfg->method->save_lmf) {
1268                 /* Reserve stack space for saving LMF */
1269                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1270                 g_assert (offset == 0);
1271                 if (cfg->arch.omit_fp) {
1272                         cfg->arch.lmf_offset = offset;
1273                         offset += sizeof (MonoLMF);
1274                 }
1275                 else {
1276                         offset += sizeof (MonoLMF);
1277                         cfg->arch.lmf_offset = -offset;
1278                 }
1279         } else {
1280                 if (cfg->arch.omit_fp)
1281                         cfg->arch.reg_save_area_offset = offset;
1282                 /* Reserve space for caller saved registers */
1283                 for (i = 0; i < AMD64_NREG; ++i)
1284                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1285                                 offset += sizeof (gpointer);
1286                         }
1287         }
1288
1289         if (sig->ret->type != MONO_TYPE_VOID) {
1290                 switch (cinfo->ret.storage) {
1291                 case ArgInIReg:
1292                 case ArgInFloatSSEReg:
1293                 case ArgInDoubleSSEReg:
1294                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1295                                 if (cfg->globalra) {
1296                                         cfg->vret_addr->opcode = OP_REGVAR;
1297                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1298                                 } else {
1299                                         /* The register is volatile */
1300                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1301                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1302                                         if (cfg->arch.omit_fp) {
1303                                                 cfg->vret_addr->inst_offset = offset;
1304                                                 offset += 8;
1305                                         } else {
1306                                                 offset += 8;
1307                                                 cfg->vret_addr->inst_offset = -offset;
1308                                         }
1309                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1310                                                 printf ("vret_addr =");
1311                                                 mono_print_ins (cfg->vret_addr);
1312                                         }
1313                                 }
1314                         }
1315                         else {
1316                                 cfg->ret->opcode = OP_REGVAR;
1317                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1318                         }
1319                         break;
1320                 case ArgValuetypeInReg:
1321                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1322                         cfg->ret->opcode = OP_REGOFFSET;
1323                         cfg->ret->inst_basereg = cfg->frame_reg;
1324                         if (cfg->arch.omit_fp) {
1325                                 cfg->ret->inst_offset = offset;
1326                                 offset += 16;
1327                         } else {
1328                                 offset += 16;
1329                                 cfg->ret->inst_offset = - offset;
1330                         }
1331                         break;
1332                 default:
1333                         g_assert_not_reached ();
1334                 }
1335                 if (!cfg->globalra)
1336                         cfg->ret->dreg = cfg->ret->inst_c0;
1337         }
1338
1339         /* Allocate locals */
1340         if (!cfg->globalra) {
1341                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1342                 if (locals_stack_align) {
1343                         offset += (locals_stack_align - 1);
1344                         offset &= ~(locals_stack_align - 1);
1345                 }
1346                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1347                         if (offsets [i] != -1) {
1348                                 MonoInst *ins = cfg->varinfo [i];
1349                                 ins->opcode = OP_REGOFFSET;
1350                                 ins->inst_basereg = cfg->frame_reg;
1351                                 if (cfg->arch.omit_fp)
1352                                         ins->inst_offset = (offset + offsets [i]);
1353                                 else
1354                                         ins->inst_offset = - (offset + offsets [i]);
1355                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1356                         }
1357                 }
1358                 offset += locals_stack_size;
1359         }
1360
1361         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1362                 g_assert (!cfg->arch.omit_fp);
1363                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1364                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1365         }
1366
1367         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1368                 ins = cfg->args [i];
1369                 if (ins->opcode != OP_REGVAR) {
1370                         ArgInfo *ainfo = &cinfo->args [i];
1371                         gboolean inreg = TRUE;
1372                         MonoType *arg_type;
1373
1374                         if (sig->hasthis && (i == 0))
1375                                 arg_type = &mono_defaults.object_class->byval_arg;
1376                         else
1377                                 arg_type = sig->params [i - sig->hasthis];
1378
1379                         if (cfg->globalra) {
1380                                 /* The new allocator needs info about the original locations of the arguments */
1381                                 switch (ainfo->storage) {
1382                                 case ArgInIReg:
1383                                 case ArgInFloatSSEReg:
1384                                 case ArgInDoubleSSEReg:
1385                                         ins->opcode = OP_REGVAR;
1386                                         ins->inst_c0 = ainfo->reg;
1387                                         break;
1388                                 case ArgOnStack:
1389                                         g_assert (!cfg->arch.omit_fp);
1390                                         ins->opcode = OP_REGOFFSET;
1391                                         ins->inst_basereg = cfg->frame_reg;
1392                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1393                                         break;
1394                                 case ArgValuetypeInReg:
1395                                         ins->opcode = OP_REGOFFSET;
1396                                         ins->inst_basereg = cfg->frame_reg;
1397                                         /* These arguments are saved to the stack in the prolog */
1398                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1399                                         if (cfg->arch.omit_fp) {
1400                                                 ins->inst_offset = offset;
1401                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1402                                         } else {
1403                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1404                                                 ins->inst_offset = - offset;
1405                                         }
1406                                         break;
1407                                 default:
1408                                         g_assert_not_reached ();
1409                                 }
1410
1411                                 continue;
1412                         }
1413
1414                         /* FIXME: Allocate volatile arguments to registers */
1415                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1416                                 inreg = FALSE;
1417
1418                         /*
1419                          * Under AMD64, all registers used to pass arguments to functions
1420                          * are volatile across calls.
1421                          * FIXME: Optimize this.
1422                          */
1423                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1424                                 inreg = FALSE;
1425
1426                         ins->opcode = OP_REGOFFSET;
1427
1428                         switch (ainfo->storage) {
1429                         case ArgInIReg:
1430                         case ArgInFloatSSEReg:
1431                         case ArgInDoubleSSEReg:
1432                                 if (inreg) {
1433                                         ins->opcode = OP_REGVAR;
1434                                         ins->dreg = ainfo->reg;
1435                                 }
1436                                 break;
1437                         case ArgOnStack:
1438                                 g_assert (!cfg->arch.omit_fp);
1439                                 ins->opcode = OP_REGOFFSET;
1440                                 ins->inst_basereg = cfg->frame_reg;
1441                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1442                                 break;
1443                         case ArgValuetypeInReg:
1444                                 break;
1445                         case ArgValuetypeAddrInIReg: {
1446                                 MonoInst *indir;
1447                                 g_assert (!cfg->arch.omit_fp);
1448
1449                                 MONO_INST_NEW (cfg, indir, 0);
1450                                 indir->opcode = OP_REGOFFSET;
1451                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1452                                         indir->inst_basereg = cfg->frame_reg;
1453                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1454                                         offset += (sizeof (gpointer));
1455                                         indir->inst_offset = - offset;
1456                                 }
1457                                 else {
1458                                         indir->inst_basereg = cfg->frame_reg;
1459                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1460                                 }
1461
1462                                 ins->opcode = OP_VTARG_ADDR;
1463                                 ins->inst_left = indir;
1464
1465                                 break;
1466                         }
1467                         default:
1468                                 NOT_IMPLEMENTED;
1469                         }
1470
1471                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1472                                 ins->opcode = OP_REGOFFSET;
1473                                 ins->inst_basereg = cfg->frame_reg;
1474                                 /* These arguments are saved to the stack in the prolog */
1475                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1476                                 if (cfg->arch.omit_fp) {
1477                                         ins->inst_offset = offset;
1478                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1479                                 } else {
1480                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1481                                         ins->inst_offset = - offset;
1482                                 }
1483                         }
1484                 }
1485         }
1486
1487         cfg->stack_offset = offset;
1488 }
1489
1490 void
1491 mono_arch_create_vars (MonoCompile *cfg)
1492 {
1493         MonoMethodSignature *sig;
1494         CallInfo *cinfo;
1495
1496         sig = mono_method_signature (cfg->method);
1497
1498         if (!cfg->arch.cinfo)
1499                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1500         cinfo = cfg->arch.cinfo;
1501
1502         if (cinfo->ret.storage == ArgValuetypeInReg)
1503                 cfg->ret_var_is_local = TRUE;
1504
1505         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1506                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1507                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1508                         printf ("vret_addr = ");
1509                         mono_print_ins (cfg->vret_addr);
1510                 }
1511         }
1512 }
1513
1514 static void
1515 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1516 {
1517         switch (storage) {
1518         case ArgInIReg:
1519                 arg->opcode = OP_OUTARG_REG;
1520                 arg->inst_left = tree;
1521                 arg->inst_call = call;
1522                 arg->backend.reg3 = reg;
1523                 break;
1524         case ArgInFloatSSEReg:
1525                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1526                 arg->inst_left = tree;
1527                 arg->inst_call = call;
1528                 arg->backend.reg3 = reg;
1529                 break;
1530         case ArgInDoubleSSEReg:
1531                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1532                 arg->inst_left = tree;
1533                 arg->inst_call = call;
1534                 arg->backend.reg3 = reg;
1535                 break;
1536         default:
1537                 g_assert_not_reached ();
1538         }
1539 }
1540
1541 static void
1542 add_outarg_reg2 (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1543 {
1544         MonoInst *ins;
1545
1546         switch (storage) {
1547         case ArgInIReg:
1548                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1549                 ins->dreg = mono_alloc_ireg (cfg);
1550                 ins->sreg1 = tree->dreg;
1551                 MONO_ADD_INS (cfg->cbb, ins);
1552                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1553                 break;
1554         case ArgInFloatSSEReg:
1555                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1556                 ins->dreg = mono_alloc_freg (cfg);
1557                 ins->sreg1 = tree->dreg;
1558                 MONO_ADD_INS (cfg->cbb, ins);
1559
1560                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1561                 break;
1562         case ArgInDoubleSSEReg:
1563                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1564                 ins->dreg = mono_alloc_freg (cfg);
1565                 ins->sreg1 = tree->dreg;
1566                 MONO_ADD_INS (cfg->cbb, ins);
1567
1568                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1569
1570                 break;
1571         default:
1572                 g_assert_not_reached ();
1573         }
1574 }
1575
1576 static int
1577 arg_storage_to_ldind (ArgStorage storage)
1578 {
1579         switch (storage) {
1580         case ArgInIReg:
1581                 return CEE_LDIND_I;
1582         case ArgInDoubleSSEReg:
1583                 return CEE_LDIND_R8;
1584         case ArgInFloatSSEReg:
1585                 return CEE_LDIND_R4;
1586         default:
1587                 g_assert_not_reached ();
1588         }
1589
1590         return -1;
1591 }
1592
1593 static int
1594 arg_storage_to_load_membase (ArgStorage storage)
1595 {
1596         switch (storage) {
1597         case ArgInIReg:
1598                 return OP_LOAD_MEMBASE;
1599         case ArgInDoubleSSEReg:
1600                 return OP_LOADR8_MEMBASE;
1601         case ArgInFloatSSEReg:
1602                 return OP_LOADR4_MEMBASE;
1603         default:
1604                 g_assert_not_reached ();
1605         }
1606
1607         return -1;
1608 }
1609
1610 static void
1611 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1612 {
1613         MonoInst *arg;
1614         MonoMethodSignature *tmp_sig;
1615         MonoInst *sig_arg;
1616
1617         /* FIXME: Add support for signature tokens to AOT */
1618         cfg->disable_aot = TRUE;
1619
1620         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1621
1622         /*
1623          * mono_ArgIterator_Setup assumes the signature cookie is
1624          * passed first and all the arguments which were before it are
1625          * passed on the stack after the signature. So compensate by
1626          * passing a different signature.
1627          */
1628         tmp_sig = mono_metadata_signature_dup (call->signature);
1629         tmp_sig->param_count -= call->signature->sentinelpos;
1630         tmp_sig->sentinelpos = 0;
1631         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1632
1633         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1634         sig_arg->inst_p0 = tmp_sig;
1635
1636         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1637         arg->inst_left = sig_arg;
1638         arg->type = STACK_PTR;
1639
1640         /* prepend, so they get reversed */
1641         arg->next = call->out_args;
1642         call->out_args = arg;
1643 }
1644
1645 /*
1646  * take the arguments and generate the arch-specific
1647  * instructions to properly call the function in call.
1648  * This includes pushing, moving arguments to the right register
1649  * etc.
1650  */
1651 MonoCallInst*
1652 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1653         MonoInst *arg, *in;
1654         MonoMethodSignature *sig;
1655         int i, n, stack_size;
1656         CallInfo *cinfo;
1657         ArgInfo *ainfo;
1658
1659         stack_size = 0;
1660
1661         sig = call->signature;
1662         n = sig->param_count + sig->hasthis;
1663
1664         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1665
1666         if (cfg->method->save_lmf) {
1667                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1668                 arg->next = call->out_args;
1669                 call->out_args = arg;
1670         }
1671
1672         for (i = 0; i < n; ++i) {
1673                 ainfo = cinfo->args + i;
1674
1675                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1676                         /* Emit the signature cookie just before the implicit arguments */
1677                         emit_sig_cookie (cfg, call, cinfo);
1678                 }
1679
1680                 if (is_virtual && i == 0) {
1681                         /* the argument will be attached to the call instruction */
1682                         in = call->args [i];
1683                 } else {
1684                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1685                         in = call->args [i];
1686                         arg->cil_code = in->cil_code;
1687                         arg->inst_left = in;
1688                         arg->type = in->type;
1689                         /* prepend, so they get reversed */
1690                         arg->next = call->out_args;
1691                         call->out_args = arg;
1692 #if 0
1693                         if (!cinfo->stack_usage)
1694                                 /* Keep the assignments to the arg registers in order if possible */
1695                                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1696                         else
1697                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1698 #endif
1699
1700                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1701                                 guint32 align;
1702                                 guint32 size;
1703
1704                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1705                                         size = sizeof (MonoTypedRef);
1706                                         align = sizeof (gpointer);
1707                                 }
1708                                 else
1709                                 if (sig->pinvoke)
1710                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1711                                 else {
1712                                         /*
1713                                          * Other backends use mini_type_stack_size (), but that
1714                                          * aligns the size to 8, which is larger than the size of
1715                                          * the source, leading to reads of invalid memory if the
1716                                          * source is at the end of address space.
1717                                          */
1718                                         size = mono_class_value_size (in->klass, &align);
1719                                 }
1720                                 if (ainfo->storage == ArgValuetypeInReg) {
1721                                         if (ainfo->pair_storage [1] == ArgNone) {
1722                                                 MonoInst *load;
1723
1724                                                 /* Simpler case */
1725
1726                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1727                                                 load->inst_left = in;
1728
1729                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1730                                         }
1731                                         else {
1732                                                 /* Trees can't be shared so make a copy */
1733                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1734                                                 MonoInst *load, *load2, *offset_ins;
1735
1736                                                 /* Reg1 */
1737                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1738                                                 load->ssa_op = MONO_SSA_LOAD;
1739                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1740
1741                                                 NEW_ICONST (cfg, offset_ins, 0);
1742                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1743                                                 load2->inst_left = load;
1744                                                 load2->inst_right = offset_ins;
1745
1746                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1747                                                 load->inst_left = load2;
1748
1749                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1750
1751                                                 /* Reg2 */
1752                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1753                                                 load->ssa_op = MONO_SSA_LOAD;
1754                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1755
1756                                                 NEW_ICONST (cfg, offset_ins, 8);
1757                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1758                                                 load2->inst_left = load;
1759                                                 load2->inst_right = offset_ins;
1760
1761                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1762                                                 load->inst_left = load2;
1763
1764                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1765                                                 arg->cil_code = in->cil_code;
1766                                                 arg->type = in->type;
1767                                                 /* prepend, so they get reversed */
1768                                                 arg->next = call->out_args;
1769                                                 call->out_args = arg;
1770
1771                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1772
1773                                                 /* Prepend a copy inst */
1774                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1775                                                 arg->cil_code = in->cil_code;
1776                                                 arg->ssa_op = MONO_SSA_STORE;
1777                                                 arg->inst_left = vtaddr;
1778                                                 arg->inst_right = in;
1779                                                 arg->type = in->type;
1780
1781                                                 /* prepend, so they get reversed */
1782                                                 arg->next = call->out_args;
1783                                                 call->out_args = arg;
1784                                         }
1785                                 }
1786                                 else if (ainfo->storage == ArgValuetypeAddrInIReg){
1787
1788                                         /* Add a temp variable to the method*/
1789                                         MonoInst *load;
1790                                         MonoInst *vtaddr = mono_compile_create_var (cfg, &in->klass->byval_arg, OP_LOCAL);
1791
1792                                         MONO_INST_NEW (cfg, load, OP_LDADDR);
1793                                         load->ssa_op = MONO_SSA_LOAD;
1794                                         load->inst_left = vtaddr;
1795
1796                                         if (ainfo->pair_storage [0] == ArgInIReg) {
1797                                                 /* Inserted after the copy.  Load the address of the temp to the argument regster.*/
1798                                                 arg->opcode = OP_OUTARG_REG;
1799                                                 arg->inst_left = load;
1800                                                 arg->inst_call = call;
1801                                                 arg->backend.reg3 =  ainfo->pair_regs [0];
1802                                         }
1803                                         else {
1804                                                 /* Inserted after the copy.  Load the address of the temp on the stack.*/
1805                                                 arg->opcode = OP_OUTARG_VT;
1806                                                 arg->inst_left = load;
1807                                                 arg->type = STACK_PTR;
1808                                                 arg->klass = mono_defaults.int_class;
1809                                                 arg->backend.is_pinvoke = sig->pinvoke;
1810                                                 arg->inst_imm = size;
1811                                         }
1812
1813                                         /*Copy the argument to the temp variable.*/
1814                                         MONO_INST_NEW (cfg, load, OP_MEMCPY);
1815                                         load->backend.memcpy_args = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoMemcpyArgs));
1816                                         load->backend.memcpy_args->size = size;
1817                                         load->backend.memcpy_args->align = align;
1818                                         load->inst_left = (cfg)->varinfo [vtaddr->inst_c0];
1819                                         load->inst_right = in->inst_i0;
1820
1821                                         // FIXME:
1822                                         g_assert_not_reached ();
1823                                         //MONO_INST_LIST_ADD (&load->node, &call->out_args);
1824                                 }
1825                                 else {
1826                                         arg->opcode = OP_OUTARG_VT;
1827                                         arg->klass = in->klass;
1828                                         arg->backend.is_pinvoke = sig->pinvoke;
1829                                         arg->inst_imm = size;
1830                                 }
1831                         }
1832                         else {
1833                                 switch (ainfo->storage) {
1834                                 case ArgInIReg:
1835                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1836                                         break;
1837                                 case ArgInFloatSSEReg:
1838                                 case ArgInDoubleSSEReg:
1839                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1840                                         break;
1841                                 case ArgOnStack:
1842                                         arg->opcode = OP_OUTARG;
1843                                         if (!sig->params [i - sig->hasthis]->byref) {
1844                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1845                                                         arg->opcode = OP_OUTARG_R4;
1846                                                 else
1847                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1848                                                                 arg->opcode = OP_OUTARG_R8;
1849                                         }
1850                                         break;
1851                                 default:
1852                                         g_assert_not_reached ();
1853                                 }
1854                         }
1855                 }
1856         }
1857
1858         /* Handle the case where there are no implicit arguments */
1859         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1860                 emit_sig_cookie (cfg, call, cinfo);
1861         }
1862
1863         if (cinfo->ret.storage == ArgValuetypeInReg) {
1864                 /* This is needed by mono_arch_emit_this_vret_args () */
1865                 if (!cfg->arch.vret_addr_loc) {
1866                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1867                         /* Prevent it from being register allocated or optimized away */
1868                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1869                 }
1870         }
1871
1872         if (cinfo->need_stack_align) {
1873                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1874                 arg->inst_c0 = 8;
1875                 /* prepend, so they get reversed */
1876                 arg->next = call->out_args;
1877                 call->out_args = arg;
1878         }
1879
1880 #ifdef PLATFORM_WIN32
1881         /* Always reserve 32 bytes of stack space on Win64 */
1882         /*MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1883         arg->inst_c0 = 32;
1884         MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);*/
1885         NOT_IMPLEMENTED;
1886 #endif
1887
1888 #if 0
1889         if (cfg->method->save_lmf) {
1890                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1891                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1892         }
1893 #endif
1894
1895         call->stack_usage = cinfo->stack_usage;
1896         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1897         cfg->flags |= MONO_CFG_HAS_CALLS;
1898
1899         return call;
1900 }
1901
1902 static void
1903 emit_sig_cookie2 (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1904 {
1905         MonoInst *arg;
1906         MonoMethodSignature *tmp_sig;
1907         MonoInst *sig_arg;
1908
1909         if (call->tail_call)
1910                 NOT_IMPLEMENTED;
1911
1912         /* FIXME: Add support for signature tokens to AOT */
1913         cfg->disable_aot = TRUE;
1914
1915         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1916
1917         /*
1918          * mono_ArgIterator_Setup assumes the signature cookie is
1919          * passed first and all the arguments which were before it are
1920          * passed on the stack after the signature. So compensate by
1921          * passing a different signature.
1922          */
1923         tmp_sig = mono_metadata_signature_dup (call->signature);
1924         tmp_sig->param_count -= call->signature->sentinelpos;
1925         tmp_sig->sentinelpos = 0;
1926         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1927
1928         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1929         sig_arg->dreg = mono_alloc_ireg (cfg);
1930         sig_arg->inst_p0 = tmp_sig;
1931         MONO_ADD_INS (cfg->cbb, sig_arg);
1932
1933         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1934         arg->sreg1 = sig_arg->dreg;
1935         MONO_ADD_INS (cfg->cbb, arg);
1936 }
1937
1938 void
1939 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1940 {
1941         MonoInst *arg, *in;
1942         MonoMethodSignature *sig;
1943         int i, n, stack_size;
1944         CallInfo *cinfo;
1945         ArgInfo *ainfo;
1946
1947         stack_size = 0;
1948
1949         sig = call->signature;
1950         n = sig->param_count + sig->hasthis;
1951
1952         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1953
1954         if (cinfo->need_stack_align) {
1955                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1956         }
1957
1958         /*
1959          * Emit all parameters passed in registers in non-reverse order for better readability
1960          * and to help the optimization in emit_prolog ().
1961          */
1962         for (i = 0; i < n; ++i) {
1963                 ainfo = cinfo->args + i;
1964
1965                 in = call->args [i];
1966
1967                 if (ainfo->storage == ArgInIReg)
1968                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1969         }
1970
1971         for (i = n - 1; i >= 0; --i) {
1972                 ainfo = cinfo->args + i;
1973
1974                 in = call->args [i];
1975
1976                 switch (ainfo->storage) {
1977                 case ArgInIReg:
1978                         /* Already done */
1979                         break;
1980                 case ArgInFloatSSEReg:
1981                 case ArgInDoubleSSEReg:
1982                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1983                         break;
1984                 case ArgOnStack:
1985                 case ArgValuetypeInReg:
1986                 case ArgValuetypeAddrInIReg:
1987                         if (ainfo->storage == ArgOnStack && call->tail_call)
1988                                 NOT_IMPLEMENTED;
1989                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1990                                 guint32 align;
1991                                 guint32 size;
1992
1993                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1994                                         size = sizeof (MonoTypedRef);
1995                                         align = sizeof (gpointer);
1996                                 }
1997                                 else {
1998                                         if (sig->pinvoke)
1999                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2000                                         else {
2001                                                 /*
2002                                                  * Other backends use mono_type_stack_size (), but that
2003                                                  * aligns the size to 8, which is larger than the size of
2004                                                  * the source, leading to reads of invalid memory if the
2005                                                  * source is at the end of address space.
2006                                                  */
2007                                                 size = mono_class_value_size (in->klass, &align);
2008                                         }
2009                                 }
2010                                 g_assert (in->klass);
2011
2012                                 if (size > 0) {
2013                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2014                                         arg->sreg1 = in->dreg;
2015                                         arg->klass = in->klass;
2016                                         arg->backend.size = size;
2017                                         arg->inst_p0 = call;
2018                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2019                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2020
2021                                         MONO_ADD_INS (cfg->cbb, arg);
2022                                 }
2023                         } else {
2024                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2025                                 arg->sreg1 = in->dreg;
2026                                 if (!sig->params [i - sig->hasthis]->byref) {
2027                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2028                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2029                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
2030                                                 arg->inst_destbasereg = X86_ESP;
2031                                                 arg->inst_offset = 0;
2032                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2033                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2034                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
2035                                                 arg->inst_destbasereg = X86_ESP;
2036                                                 arg->inst_offset = 0;
2037                                         }
2038                                 }
2039                                 MONO_ADD_INS (cfg->cbb, arg);
2040                         }
2041                         break;
2042                 default:
2043                         g_assert_not_reached ();
2044                 }
2045
2046                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2047                         /* Emit the signature cookie just before the implicit arguments */
2048                         emit_sig_cookie2 (cfg, call, cinfo);
2049                 }
2050         }
2051
2052         /* Handle the case where there are no implicit arguments */
2053         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
2054                 emit_sig_cookie2 (cfg, call, cinfo);
2055         }
2056
2057         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2058                 MonoInst *vtarg;
2059
2060                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2061                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2062                                 /*
2063                                  * Tell the JIT to use a more efficient calling convention: call using
2064                                  * OP_CALL, compute the result location after the call, and save the
2065                                  * result there.
2066                                  */
2067                                 call->vret_in_reg = TRUE;
2068                                 /*
2069                                  * Nullify the instruction computing the vret addr to enable
2070                                  * future optimizations.
2071                                  */
2072                                 if (call->vret_var)
2073                                         NULLIFY_INS (call->vret_var);
2074                         } else {
2075                                 if (call->tail_call)
2076                                         NOT_IMPLEMENTED;
2077                                 /*
2078                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2079                                  * the stack. Push the address here, so the call instruction can
2080                                  * access it.
2081                                  */
2082                                 if (!cfg->arch.vret_addr_loc) {
2083                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2084                                         /* Prevent it from being register allocated or optimized away */
2085                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2086                                 }
2087
2088                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2089                         }
2090                 }
2091                 else {
2092                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2093                         vtarg->sreg1 = call->vret_var->dreg;
2094                         vtarg->dreg = mono_alloc_preg (cfg);
2095                         MONO_ADD_INS (cfg->cbb, vtarg);
2096
2097                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2098                 }
2099         }
2100
2101 #ifdef PLATFORM_WIN32
2102         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2103                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2104         }
2105 #endif
2106
2107         if (cfg->method->save_lmf) {
2108                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2109                 MONO_ADD_INS (cfg->cbb, arg);
2110         }
2111
2112         call->stack_usage = cinfo->stack_usage;
2113 }
2114
2115 void
2116 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2117 {
2118         MonoInst *arg;
2119         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2120         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2121         int size = ins->backend.size;
2122
2123         if (ainfo->storage == ArgValuetypeInReg) {
2124                 MonoInst *load;
2125                 int part;
2126
2127                 for (part = 0; part < 2; ++part) {
2128                         if (ainfo->pair_storage [part] == ArgNone)
2129                                 continue;
2130
2131                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2132                         load->inst_basereg = src->dreg;
2133                         load->inst_offset = part * sizeof (gpointer);
2134
2135                         switch (ainfo->pair_storage [part]) {
2136                         case ArgInIReg:
2137                                 load->dreg = mono_alloc_ireg (cfg);
2138                                 break;
2139                         case ArgInDoubleSSEReg:
2140                         case ArgInFloatSSEReg:
2141                                 load->dreg = mono_alloc_freg (cfg);
2142                                 break;
2143                         default:
2144                                 g_assert_not_reached ();
2145                         }
2146                         MONO_ADD_INS (cfg->cbb, load);
2147
2148                         add_outarg_reg2 (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2149                 }
2150         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2151                 MonoInst *vtaddr, *load;
2152                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2153
2154                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2155                 load->inst_p0 = vtaddr;
2156                 vtaddr->flags |= MONO_INST_INDIRECT;
2157                 load->type = STACK_MP;
2158                 load->klass = vtaddr->klass;
2159                 load->dreg = mono_alloc_ireg (cfg);
2160                 MONO_ADD_INS (cfg->cbb, load);
2161                 mini_emit_memcpy2 (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2162
2163                 if (ainfo->pair_storage [0] == ArgInIReg) {
2164                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2165                         arg->dreg = ainfo->pair_regs [0];
2166                         arg->sreg1 = load->dreg;
2167                         arg->inst_imm = 0;
2168                         MONO_ADD_INS (cfg->cbb, arg);
2169                 } else {
2170                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2171                         arg->sreg1 = load->dreg;
2172                         MONO_ADD_INS (cfg->cbb, arg);
2173                 }
2174         } else {
2175                 if (size == 8) {
2176                         /* Can't use this for < 8 since it does an 8 byte memory load */
2177                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2178                         arg->inst_basereg = src->dreg;
2179                         arg->inst_offset = 0;
2180                         MONO_ADD_INS (cfg->cbb, arg);
2181                 } else if (size <= 40) {
2182                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2183                         mini_emit_memcpy2 (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2184                 } else {
2185                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2186                         arg->inst_basereg = src->dreg;
2187                         arg->inst_offset = 0;
2188                         arg->inst_imm = size;
2189                         MONO_ADD_INS (cfg->cbb, arg);
2190                 }
2191         }
2192 }
2193
2194 void
2195 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2196 {
2197         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2198
2199         if (!ret->byref) {
2200                 if (ret->type == MONO_TYPE_R4) {
2201                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2202                         return;
2203                 } else if (ret->type == MONO_TYPE_R8) {
2204                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2205                         return;
2206                 }
2207         }
2208
2209         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2210 }
2211
2212 #define EMIT_COND_BRANCH(ins,cond,sign) \
2213 if (ins->flags & MONO_INST_BRLABEL) { \
2214         if (ins->inst_i0->inst_c0) { \
2215                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
2216         } else { \
2217                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
2218                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2219                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
2220                         x86_branch8 (code, cond, 0, sign); \
2221                 else \
2222                         x86_branch32 (code, cond, 0, sign); \
2223         } \
2224 } else { \
2225         if (ins->inst_true_bb->native_offset) { \
2226                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2227         } else { \
2228                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2229                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2230                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
2231                         x86_branch8 (code, cond, 0, sign); \
2232                 else \
2233                         x86_branch32 (code, cond, 0, sign); \
2234         } \
2235 }
2236
2237 /* emit an exception if condition is fail */
2238 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2239         do {                                                        \
2240                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2241                 if (tins == NULL) {                                                                             \
2242                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2243                                         MONO_PATCH_INFO_EXC, exc_name);  \
2244                         x86_branch32 (code, cond, 0, signed);               \
2245                 } else {        \
2246                         EMIT_COND_BRANCH (tins, cond, signed);  \
2247                 }                       \
2248         } while (0);
2249
2250 #define EMIT_FPCOMPARE(code) do { \
2251         amd64_fcompp (code); \
2252         amd64_fnstsw (code); \
2253 } while (0);
2254
2255 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2256     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2257         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2258         amd64_ ##op (code); \
2259         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2260         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2261 } while (0);
2262
2263 static guint8*
2264 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2265 {
2266         gboolean no_patch = FALSE;
2267
2268         /*
2269          * FIXME: Add support for thunks
2270          */
2271         {
2272                 gboolean near_call = FALSE;
2273
2274                 /*
2275                  * Indirect calls are expensive so try to make a near call if possible.
2276                  * The caller memory is allocated by the code manager so it is
2277                  * guaranteed to be at a 32 bit offset.
2278                  */
2279
2280                 if (patch_type != MONO_PATCH_INFO_ABS) {
2281                         /* The target is in memory allocated using the code manager */
2282                         near_call = TRUE;
2283
2284                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2285                                 if (((MonoMethod*)data)->klass->image->aot_module)
2286                                         /* The callee might be an AOT method */
2287                                         near_call = FALSE;
2288                                 if (((MonoMethod*)data)->dynamic)
2289                                         /* The target is in malloc-ed memory */
2290                                         near_call = FALSE;
2291                         }
2292
2293                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2294                                 /*
2295                                  * The call might go directly to a native function without
2296                                  * the wrapper.
2297                                  */
2298                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2299                                 if (mi) {
2300                                         gconstpointer target = mono_icall_get_wrapper (mi);
2301                                         if ((((guint64)target) >> 32) != 0)
2302                                                 near_call = FALSE;
2303                                 }
2304                         }
2305                 }
2306                 else {
2307                         if (!cfg->new_ir && mono_find_class_init_trampoline_by_addr (data))
2308                                 near_call = TRUE;
2309                         else if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2310                                 /*
2311                                  * This is not really an optimization, but required because the
2312                                  * generic class init trampolines use R11 to pass the vtable.
2313                                  */
2314                                 near_call = TRUE;
2315                         } else {
2316                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2317                                 if (info) {
2318                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2319                                                 strstr (cfg->method->name, info->name)) {
2320                                                 /* A call to the wrapped function */
2321                                                 if ((((guint64)data) >> 32) == 0)
2322                                                         near_call = TRUE;
2323                                                 no_patch = TRUE;
2324                                         }
2325                                         else if (info->func == info->wrapper) {
2326                                                 /* No wrapper */
2327                                                 if ((((guint64)info->func) >> 32) == 0)
2328                                                         near_call = TRUE;
2329                                         }
2330                                         else {
2331                                                 /* See the comment in mono_codegen () */
2332                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2333                                                         near_call = TRUE;
2334                                         }
2335                                 }
2336                                 else if ((((guint64)data) >> 32) == 0) {
2337                                         near_call = TRUE;
2338                                         no_patch = TRUE;
2339                                 }
2340                         }
2341                 }
2342
2343                 if (cfg->method->dynamic)
2344                         /* These methods are allocated using malloc */
2345                         near_call = FALSE;
2346
2347                 if (cfg->compile_aot)
2348                         near_call = TRUE;
2349
2350 #ifdef MONO_ARCH_NOMAP32BIT
2351                 near_call = FALSE;
2352 #endif
2353
2354                 if (near_call) {
2355                         /*
2356                          * Align the call displacement to an address divisible by 4 so it does
2357                          * not span cache lines. This is required for code patching to work on SMP
2358                          * systems.
2359                          */
2360                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2361                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2362                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2363                         amd64_call_code (code, 0);
2364                 }
2365                 else {
2366                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2367                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2368                         amd64_call_reg (code, GP_SCRATCH_REG);
2369                 }
2370         }
2371
2372         return code;
2373 }
2374
2375 static inline guint8*
2376 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2377 {
2378 #ifdef PLATFORM_WIN32
2379         if (win64_adjust_stack)
2380                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2381 #endif
2382         code = emit_call_body (cfg, code, patch_type, data);
2383 #ifdef PLATFORM_WIN32
2384         if (win64_adjust_stack)
2385                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2386 #endif
2387
2388         return code;
2389 }
2390
2391 static inline int
2392 store_membase_imm_to_store_membase_reg (int opcode)
2393 {
2394         switch (opcode) {
2395         case OP_STORE_MEMBASE_IMM:
2396                 return OP_STORE_MEMBASE_REG;
2397         case OP_STOREI4_MEMBASE_IMM:
2398                 return OP_STOREI4_MEMBASE_REG;
2399         case OP_STOREI8_MEMBASE_IMM:
2400                 return OP_STOREI8_MEMBASE_REG;
2401         }
2402
2403         return -1;
2404 }
2405
2406 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2407
2408 /*
2409  * mono_arch_peephole_pass_1:
2410  *
2411  *   Perform peephole opts which should/can be performed before local regalloc
2412  */
2413 void
2414 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2415 {
2416         MonoInst *ins, *n;
2417
2418         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2419                 MonoInst *last_ins = ins->prev;
2420
2421                 switch (ins->opcode) {
2422                 case OP_ADD_IMM:
2423                 case OP_IADD_IMM:
2424                 case OP_LADD_IMM:
2425                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2426                                 /*
2427                                  * X86_LEA is like ADD, but doesn't have the
2428                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2429                                  * its operand to 64 bit.
2430                                  */
2431                                 ins->opcode = OP_X86_LEA_MEMBASE;
2432                                 ins->inst_basereg = ins->sreg1;
2433                         }
2434                         break;
2435                 case OP_LXOR:
2436                 case OP_IXOR:
2437                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2438                                 MonoInst *ins2;
2439
2440                                 /*
2441                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2442                                  * the latter has length 2-3 instead of 6 (reverse constant
2443                                  * propagation). These instruction sequences are very common
2444                                  * in the initlocals bblock.
2445                                  */
2446                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2447                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2448                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2449                                                 ins2->sreg1 = ins->dreg;
2450                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2451                                                 /* Continue */
2452                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2453                                                 NULLIFY_INS (ins2);
2454                                                 /* Continue */
2455                                         } else {
2456                                                 break;
2457                                         }
2458                                 }
2459                         }
2460                         break;
2461                 case OP_COMPARE_IMM:
2462                 case OP_LCOMPARE_IMM:
2463                         /* OP_COMPARE_IMM (reg, 0)
2464                          * -->
2465                          * OP_AMD64_TEST_NULL (reg)
2466                          */
2467                         if (!ins->inst_imm)
2468                                 ins->opcode = OP_AMD64_TEST_NULL;
2469                         break;
2470                 case OP_ICOMPARE_IMM:
2471                         if (!ins->inst_imm)
2472                                 ins->opcode = OP_X86_TEST_NULL;
2473                         break;
2474                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2475                         /*
2476                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2477                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2478                          * -->
2479                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2480                          * OP_COMPARE_IMM reg, imm
2481                          *
2482                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2483                          */
2484                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2485                             ins->inst_basereg == last_ins->inst_destbasereg &&
2486                             ins->inst_offset == last_ins->inst_offset) {
2487                                         ins->opcode = OP_ICOMPARE_IMM;
2488                                         ins->sreg1 = last_ins->sreg1;
2489
2490                                         /* check if we can remove cmp reg,0 with test null */
2491                                         if (!ins->inst_imm)
2492                                                 ins->opcode = OP_X86_TEST_NULL;
2493                                 }
2494
2495                         break;
2496                 }
2497
2498                 mono_peephole_ins (bb, ins);
2499         }
2500 }
2501
2502 void
2503 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2504 {
2505         MonoInst *ins, *n;
2506
2507         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2508                 switch (ins->opcode) {
2509                 case OP_ICONST:
2510                 case OP_I8CONST: {
2511                         /* reg = 0 -> XOR (reg, reg) */
2512                         /* XOR sets cflags on x86, so we cant do it always */
2513                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2514                                 ins->opcode = OP_LXOR;
2515                                 ins->sreg1 = ins->dreg;
2516                                 ins->sreg2 = ins->dreg;
2517                                 /* Fall through */
2518                         } else {
2519                                 break;
2520                         }
2521                 }
2522                 case OP_LXOR:
2523                         /*
2524                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2525                          * 0 result into 64 bits.
2526                          */
2527                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2528                                 ins->opcode = OP_IXOR;
2529                         }
2530                         /* Fall through */
2531                 case OP_IXOR:
2532                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2533                                 MonoInst *ins2;
2534
2535                                 /*
2536                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2537                                  * the latter has length 2-3 instead of 6 (reverse constant
2538                                  * propagation). These instruction sequences are very common
2539                                  * in the initlocals bblock.
2540                                  */
2541                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2542                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2543                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2544                                                 ins2->sreg1 = ins->dreg;
2545                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2546                                                 /* Continue */
2547                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2548                                                 NULLIFY_INS (ins2);
2549                                                 /* Continue */
2550                                         } else {
2551                                                 break;
2552                                         }
2553                                 }
2554                         }
2555                         break;
2556                 case OP_IADD_IMM:
2557                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2558                                 ins->opcode = OP_X86_INC_REG;
2559                         break;
2560                 case OP_ISUB_IMM:
2561                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2562                                 ins->opcode = OP_X86_DEC_REG;
2563                         break;
2564                 }
2565
2566                 mono_peephole_ins (bb, ins);
2567         }
2568 }
2569
2570 #define NEW_INS(cfg,ins,dest,op) do {   \
2571                 MONO_INST_NEW ((cfg), (dest), (op)); \
2572         (dest)->cil_code = (ins)->cil_code; \
2573         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2574         } while (0)
2575
2576 /*
2577  * mono_arch_lowering_pass:
2578  *
2579  *  Converts complex opcodes into simpler ones so that each IR instruction
2580  * corresponds to one machine instruction.
2581  */
2582 void
2583 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2584 {
2585         MonoInst *ins, *n, *temp;
2586
2587         if (bb->max_vreg > cfg->rs->next_vreg)
2588                 cfg->rs->next_vreg = bb->max_vreg;
2589
2590         /*
2591          * FIXME: Need to add more instructions, but the current machine
2592          * description can't model some parts of the composite instructions like
2593          * cdq.
2594          */
2595         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2596                 switch (ins->opcode) {
2597                 case OP_DIV_IMM:
2598                 case OP_REM_IMM:
2599                 case OP_IDIV_IMM:
2600                 case OP_IREM_IMM:
2601                 case OP_IDIV_UN_IMM:
2602                 case OP_IREM_UN_IMM:
2603                         mono_decompose_op_imm (cfg, bb, ins);
2604                         break;
2605                 case OP_COMPARE_IMM:
2606                 case OP_LCOMPARE_IMM:
2607                         if (!amd64_is_imm32 (ins->inst_imm)) {
2608                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2609                                 temp->inst_c0 = ins->inst_imm;
2610                                 if (cfg->globalra)
2611                                         temp->dreg = mono_alloc_ireg (cfg);
2612                                 else
2613                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2614                                 ins->opcode = OP_COMPARE;
2615                                 ins->sreg2 = temp->dreg;
2616                         }
2617                         break;
2618                 case OP_LOAD_MEMBASE:
2619                 case OP_LOADI8_MEMBASE:
2620                         if (!amd64_is_imm32 (ins->inst_offset)) {
2621                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2622                                 temp->inst_c0 = ins->inst_offset;
2623                                 if (cfg->globalra)
2624                                         temp->dreg = mono_alloc_ireg (cfg);
2625                                 else
2626                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2627                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2628                                 ins->inst_indexreg = temp->dreg;
2629                         }
2630                         break;
2631                 case OP_STORE_MEMBASE_IMM:
2632                 case OP_STOREI8_MEMBASE_IMM:
2633                         if (!amd64_is_imm32 (ins->inst_imm)) {
2634                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2635                                 temp->inst_c0 = ins->inst_imm;
2636                                 if (cfg->globalra)
2637                                         temp->dreg = mono_alloc_ireg (cfg);
2638                                 else
2639                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2640                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2641                                 ins->sreg1 = temp->dreg;
2642                         }
2643                         break;
2644                 default:
2645                         break;
2646                 }
2647         }
2648
2649         bb->max_vreg = cfg->rs->next_vreg;
2650 }
2651
2652 static const int
2653 branch_cc_table [] = {
2654         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2655         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2656         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2657 };
2658
2659 /* Maps CMP_... constants to X86_CC_... constants */
2660 static const int
2661 cc_table [] = {
2662         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2663         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2664 };
2665
2666 static const int
2667 cc_signed_table [] = {
2668         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2669         FALSE, FALSE, FALSE, FALSE
2670 };
2671
2672 /*#include "cprop.c"*/
2673
2674 static unsigned char*
2675 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2676 {
2677         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2678
2679         if (size == 1)
2680                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2681         else if (size == 2)
2682                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2683         return code;
2684 }
2685
2686 static unsigned char*
2687 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2688 {
2689         int sreg = tree->sreg1;
2690         int need_touch = FALSE;
2691
2692 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2693         if (!tree->flags & MONO_INST_INIT)
2694                 need_touch = TRUE;
2695 #endif
2696
2697         if (need_touch) {
2698                 guint8* br[5];
2699
2700                 /*
2701                  * Under Windows:
2702                  * If requested stack size is larger than one page,
2703                  * perform stack-touch operation
2704                  */
2705                 /*
2706                  * Generate stack probe code.
2707                  * Under Windows, it is necessary to allocate one page at a time,
2708                  * "touching" stack after each successful sub-allocation. This is
2709                  * because of the way stack growth is implemented - there is a
2710                  * guard page before the lowest stack page that is currently commited.
2711                  * Stack normally grows sequentially so OS traps access to the
2712                  * guard page and commits more pages when needed.
2713                  */
2714                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2715                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2716
2717                 br[2] = code; /* loop */
2718                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2719                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2720                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2721                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2722                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2723                 amd64_patch (br[3], br[2]);
2724                 amd64_test_reg_reg (code, sreg, sreg);
2725                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2726                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2727
2728                 br[1] = code; x86_jump8 (code, 0);
2729
2730                 amd64_patch (br[0], code);
2731                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2732                 amd64_patch (br[1], code);
2733                 amd64_patch (br[4], code);
2734         }
2735         else
2736                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2737
2738         if (tree->flags & MONO_INST_INIT) {
2739                 int offset = 0;
2740                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2741                         amd64_push_reg (code, AMD64_RAX);
2742                         offset += 8;
2743                 }
2744                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2745                         amd64_push_reg (code, AMD64_RCX);
2746                         offset += 8;
2747                 }
2748                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2749                         amd64_push_reg (code, AMD64_RDI);
2750                         offset += 8;
2751                 }
2752
2753                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2754                 if (sreg != AMD64_RCX)
2755                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2756                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2757
2758                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2759                 amd64_cld (code);
2760                 amd64_prefix (code, X86_REP_PREFIX);
2761                 amd64_stosl (code);
2762
2763                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2764                         amd64_pop_reg (code, AMD64_RDI);
2765                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2766                         amd64_pop_reg (code, AMD64_RCX);
2767                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2768                         amd64_pop_reg (code, AMD64_RAX);
2769         }
2770         return code;
2771 }
2772
2773 static guint8*
2774 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2775 {
2776         CallInfo *cinfo;
2777         guint32 quad;
2778
2779         /* Move return value to the target register */
2780         /* FIXME: do this in the local reg allocator */
2781         switch (ins->opcode) {
2782         case OP_CALL:
2783         case OP_CALL_REG:
2784         case OP_CALL_MEMBASE:
2785         case OP_LCALL:
2786         case OP_LCALL_REG:
2787         case OP_LCALL_MEMBASE:
2788                 g_assert (ins->dreg == AMD64_RAX);
2789                 break;
2790         case OP_FCALL:
2791         case OP_FCALL_REG:
2792         case OP_FCALL_MEMBASE:
2793                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2794                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2795                 }
2796                 else {
2797                         if (ins->dreg != AMD64_XMM0)
2798                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2799                 }
2800                 break;
2801         case OP_VCALL:
2802         case OP_VCALL_REG:
2803         case OP_VCALL_MEMBASE:
2804         case OP_VCALL2:
2805         case OP_VCALL2_REG:
2806         case OP_VCALL2_MEMBASE:
2807                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2808                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2809                         MonoInst *loc = cfg->arch.vret_addr_loc;
2810
2811                         /* Load the destination address */
2812                         g_assert (loc->opcode == OP_REGOFFSET);
2813                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2814
2815                         for (quad = 0; quad < 2; quad ++) {
2816                                 switch (cinfo->ret.pair_storage [quad]) {
2817                                 case ArgInIReg:
2818                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2819                                         break;
2820                                 case ArgInFloatSSEReg:
2821                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2822                                         break;
2823                                 case ArgInDoubleSSEReg:
2824                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2825                                         break;
2826                                 case ArgNone:
2827                                         break;
2828                                 default:
2829                                         NOT_IMPLEMENTED;
2830                                 }
2831                         }
2832                 }
2833                 break;
2834         }
2835
2836         return code;
2837 }
2838
2839 /*
2840  * emit_tls_get:
2841  * @code: buffer to store code to
2842  * @dreg: hard register where to place the result
2843  * @tls_offset: offset info
2844  *
2845  * emit_tls_get emits in @code the native code that puts in the dreg register
2846  * the item in the thread local storage identified by tls_offset.
2847  *
2848  * Returns: a pointer to the end of the stored code
2849  */
2850 static guint8*
2851 emit_tls_get (guint8* code, int dreg, int tls_offset)
2852 {
2853 #ifdef PLATFORM_WIN32
2854         g_assert (tls_offset < 64);
2855         x86_prefix (code, X86_GS_PREFIX);
2856         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2857 #else
2858         if (optimize_for_xen) {
2859                 x86_prefix (code, X86_FS_PREFIX);
2860                 amd64_mov_reg_mem (code, dreg, 0, 8);
2861                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2862         } else {
2863                 x86_prefix (code, X86_FS_PREFIX);
2864                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2865         }
2866 #endif
2867         return code;
2868 }
2869
2870 /*
2871  * emit_load_volatile_arguments:
2872  *
2873  *  Load volatile arguments from the stack to the original input registers.
2874  * Required before a tail call.
2875  */
2876 static guint8*
2877 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2878 {
2879         MonoMethod *method = cfg->method;
2880         MonoMethodSignature *sig;
2881         MonoInst *ins;
2882         CallInfo *cinfo;
2883         guint32 i, quad;
2884
2885         /* FIXME: Generate intermediate code instead */
2886
2887         sig = mono_method_signature (method);
2888
2889         cinfo = cfg->arch.cinfo;
2890
2891         /* This is the opposite of the code in emit_prolog */
2892         if (sig->ret->type != MONO_TYPE_VOID) {
2893                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2894                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2895         }
2896
2897         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2898                 ArgInfo *ainfo = cinfo->args + i;
2899                 MonoType *arg_type;
2900                 ins = cfg->args [i];
2901
2902                 if (sig->hasthis && (i == 0))
2903                         arg_type = &mono_defaults.object_class->byval_arg;
2904                 else
2905                         arg_type = sig->params [i - sig->hasthis];
2906
2907                 if (ins->opcode != OP_REGVAR) {
2908                         switch (ainfo->storage) {
2909                         case ArgInIReg: {
2910                                 guint32 size = 8;
2911
2912                                 /* FIXME: I1 etc */
2913                                 amd64_mov_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset, size);
2914                                 break;
2915                         }
2916                         case ArgInFloatSSEReg:
2917                                 amd64_movss_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2918                                 break;
2919                         case ArgInDoubleSSEReg:
2920                                 amd64_movsd_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2921                                 break;
2922                         case ArgValuetypeInReg:
2923                                 for (quad = 0; quad < 2; quad ++) {
2924                                         switch (ainfo->pair_storage [quad]) {
2925                                         case ArgInIReg:
2926                                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
2927                                                 break;
2928                                         case ArgInFloatSSEReg:
2929                                         case ArgInDoubleSSEReg:
2930                                                 g_assert_not_reached ();
2931                                                 break;
2932                                         case ArgNone:
2933                                                 break;
2934                                         default:
2935                                                 g_assert_not_reached ();
2936                                         }
2937                                 }
2938                                 break;
2939                         case ArgValuetypeAddrInIReg:
2940                                 if (ainfo->pair_storage [0] == ArgInIReg)
2941                                         amd64_mov_reg_membase (code, ainfo->pair_regs [0], ins->inst_left->inst_basereg, ins->inst_left->inst_offset,  sizeof (gpointer));
2942                                 break;
2943                         default:
2944                                 break;
2945                         }
2946                 }
2947                 else {
2948                         g_assert (ainfo->storage == ArgInIReg);
2949
2950                         amd64_mov_reg_reg (code, ainfo->reg, ins->dreg, 8);
2951                 }
2952         }
2953
2954         return code;
2955 }
2956
2957 #define REAL_PRINT_REG(text,reg) \
2958 mono_assert (reg >= 0); \
2959 amd64_push_reg (code, AMD64_RAX); \
2960 amd64_push_reg (code, AMD64_RDX); \
2961 amd64_push_reg (code, AMD64_RCX); \
2962 amd64_push_reg (code, reg); \
2963 amd64_push_imm (code, reg); \
2964 amd64_push_imm (code, text " %d %p\n"); \
2965 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2966 amd64_call_reg (code, AMD64_RAX); \
2967 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2968 amd64_pop_reg (code, AMD64_RCX); \
2969 amd64_pop_reg (code, AMD64_RDX); \
2970 amd64_pop_reg (code, AMD64_RAX);
2971
2972 /* benchmark and set based on cpu */
2973 #define LOOP_ALIGNMENT 8
2974 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2975
2976 void
2977 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2978 {
2979         MonoInst *ins;
2980         MonoCallInst *call;
2981         guint offset;
2982         guint8 *code = cfg->native_code + cfg->code_len;
2983         MonoInst *last_ins = NULL;
2984         guint last_offset = 0;
2985         int max_len, cpos;
2986
2987         if (cfg->opt & MONO_OPT_LOOP) {
2988                 int pad, align = LOOP_ALIGNMENT;
2989                 /* set alignment depending on cpu */
2990                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2991                         pad = align - pad;
2992                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2993                         amd64_padding (code, pad);
2994                         cfg->code_len += pad;
2995                         bb->native_offset = cfg->code_len;
2996                 }
2997         }
2998
2999         if (cfg->verbose_level > 2)
3000                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3001
3002         cpos = bb->max_offset;
3003
3004         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3005                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3006                 g_assert (!cfg->compile_aot);
3007                 cpos += 6;
3008
3009                 cov->data [bb->dfn].cil_code = bb->cil_code;
3010                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3011                 /* this is not thread save, but good enough */
3012                 amd64_inc_membase (code, AMD64_R11, 0);
3013         }
3014
3015         offset = code - cfg->native_code;
3016
3017         mono_debug_open_block (cfg, bb, offset);
3018
3019         MONO_BB_FOR_EACH_INS (bb, ins) {
3020                 offset = code - cfg->native_code;
3021
3022                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3023
3024                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3025                         cfg->code_size *= 2;
3026                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3027                         code = cfg->native_code + offset;
3028                         mono_jit_stats.code_reallocs++;
3029                 }
3030
3031                 if (cfg->debug_info)
3032                         mono_debug_record_line_number (cfg, ins, offset);
3033
3034                 switch (ins->opcode) {
3035                 case OP_BIGMUL:
3036                         amd64_mul_reg (code, ins->sreg2, TRUE);
3037                         break;
3038                 case OP_BIGMUL_UN:
3039                         amd64_mul_reg (code, ins->sreg2, FALSE);
3040                         break;
3041                 case OP_X86_SETEQ_MEMBASE:
3042                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3043                         break;
3044                 case OP_STOREI1_MEMBASE_IMM:
3045                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3046                         break;
3047                 case OP_STOREI2_MEMBASE_IMM:
3048                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3049                         break;
3050                 case OP_STOREI4_MEMBASE_IMM:
3051                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3052                         break;
3053                 case OP_STOREI1_MEMBASE_REG:
3054                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3055                         break;
3056                 case OP_STOREI2_MEMBASE_REG:
3057                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3058                         break;
3059                 case OP_STORE_MEMBASE_REG:
3060                 case OP_STOREI8_MEMBASE_REG:
3061                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3062                         break;
3063                 case OP_STOREI4_MEMBASE_REG:
3064                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3065                         break;
3066                 case OP_STORE_MEMBASE_IMM:
3067                 case OP_STOREI8_MEMBASE_IMM:
3068                         g_assert (amd64_is_imm32 (ins->inst_imm));
3069                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3070                         break;
3071                 case OP_LOAD_MEM:
3072                 case OP_LOADI8_MEM:
3073                         // FIXME: Decompose this earlier
3074                         if (amd64_is_imm32 (ins->inst_imm))
3075                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3076                         else {
3077                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3078                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3079                         }
3080                         break;
3081                 case OP_LOADI4_MEM:
3082                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3083                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3084                         break;
3085                 case OP_LOADU4_MEM:
3086                         // FIXME: Decompose this earlier
3087                         if (cfg->new_ir) {
3088                                 if (amd64_is_imm32 (ins->inst_imm))
3089                                         amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3090                                 else {
3091                                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3092                                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3093                                 }
3094                         } else {
3095                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
3096                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3097                         }
3098                         break;
3099                 case OP_LOADU1_MEM:
3100                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3101                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3102                         break;
3103                 case OP_LOADU2_MEM:
3104                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3105                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3106                         break;
3107                 case OP_LOAD_MEMBASE:
3108                 case OP_LOADI8_MEMBASE:
3109                         g_assert (amd64_is_imm32 (ins->inst_offset));
3110                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3111                         break;
3112                 case OP_LOADI4_MEMBASE:
3113                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3114                         break;
3115                 case OP_LOADU4_MEMBASE:
3116                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3117                         break;
3118                 case OP_LOADU1_MEMBASE:
3119                         /* The cpu zero extends the result into 64 bits */
3120                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3121                         break;
3122                 case OP_LOADI1_MEMBASE:
3123                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3124                         break;
3125                 case OP_LOADU2_MEMBASE:
3126                         /* The cpu zero extends the result into 64 bits */
3127                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3128                         break;
3129                 case OP_LOADI2_MEMBASE:
3130                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3131                         break;
3132                 case OP_AMD64_LOADI8_MEMINDEX:
3133                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3134                         break;
3135                 case OP_LCONV_TO_I1:
3136                 case OP_ICONV_TO_I1:
3137                 case OP_SEXT_I1:
3138                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3139                         break;
3140                 case OP_LCONV_TO_I2:
3141                 case OP_ICONV_TO_I2:
3142                 case OP_SEXT_I2:
3143                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3144                         break;
3145                 case OP_LCONV_TO_U1:
3146                 case OP_ICONV_TO_U1:
3147                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3148                         break;
3149                 case OP_LCONV_TO_U2:
3150                 case OP_ICONV_TO_U2:
3151                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3152                         break;
3153                 case OP_ZEXT_I4:
3154                         /* Clean out the upper word */
3155                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3156                         break;
3157                 case OP_SEXT_I4:
3158                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3159                         break;
3160                 case OP_COMPARE:
3161                 case OP_LCOMPARE:
3162                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3163                         break;
3164                 case OP_COMPARE_IMM:
3165                 case OP_LCOMPARE_IMM:
3166                         g_assert (amd64_is_imm32 (ins->inst_imm));
3167                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3168                         break;
3169                 case OP_X86_COMPARE_REG_MEMBASE:
3170                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3171                         break;
3172                 case OP_X86_TEST_NULL:
3173                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3174                         break;
3175                 case OP_AMD64_TEST_NULL:
3176                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3177                         break;
3178
3179                 case OP_X86_ADD_REG_MEMBASE:
3180                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3181                         break;
3182                 case OP_X86_SUB_REG_MEMBASE:
3183                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3184                         break;
3185                 case OP_X86_AND_REG_MEMBASE:
3186                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3187                         break;
3188                 case OP_X86_OR_REG_MEMBASE:
3189                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3190                         break;
3191                 case OP_X86_XOR_REG_MEMBASE:
3192                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3193                         break;
3194
3195                 case OP_X86_ADD_MEMBASE_IMM:
3196                         /* FIXME: Make a 64 version too */
3197                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3198                         break;
3199                 case OP_X86_SUB_MEMBASE_IMM:
3200                         g_assert (amd64_is_imm32 (ins->inst_imm));
3201                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3202                         break;
3203                 case OP_X86_AND_MEMBASE_IMM:
3204                         g_assert (amd64_is_imm32 (ins->inst_imm));
3205                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3206                         break;
3207                 case OP_X86_OR_MEMBASE_IMM:
3208                         g_assert (amd64_is_imm32 (ins->inst_imm));
3209                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3210                         break;
3211                 case OP_X86_XOR_MEMBASE_IMM:
3212                         g_assert (amd64_is_imm32 (ins->inst_imm));
3213                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3214                         break;
3215                 case OP_X86_ADD_MEMBASE_REG:
3216                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3217                         break;
3218                 case OP_X86_SUB_MEMBASE_REG:
3219                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3220                         break;
3221                 case OP_X86_AND_MEMBASE_REG:
3222                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3223                         break;
3224                 case OP_X86_OR_MEMBASE_REG:
3225                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3226                         break;
3227                 case OP_X86_XOR_MEMBASE_REG:
3228                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3229                         break;
3230                 case OP_X86_INC_MEMBASE:
3231                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3232                         break;
3233                 case OP_X86_INC_REG:
3234                         amd64_inc_reg_size (code, ins->dreg, 4);
3235                         break;
3236                 case OP_X86_DEC_MEMBASE:
3237                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3238                         break;
3239                 case OP_X86_DEC_REG:
3240                         amd64_dec_reg_size (code, ins->dreg, 4);
3241                         break;
3242                 case OP_X86_MUL_REG_MEMBASE:
3243                 case OP_X86_MUL_MEMBASE_REG:
3244                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3245                         break;
3246                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3247                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3248                         break;
3249                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3250                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3251                         break;
3252                 case OP_AMD64_COMPARE_MEMBASE_REG:
3253                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3254                         break;
3255                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3256                         g_assert (amd64_is_imm32 (ins->inst_imm));
3257                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3258                         break;
3259                 case OP_X86_COMPARE_MEMBASE8_IMM:
3260                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3261                         break;
3262                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3263                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3264                         break;
3265                 case OP_AMD64_COMPARE_REG_MEMBASE:
3266                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3267                         break;
3268
3269                 case OP_AMD64_ADD_REG_MEMBASE:
3270                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3271                         break;
3272                 case OP_AMD64_SUB_REG_MEMBASE:
3273                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3274                         break;
3275                 case OP_AMD64_AND_REG_MEMBASE:
3276                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3277                         break;
3278                 case OP_AMD64_OR_REG_MEMBASE:
3279                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3280                         break;
3281                 case OP_AMD64_XOR_REG_MEMBASE:
3282                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3283                         break;
3284
3285                 case OP_AMD64_ADD_MEMBASE_REG:
3286                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3287                         break;
3288                 case OP_AMD64_SUB_MEMBASE_REG:
3289                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3290                         break;
3291                 case OP_AMD64_AND_MEMBASE_REG:
3292                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3293                         break;
3294                 case OP_AMD64_OR_MEMBASE_REG:
3295                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3296                         break;
3297                 case OP_AMD64_XOR_MEMBASE_REG:
3298                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3299                         break;
3300
3301                 case OP_AMD64_ADD_MEMBASE_IMM:
3302                         g_assert (amd64_is_imm32 (ins->inst_imm));
3303                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3304                         break;
3305                 case OP_AMD64_SUB_MEMBASE_IMM:
3306                         g_assert (amd64_is_imm32 (ins->inst_imm));
3307                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3308                         break;
3309                 case OP_AMD64_AND_MEMBASE_IMM:
3310                         g_assert (amd64_is_imm32 (ins->inst_imm));
3311                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3312                         break;
3313                 case OP_AMD64_OR_MEMBASE_IMM:
3314                         g_assert (amd64_is_imm32 (ins->inst_imm));
3315                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3316                         break;
3317                 case OP_AMD64_XOR_MEMBASE_IMM:
3318                         g_assert (amd64_is_imm32 (ins->inst_imm));
3319                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3320                         break;
3321
3322                 case OP_BREAK:
3323                         amd64_breakpoint (code);
3324                         break;
3325                 case OP_NOP:
3326                 case OP_DUMMY_USE:
3327                 case OP_DUMMY_STORE:
3328                 case OP_NOT_REACHED:
3329                 case OP_NOT_NULL:
3330                         break;
3331                 case OP_ADDCC:
3332                 case OP_LADD:
3333                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3334                         break;
3335                 case OP_ADC:
3336                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3337                         break;
3338                 case OP_ADD_IMM:
3339                 case OP_LADD_IMM:
3340                         g_assert (amd64_is_imm32 (ins->inst_imm));
3341                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3342                         break;
3343                 case OP_ADC_IMM:
3344                         g_assert (amd64_is_imm32 (ins->inst_imm));
3345                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3346                         break;
3347                 case OP_SUBCC:
3348                 case OP_LSUB:
3349                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3350                         break;
3351                 case OP_SBB:
3352                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3353                         break;
3354                 case OP_SUB_IMM:
3355                 case OP_LSUB_IMM:
3356                         g_assert (amd64_is_imm32 (ins->inst_imm));
3357                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3358                         break;
3359                 case OP_SBB_IMM:
3360                         g_assert (amd64_is_imm32 (ins->inst_imm));
3361                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3362                         break;
3363                 case OP_LAND:
3364                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3365                         break;
3366                 case OP_AND_IMM:
3367                 case OP_LAND_IMM:
3368                         g_assert (amd64_is_imm32 (ins->inst_imm));
3369                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3370                         break;
3371                 case OP_LMUL:
3372                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3373                         break;
3374                 case OP_MUL_IMM:
3375                 case OP_LMUL_IMM:
3376                 case OP_IMUL_IMM: {
3377                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3378
3379                         switch (ins->inst_imm) {
3380                         case 2:
3381                                 /* MOV r1, r2 */
3382                                 /* ADD r1, r1 */
3383                                 if (ins->dreg != ins->sreg1)
3384                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3385                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3386                                 break;
3387                         case 3:
3388                                 /* LEA r1, [r2 + r2*2] */
3389                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3390                                 break;
3391                         case 5:
3392                                 /* LEA r1, [r2 + r2*4] */
3393                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3394                                 break;
3395                         case 6:
3396                                 /* LEA r1, [r2 + r2*2] */
3397                                 /* ADD r1, r1          */
3398                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3399                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3400                                 break;
3401                         case 9:
3402                                 /* LEA r1, [r2 + r2*8] */
3403                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3404                                 break;
3405                         case 10:
3406                                 /* LEA r1, [r2 + r2*4] */
3407                                 /* ADD r1, r1          */
3408                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3409                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3410                                 break;
3411                         case 12:
3412                                 /* LEA r1, [r2 + r2*2] */
3413                                 /* SHL r1, 2           */
3414                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3415                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3416                                 break;
3417                         case 25:
3418                                 /* LEA r1, [r2 + r2*4] */
3419                                 /* LEA r1, [r1 + r1*4] */
3420                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3421                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3422                                 break;
3423                         case 100:
3424                                 /* LEA r1, [r2 + r2*4] */
3425                                 /* SHL r1, 2           */
3426                                 /* LEA r1, [r1 + r1*4] */
3427                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3428                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3429                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3430                                 break;
3431                         default:
3432                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3433                                 break;
3434                         }
3435                         break;
3436                 }
3437                 case OP_LDIV:
3438                 case OP_LREM:
3439                         /* Regalloc magic makes the div/rem cases the same */
3440                         if (ins->sreg2 == AMD64_RDX) {
3441                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3442                                 amd64_cdq (code);
3443                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3444                         } else {
3445                                 amd64_cdq (code);
3446                                 amd64_div_reg (code, ins->sreg2, TRUE);
3447                         }
3448                         break;
3449                 case OP_LDIV_UN:
3450                 case OP_LREM_UN:
3451                         if (ins->sreg2 == AMD64_RDX) {
3452                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3453                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3454                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3455                         } else {
3456                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3457                                 amd64_div_reg (code, ins->sreg2, FALSE);
3458                         }
3459                         break;
3460                 case OP_IDIV:
3461                 case OP_IREM:
3462                         if (ins->sreg2 == AMD64_RDX) {
3463                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3464                                 amd64_cdq_size (code, 4);
3465                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3466                         } else {
3467                                 amd64_cdq_size (code, 4);
3468                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3469                         }
3470                         break;
3471                 case OP_IDIV_UN:
3472                 case OP_IREM_UN:
3473                         if (ins->sreg2 == AMD64_RDX) {
3474                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3475                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3476                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3477                         } else {
3478                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3479                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3480                         }
3481                         break;
3482                 case OP_LMUL_OVF:
3483                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3484                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3485                         break;
3486                 case OP_LOR:
3487                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3488                         break;
3489                 case OP_OR_IMM:
3490                 case OP_LOR_IMM:
3491                         g_assert (amd64_is_imm32 (ins->inst_imm));
3492                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3493                         break;
3494                 case OP_LXOR:
3495                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3496                         break;
3497                 case OP_XOR_IMM:
3498                 case OP_LXOR_IMM:
3499                         g_assert (amd64_is_imm32 (ins->inst_imm));
3500                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3501                         break;
3502                 case OP_LSHL:
3503                         g_assert (ins->sreg2 == AMD64_RCX);
3504                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3505                         break;
3506                 case OP_LSHR:
3507                         g_assert (ins->sreg2 == AMD64_RCX);
3508                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3509                         break;
3510                 case OP_SHR_IMM:
3511                         g_assert (amd64_is_imm32 (ins->inst_imm));
3512                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3513                         break;
3514                 case OP_LSHR_IMM:
3515                         g_assert (amd64_is_imm32 (ins->inst_imm));
3516                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3517                         break;
3518                 case OP_SHR_UN_IMM:
3519                         g_assert (amd64_is_imm32 (ins->inst_imm));
3520                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3521                         break;
3522                 case OP_LSHR_UN_IMM:
3523                         g_assert (amd64_is_imm32 (ins->inst_imm));
3524                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3525                         break;
3526                 case OP_LSHR_UN:
3527                         g_assert (ins->sreg2 == AMD64_RCX);
3528                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3529                         break;
3530                 case OP_SHL_IMM:
3531                         g_assert (amd64_is_imm32 (ins->inst_imm));
3532                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3533                         break;
3534                 case OP_LSHL_IMM:
3535                         g_assert (amd64_is_imm32 (ins->inst_imm));
3536                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3537                         break;
3538
3539                 case OP_IADDCC:
3540                 case OP_IADD:
3541                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3542                         break;
3543                 case OP_IADC:
3544                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3545                         break;
3546                 case OP_IADD_IMM:
3547                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3548                         break;
3549                 case OP_IADC_IMM:
3550                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3551                         break;
3552                 case OP_ISUBCC:
3553                 case OP_ISUB:
3554                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3555                         break;
3556                 case OP_ISBB:
3557                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3558                         break;
3559                 case OP_ISUB_IMM:
3560                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3561                         break;
3562                 case OP_ISBB_IMM:
3563                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3564                         break;
3565                 case OP_IAND:
3566                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3567                         break;
3568                 case OP_IAND_IMM:
3569                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3570                         break;
3571                 case OP_IOR:
3572                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3573                         break;
3574                 case OP_IOR_IMM:
3575                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3576                         break;
3577                 case OP_IXOR:
3578                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3579                         break;
3580                 case OP_IXOR_IMM:
3581                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3582                         break;
3583                 case OP_INEG:
3584                         amd64_neg_reg_size (code, ins->sreg1, 4);
3585                         break;
3586                 case OP_INOT:
3587                         amd64_not_reg_size (code, ins->sreg1, 4);
3588                         break;
3589                 case OP_ISHL:
3590                         g_assert (ins->sreg2 == AMD64_RCX);
3591                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3592                         break;
3593                 case OP_ISHR:
3594                         g_assert (ins->sreg2 == AMD64_RCX);
3595                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3596                         break;
3597                 case OP_ISHR_IMM:
3598                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3599                         break;
3600                 case OP_ISHR_UN_IMM:
3601                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3602                         break;
3603                 case OP_ISHR_UN:
3604                         g_assert (ins->sreg2 == AMD64_RCX);
3605                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3606                         break;
3607                 case OP_ISHL_IMM:
3608                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3609                         break;
3610                 case OP_IMUL:
3611                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3612                         break;
3613                 case OP_IMUL_OVF:
3614                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3615                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3616                         break;
3617                 case OP_IMUL_OVF_UN:
3618                 case OP_LMUL_OVF_UN: {
3619                         /* the mul operation and the exception check should most likely be split */
3620                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3621                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3622                         /*g_assert (ins->sreg2 == X86_EAX);
3623                         g_assert (ins->dreg == X86_EAX);*/
3624                         if (ins->sreg2 == X86_EAX) {
3625                                 non_eax_reg = ins->sreg1;
3626                         } else if (ins->sreg1 == X86_EAX) {
3627                                 non_eax_reg = ins->sreg2;
3628                         } else {
3629                                 /* no need to save since we're going to store to it anyway */
3630                                 if (ins->dreg != X86_EAX) {
3631                                         saved_eax = TRUE;
3632                                         amd64_push_reg (code, X86_EAX);
3633                                 }
3634                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3635                                 non_eax_reg = ins->sreg2;
3636                         }
3637                         if (ins->dreg == X86_EDX) {
3638                                 if (!saved_eax) {
3639                                         saved_eax = TRUE;
3640                                         amd64_push_reg (code, X86_EAX);
3641                                 }
3642                         } else {
3643                                 saved_edx = TRUE;
3644                                 amd64_push_reg (code, X86_EDX);
3645                         }
3646                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3647                         /* save before the check since pop and mov don't change the flags */
3648                         if (ins->dreg != X86_EAX)
3649                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3650                         if (saved_edx)
3651                                 amd64_pop_reg (code, X86_EDX);
3652                         if (saved_eax)
3653                                 amd64_pop_reg (code, X86_EAX);
3654                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3655                         break;
3656                 }
3657                 case OP_ICOMPARE:
3658                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3659                         break;
3660                 case OP_ICOMPARE_IMM:
3661                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3662                         break;
3663                 case OP_IBEQ:
3664                 case OP_IBLT:
3665                 case OP_IBGT:
3666                 case OP_IBGE:
3667                 case OP_IBLE:
3668                 case OP_LBEQ:
3669                 case OP_LBLT:
3670                 case OP_LBGT:
3671                 case OP_LBGE:
3672                 case OP_LBLE:
3673                 case OP_IBNE_UN:
3674                 case OP_IBLT_UN:
3675                 case OP_IBGT_UN:
3676                 case OP_IBGE_UN:
3677                 case OP_IBLE_UN:
3678                 case OP_LBNE_UN:
3679                 case OP_LBLT_UN:
3680                 case OP_LBGT_UN:
3681                 case OP_LBGE_UN:
3682                 case OP_LBLE_UN:
3683                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3684                         break;
3685
3686                 case OP_CMOV_IEQ:
3687                 case OP_CMOV_IGE:
3688                 case OP_CMOV_IGT:
3689                 case OP_CMOV_ILE:
3690                 case OP_CMOV_ILT:
3691                 case OP_CMOV_INE_UN:
3692                 case OP_CMOV_IGE_UN:
3693                 case OP_CMOV_IGT_UN:
3694                 case OP_CMOV_ILE_UN:
3695                 case OP_CMOV_ILT_UN:
3696                 case OP_CMOV_LEQ:
3697                 case OP_CMOV_LGE:
3698                 case OP_CMOV_LGT:
3699                 case OP_CMOV_LLE:
3700                 case OP_CMOV_LLT:
3701                 case OP_CMOV_LNE_UN:
3702                 case OP_CMOV_LGE_UN:
3703                 case OP_CMOV_LGT_UN:
3704                 case OP_CMOV_LLE_UN:
3705                 case OP_CMOV_LLT_UN:
3706                         g_assert (ins->dreg == ins->sreg1);
3707                         /* This needs to operate on 64 bit values */
3708                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3709                         break;
3710
3711                 case OP_LNOT:
3712                         amd64_not_reg (code, ins->sreg1);
3713                         break;
3714                 case OP_LNEG:
3715                         amd64_neg_reg (code, ins->sreg1);
3716                         break;
3717
3718                 case OP_ICONST:
3719                 case OP_I8CONST:
3720                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3721                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3722                         else
3723                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3724                         break;
3725                 case OP_AOTCONST:
3726                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3727                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3728                         break;
3729                 case OP_JUMP_TABLE:
3730                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3731                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3732                         break;
3733                 case OP_MOVE:
3734                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3735                         break;
3736                 case OP_AMD64_SET_XMMREG_R4: {
3737                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3738                         break;
3739                 }
3740                 case OP_AMD64_SET_XMMREG_R8: {
3741                         if (ins->dreg != ins->sreg1)
3742                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3743                         break;
3744                 }
3745                 case OP_JMP:
3746                 case OP_TAILCALL: {
3747                         /*
3748                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3749                          * Keep in sync with the code in emit_epilog.
3750                          */
3751                         int pos = 0, i;
3752
3753                         /* FIXME: no tracing support... */
3754                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3755                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3756
3757                         g_assert (!cfg->method->save_lmf);
3758
3759                         if (ins->opcode == OP_JMP)
3760                                 code = emit_load_volatile_arguments (cfg, code);
3761
3762                         if (cfg->arch.omit_fp) {
3763                                 guint32 save_offset = 0;
3764                                 /* Pop callee-saved registers */
3765                                 for (i = 0; i < AMD64_NREG; ++i)
3766                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3767                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3768                                                 save_offset += 8;
3769                                         }
3770                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3771                         }
3772                         else {
3773                                 for (i = 0; i < AMD64_NREG; ++i)
3774                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3775                                                 pos -= sizeof (gpointer);
3776
3777                                 if (pos)
3778                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3779
3780                                 /* Pop registers in reverse order */
3781                                 for (i = AMD64_NREG - 1; i > 0; --i)
3782                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3783                                                 amd64_pop_reg (code, i);
3784                                         }
3785
3786                                 amd64_leave (code);
3787                         }
3788
3789                         offset = code - cfg->native_code;
3790                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3791                         if (cfg->compile_aot)
3792                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3793                         else
3794                                 amd64_set_reg_template (code, AMD64_R11);
3795                         amd64_jump_reg (code, AMD64_R11);
3796                         break;
3797                 }
3798                 case OP_CHECK_THIS:
3799                         /* ensure ins->sreg1 is not NULL */
3800                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3801                         break;
3802                 case OP_ARGLIST: {
3803                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3804                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3805                         break;
3806                 }
3807                 case OP_CALL:
3808                 case OP_FCALL:
3809                 case OP_LCALL:
3810                 case OP_VCALL:
3811                 case OP_VCALL2:
3812                 case OP_VOIDCALL:
3813                         call = (MonoCallInst*)ins;
3814                         /*
3815                          * The AMD64 ABI forces callers to know about varargs.
3816                          */
3817                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3818                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3819                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3820                                 /*
3821                                  * Since the unmanaged calling convention doesn't contain a
3822                                  * 'vararg' entry, we have to treat every pinvoke call as a
3823                                  * potential vararg call.
3824                                  */
3825                                 guint32 nregs, i;
3826                                 nregs = 0;
3827                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3828                                         if (call->used_fregs & (1 << i))
3829                                                 nregs ++;
3830                                 if (!nregs)
3831                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3832                                 else
3833                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3834                         }
3835
3836                         if (ins->flags & MONO_INST_HAS_METHOD)
3837                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3838                         else
3839                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3840                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3841                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3842                         code = emit_move_return_value (cfg, ins, code);
3843                         break;
3844                 case OP_FCALL_REG:
3845                 case OP_LCALL_REG:
3846                 case OP_VCALL_REG:
3847                 case OP_VCALL2_REG:
3848                 case OP_VOIDCALL_REG:
3849                 case OP_CALL_REG:
3850                         call = (MonoCallInst*)ins;
3851
3852                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3853                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3854                                 ins->sreg1 = AMD64_R11;
3855                         }
3856
3857                         /*
3858                          * The AMD64 ABI forces callers to know about varargs.
3859                          */
3860                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3861                                 if (ins->sreg1 == AMD64_RAX) {
3862                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3863                                         ins->sreg1 = AMD64_R11;
3864                                 }
3865                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3866                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3867                                 /*
3868                                  * Since the unmanaged calling convention doesn't contain a
3869                                  * 'vararg' entry, we have to treat every pinvoke call as a
3870                                  * potential vararg call.
3871                                  */
3872                                 guint32 nregs, i;
3873                                 nregs = 0;
3874                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3875                                         if (call->used_fregs & (1 << i))
3876                                                 nregs ++;
3877                                 if (ins->sreg1 == AMD64_RAX) {
3878                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3879                                         ins->sreg1 = AMD64_R11;
3880                                 }
3881                                 if (!nregs)
3882                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3883                                 else
3884                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3885                         }
3886
3887                         amd64_call_reg (code, ins->sreg1);
3888                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3889                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3890                         code = emit_move_return_value (cfg, ins, code);
3891                         break;
3892                 case OP_FCALL_MEMBASE:
3893                 case OP_LCALL_MEMBASE:
3894                 case OP_VCALL_MEMBASE:
3895                 case OP_VCALL2_MEMBASE:
3896                 case OP_VOIDCALL_MEMBASE:
3897                 case OP_CALL_MEMBASE:
3898                         call = (MonoCallInst*)ins;
3899
3900                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3901                                 /*
3902                                  * Can't use R11 because it is clobbered by the trampoline
3903                                  * code, and the reg value is needed by get_vcall_slot_addr.
3904                                  */
3905                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3906                                 ins->sreg1 = AMD64_RAX;
3907                         }
3908
3909                         if (call->method && ins->inst_offset < 0) {
3910                                 gssize val;
3911
3912                                 /*
3913                                  * This is a possible IMT call so save the IMT method in the proper
3914                                  * register. We don't use the generic code in method-to-ir.c, because
3915                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3916                                  * maintain control over the layout of the code.
3917                                  * Also put the base reg in %rax to simplify find_imt_method ().
3918                                  */
3919                                 if (ins->sreg1 != AMD64_RAX) {
3920                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3921                                         ins->sreg1 = AMD64_RAX;
3922                                 }
3923                                 val = (gssize)(gpointer)call->method;
3924
3925                                 // FIXME: Generics sharing
3926 #if 0
3927                                 if ((((guint64)val) >> 32) == 0)
3928                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3929                                 else
3930                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3931 #endif
3932                         }
3933
3934                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3935                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3936                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3937                         code = emit_move_return_value (cfg, ins, code);
3938                         break;
3939                 case OP_AMD64_SAVE_SP_TO_LMF:
3940                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3941                         break;
3942                 case OP_OUTARG:
3943                 case OP_X86_PUSH:
3944                         amd64_push_reg (code, ins->sreg1);
3945                         break;
3946                 case OP_X86_PUSH_IMM:
3947                         g_assert (amd64_is_imm32 (ins->inst_imm));
3948                         amd64_push_imm (code, ins->inst_imm);
3949                         break;
3950                 case OP_X86_PUSH_MEMBASE:
3951                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3952                         break;
3953                 case OP_X86_PUSH_OBJ: {
3954                         int size = ALIGN_TO (ins->inst_imm, 8);
3955                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3956                         amd64_push_reg (code, AMD64_RDI);
3957                         amd64_push_reg (code, AMD64_RSI);
3958                         amd64_push_reg (code, AMD64_RCX);
3959                         if (ins->inst_offset)
3960                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3961                         else
3962                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3963                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8) + (size - ins->inst_imm));
3964                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3965                         amd64_cld (code);
3966                         amd64_prefix (code, X86_REP_PREFIX);
3967                         amd64_movsd (code);
3968                         amd64_pop_reg (code, AMD64_RCX);
3969                         amd64_pop_reg (code, AMD64_RSI);
3970                         amd64_pop_reg (code, AMD64_RDI);
3971                         break;
3972                 }
3973                 case OP_X86_LEA:
3974                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3975                         break;
3976                 case OP_X86_LEA_MEMBASE:
3977                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3978                         break;
3979                 case OP_X86_XCHG:
3980                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3981                         break;
3982                 case OP_LOCALLOC:
3983                         /* keep alignment */
3984                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3985                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3986                         code = mono_emit_stack_alloc (code, ins);
3987                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3988                         break;
3989                 case OP_LOCALLOC_IMM: {
3990                         guint32 size = ins->inst_imm;
3991                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3992
3993                         if (ins->flags & MONO_INST_INIT) {
3994                                 if (size < 64) {
3995                                         int i;
3996
3997                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3998                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3999
4000                                         for (i = 0; i < size; i += 8)
4001                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4002                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4003                                 } else {
4004                                         amd64_mov_reg_imm (code, ins->dreg, size);
4005                                         ins->sreg1 = ins->dreg;
4006
4007                                         code = mono_emit_stack_alloc (code, ins);
4008                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4009                                 }
4010                         } else {
4011                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4012                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4013                         }
4014                         break;
4015                 }
4016                 case OP_THROW: {
4017                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4018                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4019                                              (gpointer)"mono_arch_throw_exception", FALSE);
4020                         break;
4021                 }
4022                 case OP_RETHROW: {
4023                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4024                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4025                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4026                         break;
4027                 }
4028                 case OP_CALL_HANDLER:
4029                         /* Align stack */
4030                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4031                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4032                         amd64_call_imm (code, 0);
4033                         /* Restore stack alignment */
4034                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4035                         break;
4036                 case OP_START_HANDLER: {
4037                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4038                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4039                         break;
4040                 }
4041                 case OP_ENDFINALLY: {
4042                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4043                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4044                         amd64_ret (code);
4045                         break;
4046                 }
4047                 case OP_ENDFILTER: {
4048                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4049                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4050                         /* The local allocator will put the result into RAX */
4051                         amd64_ret (code);
4052                         break;
4053                 }
4054
4055                 case OP_LABEL:
4056                         ins->inst_c0 = code - cfg->native_code;
4057                         break;
4058                 case OP_BR:
4059                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4060                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4061                         //break;
4062                         if (ins->flags & MONO_INST_BRLABEL) {
4063                                 if (ins->inst_i0->inst_c0) {
4064                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
4065                                 } else {
4066                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
4067                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4068                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
4069                                                 x86_jump8 (code, 0);
4070                                         else
4071                                                 x86_jump32 (code, 0);
4072                                 }
4073                         } else {
4074                                 if (ins->inst_target_bb->native_offset) {
4075                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4076                                 } else {
4077                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4078                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4079                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
4080                                                 x86_jump8 (code, 0);
4081                                         else
4082                                                 x86_jump32 (code, 0);
4083                                 }
4084                         }
4085                         break;
4086                 case OP_BR_REG:
4087                         amd64_jump_reg (code, ins->sreg1);
4088                         break;
4089                 case OP_CEQ:
4090                 case OP_LCEQ:
4091                 case OP_ICEQ:
4092                 case OP_CLT:
4093                 case OP_LCLT:
4094                 case OP_ICLT:
4095                 case OP_CGT:
4096                 case OP_ICGT:
4097                 case OP_LCGT:
4098                 case OP_CLT_UN:
4099                 case OP_LCLT_UN:
4100                 case OP_ICLT_UN:
4101                 case OP_CGT_UN:
4102                 case OP_LCGT_UN:
4103                 case OP_ICGT_UN:
4104                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4105                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4106                         break;
4107                 case OP_COND_EXC_EQ:
4108                 case OP_COND_EXC_NE_UN:
4109                 case OP_COND_EXC_LT:
4110                 case OP_COND_EXC_LT_UN:
4111                 case OP_COND_EXC_GT:
4112                 case OP_COND_EXC_GT_UN:
4113                 case OP_COND_EXC_GE:
4114                 case OP_COND_EXC_GE_UN:
4115                 case OP_COND_EXC_LE:
4116                 case OP_COND_EXC_LE_UN:
4117                 case OP_COND_EXC_IEQ:
4118                 case OP_COND_EXC_INE_UN:
4119                 case OP_COND_EXC_ILT:
4120                 case OP_COND_EXC_ILT_UN:
4121                 case OP_COND_EXC_IGT:
4122                 case OP_COND_EXC_IGT_UN:
4123                 case OP_COND_EXC_IGE:
4124                 case OP_COND_EXC_IGE_UN:
4125                 case OP_COND_EXC_ILE:
4126                 case OP_COND_EXC_ILE_UN:
4127                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4128                         break;
4129                 case OP_COND_EXC_OV:
4130                 case OP_COND_EXC_NO:
4131                 case OP_COND_EXC_C:
4132                 case OP_COND_EXC_NC:
4133                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4134                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4135                         break;
4136                 case OP_COND_EXC_IOV:
4137                 case OP_COND_EXC_INO:
4138                 case OP_COND_EXC_IC:
4139                 case OP_COND_EXC_INC:
4140                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4141                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4142                         break;
4143
4144                 /* floating point opcodes */
4145                 case OP_R8CONST: {
4146                         double d = *(double *)ins->inst_p0;
4147
4148                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4149                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4150                         }
4151                         else {
4152                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4153                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4154                         }
4155                         break;
4156                 }
4157                 case OP_R4CONST: {
4158                         float f = *(float *)ins->inst_p0;
4159
4160                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4161                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4162                         }
4163                         else {
4164                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4165                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4166                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4167                         }
4168                         break;
4169                 }
4170                 case OP_STORER8_MEMBASE_REG:
4171                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4172                         break;
4173                 case OP_LOADR8_SPILL_MEMBASE:
4174                         g_assert_not_reached ();
4175                         break;
4176                 case OP_LOADR8_MEMBASE:
4177                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4178                         break;
4179                 case OP_STORER4_MEMBASE_REG:
4180                         /* This requires a double->single conversion */
4181                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4182                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4183                         break;
4184                 case OP_LOADR4_MEMBASE:
4185                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4186                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4187                         break;
4188                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4189                 case OP_ICONV_TO_R8:
4190                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4191                         break;
4192                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4193                 case OP_LCONV_TO_R8:
4194                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4195                         break;
4196                 case OP_FCONV_TO_R4:
4197                         /* FIXME: nothing to do ?? */
4198                         break;
4199                 case OP_FCONV_TO_I1:
4200                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4201                         break;
4202                 case OP_FCONV_TO_U1:
4203                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4204                         break;
4205                 case OP_FCONV_TO_I2:
4206                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4207                         break;
4208                 case OP_FCONV_TO_U2:
4209                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4210                         break;
4211                 case OP_FCONV_TO_U4:
4212                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4213                         break;
4214                 case OP_FCONV_TO_I4:
4215                 case OP_FCONV_TO_I:
4216                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4217                         break;
4218                 case OP_FCONV_TO_I8:
4219                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4220                         break;
4221                 case OP_LCONV_TO_R_UN: {
4222                         guint8 *br [2];
4223
4224                         /* Based on gcc code */
4225                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4226                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4227
4228                         /* Positive case */
4229                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4230                         br [1] = code; x86_jump8 (code, 0);
4231                         amd64_patch (br [0], code);
4232
4233                         /* Negative case */
4234                         /* Save to the red zone */
4235                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4236                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4237                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4238                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4239                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4240                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4241                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4242                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4243                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4244                         /* Restore */
4245                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4246                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4247                         amd64_patch (br [1], code);
4248                         break;
4249                 }
4250                 case OP_LCONV_TO_OVF_U4:
4251                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4252                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4253                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4254                         break;
4255                 case OP_LCONV_TO_OVF_I4_UN:
4256                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4257                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4258                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4259                         break;
4260                 case OP_FMOVE:
4261                         if (ins->dreg != ins->sreg1)
4262                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4263                         break;
4264                 case OP_FADD:
4265                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4266                         break;
4267                 case OP_FSUB:
4268                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4269                         break;
4270                 case OP_FMUL:
4271                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4272                         break;
4273                 case OP_FDIV:
4274                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4275                         break;
4276                 case OP_FNEG: {
4277                         static double r8_0 = -0.0;
4278
4279                         g_assert (ins->sreg1 == ins->dreg);
4280
4281                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4282                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4283                         break;
4284                 }
4285                 case OP_SIN:
4286                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4287                         break;
4288                 case OP_COS:
4289                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4290                         break;
4291                 case OP_ABS: {
4292                         static guint64 d = 0x7fffffffffffffffUL;
4293
4294                         g_assert (ins->sreg1 == ins->dreg);
4295
4296                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4297                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4298                         break;
4299                 }
4300                 case OP_SQRT:
4301                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4302                         break;
4303                 case OP_IMIN:
4304                         g_assert (cfg->opt & MONO_OPT_CMOV);
4305                         g_assert (ins->dreg == ins->sreg1);
4306                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4307                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4308                         break;
4309                 case OP_IMIN_UN:
4310                         g_assert (cfg->opt & MONO_OPT_CMOV);
4311                         g_assert (ins->dreg == ins->sreg1);
4312                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4313                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4314                         break;
4315                 case OP_IMAX:
4316                         g_assert (cfg->opt & MONO_OPT_CMOV);
4317                         g_assert (ins->dreg == ins->sreg1);
4318                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4319                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4320                         break;
4321                 case OP_IMAX_UN:
4322                         g_assert (cfg->opt & MONO_OPT_CMOV);
4323                         g_assert (ins->dreg == ins->sreg1);
4324                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4325                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4326                         break;
4327                 case OP_LMIN:
4328                         g_assert (cfg->opt & MONO_OPT_CMOV);
4329                         g_assert (ins->dreg == ins->sreg1);
4330                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4331                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4332                         break;
4333                 case OP_LMIN_UN:
4334                         g_assert (cfg->opt & MONO_OPT_CMOV);
4335                         g_assert (ins->dreg == ins->sreg1);
4336                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4337                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4338                         break;
4339                 case OP_LMAX:
4340                         g_assert (cfg->opt & MONO_OPT_CMOV);
4341                         g_assert (ins->dreg == ins->sreg1);
4342                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4343                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4344                         break;
4345                 case OP_LMAX_UN:
4346                         g_assert (cfg->opt & MONO_OPT_CMOV);
4347                         g_assert (ins->dreg == ins->sreg1);
4348                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4349                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4350                         break;
4351                 case OP_X86_FPOP:
4352                         break;
4353                 case OP_FCOMPARE:
4354                         /*
4355                          * The two arguments are swapped because the fbranch instructions
4356                          * depend on this for the non-sse case to work.
4357                          */
4358                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4359                         break;
4360                 case OP_FCEQ: {
4361                         /* zeroing the register at the start results in
4362                          * shorter and faster code (we can also remove the widening op)
4363                          */
4364                         guchar *unordered_check;
4365                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4366                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4367                         unordered_check = code;
4368                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4369                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4370                         amd64_patch (unordered_check, code);
4371                         break;
4372                 }
4373                 case OP_FCLT:
4374                 case OP_FCLT_UN:
4375                         /* zeroing the register at the start results in
4376                          * shorter and faster code (we can also remove the widening op)
4377                          */
4378                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4379                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4380                         if (ins->opcode == OP_FCLT_UN) {
4381                                 guchar *unordered_check = code;
4382                                 guchar *jump_to_end;
4383                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4384                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4385                                 jump_to_end = code;
4386                                 x86_jump8 (code, 0);
4387                                 amd64_patch (unordered_check, code);
4388                                 amd64_inc_reg (code, ins->dreg);
4389                                 amd64_patch (jump_to_end, code);
4390                         } else {
4391                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4392                         }
4393                         break;
4394                 case OP_FCGT:
4395                 case OP_FCGT_UN: {
4396                         /* zeroing the register at the start results in
4397                          * shorter and faster code (we can also remove the widening op)
4398                          */
4399                         guchar *unordered_check;
4400                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4401                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4402                         if (ins->opcode == OP_FCGT) {
4403                                 unordered_check = code;
4404                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4405                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4406                                 amd64_patch (unordered_check, code);
4407                         } else {
4408                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4409                         }
4410                         break;
4411                 }
4412                 case OP_FCLT_MEMBASE:
4413                 case OP_FCGT_MEMBASE:
4414                 case OP_FCLT_UN_MEMBASE:
4415                 case OP_FCGT_UN_MEMBASE:
4416                 case OP_FCEQ_MEMBASE: {
4417                         guchar *unordered_check, *jump_to_end;
4418                         int x86_cond;
4419
4420                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4421                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4422
4423                         switch (ins->opcode) {
4424                         case OP_FCEQ_MEMBASE:
4425                                 x86_cond = X86_CC_EQ;
4426                                 break;
4427                         case OP_FCLT_MEMBASE:
4428                         case OP_FCLT_UN_MEMBASE:
4429                                 x86_cond = X86_CC_LT;
4430                                 break;
4431                         case OP_FCGT_MEMBASE:
4432                         case OP_FCGT_UN_MEMBASE:
4433                                 x86_cond = X86_CC_GT;
4434                                 break;
4435                         default:
4436                                 g_assert_not_reached ();
4437                         }
4438
4439                         unordered_check = code;
4440                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4441                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4442
4443                         switch (ins->opcode) {
4444                         case OP_FCEQ_MEMBASE:
4445                         case OP_FCLT_MEMBASE:
4446                         case OP_FCGT_MEMBASE:
4447                                 amd64_patch (unordered_check, code);
4448                                 break;
4449                         case OP_FCLT_UN_MEMBASE:
4450                         case OP_FCGT_UN_MEMBASE:
4451                                 jump_to_end = code;
4452                                 x86_jump8 (code, 0);
4453                                 amd64_patch (unordered_check, code);
4454                                 amd64_inc_reg (code, ins->dreg);
4455                                 amd64_patch (jump_to_end, code);
4456                                 break;
4457                         default:
4458                                 break;
4459                         }
4460                         break;
4461                 }
4462                 case OP_FBEQ: {
4463                         guchar *jump = code;
4464                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4465                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4466                         amd64_patch (jump, code);
4467                         break;
4468                 }
4469                 case OP_FBNE_UN:
4470                         /* Branch if C013 != 100 */
4471                         /* branch if !ZF or (PF|CF) */
4472                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4473                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4474                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4475                         break;
4476                 case OP_FBLT:
4477                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4478                         break;
4479                 case OP_FBLT_UN:
4480                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4481                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4482                         break;
4483                 case OP_FBGT:
4484                 case OP_FBGT_UN:
4485                         if (ins->opcode == OP_FBGT) {
4486                                 guchar *br1;
4487
4488                                 /* skip branch if C1=1 */
4489                                 br1 = code;
4490                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4491                                 /* branch if (C0 | C3) = 1 */
4492                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4493                                 amd64_patch (br1, code);
4494                                 break;
4495                         } else {
4496                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4497                         }
4498                         break;
4499                 case OP_FBGE: {
4500                         /* Branch if C013 == 100 or 001 */
4501                         guchar *br1;
4502
4503                         /* skip branch if C1=1 */
4504                         br1 = code;
4505                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4506                         /* branch if (C0 | C3) = 1 */
4507                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4508                         amd64_patch (br1, code);
4509                         break;
4510                 }
4511                 case OP_FBGE_UN:
4512                         /* Branch if C013 == 000 */
4513                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4514                         break;
4515                 case OP_FBLE: {
4516                         /* Branch if C013=000 or 100 */
4517                         guchar *br1;
4518
4519                         /* skip branch if C1=1 */
4520                         br1 = code;
4521                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4522                         /* branch if C0=0 */
4523                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4524                         amd64_patch (br1, code);
4525                         break;
4526                 }
4527                 case OP_FBLE_UN:
4528                         /* Branch if C013 != 001 */
4529                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4530                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4531                         break;
4532                 case OP_CKFINITE:
4533                         /* Transfer value to the fp stack */
4534                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4535                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4536                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4537
4538                         amd64_push_reg (code, AMD64_RAX);
4539                         amd64_fxam (code);
4540                         amd64_fnstsw (code);
4541                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4542                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4543                         amd64_pop_reg (code, AMD64_RAX);
4544                         amd64_fstp (code, 0);
4545                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4546                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4547                         break;
4548                 case OP_TLS_GET: {
4549                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4550                         break;
4551                 }
4552                 case OP_MEMORY_BARRIER: {
4553                         /* Not needed on amd64 */
4554                         break;
4555                 }
4556                 case OP_ATOMIC_ADD_I4:
4557                 case OP_ATOMIC_ADD_I8: {
4558                         int dreg = ins->dreg;
4559                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4560
4561                         if (dreg == ins->inst_basereg)
4562                                 dreg = AMD64_R11;
4563
4564                         if (dreg != ins->sreg2)
4565                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4566
4567                         x86_prefix (code, X86_LOCK_PREFIX);
4568                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4569
4570                         if (dreg != ins->dreg)
4571                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4572
4573                         break;
4574                 }
4575                 case OP_ATOMIC_ADD_NEW_I4:
4576                 case OP_ATOMIC_ADD_NEW_I8: {
4577                         int dreg = ins->dreg;
4578                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4579
4580                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4581                                 dreg = AMD64_R11;
4582
4583                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4584                         amd64_prefix (code, X86_LOCK_PREFIX);
4585                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4586                         /* dreg contains the old value, add with sreg2 value */
4587                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4588
4589                         if (ins->dreg != dreg)
4590                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4591
4592                         break;
4593                 }
4594                 case OP_ATOMIC_EXCHANGE_I4:
4595                 case OP_ATOMIC_EXCHANGE_I8:
4596                 case OP_ATOMIC_CAS_IMM_I4: {
4597                         guchar *br[2];
4598                         int sreg2 = ins->sreg2;
4599                         int breg = ins->inst_basereg;
4600                         guint32 size;
4601                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4602
4603                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4604                                 size = 8;
4605                         else
4606                                 size = 4;
4607
4608                         /*
4609                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4610                          * an explanation of how this works.
4611                          */
4612
4613                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4614                          * hack to overcome limits in x86 reg allocator
4615                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4616                          */
4617                         g_assert (ins->dreg == AMD64_RAX);
4618
4619                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4620                                 /* Highly unlikely, but possible */
4621                                 need_push = TRUE;
4622
4623                         /* The pushes invalidate rsp */
4624                         if ((breg == AMD64_RAX) || need_push) {
4625                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4626                                 breg = AMD64_R11;
4627                         }
4628
4629                         /* We need the EAX reg for the comparand */
4630                         if (ins->sreg2 == AMD64_RAX) {
4631                                 if (breg != AMD64_R11) {
4632                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4633                                         sreg2 = AMD64_R11;
4634                                 } else {
4635                                         g_assert (need_push);
4636                                         amd64_push_reg (code, AMD64_RDX);
4637                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4638                                         sreg2 = AMD64_RDX;
4639                                         rdx_pushed = TRUE;
4640                                 }
4641                         }
4642
4643                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4644                                 if (ins->backend.data == NULL)
4645                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4646                                 else
4647                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4648
4649                                 amd64_prefix (code, X86_LOCK_PREFIX);
4650                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4651                         } else {
4652                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4653
4654                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4655                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4656                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4657                                 amd64_patch (br [1], br [0]);
4658                         }
4659
4660                         if (rdx_pushed)
4661                                 amd64_pop_reg (code, AMD64_RDX);
4662
4663                         break;
4664                 }
4665                 default:
4666                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4667                         g_assert_not_reached ();
4668                 }
4669
4670                 if ((code - cfg->native_code - offset) > max_len) {
4671                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4672                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4673                         g_assert_not_reached ();
4674                 }
4675
4676                 cpos += max_len;
4677
4678                 last_ins = ins;
4679                 last_offset = offset;
4680         }
4681
4682         cfg->code_len = code - cfg->native_code;
4683 }
4684
4685 void
4686 mono_arch_register_lowlevel_calls (void)
4687 {
4688         /* The signature doesn't matter */
4689         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4690 }
4691
4692 void
4693 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4694 {
4695         MonoJumpInfo *patch_info;
4696         gboolean compile_aot = !run_cctors;
4697
4698         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4699                 unsigned char *ip = patch_info->ip.i + code;
4700                 unsigned char *target;
4701
4702                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4703
4704                 if (compile_aot) {
4705                         switch (patch_info->type) {
4706                         case MONO_PATCH_INFO_BB:
4707                         case MONO_PATCH_INFO_LABEL:
4708                                 break;
4709                         default:
4710                                 /* No need to patch these */
4711                                 continue;
4712                         }
4713                 }
4714
4715                 switch (patch_info->type) {
4716                 case MONO_PATCH_INFO_NONE:
4717                         continue;
4718                 case MONO_PATCH_INFO_METHOD_REL:
4719                 case MONO_PATCH_INFO_R8:
4720                 case MONO_PATCH_INFO_R4:
4721                         g_assert_not_reached ();
4722                         continue;
4723                 case MONO_PATCH_INFO_BB:
4724                         break;
4725                 default:
4726                         break;
4727                 }
4728
4729                 /*
4730                  * Debug code to help track down problems where the target of a near call is
4731                  * is not valid.
4732                  */
4733                 if (amd64_is_near_call (ip)) {
4734                         gint64 disp = (guint8*)target - (guint8*)ip;
4735
4736                         if (!amd64_is_imm32 (disp)) {
4737                                 printf ("TYPE: %d\n", patch_info->type);
4738                                 switch (patch_info->type) {
4739                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4740                                         printf ("V: %s\n", patch_info->data.name);
4741                                         break;
4742                                 case MONO_PATCH_INFO_METHOD_JUMP:
4743                                 case MONO_PATCH_INFO_METHOD:
4744                                         printf ("V: %s\n", patch_info->data.method->name);
4745                                         break;
4746                                 default:
4747                                         break;
4748                                 }
4749                         }
4750                 }
4751
4752                 amd64_patch (ip, (gpointer)target);
4753         }
4754 }
4755
4756 static int
4757 get_max_epilog_size (MonoCompile *cfg)
4758 {
4759         int max_epilog_size = 16;
4760
4761         if (cfg->method->save_lmf)
4762                 max_epilog_size += 256;
4763
4764         if (mono_jit_trace_calls != NULL)
4765                 max_epilog_size += 50;
4766
4767         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4768                 max_epilog_size += 50;
4769
4770         max_epilog_size += (AMD64_NREG * 2);
4771
4772         return max_epilog_size;
4773 }
4774
4775 /*
4776  * This macro is used for testing whenever the unwinder works correctly at every point
4777  * where an async exception can happen.
4778  */
4779 /* This will generate a SIGSEGV at the given point in the code */
4780 #define async_exc_point(code) do { \
4781     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4782          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4783              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4784          cfg->arch.async_point_count ++; \
4785     } \
4786 } while (0)
4787
4788 guint8 *
4789 mono_arch_emit_prolog (MonoCompile *cfg)
4790 {
4791         MonoMethod *method = cfg->method;
4792         MonoBasicBlock *bb;
4793         MonoMethodSignature *sig;
4794         MonoInst *ins;
4795         int alloc_size, pos, max_offset, i, quad, max_epilog_size;
4796         guint8 *code;
4797         CallInfo *cinfo;
4798         gint32 lmf_offset = cfg->arch.lmf_offset;
4799         gboolean args_clobbered = FALSE;
4800         gboolean trace = FALSE;
4801
4802         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4803
4804         code = cfg->native_code = g_malloc (cfg->code_size);
4805
4806         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4807                 trace = TRUE;
4808
4809         /* Amount of stack space allocated by register saving code */
4810         pos = 0;
4811
4812         /*
4813          * The prolog consists of the following parts:
4814          * FP present:
4815          * - push rbp, mov rbp, rsp
4816          * - save callee saved regs using pushes
4817          * - allocate frame
4818          * - save rgctx if needed
4819          * - save lmf if needed
4820          * FP not present:
4821          * - allocate frame
4822          * - save rgctx if needed
4823          * - save lmf if needed
4824          * - save callee saved regs using moves
4825          */
4826
4827         async_exc_point (code);
4828
4829         if (!cfg->arch.omit_fp) {
4830                 amd64_push_reg (code, AMD64_RBP);
4831                 async_exc_point (code);
4832 #ifdef PLATFORM_WIN32
4833                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4834 #endif
4835
4836                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4837                 async_exc_point (code);
4838 #ifdef PLATFORM_WIN32
4839                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4840 #endif
4841         }
4842
4843         /* Save callee saved registers */
4844         if (!cfg->arch.omit_fp && !method->save_lmf) {
4845                 for (i = 0; i < AMD64_NREG; ++i)
4846                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4847                                 amd64_push_reg (code, i);
4848                                 pos += sizeof (gpointer);
4849                                 async_exc_point (code);
4850                         }
4851         }
4852
4853         if (cfg->arch.omit_fp) {
4854                 /*
4855                  * On enter, the stack is misaligned by the the pushing of the return
4856                  * address. It is either made aligned by the pushing of %rbp, or by
4857                  * this.
4858                  */
4859                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4860                 if ((alloc_size % 16) == 0)
4861                         alloc_size += 8;
4862         } else {
4863                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4864
4865                 alloc_size -= pos;
4866         }
4867
4868         cfg->arch.stack_alloc_size = alloc_size;
4869
4870         /* Allocate stack frame */
4871         if (alloc_size) {
4872                 /* See mono_emit_stack_alloc */
4873 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4874                 guint32 remaining_size = alloc_size;
4875                 while (remaining_size >= 0x1000) {
4876                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4877                         async_exc_point (code);
4878 #ifdef PLATFORM_WIN32
4879                         if (cfg->arch.omit_fp)
4880                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4881 #endif
4882
4883                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4884                         remaining_size -= 0x1000;
4885                 }
4886                 if (remaining_size) {
4887                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4888                         async_exc_point (code);
4889 #ifdef PLATFORM_WIN32
4890                         if (cfg->arch.omit_fp)
4891                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4892 #endif
4893                 }
4894 #else
4895                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4896                 async_exc_point (code);
4897 #endif
4898         }
4899
4900         /* Stack alignment check */
4901 #if 0
4902         {
4903                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4904                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4905                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4906                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4907                 amd64_breakpoint (code);
4908         }
4909 #endif
4910
4911         /* Save LMF */
4912         if (method->save_lmf) {
4913                 /*
4914                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4915                  */
4916                 /* sp is saved right before calls */
4917                 /* Skip method (only needed for trampoline LMF frames) */
4918                 /* Save callee saved regs */
4919                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4920                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4921                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4922                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4923                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4924                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4925         }
4926
4927         /* Save callee saved registers */
4928         if (cfg->arch.omit_fp && !method->save_lmf) {
4929                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4930
4931                 /* Save caller saved registers after sp is adjusted */
4932                 /* The registers are saved at the bottom of the frame */
4933                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4934                 for (i = 0; i < AMD64_NREG; ++i)
4935                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4936                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4937                                 save_area_offset += 8;
4938                                 async_exc_point (code);
4939                         }
4940         }
4941
4942         /* store runtime generic context */
4943         if (cfg->rgctx_var) {
4944                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4945                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4946
4947                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4948         }
4949
4950         /* compute max_offset in order to use short forward jumps */
4951         max_offset = 0;
4952         max_epilog_size = get_max_epilog_size (cfg);
4953         if (cfg->opt & MONO_OPT_BRANCH) {
4954                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4955                         MonoInst *ins;
4956                         bb->max_offset = max_offset;
4957
4958                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4959                                 max_offset += 6;
4960                         /* max alignment for loops */
4961                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4962                                 max_offset += LOOP_ALIGNMENT;
4963
4964                         MONO_BB_FOR_EACH_INS (bb, ins) {
4965                                 if (ins->opcode == OP_LABEL)
4966                                         ins->inst_c1 = max_offset;
4967
4968                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4969                         }
4970
4971                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4972                                 /* The tracing code can be quite large */
4973                                 max_offset += max_epilog_size;
4974                 }
4975         }
4976
4977         sig = mono_method_signature (method);
4978         pos = 0;
4979
4980         cinfo = cfg->arch.cinfo;
4981
4982         if (sig->ret->type != MONO_TYPE_VOID) {
4983                 /* Save volatile arguments to the stack */
4984                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4985                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4986         }
4987
4988         /* Keep this in sync with emit_load_volatile_arguments */
4989         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4990                 ArgInfo *ainfo = cinfo->args + i;
4991                 gint32 stack_offset;
4992                 MonoType *arg_type;
4993
4994                 ins = cfg->args [i];
4995
4996                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4997                         /* Unused arguments */
4998                         continue;
4999
5000                 if (sig->hasthis && (i == 0))
5001                         arg_type = &mono_defaults.object_class->byval_arg;
5002                 else
5003                         arg_type = sig->params [i - sig->hasthis];
5004
5005                 stack_offset = ainfo->offset + ARGS_OFFSET;
5006
5007                 if (cfg->globalra) {
5008                         /* All the other moves are done by the register allocator */
5009                         switch (ainfo->storage) {
5010                         case ArgInFloatSSEReg:
5011                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5012                                 break;
5013                         case ArgValuetypeInReg:
5014                                 for (quad = 0; quad < 2; quad ++) {
5015                                         switch (ainfo->pair_storage [quad]) {
5016                                         case ArgInIReg:
5017                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5018                                                 break;
5019                                         case ArgInFloatSSEReg:
5020                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5021                                                 break;
5022                                         case ArgInDoubleSSEReg:
5023                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5024                                                 break;
5025                                         case ArgNone:
5026                                                 break;
5027                                         default:
5028                                                 g_assert_not_reached ();
5029                                         }
5030                                 }
5031                                 break;
5032                         default:
5033                                 break;
5034                         }
5035
5036                         continue;
5037                 }
5038
5039                 /* Save volatile arguments to the stack */
5040                 if (ins->opcode != OP_REGVAR) {
5041                         switch (ainfo->storage) {
5042                         case ArgInIReg: {
5043                                 guint32 size = 8;
5044
5045                                 /* FIXME: I1 etc */
5046                                 /*
5047                                 if (stack_offset & 0x1)
5048                                         size = 1;
5049                                 else if (stack_offset & 0x2)
5050                                         size = 2;
5051                                 else if (stack_offset & 0x4)
5052                                         size = 4;
5053                                 else
5054                                         size = 8;
5055                                 */
5056                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5057                                 break;
5058                         }
5059                         case ArgInFloatSSEReg:
5060                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5061                                 break;
5062                         case ArgInDoubleSSEReg:
5063                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5064                                 break;
5065                         case ArgValuetypeInReg:
5066                                 for (quad = 0; quad < 2; quad ++) {
5067                                         switch (ainfo->pair_storage [quad]) {
5068                                         case ArgInIReg:
5069                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5070                                                 break;
5071                                         case ArgInFloatSSEReg:
5072                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5073                                                 break;
5074                                         case ArgInDoubleSSEReg:
5075                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5076                                                 break;
5077                                         case ArgNone:
5078                                                 break;
5079                                         default:
5080                                                 g_assert_not_reached ();
5081                                         }
5082                                 }
5083                                 break;
5084                         case ArgValuetypeAddrInIReg:
5085                                 if (ainfo->pair_storage [0] == ArgInIReg)
5086                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5087                                 break;
5088                         default:
5089                                 break;
5090                         }
5091                 } else {
5092                         /* Argument allocated to (non-volatile) register */
5093                         switch (ainfo->storage) {
5094                         case ArgInIReg:
5095                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5096                                 break;
5097                         case ArgOnStack:
5098                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5099                                 break;
5100                         default:
5101                                 g_assert_not_reached ();
5102                         }
5103                 }
5104         }
5105
5106         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5107         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5108                 guint64 domain = (guint64)cfg->domain;
5109
5110                 args_clobbered = TRUE;
5111
5112                 /*
5113                  * The call might clobber argument registers, but they are already
5114                  * saved to the stack/global regs.
5115                  */
5116                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5117                         guint8 *buf, *no_domain_branch;
5118
5119                         code = emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5120                         if ((domain >> 32) == 0)
5121                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5122                         else
5123                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5124                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
5125                         no_domain_branch = code;
5126                         x86_branch8 (code, X86_CC_NE, 0, 0);
5127                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
5128                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5129                         buf = code;
5130                         x86_branch8 (code, X86_CC_NE, 0, 0);
5131                         amd64_patch (no_domain_branch, code);
5132                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5133                                           (gpointer)"mono_jit_thread_attach", TRUE);
5134                         amd64_patch (buf, code);
5135 #ifdef PLATFORM_WIN32
5136                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5137                         /* FIXME: Add a separate key for LMF to avoid this */
5138                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5139 #endif
5140                 } else {
5141                         g_assert (!cfg->compile_aot);
5142                         if ((domain >> 32) == 0)
5143                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5144                         else
5145                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5146                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5147                                           (gpointer)"mono_jit_thread_attach", TRUE);
5148                 }
5149         }
5150
5151         if (method->save_lmf) {
5152                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5153                         /*
5154                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5155                          * through the mono_lmf_addr TLS variable.
5156                          */
5157                         /* %rax = previous_lmf */
5158                         x86_prefix (code, X86_FS_PREFIX);
5159                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5160
5161                         /* Save previous_lmf */
5162                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
5163                         /* Set new lmf */
5164                         if (lmf_offset == 0) {
5165                                 x86_prefix (code, X86_FS_PREFIX);
5166                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
5167                         } else {
5168                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5169                                 x86_prefix (code, X86_FS_PREFIX);
5170                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5171                         }
5172                 } else {
5173                         if (lmf_addr_tls_offset != -1) {
5174                                 /* Load lmf quicky using the FS register */
5175                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
5176 #ifdef PLATFORM_WIN32
5177                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5178                                 /* FIXME: Add a separate key for LMF to avoid this */
5179                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5180 #endif
5181                         }
5182                         else {
5183                                 /*
5184                                  * The call might clobber argument registers, but they are already
5185                                  * saved to the stack/global regs.
5186                                  */
5187                                 args_clobbered = TRUE;
5188                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5189                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
5190                         }
5191
5192                         /* Save lmf_addr */
5193                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
5194                         /* Save previous_lmf */
5195                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
5196                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
5197                         /* Set new lmf */
5198                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5199                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
5200                 }
5201         }
5202
5203         if (trace) {
5204                 args_clobbered = TRUE;
5205                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5206         }
5207
5208         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5209                 args_clobbered = TRUE;
5210
5211         /*
5212          * Optimize the common case of the first bblock making a call with the same
5213          * arguments as the method. This works because the arguments are still in their
5214          * original argument registers.
5215          * FIXME: Generalize this
5216          */
5217         if (!args_clobbered) {
5218                 MonoBasicBlock *first_bb = cfg->bb_entry;
5219                 MonoInst *next;
5220
5221                 next = mono_bb_first_ins (first_bb);
5222                 if (!next && first_bb->next_bb) {
5223                         first_bb = first_bb->next_bb;
5224                         next = mono_bb_first_ins (first_bb);
5225                 }
5226
5227                 if (first_bb->in_count > 1)
5228                         next = NULL;
5229
5230                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
5231                         ArgInfo *ainfo = cinfo->args + i;
5232                         gboolean match = FALSE;
5233
5234                         ins = cfg->args [i];
5235                         if (ins->opcode != OP_REGVAR) {
5236                                 switch (ainfo->storage) {
5237                                 case ArgInIReg: {
5238                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
5239                                                 if (next->dreg == ainfo->reg) {
5240                                                         NULLIFY_INS (next);
5241                                                         match = TRUE;
5242                                                 } else {
5243                                                         next->opcode = OP_MOVE;
5244                                                         next->sreg1 = ainfo->reg;
5245                                                         /* Only continue if the instruction doesn't change argument regs */
5246                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
5247                                                                 match = TRUE;
5248                                                 }
5249                                         }
5250                                         break;
5251                                 }
5252                                 default:
5253                                         break;
5254                                 }
5255                         } else {
5256                                 /* Argument allocated to (non-volatile) register */
5257                                 switch (ainfo->storage) {
5258                                 case ArgInIReg:
5259                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
5260                                                 NULLIFY_INS (next);
5261                                                 match = TRUE;
5262                                         }
5263                                         break;
5264                                 default:
5265                                         break;
5266                                 }
5267                         }
5268
5269                         if (match) {
5270                                 next = next->next;
5271                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
5272                                 if (!next)
5273                                         break;
5274                         }
5275                 }
5276         }
5277
5278         cfg->code_len = code - cfg->native_code;
5279
5280         g_assert (cfg->code_len < cfg->code_size);
5281
5282         return code;
5283 }
5284
5285 void
5286 mono_arch_emit_epilog (MonoCompile *cfg)
5287 {
5288         MonoMethod *method = cfg->method;
5289         int quad, pos, i;
5290         guint8 *code;
5291         int max_epilog_size;
5292         CallInfo *cinfo;
5293         gint32 lmf_offset = cfg->arch.lmf_offset;
5294
5295         max_epilog_size = get_max_epilog_size (cfg);
5296
5297         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5298                 cfg->code_size *= 2;
5299                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5300                 mono_jit_stats.code_reallocs++;
5301         }
5302
5303         code = cfg->native_code + cfg->code_len;
5304
5305         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5306                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5307
5308         /* the code restoring the registers must be kept in sync with OP_JMP */
5309         pos = 0;
5310
5311         if (method->save_lmf) {
5312                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5313                         /*
5314                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5315                          * through the mono_lmf_addr TLS variable.
5316                          */
5317                         /* reg = previous_lmf */
5318                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5319                         x86_prefix (code, X86_FS_PREFIX);
5320                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5321                 } else {
5322                         /* Restore previous lmf */
5323                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5324                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5325                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5326                 }
5327
5328                 /* Restore caller saved regs */
5329                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5330                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5331                 }
5332                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5333                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5334                 }
5335                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5336                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5337                 }
5338                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5339                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5340                 }
5341                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5342                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5343                 }
5344                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5345                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5346                 }
5347         } else {
5348
5349                 if (cfg->arch.omit_fp) {
5350                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5351
5352                         for (i = 0; i < AMD64_NREG; ++i)
5353                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5354                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5355                                         save_area_offset += 8;
5356                                 }
5357                 }
5358                 else {
5359                         for (i = 0; i < AMD64_NREG; ++i)
5360                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5361                                         pos -= sizeof (gpointer);
5362
5363                         if (pos) {
5364                                 if (pos == - sizeof (gpointer)) {
5365                                         /* Only one register, so avoid lea */
5366                                         for (i = AMD64_NREG - 1; i > 0; --i)
5367                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5368                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5369                                                 }
5370                                 }
5371                                 else {
5372                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5373
5374                                         /* Pop registers in reverse order */
5375                                         for (i = AMD64_NREG - 1; i > 0; --i)
5376                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5377                                                         amd64_pop_reg (code, i);
5378                                                 }
5379                                 }
5380                         }
5381                 }
5382         }
5383
5384         /* Load returned vtypes into registers if needed */
5385         cinfo = cfg->arch.cinfo;
5386         if (cinfo->ret.storage == ArgValuetypeInReg) {
5387                 ArgInfo *ainfo = &cinfo->ret;
5388                 MonoInst *inst = cfg->ret;
5389
5390                 for (quad = 0; quad < 2; quad ++) {
5391                         switch (ainfo->pair_storage [quad]) {
5392                         case ArgInIReg:
5393                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5394                                 break;
5395                         case ArgInFloatSSEReg:
5396                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5397                                 break;
5398                         case ArgInDoubleSSEReg:
5399                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5400                                 break;
5401                         case ArgNone:
5402                                 break;
5403                         default:
5404                                 g_assert_not_reached ();
5405                         }
5406                 }
5407         }
5408
5409         if (cfg->arch.omit_fp) {
5410                 if (cfg->arch.stack_alloc_size)
5411                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5412         } else {
5413                 amd64_leave (code);
5414         }
5415         async_exc_point (code);
5416         amd64_ret (code);
5417
5418         cfg->code_len = code - cfg->native_code;
5419
5420         g_assert (cfg->code_len < cfg->code_size);
5421
5422         if (cfg->arch.omit_fp) {
5423                 /*
5424                  * Encode the stack size into used_int_regs so the exception handler
5425                  * can access it.
5426                  */
5427                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5428                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5429         }
5430 }
5431
5432 void
5433 mono_arch_emit_exceptions (MonoCompile *cfg)
5434 {
5435         MonoJumpInfo *patch_info;
5436         int nthrows, i;
5437         guint8 *code;
5438         MonoClass *exc_classes [16];
5439         guint8 *exc_throw_start [16], *exc_throw_end [16];
5440         guint32 code_size = 0;
5441
5442         /* Compute needed space */
5443         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5444                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5445                         code_size += 40;
5446                 if (patch_info->type == MONO_PATCH_INFO_R8)
5447                         code_size += 8 + 15; /* sizeof (double) + alignment */
5448                 if (patch_info->type == MONO_PATCH_INFO_R4)
5449                         code_size += 4 + 15; /* sizeof (float) + alignment */
5450         }
5451
5452         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5453                 cfg->code_size *= 2;
5454                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5455                 mono_jit_stats.code_reallocs++;
5456         }
5457
5458         code = cfg->native_code + cfg->code_len;
5459
5460         /* add code to raise exceptions */
5461         nthrows = 0;
5462         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5463                 switch (patch_info->type) {
5464                 case MONO_PATCH_INFO_EXC: {
5465                         MonoClass *exc_class;
5466                         guint8 *buf, *buf2;
5467                         guint32 throw_ip;
5468
5469                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5470
5471                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5472                         g_assert (exc_class);
5473                         throw_ip = patch_info->ip.i;
5474
5475                         //x86_breakpoint (code);
5476                         /* Find a throw sequence for the same exception class */
5477                         for (i = 0; i < nthrows; ++i)
5478                                 if (exc_classes [i] == exc_class)
5479                                         break;
5480                         if (i < nthrows) {
5481                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5482                                 x86_jump_code (code, exc_throw_start [i]);
5483                                 patch_info->type = MONO_PATCH_INFO_NONE;
5484                         }
5485                         else {
5486                                 buf = code;
5487                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5488                                 buf2 = code;
5489
5490                                 if (nthrows < 16) {
5491                                         exc_classes [nthrows] = exc_class;
5492                                         exc_throw_start [nthrows] = code;
5493                                 }
5494                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5495
5496                                 patch_info->type = MONO_PATCH_INFO_NONE;
5497
5498                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5499
5500                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5501                                 while (buf < buf2)
5502                                         x86_nop (buf);
5503
5504                                 if (nthrows < 16) {
5505                                         exc_throw_end [nthrows] = code;
5506                                         nthrows ++;
5507                                 }
5508                         }
5509                         break;
5510                 }
5511                 default:
5512                         /* do nothing */
5513                         break;
5514                 }
5515         }
5516
5517         /* Handle relocations with RIP relative addressing */
5518         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5519                 gboolean remove = FALSE;
5520
5521                 switch (patch_info->type) {
5522                 case MONO_PATCH_INFO_R8:
5523                 case MONO_PATCH_INFO_R4: {
5524                         guint8 *pos;
5525
5526                         /* The SSE opcodes require a 16 byte alignment */
5527                         code = (guint8*)ALIGN_TO (code, 16);
5528
5529                         pos = cfg->native_code + patch_info->ip.i;
5530
5531                         if (IS_REX (pos [1]))
5532                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5533                         else
5534                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5535
5536                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5537                                 *(double*)code = *(double*)patch_info->data.target;
5538                                 code += sizeof (double);
5539                         } else {
5540                                 *(float*)code = *(float*)patch_info->data.target;
5541                                 code += sizeof (float);
5542                         }
5543
5544                         remove = TRUE;
5545                         break;
5546                 }
5547                 default:
5548                         break;
5549                 }
5550
5551                 if (remove) {
5552                         if (patch_info == cfg->patch_info)
5553                                 cfg->patch_info = patch_info->next;
5554                         else {
5555                                 MonoJumpInfo *tmp;
5556
5557                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5558                                         ;
5559                                 tmp->next = patch_info->next;
5560                         }
5561                 }
5562         }
5563
5564         cfg->code_len = code - cfg->native_code;
5565
5566         g_assert (cfg->code_len < cfg->code_size);
5567
5568 }
5569
5570 void*
5571 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5572 {
5573         guchar *code = p;
5574         CallInfo *cinfo = NULL;
5575         MonoMethodSignature *sig;
5576         MonoInst *inst;
5577         int i, n, stack_area = 0;
5578
5579         /* Keep this in sync with mono_arch_get_argument_info */
5580
5581         if (enable_arguments) {
5582                 /* Allocate a new area on the stack and save arguments there */
5583                 sig = mono_method_signature (cfg->method);
5584
5585                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5586
5587                 n = sig->param_count + sig->hasthis;
5588
5589                 stack_area = ALIGN_TO (n * 8, 16);
5590
5591                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5592
5593                 for (i = 0; i < n; ++i) {
5594                         inst = cfg->args [i];
5595
5596                         if (inst->opcode == OP_REGVAR)
5597                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5598                         else {
5599                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5600                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5601                         }
5602                 }
5603         }
5604
5605         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5606         amd64_set_reg_template (code, AMD64_ARG_REG1);
5607         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5608         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5609
5610         if (enable_arguments)
5611                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5612
5613         return code;
5614 }
5615
5616 enum {
5617         SAVE_NONE,
5618         SAVE_STRUCT,
5619         SAVE_EAX,
5620         SAVE_EAX_EDX,
5621         SAVE_XMM
5622 };
5623
5624 void*
5625 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5626 {
5627         guchar *code = p;
5628         int save_mode = SAVE_NONE;
5629         MonoMethod *method = cfg->method;
5630         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5631
5632         switch (rtype) {
5633         case MONO_TYPE_VOID:
5634                 /* special case string .ctor icall */
5635                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5636                         save_mode = SAVE_EAX;
5637                 else
5638                         save_mode = SAVE_NONE;
5639                 break;
5640         case MONO_TYPE_I8:
5641         case MONO_TYPE_U8:
5642                 save_mode = SAVE_EAX;
5643                 break;
5644         case MONO_TYPE_R4:
5645         case MONO_TYPE_R8:
5646                 save_mode = SAVE_XMM;
5647                 break;
5648         case MONO_TYPE_GENERICINST:
5649                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5650                         save_mode = SAVE_EAX;
5651                         break;
5652                 }
5653                 /* Fall through */
5654         case MONO_TYPE_VALUETYPE:
5655                 save_mode = SAVE_STRUCT;
5656                 break;
5657         default:
5658                 save_mode = SAVE_EAX;
5659                 break;
5660         }
5661
5662         /* Save the result and copy it into the proper argument register */
5663         switch (save_mode) {
5664         case SAVE_EAX:
5665                 amd64_push_reg (code, AMD64_RAX);
5666                 /* Align stack */
5667                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5668                 if (enable_arguments)
5669                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5670                 break;
5671         case SAVE_STRUCT:
5672                 /* FIXME: */
5673                 if (enable_arguments)
5674                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5675                 break;
5676         case SAVE_XMM:
5677                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5678                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5679                 /* Align stack */
5680                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5681                 /*
5682                  * The result is already in the proper argument register so no copying
5683                  * needed.
5684                  */
5685                 break;
5686         case SAVE_NONE:
5687                 break;
5688         default:
5689                 g_assert_not_reached ();
5690         }
5691
5692         /* Set %al since this is a varargs call */
5693         if (save_mode == SAVE_XMM)
5694                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5695         else
5696                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5697
5698         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5699         amd64_set_reg_template (code, AMD64_ARG_REG1);
5700         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5701
5702         /* Restore result */
5703         switch (save_mode) {
5704         case SAVE_EAX:
5705                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5706                 amd64_pop_reg (code, AMD64_RAX);
5707                 break;
5708         case SAVE_STRUCT:
5709                 /* FIXME: */
5710                 break;
5711         case SAVE_XMM:
5712                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5713                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5714                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5715                 break;
5716         case SAVE_NONE:
5717                 break;
5718         default:
5719                 g_assert_not_reached ();
5720         }
5721
5722         return code;
5723 }
5724
5725 void
5726 mono_arch_flush_icache (guint8 *code, gint size)
5727 {
5728         /* Not needed */
5729 }
5730
5731 void
5732 mono_arch_flush_register_windows (void)
5733 {
5734 }
5735
5736 gboolean
5737 mono_arch_is_inst_imm (gint64 imm)
5738 {
5739         return amd64_is_imm32 (imm);
5740 }
5741
5742 /*
5743  * Determine whenever the trap whose info is in SIGINFO is caused by
5744  * integer overflow.
5745  */
5746 gboolean
5747 mono_arch_is_int_overflow (void *sigctx, void *info)
5748 {
5749         MonoContext ctx;
5750         guint8* rip;
5751         int reg;
5752         gint64 value;
5753
5754         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5755
5756         rip = (guint8*)ctx.rip;
5757
5758         if (IS_REX (rip [0])) {
5759                 reg = amd64_rex_b (rip [0]);
5760                 rip ++;
5761         }
5762         else
5763                 reg = 0;
5764
5765         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5766                 /* idiv REG */
5767                 reg += x86_modrm_rm (rip [1]);
5768
5769                 switch (reg) {
5770                 case AMD64_RAX:
5771                         value = ctx.rax;
5772                         break;
5773                 case AMD64_RBX:
5774                         value = ctx.rbx;
5775                         break;
5776                 case AMD64_RCX:
5777                         value = ctx.rcx;
5778                         break;
5779                 case AMD64_RDX:
5780                         value = ctx.rdx;
5781                         break;
5782                 case AMD64_RBP:
5783                         value = ctx.rbp;
5784                         break;
5785                 case AMD64_RSP:
5786                         value = ctx.rsp;
5787                         break;
5788                 case AMD64_RSI:
5789                         value = ctx.rsi;
5790                         break;
5791                 case AMD64_RDI:
5792                         value = ctx.rdi;
5793                         break;
5794                 case AMD64_R12:
5795                         value = ctx.r12;
5796                         break;
5797                 case AMD64_R13:
5798                         value = ctx.r13;
5799                         break;
5800                 case AMD64_R14:
5801                         value = ctx.r14;
5802                         break;
5803                 case AMD64_R15:
5804                         value = ctx.r15;
5805                         break;
5806                 default:
5807                         g_assert_not_reached ();
5808                         reg = -1;
5809                 }
5810
5811                 if (value == -1)
5812                         return TRUE;
5813         }
5814
5815         return FALSE;
5816 }
5817
5818 guint32
5819 mono_arch_get_patch_offset (guint8 *code)
5820 {
5821         return 3;
5822 }
5823
5824 /**
5825  * mono_breakpoint_clean_code:
5826  *
5827  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5828  * breakpoints in the original code, they are removed in the copy.
5829  *
5830  * Returns TRUE if no sw breakpoint was present.
5831  */
5832 gboolean
5833 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5834 {
5835         int i;
5836         gboolean can_write = TRUE;
5837         /*
5838          * If method_start is non-NULL we need to perform bound checks, since we access memory
5839          * at code - offset we could go before the start of the method and end up in a different
5840          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5841          * instead.
5842          */
5843         if (!method_start || code - offset >= method_start) {
5844                 memcpy (buf, code - offset, size);
5845         } else {
5846                 int diff = code - method_start;
5847                 memset (buf, 0, size);
5848                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5849         }
5850         code -= offset;
5851         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5852                 int idx = mono_breakpoint_info_index [i];
5853                 guint8 *ptr;
5854                 if (idx < 1)
5855                         continue;
5856                 ptr = mono_breakpoint_info [idx].address;
5857                 if (ptr >= code && ptr < code + size) {
5858                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5859                         can_write = FALSE;
5860                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5861                         buf [ptr - code] = saved_byte;
5862                 }
5863         }
5864         return can_write;
5865 }
5866
5867 gpointer
5868 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5869 {
5870         guint8 buf [10];
5871         guint32 reg;
5872         gint32 disp;
5873         guint8 rex = 0;
5874
5875         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5876         code = buf + 9;
5877
5878         *displacement = 0;
5879
5880         /* go to the start of the call instruction
5881          *
5882          * address_byte = (m << 6) | (o << 3) | reg
5883          * call opcode: 0xff address_byte displacement
5884          * 0xff m=1,o=2 imm8
5885          * 0xff m=2,o=2 imm32
5886          */
5887         code -= 7;
5888
5889         /*
5890          * A given byte sequence can match more than case here, so we have to be
5891          * really careful about the ordering of the cases. Longer sequences
5892          * come first.
5893          */
5894 #ifdef MONO_ARCH_HAVE_IMT
5895         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5896                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5897                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5898                  * ff 50 fc                call   *0xfffffffc(%rax)
5899                  */
5900                 reg = amd64_modrm_rm (code [5]);
5901                 disp = (signed char)code [6];
5902                 /* R10 is clobbered by the IMT thunk code */
5903                 g_assert (reg != AMD64_R10);
5904         }
5905 #else
5906         if (0) {
5907         }
5908 #endif
5909         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5910                         /*
5911                          * This is a interface call
5912                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5913                          * ff 10                  callq  *(%rax)
5914                          */
5915                 if (IS_REX (code [4]))
5916                         rex = code [4];
5917                 reg = amd64_modrm_rm (code [6]);
5918                 disp = 0;
5919                 /* R10 is clobbered by the IMT thunk code */
5920                 g_assert (reg != AMD64_R10);
5921         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5922                 /* call OFFSET(%rip) */
5923                 disp = *(guint32*)(code + 3);
5924                 return (gpointer*)(code + disp + 7);
5925         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5926                 /* call *[r12+disp32] */
5927                 if (IS_REX (code [-1]))
5928                         rex = code [-1];
5929                 reg = AMD64_RSP;
5930                 disp = *(gint32*)(code + 3);
5931         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5932                 /* call *[reg+disp32] */
5933                 if (IS_REX (code [0]))
5934                         rex = code [0];
5935                 reg = amd64_modrm_rm (code [2]);
5936                 disp = *(gint32*)(code + 3);
5937                 /* R10 is clobbered by the IMT thunk code */
5938                 g_assert (reg != AMD64_R10);
5939         } else if (code [2] == 0xe8) {
5940                 /* call <ADDR> */
5941                 return NULL;
5942         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5943                 /* call *[r12+disp32] */
5944                 if (IS_REX (code [2]))
5945                         rex = code [2];
5946                 reg = AMD64_RSP;
5947                 disp = *(gint8*)(code + 6);
5948         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5949                 /* call *%reg */
5950                 return NULL;
5951         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5952                 /* call *[reg+disp8] */
5953                 if (IS_REX (code [3]))
5954                         rex = code [3];
5955                 reg = amd64_modrm_rm (code [5]);
5956                 disp = *(gint8*)(code + 6);
5957                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5958         }
5959         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5960                         /*
5961                          * This is a interface call: should check the above code can't catch it earlier
5962                          * 8b 40 30   mov    0x30(%eax),%eax
5963                          * ff 10      call   *(%eax)
5964                          */
5965                 if (IS_REX (code [4]))
5966                         rex = code [4];
5967                 reg = amd64_modrm_rm (code [6]);
5968                 disp = 0;
5969         }
5970         else
5971                 g_assert_not_reached ();
5972
5973         reg += amd64_rex_b (rex);
5974
5975         /* R11 is clobbered by the trampoline code */
5976         g_assert (reg != AMD64_R11);
5977
5978         *displacement = disp;
5979         return regs [reg];
5980 }
5981
5982 gpointer*
5983 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5984 {
5985         gpointer vt;
5986         int displacement;
5987         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5988         if (!vt)
5989                 return NULL;
5990         return (gpointer*)((char*)vt + displacement);
5991 }
5992
5993 int
5994 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5995 {
5996         int this_reg = AMD64_ARG_REG1;
5997
5998         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5999                 CallInfo *cinfo;
6000
6001                 if (!gsctx && code)
6002                         gsctx = mono_get_generic_context_from_code (code);
6003
6004                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6005
6006                 if (cinfo->ret.storage != ArgValuetypeInReg)
6007                         this_reg = AMD64_ARG_REG2;
6008                 g_free (cinfo);
6009         }
6010
6011         return this_reg;
6012 }
6013
6014 gpointer
6015 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
6016 {
6017         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6018 }
6019
6020 #define MAX_ARCH_DELEGATE_PARAMS 10
6021
6022 gpointer
6023 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6024 {
6025         guint8 *code, *start;
6026         int i;
6027
6028         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6029                 return NULL;
6030
6031         /* FIXME: Support more cases */
6032         if (MONO_TYPE_ISSTRUCT (sig->ret))
6033                 return NULL;
6034
6035         if (has_target) {
6036                 static guint8* cached = NULL;
6037
6038                 if (cached)
6039                         return cached;
6040
6041                 start = code = mono_global_codeman_reserve (64);
6042
6043                 /* Replace the this argument with the target */
6044                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6045                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6046                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6047
6048                 g_assert ((code - start) < 64);
6049
6050                 mono_debug_add_delegate_trampoline (start, code - start);
6051
6052                 mono_memory_barrier ();
6053
6054                 cached = start;
6055         } else {
6056                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6057                 for (i = 0; i < sig->param_count; ++i)
6058                         if (!mono_is_regsize_var (sig->params [i]))
6059                                 return NULL;
6060                 if (sig->param_count > 4)
6061                         return NULL;
6062
6063                 code = cache [sig->param_count];
6064                 if (code)
6065                         return code;
6066
6067                 start = code = mono_global_codeman_reserve (64);
6068
6069                 if (sig->param_count == 0) {
6070                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6071                 } else {
6072                         /* We have to shift the arguments left */
6073                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6074                         for (i = 0; i < sig->param_count; ++i) {
6075 #ifdef PLATFORM_WIN32
6076                                 if (i < 3)
6077                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6078                                 else
6079                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6080 #else
6081                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6082 #endif
6083                         }
6084
6085                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6086                 }
6087                 g_assert ((code - start) < 64);
6088
6089                 mono_debug_add_delegate_trampoline (start, code - start);
6090
6091                 mono_memory_barrier ();
6092
6093                 cache [sig->param_count] = start;
6094         }
6095
6096         return start;
6097 }
6098
6099 /*
6100  * Support for fast access to the thread-local lmf structure using the GS
6101  * segment register on NPTL + kernel 2.6.x.
6102  */
6103
6104 static gboolean tls_offset_inited = FALSE;
6105
6106 void
6107 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
6108 {
6109         if (!tls_offset_inited) {
6110 #ifdef PLATFORM_WIN32
6111                 /*
6112                  * We need to init this multiple times, since when we are first called, the key might not
6113                  * be initialized yet.
6114                  */
6115                 appdomain_tls_offset = mono_domain_get_tls_key ();
6116                 lmf_tls_offset = mono_get_jit_tls_key ();
6117                 thread_tls_offset = mono_thread_get_tls_key ();
6118                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
6119
6120                 /* Only 64 tls entries can be accessed using inline code */
6121                 if (appdomain_tls_offset >= 64)
6122                         appdomain_tls_offset = -1;
6123                 if (lmf_tls_offset >= 64)
6124                         lmf_tls_offset = -1;
6125                 if (thread_tls_offset >= 64)
6126                         thread_tls_offset = -1;
6127 #else
6128                 tls_offset_inited = TRUE;
6129 #ifdef MONO_XEN_OPT
6130                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
6131 #endif
6132                 appdomain_tls_offset = mono_domain_get_tls_offset ();
6133                 lmf_tls_offset = mono_get_lmf_tls_offset ();
6134                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
6135                 thread_tls_offset = mono_thread_get_tls_offset ();
6136 #endif
6137         }
6138 }
6139
6140 void
6141 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6142 {
6143 }
6144
6145 void
6146 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
6147 {
6148         MonoCallInst *call = (MonoCallInst*)inst;
6149         CallInfo * cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, inst->signature, FALSE);
6150
6151         if (vt_reg != -1) {
6152                 MonoInst *vtarg;
6153
6154                 if (cinfo->ret.storage == ArgValuetypeInReg) {
6155                         /*
6156                          * The valuetype is in RAX:RDX after the call, need to be copied to
6157                          * the stack. Save the address here, so the call instruction can
6158                          * access it.
6159                          */
6160                         MonoInst *loc = cfg->arch.vret_addr_loc;
6161
6162                         g_assert (loc);
6163                         g_assert (loc->opcode == OP_REGOFFSET);
6164
6165                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, loc->inst_basereg, loc->inst_offset, vt_reg);
6166                 } else {
6167                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
6168                         vtarg->sreg1 = vt_reg;
6169                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
6170                         mono_bblock_add_inst (cfg->cbb, vtarg);
6171
6172                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
6173                 }
6174         }
6175
6176         /* add the this argument */
6177         if (this_reg != -1) {
6178                 MonoInst *this;
6179                 MONO_INST_NEW (cfg, this, OP_MOVE);
6180                 this->type = this_type;
6181                 this->sreg1 = this_reg;
6182                 this->dreg = mono_regstate_next_int (cfg->rs);
6183                 mono_bblock_add_inst (cfg->cbb, this);
6184
6185                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
6186         }
6187 }
6188
6189 #ifdef MONO_ARCH_HAVE_IMT
6190
6191 #define CMP_SIZE (6 + 1)
6192 #define CMP_REG_REG_SIZE (4 + 1)
6193 #define BR_SMALL_SIZE 2
6194 #define BR_LARGE_SIZE 6
6195 #define MOV_REG_IMM_SIZE 10
6196 #define MOV_REG_IMM_32BIT_SIZE 6
6197 #define JUMP_REG_SIZE (2 + 1)
6198
6199 static int
6200 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
6201 {
6202         int i, distance = 0;
6203         for (i = start; i < target; ++i)
6204                 distance += imt_entries [i]->chunk_size;
6205         return distance;
6206 }
6207
6208 /*
6209  * LOCKING: called with the domain lock held
6210  */
6211 gpointer
6212 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count)
6213 {
6214         int i;
6215         int size = 0;
6216         guint8 *code, *start;
6217         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
6218
6219         for (i = 0; i < count; ++i) {
6220                 MonoIMTCheckItem *item = imt_entries [i];
6221                 if (item->is_equals) {
6222                         if (item->check_target_idx) {
6223                                 if (!item->compare_done) {
6224                                         if (amd64_is_imm32 (item->method))
6225                                                 item->chunk_size += CMP_SIZE;
6226                                         else
6227                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6228                                 }
6229                                 if (vtable_is_32bit)
6230                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6231                                 else
6232                                         item->chunk_size += MOV_REG_IMM_SIZE;
6233                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
6234                         } else {
6235                                 if (vtable_is_32bit)
6236                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6237                                 else
6238                                         item->chunk_size += MOV_REG_IMM_SIZE;
6239                                 item->chunk_size += JUMP_REG_SIZE;
6240                                 /* with assert below:
6241                                  * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
6242                                  */
6243                         }
6244                 } else {
6245                         if (amd64_is_imm32 (item->method))
6246                                 item->chunk_size += CMP_SIZE;
6247                         else
6248                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6249                         item->chunk_size += BR_LARGE_SIZE;
6250                         imt_entries [item->check_target_idx]->compare_done = TRUE;
6251                 }
6252                 size += item->chunk_size;
6253         }
6254         code = mono_code_manager_reserve (domain->code_mp, size);
6255         start = code;
6256         for (i = 0; i < count; ++i) {
6257                 MonoIMTCheckItem *item = imt_entries [i];
6258                 item->code_target = code;
6259                 if (item->is_equals) {
6260                         if (item->check_target_idx) {
6261                                 if (!item->compare_done) {
6262                                         if (amd64_is_imm32 (item->method))
6263                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6264                                         else {
6265                                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6266                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6267                                         }
6268                                 }
6269                                 item->jmp_code = code;
6270                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6271                                 /* See the comment below about R10 */
6272                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6273                                 amd64_jump_membase (code, AMD64_R10, 0);
6274                         } else {
6275                                 /* enable the commented code to assert on wrong method */
6276 #if 0
6277                                 if (amd64_is_imm32 (item->method))
6278                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6279                                 else {
6280                                         amd64_mov_reg_imm (code, AMD64_R10, item->method);
6281                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6282                                 }
6283                                 item->jmp_code = code;
6284                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6285                                 /* See the comment below about R10 */
6286                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6287                                 amd64_jump_membase (code, AMD64_R10, 0);
6288                                 amd64_patch (item->jmp_code, code);
6289                                 amd64_breakpoint (code);
6290                                 item->jmp_code = NULL;
6291 #else
6292                                 /* We're using R10 here because R11
6293                                    needs to be preserved.  R10 needs
6294                                    to be preserved for calls which
6295                                    require a runtime generic context,
6296                                    but interface calls don't. */
6297                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6298                                 amd64_jump_membase (code, AMD64_R10, 0);
6299 #endif
6300                         }
6301                 } else {
6302                         if (amd64_is_imm32 (item->method))
6303                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6304                         else {
6305                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6306                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6307                         }
6308                         item->jmp_code = code;
6309                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6310                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6311                         else
6312                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6313                 }
6314                 g_assert (code - item->code_target <= item->chunk_size);
6315         }
6316         /* patch the branches to get to the target items */
6317         for (i = 0; i < count; ++i) {
6318                 MonoIMTCheckItem *item = imt_entries [i];
6319                 if (item->jmp_code) {
6320                         if (item->check_target_idx) {
6321                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6322                         }
6323                 }
6324         }
6325
6326         mono_stats.imt_thunks_size += code - start;
6327         g_assert (code - start <= size);
6328
6329         return start;
6330 }
6331
6332 MonoMethod*
6333 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6334 {
6335         return regs [MONO_ARCH_IMT_REG];
6336 }
6337
6338 MonoObject*
6339 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6340 {
6341         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6342 }
6343
6344 void
6345 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6346 {
6347         /* Done by the implementation of the CALL_MEMBASE opcodes */
6348 }
6349 #endif
6350
6351 MonoVTable*
6352 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6353 {
6354         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6355 }
6356
6357 MonoInst*
6358 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6359 {
6360         MonoInst *ins = NULL;
6361
6362         if (cmethod->klass == mono_defaults.math_class) {
6363                 if (strcmp (cmethod->name, "Sin") == 0) {
6364                         MONO_INST_NEW (cfg, ins, OP_SIN);
6365                         ins->inst_i0 = args [0];
6366                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6367                         MONO_INST_NEW (cfg, ins, OP_COS);
6368                         ins->inst_i0 = args [0];
6369                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6370                         MONO_INST_NEW (cfg, ins, OP_SQRT);
6371                         ins->inst_i0 = args [0];
6372                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6373                         MONO_INST_NEW (cfg, ins, OP_ABS);
6374                         ins->inst_i0 = args [0];
6375                 }
6376
6377                 if (cfg->opt & MONO_OPT_CMOV) {
6378                         int opcode = 0;
6379
6380                         if (strcmp (cmethod->name, "Min") == 0) {
6381                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6382                                         opcode = OP_IMIN;
6383                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6384                                         opcode = OP_IMIN_UN;
6385                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6386                                         opcode = OP_LMIN;
6387                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6388                                         opcode = OP_LMIN_UN;
6389                         } else if (strcmp (cmethod->name, "Max") == 0) {
6390                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6391                                         opcode = OP_IMAX;
6392                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6393                                         opcode = OP_IMAX_UN;
6394                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6395                                         opcode = OP_LMAX;
6396                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6397                                         opcode = OP_LMAX_UN;
6398                         }
6399
6400                         if (opcode) {
6401                                 MONO_INST_NEW (cfg, ins, opcode);
6402                                 ins->inst_i0 = args [0];
6403                                 ins->inst_i1 = args [1];
6404                         }
6405                 }
6406
6407 #if 0
6408                 /* OP_FREM is not IEEE compatible */
6409                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6410                         MONO_INST_NEW (cfg, ins, OP_FREM);
6411                         ins->inst_i0 = args [0];
6412                         ins->inst_i1 = args [1];
6413                 }
6414 #endif
6415         }
6416
6417         return ins;
6418 }
6419
6420 MonoInst*
6421 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6422 {
6423         MonoInst *ins = NULL;
6424         int opcode = 0;
6425
6426         if (cmethod->klass == mono_defaults.math_class) {
6427                 if (strcmp (cmethod->name, "Sin") == 0) {
6428                         opcode = OP_SIN;
6429                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6430                         opcode = OP_COS;
6431                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6432                         opcode = OP_SQRT;
6433                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6434                         opcode = OP_ABS;
6435                 }
6436
6437                 if (opcode) {
6438                         MONO_INST_NEW (cfg, ins, opcode);
6439                         ins->type = STACK_R8;
6440                         ins->dreg = mono_alloc_freg (cfg);
6441                         ins->sreg1 = args [0]->dreg;
6442                         MONO_ADD_INS (cfg->cbb, ins);
6443                 }
6444
6445                 opcode = 0;
6446                 if (cfg->opt & MONO_OPT_CMOV) {
6447                         if (strcmp (cmethod->name, "Min") == 0) {
6448                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6449                                         opcode = OP_IMIN;
6450                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6451                                         opcode = OP_IMIN_UN;
6452                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6453                                         opcode = OP_LMIN;
6454                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6455                                         opcode = OP_LMIN_UN;
6456                         } else if (strcmp (cmethod->name, "Max") == 0) {
6457                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6458                                         opcode = OP_IMAX;
6459                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6460                                         opcode = OP_IMAX_UN;
6461                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6462                                         opcode = OP_LMAX;
6463                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6464                                         opcode = OP_LMAX_UN;
6465                         }
6466                 }
6467
6468                 if (opcode) {
6469                         MONO_INST_NEW (cfg, ins, opcode);
6470                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6471                         ins->dreg = mono_alloc_ireg (cfg);
6472                         ins->sreg1 = args [0]->dreg;
6473                         ins->sreg2 = args [1]->dreg;
6474                         MONO_ADD_INS (cfg->cbb, ins);
6475                 }
6476
6477 #if 0
6478                 /* OP_FREM is not IEEE compatible */
6479                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6480                         MONO_INST_NEW (cfg, ins, OP_FREM);
6481                         ins->inst_i0 = args [0];
6482                         ins->inst_i1 = args [1];
6483                 }
6484 #endif
6485         }
6486
6487         /*
6488          * Can't implement CompareExchange methods this way since they have
6489          * three arguments.
6490          */
6491
6492         return ins;
6493 }
6494
6495 gboolean
6496 mono_arch_print_tree (MonoInst *tree, int arity)
6497 {
6498         return 0;
6499 }
6500
6501 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6502 {
6503         MonoInst* ins;
6504
6505         if (appdomain_tls_offset == -1)
6506                 return NULL;
6507
6508         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6509         ins->inst_offset = appdomain_tls_offset;
6510         return ins;
6511 }
6512
6513 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6514 {
6515         MonoInst* ins;
6516
6517         if (thread_tls_offset == -1)
6518                 return NULL;
6519
6520         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6521         ins->inst_offset = thread_tls_offset;
6522         return ins;
6523 }
6524
6525 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6526
6527 gpointer
6528 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6529 {
6530         switch (reg) {
6531         case AMD64_RCX: return (gpointer)ctx->rcx;
6532         case AMD64_RDX: return (gpointer)ctx->rdx;
6533         case AMD64_RBX: return (gpointer)ctx->rbx;
6534         case AMD64_RBP: return (gpointer)ctx->rbp;
6535         case AMD64_RSP: return (gpointer)ctx->rsp;
6536         default:
6537                 if (reg < 8)
6538                         return _CTX_REG (ctx, rax, reg);
6539                 else if (reg >= 12)
6540                         return _CTX_REG (ctx, r12, reg - 12);
6541                 else
6542                         g_assert_not_reached ();
6543         }
6544 }