2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internal.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-mmap.h>
31 #include <mono/utils/mono-memory-model.h>
32 #include <mono/utils/mono-tls.h>
33 #include <mono/utils/mono-hwcap-x86.h>
37 #include "mini-amd64.h"
38 #include "cpu-amd64.h"
39 #include "debugger-agent.h"
43 static gint jit_tls_offset = -1;
47 static gboolean optimize_for_xen = TRUE;
49 #define optimize_for_xen 0
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
59 /* Under windows, the calling convention is never stdcall */
60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
65 /* This mutex protects architecture specific caches */
66 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
67 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
68 static CRITICAL_SECTION mini_arch_mutex;
71 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
73 /* Structure used by the sequence points in AOTed code */
75 gpointer ss_trigger_page;
76 gpointer bp_trigger_page;
77 gpointer bp_addrs [MONO_ZERO_LEN_ARRAY];
81 * The code generated for sequence points reads from this location, which is
82 * made read-only when single stepping is enabled.
84 static gpointer ss_trigger_page;
86 /* Enabled breakpoints read from this trigger page */
87 static gpointer bp_trigger_page;
89 /* The size of the breakpoint sequence */
90 static int breakpoint_size;
92 /* The size of the breakpoint instruction causing the actual fault */
93 static int breakpoint_fault_size;
95 /* The size of the single step instruction causing the actual fault */
96 static int single_step_fault_size;
99 /* On Win64 always reserve first 32 bytes for first four arguments */
100 #define ARGS_OFFSET 48
102 #define ARGS_OFFSET 16
104 #define GP_SCRATCH_REG AMD64_R11
107 * AMD64 register usage:
108 * - callee saved registers are used for global register allocation
109 * - %r11 is used for materializing 64 bit constants in opcodes
110 * - the rest is used for local allocation
114 * Floating point comparison results:
124 mono_arch_regname (int reg)
127 case AMD64_RAX: return "%rax";
128 case AMD64_RBX: return "%rbx";
129 case AMD64_RCX: return "%rcx";
130 case AMD64_RDX: return "%rdx";
131 case AMD64_RSP: return "%rsp";
132 case AMD64_RBP: return "%rbp";
133 case AMD64_RDI: return "%rdi";
134 case AMD64_RSI: return "%rsi";
135 case AMD64_R8: return "%r8";
136 case AMD64_R9: return "%r9";
137 case AMD64_R10: return "%r10";
138 case AMD64_R11: return "%r11";
139 case AMD64_R12: return "%r12";
140 case AMD64_R13: return "%r13";
141 case AMD64_R14: return "%r14";
142 case AMD64_R15: return "%r15";
147 static const char * packed_xmmregs [] = {
148 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
149 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
152 static const char * single_xmmregs [] = {
153 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
154 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
158 mono_arch_fregname (int reg)
160 if (reg < AMD64_XMM_NREG)
161 return single_xmmregs [reg];
167 mono_arch_xregname (int reg)
169 if (reg < AMD64_XMM_NREG)
170 return packed_xmmregs [reg];
179 return mono_debug_count ();
185 static inline gboolean
186 amd64_is_near_call (guint8 *code)
189 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
192 return code [0] == 0xe8;
195 #ifdef __native_client_codegen__
197 /* Keep track of instruction "depth", that is, the level of sub-instruction */
198 /* for any given instruction. For instance, amd64_call_reg resolves to */
199 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
200 /* We only want to force bundle alignment for the top level instruction, */
201 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
202 static MonoNativeTlsKey nacl_instruction_depth;
204 static MonoNativeTlsKey nacl_rex_tag;
205 static MonoNativeTlsKey nacl_legacy_prefix_tag;
208 amd64_nacl_clear_legacy_prefix_tag ()
210 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
214 amd64_nacl_tag_legacy_prefix (guint8* code)
216 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
217 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
221 amd64_nacl_tag_rex (guint8* code)
223 mono_native_tls_set_value (nacl_rex_tag, code);
227 amd64_nacl_get_legacy_prefix_tag ()
229 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
233 amd64_nacl_get_rex_tag ()
235 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
238 /* Increment the instruction "depth" described above */
240 amd64_nacl_instruction_pre ()
242 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
244 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
247 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
248 /* alignment if depth == 0 (top level instruction) */
249 /* IN: start, end pointers to instruction beginning and end */
250 /* OUT: start, end pointers to beginning and end after possible alignment */
251 /* GLOBALS: nacl_instruction_depth defined above */
253 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
255 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
257 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
259 g_assert ( depth >= 0 );
261 uintptr_t space_in_block;
263 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
264 /* if legacy prefix is present, and if it was emitted before */
265 /* the start of the instruction sequence, adjust the start */
266 if (prefix != NULL && prefix < *start) {
267 g_assert (*start - prefix <= 3);/* only 3 are allowed */
270 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
271 instlen = (uintptr_t)(*end - *start);
272 /* Only check for instructions which are less than */
273 /* kNaClAlignment. The only instructions that should ever */
274 /* be that long are call sequences, which are already */
275 /* padded out to align the return to the next bundle. */
276 if (instlen > space_in_block && instlen < kNaClAlignment) {
277 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
278 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
279 const size_t length = (size_t)((*end)-(*start));
280 g_assert (length < MAX_NACL_INST_LENGTH);
282 memcpy (copy_of_instruction, *start, length);
283 *start = mono_arch_nacl_pad (*start, space_in_block);
284 memcpy (*start, copy_of_instruction, length);
285 *end = *start + length;
287 amd64_nacl_clear_legacy_prefix_tag ();
288 amd64_nacl_tag_rex (NULL);
292 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
293 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
294 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
295 /* make sure the upper 32-bits are cleared, and use that register in the */
296 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
298 /* pointer to current instruction stream (in the */
299 /* middle of an instruction, after opcode is emitted) */
300 /* basereg/offset/dreg */
301 /* operands of normal membase address */
303 /* pointer to the end of the membase/memindex emit */
304 /* GLOBALS: nacl_rex_tag */
305 /* position in instruction stream that rex prefix was emitted */
306 /* nacl_legacy_prefix_tag */
307 /* (possibly NULL) position in instruction of legacy x86 prefix */
309 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
311 gint8 true_basereg = basereg;
313 /* Cache these values, they might change */
314 /* as new instructions are emitted below. */
315 guint8* rex_tag = amd64_nacl_get_rex_tag ();
316 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
318 /* 'basereg' is given masked to 0x7 at this point, so check */
319 /* the rex prefix to see if this is an extended register. */
320 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
324 #define X86_LEA_OPCODE (0x8D)
326 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
327 guint8* old_instruction_start;
329 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
330 /* 32-bits of the old base register (new index register) */
332 guint8* buf_ptr = buf;
335 g_assert (rex_tag != NULL);
337 if (IS_REX(*rex_tag)) {
338 /* The old rex.B should be the new rex.X */
339 if (*rex_tag & AMD64_REX_B) {
340 *rex_tag |= AMD64_REX_X;
342 /* Since our new base is %r15 set rex.B */
343 *rex_tag |= AMD64_REX_B;
345 /* Shift the instruction by one byte */
346 /* so we can insert a rex prefix */
347 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
349 /* New rex prefix only needs rex.B for %r15 base */
350 *rex_tag = AMD64_REX(AMD64_REX_B);
353 if (legacy_prefix_tag) {
354 old_instruction_start = legacy_prefix_tag;
356 old_instruction_start = rex_tag;
359 /* Clears the upper 32-bits of the previous base register */
360 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
361 insert_len = buf_ptr - buf;
363 /* Move the old instruction forward to make */
364 /* room for 'mov' stored in 'buf_ptr' */
365 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
367 memcpy (old_instruction_start, buf, insert_len);
369 /* Sandboxed replacement for the normal membase_emit */
370 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
373 /* Normal default behavior, emit membase memory location */
374 x86_membase_emit_body (*code, dreg, basereg, offset);
379 static inline unsigned char*
380 amd64_skip_nops (unsigned char* code)
385 if ( code[0] == 0x90) {
389 if ( code[0] == 0x66 && code[1] == 0x90) {
393 if (code[0] == 0x0f && code[1] == 0x1f
394 && code[2] == 0x00) {
398 if (code[0] == 0x0f && code[1] == 0x1f
399 && code[2] == 0x40 && code[3] == 0x00) {
403 if (code[0] == 0x0f && code[1] == 0x1f
404 && code[2] == 0x44 && code[3] == 0x00
405 && code[4] == 0x00) {
409 if (code[0] == 0x66 && code[1] == 0x0f
410 && code[2] == 0x1f && code[3] == 0x44
411 && code[4] == 0x00 && code[5] == 0x00) {
415 if (code[0] == 0x0f && code[1] == 0x1f
416 && code[2] == 0x80 && code[3] == 0x00
417 && code[4] == 0x00 && code[5] == 0x00
418 && code[6] == 0x00) {
422 if (code[0] == 0x0f && code[1] == 0x1f
423 && code[2] == 0x84 && code[3] == 0x00
424 && code[4] == 0x00 && code[5] == 0x00
425 && code[6] == 0x00 && code[7] == 0x00) {
434 mono_arch_nacl_skip_nops (guint8* code)
436 return amd64_skip_nops(code);
439 #endif /*__native_client_codegen__*/
442 amd64_patch (unsigned char* code, gpointer target)
446 #ifdef __native_client_codegen__
447 code = amd64_skip_nops (code);
449 #if defined(__native_client_codegen__) && defined(__native_client__)
450 if (nacl_is_code_address (code)) {
451 /* For tail calls, code is patched after being installed */
452 /* but not through the normal "patch callsite" method. */
453 unsigned char buf[kNaClAlignment];
454 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
456 memcpy (buf, aligned_code, kNaClAlignment);
457 /* Patch a temp buffer of bundle size, */
458 /* then install to actual location. */
459 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
460 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
464 target = nacl_modify_patch_target (target);
468 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
473 if ((code [0] & 0xf8) == 0xb8) {
474 /* amd64_set_reg_template */
475 *(guint64*)(code + 1) = (guint64)target;
477 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
478 /* mov 0(%rip), %dreg */
479 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
481 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
482 /* call *<OFFSET>(%rip) */
483 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
485 else if (code [0] == 0xe8) {
487 gint64 disp = (guint8*)target - (guint8*)code;
488 g_assert (amd64_is_imm32 (disp));
489 x86_patch (code, (unsigned char*)target);
492 x86_patch (code, (unsigned char*)target);
496 mono_amd64_patch (unsigned char* code, gpointer target)
498 amd64_patch (code, target);
507 ArgValuetypeAddrInIReg,
508 ArgNone /* only in pair_storage */
516 /* Only if storage == ArgValuetypeInReg */
517 ArgStorage pair_storage [2];
527 gboolean need_stack_align;
528 gboolean vtype_retaddr;
529 /* The index of the vret arg in the argument list */
536 #define DEBUG(a) if (cfg->verbose_level > 1) a
541 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
543 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
547 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
549 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
553 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
555 ainfo->offset = *stack_size;
557 if (*gr >= PARAM_REGS) {
558 ainfo->storage = ArgOnStack;
559 /* Since the same stack slot size is used for all arg */
560 /* types, it needs to be big enough to hold them all */
561 (*stack_size) += sizeof(mgreg_t);
564 ainfo->storage = ArgInIReg;
565 ainfo->reg = param_regs [*gr];
571 #define FLOAT_PARAM_REGS 4
573 #define FLOAT_PARAM_REGS 8
577 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
579 ainfo->offset = *stack_size;
581 if (*gr >= FLOAT_PARAM_REGS) {
582 ainfo->storage = ArgOnStack;
583 /* Since the same stack slot size is used for both float */
584 /* types, it needs to be big enough to hold them both */
585 (*stack_size) += sizeof(mgreg_t);
588 /* A double register */
590 ainfo->storage = ArgInDoubleSSEReg;
592 ainfo->storage = ArgInFloatSSEReg;
598 typedef enum ArgumentClass {
606 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
608 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
611 ptype = mini_type_get_underlying_type (gsctx, type);
612 switch (ptype->type) {
613 case MONO_TYPE_BOOLEAN:
623 case MONO_TYPE_STRING:
624 case MONO_TYPE_OBJECT:
625 case MONO_TYPE_CLASS:
626 case MONO_TYPE_SZARRAY:
628 case MONO_TYPE_FNPTR:
629 case MONO_TYPE_ARRAY:
632 class2 = ARG_CLASS_INTEGER;
637 class2 = ARG_CLASS_INTEGER;
639 class2 = ARG_CLASS_SSE;
643 case MONO_TYPE_TYPEDBYREF:
644 g_assert_not_reached ();
646 case MONO_TYPE_GENERICINST:
647 if (!mono_type_generic_inst_is_valuetype (ptype)) {
648 class2 = ARG_CLASS_INTEGER;
652 case MONO_TYPE_VALUETYPE: {
653 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
656 for (i = 0; i < info->num_fields; ++i) {
658 class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
663 g_assert_not_reached ();
667 if (class1 == class2)
669 else if (class1 == ARG_CLASS_NO_CLASS)
671 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
672 class1 = ARG_CLASS_MEMORY;
673 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
674 class1 = ARG_CLASS_INTEGER;
676 class1 = ARG_CLASS_SSE;
680 #ifdef __native_client_codegen__
682 /* Default alignment for Native Client is 32-byte. */
683 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
685 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
686 /* Check that alignment doesn't cross an alignment boundary. */
688 mono_arch_nacl_pad(guint8 *code, int pad)
690 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
692 if (pad == 0) return code;
693 /* assertion: alignment cannot cross a block boundary */
694 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
695 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
696 while (pad >= kMaxPadding) {
697 amd64_padding (code, kMaxPadding);
700 if (pad != 0) amd64_padding (code, pad);
706 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
708 guint32 *gr, guint32 *fr, guint32 *stack_size)
710 guint32 size, quad, nquads, i;
711 /* Keep track of the size used in each quad so we can */
712 /* use the right size when copying args/return vars. */
713 guint32 quadsize [2] = {8, 8};
714 ArgumentClass args [2];
715 MonoMarshalType *info = NULL;
717 MonoGenericSharingContext tmp_gsctx;
718 gboolean pass_on_stack = FALSE;
721 * The gsctx currently contains no data, it is only used for checking whenever
722 * open types are allowed, some callers like mono_arch_get_argument_info ()
723 * don't pass it to us, so work around that.
728 klass = mono_class_from_mono_type (type);
729 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
731 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
732 /* We pass and return vtypes of size 8 in a register */
733 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
734 pass_on_stack = TRUE;
738 pass_on_stack = TRUE;
742 /* If this struct can't be split up naturally into 8-byte */
743 /* chunks (registers), pass it on the stack. */
744 if (sig->pinvoke && !pass_on_stack) {
748 info = mono_marshal_load_type_info (klass);
750 for (i = 0; i < info->num_fields; ++i) {
751 field_size = mono_marshal_type_size (info->fields [i].field->type,
752 info->fields [i].mspec,
753 &align, TRUE, klass->unicode);
754 if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
755 pass_on_stack = TRUE;
762 /* Allways pass in memory */
763 ainfo->offset = *stack_size;
764 *stack_size += ALIGN_TO (size, 8);
765 ainfo->storage = ArgOnStack;
770 /* FIXME: Handle structs smaller than 8 bytes */
771 //if ((size % 8) != 0)
780 /* Always pass in 1 or 2 integer registers */
781 args [0] = ARG_CLASS_INTEGER;
782 args [1] = ARG_CLASS_INTEGER;
783 /* Only the simplest cases are supported */
784 if (is_return && nquads != 1) {
785 args [0] = ARG_CLASS_MEMORY;
786 args [1] = ARG_CLASS_MEMORY;
790 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
791 * The X87 and SSEUP stuff is left out since there are no such types in
794 info = mono_marshal_load_type_info (klass);
798 if (info->native_size > 16) {
799 ainfo->offset = *stack_size;
800 *stack_size += ALIGN_TO (info->native_size, 8);
801 ainfo->storage = ArgOnStack;
806 switch (info->native_size) {
807 case 1: case 2: case 4: case 8:
811 ainfo->storage = ArgOnStack;
812 ainfo->offset = *stack_size;
813 *stack_size += ALIGN_TO (info->native_size, 8);
816 ainfo->storage = ArgValuetypeAddrInIReg;
818 if (*gr < PARAM_REGS) {
819 ainfo->pair_storage [0] = ArgInIReg;
820 ainfo->pair_regs [0] = param_regs [*gr];
824 ainfo->pair_storage [0] = ArgOnStack;
825 ainfo->offset = *stack_size;
834 args [0] = ARG_CLASS_NO_CLASS;
835 args [1] = ARG_CLASS_NO_CLASS;
836 for (quad = 0; quad < nquads; ++quad) {
839 ArgumentClass class1;
841 if (info->num_fields == 0)
842 class1 = ARG_CLASS_MEMORY;
844 class1 = ARG_CLASS_NO_CLASS;
845 for (i = 0; i < info->num_fields; ++i) {
846 size = mono_marshal_type_size (info->fields [i].field->type,
847 info->fields [i].mspec,
848 &align, TRUE, klass->unicode);
849 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
850 /* Unaligned field */
854 /* Skip fields in other quad */
855 if ((quad == 0) && (info->fields [i].offset >= 8))
857 if ((quad == 1) && (info->fields [i].offset < 8))
860 /* How far into this quad this data extends.*/
861 /* (8 is size of quad) */
862 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
864 class1 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class1);
866 g_assert (class1 != ARG_CLASS_NO_CLASS);
867 args [quad] = class1;
871 /* Post merger cleanup */
872 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
873 args [0] = args [1] = ARG_CLASS_MEMORY;
875 /* Allocate registers */
880 ainfo->storage = ArgValuetypeInReg;
881 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
882 ainfo->nregs = nquads;
883 for (quad = 0; quad < nquads; ++quad) {
884 switch (args [quad]) {
885 case ARG_CLASS_INTEGER:
886 if (*gr >= PARAM_REGS)
887 args [quad] = ARG_CLASS_MEMORY;
889 ainfo->pair_storage [quad] = ArgInIReg;
891 ainfo->pair_regs [quad] = return_regs [*gr];
893 ainfo->pair_regs [quad] = param_regs [*gr];
898 if (*fr >= FLOAT_PARAM_REGS)
899 args [quad] = ARG_CLASS_MEMORY;
901 if (quadsize[quad] <= 4)
902 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
903 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
904 ainfo->pair_regs [quad] = *fr;
908 case ARG_CLASS_MEMORY:
911 g_assert_not_reached ();
915 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
916 /* Revert possible register assignments */
920 ainfo->offset = *stack_size;
922 *stack_size += ALIGN_TO (info->native_size, 8);
924 *stack_size += nquads * sizeof(mgreg_t);
925 ainfo->storage = ArgOnStack;
933 * Obtain information about a call according to the calling convention.
934 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
935 * Draft Version 0.23" document for more information.
938 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
940 guint32 i, gr, fr, pstart;
942 int n = sig->hasthis + sig->param_count;
943 guint32 stack_size = 0;
945 gboolean is_pinvoke = sig->pinvoke;
948 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
950 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
959 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
960 switch (ret_type->type) {
961 case MONO_TYPE_BOOLEAN:
972 case MONO_TYPE_FNPTR:
973 case MONO_TYPE_CLASS:
974 case MONO_TYPE_OBJECT:
975 case MONO_TYPE_SZARRAY:
976 case MONO_TYPE_ARRAY:
977 case MONO_TYPE_STRING:
978 cinfo->ret.storage = ArgInIReg;
979 cinfo->ret.reg = AMD64_RAX;
983 cinfo->ret.storage = ArgInIReg;
984 cinfo->ret.reg = AMD64_RAX;
987 cinfo->ret.storage = ArgInFloatSSEReg;
988 cinfo->ret.reg = AMD64_XMM0;
991 cinfo->ret.storage = ArgInDoubleSSEReg;
992 cinfo->ret.reg = AMD64_XMM0;
994 case MONO_TYPE_GENERICINST:
995 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
996 cinfo->ret.storage = ArgInIReg;
997 cinfo->ret.reg = AMD64_RAX;
1001 #if defined( __native_client_codegen__ )
1002 case MONO_TYPE_TYPEDBYREF:
1004 case MONO_TYPE_VALUETYPE: {
1005 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1007 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1008 if (cinfo->ret.storage == ArgOnStack) {
1009 cinfo->vtype_retaddr = TRUE;
1010 /* The caller passes the address where the value is stored */
1014 #if !defined( __native_client_codegen__ )
1015 case MONO_TYPE_TYPEDBYREF:
1016 /* Same as a valuetype with size 24 */
1017 cinfo->vtype_retaddr = TRUE;
1020 case MONO_TYPE_VOID:
1023 g_error ("Can't handle as return value 0x%x", ret_type->type);
1029 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1030 * the first argument, allowing 'this' to be always passed in the first arg reg.
1031 * Also do this if the first argument is a reference type, since virtual calls
1032 * are sometimes made using calli without sig->hasthis set, like in the delegate
1035 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1037 add_general (&gr, &stack_size, cinfo->args + 0);
1039 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1042 add_general (&gr, &stack_size, &cinfo->ret);
1043 cinfo->vret_arg_index = 1;
1047 add_general (&gr, &stack_size, cinfo->args + 0);
1049 if (cinfo->vtype_retaddr)
1050 add_general (&gr, &stack_size, &cinfo->ret);
1053 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1055 fr = FLOAT_PARAM_REGS;
1057 /* Emit the signature cookie just before the implicit arguments */
1058 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1061 for (i = pstart; i < sig->param_count; ++i) {
1062 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1066 /* The float param registers and other param registers must be the same index on Windows x64.*/
1073 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1074 /* We allways pass the sig cookie on the stack for simplicity */
1076 * Prevent implicit arguments + the sig cookie from being passed
1080 fr = FLOAT_PARAM_REGS;
1082 /* Emit the signature cookie just before the implicit arguments */
1083 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1086 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1087 switch (ptype->type) {
1088 case MONO_TYPE_BOOLEAN:
1091 add_general (&gr, &stack_size, ainfo);
1095 case MONO_TYPE_CHAR:
1096 add_general (&gr, &stack_size, ainfo);
1100 add_general (&gr, &stack_size, ainfo);
1105 case MONO_TYPE_FNPTR:
1106 case MONO_TYPE_CLASS:
1107 case MONO_TYPE_OBJECT:
1108 case MONO_TYPE_STRING:
1109 case MONO_TYPE_SZARRAY:
1110 case MONO_TYPE_ARRAY:
1111 add_general (&gr, &stack_size, ainfo);
1113 case MONO_TYPE_GENERICINST:
1114 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1115 add_general (&gr, &stack_size, ainfo);
1119 case MONO_TYPE_VALUETYPE:
1120 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1122 case MONO_TYPE_TYPEDBYREF:
1123 #if defined( HOST_WIN32 ) || defined( __native_client_codegen__ )
1124 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1126 stack_size += sizeof (MonoTypedRef);
1127 ainfo->storage = ArgOnStack;
1132 add_general (&gr, &stack_size, ainfo);
1135 add_float (&fr, &stack_size, ainfo, FALSE);
1138 add_float (&fr, &stack_size, ainfo, TRUE);
1141 g_assert_not_reached ();
1145 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1147 fr = FLOAT_PARAM_REGS;
1149 /* Emit the signature cookie just before the implicit arguments */
1150 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1154 // There always is 32 bytes reserved on the stack when calling on Winx64
1158 #ifndef MONO_AMD64_NO_PUSHES
1159 if (stack_size & 0x8) {
1160 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1161 cinfo->need_stack_align = TRUE;
1166 cinfo->stack_usage = stack_size;
1167 cinfo->reg_usage = gr;
1168 cinfo->freg_usage = fr;
1173 * mono_arch_get_argument_info:
1174 * @csig: a method signature
1175 * @param_count: the number of parameters to consider
1176 * @arg_info: an array to store the result infos
1178 * Gathers information on parameters such as size, alignment and
1179 * padding. arg_info should be large enought to hold param_count + 1 entries.
1181 * Returns the size of the argument area on the stack.
1184 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1187 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1188 guint32 args_size = cinfo->stack_usage;
1190 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1191 if (csig->hasthis) {
1192 arg_info [0].offset = 0;
1195 for (k = 0; k < param_count; k++) {
1196 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1198 arg_info [k + 1].size = 0;
1207 mono_arch_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1211 MonoType *callee_ret;
1213 c1 = get_call_info (NULL, NULL, caller_sig);
1214 c2 = get_call_info (NULL, NULL, callee_sig);
1215 res = c1->stack_usage >= c2->stack_usage;
1216 callee_ret = mini_replace_type (callee_sig->ret);
1217 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1218 /* An address on the callee's stack is passed as the first argument */
1228 * Initialize the cpu to execute managed code.
1231 mono_arch_cpu_init (void)
1236 /* spec compliance requires running with double precision */
1237 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1238 fpcw &= ~X86_FPCW_PRECC_MASK;
1239 fpcw |= X86_FPCW_PREC_DOUBLE;
1240 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1241 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1243 /* TODO: This is crashing on Win64 right now.
1244 * _control87 (_PC_53, MCW_PC);
1250 * Initialize architecture specific code.
1253 mono_arch_init (void)
1257 InitializeCriticalSection (&mini_arch_mutex);
1258 #if defined(__native_client_codegen__)
1259 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1260 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1261 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1262 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1265 #ifdef MONO_ARCH_NOMAP32BIT
1266 flags = MONO_MMAP_READ;
1267 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1268 breakpoint_size = 13;
1269 breakpoint_fault_size = 3;
1271 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1272 /* amd64_mov_reg_mem () */
1273 breakpoint_size = 8;
1274 breakpoint_fault_size = 8;
1277 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1278 single_step_fault_size = 4;
1280 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1281 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1282 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1284 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1285 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1286 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1290 * Cleanup architecture specific code.
1293 mono_arch_cleanup (void)
1295 DeleteCriticalSection (&mini_arch_mutex);
1296 #if defined(__native_client_codegen__)
1297 mono_native_tls_free (nacl_instruction_depth);
1298 mono_native_tls_free (nacl_rex_tag);
1299 mono_native_tls_free (nacl_legacy_prefix_tag);
1304 * This function returns the optimizations supported on this cpu.
1307 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1313 if (mono_hwcap_x86_has_cmov) {
1314 opts |= MONO_OPT_CMOV;
1316 if (mono_hwcap_x86_has_fcmov)
1317 opts |= MONO_OPT_FCMOV;
1319 *exclude_mask |= MONO_OPT_FCMOV;
1321 *exclude_mask |= MONO_OPT_CMOV;
1328 * This function test for all SSE functions supported.
1330 * Returns a bitmask corresponding to all supported versions.
1334 mono_arch_cpu_enumerate_simd_versions (void)
1336 guint32 sse_opts = 0;
1338 if (mono_hwcap_x86_has_sse1)
1339 sse_opts |= SIMD_VERSION_SSE1;
1341 if (mono_hwcap_x86_has_sse2)
1342 sse_opts |= SIMD_VERSION_SSE2;
1344 if (mono_hwcap_x86_has_sse3)
1345 sse_opts |= SIMD_VERSION_SSE3;
1347 if (mono_hwcap_x86_has_ssse3)
1348 sse_opts |= SIMD_VERSION_SSSE3;
1350 if (mono_hwcap_x86_has_sse41)
1351 sse_opts |= SIMD_VERSION_SSE41;
1353 if (mono_hwcap_x86_has_sse42)
1354 sse_opts |= SIMD_VERSION_SSE42;
1356 if (mono_hwcap_x86_has_sse4a)
1357 sse_opts |= SIMD_VERSION_SSE4a;
1365 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1370 for (i = 0; i < cfg->num_varinfo; i++) {
1371 MonoInst *ins = cfg->varinfo [i];
1372 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1375 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1378 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1379 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1382 if (mono_is_regsize_var (ins->inst_vtype)) {
1383 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1384 g_assert (i == vmv->idx);
1385 vars = g_list_prepend (vars, vmv);
1389 vars = mono_varlist_sort (cfg, vars, 0);
1395 * mono_arch_compute_omit_fp:
1397 * Determine whenever the frame pointer can be eliminated.
1400 mono_arch_compute_omit_fp (MonoCompile *cfg)
1402 MonoMethodSignature *sig;
1403 MonoMethodHeader *header;
1407 if (cfg->arch.omit_fp_computed)
1410 header = cfg->header;
1412 sig = mono_method_signature (cfg->method);
1414 if (!cfg->arch.cinfo)
1415 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1416 cinfo = cfg->arch.cinfo;
1419 * FIXME: Remove some of the restrictions.
1421 cfg->arch.omit_fp = TRUE;
1422 cfg->arch.omit_fp_computed = TRUE;
1424 #ifdef __native_client_codegen__
1425 /* NaCl modules may not change the value of RBP, so it cannot be */
1426 /* used as a normal register, but it can be used as a frame pointer*/
1427 cfg->disable_omit_fp = TRUE;
1428 cfg->arch.omit_fp = FALSE;
1431 if (cfg->disable_omit_fp)
1432 cfg->arch.omit_fp = FALSE;
1434 if (!debug_omit_fp ())
1435 cfg->arch.omit_fp = FALSE;
1437 if (cfg->method->save_lmf)
1438 cfg->arch.omit_fp = FALSE;
1440 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1441 cfg->arch.omit_fp = FALSE;
1442 if (header->num_clauses)
1443 cfg->arch.omit_fp = FALSE;
1444 if (cfg->param_area)
1445 cfg->arch.omit_fp = FALSE;
1446 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1447 cfg->arch.omit_fp = FALSE;
1448 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1449 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1450 cfg->arch.omit_fp = FALSE;
1451 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1452 ArgInfo *ainfo = &cinfo->args [i];
1454 if (ainfo->storage == ArgOnStack) {
1456 * The stack offset can only be determined when the frame
1459 cfg->arch.omit_fp = FALSE;
1464 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1465 MonoInst *ins = cfg->varinfo [i];
1468 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1473 mono_arch_get_global_int_regs (MonoCompile *cfg)
1477 mono_arch_compute_omit_fp (cfg);
1479 if (cfg->globalra) {
1480 if (cfg->arch.omit_fp)
1481 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1483 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1484 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1485 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1486 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1487 #ifndef __native_client_codegen__
1488 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1491 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1492 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1493 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1494 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1495 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1496 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1497 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1498 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1500 if (cfg->arch.omit_fp)
1501 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1503 /* We use the callee saved registers for global allocation */
1504 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1505 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1506 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1507 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1508 #ifndef __native_client_codegen__
1509 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1512 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1513 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1521 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1526 /* All XMM registers */
1527 for (i = 0; i < 16; ++i)
1528 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1534 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1536 static GList *r = NULL;
1541 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1542 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1543 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1544 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1545 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1546 #ifndef __native_client_codegen__
1547 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1550 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1551 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1552 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1553 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1554 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1555 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1556 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1557 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1559 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1566 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1569 static GList *r = NULL;
1574 for (i = 0; i < AMD64_XMM_NREG; ++i)
1575 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1577 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1584 * mono_arch_regalloc_cost:
1586 * Return the cost, in number of memory references, of the action of
1587 * allocating the variable VMV into a register during global register
1591 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1593 MonoInst *ins = cfg->varinfo [vmv->idx];
1595 if (cfg->method->save_lmf)
1596 /* The register is already saved */
1597 /* substract 1 for the invisible store in the prolog */
1598 return (ins->opcode == OP_ARG) ? 0 : 1;
1601 return (ins->opcode == OP_ARG) ? 1 : 2;
1605 * mono_arch_fill_argument_info:
1607 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1611 mono_arch_fill_argument_info (MonoCompile *cfg)
1614 MonoMethodSignature *sig;
1615 MonoMethodHeader *header;
1620 header = cfg->header;
1622 sig = mono_method_signature (cfg->method);
1624 cinfo = cfg->arch.cinfo;
1625 sig_ret = mini_replace_type (sig->ret);
1628 * Contrary to mono_arch_allocate_vars (), the information should describe
1629 * where the arguments are at the beginning of the method, not where they can be
1630 * accessed during the execution of the method. The later makes no sense for the
1631 * global register allocator, since a variable can be in more than one location.
1633 if (sig_ret->type != MONO_TYPE_VOID) {
1634 switch (cinfo->ret.storage) {
1636 case ArgInFloatSSEReg:
1637 case ArgInDoubleSSEReg:
1638 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1639 cfg->vret_addr->opcode = OP_REGVAR;
1640 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1643 cfg->ret->opcode = OP_REGVAR;
1644 cfg->ret->inst_c0 = cinfo->ret.reg;
1647 case ArgValuetypeInReg:
1648 cfg->ret->opcode = OP_REGOFFSET;
1649 cfg->ret->inst_basereg = -1;
1650 cfg->ret->inst_offset = -1;
1653 g_assert_not_reached ();
1657 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1658 ArgInfo *ainfo = &cinfo->args [i];
1661 ins = cfg->args [i];
1663 if (sig->hasthis && (i == 0))
1664 arg_type = &mono_defaults.object_class->byval_arg;
1666 arg_type = sig->params [i - sig->hasthis];
1668 switch (ainfo->storage) {
1670 case ArgInFloatSSEReg:
1671 case ArgInDoubleSSEReg:
1672 ins->opcode = OP_REGVAR;
1673 ins->inst_c0 = ainfo->reg;
1676 ins->opcode = OP_REGOFFSET;
1677 ins->inst_basereg = -1;
1678 ins->inst_offset = -1;
1680 case ArgValuetypeInReg:
1682 ins->opcode = OP_NOP;
1685 g_assert_not_reached ();
1691 mono_arch_allocate_vars (MonoCompile *cfg)
1694 MonoMethodSignature *sig;
1695 MonoMethodHeader *header;
1698 guint32 locals_stack_size, locals_stack_align;
1702 header = cfg->header;
1704 sig = mono_method_signature (cfg->method);
1706 cinfo = cfg->arch.cinfo;
1707 sig_ret = mini_replace_type (sig->ret);
1709 mono_arch_compute_omit_fp (cfg);
1712 * We use the ABI calling conventions for managed code as well.
1713 * Exception: valuetypes are only sometimes passed or returned in registers.
1717 * The stack looks like this:
1718 * <incoming arguments passed on the stack>
1720 * <lmf/caller saved registers>
1723 * <localloc area> -> grows dynamically
1727 if (cfg->arch.omit_fp) {
1728 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1729 cfg->frame_reg = AMD64_RSP;
1732 /* Locals are allocated backwards from %fp */
1733 cfg->frame_reg = AMD64_RBP;
1737 if (cfg->method->save_lmf) {
1738 /* The LMF var is allocated normally */
1740 if (cfg->arch.omit_fp)
1741 cfg->arch.reg_save_area_offset = offset;
1742 /* Reserve space for callee saved registers */
1743 for (i = 0; i < AMD64_NREG; ++i)
1744 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1745 offset += sizeof(mgreg_t);
1747 if (!cfg->arch.omit_fp)
1748 cfg->arch.reg_save_area_offset = -offset;
1751 if (sig_ret->type != MONO_TYPE_VOID) {
1752 switch (cinfo->ret.storage) {
1754 case ArgInFloatSSEReg:
1755 case ArgInDoubleSSEReg:
1756 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1757 if (cfg->globalra) {
1758 cfg->vret_addr->opcode = OP_REGVAR;
1759 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1761 /* The register is volatile */
1762 cfg->vret_addr->opcode = OP_REGOFFSET;
1763 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1764 if (cfg->arch.omit_fp) {
1765 cfg->vret_addr->inst_offset = offset;
1769 cfg->vret_addr->inst_offset = -offset;
1771 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1772 printf ("vret_addr =");
1773 mono_print_ins (cfg->vret_addr);
1778 cfg->ret->opcode = OP_REGVAR;
1779 cfg->ret->inst_c0 = cinfo->ret.reg;
1782 case ArgValuetypeInReg:
1783 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1784 cfg->ret->opcode = OP_REGOFFSET;
1785 cfg->ret->inst_basereg = cfg->frame_reg;
1786 if (cfg->arch.omit_fp) {
1787 cfg->ret->inst_offset = offset;
1788 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1790 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1791 cfg->ret->inst_offset = - offset;
1795 g_assert_not_reached ();
1798 cfg->ret->dreg = cfg->ret->inst_c0;
1801 /* Allocate locals */
1802 if (!cfg->globalra) {
1803 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1804 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1805 char *mname = mono_method_full_name (cfg->method, TRUE);
1806 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1807 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1812 if (locals_stack_align) {
1813 offset += (locals_stack_align - 1);
1814 offset &= ~(locals_stack_align - 1);
1816 if (cfg->arch.omit_fp) {
1817 cfg->locals_min_stack_offset = offset;
1818 cfg->locals_max_stack_offset = offset + locals_stack_size;
1820 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1821 cfg->locals_max_stack_offset = - offset;
1824 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1825 if (offsets [i] != -1) {
1826 MonoInst *ins = cfg->varinfo [i];
1827 ins->opcode = OP_REGOFFSET;
1828 ins->inst_basereg = cfg->frame_reg;
1829 if (cfg->arch.omit_fp)
1830 ins->inst_offset = (offset + offsets [i]);
1832 ins->inst_offset = - (offset + offsets [i]);
1833 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1836 offset += locals_stack_size;
1839 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1840 g_assert (!cfg->arch.omit_fp);
1841 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1842 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1845 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1846 ins = cfg->args [i];
1847 if (ins->opcode != OP_REGVAR) {
1848 ArgInfo *ainfo = &cinfo->args [i];
1849 gboolean inreg = TRUE;
1852 if (sig->hasthis && (i == 0))
1853 arg_type = &mono_defaults.object_class->byval_arg;
1855 arg_type = sig->params [i - sig->hasthis];
1857 if (cfg->globalra) {
1858 /* The new allocator needs info about the original locations of the arguments */
1859 switch (ainfo->storage) {
1861 case ArgInFloatSSEReg:
1862 case ArgInDoubleSSEReg:
1863 ins->opcode = OP_REGVAR;
1864 ins->inst_c0 = ainfo->reg;
1867 g_assert (!cfg->arch.omit_fp);
1868 ins->opcode = OP_REGOFFSET;
1869 ins->inst_basereg = cfg->frame_reg;
1870 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1872 case ArgValuetypeInReg:
1873 ins->opcode = OP_REGOFFSET;
1874 ins->inst_basereg = cfg->frame_reg;
1875 /* These arguments are saved to the stack in the prolog */
1876 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1877 if (cfg->arch.omit_fp) {
1878 ins->inst_offset = offset;
1879 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1881 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1882 ins->inst_offset = - offset;
1886 g_assert_not_reached ();
1892 /* FIXME: Allocate volatile arguments to registers */
1893 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1897 * Under AMD64, all registers used to pass arguments to functions
1898 * are volatile across calls.
1899 * FIXME: Optimize this.
1901 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1904 ins->opcode = OP_REGOFFSET;
1906 switch (ainfo->storage) {
1908 case ArgInFloatSSEReg:
1909 case ArgInDoubleSSEReg:
1911 ins->opcode = OP_REGVAR;
1912 ins->dreg = ainfo->reg;
1916 g_assert (!cfg->arch.omit_fp);
1917 ins->opcode = OP_REGOFFSET;
1918 ins->inst_basereg = cfg->frame_reg;
1919 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1921 case ArgValuetypeInReg:
1923 case ArgValuetypeAddrInIReg: {
1925 g_assert (!cfg->arch.omit_fp);
1927 MONO_INST_NEW (cfg, indir, 0);
1928 indir->opcode = OP_REGOFFSET;
1929 if (ainfo->pair_storage [0] == ArgInIReg) {
1930 indir->inst_basereg = cfg->frame_reg;
1931 offset = ALIGN_TO (offset, sizeof (gpointer));
1932 offset += (sizeof (gpointer));
1933 indir->inst_offset = - offset;
1936 indir->inst_basereg = cfg->frame_reg;
1937 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1940 ins->opcode = OP_VTARG_ADDR;
1941 ins->inst_left = indir;
1949 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1950 ins->opcode = OP_REGOFFSET;
1951 ins->inst_basereg = cfg->frame_reg;
1952 /* These arguments are saved to the stack in the prolog */
1953 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1954 if (cfg->arch.omit_fp) {
1955 ins->inst_offset = offset;
1956 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1957 // Arguments are yet supported by the stack map creation code
1958 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1960 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1961 ins->inst_offset = - offset;
1962 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1968 cfg->stack_offset = offset;
1972 mono_arch_create_vars (MonoCompile *cfg)
1974 MonoMethodSignature *sig;
1978 sig = mono_method_signature (cfg->method);
1980 if (!cfg->arch.cinfo)
1981 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1982 cinfo = cfg->arch.cinfo;
1984 if (cinfo->ret.storage == ArgValuetypeInReg)
1985 cfg->ret_var_is_local = TRUE;
1987 sig_ret = mini_replace_type (sig->ret);
1988 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1989 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1990 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1991 printf ("vret_addr = ");
1992 mono_print_ins (cfg->vret_addr);
1996 if (cfg->gen_seq_points) {
1999 if (cfg->compile_aot) {
2000 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2001 ins->flags |= MONO_INST_VOLATILE;
2002 cfg->arch.seq_point_info_var = ins;
2005 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2006 ins->flags |= MONO_INST_VOLATILE;
2007 cfg->arch.ss_trigger_page_var = ins;
2010 #ifdef MONO_AMD64_NO_PUSHES
2012 * When this is set, we pass arguments on the stack by moves, and by allocating
2013 * a bigger stack frame, instead of pushes.
2014 * Pushes complicate exception handling because the arguments on the stack have
2015 * to be popped each time a frame is unwound. They also make fp elimination
2017 * FIXME: This doesn't work inside filter/finally clauses, since those execute
2018 * on a new frame which doesn't include a param area.
2020 cfg->arch.no_pushes = TRUE;
2023 if (cfg->method->save_lmf)
2024 cfg->create_lmf_var = TRUE;
2026 #if !defined(HOST_WIN32)
2027 if (cfg->method->save_lmf) {
2029 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2030 cfg->lmf_ir_mono_lmf = TRUE;
2034 #ifndef MONO_AMD64_NO_PUSHES
2035 cfg->arch_eh_jit_info = 1;
2040 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2046 MONO_INST_NEW (cfg, ins, OP_MOVE);
2047 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2048 ins->sreg1 = tree->dreg;
2049 MONO_ADD_INS (cfg->cbb, ins);
2050 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2052 case ArgInFloatSSEReg:
2053 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2054 ins->dreg = mono_alloc_freg (cfg);
2055 ins->sreg1 = tree->dreg;
2056 MONO_ADD_INS (cfg->cbb, ins);
2058 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2060 case ArgInDoubleSSEReg:
2061 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2062 ins->dreg = mono_alloc_freg (cfg);
2063 ins->sreg1 = tree->dreg;
2064 MONO_ADD_INS (cfg->cbb, ins);
2066 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2070 g_assert_not_reached ();
2075 arg_storage_to_load_membase (ArgStorage storage)
2079 #if defined(__mono_ilp32__)
2080 return OP_LOADI8_MEMBASE;
2082 return OP_LOAD_MEMBASE;
2084 case ArgInDoubleSSEReg:
2085 return OP_LOADR8_MEMBASE;
2086 case ArgInFloatSSEReg:
2087 return OP_LOADR4_MEMBASE;
2089 g_assert_not_reached ();
2096 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2099 MonoMethodSignature *tmp_sig;
2102 if (call->tail_call)
2105 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2108 * mono_ArgIterator_Setup assumes the signature cookie is
2109 * passed first and all the arguments which were before it are
2110 * passed on the stack after the signature. So compensate by
2111 * passing a different signature.
2113 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2114 tmp_sig->param_count -= call->signature->sentinelpos;
2115 tmp_sig->sentinelpos = 0;
2116 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2118 sig_reg = mono_alloc_ireg (cfg);
2119 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2121 if (cfg->arch.no_pushes) {
2122 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2124 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2125 arg->sreg1 = sig_reg;
2126 MONO_ADD_INS (cfg->cbb, arg);
2130 static inline LLVMArgStorage
2131 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2135 return LLVMArgInIReg;
2139 g_assert_not_reached ();
2146 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2152 LLVMCallInfo *linfo;
2153 MonoType *t, *sig_ret;
2155 n = sig->param_count + sig->hasthis;
2156 sig_ret = mini_replace_type (sig->ret);
2158 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2160 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2163 * LLVM always uses the native ABI while we use our own ABI, the
2164 * only difference is the handling of vtypes:
2165 * - we only pass/receive them in registers in some cases, and only
2166 * in 1 or 2 integer registers.
2168 if (cinfo->ret.storage == ArgValuetypeInReg) {
2170 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2171 cfg->disable_llvm = TRUE;
2175 linfo->ret.storage = LLVMArgVtypeInReg;
2176 for (j = 0; j < 2; ++j)
2177 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2180 if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2181 /* Vtype returned using a hidden argument */
2182 linfo->ret.storage = LLVMArgVtypeRetAddr;
2183 linfo->vret_arg_index = cinfo->vret_arg_index;
2186 for (i = 0; i < n; ++i) {
2187 ainfo = cinfo->args + i;
2189 if (i >= sig->hasthis)
2190 t = sig->params [i - sig->hasthis];
2192 t = &mono_defaults.int_class->byval_arg;
2194 linfo->args [i].storage = LLVMArgNone;
2196 switch (ainfo->storage) {
2198 linfo->args [i].storage = LLVMArgInIReg;
2200 case ArgInDoubleSSEReg:
2201 case ArgInFloatSSEReg:
2202 linfo->args [i].storage = LLVMArgInFPReg;
2205 if (MONO_TYPE_ISSTRUCT (t)) {
2206 linfo->args [i].storage = LLVMArgVtypeByVal;
2208 linfo->args [i].storage = LLVMArgInIReg;
2210 if (t->type == MONO_TYPE_R4)
2211 linfo->args [i].storage = LLVMArgInFPReg;
2212 else if (t->type == MONO_TYPE_R8)
2213 linfo->args [i].storage = LLVMArgInFPReg;
2217 case ArgValuetypeInReg:
2219 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2220 cfg->disable_llvm = TRUE;
2224 linfo->args [i].storage = LLVMArgVtypeInReg;
2225 for (j = 0; j < 2; ++j)
2226 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2229 cfg->exception_message = g_strdup ("ainfo->storage");
2230 cfg->disable_llvm = TRUE;
2240 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2243 MonoMethodSignature *sig;
2245 int i, n, stack_size;
2251 sig = call->signature;
2252 n = sig->param_count + sig->hasthis;
2254 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2258 if (COMPILE_LLVM (cfg)) {
2259 /* We shouldn't be called in the llvm case */
2260 cfg->disable_llvm = TRUE;
2264 if (cinfo->need_stack_align) {
2265 if (!cfg->arch.no_pushes)
2266 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2270 * Emit all arguments which are passed on the stack to prevent register
2271 * allocation problems.
2273 if (cfg->arch.no_pushes) {
2274 for (i = 0; i < n; ++i) {
2276 ainfo = cinfo->args + i;
2278 in = call->args [i];
2280 if (sig->hasthis && i == 0)
2281 t = &mono_defaults.object_class->byval_arg;
2283 t = sig->params [i - sig->hasthis];
2285 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2287 if (t->type == MONO_TYPE_R4)
2288 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2289 else if (t->type == MONO_TYPE_R8)
2290 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2292 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2294 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2296 if (cfg->compute_gc_maps) {
2299 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2306 * Emit all parameters passed in registers in non-reverse order for better readability
2307 * and to help the optimization in emit_prolog ().
2309 for (i = 0; i < n; ++i) {
2310 ainfo = cinfo->args + i;
2312 in = call->args [i];
2314 if (ainfo->storage == ArgInIReg)
2315 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2318 for (i = n - 1; i >= 0; --i) {
2319 ainfo = cinfo->args + i;
2321 in = call->args [i];
2323 switch (ainfo->storage) {
2327 case ArgInFloatSSEReg:
2328 case ArgInDoubleSSEReg:
2329 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2332 case ArgValuetypeInReg:
2333 case ArgValuetypeAddrInIReg:
2334 if (ainfo->storage == ArgOnStack && call->tail_call) {
2335 MonoInst *call_inst = (MonoInst*)call;
2336 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2337 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2338 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2342 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2343 size = sizeof (MonoTypedRef);
2344 align = sizeof (gpointer);
2348 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2351 * Other backends use mono_type_stack_size (), but that
2352 * aligns the size to 8, which is larger than the size of
2353 * the source, leading to reads of invalid memory if the
2354 * source is at the end of address space.
2356 size = mono_class_value_size (in->klass, &align);
2359 g_assert (in->klass);
2361 if (ainfo->storage == ArgOnStack && size >= 10000) {
2362 /* Avoid asserts in emit_memcpy () */
2363 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2364 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2365 /* Continue normally */
2369 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2370 arg->sreg1 = in->dreg;
2371 arg->klass = in->klass;
2372 arg->backend.size = size;
2373 arg->inst_p0 = call;
2374 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2375 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2377 MONO_ADD_INS (cfg->cbb, arg);
2380 if (cfg->arch.no_pushes) {
2383 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2384 arg->sreg1 = in->dreg;
2385 if (!sig->params [i - sig->hasthis]->byref) {
2386 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2387 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2388 arg->opcode = OP_STORER4_MEMBASE_REG;
2389 arg->inst_destbasereg = X86_ESP;
2390 arg->inst_offset = 0;
2391 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2392 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2393 arg->opcode = OP_STORER8_MEMBASE_REG;
2394 arg->inst_destbasereg = X86_ESP;
2395 arg->inst_offset = 0;
2398 MONO_ADD_INS (cfg->cbb, arg);
2403 g_assert_not_reached ();
2406 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2407 /* Emit the signature cookie just before the implicit arguments */
2408 emit_sig_cookie (cfg, call, cinfo);
2411 /* Handle the case where there are no implicit arguments */
2412 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2413 emit_sig_cookie (cfg, call, cinfo);
2415 sig_ret = mini_replace_type (sig->ret);
2416 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2419 if (cinfo->ret.storage == ArgValuetypeInReg) {
2420 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2422 * Tell the JIT to use a more efficient calling convention: call using
2423 * OP_CALL, compute the result location after the call, and save the
2426 call->vret_in_reg = TRUE;
2428 * Nullify the instruction computing the vret addr to enable
2429 * future optimizations.
2432 NULLIFY_INS (call->vret_var);
2434 if (call->tail_call)
2437 * The valuetype is in RAX:RDX after the call, need to be copied to
2438 * the stack. Push the address here, so the call instruction can
2441 if (!cfg->arch.vret_addr_loc) {
2442 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2443 /* Prevent it from being register allocated or optimized away */
2444 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2447 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2451 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2452 vtarg->sreg1 = call->vret_var->dreg;
2453 vtarg->dreg = mono_alloc_preg (cfg);
2454 MONO_ADD_INS (cfg->cbb, vtarg);
2456 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2461 if (call->inst.opcode != OP_TAILCALL) {
2462 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2466 if (cfg->method->save_lmf) {
2467 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2468 MONO_ADD_INS (cfg->cbb, arg);
2471 call->stack_usage = cinfo->stack_usage;
2475 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2478 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2479 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2480 int size = ins->backend.size;
2482 if (ainfo->storage == ArgValuetypeInReg) {
2486 for (part = 0; part < 2; ++part) {
2487 if (ainfo->pair_storage [part] == ArgNone)
2490 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2491 load->inst_basereg = src->dreg;
2492 load->inst_offset = part * sizeof(mgreg_t);
2494 switch (ainfo->pair_storage [part]) {
2496 load->dreg = mono_alloc_ireg (cfg);
2498 case ArgInDoubleSSEReg:
2499 case ArgInFloatSSEReg:
2500 load->dreg = mono_alloc_freg (cfg);
2503 g_assert_not_reached ();
2505 MONO_ADD_INS (cfg->cbb, load);
2507 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2509 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2510 MonoInst *vtaddr, *load;
2511 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2513 g_assert (!cfg->arch.no_pushes);
2515 MONO_INST_NEW (cfg, load, OP_LDADDR);
2516 cfg->has_indirection = TRUE;
2517 load->inst_p0 = vtaddr;
2518 vtaddr->flags |= MONO_INST_INDIRECT;
2519 load->type = STACK_MP;
2520 load->klass = vtaddr->klass;
2521 load->dreg = mono_alloc_ireg (cfg);
2522 MONO_ADD_INS (cfg->cbb, load);
2523 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2525 if (ainfo->pair_storage [0] == ArgInIReg) {
2526 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2527 arg->dreg = mono_alloc_ireg (cfg);
2528 arg->sreg1 = load->dreg;
2530 MONO_ADD_INS (cfg->cbb, arg);
2531 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2533 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2534 arg->sreg1 = load->dreg;
2535 MONO_ADD_INS (cfg->cbb, arg);
2539 if (cfg->arch.no_pushes) {
2540 int dreg = mono_alloc_ireg (cfg);
2542 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2545 /* Can't use this for < 8 since it does an 8 byte memory load */
2546 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2547 arg->inst_basereg = src->dreg;
2548 arg->inst_offset = 0;
2549 MONO_ADD_INS (cfg->cbb, arg);
2551 } else if (size <= 40) {
2552 if (cfg->arch.no_pushes) {
2553 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2555 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2556 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2559 if (cfg->arch.no_pushes) {
2560 // FIXME: Code growth
2561 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2563 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2564 arg->inst_basereg = src->dreg;
2565 arg->inst_offset = 0;
2566 arg->inst_imm = size;
2567 MONO_ADD_INS (cfg->cbb, arg);
2571 if (cfg->compute_gc_maps) {
2573 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2579 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2581 MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2583 if (ret->type == MONO_TYPE_R4) {
2584 if (COMPILE_LLVM (cfg))
2585 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2587 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2589 } else if (ret->type == MONO_TYPE_R8) {
2590 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2594 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2597 #endif /* DISABLE_JIT */
2599 #define EMIT_COND_BRANCH(ins,cond,sign) \
2600 if (ins->inst_true_bb->native_offset) { \
2601 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2603 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2604 if ((cfg->opt & MONO_OPT_BRANCH) && \
2605 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2606 x86_branch8 (code, cond, 0, sign); \
2608 x86_branch32 (code, cond, 0, sign); \
2612 MonoMethodSignature *sig;
2617 mgreg_t regs [PARAM_REGS];
2623 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2631 switch (cinfo->ret.storage) {
2635 case ArgValuetypeInReg: {
2636 ArgInfo *ainfo = &cinfo->ret;
2638 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2640 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2648 for (i = 0; i < cinfo->nargs; ++i) {
2649 ArgInfo *ainfo = &cinfo->args [i];
2650 switch (ainfo->storage) {
2653 case ArgValuetypeInReg:
2654 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2656 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2668 * mono_arch_dyn_call_prepare:
2670 * Return a pointer to an arch-specific structure which contains information
2671 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2672 * supported for SIG.
2673 * This function is equivalent to ffi_prep_cif in libffi.
2676 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2678 ArchDynCallInfo *info;
2681 cinfo = get_call_info (NULL, NULL, sig);
2683 if (!dyn_call_supported (sig, cinfo)) {
2688 info = g_new0 (ArchDynCallInfo, 1);
2689 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2691 info->cinfo = cinfo;
2693 return (MonoDynCallInfo*)info;
2697 * mono_arch_dyn_call_free:
2699 * Free a MonoDynCallInfo structure.
2702 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2704 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2706 g_free (ainfo->cinfo);
2710 #if !defined(__native_client__)
2711 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2712 #define GREG_TO_PTR(greg) (gpointer)(greg)
2714 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2715 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2716 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2720 * mono_arch_get_start_dyn_call:
2722 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2723 * store the result into BUF.
2724 * ARGS should be an array of pointers pointing to the arguments.
2725 * RET should point to a memory buffer large enought to hold the result of the
2727 * This function should be as fast as possible, any work which does not depend
2728 * on the actual values of the arguments should be done in
2729 * mono_arch_dyn_call_prepare ().
2730 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2734 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2736 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2737 DynCallArgs *p = (DynCallArgs*)buf;
2738 int arg_index, greg, i, pindex;
2739 MonoMethodSignature *sig = dinfo->sig;
2741 g_assert (buf_len >= sizeof (DynCallArgs));
2750 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2751 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2756 if (dinfo->cinfo->vtype_retaddr)
2757 p->regs [greg ++] = PTR_TO_GREG(ret);
2759 for (i = pindex; i < sig->param_count; i++) {
2760 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2761 gpointer *arg = args [arg_index ++];
2764 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2769 case MONO_TYPE_STRING:
2770 case MONO_TYPE_CLASS:
2771 case MONO_TYPE_ARRAY:
2772 case MONO_TYPE_SZARRAY:
2773 case MONO_TYPE_OBJECT:
2777 #if !defined(__mono_ilp32__)
2781 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2782 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2784 #if defined(__mono_ilp32__)
2787 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2788 p->regs [greg ++] = *(guint64*)(arg);
2791 case MONO_TYPE_BOOLEAN:
2793 p->regs [greg ++] = *(guint8*)(arg);
2796 p->regs [greg ++] = *(gint8*)(arg);
2799 p->regs [greg ++] = *(gint16*)(arg);
2802 case MONO_TYPE_CHAR:
2803 p->regs [greg ++] = *(guint16*)(arg);
2806 p->regs [greg ++] = *(gint32*)(arg);
2809 p->regs [greg ++] = *(guint32*)(arg);
2811 case MONO_TYPE_GENERICINST:
2812 if (MONO_TYPE_IS_REFERENCE (t)) {
2813 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2818 case MONO_TYPE_VALUETYPE: {
2819 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2821 g_assert (ainfo->storage == ArgValuetypeInReg);
2822 if (ainfo->pair_storage [0] != ArgNone) {
2823 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2824 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2826 if (ainfo->pair_storage [1] != ArgNone) {
2827 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2828 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2833 g_assert_not_reached ();
2837 g_assert (greg <= PARAM_REGS);
2841 * mono_arch_finish_dyn_call:
2843 * Store the result of a dyn call into the return value buffer passed to
2844 * start_dyn_call ().
2845 * This function should be as fast as possible, any work which does not depend
2846 * on the actual values of the arguments should be done in
2847 * mono_arch_dyn_call_prepare ().
2850 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2852 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2853 MonoMethodSignature *sig = dinfo->sig;
2854 guint8 *ret = ((DynCallArgs*)buf)->ret;
2855 mgreg_t res = ((DynCallArgs*)buf)->res;
2856 MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2858 switch (sig_ret->type) {
2859 case MONO_TYPE_VOID:
2860 *(gpointer*)ret = NULL;
2862 case MONO_TYPE_STRING:
2863 case MONO_TYPE_CLASS:
2864 case MONO_TYPE_ARRAY:
2865 case MONO_TYPE_SZARRAY:
2866 case MONO_TYPE_OBJECT:
2870 *(gpointer*)ret = GREG_TO_PTR(res);
2876 case MONO_TYPE_BOOLEAN:
2877 *(guint8*)ret = res;
2880 *(gint16*)ret = res;
2883 case MONO_TYPE_CHAR:
2884 *(guint16*)ret = res;
2887 *(gint32*)ret = res;
2890 *(guint32*)ret = res;
2893 *(gint64*)ret = res;
2896 *(guint64*)ret = res;
2898 case MONO_TYPE_GENERICINST:
2899 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2900 *(gpointer*)ret = GREG_TO_PTR(res);
2905 case MONO_TYPE_VALUETYPE:
2906 if (dinfo->cinfo->vtype_retaddr) {
2909 ArgInfo *ainfo = &dinfo->cinfo->ret;
2911 g_assert (ainfo->storage == ArgValuetypeInReg);
2913 if (ainfo->pair_storage [0] != ArgNone) {
2914 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2915 ((mgreg_t*)ret)[0] = res;
2918 g_assert (ainfo->pair_storage [1] == ArgNone);
2922 g_assert_not_reached ();
2926 /* emit an exception if condition is fail */
2927 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2929 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2930 if (tins == NULL) { \
2931 mono_add_patch_info (cfg, code - cfg->native_code, \
2932 MONO_PATCH_INFO_EXC, exc_name); \
2933 x86_branch32 (code, cond, 0, signed); \
2935 EMIT_COND_BRANCH (tins, cond, signed); \
2939 #define EMIT_FPCOMPARE(code) do { \
2940 amd64_fcompp (code); \
2941 amd64_fnstsw (code); \
2944 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2945 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2946 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2947 amd64_ ##op (code); \
2948 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2949 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2953 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2955 gboolean no_patch = FALSE;
2958 * FIXME: Add support for thunks
2961 gboolean near_call = FALSE;
2964 * Indirect calls are expensive so try to make a near call if possible.
2965 * The caller memory is allocated by the code manager so it is
2966 * guaranteed to be at a 32 bit offset.
2969 if (patch_type != MONO_PATCH_INFO_ABS) {
2970 /* The target is in memory allocated using the code manager */
2973 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2974 if (((MonoMethod*)data)->klass->image->aot_module)
2975 /* The callee might be an AOT method */
2977 if (((MonoMethod*)data)->dynamic)
2978 /* The target is in malloc-ed memory */
2982 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2984 * The call might go directly to a native function without
2987 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2989 gconstpointer target = mono_icall_get_wrapper (mi);
2990 if ((((guint64)target) >> 32) != 0)
2996 MonoJumpInfo *jinfo = NULL;
2998 if (cfg->abs_patches)
2999 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
3001 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3002 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3003 if (mi && (((guint64)mi->func) >> 32) == 0)
3008 * This is not really an optimization, but required because the
3009 * generic class init trampolines use R11 to pass the vtable.
3014 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3016 if (info->func == info->wrapper) {
3018 if ((((guint64)info->func) >> 32) == 0)
3022 /* See the comment in mono_codegen () */
3023 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3027 else if ((((guint64)data) >> 32) == 0) {
3034 if (cfg->method->dynamic)
3035 /* These methods are allocated using malloc */
3038 #ifdef MONO_ARCH_NOMAP32BIT
3041 #if defined(__native_client__)
3042 /* Always use near_call == TRUE for Native Client */
3045 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3046 if (optimize_for_xen)
3049 if (cfg->compile_aot) {
3056 * Align the call displacement to an address divisible by 4 so it does
3057 * not span cache lines. This is required for code patching to work on SMP
3060 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3061 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3062 amd64_padding (code, pad_size);
3064 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3065 amd64_call_code (code, 0);
3068 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3069 amd64_set_reg_template (code, GP_SCRATCH_REG);
3070 amd64_call_reg (code, GP_SCRATCH_REG);
3077 static inline guint8*
3078 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3081 if (win64_adjust_stack)
3082 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3084 code = emit_call_body (cfg, code, patch_type, data);
3086 if (win64_adjust_stack)
3087 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3094 store_membase_imm_to_store_membase_reg (int opcode)
3097 case OP_STORE_MEMBASE_IMM:
3098 return OP_STORE_MEMBASE_REG;
3099 case OP_STOREI4_MEMBASE_IMM:
3100 return OP_STOREI4_MEMBASE_REG;
3101 case OP_STOREI8_MEMBASE_IMM:
3102 return OP_STOREI8_MEMBASE_REG;
3110 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3113 * mono_arch_peephole_pass_1:
3115 * Perform peephole opts which should/can be performed before local regalloc
3118 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3122 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3123 MonoInst *last_ins = ins->prev;
3125 switch (ins->opcode) {
3129 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3131 * X86_LEA is like ADD, but doesn't have the
3132 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3133 * its operand to 64 bit.
3135 ins->opcode = OP_X86_LEA_MEMBASE;
3136 ins->inst_basereg = ins->sreg1;
3141 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3145 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3146 * the latter has length 2-3 instead of 6 (reverse constant
3147 * propagation). These instruction sequences are very common
3148 * in the initlocals bblock.
3150 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3151 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3152 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3153 ins2->sreg1 = ins->dreg;
3154 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3156 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3165 case OP_COMPARE_IMM:
3166 case OP_LCOMPARE_IMM:
3167 /* OP_COMPARE_IMM (reg, 0)
3169 * OP_AMD64_TEST_NULL (reg)
3172 ins->opcode = OP_AMD64_TEST_NULL;
3174 case OP_ICOMPARE_IMM:
3176 ins->opcode = OP_X86_TEST_NULL;
3178 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3180 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3181 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3183 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3184 * OP_COMPARE_IMM reg, imm
3186 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3188 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3189 ins->inst_basereg == last_ins->inst_destbasereg &&
3190 ins->inst_offset == last_ins->inst_offset) {
3191 ins->opcode = OP_ICOMPARE_IMM;
3192 ins->sreg1 = last_ins->sreg1;
3194 /* check if we can remove cmp reg,0 with test null */
3196 ins->opcode = OP_X86_TEST_NULL;
3202 mono_peephole_ins (bb, ins);
3207 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3211 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3212 switch (ins->opcode) {
3215 /* reg = 0 -> XOR (reg, reg) */
3216 /* XOR sets cflags on x86, so we cant do it always */
3217 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3218 ins->opcode = OP_LXOR;
3219 ins->sreg1 = ins->dreg;
3220 ins->sreg2 = ins->dreg;
3228 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3229 * 0 result into 64 bits.
3231 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3232 ins->opcode = OP_IXOR;
3236 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3240 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3241 * the latter has length 2-3 instead of 6 (reverse constant
3242 * propagation). These instruction sequences are very common
3243 * in the initlocals bblock.
3245 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3246 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3247 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3248 ins2->sreg1 = ins->dreg;
3249 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3251 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3261 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3262 ins->opcode = OP_X86_INC_REG;
3265 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3266 ins->opcode = OP_X86_DEC_REG;
3270 mono_peephole_ins (bb, ins);
3274 #define NEW_INS(cfg,ins,dest,op) do { \
3275 MONO_INST_NEW ((cfg), (dest), (op)); \
3276 (dest)->cil_code = (ins)->cil_code; \
3277 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3281 * mono_arch_lowering_pass:
3283 * Converts complex opcodes into simpler ones so that each IR instruction
3284 * corresponds to one machine instruction.
3287 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3289 MonoInst *ins, *n, *temp;
3292 * FIXME: Need to add more instructions, but the current machine
3293 * description can't model some parts of the composite instructions like
3296 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3297 switch (ins->opcode) {
3301 case OP_IDIV_UN_IMM:
3302 case OP_IREM_UN_IMM:
3303 mono_decompose_op_imm (cfg, bb, ins);
3306 /* Keep the opcode if we can implement it efficiently */
3307 if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
3308 mono_decompose_op_imm (cfg, bb, ins);
3310 case OP_COMPARE_IMM:
3311 case OP_LCOMPARE_IMM:
3312 if (!amd64_is_imm32 (ins->inst_imm)) {
3313 NEW_INS (cfg, ins, temp, OP_I8CONST);
3314 temp->inst_c0 = ins->inst_imm;
3315 temp->dreg = mono_alloc_ireg (cfg);
3316 ins->opcode = OP_COMPARE;
3317 ins->sreg2 = temp->dreg;
3320 #ifndef __mono_ilp32__
3321 case OP_LOAD_MEMBASE:
3323 case OP_LOADI8_MEMBASE:
3324 #ifndef __native_client_codegen__
3325 /* Don't generate memindex opcodes (to simplify */
3326 /* read sandboxing) */
3327 if (!amd64_is_imm32 (ins->inst_offset)) {
3328 NEW_INS (cfg, ins, temp, OP_I8CONST);
3329 temp->inst_c0 = ins->inst_offset;
3330 temp->dreg = mono_alloc_ireg (cfg);
3331 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3332 ins->inst_indexreg = temp->dreg;
3336 #ifndef __mono_ilp32__
3337 case OP_STORE_MEMBASE_IMM:
3339 case OP_STOREI8_MEMBASE_IMM:
3340 if (!amd64_is_imm32 (ins->inst_imm)) {
3341 NEW_INS (cfg, ins, temp, OP_I8CONST);
3342 temp->inst_c0 = ins->inst_imm;
3343 temp->dreg = mono_alloc_ireg (cfg);
3344 ins->opcode = OP_STOREI8_MEMBASE_REG;
3345 ins->sreg1 = temp->dreg;
3348 #ifdef MONO_ARCH_SIMD_INTRINSICS
3349 case OP_EXPAND_I1: {
3350 int temp_reg1 = mono_alloc_ireg (cfg);
3351 int temp_reg2 = mono_alloc_ireg (cfg);
3352 int original_reg = ins->sreg1;
3354 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3355 temp->sreg1 = original_reg;
3356 temp->dreg = temp_reg1;
3358 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3359 temp->sreg1 = temp_reg1;
3360 temp->dreg = temp_reg2;
3363 NEW_INS (cfg, ins, temp, OP_LOR);
3364 temp->sreg1 = temp->dreg = temp_reg2;
3365 temp->sreg2 = temp_reg1;
3367 ins->opcode = OP_EXPAND_I2;
3368 ins->sreg1 = temp_reg2;
3377 bb->max_vreg = cfg->next_vreg;
3381 branch_cc_table [] = {
3382 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3383 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3384 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3387 /* Maps CMP_... constants to X86_CC_... constants */
3390 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3391 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3395 cc_signed_table [] = {
3396 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3397 FALSE, FALSE, FALSE, FALSE
3400 /*#include "cprop.c"*/
3402 static unsigned char*
3403 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3405 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3408 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3410 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3414 static unsigned char*
3415 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3417 int sreg = tree->sreg1;
3418 int need_touch = FALSE;
3420 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3421 if (!tree->flags & MONO_INST_INIT)
3430 * If requested stack size is larger than one page,
3431 * perform stack-touch operation
3434 * Generate stack probe code.
3435 * Under Windows, it is necessary to allocate one page at a time,
3436 * "touching" stack after each successful sub-allocation. This is
3437 * because of the way stack growth is implemented - there is a
3438 * guard page before the lowest stack page that is currently commited.
3439 * Stack normally grows sequentially so OS traps access to the
3440 * guard page and commits more pages when needed.
3442 amd64_test_reg_imm (code, sreg, ~0xFFF);
3443 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3445 br[2] = code; /* loop */
3446 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3447 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3448 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3449 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3450 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3451 amd64_patch (br[3], br[2]);
3452 amd64_test_reg_reg (code, sreg, sreg);
3453 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3454 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3456 br[1] = code; x86_jump8 (code, 0);
3458 amd64_patch (br[0], code);
3459 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3460 amd64_patch (br[1], code);
3461 amd64_patch (br[4], code);
3464 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3466 if (tree->flags & MONO_INST_INIT) {
3468 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3469 amd64_push_reg (code, AMD64_RAX);
3472 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3473 amd64_push_reg (code, AMD64_RCX);
3476 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3477 amd64_push_reg (code, AMD64_RDI);
3481 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3482 if (sreg != AMD64_RCX)
3483 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3484 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3486 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3487 if (cfg->param_area && cfg->arch.no_pushes)
3488 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3490 #if defined(__default_codegen__)
3491 amd64_prefix (code, X86_REP_PREFIX);
3493 #elif defined(__native_client_codegen__)
3494 /* NaCl stos pseudo-instruction */
3495 amd64_codegen_pre(code);
3496 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3497 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3498 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3499 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3500 amd64_prefix (code, X86_REP_PREFIX);
3502 amd64_codegen_post(code);
3503 #endif /* __native_client_codegen__ */
3505 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3506 amd64_pop_reg (code, AMD64_RDI);
3507 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3508 amd64_pop_reg (code, AMD64_RCX);
3509 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3510 amd64_pop_reg (code, AMD64_RAX);
3516 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3521 /* Move return value to the target register */
3522 /* FIXME: do this in the local reg allocator */
3523 switch (ins->opcode) {
3526 case OP_CALL_MEMBASE:
3529 case OP_LCALL_MEMBASE:
3530 g_assert (ins->dreg == AMD64_RAX);
3534 case OP_FCALL_MEMBASE:
3535 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3536 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3539 if (ins->dreg != AMD64_XMM0)
3540 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3545 case OP_VCALL_MEMBASE:
3548 case OP_VCALL2_MEMBASE:
3549 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3550 if (cinfo->ret.storage == ArgValuetypeInReg) {
3551 MonoInst *loc = cfg->arch.vret_addr_loc;
3553 /* Load the destination address */
3554 g_assert (loc->opcode == OP_REGOFFSET);
3555 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3557 for (quad = 0; quad < 2; quad ++) {
3558 switch (cinfo->ret.pair_storage [quad]) {
3560 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3562 case ArgInFloatSSEReg:
3563 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3565 case ArgInDoubleSSEReg:
3566 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3581 #endif /* DISABLE_JIT */
3584 static int tls_gs_offset;
3588 mono_amd64_have_tls_get (void)
3591 static gboolean have_tls_get = FALSE;
3592 static gboolean inited = FALSE;
3596 return have_tls_get;
3598 ins = (guint8*)pthread_getspecific;
3601 * We're looking for these two instructions:
3603 * mov %gs:[offset](,%rdi,8),%rax
3606 have_tls_get = ins [0] == 0x65 &&
3618 tls_gs_offset = ins[5];
3620 return have_tls_get;
3627 mono_amd64_get_tls_gs_offset (void)
3630 return tls_gs_offset;
3632 g_assert_not_reached ();
3638 * mono_amd64_emit_tls_get:
3639 * @code: buffer to store code to
3640 * @dreg: hard register where to place the result
3641 * @tls_offset: offset info
3643 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3644 * the dreg register the item in the thread local storage identified
3647 * Returns: a pointer to the end of the stored code
3650 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3653 g_assert (tls_offset < 64);
3654 x86_prefix (code, X86_GS_PREFIX);
3655 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3656 #elif defined(__APPLE__)
3657 x86_prefix (code, X86_GS_PREFIX);
3658 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3660 if (optimize_for_xen) {
3661 x86_prefix (code, X86_FS_PREFIX);
3662 amd64_mov_reg_mem (code, dreg, 0, 8);
3663 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3665 x86_prefix (code, X86_FS_PREFIX);
3666 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3673 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3675 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3677 if (dreg != offset_reg)
3678 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3679 amd64_prefix (code, X86_GS_PREFIX);
3680 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3681 #elif defined(__linux__)
3684 if (dreg == offset_reg) {
3685 /* Use a temporary reg by saving it to the redzone */
3686 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3687 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3688 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3689 offset_reg = tmpreg;
3691 x86_prefix (code, X86_FS_PREFIX);
3692 amd64_mov_reg_mem (code, dreg, 0, 8);
3693 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3695 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3697 g_assert_not_reached ();
3703 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3706 g_assert_not_reached ();
3707 #elif defined(__APPLE__)
3708 x86_prefix (code, X86_GS_PREFIX);
3709 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3711 g_assert (!optimize_for_xen);
3712 x86_prefix (code, X86_FS_PREFIX);
3713 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3719 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3721 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3723 g_assert_not_reached ();
3724 #elif defined(__APPLE__)
3725 x86_prefix (code, X86_GS_PREFIX);
3726 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3728 x86_prefix (code, X86_FS_PREFIX);
3729 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3735 * mono_arch_translate_tls_offset:
3737 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3740 mono_arch_translate_tls_offset (int offset)
3743 return tls_gs_offset + (offset * 8);
3752 * Emit code to initialize an LMF structure at LMF_OFFSET.
3755 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3760 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3763 * sp is saved right before calls but we need to save it here too so
3764 * async stack walks would work.
3766 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3767 /* Skip method (only needed for trampoline LMF frames) */
3768 /* Save callee saved regs */
3769 for (i = 0; i < MONO_MAX_IREGS; ++i) {
3773 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
3774 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
3775 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
3776 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
3777 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
3778 #ifndef __native_client_codegen__
3779 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
3782 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
3783 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
3791 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
3792 if ((cfg->arch.omit_fp || (i != AMD64_RBP)) && cfa_offset != -1)
3793 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
3797 /* These can't contain refs */
3798 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3800 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3802 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3803 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3805 /* These are handled automatically by the stack marking code */
3806 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), SLOT_NOREF);
3807 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3808 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), SLOT_NOREF);
3809 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), SLOT_NOREF);
3810 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), SLOT_NOREF);
3811 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), SLOT_NOREF);
3813 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), SLOT_NOREF);
3814 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), SLOT_NOREF);
3824 * Emit code to push an LMF structure on the LMF stack.
3827 emit_push_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, gboolean *args_clobbered)
3829 if (jit_tls_offset != -1) {
3830 code = mono_amd64_emit_tls_get (code, AMD64_RAX, jit_tls_offset);
3831 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
3834 * The call might clobber argument registers, but they are already
3835 * saved to the stack/global regs.
3838 *args_clobbered = TRUE;
3839 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3840 (gpointer)"mono_get_lmf_addr", TRUE);
3844 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3845 /* Save previous_lmf */
3846 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
3847 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3849 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3850 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
3860 * Emit code to pop an LMF structure from the LMF stack.
3863 emit_pop_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
3865 /* Restore previous lmf */
3866 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3867 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3868 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
3874 #define REAL_PRINT_REG(text,reg) \
3875 mono_assert (reg >= 0); \
3876 amd64_push_reg (code, AMD64_RAX); \
3877 amd64_push_reg (code, AMD64_RDX); \
3878 amd64_push_reg (code, AMD64_RCX); \
3879 amd64_push_reg (code, reg); \
3880 amd64_push_imm (code, reg); \
3881 amd64_push_imm (code, text " %d %p\n"); \
3882 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3883 amd64_call_reg (code, AMD64_RAX); \
3884 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3885 amd64_pop_reg (code, AMD64_RCX); \
3886 amd64_pop_reg (code, AMD64_RDX); \
3887 amd64_pop_reg (code, AMD64_RAX);
3889 /* benchmark and set based on cpu */
3890 #define LOOP_ALIGNMENT 8
3891 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3895 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3900 guint8 *code = cfg->native_code + cfg->code_len;
3901 MonoInst *last_ins = NULL;
3902 guint last_offset = 0;
3905 /* Fix max_offset estimate for each successor bb */
3906 if (cfg->opt & MONO_OPT_BRANCH) {
3907 int current_offset = cfg->code_len;
3908 MonoBasicBlock *current_bb;
3909 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3910 current_bb->max_offset = current_offset;
3911 current_offset += current_bb->max_length;
3915 if (cfg->opt & MONO_OPT_LOOP) {
3916 int pad, align = LOOP_ALIGNMENT;
3917 /* set alignment depending on cpu */
3918 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3920 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3921 amd64_padding (code, pad);
3922 cfg->code_len += pad;
3923 bb->native_offset = cfg->code_len;
3927 #if defined(__native_client_codegen__)
3928 /* For Native Client, all indirect call/jump targets must be */
3929 /* 32-byte aligned. Exception handler blocks are jumped to */
3930 /* indirectly as well. */
3931 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3932 (bb->flags & BB_EXCEPTION_HANDLER);
3934 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3935 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3936 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3937 cfg->code_len += pad;
3938 bb->native_offset = cfg->code_len;
3940 #endif /*__native_client_codegen__*/
3942 if (cfg->verbose_level > 2)
3943 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3945 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3946 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3947 g_assert (!cfg->compile_aot);
3949 cov->data [bb->dfn].cil_code = bb->cil_code;
3950 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3951 /* this is not thread save, but good enough */
3952 amd64_inc_membase (code, AMD64_R11, 0);
3955 offset = code - cfg->native_code;
3957 mono_debug_open_block (cfg, bb, offset);
3959 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3960 x86_breakpoint (code);
3962 MONO_BB_FOR_EACH_INS (bb, ins) {
3963 offset = code - cfg->native_code;
3965 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3967 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3969 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3970 cfg->code_size *= 2;
3971 cfg->native_code = mono_realloc_native_code(cfg);
3972 code = cfg->native_code + offset;
3973 cfg->stat_code_reallocs++;
3976 if (cfg->debug_info)
3977 mono_debug_record_line_number (cfg, ins, offset);
3979 switch (ins->opcode) {
3981 amd64_mul_reg (code, ins->sreg2, TRUE);
3984 amd64_mul_reg (code, ins->sreg2, FALSE);
3986 case OP_X86_SETEQ_MEMBASE:
3987 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3989 case OP_STOREI1_MEMBASE_IMM:
3990 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3992 case OP_STOREI2_MEMBASE_IMM:
3993 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3995 case OP_STOREI4_MEMBASE_IMM:
3996 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3998 case OP_STOREI1_MEMBASE_REG:
3999 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
4001 case OP_STOREI2_MEMBASE_REG:
4002 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4004 /* In AMD64 NaCl, pointers are 4 bytes, */
4005 /* so STORE_* != STOREI8_*. Likewise below. */
4006 case OP_STORE_MEMBASE_REG:
4007 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4009 case OP_STOREI8_MEMBASE_REG:
4010 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4012 case OP_STOREI4_MEMBASE_REG:
4013 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4015 case OP_STORE_MEMBASE_IMM:
4016 #ifndef __native_client_codegen__
4017 /* In NaCl, this could be a PCONST type, which could */
4018 /* mean a pointer type was copied directly into the */
4019 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
4020 /* the value would be 0x00000000FFFFFFFF which is */
4021 /* not proper for an imm32 unless you cast it. */
4022 g_assert (amd64_is_imm32 (ins->inst_imm));
4024 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4026 case OP_STOREI8_MEMBASE_IMM:
4027 g_assert (amd64_is_imm32 (ins->inst_imm));
4028 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4031 #ifdef __mono_ilp32__
4032 /* In ILP32, pointers are 4 bytes, so separate these */
4033 /* cases, use literal 8 below where we really want 8 */
4034 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4035 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4039 // FIXME: Decompose this earlier
4040 if (amd64_is_imm32 (ins->inst_imm))
4041 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4043 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4044 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4048 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4049 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4052 // FIXME: Decompose this earlier
4053 if (amd64_is_imm32 (ins->inst_imm))
4054 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4056 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4057 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4061 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4062 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4065 /* For NaCl, pointers are 4 bytes, so separate these */
4066 /* cases, use literal 8 below where we really want 8 */
4067 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4068 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4070 case OP_LOAD_MEMBASE:
4071 g_assert (amd64_is_imm32 (ins->inst_offset));
4072 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4074 case OP_LOADI8_MEMBASE:
4075 /* Use literal 8 instead of sizeof pointer or */
4076 /* register, we really want 8 for this opcode */
4077 g_assert (amd64_is_imm32 (ins->inst_offset));
4078 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4080 case OP_LOADI4_MEMBASE:
4081 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4083 case OP_LOADU4_MEMBASE:
4084 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4086 case OP_LOADU1_MEMBASE:
4087 /* The cpu zero extends the result into 64 bits */
4088 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4090 case OP_LOADI1_MEMBASE:
4091 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4093 case OP_LOADU2_MEMBASE:
4094 /* The cpu zero extends the result into 64 bits */
4095 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4097 case OP_LOADI2_MEMBASE:
4098 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4100 case OP_AMD64_LOADI8_MEMINDEX:
4101 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4103 case OP_LCONV_TO_I1:
4104 case OP_ICONV_TO_I1:
4106 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4108 case OP_LCONV_TO_I2:
4109 case OP_ICONV_TO_I2:
4111 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4113 case OP_LCONV_TO_U1:
4114 case OP_ICONV_TO_U1:
4115 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4117 case OP_LCONV_TO_U2:
4118 case OP_ICONV_TO_U2:
4119 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4122 /* Clean out the upper word */
4123 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4126 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4130 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4132 case OP_COMPARE_IMM:
4133 #if defined(__mono_ilp32__)
4134 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4135 g_assert (amd64_is_imm32 (ins->inst_imm));
4136 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4139 case OP_LCOMPARE_IMM:
4140 g_assert (amd64_is_imm32 (ins->inst_imm));
4141 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4143 case OP_X86_COMPARE_REG_MEMBASE:
4144 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4146 case OP_X86_TEST_NULL:
4147 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4149 case OP_AMD64_TEST_NULL:
4150 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4153 case OP_X86_ADD_REG_MEMBASE:
4154 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4156 case OP_X86_SUB_REG_MEMBASE:
4157 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4159 case OP_X86_AND_REG_MEMBASE:
4160 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4162 case OP_X86_OR_REG_MEMBASE:
4163 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4165 case OP_X86_XOR_REG_MEMBASE:
4166 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4169 case OP_X86_ADD_MEMBASE_IMM:
4170 /* FIXME: Make a 64 version too */
4171 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4173 case OP_X86_SUB_MEMBASE_IMM:
4174 g_assert (amd64_is_imm32 (ins->inst_imm));
4175 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4177 case OP_X86_AND_MEMBASE_IMM:
4178 g_assert (amd64_is_imm32 (ins->inst_imm));
4179 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4181 case OP_X86_OR_MEMBASE_IMM:
4182 g_assert (amd64_is_imm32 (ins->inst_imm));
4183 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4185 case OP_X86_XOR_MEMBASE_IMM:
4186 g_assert (amd64_is_imm32 (ins->inst_imm));
4187 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4189 case OP_X86_ADD_MEMBASE_REG:
4190 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4192 case OP_X86_SUB_MEMBASE_REG:
4193 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4195 case OP_X86_AND_MEMBASE_REG:
4196 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4198 case OP_X86_OR_MEMBASE_REG:
4199 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4201 case OP_X86_XOR_MEMBASE_REG:
4202 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4204 case OP_X86_INC_MEMBASE:
4205 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4207 case OP_X86_INC_REG:
4208 amd64_inc_reg_size (code, ins->dreg, 4);
4210 case OP_X86_DEC_MEMBASE:
4211 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4213 case OP_X86_DEC_REG:
4214 amd64_dec_reg_size (code, ins->dreg, 4);
4216 case OP_X86_MUL_REG_MEMBASE:
4217 case OP_X86_MUL_MEMBASE_REG:
4218 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4220 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4221 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4223 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4224 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4226 case OP_AMD64_COMPARE_MEMBASE_REG:
4227 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4229 case OP_AMD64_COMPARE_MEMBASE_IMM:
4230 g_assert (amd64_is_imm32 (ins->inst_imm));
4231 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4233 case OP_X86_COMPARE_MEMBASE8_IMM:
4234 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4236 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4237 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4239 case OP_AMD64_COMPARE_REG_MEMBASE:
4240 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4243 case OP_AMD64_ADD_REG_MEMBASE:
4244 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4246 case OP_AMD64_SUB_REG_MEMBASE:
4247 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4249 case OP_AMD64_AND_REG_MEMBASE:
4250 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4252 case OP_AMD64_OR_REG_MEMBASE:
4253 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4255 case OP_AMD64_XOR_REG_MEMBASE:
4256 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4259 case OP_AMD64_ADD_MEMBASE_REG:
4260 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4262 case OP_AMD64_SUB_MEMBASE_REG:
4263 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4265 case OP_AMD64_AND_MEMBASE_REG:
4266 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4268 case OP_AMD64_OR_MEMBASE_REG:
4269 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4271 case OP_AMD64_XOR_MEMBASE_REG:
4272 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4275 case OP_AMD64_ADD_MEMBASE_IMM:
4276 g_assert (amd64_is_imm32 (ins->inst_imm));
4277 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4279 case OP_AMD64_SUB_MEMBASE_IMM:
4280 g_assert (amd64_is_imm32 (ins->inst_imm));
4281 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4283 case OP_AMD64_AND_MEMBASE_IMM:
4284 g_assert (amd64_is_imm32 (ins->inst_imm));
4285 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4287 case OP_AMD64_OR_MEMBASE_IMM:
4288 g_assert (amd64_is_imm32 (ins->inst_imm));
4289 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4291 case OP_AMD64_XOR_MEMBASE_IMM:
4292 g_assert (amd64_is_imm32 (ins->inst_imm));
4293 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4297 amd64_breakpoint (code);
4299 case OP_RELAXED_NOP:
4300 x86_prefix (code, X86_REP_PREFIX);
4308 case OP_DUMMY_STORE:
4309 case OP_NOT_REACHED:
4312 case OP_SEQ_POINT: {
4316 * Read from the single stepping trigger page. This will cause a
4317 * SIGSEGV when single stepping is enabled.
4318 * We do this _before_ the breakpoint, so single stepping after
4319 * a breakpoint is hit will step to the next IL offset.
4321 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4322 MonoInst *var = cfg->arch.ss_trigger_page_var;
4324 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4325 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4329 * This is the address which is saved in seq points,
4331 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4333 if (cfg->compile_aot) {
4334 guint32 offset = code - cfg->native_code;
4336 MonoInst *info_var = cfg->arch.seq_point_info_var;
4339 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4340 val = ((offset) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4341 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4342 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4343 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4346 * A placeholder for a possible breakpoint inserted by
4347 * mono_arch_set_breakpoint ().
4349 for (i = 0; i < breakpoint_size; ++i)
4353 * Add an additional nop so skipping the bp doesn't cause the ip to point
4354 * to another IL offset.
4362 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4365 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4369 g_assert (amd64_is_imm32 (ins->inst_imm));
4370 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4373 g_assert (amd64_is_imm32 (ins->inst_imm));
4374 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4379 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4382 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4386 g_assert (amd64_is_imm32 (ins->inst_imm));
4387 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4390 g_assert (amd64_is_imm32 (ins->inst_imm));
4391 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4394 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4398 g_assert (amd64_is_imm32 (ins->inst_imm));
4399 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4402 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4407 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4409 switch (ins->inst_imm) {
4413 if (ins->dreg != ins->sreg1)
4414 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4415 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4418 /* LEA r1, [r2 + r2*2] */
4419 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4422 /* LEA r1, [r2 + r2*4] */
4423 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4426 /* LEA r1, [r2 + r2*2] */
4428 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4429 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4432 /* LEA r1, [r2 + r2*8] */
4433 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4436 /* LEA r1, [r2 + r2*4] */
4438 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4439 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4442 /* LEA r1, [r2 + r2*2] */
4444 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4445 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4448 /* LEA r1, [r2 + r2*4] */
4449 /* LEA r1, [r1 + r1*4] */
4450 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4451 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4454 /* LEA r1, [r2 + r2*4] */
4456 /* LEA r1, [r1 + r1*4] */
4457 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4458 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4459 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4462 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4469 #if defined( __native_client_codegen__ )
4470 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4471 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4473 /* Regalloc magic makes the div/rem cases the same */
4474 if (ins->sreg2 == AMD64_RDX) {
4475 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4477 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4480 amd64_div_reg (code, ins->sreg2, TRUE);
4485 #if defined( __native_client_codegen__ )
4486 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4487 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4489 if (ins->sreg2 == AMD64_RDX) {
4490 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4491 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4492 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4494 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4495 amd64_div_reg (code, ins->sreg2, FALSE);
4500 #if defined( __native_client_codegen__ )
4501 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4502 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4504 if (ins->sreg2 == AMD64_RDX) {
4505 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4506 amd64_cdq_size (code, 4);
4507 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4509 amd64_cdq_size (code, 4);
4510 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4515 #if defined( __native_client_codegen__ )
4516 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4517 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4519 if (ins->sreg2 == AMD64_RDX) {
4520 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4521 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4522 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4524 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4525 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4529 int power = mono_is_power_of_two (ins->inst_imm);
4531 g_assert (ins->sreg1 == X86_EAX);
4532 g_assert (ins->dreg == X86_EAX);
4533 g_assert (power >= 0);
4536 amd64_mov_reg_imm (code, ins->dreg, 0);
4540 /* Based on gcc code */
4542 /* Add compensation for negative dividents */
4543 amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
4545 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
4546 amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
4547 amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
4548 /* Compute remainder */
4549 amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
4550 /* Remove compensation */
4551 amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
4555 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4556 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4559 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4563 g_assert (amd64_is_imm32 (ins->inst_imm));
4564 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4567 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4571 g_assert (amd64_is_imm32 (ins->inst_imm));
4572 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4575 g_assert (ins->sreg2 == AMD64_RCX);
4576 amd64_shift_reg (code, X86_SHL, ins->dreg);
4579 g_assert (ins->sreg2 == AMD64_RCX);
4580 amd64_shift_reg (code, X86_SAR, ins->dreg);
4583 g_assert (amd64_is_imm32 (ins->inst_imm));
4584 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4587 g_assert (amd64_is_imm32 (ins->inst_imm));
4588 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4591 g_assert (amd64_is_imm32 (ins->inst_imm));
4592 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4594 case OP_LSHR_UN_IMM:
4595 g_assert (amd64_is_imm32 (ins->inst_imm));
4596 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4599 g_assert (ins->sreg2 == AMD64_RCX);
4600 amd64_shift_reg (code, X86_SHR, ins->dreg);
4603 g_assert (amd64_is_imm32 (ins->inst_imm));
4604 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4607 g_assert (amd64_is_imm32 (ins->inst_imm));
4608 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4613 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4616 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4619 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4622 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4626 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4629 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4632 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4635 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4638 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4641 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4644 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4647 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4650 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4653 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4656 amd64_neg_reg_size (code, ins->sreg1, 4);
4659 amd64_not_reg_size (code, ins->sreg1, 4);
4662 g_assert (ins->sreg2 == AMD64_RCX);
4663 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4666 g_assert (ins->sreg2 == AMD64_RCX);
4667 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4670 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4672 case OP_ISHR_UN_IMM:
4673 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4676 g_assert (ins->sreg2 == AMD64_RCX);
4677 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4680 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4683 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4686 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4687 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4689 case OP_IMUL_OVF_UN:
4690 case OP_LMUL_OVF_UN: {
4691 /* the mul operation and the exception check should most likely be split */
4692 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4693 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4694 /*g_assert (ins->sreg2 == X86_EAX);
4695 g_assert (ins->dreg == X86_EAX);*/
4696 if (ins->sreg2 == X86_EAX) {
4697 non_eax_reg = ins->sreg1;
4698 } else if (ins->sreg1 == X86_EAX) {
4699 non_eax_reg = ins->sreg2;
4701 /* no need to save since we're going to store to it anyway */
4702 if (ins->dreg != X86_EAX) {
4704 amd64_push_reg (code, X86_EAX);
4706 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4707 non_eax_reg = ins->sreg2;
4709 if (ins->dreg == X86_EDX) {
4712 amd64_push_reg (code, X86_EAX);
4716 amd64_push_reg (code, X86_EDX);
4718 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4719 /* save before the check since pop and mov don't change the flags */
4720 if (ins->dreg != X86_EAX)
4721 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4723 amd64_pop_reg (code, X86_EDX);
4725 amd64_pop_reg (code, X86_EAX);
4726 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4730 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4732 case OP_ICOMPARE_IMM:
4733 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4755 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4763 case OP_CMOV_INE_UN:
4764 case OP_CMOV_IGE_UN:
4765 case OP_CMOV_IGT_UN:
4766 case OP_CMOV_ILE_UN:
4767 case OP_CMOV_ILT_UN:
4773 case OP_CMOV_LNE_UN:
4774 case OP_CMOV_LGE_UN:
4775 case OP_CMOV_LGT_UN:
4776 case OP_CMOV_LLE_UN:
4777 case OP_CMOV_LLT_UN:
4778 g_assert (ins->dreg == ins->sreg1);
4779 /* This needs to operate on 64 bit values */
4780 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4784 amd64_not_reg (code, ins->sreg1);
4787 amd64_neg_reg (code, ins->sreg1);
4792 if ((((guint64)ins->inst_c0) >> 32) == 0)
4793 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4795 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4798 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4799 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4802 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4803 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4806 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4808 case OP_AMD64_SET_XMMREG_R4: {
4809 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4812 case OP_AMD64_SET_XMMREG_R8: {
4813 if (ins->dreg != ins->sreg1)
4814 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4818 MonoCallInst *call = (MonoCallInst*)ins;
4819 int i, save_area_offset;
4821 /* FIXME: no tracing support... */
4822 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4823 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, TRUE);
4825 g_assert (!cfg->method->save_lmf);
4827 /* Restore callee saved registers */
4828 save_area_offset = cfg->arch.reg_save_area_offset;
4829 for (i = 0; i < AMD64_NREG; ++i)
4830 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4831 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4832 save_area_offset += 8;
4835 if (cfg->arch.omit_fp) {
4836 if (cfg->arch.stack_alloc_size)
4837 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4839 if (call->stack_usage)
4842 /* Copy arguments on the stack to our argument area */
4843 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4844 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4845 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4851 offset = code - cfg->native_code;
4852 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4853 if (cfg->compile_aot)
4854 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4856 amd64_set_reg_template (code, AMD64_R11);
4857 amd64_jump_reg (code, AMD64_R11);
4858 ins->flags |= MONO_INST_GC_CALLSITE;
4859 ins->backend.pc_offset = code - cfg->native_code;
4863 /* ensure ins->sreg1 is not NULL */
4864 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4867 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4868 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4877 call = (MonoCallInst*)ins;
4879 * The AMD64 ABI forces callers to know about varargs.
4881 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4882 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4883 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4885 * Since the unmanaged calling convention doesn't contain a
4886 * 'vararg' entry, we have to treat every pinvoke call as a
4887 * potential vararg call.
4891 for (i = 0; i < AMD64_XMM_NREG; ++i)
4892 if (call->used_fregs & (1 << i))
4895 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4897 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4900 if (ins->flags & MONO_INST_HAS_METHOD)
4901 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4903 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4904 ins->flags |= MONO_INST_GC_CALLSITE;
4905 ins->backend.pc_offset = code - cfg->native_code;
4906 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4907 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4908 code = emit_move_return_value (cfg, ins, code);
4914 case OP_VOIDCALL_REG:
4916 call = (MonoCallInst*)ins;
4918 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4919 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4920 ins->sreg1 = AMD64_R11;
4924 * The AMD64 ABI forces callers to know about varargs.
4926 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4927 if (ins->sreg1 == AMD64_RAX) {
4928 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4929 ins->sreg1 = AMD64_R11;
4931 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4932 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4934 * Since the unmanaged calling convention doesn't contain a
4935 * 'vararg' entry, we have to treat every pinvoke call as a
4936 * potential vararg call.
4940 for (i = 0; i < AMD64_XMM_NREG; ++i)
4941 if (call->used_fregs & (1 << i))
4943 if (ins->sreg1 == AMD64_RAX) {
4944 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4945 ins->sreg1 = AMD64_R11;
4948 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4950 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4953 amd64_call_reg (code, ins->sreg1);
4954 ins->flags |= MONO_INST_GC_CALLSITE;
4955 ins->backend.pc_offset = code - cfg->native_code;
4956 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4957 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4958 code = emit_move_return_value (cfg, ins, code);
4960 case OP_FCALL_MEMBASE:
4961 case OP_LCALL_MEMBASE:
4962 case OP_VCALL_MEMBASE:
4963 case OP_VCALL2_MEMBASE:
4964 case OP_VOIDCALL_MEMBASE:
4965 case OP_CALL_MEMBASE:
4966 call = (MonoCallInst*)ins;
4968 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4969 ins->flags |= MONO_INST_GC_CALLSITE;
4970 ins->backend.pc_offset = code - cfg->native_code;
4971 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4972 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4973 code = emit_move_return_value (cfg, ins, code);
4977 MonoInst *var = cfg->dyn_call_var;
4979 g_assert (var->opcode == OP_REGOFFSET);
4981 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4982 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4984 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4986 /* Save args buffer */
4987 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4989 /* Set argument registers */
4990 for (i = 0; i < PARAM_REGS; ++i)
4991 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4994 amd64_call_reg (code, AMD64_R10);
4996 ins->flags |= MONO_INST_GC_CALLSITE;
4997 ins->backend.pc_offset = code - cfg->native_code;
5000 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5001 amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5004 case OP_AMD64_SAVE_SP_TO_LMF: {
5005 MonoInst *lmf_var = cfg->lmf_var;
5006 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5010 g_assert (!cfg->arch.no_pushes);
5011 amd64_push_reg (code, ins->sreg1);
5013 case OP_X86_PUSH_IMM:
5014 g_assert (!cfg->arch.no_pushes);
5015 g_assert (amd64_is_imm32 (ins->inst_imm));
5016 amd64_push_imm (code, ins->inst_imm);
5018 case OP_X86_PUSH_MEMBASE:
5019 g_assert (!cfg->arch.no_pushes);
5020 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5022 case OP_X86_PUSH_OBJ: {
5023 int size = ALIGN_TO (ins->inst_imm, 8);
5025 g_assert (!cfg->arch.no_pushes);
5027 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5028 amd64_push_reg (code, AMD64_RDI);
5029 amd64_push_reg (code, AMD64_RSI);
5030 amd64_push_reg (code, AMD64_RCX);
5031 if (ins->inst_offset)
5032 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5034 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5035 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5036 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5038 amd64_prefix (code, X86_REP_PREFIX);
5040 amd64_pop_reg (code, AMD64_RCX);
5041 amd64_pop_reg (code, AMD64_RSI);
5042 amd64_pop_reg (code, AMD64_RDI);
5046 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5048 case OP_X86_LEA_MEMBASE:
5049 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5052 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5055 /* keep alignment */
5056 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5057 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5058 code = mono_emit_stack_alloc (cfg, code, ins);
5059 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5060 if (cfg->param_area && cfg->arch.no_pushes)
5061 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5063 case OP_LOCALLOC_IMM: {
5064 guint32 size = ins->inst_imm;
5065 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5067 if (ins->flags & MONO_INST_INIT) {
5071 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5072 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5074 for (i = 0; i < size; i += 8)
5075 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5076 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5078 amd64_mov_reg_imm (code, ins->dreg, size);
5079 ins->sreg1 = ins->dreg;
5081 code = mono_emit_stack_alloc (cfg, code, ins);
5082 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5085 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5086 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5088 if (cfg->param_area && cfg->arch.no_pushes)
5089 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5093 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5094 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5095 (gpointer)"mono_arch_throw_exception", FALSE);
5096 ins->flags |= MONO_INST_GC_CALLSITE;
5097 ins->backend.pc_offset = code - cfg->native_code;
5101 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5102 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5103 (gpointer)"mono_arch_rethrow_exception", FALSE);
5104 ins->flags |= MONO_INST_GC_CALLSITE;
5105 ins->backend.pc_offset = code - cfg->native_code;
5108 case OP_CALL_HANDLER:
5110 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5111 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5112 amd64_call_imm (code, 0);
5113 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5114 /* Restore stack alignment */
5115 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5117 case OP_START_HANDLER: {
5118 /* Even though we're saving RSP, use sizeof */
5119 /* gpointer because spvar is of type IntPtr */
5120 /* see: mono_create_spvar_for_region */
5121 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5122 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5124 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5125 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5126 cfg->param_area && cfg->arch.no_pushes) {
5127 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5131 case OP_ENDFINALLY: {
5132 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5133 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5137 case OP_ENDFILTER: {
5138 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5139 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5140 /* The local allocator will put the result into RAX */
5146 ins->inst_c0 = code - cfg->native_code;
5149 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5150 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5152 if (ins->inst_target_bb->native_offset) {
5153 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5155 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5156 if ((cfg->opt & MONO_OPT_BRANCH) &&
5157 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5158 x86_jump8 (code, 0);
5160 x86_jump32 (code, 0);
5164 amd64_jump_reg (code, ins->sreg1);
5187 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5188 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5190 case OP_COND_EXC_EQ:
5191 case OP_COND_EXC_NE_UN:
5192 case OP_COND_EXC_LT:
5193 case OP_COND_EXC_LT_UN:
5194 case OP_COND_EXC_GT:
5195 case OP_COND_EXC_GT_UN:
5196 case OP_COND_EXC_GE:
5197 case OP_COND_EXC_GE_UN:
5198 case OP_COND_EXC_LE:
5199 case OP_COND_EXC_LE_UN:
5200 case OP_COND_EXC_IEQ:
5201 case OP_COND_EXC_INE_UN:
5202 case OP_COND_EXC_ILT:
5203 case OP_COND_EXC_ILT_UN:
5204 case OP_COND_EXC_IGT:
5205 case OP_COND_EXC_IGT_UN:
5206 case OP_COND_EXC_IGE:
5207 case OP_COND_EXC_IGE_UN:
5208 case OP_COND_EXC_ILE:
5209 case OP_COND_EXC_ILE_UN:
5210 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5212 case OP_COND_EXC_OV:
5213 case OP_COND_EXC_NO:
5215 case OP_COND_EXC_NC:
5216 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5217 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5219 case OP_COND_EXC_IOV:
5220 case OP_COND_EXC_INO:
5221 case OP_COND_EXC_IC:
5222 case OP_COND_EXC_INC:
5223 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5224 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5227 /* floating point opcodes */
5229 double d = *(double *)ins->inst_p0;
5231 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5232 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5235 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5236 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5241 float f = *(float *)ins->inst_p0;
5243 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5244 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5247 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5248 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5249 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5253 case OP_STORER8_MEMBASE_REG:
5254 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5256 case OP_LOADR8_MEMBASE:
5257 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5259 case OP_STORER4_MEMBASE_REG:
5260 /* This requires a double->single conversion */
5261 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5262 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5264 case OP_LOADR4_MEMBASE:
5265 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5266 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5268 case OP_ICONV_TO_R4:
5269 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5270 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5272 case OP_ICONV_TO_R8:
5273 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5275 case OP_LCONV_TO_R4:
5276 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5277 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5279 case OP_LCONV_TO_R8:
5280 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5282 case OP_FCONV_TO_R4:
5283 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5284 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5286 case OP_FCONV_TO_I1:
5287 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5289 case OP_FCONV_TO_U1:
5290 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5292 case OP_FCONV_TO_I2:
5293 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5295 case OP_FCONV_TO_U2:
5296 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5298 case OP_FCONV_TO_U4:
5299 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5301 case OP_FCONV_TO_I4:
5303 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5305 case OP_FCONV_TO_I8:
5306 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5308 case OP_LCONV_TO_R_UN: {
5311 /* Based on gcc code */
5312 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5313 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5316 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5317 br [1] = code; x86_jump8 (code, 0);
5318 amd64_patch (br [0], code);
5321 /* Save to the red zone */
5322 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5323 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5324 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5325 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5326 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5327 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5328 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5329 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5330 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5332 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5333 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5334 amd64_patch (br [1], code);
5337 case OP_LCONV_TO_OVF_U4:
5338 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5339 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5340 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5342 case OP_LCONV_TO_OVF_I4_UN:
5343 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5344 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5345 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5348 if (ins->dreg != ins->sreg1)
5349 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5352 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5355 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5358 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5361 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5364 static double r8_0 = -0.0;
5366 g_assert (ins->sreg1 == ins->dreg);
5368 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5369 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5373 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5376 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5379 static guint64 d = 0x7fffffffffffffffUL;
5381 g_assert (ins->sreg1 == ins->dreg);
5383 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5384 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5388 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5391 g_assert (cfg->opt & MONO_OPT_CMOV);
5392 g_assert (ins->dreg == ins->sreg1);
5393 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5394 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5397 g_assert (cfg->opt & MONO_OPT_CMOV);
5398 g_assert (ins->dreg == ins->sreg1);
5399 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5400 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5403 g_assert (cfg->opt & MONO_OPT_CMOV);
5404 g_assert (ins->dreg == ins->sreg1);
5405 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5406 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5409 g_assert (cfg->opt & MONO_OPT_CMOV);
5410 g_assert (ins->dreg == ins->sreg1);
5411 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5412 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5415 g_assert (cfg->opt & MONO_OPT_CMOV);
5416 g_assert (ins->dreg == ins->sreg1);
5417 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5418 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5421 g_assert (cfg->opt & MONO_OPT_CMOV);
5422 g_assert (ins->dreg == ins->sreg1);
5423 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5424 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5427 g_assert (cfg->opt & MONO_OPT_CMOV);
5428 g_assert (ins->dreg == ins->sreg1);
5429 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5430 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5433 g_assert (cfg->opt & MONO_OPT_CMOV);
5434 g_assert (ins->dreg == ins->sreg1);
5435 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5436 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5442 * The two arguments are swapped because the fbranch instructions
5443 * depend on this for the non-sse case to work.
5445 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5449 /* zeroing the register at the start results in
5450 * shorter and faster code (we can also remove the widening op)
5452 guchar *unordered_check;
5453 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5454 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5455 unordered_check = code;
5456 x86_branch8 (code, X86_CC_P, 0, FALSE);
5458 if (ins->opcode == OP_FCEQ) {
5459 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5460 amd64_patch (unordered_check, code);
5462 guchar *jump_to_end;
5463 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5465 x86_jump8 (code, 0);
5466 amd64_patch (unordered_check, code);
5467 amd64_inc_reg (code, ins->dreg);
5468 amd64_patch (jump_to_end, code);
5474 /* zeroing the register at the start results in
5475 * shorter and faster code (we can also remove the widening op)
5477 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5478 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5479 if (ins->opcode == OP_FCLT_UN) {
5480 guchar *unordered_check = code;
5481 guchar *jump_to_end;
5482 x86_branch8 (code, X86_CC_P, 0, FALSE);
5483 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5485 x86_jump8 (code, 0);
5486 amd64_patch (unordered_check, code);
5487 amd64_inc_reg (code, ins->dreg);
5488 amd64_patch (jump_to_end, code);
5490 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5494 guchar *unordered_check;
5495 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5496 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5497 unordered_check = code;
5498 x86_branch8 (code, X86_CC_P, 0, FALSE);
5499 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5500 amd64_patch (unordered_check, code);
5505 /* zeroing the register at the start results in
5506 * shorter and faster code (we can also remove the widening op)
5508 guchar *unordered_check;
5509 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5510 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5511 if (ins->opcode == OP_FCGT) {
5512 unordered_check = code;
5513 x86_branch8 (code, X86_CC_P, 0, FALSE);
5514 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5515 amd64_patch (unordered_check, code);
5517 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5522 guchar *unordered_check;
5523 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5524 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5525 unordered_check = code;
5526 x86_branch8 (code, X86_CC_P, 0, FALSE);
5527 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5528 amd64_patch (unordered_check, code);
5532 case OP_FCLT_MEMBASE:
5533 case OP_FCGT_MEMBASE:
5534 case OP_FCLT_UN_MEMBASE:
5535 case OP_FCGT_UN_MEMBASE:
5536 case OP_FCEQ_MEMBASE: {
5537 guchar *unordered_check, *jump_to_end;
5540 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5541 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5543 switch (ins->opcode) {
5544 case OP_FCEQ_MEMBASE:
5545 x86_cond = X86_CC_EQ;
5547 case OP_FCLT_MEMBASE:
5548 case OP_FCLT_UN_MEMBASE:
5549 x86_cond = X86_CC_LT;
5551 case OP_FCGT_MEMBASE:
5552 case OP_FCGT_UN_MEMBASE:
5553 x86_cond = X86_CC_GT;
5556 g_assert_not_reached ();
5559 unordered_check = code;
5560 x86_branch8 (code, X86_CC_P, 0, FALSE);
5561 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5563 switch (ins->opcode) {
5564 case OP_FCEQ_MEMBASE:
5565 case OP_FCLT_MEMBASE:
5566 case OP_FCGT_MEMBASE:
5567 amd64_patch (unordered_check, code);
5569 case OP_FCLT_UN_MEMBASE:
5570 case OP_FCGT_UN_MEMBASE:
5572 x86_jump8 (code, 0);
5573 amd64_patch (unordered_check, code);
5574 amd64_inc_reg (code, ins->dreg);
5575 amd64_patch (jump_to_end, code);
5583 guchar *jump = code;
5584 x86_branch8 (code, X86_CC_P, 0, TRUE);
5585 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5586 amd64_patch (jump, code);
5590 /* Branch if C013 != 100 */
5591 /* branch if !ZF or (PF|CF) */
5592 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5593 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5594 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5597 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5600 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5601 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5605 if (ins->opcode == OP_FBGT) {
5608 /* skip branch if C1=1 */
5610 x86_branch8 (code, X86_CC_P, 0, FALSE);
5611 /* branch if (C0 | C3) = 1 */
5612 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5613 amd64_patch (br1, code);
5616 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5620 /* Branch if C013 == 100 or 001 */
5623 /* skip branch if C1=1 */
5625 x86_branch8 (code, X86_CC_P, 0, FALSE);
5626 /* branch if (C0 | C3) = 1 */
5627 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5628 amd64_patch (br1, code);
5632 /* Branch if C013 == 000 */
5633 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5636 /* Branch if C013=000 or 100 */
5639 /* skip branch if C1=1 */
5641 x86_branch8 (code, X86_CC_P, 0, FALSE);
5642 /* branch if C0=0 */
5643 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5644 amd64_patch (br1, code);
5648 /* Branch if C013 != 001 */
5649 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5650 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5653 /* Transfer value to the fp stack */
5654 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5655 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5656 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5658 amd64_push_reg (code, AMD64_RAX);
5660 amd64_fnstsw (code);
5661 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5662 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5663 amd64_pop_reg (code, AMD64_RAX);
5664 amd64_fstp (code, 0);
5665 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5666 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5669 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5672 case OP_TLS_GET_REG:
5673 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5676 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5679 case OP_TLS_SET_REG: {
5680 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5683 case OP_MEMORY_BARRIER: {
5684 switch (ins->backend.memory_barrier_kind) {
5685 case StoreLoadBarrier:
5687 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5688 x86_prefix (code, X86_LOCK_PREFIX);
5689 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5694 case OP_ATOMIC_ADD_I4:
5695 case OP_ATOMIC_ADD_I8: {
5696 int dreg = ins->dreg;
5697 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5699 if (dreg == ins->inst_basereg)
5702 if (dreg != ins->sreg2)
5703 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5705 x86_prefix (code, X86_LOCK_PREFIX);
5706 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5708 if (dreg != ins->dreg)
5709 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5713 case OP_ATOMIC_ADD_NEW_I4:
5714 case OP_ATOMIC_ADD_NEW_I8: {
5715 int dreg = ins->dreg;
5716 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
5718 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5721 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5722 amd64_prefix (code, X86_LOCK_PREFIX);
5723 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5724 /* dreg contains the old value, add with sreg2 value */
5725 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5727 if (ins->dreg != dreg)
5728 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5732 case OP_ATOMIC_EXCHANGE_I4:
5733 case OP_ATOMIC_EXCHANGE_I8: {
5735 int sreg2 = ins->sreg2;
5736 int breg = ins->inst_basereg;
5738 gboolean need_push = FALSE, rdx_pushed = FALSE;
5740 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5746 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5747 * an explanation of how this works.
5750 /* cmpxchg uses eax as comperand, need to make sure we can use it
5751 * hack to overcome limits in x86 reg allocator
5752 * (req: dreg == eax and sreg2 != eax and breg != eax)
5754 g_assert (ins->dreg == AMD64_RAX);
5756 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5757 /* Highly unlikely, but possible */
5760 /* The pushes invalidate rsp */
5761 if ((breg == AMD64_RAX) || need_push) {
5762 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5766 /* We need the EAX reg for the comparand */
5767 if (ins->sreg2 == AMD64_RAX) {
5768 if (breg != AMD64_R11) {
5769 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5772 g_assert (need_push);
5773 amd64_push_reg (code, AMD64_RDX);
5774 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5780 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5782 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5783 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5784 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5785 amd64_patch (br [1], br [0]);
5788 amd64_pop_reg (code, AMD64_RDX);
5792 case OP_ATOMIC_CAS_I4:
5793 case OP_ATOMIC_CAS_I8: {
5796 if (ins->opcode == OP_ATOMIC_CAS_I8)
5802 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5803 * an explanation of how this works.
5805 g_assert (ins->sreg3 == AMD64_RAX);
5806 g_assert (ins->sreg1 != AMD64_RAX);
5807 g_assert (ins->sreg1 != ins->sreg2);
5809 amd64_prefix (code, X86_LOCK_PREFIX);
5810 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5812 if (ins->dreg != AMD64_RAX)
5813 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5816 case OP_CARD_TABLE_WBARRIER: {
5817 int ptr = ins->sreg1;
5818 int value = ins->sreg2;
5820 int nursery_shift, card_table_shift;
5821 gpointer card_table_mask;
5822 size_t nursery_size;
5824 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5825 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5826 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5828 /*If either point to the stack we can simply avoid the WB. This happens due to
5829 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5831 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5835 * We need one register we can clobber, we choose EDX and make sreg1
5836 * fixed EAX to work around limitations in the local register allocator.
5837 * sreg2 might get allocated to EDX, but that is not a problem since
5838 * we use it before clobbering EDX.
5840 g_assert (ins->sreg1 == AMD64_RAX);
5843 * This is the code we produce:
5846 * edx >>= nursery_shift
5847 * cmp edx, (nursery_start >> nursery_shift)
5850 * edx >>= card_table_shift
5856 if (mono_gc_card_table_nursery_check ()) {
5857 if (value != AMD64_RDX)
5858 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5859 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5860 if (shifted_nursery_start >> 31) {
5862 * The value we need to compare against is 64 bits, so we need
5863 * another spare register. We use RBX, which we save and
5866 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5867 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5868 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5869 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5871 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5873 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5875 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5876 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5877 if (card_table_mask)
5878 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5880 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5881 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5883 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5885 if (mono_gc_card_table_nursery_check ())
5886 x86_patch (br, code);
5889 #ifdef MONO_ARCH_SIMD_INTRINSICS
5890 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5892 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5895 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5898 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5901 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5904 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5907 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5910 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5911 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5914 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5917 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5920 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5923 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5926 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5929 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5932 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5935 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5938 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5941 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5944 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5947 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5950 case OP_PSHUFLEW_HIGH:
5951 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5952 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5954 case OP_PSHUFLEW_LOW:
5955 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5956 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5959 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5960 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5963 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5964 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5967 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5968 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5972 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5975 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5978 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5981 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5984 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5987 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5990 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5991 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5994 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5997 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6000 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6003 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6006 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6009 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6012 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6015 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6018 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6021 case OP_EXTRACT_MASK:
6022 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6026 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6029 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6032 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6036 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6039 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6042 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6045 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6049 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6052 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6055 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6058 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6062 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6065 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6068 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6072 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6075 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6078 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6082 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6085 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6089 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6092 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6095 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6099 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6102 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6105 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6109 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6112 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6115 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6118 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6122 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6125 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6128 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6131 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6134 case OP_PSUM_ABS_DIFF:
6135 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6138 case OP_UNPACK_LOWB:
6139 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6141 case OP_UNPACK_LOWW:
6142 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6144 case OP_UNPACK_LOWD:
6145 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6147 case OP_UNPACK_LOWQ:
6148 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6150 case OP_UNPACK_LOWPS:
6151 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6153 case OP_UNPACK_LOWPD:
6154 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6157 case OP_UNPACK_HIGHB:
6158 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6160 case OP_UNPACK_HIGHW:
6161 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6163 case OP_UNPACK_HIGHD:
6164 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6166 case OP_UNPACK_HIGHQ:
6167 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6169 case OP_UNPACK_HIGHPS:
6170 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6172 case OP_UNPACK_HIGHPD:
6173 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6177 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6180 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6183 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6186 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6189 case OP_PADDB_SAT_UN:
6190 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6192 case OP_PSUBB_SAT_UN:
6193 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6195 case OP_PADDW_SAT_UN:
6196 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6198 case OP_PSUBW_SAT_UN:
6199 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6203 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6206 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6209 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6212 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6216 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6219 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6222 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6224 case OP_PMULW_HIGH_UN:
6225 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6228 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6232 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6235 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6239 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6242 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6246 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6249 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6253 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6256 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6260 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6263 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6267 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6270 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6274 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6277 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6280 /*TODO: This is appart of the sse spec but not added
6282 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6285 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6290 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6293 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6296 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6299 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6302 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6305 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6308 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6311 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6314 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6317 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6321 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6324 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6328 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6329 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6331 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6336 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6338 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6339 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6343 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6345 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6346 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6347 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6351 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6353 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6356 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6358 case OP_EXTRACTX_U2:
6359 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6361 case OP_INSERTX_U1_SLOW:
6362 /*sreg1 is the extracted ireg (scratch)
6363 /sreg2 is the to be inserted ireg (scratch)
6364 /dreg is the xreg to receive the value*/
6366 /*clear the bits from the extracted word*/
6367 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6368 /*shift the value to insert if needed*/
6369 if (ins->inst_c0 & 1)
6370 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6371 /*join them together*/
6372 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6373 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6375 case OP_INSERTX_I4_SLOW:
6376 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6377 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6378 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6380 case OP_INSERTX_I8_SLOW:
6381 amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6383 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6385 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6388 case OP_INSERTX_R4_SLOW:
6389 switch (ins->inst_c0) {
6391 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6394 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6395 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6396 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6399 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6400 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6401 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6404 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6405 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6406 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6410 case OP_INSERTX_R8_SLOW:
6412 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6414 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6416 case OP_STOREX_MEMBASE_REG:
6417 case OP_STOREX_MEMBASE:
6418 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6420 case OP_LOADX_MEMBASE:
6421 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6423 case OP_LOADX_ALIGNED_MEMBASE:
6424 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6426 case OP_STOREX_ALIGNED_MEMBASE_REG:
6427 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6429 case OP_STOREX_NTA_MEMBASE_REG:
6430 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6432 case OP_PREFETCH_MEMBASE:
6433 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6437 /*FIXME the peephole pass should have killed this*/
6438 if (ins->dreg != ins->sreg1)
6439 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6442 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6444 case OP_ICONV_TO_R8_RAW:
6445 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6446 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6449 case OP_FCONV_TO_R8_X:
6450 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6453 case OP_XCONV_R8_TO_I4:
6454 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6455 switch (ins->backend.source_opcode) {
6456 case OP_FCONV_TO_I1:
6457 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6459 case OP_FCONV_TO_U1:
6460 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6462 case OP_FCONV_TO_I2:
6463 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6465 case OP_FCONV_TO_U2:
6466 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6472 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6473 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6474 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6477 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6478 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6481 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6482 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6485 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6486 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6487 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6490 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6491 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6494 case OP_LIVERANGE_START: {
6495 if (cfg->verbose_level > 1)
6496 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6497 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6500 case OP_LIVERANGE_END: {
6501 if (cfg->verbose_level > 1)
6502 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6503 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6506 case OP_NACL_GC_SAFE_POINT: {
6507 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6508 if (cfg->compile_aot)
6509 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6513 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6514 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6515 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6516 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6517 amd64_patch (br[0], code);
6522 case OP_GC_LIVENESS_DEF:
6523 case OP_GC_LIVENESS_USE:
6524 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6525 ins->backend.pc_offset = code - cfg->native_code;
6527 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6528 ins->backend.pc_offset = code - cfg->native_code;
6529 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6532 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6533 g_assert_not_reached ();
6536 if ((code - cfg->native_code - offset) > max_len) {
6537 #if !defined(__native_client_codegen__)
6538 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6539 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6540 g_assert_not_reached ();
6545 last_offset = offset;
6548 cfg->code_len = code - cfg->native_code;
6551 #endif /* DISABLE_JIT */
6554 mono_arch_register_lowlevel_calls (void)
6556 /* The signature doesn't matter */
6557 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6561 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6563 MonoJumpInfo *patch_info;
6564 gboolean compile_aot = !run_cctors;
6566 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6567 unsigned char *ip = patch_info->ip.i + code;
6568 unsigned char *target;
6571 switch (patch_info->type) {
6572 case MONO_PATCH_INFO_BB:
6573 case MONO_PATCH_INFO_LABEL:
6576 /* No need to patch these */
6581 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6583 switch (patch_info->type) {
6584 case MONO_PATCH_INFO_NONE:
6586 case MONO_PATCH_INFO_METHOD_REL:
6587 case MONO_PATCH_INFO_R8:
6588 case MONO_PATCH_INFO_R4:
6589 g_assert_not_reached ();
6591 case MONO_PATCH_INFO_BB:
6598 * Debug code to help track down problems where the target of a near call is
6601 if (amd64_is_near_call (ip)) {
6602 gint64 disp = (guint8*)target - (guint8*)ip;
6604 if (!amd64_is_imm32 (disp)) {
6605 printf ("TYPE: %d\n", patch_info->type);
6606 switch (patch_info->type) {
6607 case MONO_PATCH_INFO_INTERNAL_METHOD:
6608 printf ("V: %s\n", patch_info->data.name);
6610 case MONO_PATCH_INFO_METHOD_JUMP:
6611 case MONO_PATCH_INFO_METHOD:
6612 printf ("V: %s\n", patch_info->data.method->name);
6620 amd64_patch (ip, (gpointer)target);
6627 get_max_epilog_size (MonoCompile *cfg)
6629 int max_epilog_size = 16;
6631 if (cfg->method->save_lmf)
6632 max_epilog_size += 256;
6634 if (mono_jit_trace_calls != NULL)
6635 max_epilog_size += 50;
6637 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6638 max_epilog_size += 50;
6640 max_epilog_size += (AMD64_NREG * 2);
6642 return max_epilog_size;
6646 * This macro is used for testing whenever the unwinder works correctly at every point
6647 * where an async exception can happen.
6649 /* This will generate a SIGSEGV at the given point in the code */
6650 #define async_exc_point(code) do { \
6651 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6652 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6653 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6654 cfg->arch.async_point_count ++; \
6659 mono_arch_emit_prolog (MonoCompile *cfg)
6661 MonoMethod *method = cfg->method;
6663 MonoMethodSignature *sig;
6665 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6668 MonoInst *lmf_var = cfg->lmf_var;
6669 gboolean args_clobbered = FALSE;
6670 gboolean trace = FALSE;
6671 #ifdef __native_client_codegen__
6672 guint alignment_check;
6675 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
6677 #if defined(__default_codegen__)
6678 code = cfg->native_code = g_malloc (cfg->code_size);
6679 #elif defined(__native_client_codegen__)
6680 /* native_code_alloc is not 32-byte aligned, native_code is. */
6681 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6683 /* Align native_code to next nearest kNaclAlignment byte. */
6684 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6685 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6687 code = cfg->native_code;
6689 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6690 g_assert (alignment_check == 0);
6693 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6696 /* Amount of stack space allocated by register saving code */
6699 /* Offset between RSP and the CFA */
6703 * The prolog consists of the following parts:
6705 * - push rbp, mov rbp, rsp
6706 * - save callee saved regs using pushes
6708 * - save rgctx if needed
6709 * - save lmf if needed
6712 * - save rgctx if needed
6713 * - save lmf if needed
6714 * - save callee saved regs using moves
6719 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6720 // IP saved at CFA - 8
6721 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6722 async_exc_point (code);
6723 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6725 if (!cfg->arch.omit_fp) {
6726 amd64_push_reg (code, AMD64_RBP);
6728 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6729 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6730 async_exc_point (code);
6732 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6734 /* These are handled automatically by the stack marking code */
6735 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6737 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6738 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6739 async_exc_point (code);
6741 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6745 /* The param area is always at offset 0 from sp */
6746 /* This needs to be allocated here, since it has to come after the spill area */
6747 if (cfg->arch.no_pushes && cfg->param_area) {
6748 if (cfg->arch.omit_fp)
6750 g_assert_not_reached ();
6751 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6754 if (cfg->arch.omit_fp) {
6756 * On enter, the stack is misaligned by the pushing of the return
6757 * address. It is either made aligned by the pushing of %rbp, or by
6760 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6761 if ((alloc_size % 16) == 0) {
6763 /* Mark the padding slot as NOREF */
6764 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6767 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6768 if (cfg->stack_offset != alloc_size) {
6769 /* Mark the padding slot as NOREF */
6770 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6772 cfg->arch.sp_fp_offset = alloc_size;
6776 cfg->arch.stack_alloc_size = alloc_size;
6778 /* Allocate stack frame */
6780 /* See mono_emit_stack_alloc */
6781 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6782 guint32 remaining_size = alloc_size;
6783 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6784 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6785 guint32 offset = code - cfg->native_code;
6786 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6787 while (required_code_size >= (cfg->code_size - offset))
6788 cfg->code_size *= 2;
6789 cfg->native_code = mono_realloc_native_code (cfg);
6790 code = cfg->native_code + offset;
6791 cfg->stat_code_reallocs++;
6794 while (remaining_size >= 0x1000) {
6795 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6796 if (cfg->arch.omit_fp) {
6797 cfa_offset += 0x1000;
6798 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6800 async_exc_point (code);
6802 if (cfg->arch.omit_fp)
6803 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6806 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6807 remaining_size -= 0x1000;
6809 if (remaining_size) {
6810 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6811 if (cfg->arch.omit_fp) {
6812 cfa_offset += remaining_size;
6813 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6814 async_exc_point (code);
6817 if (cfg->arch.omit_fp)
6818 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6822 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6823 if (cfg->arch.omit_fp) {
6824 cfa_offset += alloc_size;
6825 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6826 async_exc_point (code);
6831 /* Stack alignment check */
6834 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6835 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6836 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6837 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6838 amd64_breakpoint (code);
6842 #ifndef TARGET_WIN32
6843 if (mini_get_debug_options ()->init_stacks) {
6844 /* Fill the stack frame with a dummy value to force deterministic behavior */
6846 /* Save registers to the red zone */
6847 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6848 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6850 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6851 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6852 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6855 #if defined(__default_codegen__)
6856 amd64_prefix (code, X86_REP_PREFIX);
6858 #elif defined(__native_client_codegen__)
6859 /* NaCl stos pseudo-instruction */
6860 amd64_codegen_pre (code);
6861 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6862 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6863 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6864 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6865 amd64_prefix (code, X86_REP_PREFIX);
6867 amd64_codegen_post (code);
6868 #endif /* __native_client_codegen__ */
6870 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6871 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6876 if (method->save_lmf) {
6877 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6880 /* Save callee saved registers */
6881 if (!method->save_lmf) {
6882 gint32 save_area_offset;
6884 if (cfg->arch.omit_fp) {
6885 save_area_offset = cfg->arch.reg_save_area_offset;
6886 /* Save caller saved registers after sp is adjusted */
6887 /* The registers are saved at the bottom of the frame */
6888 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6890 /* The registers are saved just below the saved rbp */
6891 save_area_offset = cfg->arch.reg_save_area_offset;
6894 for (i = 0; i < AMD64_NREG; ++i)
6895 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6896 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6898 if (cfg->arch.omit_fp) {
6899 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6900 /* These are handled automatically by the stack marking code */
6901 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6903 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6907 save_area_offset += 8;
6908 async_exc_point (code);
6912 /* store runtime generic context */
6913 if (cfg->rgctx_var) {
6914 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6915 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6917 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6919 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6920 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6923 /* compute max_length in order to use short forward jumps */
6924 max_epilog_size = get_max_epilog_size (cfg);
6925 if (cfg->opt & MONO_OPT_BRANCH) {
6926 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6930 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6932 /* max alignment for loops */
6933 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6934 max_length += LOOP_ALIGNMENT;
6935 #ifdef __native_client_codegen__
6936 /* max alignment for native client */
6937 max_length += kNaClAlignment;
6940 MONO_BB_FOR_EACH_INS (bb, ins) {
6941 #ifdef __native_client_codegen__
6943 int space_in_block = kNaClAlignment -
6944 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6945 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6946 if (space_in_block < max_len && max_len < kNaClAlignment) {
6947 max_length += space_in_block;
6950 #endif /*__native_client_codegen__*/
6951 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6954 /* Take prolog and epilog instrumentation into account */
6955 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6956 max_length += max_epilog_size;
6958 bb->max_length = max_length;
6962 sig = mono_method_signature (method);
6965 cinfo = cfg->arch.cinfo;
6967 if (sig->ret->type != MONO_TYPE_VOID) {
6968 /* Save volatile arguments to the stack */
6969 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6970 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6973 /* Keep this in sync with emit_load_volatile_arguments */
6974 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6975 ArgInfo *ainfo = cinfo->args + i;
6976 gint32 stack_offset;
6979 ins = cfg->args [i];
6981 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6982 /* Unused arguments */
6985 if (sig->hasthis && (i == 0))
6986 arg_type = &mono_defaults.object_class->byval_arg;
6988 arg_type = sig->params [i - sig->hasthis];
6990 stack_offset = ainfo->offset + ARGS_OFFSET;
6992 if (cfg->globalra) {
6993 /* All the other moves are done by the register allocator */
6994 switch (ainfo->storage) {
6995 case ArgInFloatSSEReg:
6996 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6998 case ArgValuetypeInReg:
6999 for (quad = 0; quad < 2; quad ++) {
7000 switch (ainfo->pair_storage [quad]) {
7002 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7004 case ArgInFloatSSEReg:
7005 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7007 case ArgInDoubleSSEReg:
7008 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7013 g_assert_not_reached ();
7024 /* Save volatile arguments to the stack */
7025 if (ins->opcode != OP_REGVAR) {
7026 switch (ainfo->storage) {
7032 if (stack_offset & 0x1)
7034 else if (stack_offset & 0x2)
7036 else if (stack_offset & 0x4)
7041 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7044 * Save the original location of 'this',
7045 * get_generic_info_from_stack_frame () needs this to properly look up
7046 * the argument value during the handling of async exceptions.
7048 if (ins == cfg->args [0]) {
7049 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7050 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7054 case ArgInFloatSSEReg:
7055 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7057 case ArgInDoubleSSEReg:
7058 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7060 case ArgValuetypeInReg:
7061 for (quad = 0; quad < 2; quad ++) {
7062 switch (ainfo->pair_storage [quad]) {
7064 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7066 case ArgInFloatSSEReg:
7067 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7069 case ArgInDoubleSSEReg:
7070 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7075 g_assert_not_reached ();
7079 case ArgValuetypeAddrInIReg:
7080 if (ainfo->pair_storage [0] == ArgInIReg)
7081 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7087 /* Argument allocated to (non-volatile) register */
7088 switch (ainfo->storage) {
7090 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7093 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7096 g_assert_not_reached ();
7099 if (ins == cfg->args [0]) {
7100 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7101 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7107 if (method->save_lmf) {
7108 code = emit_push_lmf (cfg, code, lmf_var->inst_offset, &args_clobbered);
7111 args_clobbered = TRUE;
7115 args_clobbered = TRUE;
7116 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7119 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7120 args_clobbered = TRUE;
7123 * Optimize the common case of the first bblock making a call with the same
7124 * arguments as the method. This works because the arguments are still in their
7125 * original argument registers.
7126 * FIXME: Generalize this
7128 if (!args_clobbered) {
7129 MonoBasicBlock *first_bb = cfg->bb_entry;
7132 next = mono_bb_first_ins (first_bb);
7133 if (!next && first_bb->next_bb) {
7134 first_bb = first_bb->next_bb;
7135 next = mono_bb_first_ins (first_bb);
7138 if (first_bb->in_count > 1)
7141 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7142 ArgInfo *ainfo = cinfo->args + i;
7143 gboolean match = FALSE;
7145 ins = cfg->args [i];
7146 if (ins->opcode != OP_REGVAR) {
7147 switch (ainfo->storage) {
7149 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7150 if (next->dreg == ainfo->reg) {
7154 next->opcode = OP_MOVE;
7155 next->sreg1 = ainfo->reg;
7156 /* Only continue if the instruction doesn't change argument regs */
7157 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7167 /* Argument allocated to (non-volatile) register */
7168 switch (ainfo->storage) {
7170 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7182 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7189 if (cfg->gen_seq_points) {
7190 MonoInst *info_var = cfg->arch.seq_point_info_var;
7192 /* Initialize seq_point_info_var */
7193 if (cfg->compile_aot) {
7194 /* Initialize the variable from a GOT slot */
7195 /* Same as OP_AOTCONST */
7196 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7197 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7198 g_assert (info_var->opcode == OP_REGOFFSET);
7199 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7202 /* Initialize ss_trigger_page_var */
7203 ins = cfg->arch.ss_trigger_page_var;
7205 g_assert (ins->opcode == OP_REGOFFSET);
7207 if (cfg->compile_aot) {
7208 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7209 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7211 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7213 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7216 cfg->code_len = code - cfg->native_code;
7218 g_assert (cfg->code_len < cfg->code_size);
7224 mono_arch_emit_epilog (MonoCompile *cfg)
7226 MonoMethod *method = cfg->method;
7229 int max_epilog_size;
7231 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7233 max_epilog_size = get_max_epilog_size (cfg);
7235 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7236 cfg->code_size *= 2;
7237 cfg->native_code = mono_realloc_native_code (cfg);
7238 cfg->stat_code_reallocs++;
7241 code = cfg->native_code + cfg->code_len;
7243 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7244 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7246 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7249 if (method->save_lmf) {
7251 code = emit_pop_lmf (cfg, code, lmf_offset);
7254 /* check if we need to restore protection of the stack after a stack overflow */
7255 if (mono_get_jit_tls_offset () != -1) {
7257 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7258 /* we load the value in a separate instruction: this mechanism may be
7259 * used later as a safer way to do thread interruption
7261 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7262 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7264 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7265 /* note that the call trampoline will preserve eax/edx */
7266 x86_call_reg (code, X86_ECX);
7267 x86_patch (patch, code);
7269 /* FIXME: maybe save the jit tls in the prolog */
7272 /* Restore caller saved regs */
7273 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7274 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7276 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
7277 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
7279 if (cfg->used_int_regs & (1 << AMD64_R12)) {
7280 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
7282 if (cfg->used_int_regs & (1 << AMD64_R13)) {
7283 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
7285 if (cfg->used_int_regs & (1 << AMD64_R14)) {
7286 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
7288 if (cfg->used_int_regs & (1 << AMD64_R15)) {
7289 #if defined(__default_codegen__)
7290 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
7291 #elif defined(__native_client_codegen__)
7292 g_assert_not_reached();
7296 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
7297 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
7299 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
7300 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
7304 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7306 for (i = 0; i < AMD64_NREG; ++i)
7307 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7308 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7309 save_area_offset += 8;
7313 /* Load returned vtypes into registers if needed */
7314 cinfo = cfg->arch.cinfo;
7315 if (cinfo->ret.storage == ArgValuetypeInReg) {
7316 ArgInfo *ainfo = &cinfo->ret;
7317 MonoInst *inst = cfg->ret;
7319 for (quad = 0; quad < 2; quad ++) {
7320 switch (ainfo->pair_storage [quad]) {
7322 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7324 case ArgInFloatSSEReg:
7325 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7327 case ArgInDoubleSSEReg:
7328 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7333 g_assert_not_reached ();
7338 if (cfg->arch.omit_fp) {
7339 if (cfg->arch.stack_alloc_size)
7340 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7344 async_exc_point (code);
7347 cfg->code_len = code - cfg->native_code;
7349 g_assert (cfg->code_len < cfg->code_size);
7353 mono_arch_emit_exceptions (MonoCompile *cfg)
7355 MonoJumpInfo *patch_info;
7358 MonoClass *exc_classes [16];
7359 guint8 *exc_throw_start [16], *exc_throw_end [16];
7360 guint32 code_size = 0;
7362 /* Compute needed space */
7363 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7364 if (patch_info->type == MONO_PATCH_INFO_EXC)
7366 if (patch_info->type == MONO_PATCH_INFO_R8)
7367 code_size += 8 + 15; /* sizeof (double) + alignment */
7368 if (patch_info->type == MONO_PATCH_INFO_R4)
7369 code_size += 4 + 15; /* sizeof (float) + alignment */
7370 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7371 code_size += 8 + 7; /*sizeof (void*) + alignment */
7374 #ifdef __native_client_codegen__
7375 /* Give us extra room on Native Client. This could be */
7376 /* more carefully calculated, but bundle alignment makes */
7377 /* it much trickier, so *2 like other places is good. */
7381 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7382 cfg->code_size *= 2;
7383 cfg->native_code = mono_realloc_native_code (cfg);
7384 cfg->stat_code_reallocs++;
7387 code = cfg->native_code + cfg->code_len;
7389 /* add code to raise exceptions */
7391 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7392 switch (patch_info->type) {
7393 case MONO_PATCH_INFO_EXC: {
7394 MonoClass *exc_class;
7398 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7400 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7401 g_assert (exc_class);
7402 throw_ip = patch_info->ip.i;
7404 //x86_breakpoint (code);
7405 /* Find a throw sequence for the same exception class */
7406 for (i = 0; i < nthrows; ++i)
7407 if (exc_classes [i] == exc_class)
7410 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7411 x86_jump_code (code, exc_throw_start [i]);
7412 patch_info->type = MONO_PATCH_INFO_NONE;
7416 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7420 exc_classes [nthrows] = exc_class;
7421 exc_throw_start [nthrows] = code;
7423 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7425 patch_info->type = MONO_PATCH_INFO_NONE;
7427 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7429 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7434 exc_throw_end [nthrows] = code;
7444 g_assert(code < cfg->native_code + cfg->code_size);
7447 /* Handle relocations with RIP relative addressing */
7448 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7449 gboolean remove = FALSE;
7450 guint8 *orig_code = code;
7452 switch (patch_info->type) {
7453 case MONO_PATCH_INFO_R8:
7454 case MONO_PATCH_INFO_R4: {
7455 guint8 *pos, *patch_pos;
7458 /* The SSE opcodes require a 16 byte alignment */
7459 #if defined(__default_codegen__)
7460 code = (guint8*)ALIGN_TO (code, 16);
7461 #elif defined(__native_client_codegen__)
7463 /* Pad this out with HLT instructions */
7464 /* or we can get garbage bytes emitted */
7465 /* which will fail validation */
7466 guint8 *aligned_code;
7467 /* extra align to make room for */
7468 /* mov/push below */
7469 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7470 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7471 /* The technique of hiding data in an */
7472 /* instruction has a problem here: we */
7473 /* need the data aligned to a 16-byte */
7474 /* boundary but the instruction cannot */
7475 /* cross the bundle boundary. so only */
7476 /* odd multiples of 16 can be used */
7477 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7480 while (code < aligned_code) {
7481 *(code++) = 0xf4; /* hlt */
7486 pos = cfg->native_code + patch_info->ip.i;
7487 if (IS_REX (pos [1])) {
7488 patch_pos = pos + 5;
7489 target_pos = code - pos - 9;
7492 patch_pos = pos + 4;
7493 target_pos = code - pos - 8;
7496 if (patch_info->type == MONO_PATCH_INFO_R8) {
7497 #ifdef __native_client_codegen__
7498 /* Hide 64-bit data in a */
7499 /* "mov imm64, r11" instruction. */
7500 /* write it before the start of */
7502 *(code-2) = 0x49; /* prefix */
7503 *(code-1) = 0xbb; /* mov X, %r11 */
7505 *(double*)code = *(double*)patch_info->data.target;
7506 code += sizeof (double);
7508 #ifdef __native_client_codegen__
7509 /* Hide 32-bit data in a */
7510 /* "push imm32" instruction. */
7511 *(code-1) = 0x68; /* push */
7513 *(float*)code = *(float*)patch_info->data.target;
7514 code += sizeof (float);
7517 *(guint32*)(patch_pos) = target_pos;
7522 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7525 if (cfg->compile_aot)
7528 /*loading is faster against aligned addresses.*/
7529 code = (guint8*)ALIGN_TO (code, 8);
7530 memset (orig_code, 0, code - orig_code);
7532 pos = cfg->native_code + patch_info->ip.i;
7534 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7535 if (IS_REX (pos [1]))
7536 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7538 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7540 *(gpointer*)code = (gpointer)patch_info->data.target;
7541 code += sizeof (gpointer);
7551 if (patch_info == cfg->patch_info)
7552 cfg->patch_info = patch_info->next;
7556 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7558 tmp->next = patch_info->next;
7561 g_assert (code < cfg->native_code + cfg->code_size);
7564 cfg->code_len = code - cfg->native_code;
7566 g_assert (cfg->code_len < cfg->code_size);
7570 #endif /* DISABLE_JIT */
7573 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7576 CallInfo *cinfo = NULL;
7577 MonoMethodSignature *sig;
7579 int i, n, stack_area = 0;
7581 /* Keep this in sync with mono_arch_get_argument_info */
7583 if (enable_arguments) {
7584 /* Allocate a new area on the stack and save arguments there */
7585 sig = mono_method_signature (cfg->method);
7587 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7589 n = sig->param_count + sig->hasthis;
7591 stack_area = ALIGN_TO (n * 8, 16);
7593 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7595 for (i = 0; i < n; ++i) {
7596 inst = cfg->args [i];
7598 if (inst->opcode == OP_REGVAR)
7599 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7601 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7602 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7607 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7608 amd64_set_reg_template (code, AMD64_ARG_REG1);
7609 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7610 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7612 if (enable_arguments)
7613 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7627 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7630 int save_mode = SAVE_NONE;
7631 MonoMethod *method = cfg->method;
7632 MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7635 switch (ret_type->type) {
7636 case MONO_TYPE_VOID:
7637 /* special case string .ctor icall */
7638 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7639 save_mode = SAVE_EAX;
7641 save_mode = SAVE_NONE;
7645 save_mode = SAVE_EAX;
7649 save_mode = SAVE_XMM;
7651 case MONO_TYPE_GENERICINST:
7652 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7653 save_mode = SAVE_EAX;
7657 case MONO_TYPE_VALUETYPE:
7658 save_mode = SAVE_STRUCT;
7661 save_mode = SAVE_EAX;
7665 /* Save the result and copy it into the proper argument register */
7666 switch (save_mode) {
7668 amd64_push_reg (code, AMD64_RAX);
7670 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7671 if (enable_arguments)
7672 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7676 if (enable_arguments)
7677 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7680 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7681 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7683 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7685 * The result is already in the proper argument register so no copying
7692 g_assert_not_reached ();
7695 /* Set %al since this is a varargs call */
7696 if (save_mode == SAVE_XMM)
7697 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7699 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7701 if (preserve_argument_registers) {
7702 for (i = 0; i < PARAM_REGS; ++i)
7703 amd64_push_reg (code, param_regs [i]);
7706 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7707 amd64_set_reg_template (code, AMD64_ARG_REG1);
7708 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7710 if (preserve_argument_registers) {
7711 for (i = PARAM_REGS - 1; i >= 0; --i)
7712 amd64_pop_reg (code, param_regs [i]);
7715 /* Restore result */
7716 switch (save_mode) {
7718 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7719 amd64_pop_reg (code, AMD64_RAX);
7725 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7726 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7727 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7732 g_assert_not_reached ();
7739 mono_arch_flush_icache (guint8 *code, gint size)
7745 mono_arch_flush_register_windows (void)
7750 mono_arch_is_inst_imm (gint64 imm)
7752 return amd64_is_imm32 (imm);
7756 * Determine whenever the trap whose info is in SIGINFO is caused by
7760 mono_arch_is_int_overflow (void *sigctx, void *info)
7767 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7769 rip = (guint8*)ctx.rip;
7771 if (IS_REX (rip [0])) {
7772 reg = amd64_rex_b (rip [0]);
7778 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7780 reg += x86_modrm_rm (rip [1]);
7820 g_assert_not_reached ();
7832 mono_arch_get_patch_offset (guint8 *code)
7838 * mono_breakpoint_clean_code:
7840 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7841 * breakpoints in the original code, they are removed in the copy.
7843 * Returns TRUE if no sw breakpoint was present.
7846 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7849 gboolean can_write = TRUE;
7851 * If method_start is non-NULL we need to perform bound checks, since we access memory
7852 * at code - offset we could go before the start of the method and end up in a different
7853 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7856 if (!method_start || code - offset >= method_start) {
7857 memcpy (buf, code - offset, size);
7859 int diff = code - method_start;
7860 memset (buf, 0, size);
7861 memcpy (buf + offset - diff, method_start, diff + size - offset);
7864 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7865 int idx = mono_breakpoint_info_index [i];
7869 ptr = mono_breakpoint_info [idx].address;
7870 if (ptr >= code && ptr < code + size) {
7871 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7873 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7874 buf [ptr - code] = saved_byte;
7880 #if defined(__native_client_codegen__)
7881 /* For membase calls, we want the base register. for Native Client, */
7882 /* all indirect calls have the following sequence with the given sizes: */
7883 /* mov %eXX,%eXX [2-3] */
7884 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7885 /* and $0xffffffffffffffe0,%r11d [4] */
7886 /* add %r15,%r11 [3] */
7887 /* callq *%r11 [3] */
7890 /* Determine if code points to a NaCl call-through-register sequence, */
7891 /* (i.e., the last 3 instructions listed above) */
7893 is_nacl_call_reg_sequence(guint8* code)
7895 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7896 "\x4d\x03\xdf" /* add */
7897 "\x41\xff\xd3"; /* call */
7898 return memcmp(code, sequence, 10) == 0;
7901 /* Determine if code points to the first opcode of the mov membase component */
7902 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7903 /* (there could be a REX prefix before the opcode but it is ignored) */
7905 is_nacl_indirect_call_membase_sequence(guint8* code)
7907 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7908 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7909 /* and that src reg = dest reg */
7910 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7911 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7913 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7914 /* and has dst of r11 and base of r15 */
7915 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7916 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7918 #endif /* __native_client_codegen__ */
7921 mono_arch_get_this_arg_reg (guint8 *code)
7923 return AMD64_ARG_REG1;
7927 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7929 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7932 #define MAX_ARCH_DELEGATE_PARAMS 10
7935 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7937 guint8 *code, *start;
7941 start = code = mono_global_codeman_reserve (64);
7943 /* Replace the this argument with the target */
7944 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7945 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7946 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7948 g_assert ((code - start) < 64);
7950 start = code = mono_global_codeman_reserve (64);
7952 if (param_count == 0) {
7953 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7955 /* We have to shift the arguments left */
7956 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7957 for (i = 0; i < param_count; ++i) {
7960 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7962 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7964 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7968 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7970 g_assert ((code - start) < 64);
7973 nacl_global_codeman_validate(&start, 64, &code);
7975 mono_debug_add_delegate_trampoline (start, code - start);
7978 *code_len = code - start;
7981 if (mono_jit_map_is_enabled ()) {
7984 buff = (char*)"delegate_invoke_has_target";
7986 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7987 mono_emit_jit_tramp (start, code - start, buff);
7996 * mono_arch_get_delegate_invoke_impls:
7998 * Return a list of MonoTrampInfo structures for the delegate invoke impl
8002 mono_arch_get_delegate_invoke_impls (void)
8010 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
8011 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
8013 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
8014 code = get_delegate_invoke_impl (FALSE, i, &code_len);
8015 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
8016 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
8017 g_free (tramp_name);
8024 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8026 guint8 *code, *start;
8029 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8032 /* FIXME: Support more cases */
8033 if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
8037 static guint8* cached = NULL;
8043 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8045 start = get_delegate_invoke_impl (TRUE, 0, NULL);
8047 mono_memory_barrier ();
8051 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8052 for (i = 0; i < sig->param_count; ++i)
8053 if (!mono_is_regsize_var (sig->params [i]))
8055 if (sig->param_count > 4)
8058 code = cache [sig->param_count];
8062 if (mono_aot_only) {
8063 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8064 start = mono_aot_get_trampoline (name);
8067 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8070 mono_memory_barrier ();
8072 cache [sig->param_count] = start;
8078 mono_arch_finish_init (void)
8082 * We need to init this multiple times, since when we are first called, the key might not
8083 * be initialized yet.
8085 jit_tls_offset = mono_get_jit_tls_key ();
8087 /* Only 64 tls entries can be accessed using inline code */
8088 if (jit_tls_offset >= 64)
8089 jit_tls_offset = -1;
8092 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8098 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8102 #ifdef MONO_ARCH_HAVE_IMT
8104 #if defined(__default_codegen__)
8105 #define CMP_SIZE (6 + 1)
8106 #define CMP_REG_REG_SIZE (4 + 1)
8107 #define BR_SMALL_SIZE 2
8108 #define BR_LARGE_SIZE 6
8109 #define MOV_REG_IMM_SIZE 10
8110 #define MOV_REG_IMM_32BIT_SIZE 6
8111 #define JUMP_REG_SIZE (2 + 1)
8112 #elif defined(__native_client_codegen__)
8113 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8114 #define CMP_SIZE ((6 + 1) * 2 - 1)
8115 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8116 #define BR_SMALL_SIZE (2 * 2 - 1)
8117 #define BR_LARGE_SIZE (6 * 2 - 1)
8118 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8119 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8120 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8121 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8122 /* Jump membase's size is large and unpredictable */
8123 /* in native client, just pad it out a whole bundle. */
8124 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8128 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8130 int i, distance = 0;
8131 for (i = start; i < target; ++i)
8132 distance += imt_entries [i]->chunk_size;
8137 * LOCKING: called with the domain lock held
8140 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8141 gpointer fail_tramp)
8145 guint8 *code, *start;
8146 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8148 for (i = 0; i < count; ++i) {
8149 MonoIMTCheckItem *item = imt_entries [i];
8150 if (item->is_equals) {
8151 if (item->check_target_idx) {
8152 if (!item->compare_done) {
8153 if (amd64_is_imm32 (item->key))
8154 item->chunk_size += CMP_SIZE;
8156 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8158 if (item->has_target_code) {
8159 item->chunk_size += MOV_REG_IMM_SIZE;
8161 if (vtable_is_32bit)
8162 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8164 item->chunk_size += MOV_REG_IMM_SIZE;
8165 #ifdef __native_client_codegen__
8166 item->chunk_size += JUMP_MEMBASE_SIZE;
8169 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8172 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8173 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8175 if (vtable_is_32bit)
8176 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8178 item->chunk_size += MOV_REG_IMM_SIZE;
8179 item->chunk_size += JUMP_REG_SIZE;
8180 /* with assert below:
8181 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8183 #ifdef __native_client_codegen__
8184 item->chunk_size += JUMP_MEMBASE_SIZE;
8189 if (amd64_is_imm32 (item->key))
8190 item->chunk_size += CMP_SIZE;
8192 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8193 item->chunk_size += BR_LARGE_SIZE;
8194 imt_entries [item->check_target_idx]->compare_done = TRUE;
8196 size += item->chunk_size;
8198 #if defined(__native_client__) && defined(__native_client_codegen__)
8199 /* In Native Client, we don't re-use thunks, allocate from the */
8200 /* normal code manager paths. */
8201 code = mono_domain_code_reserve (domain, size);
8204 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8206 code = mono_domain_code_reserve (domain, size);
8209 for (i = 0; i < count; ++i) {
8210 MonoIMTCheckItem *item = imt_entries [i];
8211 item->code_target = code;
8212 if (item->is_equals) {
8213 gboolean fail_case = !item->check_target_idx && fail_tramp;
8215 if (item->check_target_idx || fail_case) {
8216 if (!item->compare_done || fail_case) {
8217 if (amd64_is_imm32 (item->key))
8218 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8220 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8221 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8224 item->jmp_code = code;
8225 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8226 if (item->has_target_code) {
8227 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8228 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8230 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8231 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8235 amd64_patch (item->jmp_code, code);
8236 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8237 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8238 item->jmp_code = NULL;
8241 /* enable the commented code to assert on wrong method */
8243 if (amd64_is_imm32 (item->key))
8244 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8246 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8247 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8249 item->jmp_code = code;
8250 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8251 /* See the comment below about R10 */
8252 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8253 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8254 amd64_patch (item->jmp_code, code);
8255 amd64_breakpoint (code);
8256 item->jmp_code = NULL;
8258 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8259 needs to be preserved. R10 needs
8260 to be preserved for calls which
8261 require a runtime generic context,
8262 but interface calls don't. */
8263 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8264 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8268 if (amd64_is_imm32 (item->key))
8269 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8271 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8272 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8274 item->jmp_code = code;
8275 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8276 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8278 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8280 g_assert (code - item->code_target <= item->chunk_size);
8282 /* patch the branches to get to the target items */
8283 for (i = 0; i < count; ++i) {
8284 MonoIMTCheckItem *item = imt_entries [i];
8285 if (item->jmp_code) {
8286 if (item->check_target_idx) {
8287 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8293 mono_stats.imt_thunks_size += code - start;
8294 g_assert (code - start <= size);
8296 nacl_domain_code_validate(domain, &start, size, &code);
8302 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8304 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8309 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8311 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8315 mono_arch_get_cie_program (void)
8319 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8320 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8326 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8328 MonoInst *ins = NULL;
8331 if (cmethod->klass == mono_defaults.math_class) {
8332 if (strcmp (cmethod->name, "Sin") == 0) {
8334 } else if (strcmp (cmethod->name, "Cos") == 0) {
8336 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8338 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8343 MONO_INST_NEW (cfg, ins, opcode);
8344 ins->type = STACK_R8;
8345 ins->dreg = mono_alloc_freg (cfg);
8346 ins->sreg1 = args [0]->dreg;
8347 MONO_ADD_INS (cfg->cbb, ins);
8351 if (cfg->opt & MONO_OPT_CMOV) {
8352 if (strcmp (cmethod->name, "Min") == 0) {
8353 if (fsig->params [0]->type == MONO_TYPE_I4)
8355 if (fsig->params [0]->type == MONO_TYPE_U4)
8356 opcode = OP_IMIN_UN;
8357 else if (fsig->params [0]->type == MONO_TYPE_I8)
8359 else if (fsig->params [0]->type == MONO_TYPE_U8)
8360 opcode = OP_LMIN_UN;
8361 } else if (strcmp (cmethod->name, "Max") == 0) {
8362 if (fsig->params [0]->type == MONO_TYPE_I4)
8364 if (fsig->params [0]->type == MONO_TYPE_U4)
8365 opcode = OP_IMAX_UN;
8366 else if (fsig->params [0]->type == MONO_TYPE_I8)
8368 else if (fsig->params [0]->type == MONO_TYPE_U8)
8369 opcode = OP_LMAX_UN;
8374 MONO_INST_NEW (cfg, ins, opcode);
8375 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8376 ins->dreg = mono_alloc_ireg (cfg);
8377 ins->sreg1 = args [0]->dreg;
8378 ins->sreg2 = args [1]->dreg;
8379 MONO_ADD_INS (cfg->cbb, ins);
8383 /* OP_FREM is not IEEE compatible */
8384 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8385 MONO_INST_NEW (cfg, ins, OP_FREM);
8386 ins->inst_i0 = args [0];
8387 ins->inst_i1 = args [1];
8393 * Can't implement CompareExchange methods this way since they have
8401 mono_arch_print_tree (MonoInst *tree, int arity)
8406 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8409 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8412 case AMD64_RCX: return ctx->rcx;
8413 case AMD64_RDX: return ctx->rdx;
8414 case AMD64_RBX: return ctx->rbx;
8415 case AMD64_RBP: return ctx->rbp;
8416 case AMD64_RSP: return ctx->rsp;
8418 return _CTX_REG (ctx, rax, reg);
8423 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8442 _CTX_REG (ctx, rax, reg) = val;
8446 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8448 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8451 gpointer *sp, old_value;
8453 const unsigned char *handler;
8455 /*Decode the first instruction to figure out where did we store the spvar*/
8456 /*Our jit MUST generate the following:
8459 Which is encoded as: REX.W 0x89 mod_rm
8460 mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8461 mod (reg + imm8): 01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8462 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8464 FIXME can we generate frameless methods on this case?
8467 handler = clause->handler_start;
8470 if (*handler != 0x48)
8475 if (*handler != 0x89)
8479 if (*handler == 0x65)
8480 offset = *(signed char*)(handler + 1);
8481 else if (*handler == 0xA5)
8482 offset = *(int*)(handler + 1);
8487 bp = MONO_CONTEXT_GET_BP (ctx);
8488 sp = *(gpointer*)(bp + offset);
8491 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8500 * mono_arch_emit_load_aotconst:
8502 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8503 * TARGET from the mscorlib GOT in full-aot code.
8504 * On AMD64, the result is placed into R11.
8507 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8509 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8510 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8516 * mono_arch_get_trampolines:
8518 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8522 mono_arch_get_trampolines (gboolean aot)
8524 return mono_amd64_get_exception_trampolines (aot);
8527 /* Soft Debug support */
8528 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8531 * mono_arch_set_breakpoint:
8533 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8534 * The location should contain code emitted by OP_SEQ_POINT.
8537 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8540 guint8 *orig_code = code;
8543 guint32 native_offset = ip - (guint8*)ji->code_start;
8544 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8546 g_assert (info->bp_addrs [native_offset] == 0);
8547 info->bp_addrs [native_offset] = bp_trigger_page;
8550 * In production, we will use int3 (has to fix the size in the md
8551 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8554 g_assert (code [0] == 0x90);
8555 if (breakpoint_size == 8) {
8556 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8558 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8559 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8562 g_assert (code - orig_code == breakpoint_size);
8567 * mono_arch_clear_breakpoint:
8569 * Clear the breakpoint at IP.
8572 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8578 guint32 native_offset = ip - (guint8*)ji->code_start;
8579 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8581 g_assert (info->bp_addrs [native_offset] == 0);
8582 info->bp_addrs [native_offset] = info;
8584 for (i = 0; i < breakpoint_size; ++i)
8590 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8593 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8596 siginfo_t* sinfo = (siginfo_t*) info;
8597 /* Sometimes the address is off by 4 */
8598 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8606 * mono_arch_skip_breakpoint:
8608 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8609 * we resume, the instruction is not executed again.
8612 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8615 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8616 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8618 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8623 * mono_arch_start_single_stepping:
8625 * Start single stepping.
8628 mono_arch_start_single_stepping (void)
8630 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8634 * mono_arch_stop_single_stepping:
8636 * Stop single stepping.
8639 mono_arch_stop_single_stepping (void)
8641 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8645 * mono_arch_is_single_step_event:
8647 * Return whenever the machine state in SIGCTX corresponds to a single
8651 mono_arch_is_single_step_event (void *info, void *sigctx)
8654 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8657 siginfo_t* sinfo = (siginfo_t*) info;
8658 /* Sometimes the address is off by 4 */
8659 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8667 * mono_arch_skip_single_step:
8669 * Modify CTX so the ip is placed after the single step trigger instruction,
8670 * we resume, the instruction is not executed again.
8673 mono_arch_skip_single_step (MonoContext *ctx)
8675 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8679 * mono_arch_create_seq_point_info:
8681 * Return a pointer to a data structure which is used by the sequence
8682 * point implementation in AOTed code.
8685 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8691 // FIXME: Add a free function
8693 mono_domain_lock (domain);
8694 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8696 mono_domain_unlock (domain);
8699 ji = mono_jit_info_table_find (domain, (char*)code);
8702 // FIXME: Optimize the size
8703 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8705 info->ss_trigger_page = ss_trigger_page;
8706 info->bp_trigger_page = bp_trigger_page;
8707 /* Initialize to a valid address */
8708 for (i = 0; i < ji->code_size; ++i)
8709 info->bp_addrs [i] = info;
8711 mono_domain_lock (domain);
8712 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8714 mono_domain_unlock (domain);
8721 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8723 ext->lmf.previous_lmf = prev_lmf;
8724 /* Mark that this is a MonoLMFExt */
8725 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8726 ext->lmf.rsp = (gssize)ext;