mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 /*
  72  * The code generated for sequence points reads from this location, which is
  73  * made read-only when single stepping is enabled.
  74  */
  75 static gpointer ss_trigger_page;
  76
  77 /* Enabled breakpoints read from this trigger page */
  78 static gpointer bp_trigger_page;
  79
  80 /* The size of the breakpoint sequence */
  81 static int breakpoint_size;
  82
  83 /* The size of the breakpoint instruction causing the actual fault */
  84 static int breakpoint_fault_size;
  85
  86 /* The size of the single step instruction causing the actual fault */
  87 static int single_step_fault_size;
  88
  89 /* The single step trampoline */
  90 static gpointer ss_trampoline;
  91
  92 /* Offset between fp and the first argument in the callee */
  93 #define ARGS_OFFSET 16
  94 #define GP_SCRATCH_REG AMD64_R11
  95
  96 /*
  97  * AMD64 register usage:
  98  * - callee saved registers are used for global register allocation
  99  * - %r11 is used for materializing 64 bit constants in opcodes
 100  * - the rest is used for local allocation
 101  */
 102
 103 /*
 104  * Floating point comparison results:
 105  *                  ZF PF CF
 106  * A > B            0  0  0
 107  * A < B            0  0  1
 108  * A = B            1  0  0
 109  * A > B            0  0  0
 110  * UNORDERED        1  1  1
 111  */
 112
 113 const char*
 114 mono_arch_regname (int reg)
 115 {
 116         switch (reg) {
 117         case AMD64_RAX: return "%rax";
 118         case AMD64_RBX: return "%rbx";
 119         case AMD64_RCX: return "%rcx";
 120         case AMD64_RDX: return "%rdx";
 121         case AMD64_RSP: return "%rsp";
 122         case AMD64_RBP: return "%rbp";
 123         case AMD64_RDI: return "%rdi";
 124         case AMD64_RSI: return "%rsi";
 125         case AMD64_R8: return "%r8";
 126         case AMD64_R9: return "%r9";
 127         case AMD64_R10: return "%r10";
 128         case AMD64_R11: return "%r11";
 129         case AMD64_R12: return "%r12";
 130         case AMD64_R13: return "%r13";
 131         case AMD64_R14: return "%r14";
 132         case AMD64_R15: return "%r15";
 133         }
 134         return "unknown";
 135 }
 136
 137 static const char * packed_xmmregs [] = {
 138         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 139         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 140 };
 141
 142 static const char * single_xmmregs [] = {
 143         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 144         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 145 };
 146
 147 const char*
 148 mono_arch_fregname (int reg)
 149 {
 150         if (reg < AMD64_XMM_NREG)
 151                 return single_xmmregs [reg];
 152         else
 153                 return "unknown";
 154 }
 155
 156 const char *
 157 mono_arch_xregname (int reg)
 158 {
 159         if (reg < AMD64_XMM_NREG)
 160                 return packed_xmmregs [reg];
 161         else
 162                 return "unknown";
 163 }
 164
 165 static gboolean
 166 debug_omit_fp (void)
 167 {
 168 #if 0
 169         return mono_debug_count ();
 170 #else
 171         return TRUE;
 172 #endif
 173 }
 174
 175 static inline gboolean
 176 amd64_is_near_call (guint8 *code)
 177 {
 178         /* Skip REX */
 179         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 180                 code += 1;
 181
 182         return code [0] == 0xe8;
 183 }
 184
 185 #ifdef __native_client_codegen__
 186
 187 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 188 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 189 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 190 /* We only want to force bundle alignment for the top level instruction,    */
 191 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 192 static MonoNativeTlsKey nacl_instruction_depth;
 193
 194 static MonoNativeTlsKey nacl_rex_tag;
 195 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 196
 197 void
 198 amd64_nacl_clear_legacy_prefix_tag ()
 199 {
 200         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 201 }
 202
 203 void
 204 amd64_nacl_tag_legacy_prefix (guint8* code)
 205 {
 206         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 207                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 208 }
 209
 210 void
 211 amd64_nacl_tag_rex (guint8* code)
 212 {
 213         mono_native_tls_set_value (nacl_rex_tag, code);
 214 }
 215
 216 guint8*
 217 amd64_nacl_get_legacy_prefix_tag ()
 218 {
 219         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 220 }
 221
 222 guint8*
 223 amd64_nacl_get_rex_tag ()
 224 {
 225         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 226 }
 227
 228 /* Increment the instruction "depth" described above */
 229 void
 230 amd64_nacl_instruction_pre ()
 231 {
 232         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 233         depth++;
 234         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 235 }
 236
 237 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 238 /* alignment if depth == 0 (top level instruction)                          */
 239 /* IN: start, end    pointers to instruction beginning and end              */
 240 /* OUT: start, end   pointers to beginning and end after possible alignment */
 241 /* GLOBALS: nacl_instruction_depth     defined above                        */
 242 void
 243 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 244 {
 245         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 246         depth--;
 247         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 248
 249         g_assert ( depth >= 0 );
 250         if (depth == 0) {
 251                 uintptr_t space_in_block;
 252                 uintptr_t instlen;
 253                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 254                 /* if legacy prefix is present, and if it was emitted before */
 255                 /* the start of the instruction sequence, adjust the start   */
 256                 if (prefix != NULL && prefix < *start) {
 257                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 258                         *start = prefix;
 259                 }
 260                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 261                 instlen = (uintptr_t)(*end - *start);
 262                 /* Only check for instructions which are less than        */
 263                 /* kNaClAlignment. The only instructions that should ever */
 264                 /* be that long are call sequences, which are already     */
 265                 /* padded out to align the return to the next bundle.     */
 266                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 267                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 268                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 269                         const size_t length = (size_t)((*end)-(*start));
 270                         g_assert (length < MAX_NACL_INST_LENGTH);
 271
 272                         memcpy (copy_of_instruction, *start, length);
 273                         *start = mono_arch_nacl_pad (*start, space_in_block);
 274                         memcpy (*start, copy_of_instruction, length);
 275                         *end = *start + length;
 276                 }
 277                 amd64_nacl_clear_legacy_prefix_tag ();
 278                 amd64_nacl_tag_rex (NULL);
 279         }
 280 }
 281
 282 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 283 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 284 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 285 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 286 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 287 /* IN:      code                                                            */
 288 /*             pointer to current instruction stream (in the                */
 289 /*             middle of an instruction, after opcode is emitted)           */
 290 /*          basereg/offset/dreg                                             */
 291 /*             operands of normal membase address                           */
 292 /* OUT:     code                                                            */
 293 /*             pointer to the end of the membase/memindex emit              */
 294 /* GLOBALS: nacl_rex_tag                                                    */
 295 /*             position in instruction stream that rex prefix was emitted   */
 296 /*          nacl_legacy_prefix_tag                                          */
 297 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 298 void
 299 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 300 {
 301         gint8 true_basereg = basereg;
 302
 303         /* Cache these values, they might change  */
 304         /* as new instructions are emitted below. */
 305         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 306         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 307
 308         /* 'basereg' is given masked to 0x7 at this point, so check */
 309         /* the rex prefix to see if this is an extended register.   */
 310         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 311                 true_basereg |= 0x8;
 312         }
 313
 314 #define X86_LEA_OPCODE (0x8D)
 315
 316         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 317                 guint8* old_instruction_start;
 318
 319                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 320                 /* 32-bits of the old base register (new index register)     */
 321                 guint8 buf[32];
 322                 guint8* buf_ptr = buf;
 323                 size_t insert_len;
 324
 325                 g_assert (rex_tag != NULL);
 326
 327                 if (IS_REX(*rex_tag)) {
 328                         /* The old rex.B should be the new rex.X */
 329                         if (*rex_tag & AMD64_REX_B) {
 330                                 *rex_tag |= AMD64_REX_X;
 331                         }
 332                         /* Since our new base is %r15 set rex.B */
 333                         *rex_tag |= AMD64_REX_B;
 334                 } else {
 335                         /* Shift the instruction by one byte  */
 336                         /* so we can insert a rex prefix      */
 337                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 338                         *code += 1;
 339                         /* New rex prefix only needs rex.B for %r15 base */
 340                         *rex_tag = AMD64_REX(AMD64_REX_B);
 341                 }
 342
 343                 if (legacy_prefix_tag) {
 344                         old_instruction_start = legacy_prefix_tag;
 345                 } else {
 346                         old_instruction_start = rex_tag;
 347                 }
 348
 349                 /* Clears the upper 32-bits of the previous base register */
 350                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 351                 insert_len = buf_ptr - buf;
 352
 353                 /* Move the old instruction forward to make */
 354                 /* room for 'mov' stored in 'buf_ptr'       */
 355                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 356                 *code += insert_len;
 357                 memcpy (old_instruction_start, buf, insert_len);
 358
 359                 /* Sandboxed replacement for the normal membase_emit */
 360                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 361
 362         } else {
 363                 /* Normal default behavior, emit membase memory location */
 364                 x86_membase_emit_body (*code, dreg, basereg, offset);
 365         }
 366 }
 367
 368
 369 static inline unsigned char*
 370 amd64_skip_nops (unsigned char* code)
 371 {
 372         guint8 in_nop;
 373         do {
 374                 in_nop = 0;
 375                 if (   code[0] == 0x90) {
 376                         in_nop = 1;
 377                         code += 1;
 378                 }
 379                 if (   code[0] == 0x66 && code[1] == 0x90) {
 380                         in_nop = 1;
 381                         code += 2;
 382                 }
 383                 if (code[0] == 0x0f && code[1] == 0x1f
 384                  && code[2] == 0x00) {
 385                         in_nop = 1;
 386                         code += 3;
 387                 }
 388                 if (code[0] == 0x0f && code[1] == 0x1f
 389                  && code[2] == 0x40 && code[3] == 0x00) {
 390                         in_nop = 1;
 391                         code += 4;
 392                 }
 393                 if (code[0] == 0x0f && code[1] == 0x1f
 394                  && code[2] == 0x44 && code[3] == 0x00
 395                  && code[4] == 0x00) {
 396                         in_nop = 1;
 397                         code += 5;
 398                 }
 399                 if (code[0] == 0x66 && code[1] == 0x0f
 400                  && code[2] == 0x1f && code[3] == 0x44
 401                  && code[4] == 0x00 && code[5] == 0x00) {
 402                         in_nop = 1;
 403                         code += 6;
 404                 }
 405                 if (code[0] == 0x0f && code[1] == 0x1f
 406                  && code[2] == 0x80 && code[3] == 0x00
 407                  && code[4] == 0x00 && code[5] == 0x00
 408                  && code[6] == 0x00) {
 409                         in_nop = 1;
 410                         code += 7;
 411                 }
 412                 if (code[0] == 0x0f && code[1] == 0x1f
 413                  && code[2] == 0x84 && code[3] == 0x00
 414                  && code[4] == 0x00 && code[5] == 0x00
 415                  && code[6] == 0x00 && code[7] == 0x00) {
 416                         in_nop = 1;
 417                         code += 8;
 418                 }
 419         } while ( in_nop );
 420         return code;
 421 }
 422
 423 guint8*
 424 mono_arch_nacl_skip_nops (guint8* code)
 425 {
 426   return amd64_skip_nops(code);
 427 }
 428
 429 #endif /*__native_client_codegen__*/
 430
 431 static inline void
 432 amd64_patch (unsigned char* code, gpointer target)
 433 {
 434         guint8 rex = 0;
 435
 436 #ifdef __native_client_codegen__
 437         code = amd64_skip_nops (code);
 438 #endif
 439 #if defined(__native_client_codegen__) && defined(__native_client__)
 440         if (nacl_is_code_address (code)) {
 441                 /* For tail calls, code is patched after being installed */
 442                 /* but not through the normal "patch callsite" method.   */
 443                 unsigned char buf[kNaClAlignment];
 444                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 445                 int ret;
 446                 memcpy (buf, aligned_code, kNaClAlignment);
 447                 /* Patch a temp buffer of bundle size, */
 448                 /* then install to actual location.    */
 449                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 450                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 451                 g_assert (ret == 0);
 452                 return;
 453         }
 454         target = nacl_modify_patch_target (target);
 455 #endif
 456
 457         /* Skip REX */
 458         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 459                 rex = code [0];
 460                 code += 1;
 461         }
 462
 463         if ((code [0] & 0xf8) == 0xb8) {
 464                 /* amd64_set_reg_template */
 465                 *(guint64*)(code + 1) = (guint64)target;
 466         }
 467         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 468                 /* mov 0(%rip), %dreg */
 469                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 470         }
 471         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 472                 /* call *<OFFSET>(%rip) */
 473                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 474         }
 475         else if (code [0] == 0xe8) {
 476                 /* call <DISP> */
 477                 gint64 disp = (guint8*)target - (guint8*)code;
 478                 g_assert (amd64_is_imm32 (disp));
 479                 x86_patch (code, (unsigned char*)target);
 480         }
 481         else
 482                 x86_patch (code, (unsigned char*)target);
 483 }
 484
 485 void
 486 mono_amd64_patch (unsigned char* code, gpointer target)
 487 {
 488         amd64_patch (code, target);
 489 }
 490
 491 typedef enum {
 492         ArgInIReg,
 493         ArgInFloatSSEReg,
 494         ArgInDoubleSSEReg,
 495         ArgOnStack,
 496         ArgValuetypeInReg,
 497         ArgValuetypeAddrInIReg,
 498         ArgNone /* only in pair_storage */
 499 } ArgStorage;
 500
 501 typedef struct {
 502         gint16 offset;
 503         gint8  reg;
 504         ArgStorage storage;
 505
 506         /* Only if storage == ArgValuetypeInReg */
 507         ArgStorage pair_storage [2];
 508         gint8 pair_regs [2];
 509         /* The size of each pair */
 510         int pair_size [2];
 511         int nregs;
 512 } ArgInfo;
 513
 514 typedef struct {
 515         int nargs;
 516         guint32 stack_usage;
 517         guint32 reg_usage;
 518         guint32 freg_usage;
 519         gboolean need_stack_align;
 520         gboolean vtype_retaddr;
 521         /* The index of the vret arg in the argument list */
 522         int vret_arg_index;
 523         ArgInfo ret;
 524         ArgInfo sig_cookie;
 525         ArgInfo args [1];
 526 } CallInfo;
 527
 528 #define DEBUG(a) if (cfg->verbose_level > 1) a
 529
 530 #ifdef TARGET_WIN32
 531 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 532
 533 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #else
 535 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 536
 537  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 538 #endif
 539
 540 static void inline
 541 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 542 {
 543     ainfo->offset = *stack_size;
 544
 545     if (*gr >= PARAM_REGS) {
 546                 ainfo->storage = ArgOnStack;
 547                 /* Since the same stack slot size is used for all arg */
 548                 /*  types, it needs to be big enough to hold them all */
 549                 (*stack_size) += sizeof(mgreg_t);
 550     }
 551     else {
 552                 ainfo->storage = ArgInIReg;
 553                 ainfo->reg = param_regs [*gr];
 554                 (*gr) ++;
 555     }
 556 }
 557
 558 #ifdef TARGET_WIN32
 559 #define FLOAT_PARAM_REGS 4
 560 #else
 561 #define FLOAT_PARAM_REGS 8
 562 #endif
 563
 564 static void inline
 565 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 566 {
 567     ainfo->offset = *stack_size;
 568
 569     if (*gr >= FLOAT_PARAM_REGS) {
 570                 ainfo->storage = ArgOnStack;
 571                 /* Since the same stack slot size is used for both float */
 572                 /*  types, it needs to be big enough to hold them both */
 573                 (*stack_size) += sizeof(mgreg_t);
 574     }
 575     else {
 576                 /* A double register */
 577                 if (is_double)
 578                         ainfo->storage = ArgInDoubleSSEReg;
 579                 else
 580                         ainfo->storage = ArgInFloatSSEReg;
 581                 ainfo->reg = *gr;
 582                 (*gr) += 1;
 583     }
 584 }
 585
 586 typedef enum ArgumentClass {
 587         ARG_CLASS_NO_CLASS,
 588         ARG_CLASS_MEMORY,
 589         ARG_CLASS_INTEGER,
 590         ARG_CLASS_SSE
 591 } ArgumentClass;
 592
 593 static ArgumentClass
 594 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 595 {
 596         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 597         MonoType *ptype;
 598
 599         ptype = mini_type_get_underlying_type (gsctx, type);
 600         switch (ptype->type) {
 601         case MONO_TYPE_I1:
 602         case MONO_TYPE_U1:
 603         case MONO_TYPE_I2:
 604         case MONO_TYPE_U2:
 605         case MONO_TYPE_I4:
 606         case MONO_TYPE_U4:
 607         case MONO_TYPE_I:
 608         case MONO_TYPE_U:
 609         case MONO_TYPE_STRING:
 610         case MONO_TYPE_OBJECT:
 611         case MONO_TYPE_CLASS:
 612         case MONO_TYPE_SZARRAY:
 613         case MONO_TYPE_PTR:
 614         case MONO_TYPE_FNPTR:
 615         case MONO_TYPE_ARRAY:
 616         case MONO_TYPE_I8:
 617         case MONO_TYPE_U8:
 618                 class2 = ARG_CLASS_INTEGER;
 619                 break;
 620         case MONO_TYPE_R4:
 621         case MONO_TYPE_R8:
 622 #ifdef TARGET_WIN32
 623                 class2 = ARG_CLASS_INTEGER;
 624 #else
 625                 class2 = ARG_CLASS_SSE;
 626 #endif
 627                 break;
 628
 629         case MONO_TYPE_TYPEDBYREF:
 630                 g_assert_not_reached ();
 631
 632         case MONO_TYPE_GENERICINST:
 633                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 634                         class2 = ARG_CLASS_INTEGER;
 635                         break;
 636                 }
 637                 /* fall through */
 638         case MONO_TYPE_VALUETYPE: {
 639                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 640                 int i;
 641
 642                 for (i = 0; i < info->num_fields; ++i) {
 643                         class2 = class1;
 644                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 645                 }
 646                 break;
 647         }
 648         default:
 649                 g_assert_not_reached ();
 650         }
 651
 652         /* Merge */
 653         if (class1 == class2)
 654                 ;
 655         else if (class1 == ARG_CLASS_NO_CLASS)
 656                 class1 = class2;
 657         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 658                 class1 = ARG_CLASS_MEMORY;
 659         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 660                 class1 = ARG_CLASS_INTEGER;
 661         else
 662                 class1 = ARG_CLASS_SSE;
 663
 664         return class1;
 665 }
 666 #ifdef __native_client_codegen__
 667
 668 /* Default alignment for Native Client is 32-byte. */
 669 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 670
 671 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 672 /* Check that alignment doesn't cross an alignment boundary.             */
 673 guint8*
 674 mono_arch_nacl_pad(guint8 *code, int pad)
 675 {
 676         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 677
 678         if (pad == 0) return code;
 679         /* assertion: alignment cannot cross a block boundary */
 680         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 681                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 682         while (pad >= kMaxPadding) {
 683                 amd64_padding (code, kMaxPadding);
 684                 pad -= kMaxPadding;
 685         }
 686         if (pad != 0) amd64_padding (code, pad);
 687         return code;
 688 }
 689 #endif
 690
 691 static int
 692 count_fields_nested (MonoClass *klass)
 693 {
 694         MonoMarshalType *info;
 695         int i, count;
 696
 697         info = mono_marshal_load_type_info (klass);
 698         g_assert(info);
 699         count = 0;
 700         for (i = 0; i < info->num_fields; ++i) {
 701                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 702                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 703                 else
 704                         count ++;
 705         }
 706         return count;
 707 }
 708
 709 static int
 710 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 711 {
 712         MonoMarshalType *info;
 713         int i;
 714
 715         info = mono_marshal_load_type_info (klass);
 716         g_assert(info);
 717         for (i = 0; i < info->num_fields; ++i) {
 718                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 719                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 720                 } else {
 721                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 722                         fields [index].offset += offset;
 723                         index ++;
 724                 }
 725         }
 726         return index;
 727 }
 728
 729 static void
 730 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 731                            gboolean is_return,
 732                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 733 {
 734         guint32 size, quad, nquads, i, nfields;
 735         /* Keep track of the size used in each quad so we can */
 736         /* use the right size when copying args/return vars.  */
 737         guint32 quadsize [2] = {8, 8};
 738         ArgumentClass args [2];
 739         MonoMarshalType *info = NULL;
 740         MonoMarshalField *fields = NULL;
 741         MonoClass *klass;
 742         MonoGenericSharingContext tmp_gsctx;
 743         gboolean pass_on_stack = FALSE;
 744
 745         /*
 746          * The gsctx currently contains no data, it is only used for checking whenever
 747          * open types are allowed, some callers like mono_arch_get_argument_info ()
 748          * don't pass it to us, so work around that.
 749          */
 750         if (!gsctx)
 751                 gsctx = &tmp_gsctx;
 752
 753         klass = mono_class_from_mono_type (type);
 754         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 755 #ifndef TARGET_WIN32
 756         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 757                 /* We pass and return vtypes of size 8 in a register */
 758         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 759                 pass_on_stack = TRUE;
 760         }
 761 #else
 762         if (!sig->pinvoke) {
 763                 pass_on_stack = TRUE;
 764         }
 765 #endif
 766
 767         /* If this struct can't be split up naturally into 8-byte */
 768         /* chunks (registers), pass it on the stack.              */
 769         if (sig->pinvoke && !pass_on_stack) {
 770                 guint32 align;
 771                 guint32 field_size;
 772
 773                 info = mono_marshal_load_type_info (klass);
 774                 g_assert (info);
 775
 776                 /*
 777                  * Collect field information recursively to be able to
 778                  * handle nested structures.
 779                  */
 780                 nfields = count_fields_nested (klass);
 781                 fields = g_new0 (MonoMarshalField, nfields);
 782                 collect_field_info_nested (klass, fields, 0, 0);
 783
 784                 for (i = 0; i < nfields; ++i) {
 785                         field_size = mono_marshal_type_size (fields [i].field->type,
 786                                                            fields [i].mspec,
 787                                                            &align, TRUE, klass->unicode);
 788                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 789                                 pass_on_stack = TRUE;
 790                                 break;
 791                         }
 792                 }
 793         }
 794
 795         if (pass_on_stack) {
 796                 /* Allways pass in memory */
 797                 ainfo->offset = *stack_size;
 798                 *stack_size += ALIGN_TO (size, 8);
 799                 ainfo->storage = ArgOnStack;
 800
 801                 g_free (fields);
 802                 return;
 803         }
 804
 805         /* FIXME: Handle structs smaller than 8 bytes */
 806         //if ((size % 8) != 0)
 807         //      NOT_IMPLEMENTED;
 808
 809         if (size > 8)
 810                 nquads = 2;
 811         else
 812                 nquads = 1;
 813
 814         if (!sig->pinvoke) {
 815                 int n = mono_class_value_size (klass, NULL);
 816
 817                 quadsize [0] = n >= 8 ? 8 : n;
 818                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 819
 820                 /* Always pass in 1 or 2 integer registers */
 821                 args [0] = ARG_CLASS_INTEGER;
 822                 args [1] = ARG_CLASS_INTEGER;
 823                 /* Only the simplest cases are supported */
 824                 if (is_return && nquads != 1) {
 825                         args [0] = ARG_CLASS_MEMORY;
 826                         args [1] = ARG_CLASS_MEMORY;
 827                 }
 828         } else {
 829                 /*
 830                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 831                  * The X87 and SSEUP stuff is left out since there are no such types in
 832                  * the CLR.
 833                  */
 834                 g_assert (info);
 835                 g_assert (fields);
 836
 837 #ifndef TARGET_WIN32
 838                 if (info->native_size > 16) {
 839                         ainfo->offset = *stack_size;
 840                         *stack_size += ALIGN_TO (info->native_size, 8);
 841                         ainfo->storage = ArgOnStack;
 842
 843                         g_free (fields);
 844                         return;
 845                 }
 846 #else
 847                 switch (info->native_size) {
 848                 case 1: case 2: case 4: case 8:
 849                         break;
 850                 default:
 851                         if (is_return) {
 852                                 ainfo->storage = ArgOnStack;
 853                                 ainfo->offset = *stack_size;
 854                                 *stack_size += ALIGN_TO (info->native_size, 8);
 855                         }
 856                         else {
 857                                 ainfo->storage = ArgValuetypeAddrInIReg;
 858
 859                                 if (*gr < PARAM_REGS) {
 860                                         ainfo->pair_storage [0] = ArgInIReg;
 861                                         ainfo->pair_regs [0] = param_regs [*gr];
 862                                         (*gr) ++;
 863                                 }
 864                                 else {
 865                                         ainfo->pair_storage [0] = ArgOnStack;
 866                                         ainfo->offset = *stack_size;
 867                                         *stack_size += 8;
 868                                 }
 869                         }
 870
 871                         g_free (fields);
 872                         return;
 873                 }
 874 #endif
 875
 876                 args [0] = ARG_CLASS_NO_CLASS;
 877                 args [1] = ARG_CLASS_NO_CLASS;
 878                 for (quad = 0; quad < nquads; ++quad) {
 879                         int size;
 880                         guint32 align;
 881                         ArgumentClass class1;
 882
 883                         if (nfields == 0)
 884                                 class1 = ARG_CLASS_MEMORY;
 885                         else
 886                                 class1 = ARG_CLASS_NO_CLASS;
 887                         for (i = 0; i < nfields; ++i) {
 888                                 size = mono_marshal_type_size (fields [i].field->type,
 889                                                                                            fields [i].mspec,
 890                                                                                            &align, TRUE, klass->unicode);
 891                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 892                                         /* Unaligned field */
 893                                         NOT_IMPLEMENTED;
 894                                 }
 895
 896                                 /* Skip fields in other quad */
 897                                 if ((quad == 0) && (fields [i].offset >= 8))
 898                                         continue;
 899                                 if ((quad == 1) && (fields [i].offset < 8))
 900                                         continue;
 901
 902                                 /* How far into this quad this data extends.*/
 903                                 /* (8 is size of quad) */
 904                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 905
 906                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 907                         }
 908                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 909                         args [quad] = class1;
 910                 }
 911         }
 912
 913         g_free (fields);
 914
 915         /* Post merger cleanup */
 916         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 917                 args [0] = args [1] = ARG_CLASS_MEMORY;
 918
 919         /* Allocate registers */
 920         {
 921                 int orig_gr = *gr;
 922                 int orig_fr = *fr;
 923
 924                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 925                         quadsize [0] ++;
 926                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 927                         quadsize [1] ++;
 928
 929                 ainfo->storage = ArgValuetypeInReg;
 930                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 931                 g_assert (quadsize [0] <= 8);
 932                 g_assert (quadsize [1] <= 8);
 933                 ainfo->pair_size [0] = quadsize [0];
 934                 ainfo->pair_size [1] = quadsize [1];
 935                 ainfo->nregs = nquads;
 936                 for (quad = 0; quad < nquads; ++quad) {
 937                         switch (args [quad]) {
 938                         case ARG_CLASS_INTEGER:
 939                                 if (*gr >= PARAM_REGS)
 940                                         args [quad] = ARG_CLASS_MEMORY;
 941                                 else {
 942                                         ainfo->pair_storage [quad] = ArgInIReg;
 943                                         if (is_return)
 944                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 945                                         else
 946                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 947                                         (*gr) ++;
 948                                 }
 949                                 break;
 950                         case ARG_CLASS_SSE:
 951                                 if (*fr >= FLOAT_PARAM_REGS)
 952                                         args [quad] = ARG_CLASS_MEMORY;
 953                                 else {
 954                                         if (quadsize[quad] <= 4)
 955                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 956                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 957                                         ainfo->pair_regs [quad] = *fr;
 958                                         (*fr) ++;
 959                                 }
 960                                 break;
 961                         case ARG_CLASS_MEMORY:
 962                                 break;
 963                         default:
 964                                 g_assert_not_reached ();
 965                         }
 966                 }
 967
 968                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 969                         /* Revert possible register assignments */
 970                         *gr = orig_gr;
 971                         *fr = orig_fr;
 972
 973                         ainfo->offset = *stack_size;
 974                         if (sig->pinvoke)
 975                                 *stack_size += ALIGN_TO (info->native_size, 8);
 976                         else
 977                                 *stack_size += nquads * sizeof(mgreg_t);
 978                         ainfo->storage = ArgOnStack;
 979                 }
 980         }
 981 }
 982
 983 /*
 984  * get_call_info:
 985  *
 986  *  Obtain information about a call according to the calling convention.
 987  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 988  * Draft Version 0.23" document for more information.
 989  */
 990 static CallInfo*
 991 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 992 {
 993         guint32 i, gr, fr, pstart;
 994         MonoType *ret_type;
 995         int n = sig->hasthis + sig->param_count;
 996         guint32 stack_size = 0;
 997         CallInfo *cinfo;
 998         gboolean is_pinvoke = sig->pinvoke;
 999
1000         if (mp)
1001                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002         else
1003                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1004
1005         cinfo->nargs = n;
1006
1007         gr = 0;
1008         fr = 0;
1009
1010 #ifdef TARGET_WIN32
1011         /* Reserve space where the callee can save the argument registers */
1012         stack_size = 4 * sizeof (mgreg_t);
1013 #endif
1014
1015         /* return value */
1016         ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1017         switch (ret_type->type) {
1018         case MONO_TYPE_I1:
1019         case MONO_TYPE_U1:
1020         case MONO_TYPE_I2:
1021         case MONO_TYPE_U2:
1022         case MONO_TYPE_I4:
1023         case MONO_TYPE_U4:
1024         case MONO_TYPE_I:
1025         case MONO_TYPE_U:
1026         case MONO_TYPE_PTR:
1027         case MONO_TYPE_FNPTR:
1028         case MONO_TYPE_CLASS:
1029         case MONO_TYPE_OBJECT:
1030         case MONO_TYPE_SZARRAY:
1031         case MONO_TYPE_ARRAY:
1032         case MONO_TYPE_STRING:
1033                 cinfo->ret.storage = ArgInIReg;
1034                 cinfo->ret.reg = AMD64_RAX;
1035                 break;
1036         case MONO_TYPE_U8:
1037         case MONO_TYPE_I8:
1038                 cinfo->ret.storage = ArgInIReg;
1039                 cinfo->ret.reg = AMD64_RAX;
1040                 break;
1041         case MONO_TYPE_R4:
1042                 cinfo->ret.storage = ArgInFloatSSEReg;
1043                 cinfo->ret.reg = AMD64_XMM0;
1044                 break;
1045         case MONO_TYPE_R8:
1046                 cinfo->ret.storage = ArgInDoubleSSEReg;
1047                 cinfo->ret.reg = AMD64_XMM0;
1048                 break;
1049         case MONO_TYPE_GENERICINST:
1050                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1051                         cinfo->ret.storage = ArgInIReg;
1052                         cinfo->ret.reg = AMD64_RAX;
1053                         break;
1054                 }
1055                 /* fall through */
1056 #if defined( __native_client_codegen__ )
1057         case MONO_TYPE_TYPEDBYREF:
1058 #endif
1059         case MONO_TYPE_VALUETYPE: {
1060                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1061
1062                 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1063                 if (cinfo->ret.storage == ArgOnStack) {
1064                         cinfo->vtype_retaddr = TRUE;
1065                         /* The caller passes the address where the value is stored */
1066                 }
1067                 break;
1068         }
1069 #if !defined( __native_client_codegen__ )
1070         case MONO_TYPE_TYPEDBYREF:
1071                 /* Same as a valuetype with size 24 */
1072                 cinfo->vtype_retaddr = TRUE;
1073                 break;
1074 #endif
1075         case MONO_TYPE_VOID:
1076                 break;
1077         default:
1078                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1079         }
1080
1081         pstart = 0;
1082         /*
1083          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1084          * the first argument, allowing 'this' to be always passed in the first arg reg.
1085          * Also do this if the first argument is a reference type, since virtual calls
1086          * are sometimes made using calli without sig->hasthis set, like in the delegate
1087          * invoke wrappers.
1088          */
1089         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1090                 if (sig->hasthis) {
1091                         add_general (&gr, &stack_size, cinfo->args + 0);
1092                 } else {
1093                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1094                         pstart = 1;
1095                 }
1096                 add_general (&gr, &stack_size, &cinfo->ret);
1097                 cinfo->vret_arg_index = 1;
1098         } else {
1099                 /* this */
1100                 if (sig->hasthis)
1101                         add_general (&gr, &stack_size, cinfo->args + 0);
1102
1103                 if (cinfo->vtype_retaddr)
1104                         add_general (&gr, &stack_size, &cinfo->ret);
1105         }
1106
1107         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1108                 gr = PARAM_REGS;
1109                 fr = FLOAT_PARAM_REGS;
1110
1111                 /* Emit the signature cookie just before the implicit arguments */
1112                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1113         }
1114
1115         for (i = pstart; i < sig->param_count; ++i) {
1116                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1117                 MonoType *ptype;
1118
1119 #ifdef TARGET_WIN32
1120                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1121                 if (gr > fr)
1122                         fr = gr;
1123                 else if (fr > gr)
1124                         gr = fr;
1125 #endif
1126
1127                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1128                         /* We allways pass the sig cookie on the stack for simplicity */
1129                         /*
1130                          * Prevent implicit arguments + the sig cookie from being passed
1131                          * in registers.
1132                          */
1133                         gr = PARAM_REGS;
1134                         fr = FLOAT_PARAM_REGS;
1135
1136                         /* Emit the signature cookie just before the implicit arguments */
1137                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1138                 }
1139
1140                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1141                 switch (ptype->type) {
1142                 case MONO_TYPE_I1:
1143                 case MONO_TYPE_U1:
1144                         add_general (&gr, &stack_size, ainfo);
1145                         break;
1146                 case MONO_TYPE_I2:
1147                 case MONO_TYPE_U2:
1148                         add_general (&gr, &stack_size, ainfo);
1149                         break;
1150                 case MONO_TYPE_I4:
1151                 case MONO_TYPE_U4:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I:
1155                 case MONO_TYPE_U:
1156                 case MONO_TYPE_PTR:
1157                 case MONO_TYPE_FNPTR:
1158                 case MONO_TYPE_CLASS:
1159                 case MONO_TYPE_OBJECT:
1160                 case MONO_TYPE_STRING:
1161                 case MONO_TYPE_SZARRAY:
1162                 case MONO_TYPE_ARRAY:
1163                         add_general (&gr, &stack_size, ainfo);
1164                         break;
1165                 case MONO_TYPE_GENERICINST:
1166                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1167                                 add_general (&gr, &stack_size, ainfo);
1168                                 break;
1169                         }
1170                         /* fall through */
1171                 case MONO_TYPE_VALUETYPE:
1172                 case MONO_TYPE_TYPEDBYREF:
1173                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1174                         break;
1175                 case MONO_TYPE_U8:
1176
1177                 case MONO_TYPE_I8:
1178                         add_general (&gr, &stack_size, ainfo);
1179                         break;
1180                 case MONO_TYPE_R4:
1181                         add_float (&fr, &stack_size, ainfo, FALSE);
1182                         break;
1183                 case MONO_TYPE_R8:
1184                         add_float (&fr, &stack_size, ainfo, TRUE);
1185                         break;
1186                 default:
1187                         g_assert_not_reached ();
1188                 }
1189         }
1190
1191         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1192                 gr = PARAM_REGS;
1193                 fr = FLOAT_PARAM_REGS;
1194
1195                 /* Emit the signature cookie just before the implicit arguments */
1196                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1197         }
1198
1199         cinfo->stack_usage = stack_size;
1200         cinfo->reg_usage = gr;
1201         cinfo->freg_usage = fr;
1202         return cinfo;
1203 }
1204
1205 /*
1206  * mono_arch_get_argument_info:
1207  * @csig:  a method signature
1208  * @param_count: the number of parameters to consider
1209  * @arg_info: an array to store the result infos
1210  *
1211  * Gathers information on parameters such as size, alignment and
1212  * padding. arg_info should be large enought to hold param_count + 1 entries.
1213  *
1214  * Returns the size of the argument area on the stack.
1215  */
1216 int
1217 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1218 {
1219         int k;
1220         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1221         guint32 args_size = cinfo->stack_usage;
1222
1223         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1224         if (csig->hasthis) {
1225                 arg_info [0].offset = 0;
1226         }
1227
1228         for (k = 0; k < param_count; k++) {
1229                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1230                 /* FIXME: */
1231                 arg_info [k + 1].size = 0;
1232         }
1233
1234         g_free (cinfo);
1235
1236         return args_size;
1237 }
1238
1239 gboolean
1240 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1241 {
1242         CallInfo *c1, *c2;
1243         gboolean res;
1244         MonoType *callee_ret;
1245
1246         c1 = get_call_info (NULL, NULL, caller_sig);
1247         c2 = get_call_info (NULL, NULL, callee_sig);
1248         res = c1->stack_usage >= c2->stack_usage;
1249         callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1250         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1251                 /* An address on the callee's stack is passed as the first argument */
1252                 res = FALSE;
1253
1254         g_free (c1);
1255         g_free (c2);
1256
1257         return res;
1258 }
1259
1260 /*
1261  * Initialize the cpu to execute managed code.
1262  */
1263 void
1264 mono_arch_cpu_init (void)
1265 {
1266 #ifndef _MSC_VER
1267         guint16 fpcw;
1268
1269         /* spec compliance requires running with double precision */
1270         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1271         fpcw &= ~X86_FPCW_PRECC_MASK;
1272         fpcw |= X86_FPCW_PREC_DOUBLE;
1273         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275 #else
1276         /* TODO: This is crashing on Win64 right now.
1277         * _control87 (_PC_53, MCW_PC);
1278         */
1279 #endif
1280 }
1281
1282 /*
1283  * Initialize architecture specific code.
1284  */
1285 void
1286 mono_arch_init (void)
1287 {
1288         int flags;
1289
1290         mono_mutex_init_recursive (&mini_arch_mutex);
1291 #if defined(__native_client_codegen__)
1292         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1293         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1294         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1295         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1296 #endif
1297
1298 #ifdef MONO_ARCH_NOMAP32BIT
1299         flags = MONO_MMAP_READ;
1300         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1301         breakpoint_size = 13;
1302         breakpoint_fault_size = 3;
1303 #else
1304         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1305         /* amd64_mov_reg_mem () */
1306         breakpoint_size = 8;
1307         breakpoint_fault_size = 8;
1308 #endif
1309
1310         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1311         single_step_fault_size = 4;
1312
1313         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1314         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1315         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1316
1317         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1318         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1319         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1320         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1321 }
1322
1323 /*
1324  * Cleanup architecture specific code.
1325  */
1326 void
1327 mono_arch_cleanup (void)
1328 {
1329         mono_mutex_destroy (&mini_arch_mutex);
1330 #if defined(__native_client_codegen__)
1331         mono_native_tls_free (nacl_instruction_depth);
1332         mono_native_tls_free (nacl_rex_tag);
1333         mono_native_tls_free (nacl_legacy_prefix_tag);
1334 #endif
1335 }
1336
1337 /*
1338  * This function returns the optimizations supported on this cpu.
1339  */
1340 guint32
1341 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1342 {
1343         guint32 opts = 0;
1344
1345         *exclude_mask = 0;
1346
1347         if (mono_hwcap_x86_has_cmov) {
1348                 opts |= MONO_OPT_CMOV;
1349
1350                 if (mono_hwcap_x86_has_fcmov)
1351                         opts |= MONO_OPT_FCMOV;
1352                 else
1353                         *exclude_mask |= MONO_OPT_FCMOV;
1354         } else {
1355                 *exclude_mask |= MONO_OPT_CMOV;
1356         }
1357
1358         return opts;
1359 }
1360
1361 /*
1362  * This function test for all SSE functions supported.
1363  *
1364  * Returns a bitmask corresponding to all supported versions.
1365  *
1366  */
1367 guint32
1368 mono_arch_cpu_enumerate_simd_versions (void)
1369 {
1370         guint32 sse_opts = 0;
1371
1372         if (mono_hwcap_x86_has_sse1)
1373                 sse_opts |= SIMD_VERSION_SSE1;
1374
1375         if (mono_hwcap_x86_has_sse2)
1376                 sse_opts |= SIMD_VERSION_SSE2;
1377
1378         if (mono_hwcap_x86_has_sse3)
1379                 sse_opts |= SIMD_VERSION_SSE3;
1380
1381         if (mono_hwcap_x86_has_ssse3)
1382                 sse_opts |= SIMD_VERSION_SSSE3;
1383
1384         if (mono_hwcap_x86_has_sse41)
1385                 sse_opts |= SIMD_VERSION_SSE41;
1386
1387         if (mono_hwcap_x86_has_sse42)
1388                 sse_opts |= SIMD_VERSION_SSE42;
1389
1390         if (mono_hwcap_x86_has_sse4a)
1391                 sse_opts |= SIMD_VERSION_SSE4a;
1392
1393         return sse_opts;
1394 }
1395
1396 #ifndef DISABLE_JIT
1397
1398 GList *
1399 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1400 {
1401         GList *vars = NULL;
1402         int i;
1403
1404         for (i = 0; i < cfg->num_varinfo; i++) {
1405                 MonoInst *ins = cfg->varinfo [i];
1406                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1407
1408                 /* unused vars */
1409                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1410                         continue;
1411
1412                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1413                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1414                         continue;
1415
1416                 if (mono_is_regsize_var (ins->inst_vtype)) {
1417                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1418                         g_assert (i == vmv->idx);
1419                         vars = g_list_prepend (vars, vmv);
1420                 }
1421         }
1422
1423         vars = mono_varlist_sort (cfg, vars, 0);
1424
1425         return vars;
1426 }
1427
1428 /**
1429  * mono_arch_compute_omit_fp:
1430  *
1431  *   Determine whenever the frame pointer can be eliminated.
1432  */
1433 static void
1434 mono_arch_compute_omit_fp (MonoCompile *cfg)
1435 {
1436         MonoMethodSignature *sig;
1437         MonoMethodHeader *header;
1438         int i, locals_size;
1439         CallInfo *cinfo;
1440
1441         if (cfg->arch.omit_fp_computed)
1442                 return;
1443
1444         header = cfg->header;
1445
1446         sig = mono_method_signature (cfg->method);
1447
1448         if (!cfg->arch.cinfo)
1449                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1450         cinfo = cfg->arch.cinfo;
1451
1452         /*
1453          * FIXME: Remove some of the restrictions.
1454          */
1455         cfg->arch.omit_fp = TRUE;
1456         cfg->arch.omit_fp_computed = TRUE;
1457
1458 #ifdef __native_client_codegen__
1459         /* NaCl modules may not change the value of RBP, so it cannot be */
1460         /* used as a normal register, but it can be used as a frame pointer*/
1461         cfg->disable_omit_fp = TRUE;
1462         cfg->arch.omit_fp = FALSE;
1463 #endif
1464
1465         if (cfg->disable_omit_fp)
1466                 cfg->arch.omit_fp = FALSE;
1467
1468         if (!debug_omit_fp ())
1469                 cfg->arch.omit_fp = FALSE;
1470         /*
1471         if (cfg->method->save_lmf)
1472                 cfg->arch.omit_fp = FALSE;
1473         */
1474         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1475                 cfg->arch.omit_fp = FALSE;
1476         if (header->num_clauses)
1477                 cfg->arch.omit_fp = FALSE;
1478         if (cfg->param_area)
1479                 cfg->arch.omit_fp = FALSE;
1480         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1481                 cfg->arch.omit_fp = FALSE;
1482         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1483                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1484                 cfg->arch.omit_fp = FALSE;
1485         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1486                 ArgInfo *ainfo = &cinfo->args [i];
1487
1488                 if (ainfo->storage == ArgOnStack) {
1489                         /*
1490                          * The stack offset can only be determined when the frame
1491                          * size is known.
1492                          */
1493                         cfg->arch.omit_fp = FALSE;
1494                 }
1495         }
1496
1497         locals_size = 0;
1498         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1499                 MonoInst *ins = cfg->varinfo [i];
1500                 int ialign;
1501
1502                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1503         }
1504 }
1505
1506 GList *
1507 mono_arch_get_global_int_regs (MonoCompile *cfg)
1508 {
1509         GList *regs = NULL;
1510
1511         mono_arch_compute_omit_fp (cfg);
1512
1513         if (cfg->arch.omit_fp)
1514                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1515
1516         /* We use the callee saved registers for global allocation */
1517         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1518         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1519         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1520         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1521 #ifndef __native_client_codegen__
1522         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1523 #endif
1524 #ifdef TARGET_WIN32
1525         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1526         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1527 #endif
1528
1529         return regs;
1530 }
1531
1532 GList*
1533 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1534 {
1535         GList *regs = NULL;
1536         int i;
1537
1538         /* All XMM registers */
1539         for (i = 0; i < 16; ++i)
1540                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1541
1542         return regs;
1543 }
1544
1545 GList*
1546 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1547 {
1548         static GList *r = NULL;
1549
1550         if (r == NULL) {
1551                 GList *regs = NULL;
1552
1553                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1554                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1555                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1556                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1557                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1558 #ifndef __native_client_codegen__
1559                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1560 #endif
1561
1562                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1563                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1564                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1565                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1566                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1567                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1568                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1569                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1570
1571                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1572         }
1573
1574         return r;
1575 }
1576
1577 GList*
1578 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1579 {
1580         int i;
1581         static GList *r = NULL;
1582
1583         if (r == NULL) {
1584                 GList *regs = NULL;
1585
1586                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1587                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1588
1589                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1590         }
1591
1592         return r;
1593 }
1594
1595 /*
1596  * mono_arch_regalloc_cost:
1597  *
1598  *  Return the cost, in number of memory references, of the action of
1599  * allocating the variable VMV into a register during global register
1600  * allocation.
1601  */
1602 guint32
1603 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1604 {
1605         MonoInst *ins = cfg->varinfo [vmv->idx];
1606
1607         if (cfg->method->save_lmf)
1608                 /* The register is already saved */
1609                 /* substract 1 for the invisible store in the prolog */
1610                 return (ins->opcode == OP_ARG) ? 0 : 1;
1611         else
1612                 /* push+pop */
1613                 return (ins->opcode == OP_ARG) ? 1 : 2;
1614 }
1615
1616 /*
1617  * mono_arch_fill_argument_info:
1618  *
1619  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1620  * of the method.
1621  */
1622 void
1623 mono_arch_fill_argument_info (MonoCompile *cfg)
1624 {
1625         MonoType *sig_ret;
1626         MonoMethodSignature *sig;
1627         MonoInst *ins;
1628         int i;
1629         CallInfo *cinfo;
1630
1631         sig = mono_method_signature (cfg->method);
1632
1633         cinfo = cfg->arch.cinfo;
1634         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1635
1636         /*
1637          * Contrary to mono_arch_allocate_vars (), the information should describe
1638          * where the arguments are at the beginning of the method, not where they can be
1639          * accessed during the execution of the method. The later makes no sense for the
1640          * global register allocator, since a variable can be in more than one location.
1641          */
1642         if (sig_ret->type != MONO_TYPE_VOID) {
1643                 switch (cinfo->ret.storage) {
1644                 case ArgInIReg:
1645                 case ArgInFloatSSEReg:
1646                 case ArgInDoubleSSEReg:
1647                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1648                                 cfg->vret_addr->opcode = OP_REGVAR;
1649                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1650                         }
1651                         else {
1652                                 cfg->ret->opcode = OP_REGVAR;
1653                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1654                         }
1655                         break;
1656                 case ArgValuetypeInReg:
1657                         cfg->ret->opcode = OP_REGOFFSET;
1658                         cfg->ret->inst_basereg = -1;
1659                         cfg->ret->inst_offset = -1;
1660                         break;
1661                 default:
1662                         g_assert_not_reached ();
1663                 }
1664         }
1665
1666         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1667                 ArgInfo *ainfo = &cinfo->args [i];
1668
1669                 ins = cfg->args [i];
1670
1671                 switch (ainfo->storage) {
1672                 case ArgInIReg:
1673                 case ArgInFloatSSEReg:
1674                 case ArgInDoubleSSEReg:
1675                         ins->opcode = OP_REGVAR;
1676                         ins->inst_c0 = ainfo->reg;
1677                         break;
1678                 case ArgOnStack:
1679                         ins->opcode = OP_REGOFFSET;
1680                         ins->inst_basereg = -1;
1681                         ins->inst_offset = -1;
1682                         break;
1683                 case ArgValuetypeInReg:
1684                         /* Dummy */
1685                         ins->opcode = OP_NOP;
1686                         break;
1687                 default:
1688                         g_assert_not_reached ();
1689                 }
1690         }
1691 }
1692
1693 void
1694 mono_arch_allocate_vars (MonoCompile *cfg)
1695 {
1696         MonoType *sig_ret;
1697         MonoMethodSignature *sig;
1698         MonoInst *ins;
1699         int i, offset;
1700         guint32 locals_stack_size, locals_stack_align;
1701         gint32 *offsets;
1702         CallInfo *cinfo;
1703
1704         sig = mono_method_signature (cfg->method);
1705
1706         cinfo = cfg->arch.cinfo;
1707         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1708
1709         mono_arch_compute_omit_fp (cfg);
1710
1711         /*
1712          * We use the ABI calling conventions for managed code as well.
1713          * Exception: valuetypes are only sometimes passed or returned in registers.
1714          */
1715
1716         /*
1717          * The stack looks like this:
1718          * <incoming arguments passed on the stack>
1719          * <return value>
1720          * <lmf/caller saved registers>
1721          * <locals>
1722          * <spill area>
1723          * <localloc area>  -> grows dynamically
1724          * <params area>
1725          */
1726
1727         if (cfg->arch.omit_fp) {
1728                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1729                 cfg->frame_reg = AMD64_RSP;
1730                 offset = 0;
1731         } else {
1732                 /* Locals are allocated backwards from %fp */
1733                 cfg->frame_reg = AMD64_RBP;
1734                 offset = 0;
1735         }
1736
1737         cfg->arch.saved_iregs = cfg->used_int_regs;
1738         if (cfg->method->save_lmf)
1739                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1740                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1741
1742         if (cfg->arch.omit_fp)
1743                 cfg->arch.reg_save_area_offset = offset;
1744         /* Reserve space for callee saved registers */
1745         for (i = 0; i < AMD64_NREG; ++i)
1746                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1747                         offset += sizeof(mgreg_t);
1748                 }
1749         if (!cfg->arch.omit_fp)
1750                 cfg->arch.reg_save_area_offset = -offset;
1751
1752         if (sig_ret->type != MONO_TYPE_VOID) {
1753                 switch (cinfo->ret.storage) {
1754                 case ArgInIReg:
1755                 case ArgInFloatSSEReg:
1756                 case ArgInDoubleSSEReg:
1757                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1758                                 /* The register is volatile */
1759                                 cfg->vret_addr->opcode = OP_REGOFFSET;
1760                                 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1761                                 if (cfg->arch.omit_fp) {
1762                                         cfg->vret_addr->inst_offset = offset;
1763                                         offset += 8;
1764                                 } else {
1765                                         offset += 8;
1766                                         cfg->vret_addr->inst_offset = -offset;
1767                                 }
1768                                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1769                                         printf ("vret_addr =");
1770                                         mono_print_ins (cfg->vret_addr);
1771                                 }
1772                         }
1773                         else {
1774                                 cfg->ret->opcode = OP_REGVAR;
1775                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1776                         }
1777                         break;
1778                 case ArgValuetypeInReg:
1779                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1780                         cfg->ret->opcode = OP_REGOFFSET;
1781                         cfg->ret->inst_basereg = cfg->frame_reg;
1782                         if (cfg->arch.omit_fp) {
1783                                 cfg->ret->inst_offset = offset;
1784                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1785                         } else {
1786                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1787                                 cfg->ret->inst_offset = - offset;
1788                         }
1789                         break;
1790                 default:
1791                         g_assert_not_reached ();
1792                 }
1793                 cfg->ret->dreg = cfg->ret->inst_c0;
1794         }
1795
1796         /* Allocate locals */
1797         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1798         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1799                 char *mname = mono_method_full_name (cfg->method, TRUE);
1800                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1801                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1802                 g_free (mname);
1803                 return;
1804         }
1805
1806         if (locals_stack_align) {
1807                 offset += (locals_stack_align - 1);
1808                 offset &= ~(locals_stack_align - 1);
1809         }
1810         if (cfg->arch.omit_fp) {
1811                 cfg->locals_min_stack_offset = offset;
1812                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1813         } else {
1814                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1815                 cfg->locals_max_stack_offset = - offset;
1816         }
1817
1818         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1819                 if (offsets [i] != -1) {
1820                         MonoInst *ins = cfg->varinfo [i];
1821                         ins->opcode = OP_REGOFFSET;
1822                         ins->inst_basereg = cfg->frame_reg;
1823                         if (cfg->arch.omit_fp)
1824                                 ins->inst_offset = (offset + offsets [i]);
1825                         else
1826                                 ins->inst_offset = - (offset + offsets [i]);
1827                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1828                 }
1829         }
1830         offset += locals_stack_size;
1831
1832         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1833                 g_assert (!cfg->arch.omit_fp);
1834                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1835                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1836         }
1837
1838         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1839                 ins = cfg->args [i];
1840                 if (ins->opcode != OP_REGVAR) {
1841                         ArgInfo *ainfo = &cinfo->args [i];
1842                         gboolean inreg = TRUE;
1843
1844                         /* FIXME: Allocate volatile arguments to registers */
1845                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1846                                 inreg = FALSE;
1847
1848                         /*
1849                          * Under AMD64, all registers used to pass arguments to functions
1850                          * are volatile across calls.
1851                          * FIXME: Optimize this.
1852                          */
1853                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1854                                 inreg = FALSE;
1855
1856                         ins->opcode = OP_REGOFFSET;
1857
1858                         switch (ainfo->storage) {
1859                         case ArgInIReg:
1860                         case ArgInFloatSSEReg:
1861                         case ArgInDoubleSSEReg:
1862                                 if (inreg) {
1863                                         ins->opcode = OP_REGVAR;
1864                                         ins->dreg = ainfo->reg;
1865                                 }
1866                                 break;
1867                         case ArgOnStack:
1868                                 g_assert (!cfg->arch.omit_fp);
1869                                 ins->opcode = OP_REGOFFSET;
1870                                 ins->inst_basereg = cfg->frame_reg;
1871                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1872                                 break;
1873                         case ArgValuetypeInReg:
1874                                 break;
1875                         case ArgValuetypeAddrInIReg: {
1876                                 MonoInst *indir;
1877                                 g_assert (!cfg->arch.omit_fp);
1878
1879                                 MONO_INST_NEW (cfg, indir, 0);
1880                                 indir->opcode = OP_REGOFFSET;
1881                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1882                                         indir->inst_basereg = cfg->frame_reg;
1883                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1884                                         offset += (sizeof (gpointer));
1885                                         indir->inst_offset = - offset;
1886                                 }
1887                                 else {
1888                                         indir->inst_basereg = cfg->frame_reg;
1889                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1890                                 }
1891
1892                                 ins->opcode = OP_VTARG_ADDR;
1893                                 ins->inst_left = indir;
1894
1895                                 break;
1896                         }
1897                         default:
1898                                 NOT_IMPLEMENTED;
1899                         }
1900
1901                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1902                                 ins->opcode = OP_REGOFFSET;
1903                                 ins->inst_basereg = cfg->frame_reg;
1904                                 /* These arguments are saved to the stack in the prolog */
1905                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1906                                 if (cfg->arch.omit_fp) {
1907                                         ins->inst_offset = offset;
1908                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1909                                         // Arguments are yet supported by the stack map creation code
1910                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1911                                 } else {
1912                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1913                                         ins->inst_offset = - offset;
1914                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1915                                 }
1916                         }
1917                 }
1918         }
1919
1920         cfg->stack_offset = offset;
1921 }
1922
1923 void
1924 mono_arch_create_vars (MonoCompile *cfg)
1925 {
1926         MonoMethodSignature *sig;
1927         CallInfo *cinfo;
1928         MonoType *sig_ret;
1929
1930         sig = mono_method_signature (cfg->method);
1931
1932         if (!cfg->arch.cinfo)
1933                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1934         cinfo = cfg->arch.cinfo;
1935
1936         if (cinfo->ret.storage == ArgValuetypeInReg)
1937                 cfg->ret_var_is_local = TRUE;
1938
1939         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1940         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1941                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1942                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1943                         printf ("vret_addr = ");
1944                         mono_print_ins (cfg->vret_addr);
1945                 }
1946         }
1947
1948         if (cfg->gen_sdb_seq_points) {
1949                 MonoInst *ins;
1950
1951                 if (cfg->compile_aot) {
1952                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1953                         ins->flags |= MONO_INST_VOLATILE;
1954                         cfg->arch.seq_point_info_var = ins;
1955
1956                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1957                         ins->flags |= MONO_INST_VOLATILE;
1958                         cfg->arch.ss_tramp_var = ins;
1959                 }
1960
1961             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1962                 ins->flags |= MONO_INST_VOLATILE;
1963                 cfg->arch.ss_trigger_page_var = ins;
1964         }
1965
1966         if (cfg->method->save_lmf)
1967                 cfg->create_lmf_var = TRUE;
1968
1969         if (cfg->method->save_lmf) {
1970                 cfg->lmf_ir = TRUE;
1971 #if !defined(TARGET_WIN32)
1972                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1973                         cfg->lmf_ir_mono_lmf = TRUE;
1974 #endif
1975         }
1976 }
1977
1978 static void
1979 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1980 {
1981         MonoInst *ins;
1982
1983         switch (storage) {
1984         case ArgInIReg:
1985                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1986                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1987                 ins->sreg1 = tree->dreg;
1988                 MONO_ADD_INS (cfg->cbb, ins);
1989                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1990                 break;
1991         case ArgInFloatSSEReg:
1992                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1993                 ins->dreg = mono_alloc_freg (cfg);
1994                 ins->sreg1 = tree->dreg;
1995                 MONO_ADD_INS (cfg->cbb, ins);
1996
1997                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1998                 break;
1999         case ArgInDoubleSSEReg:
2000                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2001                 ins->dreg = mono_alloc_freg (cfg);
2002                 ins->sreg1 = tree->dreg;
2003                 MONO_ADD_INS (cfg->cbb, ins);
2004
2005                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2006
2007                 break;
2008         default:
2009                 g_assert_not_reached ();
2010         }
2011 }
2012
2013 static int
2014 arg_storage_to_load_membase (ArgStorage storage)
2015 {
2016         switch (storage) {
2017         case ArgInIReg:
2018 #if defined(__mono_ilp32__)
2019                 return OP_LOADI8_MEMBASE;
2020 #else
2021                 return OP_LOAD_MEMBASE;
2022 #endif
2023         case ArgInDoubleSSEReg:
2024                 return OP_LOADR8_MEMBASE;
2025         case ArgInFloatSSEReg:
2026                 return OP_LOADR4_MEMBASE;
2027         default:
2028                 g_assert_not_reached ();
2029         }
2030
2031         return -1;
2032 }
2033
2034 static void
2035 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2036 {
2037         MonoMethodSignature *tmp_sig;
2038         int sig_reg;
2039
2040         if (call->tail_call)
2041                 NOT_IMPLEMENTED;
2042
2043         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2044
2045         /*
2046          * mono_ArgIterator_Setup assumes the signature cookie is
2047          * passed first and all the arguments which were before it are
2048          * passed on the stack after the signature. So compensate by
2049          * passing a different signature.
2050          */
2051         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2052         tmp_sig->param_count -= call->signature->sentinelpos;
2053         tmp_sig->sentinelpos = 0;
2054         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2055
2056         sig_reg = mono_alloc_ireg (cfg);
2057         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2058
2059         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2060 }
2061
2062 #ifdef ENABLE_LLVM
2063 static inline LLVMArgStorage
2064 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2065 {
2066         switch (storage) {
2067         case ArgInIReg:
2068                 return LLVMArgInIReg;
2069         case ArgNone:
2070                 return LLVMArgNone;
2071         default:
2072                 g_assert_not_reached ();
2073                 return LLVMArgNone;
2074         }
2075 }
2076
2077 LLVMCallInfo*
2078 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2079 {
2080         int i, n;
2081         CallInfo *cinfo;
2082         ArgInfo *ainfo;
2083         int j;
2084         LLVMCallInfo *linfo;
2085         MonoType *t, *sig_ret;
2086
2087         n = sig->param_count + sig->hasthis;
2088         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2089
2090         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2091
2092         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2093
2094         /*
2095          * LLVM always uses the native ABI while we use our own ABI, the
2096          * only difference is the handling of vtypes:
2097          * - we only pass/receive them in registers in some cases, and only
2098          *   in 1 or 2 integer registers.
2099          */
2100         if (cinfo->ret.storage == ArgValuetypeInReg) {
2101                 if (sig->pinvoke) {
2102                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2103                         cfg->disable_llvm = TRUE;
2104                         return linfo;
2105                 }
2106
2107                 linfo->ret.storage = LLVMArgVtypeInReg;
2108                 for (j = 0; j < 2; ++j)
2109                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2110         }
2111
2112         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2113                 /* Vtype returned using a hidden argument */
2114                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2115                 linfo->vret_arg_index = cinfo->vret_arg_index;
2116         }
2117
2118         for (i = 0; i < n; ++i) {
2119                 ainfo = cinfo->args + i;
2120
2121                 if (i >= sig->hasthis)
2122                         t = sig->params [i - sig->hasthis];
2123                 else
2124                         t = &mono_defaults.int_class->byval_arg;
2125
2126                 linfo->args [i].storage = LLVMArgNone;
2127
2128                 switch (ainfo->storage) {
2129                 case ArgInIReg:
2130                         linfo->args [i].storage = LLVMArgInIReg;
2131                         break;
2132                 case ArgInDoubleSSEReg:
2133                 case ArgInFloatSSEReg:
2134                         linfo->args [i].storage = LLVMArgInFPReg;
2135                         break;
2136                 case ArgOnStack:
2137                         if (MONO_TYPE_ISSTRUCT (t)) {
2138                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2139                         } else {
2140                                 linfo->args [i].storage = LLVMArgInIReg;
2141                                 if (!t->byref) {
2142                                         if (t->type == MONO_TYPE_R4)
2143                                                 linfo->args [i].storage = LLVMArgInFPReg;
2144                                         else if (t->type == MONO_TYPE_R8)
2145                                                 linfo->args [i].storage = LLVMArgInFPReg;
2146                                 }
2147                         }
2148                         break;
2149                 case ArgValuetypeInReg:
2150                         if (sig->pinvoke) {
2151                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2152                                 cfg->disable_llvm = TRUE;
2153                                 return linfo;
2154                         }
2155
2156                         linfo->args [i].storage = LLVMArgVtypeInReg;
2157                         for (j = 0; j < 2; ++j)
2158                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2159                         break;
2160                 default:
2161                         cfg->exception_message = g_strdup ("ainfo->storage");
2162                         cfg->disable_llvm = TRUE;
2163                         break;
2164                 }
2165         }
2166
2167         return linfo;
2168 }
2169 #endif
2170
2171 void
2172 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2173 {
2174         MonoInst *arg, *in;
2175         MonoMethodSignature *sig;
2176         MonoType *sig_ret;
2177         int i, n;
2178         CallInfo *cinfo;
2179         ArgInfo *ainfo;
2180
2181         sig = call->signature;
2182         n = sig->param_count + sig->hasthis;
2183
2184         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2185
2186         sig_ret = sig->ret;
2187
2188         if (COMPILE_LLVM (cfg)) {
2189                 /* We shouldn't be called in the llvm case */
2190                 cfg->disable_llvm = TRUE;
2191                 return;
2192         }
2193
2194         /*
2195          * Emit all arguments which are passed on the stack to prevent register
2196          * allocation problems.
2197          */
2198         for (i = 0; i < n; ++i) {
2199                 MonoType *t;
2200                 ainfo = cinfo->args + i;
2201
2202                 in = call->args [i];
2203
2204                 if (sig->hasthis && i == 0)
2205                         t = &mono_defaults.object_class->byval_arg;
2206                 else
2207                         t = sig->params [i - sig->hasthis];
2208
2209                 t = mini_get_underlying_type (cfg, t);
2210                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2211                         if (!t->byref) {
2212                                 if (t->type == MONO_TYPE_R4)
2213                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2214                                 else if (t->type == MONO_TYPE_R8)
2215                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2216                                 else
2217                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2218                         } else {
2219                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2220                         }
2221                         if (cfg->compute_gc_maps) {
2222                                 MonoInst *def;
2223
2224                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2225                         }
2226                 }
2227         }
2228
2229         /*
2230          * Emit all parameters passed in registers in non-reverse order for better readability
2231          * and to help the optimization in emit_prolog ().
2232          */
2233         for (i = 0; i < n; ++i) {
2234                 ainfo = cinfo->args + i;
2235
2236                 in = call->args [i];
2237
2238                 if (ainfo->storage == ArgInIReg)
2239                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2240         }
2241
2242         for (i = n - 1; i >= 0; --i) {
2243                 MonoType *t;
2244
2245                 ainfo = cinfo->args + i;
2246
2247                 in = call->args [i];
2248
2249                 if (sig->hasthis && i == 0)
2250                         t = &mono_defaults.object_class->byval_arg;
2251                 else
2252                         t = sig->params [i - sig->hasthis];
2253                 t = mini_get_underlying_type (cfg, t);
2254
2255                 switch (ainfo->storage) {
2256                 case ArgInIReg:
2257                         /* Already done */
2258                         break;
2259                 case ArgInFloatSSEReg:
2260                 case ArgInDoubleSSEReg:
2261                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2262                         break;
2263                 case ArgOnStack:
2264                 case ArgValuetypeInReg:
2265                 case ArgValuetypeAddrInIReg:
2266                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2267                                 MonoInst *call_inst = (MonoInst*)call;
2268                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2269                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2270                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
2271                                 guint32 align;
2272                                 guint32 size;
2273
2274                                 if (t->type == MONO_TYPE_TYPEDBYREF) {
2275                                         size = sizeof (MonoTypedRef);
2276                                         align = sizeof (gpointer);
2277                                 }
2278                                 else {
2279                                         if (sig->pinvoke)
2280                                                 size = mono_type_native_stack_size (t, &align);
2281                                         else {
2282                                                 /*
2283                                                  * Other backends use mono_type_stack_size (), but that
2284                                                  * aligns the size to 8, which is larger than the size of
2285                                                  * the source, leading to reads of invalid memory if the
2286                                                  * source is at the end of address space.
2287                                                  */
2288                                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2289                                         }
2290                                 }
2291                                 g_assert (in->klass);
2292
2293                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2294                                         /* Avoid asserts in emit_memcpy () */
2295                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2296                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2297                                         /* Continue normally */
2298                                 }
2299
2300                                 if (size > 0) {
2301                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2302                                         arg->sreg1 = in->dreg;
2303                                         arg->klass = mono_class_from_mono_type (t);
2304                                         arg->backend.size = size;
2305                                         arg->inst_p0 = call;
2306                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2307                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2308
2309                                         MONO_ADD_INS (cfg->cbb, arg);
2310                                 }
2311                         }
2312                         break;
2313                 default:
2314                         g_assert_not_reached ();
2315                 }
2316
2317                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2318                         /* Emit the signature cookie just before the implicit arguments */
2319                         emit_sig_cookie (cfg, call, cinfo);
2320         }
2321
2322         /* Handle the case where there are no implicit arguments */
2323         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2324                 emit_sig_cookie (cfg, call, cinfo);
2325
2326         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2327         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2328                 MonoInst *vtarg;
2329
2330                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2331                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2332                                 /*
2333                                  * Tell the JIT to use a more efficient calling convention: call using
2334                                  * OP_CALL, compute the result location after the call, and save the
2335                                  * result there.
2336                                  */
2337                                 call->vret_in_reg = TRUE;
2338                                 /*
2339                                  * Nullify the instruction computing the vret addr to enable
2340                                  * future optimizations.
2341                                  */
2342                                 if (call->vret_var)
2343                                         NULLIFY_INS (call->vret_var);
2344                         } else {
2345                                 if (call->tail_call)
2346                                         NOT_IMPLEMENTED;
2347                                 /*
2348                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2349                                  * the stack. Push the address here, so the call instruction can
2350                                  * access it.
2351                                  */
2352                                 if (!cfg->arch.vret_addr_loc) {
2353                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2354                                         /* Prevent it from being register allocated or optimized away */
2355                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2356                                 }
2357
2358                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2359                         }
2360                 }
2361                 else {
2362                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2363                         vtarg->sreg1 = call->vret_var->dreg;
2364                         vtarg->dreg = mono_alloc_preg (cfg);
2365                         MONO_ADD_INS (cfg->cbb, vtarg);
2366
2367                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2368                 }
2369         }
2370
2371         if (cfg->method->save_lmf) {
2372                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2373                 MONO_ADD_INS (cfg->cbb, arg);
2374         }
2375
2376         call->stack_usage = cinfo->stack_usage;
2377 }
2378
2379 void
2380 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2381 {
2382         MonoInst *arg;
2383         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2384         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2385         int size = ins->backend.size;
2386
2387         if (ainfo->storage == ArgValuetypeInReg) {
2388                 MonoInst *load;
2389                 int part;
2390
2391                 for (part = 0; part < 2; ++part) {
2392                         if (ainfo->pair_storage [part] == ArgNone)
2393                                 continue;
2394
2395                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2396                         load->inst_basereg = src->dreg;
2397                         load->inst_offset = part * sizeof(mgreg_t);
2398
2399                         switch (ainfo->pair_storage [part]) {
2400                         case ArgInIReg:
2401                                 load->dreg = mono_alloc_ireg (cfg);
2402                                 break;
2403                         case ArgInDoubleSSEReg:
2404                         case ArgInFloatSSEReg:
2405                                 load->dreg = mono_alloc_freg (cfg);
2406                                 break;
2407                         default:
2408                                 g_assert_not_reached ();
2409                         }
2410                         MONO_ADD_INS (cfg->cbb, load);
2411
2412                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2413                 }
2414         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2415                 MonoInst *vtaddr, *load;
2416                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2417
2418                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2419                 cfg->has_indirection = TRUE;
2420                 load->inst_p0 = vtaddr;
2421                 vtaddr->flags |= MONO_INST_INDIRECT;
2422                 load->type = STACK_MP;
2423                 load->klass = vtaddr->klass;
2424                 load->dreg = mono_alloc_ireg (cfg);
2425                 MONO_ADD_INS (cfg->cbb, load);
2426                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2427
2428                 if (ainfo->pair_storage [0] == ArgInIReg) {
2429                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2430                         arg->dreg = mono_alloc_ireg (cfg);
2431                         arg->sreg1 = load->dreg;
2432                         arg->inst_imm = 0;
2433                         MONO_ADD_INS (cfg->cbb, arg);
2434                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2435                 } else {
2436                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2437                 }
2438         } else {
2439                 if (size == 8) {
2440                         int dreg = mono_alloc_ireg (cfg);
2441
2442                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2443                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2444                 } else if (size <= 40) {
2445                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2446                 } else {
2447                         // FIXME: Code growth
2448                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2449                 }
2450
2451                 if (cfg->compute_gc_maps) {
2452                         MonoInst *def;
2453                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2454                 }
2455         }
2456 }
2457
2458 void
2459 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2460 {
2461         MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2462
2463         if (ret->type == MONO_TYPE_R4) {
2464                 if (COMPILE_LLVM (cfg))
2465                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2466                 else
2467                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2468                 return;
2469         } else if (ret->type == MONO_TYPE_R8) {
2470                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2471                 return;
2472         }
2473
2474         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2475 }
2476
2477 #endif /* DISABLE_JIT */
2478
2479 #define EMIT_COND_BRANCH(ins,cond,sign) \
2480         if (ins->inst_true_bb->native_offset) { \
2481                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2482         } else { \
2483                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2484                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2485             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2486                         x86_branch8 (code, cond, 0, sign); \
2487                 else \
2488                         x86_branch32 (code, cond, 0, sign); \
2489 }
2490
2491 typedef struct {
2492         MonoMethodSignature *sig;
2493         CallInfo *cinfo;
2494 } ArchDynCallInfo;
2495
2496 static gboolean
2497 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2498 {
2499         int i;
2500
2501 #ifdef HOST_WIN32
2502         return FALSE;
2503 #endif
2504
2505         switch (cinfo->ret.storage) {
2506         case ArgNone:
2507         case ArgInIReg:
2508                 break;
2509         case ArgValuetypeInReg: {
2510                 ArgInfo *ainfo = &cinfo->ret;
2511
2512                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2513                         return FALSE;
2514                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2515                         return FALSE;
2516                 break;
2517         }
2518         default:
2519                 return FALSE;
2520         }
2521
2522         for (i = 0; i < cinfo->nargs; ++i) {
2523                 ArgInfo *ainfo = &cinfo->args [i];
2524                 switch (ainfo->storage) {
2525                 case ArgInIReg:
2526                         break;
2527                 case ArgValuetypeInReg:
2528                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2529                                 return FALSE;
2530                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2531                                 return FALSE;
2532                         break;
2533                 default:
2534                         return FALSE;
2535                 }
2536         }
2537
2538         return TRUE;
2539 }
2540
2541 /*
2542  * mono_arch_dyn_call_prepare:
2543  *
2544  *   Return a pointer to an arch-specific structure which contains information
2545  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2546  * supported for SIG.
2547  * This function is equivalent to ffi_prep_cif in libffi.
2548  */
2549 MonoDynCallInfo*
2550 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2551 {
2552         ArchDynCallInfo *info;
2553         CallInfo *cinfo;
2554
2555         cinfo = get_call_info (NULL, NULL, sig);
2556
2557         if (!dyn_call_supported (sig, cinfo)) {
2558                 g_free (cinfo);
2559                 return NULL;
2560         }
2561
2562         info = g_new0 (ArchDynCallInfo, 1);
2563         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2564         info->sig = sig;
2565         info->cinfo = cinfo;
2566
2567         return (MonoDynCallInfo*)info;
2568 }
2569
2570 /*
2571  * mono_arch_dyn_call_free:
2572  *
2573  *   Free a MonoDynCallInfo structure.
2574  */
2575 void
2576 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2577 {
2578         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2579
2580         g_free (ainfo->cinfo);
2581         g_free (ainfo);
2582 }
2583
2584 #if !defined(__native_client__)
2585 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2586 #define GREG_TO_PTR(greg) (gpointer)(greg)
2587 #else
2588 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2589 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2590 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2591 #endif
2592
2593 /*
2594  * mono_arch_get_start_dyn_call:
2595  *
2596  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2597  * store the result into BUF.
2598  * ARGS should be an array of pointers pointing to the arguments.
2599  * RET should point to a memory buffer large enought to hold the result of the
2600  * call.
2601  * This function should be as fast as possible, any work which does not depend
2602  * on the actual values of the arguments should be done in
2603  * mono_arch_dyn_call_prepare ().
2604  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2605  * libffi.
2606  */
2607 void
2608 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2609 {
2610         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2611         DynCallArgs *p = (DynCallArgs*)buf;
2612         int arg_index, greg, i, pindex;
2613         MonoMethodSignature *sig = dinfo->sig;
2614
2615         g_assert (buf_len >= sizeof (DynCallArgs));
2616
2617         p->res = 0;
2618         p->ret = ret;
2619
2620         arg_index = 0;
2621         greg = 0;
2622         pindex = 0;
2623
2624         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2625                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2626                 if (!sig->hasthis)
2627                         pindex = 1;
2628         }
2629
2630         if (dinfo->cinfo->vtype_retaddr)
2631                 p->regs [greg ++] = PTR_TO_GREG(ret);
2632
2633         for (i = pindex; i < sig->param_count; i++) {
2634                 MonoType *t = mini_type_get_underlying_type (NULL, sig->params [i]);
2635                 gpointer *arg = args [arg_index ++];
2636
2637                 if (t->byref) {
2638                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2639                         continue;
2640                 }
2641
2642                 switch (t->type) {
2643                 case MONO_TYPE_STRING:
2644                 case MONO_TYPE_CLASS:
2645                 case MONO_TYPE_ARRAY:
2646                 case MONO_TYPE_SZARRAY:
2647                 case MONO_TYPE_OBJECT:
2648                 case MONO_TYPE_PTR:
2649                 case MONO_TYPE_I:
2650                 case MONO_TYPE_U:
2651 #if !defined(__mono_ilp32__)
2652                 case MONO_TYPE_I8:
2653                 case MONO_TYPE_U8:
2654 #endif
2655                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2656                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2657                         break;
2658 #if defined(__mono_ilp32__)
2659                 case MONO_TYPE_I8:
2660                 case MONO_TYPE_U8:
2661                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2662                         p->regs [greg ++] = *(guint64*)(arg);
2663                         break;
2664 #endif
2665                 case MONO_TYPE_U1:
2666                         p->regs [greg ++] = *(guint8*)(arg);
2667                         break;
2668                 case MONO_TYPE_I1:
2669                         p->regs [greg ++] = *(gint8*)(arg);
2670                         break;
2671                 case MONO_TYPE_I2:
2672                         p->regs [greg ++] = *(gint16*)(arg);
2673                         break;
2674                 case MONO_TYPE_U2:
2675                         p->regs [greg ++] = *(guint16*)(arg);
2676                         break;
2677                 case MONO_TYPE_I4:
2678                         p->regs [greg ++] = *(gint32*)(arg);
2679                         break;
2680                 case MONO_TYPE_U4:
2681                         p->regs [greg ++] = *(guint32*)(arg);
2682                         break;
2683                 case MONO_TYPE_GENERICINST:
2684                     if (MONO_TYPE_IS_REFERENCE (t)) {
2685                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2686                                 break;
2687                         } else {
2688                                 /* Fall through */
2689                         }
2690                 case MONO_TYPE_VALUETYPE: {
2691                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2692
2693                         g_assert (ainfo->storage == ArgValuetypeInReg);
2694                         if (ainfo->pair_storage [0] != ArgNone) {
2695                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2696                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2697                         }
2698                         if (ainfo->pair_storage [1] != ArgNone) {
2699                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2700                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2701                         }
2702                         break;
2703                 }
2704                 default:
2705                         g_assert_not_reached ();
2706                 }
2707         }
2708
2709         g_assert (greg <= PARAM_REGS);
2710 }
2711
2712 /*
2713  * mono_arch_finish_dyn_call:
2714  *
2715  *   Store the result of a dyn call into the return value buffer passed to
2716  * start_dyn_call ().
2717  * This function should be as fast as possible, any work which does not depend
2718  * on the actual values of the arguments should be done in
2719  * mono_arch_dyn_call_prepare ().
2720  */
2721 void
2722 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2723 {
2724         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2725         MonoMethodSignature *sig = dinfo->sig;
2726         guint8 *ret = ((DynCallArgs*)buf)->ret;
2727         mgreg_t res = ((DynCallArgs*)buf)->res;
2728         MonoType *sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
2729
2730         switch (sig_ret->type) {
2731         case MONO_TYPE_VOID:
2732                 *(gpointer*)ret = NULL;
2733                 break;
2734         case MONO_TYPE_STRING:
2735         case MONO_TYPE_CLASS:
2736         case MONO_TYPE_ARRAY:
2737         case MONO_TYPE_SZARRAY:
2738         case MONO_TYPE_OBJECT:
2739         case MONO_TYPE_I:
2740         case MONO_TYPE_U:
2741         case MONO_TYPE_PTR:
2742                 *(gpointer*)ret = GREG_TO_PTR(res);
2743                 break;
2744         case MONO_TYPE_I1:
2745                 *(gint8*)ret = res;
2746                 break;
2747         case MONO_TYPE_U1:
2748                 *(guint8*)ret = res;
2749                 break;
2750         case MONO_TYPE_I2:
2751                 *(gint16*)ret = res;
2752                 break;
2753         case MONO_TYPE_U2:
2754                 *(guint16*)ret = res;
2755                 break;
2756         case MONO_TYPE_I4:
2757                 *(gint32*)ret = res;
2758                 break;
2759         case MONO_TYPE_U4:
2760                 *(guint32*)ret = res;
2761                 break;
2762         case MONO_TYPE_I8:
2763                 *(gint64*)ret = res;
2764                 break;
2765         case MONO_TYPE_U8:
2766                 *(guint64*)ret = res;
2767                 break;
2768         case MONO_TYPE_GENERICINST:
2769                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2770                         *(gpointer*)ret = GREG_TO_PTR(res);
2771                         break;
2772                 } else {
2773                         /* Fall through */
2774                 }
2775         case MONO_TYPE_VALUETYPE:
2776                 if (dinfo->cinfo->vtype_retaddr) {
2777                         /* Nothing to do */
2778                 } else {
2779                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2780
2781                         g_assert (ainfo->storage == ArgValuetypeInReg);
2782
2783                         if (ainfo->pair_storage [0] != ArgNone) {
2784                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2785                                 ((mgreg_t*)ret)[0] = res;
2786                         }
2787
2788                         g_assert (ainfo->pair_storage [1] == ArgNone);
2789                 }
2790                 break;
2791         default:
2792                 g_assert_not_reached ();
2793         }
2794 }
2795
2796 /* emit an exception if condition is fail */
2797 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2798         do {                                                        \
2799                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2800                 if (tins == NULL) {                                                                             \
2801                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2802                                         MONO_PATCH_INFO_EXC, exc_name);  \
2803                         x86_branch32 (code, cond, 0, signed);               \
2804                 } else {        \
2805                         EMIT_COND_BRANCH (tins, cond, signed);  \
2806                 }                       \
2807         } while (0);
2808
2809 #define EMIT_FPCOMPARE(code) do { \
2810         amd64_fcompp (code); \
2811         amd64_fnstsw (code); \
2812 } while (0);
2813
2814 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2815     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2816         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2817         amd64_ ##op (code); \
2818         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2819         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2820 } while (0);
2821
2822 static guint8*
2823 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2824 {
2825         gboolean no_patch = FALSE;
2826
2827         /*
2828          * FIXME: Add support for thunks
2829          */
2830         {
2831                 gboolean near_call = FALSE;
2832
2833                 /*
2834                  * Indirect calls are expensive so try to make a near call if possible.
2835                  * The caller memory is allocated by the code manager so it is
2836                  * guaranteed to be at a 32 bit offset.
2837                  */
2838
2839                 if (patch_type != MONO_PATCH_INFO_ABS) {
2840                         /* The target is in memory allocated using the code manager */
2841                         near_call = TRUE;
2842
2843                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2844                                 if (((MonoMethod*)data)->klass->image->aot_module)
2845                                         /* The callee might be an AOT method */
2846                                         near_call = FALSE;
2847                                 if (((MonoMethod*)data)->dynamic)
2848                                         /* The target is in malloc-ed memory */
2849                                         near_call = FALSE;
2850                         }
2851
2852                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2853                                 /*
2854                                  * The call might go directly to a native function without
2855                                  * the wrapper.
2856                                  */
2857                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2858                                 if (mi) {
2859                                         gconstpointer target = mono_icall_get_wrapper (mi);
2860                                         if ((((guint64)target) >> 32) != 0)
2861                                                 near_call = FALSE;
2862                                 }
2863                         }
2864                 }
2865                 else {
2866                         MonoJumpInfo *jinfo = NULL;
2867
2868                         if (cfg->abs_patches)
2869                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2870                         if (jinfo) {
2871                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2872                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2873                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2874                                                 near_call = TRUE;
2875                                         no_patch = TRUE;
2876                                 } else {
2877                                         /*
2878                                          * This is not really an optimization, but required because the
2879                                          * generic class init trampolines use R11 to pass the vtable.
2880                                          */
2881                                         near_call = TRUE;
2882                                 }
2883                         } else {
2884                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2885                                 if (info) {
2886                                         if (info->func == info->wrapper) {
2887                                                 /* No wrapper */
2888                                                 if ((((guint64)info->func) >> 32) == 0)
2889                                                         near_call = TRUE;
2890                                         }
2891                                         else {
2892                                                 /* See the comment in mono_codegen () */
2893                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2894                                                         near_call = TRUE;
2895                                         }
2896                                 }
2897                                 else if ((((guint64)data) >> 32) == 0) {
2898                                         near_call = TRUE;
2899                                         no_patch = TRUE;
2900                                 }
2901                         }
2902                 }
2903
2904                 if (cfg->method->dynamic)
2905                         /* These methods are allocated using malloc */
2906                         near_call = FALSE;
2907
2908 #ifdef MONO_ARCH_NOMAP32BIT
2909                 near_call = FALSE;
2910 #endif
2911 #if defined(__native_client__)
2912                 /* Always use near_call == TRUE for Native Client */
2913                 near_call = TRUE;
2914 #endif
2915                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2916                 if (optimize_for_xen)
2917                         near_call = FALSE;
2918
2919                 if (cfg->compile_aot) {
2920                         near_call = TRUE;
2921                         no_patch = TRUE;
2922                 }
2923
2924                 if (near_call) {
2925                         /*
2926                          * Align the call displacement to an address divisible by 4 so it does
2927                          * not span cache lines. This is required for code patching to work on SMP
2928                          * systems.
2929                          */
2930                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2931                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2932                                 amd64_padding (code, pad_size);
2933                         }
2934                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2935                         amd64_call_code (code, 0);
2936                 }
2937                 else {
2938                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2939                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2940                         amd64_call_reg (code, GP_SCRATCH_REG);
2941                 }
2942         }
2943
2944         return code;
2945 }
2946
2947 static inline guint8*
2948 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2949 {
2950 #ifdef TARGET_WIN32
2951         if (win64_adjust_stack)
2952                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2953 #endif
2954         code = emit_call_body (cfg, code, patch_type, data);
2955 #ifdef TARGET_WIN32
2956         if (win64_adjust_stack)
2957                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2958 #endif
2959
2960         return code;
2961 }
2962
2963 static inline int
2964 store_membase_imm_to_store_membase_reg (int opcode)
2965 {
2966         switch (opcode) {
2967         case OP_STORE_MEMBASE_IMM:
2968                 return OP_STORE_MEMBASE_REG;
2969         case OP_STOREI4_MEMBASE_IMM:
2970                 return OP_STOREI4_MEMBASE_REG;
2971         case OP_STOREI8_MEMBASE_IMM:
2972                 return OP_STOREI8_MEMBASE_REG;
2973         }
2974
2975         return -1;
2976 }
2977
2978 #ifndef DISABLE_JIT
2979
2980 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2981
2982 /*
2983  * mono_arch_peephole_pass_1:
2984  *
2985  *   Perform peephole opts which should/can be performed before local regalloc
2986  */
2987 void
2988 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2989 {
2990         MonoInst *ins, *n;
2991
2992         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2993                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2994
2995                 switch (ins->opcode) {
2996                 case OP_ADD_IMM:
2997                 case OP_IADD_IMM:
2998                 case OP_LADD_IMM:
2999                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3000                                 /*
3001                                  * X86_LEA is like ADD, but doesn't have the
3002                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3003                                  * its operand to 64 bit.
3004                                  */
3005                                 ins->opcode = OP_X86_LEA_MEMBASE;
3006                                 ins->inst_basereg = ins->sreg1;
3007                         }
3008                         break;
3009                 case OP_LXOR:
3010                 case OP_IXOR:
3011                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3012                                 MonoInst *ins2;
3013
3014                                 /*
3015                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3016                                  * the latter has length 2-3 instead of 6 (reverse constant
3017                                  * propagation). These instruction sequences are very common
3018                                  * in the initlocals bblock.
3019                                  */
3020                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3021                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3022                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3023                                                 ins2->sreg1 = ins->dreg;
3024                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3025                                                 /* Continue */
3026                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3027                                                 NULLIFY_INS (ins2);
3028                                                 /* Continue */
3029                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3030                                                 /* Continue */
3031                                         } else {
3032                                                 break;
3033                                         }
3034                                 }
3035                         }
3036                         break;
3037                 case OP_COMPARE_IMM:
3038                 case OP_LCOMPARE_IMM:
3039                         /* OP_COMPARE_IMM (reg, 0)
3040                          * -->
3041                          * OP_AMD64_TEST_NULL (reg)
3042                          */
3043                         if (!ins->inst_imm)
3044                                 ins->opcode = OP_AMD64_TEST_NULL;
3045                         break;
3046                 case OP_ICOMPARE_IMM:
3047                         if (!ins->inst_imm)
3048                                 ins->opcode = OP_X86_TEST_NULL;
3049                         break;
3050                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3051                         /*
3052                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3053                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3054                          * -->
3055                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3056                          * OP_COMPARE_IMM reg, imm
3057                          *
3058                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3059                          */
3060                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3061                             ins->inst_basereg == last_ins->inst_destbasereg &&
3062                             ins->inst_offset == last_ins->inst_offset) {
3063                                         ins->opcode = OP_ICOMPARE_IMM;
3064                                         ins->sreg1 = last_ins->sreg1;
3065
3066                                         /* check if we can remove cmp reg,0 with test null */
3067                                         if (!ins->inst_imm)
3068                                                 ins->opcode = OP_X86_TEST_NULL;
3069                                 }
3070
3071                         break;
3072                 }
3073
3074                 mono_peephole_ins (bb, ins);
3075         }
3076 }
3077
3078 void
3079 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3080 {
3081         MonoInst *ins, *n;
3082
3083         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3084                 switch (ins->opcode) {
3085                 case OP_ICONST:
3086                 case OP_I8CONST: {
3087                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3088                         /* reg = 0 -> XOR (reg, reg) */
3089                         /* XOR sets cflags on x86, so we cant do it always */
3090                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3091                                 ins->opcode = OP_LXOR;
3092                                 ins->sreg1 = ins->dreg;
3093                                 ins->sreg2 = ins->dreg;
3094                                 /* Fall through */
3095                         } else {
3096                                 break;
3097                         }
3098                 }
3099                 case OP_LXOR:
3100                         /*
3101                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3102                          * 0 result into 64 bits.
3103                          */
3104                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3105                                 ins->opcode = OP_IXOR;
3106                         }
3107                         /* Fall through */
3108                 case OP_IXOR:
3109                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3110                                 MonoInst *ins2;
3111
3112                                 /*
3113                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3114                                  * the latter has length 2-3 instead of 6 (reverse constant
3115                                  * propagation). These instruction sequences are very common
3116                                  * in the initlocals bblock.
3117                                  */
3118                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3119                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3120                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3121                                                 ins2->sreg1 = ins->dreg;
3122                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3123                                                 /* Continue */
3124                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3125                                                 NULLIFY_INS (ins2);
3126                                                 /* Continue */
3127                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3128                                                 /* Continue */
3129                                         } else {
3130                                                 break;
3131                                         }
3132                                 }
3133                         }
3134                         break;
3135                 case OP_IADD_IMM:
3136                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3137                                 ins->opcode = OP_X86_INC_REG;
3138                         break;
3139                 case OP_ISUB_IMM:
3140                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3141                                 ins->opcode = OP_X86_DEC_REG;
3142                         break;
3143                 }
3144
3145                 mono_peephole_ins (bb, ins);
3146         }
3147 }
3148
3149 #define NEW_INS(cfg,ins,dest,op) do {   \
3150                 MONO_INST_NEW ((cfg), (dest), (op)); \
3151         (dest)->cil_code = (ins)->cil_code; \
3152         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3153         } while (0)
3154
3155 /*
3156  * mono_arch_lowering_pass:
3157  *
3158  *  Converts complex opcodes into simpler ones so that each IR instruction
3159  * corresponds to one machine instruction.
3160  */
3161 void
3162 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3163 {
3164         MonoInst *ins, *n, *temp;
3165
3166         /*
3167          * FIXME: Need to add more instructions, but the current machine
3168          * description can't model some parts of the composite instructions like
3169          * cdq.
3170          */
3171         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3172                 switch (ins->opcode) {
3173                 case OP_DIV_IMM:
3174                 case OP_REM_IMM:
3175                 case OP_IDIV_IMM:
3176                 case OP_IDIV_UN_IMM:
3177                 case OP_IREM_UN_IMM:
3178                 case OP_LREM_IMM:
3179                 case OP_IREM_IMM:
3180                         mono_decompose_op_imm (cfg, bb, ins);
3181                         break;
3182                 case OP_COMPARE_IMM:
3183                 case OP_LCOMPARE_IMM:
3184                         if (!amd64_is_imm32 (ins->inst_imm)) {
3185                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3186                                 temp->inst_c0 = ins->inst_imm;
3187                                 temp->dreg = mono_alloc_ireg (cfg);
3188                                 ins->opcode = OP_COMPARE;
3189                                 ins->sreg2 = temp->dreg;
3190                         }
3191                         break;
3192 #ifndef __mono_ilp32__
3193                 case OP_LOAD_MEMBASE:
3194 #endif
3195                 case OP_LOADI8_MEMBASE:
3196 #ifndef __native_client_codegen__
3197                 /*  Don't generate memindex opcodes (to simplify */
3198                 /*  read sandboxing) */
3199                         if (!amd64_is_imm32 (ins->inst_offset)) {
3200                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3201                                 temp->inst_c0 = ins->inst_offset;
3202                                 temp->dreg = mono_alloc_ireg (cfg);
3203                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3204                                 ins->inst_indexreg = temp->dreg;
3205                         }
3206 #endif
3207                         break;
3208 #ifndef __mono_ilp32__
3209                 case OP_STORE_MEMBASE_IMM:
3210 #endif
3211                 case OP_STOREI8_MEMBASE_IMM:
3212                         if (!amd64_is_imm32 (ins->inst_imm)) {
3213                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3214                                 temp->inst_c0 = ins->inst_imm;
3215                                 temp->dreg = mono_alloc_ireg (cfg);
3216                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3217                                 ins->sreg1 = temp->dreg;
3218                         }
3219                         break;
3220 #ifdef MONO_ARCH_SIMD_INTRINSICS
3221                 case OP_EXPAND_I1: {
3222                                 int temp_reg1 = mono_alloc_ireg (cfg);
3223                                 int temp_reg2 = mono_alloc_ireg (cfg);
3224                                 int original_reg = ins->sreg1;
3225
3226                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3227                                 temp->sreg1 = original_reg;
3228                                 temp->dreg = temp_reg1;
3229
3230                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3231                                 temp->sreg1 = temp_reg1;
3232                                 temp->dreg = temp_reg2;
3233                                 temp->inst_imm = 8;
3234
3235                                 NEW_INS (cfg, ins, temp, OP_LOR);
3236                                 temp->sreg1 = temp->dreg = temp_reg2;
3237                                 temp->sreg2 = temp_reg1;
3238
3239                                 ins->opcode = OP_EXPAND_I2;
3240                                 ins->sreg1 = temp_reg2;
3241                         }
3242                         break;
3243 #endif
3244                 default:
3245                         break;
3246                 }
3247         }
3248
3249         bb->max_vreg = cfg->next_vreg;
3250 }
3251
3252 static const int
3253 branch_cc_table [] = {
3254         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3255         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3256         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3257 };
3258
3259 /* Maps CMP_... constants to X86_CC_... constants */
3260 static const int
3261 cc_table [] = {
3262         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3263         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3264 };
3265
3266 static const int
3267 cc_signed_table [] = {
3268         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3269         FALSE, FALSE, FALSE, FALSE
3270 };
3271
3272 /*#include "cprop.c"*/
3273
3274 static unsigned char*
3275 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3276 {
3277         if (size == 8)
3278                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3279         else
3280                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3281
3282         if (size == 1)
3283                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3284         else if (size == 2)
3285                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3286         return code;
3287 }
3288
3289 static unsigned char*
3290 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3291 {
3292         int sreg = tree->sreg1;
3293         int need_touch = FALSE;
3294
3295 #if defined(TARGET_WIN32)
3296         need_touch = TRUE;
3297 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3298         if (!tree->flags & MONO_INST_INIT)
3299                 need_touch = TRUE;
3300 #endif
3301
3302         if (need_touch) {
3303                 guint8* br[5];
3304
3305                 /*
3306                  * Under Windows:
3307                  * If requested stack size is larger than one page,
3308                  * perform stack-touch operation
3309                  */
3310                 /*
3311                  * Generate stack probe code.
3312                  * Under Windows, it is necessary to allocate one page at a time,
3313                  * "touching" stack after each successful sub-allocation. This is
3314                  * because of the way stack growth is implemented - there is a
3315                  * guard page before the lowest stack page that is currently commited.
3316                  * Stack normally grows sequentially so OS traps access to the
3317                  * guard page and commits more pages when needed.
3318                  */
3319                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3320                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3321
3322                 br[2] = code; /* loop */
3323                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3324                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3325                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3326                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3327                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3328                 amd64_patch (br[3], br[2]);
3329                 amd64_test_reg_reg (code, sreg, sreg);
3330                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3331                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3332
3333                 br[1] = code; x86_jump8 (code, 0);
3334
3335                 amd64_patch (br[0], code);
3336                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3337                 amd64_patch (br[1], code);
3338                 amd64_patch (br[4], code);
3339         }
3340         else
3341                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3342
3343         if (tree->flags & MONO_INST_INIT) {
3344                 int offset = 0;
3345                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3346                         amd64_push_reg (code, AMD64_RAX);
3347                         offset += 8;
3348                 }
3349                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3350                         amd64_push_reg (code, AMD64_RCX);
3351                         offset += 8;
3352                 }
3353                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3354                         amd64_push_reg (code, AMD64_RDI);
3355                         offset += 8;
3356                 }
3357
3358                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3359                 if (sreg != AMD64_RCX)
3360                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3361                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3362
3363                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3364                 if (cfg->param_area)
3365                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3366                 amd64_cld (code);
3367 #if defined(__default_codegen__)
3368                 amd64_prefix (code, X86_REP_PREFIX);
3369                 amd64_stosl (code);
3370 #elif defined(__native_client_codegen__)
3371                 /* NaCl stos pseudo-instruction */
3372                 amd64_codegen_pre(code);
3373                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3374                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3375                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3376                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3377                 amd64_prefix (code, X86_REP_PREFIX);
3378                 amd64_stosl (code);
3379                 amd64_codegen_post(code);
3380 #endif /* __native_client_codegen__ */
3381
3382                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3383                         amd64_pop_reg (code, AMD64_RDI);
3384                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3385                         amd64_pop_reg (code, AMD64_RCX);
3386                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3387                         amd64_pop_reg (code, AMD64_RAX);
3388         }
3389         return code;
3390 }
3391
3392 static guint8*
3393 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3394 {
3395         CallInfo *cinfo;
3396         guint32 quad;
3397
3398         /* Move return value to the target register */
3399         /* FIXME: do this in the local reg allocator */
3400         switch (ins->opcode) {
3401         case OP_CALL:
3402         case OP_CALL_REG:
3403         case OP_CALL_MEMBASE:
3404         case OP_LCALL:
3405         case OP_LCALL_REG:
3406         case OP_LCALL_MEMBASE:
3407                 g_assert (ins->dreg == AMD64_RAX);
3408                 break;
3409         case OP_FCALL:
3410         case OP_FCALL_REG:
3411         case OP_FCALL_MEMBASE: {
3412                 MonoType *rtype = mini_get_underlying_type (cfg, ((MonoCallInst*)ins)->signature->ret);
3413                 if (rtype->type == MONO_TYPE_R4) {
3414                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3415                 }
3416                 else {
3417                         if (ins->dreg != AMD64_XMM0)
3418                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3419                 }
3420                 break;
3421         }
3422         case OP_RCALL:
3423         case OP_RCALL_REG:
3424         case OP_RCALL_MEMBASE:
3425                 if (ins->dreg != AMD64_XMM0)
3426                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3427                 break;
3428         case OP_VCALL:
3429         case OP_VCALL_REG:
3430         case OP_VCALL_MEMBASE:
3431         case OP_VCALL2:
3432         case OP_VCALL2_REG:
3433         case OP_VCALL2_MEMBASE:
3434                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3435                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3436                         MonoInst *loc = cfg->arch.vret_addr_loc;
3437
3438                         /* Load the destination address */
3439                         g_assert (loc->opcode == OP_REGOFFSET);
3440                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3441
3442                         for (quad = 0; quad < 2; quad ++) {
3443                                 switch (cinfo->ret.pair_storage [quad]) {
3444                                 case ArgInIReg:
3445                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3446                                         break;
3447                                 case ArgInFloatSSEReg:
3448                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3449                                         break;
3450                                 case ArgInDoubleSSEReg:
3451                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3452                                         break;
3453                                 case ArgNone:
3454                                         break;
3455                                 default:
3456                                         NOT_IMPLEMENTED;
3457                                 }
3458                         }
3459                 }
3460                 break;
3461         }
3462
3463         return code;
3464 }
3465
3466 #endif /* DISABLE_JIT */
3467
3468 #ifdef __APPLE__
3469 static int tls_gs_offset;
3470 #endif
3471
3472 gboolean
3473 mono_amd64_have_tls_get (void)
3474 {
3475 #ifdef TARGET_MACH
3476         static gboolean have_tls_get = FALSE;
3477         static gboolean inited = FALSE;
3478         guint8 *ins;
3479
3480         if (inited)
3481                 return have_tls_get;
3482
3483         ins = (guint8*)pthread_getspecific;
3484
3485         /*
3486          * We're looking for these two instructions:
3487          *
3488          * mov    %gs:[offset](,%rdi,8),%rax
3489          * retq
3490          */
3491         have_tls_get = ins [0] == 0x65 &&
3492                        ins [1] == 0x48 &&
3493                        ins [2] == 0x8b &&
3494                        ins [3] == 0x04 &&
3495                        ins [4] == 0xfd &&
3496                        ins [6] == 0x00 &&
3497                        ins [7] == 0x00 &&
3498                        ins [8] == 0x00 &&
3499                        ins [9] == 0xc3;
3500
3501         inited = TRUE;
3502
3503         tls_gs_offset = ins[5];
3504
3505         return have_tls_get;
3506 #elif defined(TARGET_ANDROID)
3507         return FALSE;
3508 #else
3509         return TRUE;
3510 #endif
3511 }
3512
3513 int
3514 mono_amd64_get_tls_gs_offset (void)
3515 {
3516 #ifdef TARGET_OSX
3517         return tls_gs_offset;
3518 #else
3519         g_assert_not_reached ();
3520         return -1;
3521 #endif
3522 }
3523
3524 /*
3525  * mono_amd64_emit_tls_get:
3526  * @code: buffer to store code to
3527  * @dreg: hard register where to place the result
3528  * @tls_offset: offset info
3529  *
3530  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3531  * the dreg register the item in the thread local storage identified
3532  * by tls_offset.
3533  *
3534  * Returns: a pointer to the end of the stored code
3535  */
3536 guint8*
3537 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3538 {
3539 #ifdef TARGET_WIN32
3540         if (tls_offset < 64) {
3541                 x86_prefix (code, X86_GS_PREFIX);
3542                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3543         } else {
3544                 guint8 *buf [16];
3545
3546                 g_assert (tls_offset < 0x440);
3547                 /* Load TEB->TlsExpansionSlots */
3548                 x86_prefix (code, X86_GS_PREFIX);
3549                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3550                 amd64_test_reg_reg (code, dreg, dreg);
3551                 buf [0] = code;
3552                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3553                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3554                 amd64_patch (buf [0], code);
3555         }
3556 #elif defined(__APPLE__)
3557         x86_prefix (code, X86_GS_PREFIX);
3558         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3559 #else
3560         if (optimize_for_xen) {
3561                 x86_prefix (code, X86_FS_PREFIX);
3562                 amd64_mov_reg_mem (code, dreg, 0, 8);
3563                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3564         } else {
3565                 x86_prefix (code, X86_FS_PREFIX);
3566                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3567         }
3568 #endif
3569         return code;
3570 }
3571
3572 static guint8*
3573 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3574 {
3575         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3576 #ifdef TARGET_OSX
3577         if (dreg != offset_reg)
3578                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3579         amd64_prefix (code, X86_GS_PREFIX);
3580         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3581 #elif defined(__linux__)
3582         int tmpreg = -1;
3583
3584         if (dreg == offset_reg) {
3585                 /* Use a temporary reg by saving it to the redzone */
3586                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3587                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3588                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3589                 offset_reg = tmpreg;
3590         }
3591         x86_prefix (code, X86_FS_PREFIX);
3592         amd64_mov_reg_mem (code, dreg, 0, 8);
3593         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3594         if (tmpreg != -1)
3595                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3596 #else
3597         g_assert_not_reached ();
3598 #endif
3599         return code;
3600 }
3601
3602 static guint8*
3603 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3604 {
3605 #ifdef TARGET_WIN32
3606         g_assert_not_reached ();
3607 #elif defined(__APPLE__)
3608         x86_prefix (code, X86_GS_PREFIX);
3609         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3610 #else
3611         g_assert (!optimize_for_xen);
3612         x86_prefix (code, X86_FS_PREFIX);
3613         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3614 #endif
3615         return code;
3616 }
3617
3618 static guint8*
3619 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3620 {
3621         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3622 #ifdef TARGET_WIN32
3623         g_assert_not_reached ();
3624 #elif defined(__APPLE__)
3625         x86_prefix (code, X86_GS_PREFIX);
3626         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3627 #else
3628         x86_prefix (code, X86_FS_PREFIX);
3629         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3630 #endif
3631         return code;
3632 }
3633
3634  /*
3635  * mono_arch_translate_tls_offset:
3636  *
3637  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3638  */
3639 int
3640 mono_arch_translate_tls_offset (int offset)
3641 {
3642 #ifdef __APPLE__
3643         return tls_gs_offset + (offset * 8);
3644 #else
3645         return offset;
3646 #endif
3647 }
3648
3649 /*
3650  * emit_setup_lmf:
3651  *
3652  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3653  */
3654 static guint8*
3655 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3656 {
3657         /*
3658          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3659          */
3660         /*
3661          * sp is saved right before calls but we need to save it here too so
3662          * async stack walks would work.
3663          */
3664         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3665         /* Save rbp */
3666         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3667         if (cfg->arch.omit_fp && cfa_offset != -1)
3668                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3669
3670         /* These can't contain refs */
3671         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3672         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3673         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3674         /* These are handled automatically by the stack marking code */
3675         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3676
3677         return code;
3678 }
3679
3680 #define REAL_PRINT_REG(text,reg) \
3681 mono_assert (reg >= 0); \
3682 amd64_push_reg (code, AMD64_RAX); \
3683 amd64_push_reg (code, AMD64_RDX); \
3684 amd64_push_reg (code, AMD64_RCX); \
3685 amd64_push_reg (code, reg); \
3686 amd64_push_imm (code, reg); \
3687 amd64_push_imm (code, text " %d %p\n"); \
3688 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3689 amd64_call_reg (code, AMD64_RAX); \
3690 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3691 amd64_pop_reg (code, AMD64_RCX); \
3692 amd64_pop_reg (code, AMD64_RDX); \
3693 amd64_pop_reg (code, AMD64_RAX);
3694
3695 /* benchmark and set based on cpu */
3696 #define LOOP_ALIGNMENT 8
3697 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3698
3699 #ifndef DISABLE_JIT
3700 void
3701 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3702 {
3703         MonoInst *ins;
3704         MonoCallInst *call;
3705         guint offset;
3706         guint8 *code = cfg->native_code + cfg->code_len;
3707         int max_len;
3708
3709         /* Fix max_offset estimate for each successor bb */
3710         if (cfg->opt & MONO_OPT_BRANCH) {
3711                 int current_offset = cfg->code_len;
3712                 MonoBasicBlock *current_bb;
3713                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3714                         current_bb->max_offset = current_offset;
3715                         current_offset += current_bb->max_length;
3716                 }
3717         }
3718
3719         if (cfg->opt & MONO_OPT_LOOP) {
3720                 int pad, align = LOOP_ALIGNMENT;
3721                 /* set alignment depending on cpu */
3722                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3723                         pad = align - pad;
3724                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3725                         amd64_padding (code, pad);
3726                         cfg->code_len += pad;
3727                         bb->native_offset = cfg->code_len;
3728                 }
3729         }
3730
3731 #if defined(__native_client_codegen__)
3732         /* For Native Client, all indirect call/jump targets must be */
3733         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3734         /* indirectly as well.                                       */
3735         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3736                                       (bb->flags & BB_EXCEPTION_HANDLER);
3737
3738         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3739                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3740                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3741                 cfg->code_len += pad;
3742                 bb->native_offset = cfg->code_len;
3743         }
3744 #endif  /*__native_client_codegen__*/
3745
3746         if (cfg->verbose_level > 2)
3747                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3748
3749         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3750                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3751                 g_assert (!cfg->compile_aot);
3752
3753                 cov->data [bb->dfn].cil_code = bb->cil_code;
3754                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3755                 /* this is not thread save, but good enough */
3756                 amd64_inc_membase (code, AMD64_R11, 0);
3757         }
3758
3759         offset = code - cfg->native_code;
3760
3761         mono_debug_open_block (cfg, bb, offset);
3762
3763     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3764                 x86_breakpoint (code);
3765
3766         MONO_BB_FOR_EACH_INS (bb, ins) {
3767                 offset = code - cfg->native_code;
3768
3769                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3770
3771 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3772
3773                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3774                         cfg->code_size *= 2;
3775                         cfg->native_code = mono_realloc_native_code(cfg);
3776                         code = cfg->native_code + offset;
3777                         cfg->stat_code_reallocs++;
3778                 }
3779
3780                 if (cfg->debug_info)
3781                         mono_debug_record_line_number (cfg, ins, offset);
3782
3783                 switch (ins->opcode) {
3784                 case OP_BIGMUL:
3785                         amd64_mul_reg (code, ins->sreg2, TRUE);
3786                         break;
3787                 case OP_BIGMUL_UN:
3788                         amd64_mul_reg (code, ins->sreg2, FALSE);
3789                         break;
3790                 case OP_X86_SETEQ_MEMBASE:
3791                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3792                         break;
3793                 case OP_STOREI1_MEMBASE_IMM:
3794                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3795                         break;
3796                 case OP_STOREI2_MEMBASE_IMM:
3797                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3798                         break;
3799                 case OP_STOREI4_MEMBASE_IMM:
3800                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3801                         break;
3802                 case OP_STOREI1_MEMBASE_REG:
3803                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3804                         break;
3805                 case OP_STOREI2_MEMBASE_REG:
3806                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3807                         break;
3808                 /* In AMD64 NaCl, pointers are 4 bytes, */
3809                 /*  so STORE_* != STOREI8_*. Likewise below. */
3810                 case OP_STORE_MEMBASE_REG:
3811                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3812                         break;
3813                 case OP_STOREI8_MEMBASE_REG:
3814                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3815                         break;
3816                 case OP_STOREI4_MEMBASE_REG:
3817                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3818                         break;
3819                 case OP_STORE_MEMBASE_IMM:
3820 #ifndef __native_client_codegen__
3821                         /* In NaCl, this could be a PCONST type, which could */
3822                         /* mean a pointer type was copied directly into the  */
3823                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3824                         /* the value would be 0x00000000FFFFFFFF which is    */
3825                         /* not proper for an imm32 unless you cast it.       */
3826                         g_assert (amd64_is_imm32 (ins->inst_imm));
3827 #endif
3828                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3829                         break;
3830                 case OP_STOREI8_MEMBASE_IMM:
3831                         g_assert (amd64_is_imm32 (ins->inst_imm));
3832                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3833                         break;
3834                 case OP_LOAD_MEM:
3835 #ifdef __mono_ilp32__
3836                         /* In ILP32, pointers are 4 bytes, so separate these */
3837                         /* cases, use literal 8 below where we really want 8 */
3838                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3839                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3840                         break;
3841 #endif
3842                 case OP_LOADI8_MEM:
3843                         // FIXME: Decompose this earlier
3844                         if (amd64_is_imm32 (ins->inst_imm))
3845                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3846                         else {
3847                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3848                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3849                         }
3850                         break;
3851                 case OP_LOADI4_MEM:
3852                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3853                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3854                         break;
3855                 case OP_LOADU4_MEM:
3856                         // FIXME: Decompose this earlier
3857                         if (amd64_is_imm32 (ins->inst_imm))
3858                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3859                         else {
3860                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3861                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3862                         }
3863                         break;
3864                 case OP_LOADU1_MEM:
3865                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3866                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3867                         break;
3868                 case OP_LOADU2_MEM:
3869                         /* For NaCl, pointers are 4 bytes, so separate these */
3870                         /* cases, use literal 8 below where we really want 8 */
3871                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3872                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3873                         break;
3874                 case OP_LOAD_MEMBASE:
3875                         g_assert (amd64_is_imm32 (ins->inst_offset));
3876                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3877                         break;
3878                 case OP_LOADI8_MEMBASE:
3879                         /* Use literal 8 instead of sizeof pointer or */
3880                         /* register, we really want 8 for this opcode */
3881                         g_assert (amd64_is_imm32 (ins->inst_offset));
3882                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3883                         break;
3884                 case OP_LOADI4_MEMBASE:
3885                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3886                         break;
3887                 case OP_LOADU4_MEMBASE:
3888                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3889                         break;
3890                 case OP_LOADU1_MEMBASE:
3891                         /* The cpu zero extends the result into 64 bits */
3892                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3893                         break;
3894                 case OP_LOADI1_MEMBASE:
3895                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3896                         break;
3897                 case OP_LOADU2_MEMBASE:
3898                         /* The cpu zero extends the result into 64 bits */
3899                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3900                         break;
3901                 case OP_LOADI2_MEMBASE:
3902                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3903                         break;
3904                 case OP_AMD64_LOADI8_MEMINDEX:
3905                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3906                         break;
3907                 case OP_LCONV_TO_I1:
3908                 case OP_ICONV_TO_I1:
3909                 case OP_SEXT_I1:
3910                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3911                         break;
3912                 case OP_LCONV_TO_I2:
3913                 case OP_ICONV_TO_I2:
3914                 case OP_SEXT_I2:
3915                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3916                         break;
3917                 case OP_LCONV_TO_U1:
3918                 case OP_ICONV_TO_U1:
3919                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3920                         break;
3921                 case OP_LCONV_TO_U2:
3922                 case OP_ICONV_TO_U2:
3923                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3924                         break;
3925                 case OP_ZEXT_I4:
3926                         /* Clean out the upper word */
3927                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3928                         break;
3929                 case OP_SEXT_I4:
3930                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3931                         break;
3932                 case OP_COMPARE:
3933                 case OP_LCOMPARE:
3934                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3935                         break;
3936                 case OP_COMPARE_IMM:
3937 #if defined(__mono_ilp32__)
3938                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3939                         g_assert (amd64_is_imm32 (ins->inst_imm));
3940                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3941                         break;
3942 #endif
3943                 case OP_LCOMPARE_IMM:
3944                         g_assert (amd64_is_imm32 (ins->inst_imm));
3945                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3946                         break;
3947                 case OP_X86_COMPARE_REG_MEMBASE:
3948                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3949                         break;
3950                 case OP_X86_TEST_NULL:
3951                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3952                         break;
3953                 case OP_AMD64_TEST_NULL:
3954                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3955                         break;
3956
3957                 case OP_X86_ADD_REG_MEMBASE:
3958                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3959                         break;
3960                 case OP_X86_SUB_REG_MEMBASE:
3961                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3962                         break;
3963                 case OP_X86_AND_REG_MEMBASE:
3964                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3965                         break;
3966                 case OP_X86_OR_REG_MEMBASE:
3967                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3968                         break;
3969                 case OP_X86_XOR_REG_MEMBASE:
3970                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3971                         break;
3972
3973                 case OP_X86_ADD_MEMBASE_IMM:
3974                         /* FIXME: Make a 64 version too */
3975                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3976                         break;
3977                 case OP_X86_SUB_MEMBASE_IMM:
3978                         g_assert (amd64_is_imm32 (ins->inst_imm));
3979                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3980                         break;
3981                 case OP_X86_AND_MEMBASE_IMM:
3982                         g_assert (amd64_is_imm32 (ins->inst_imm));
3983                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3984                         break;
3985                 case OP_X86_OR_MEMBASE_IMM:
3986                         g_assert (amd64_is_imm32 (ins->inst_imm));
3987                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3988                         break;
3989                 case OP_X86_XOR_MEMBASE_IMM:
3990                         g_assert (amd64_is_imm32 (ins->inst_imm));
3991                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3992                         break;
3993                 case OP_X86_ADD_MEMBASE_REG:
3994                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3995                         break;
3996                 case OP_X86_SUB_MEMBASE_REG:
3997                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3998                         break;
3999                 case OP_X86_AND_MEMBASE_REG:
4000                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4001                         break;
4002                 case OP_X86_OR_MEMBASE_REG:
4003                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4004                         break;
4005                 case OP_X86_XOR_MEMBASE_REG:
4006                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4007                         break;
4008                 case OP_X86_INC_MEMBASE:
4009                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4010                         break;
4011                 case OP_X86_INC_REG:
4012                         amd64_inc_reg_size (code, ins->dreg, 4);
4013                         break;
4014                 case OP_X86_DEC_MEMBASE:
4015                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4016                         break;
4017                 case OP_X86_DEC_REG:
4018                         amd64_dec_reg_size (code, ins->dreg, 4);
4019                         break;
4020                 case OP_X86_MUL_REG_MEMBASE:
4021                 case OP_X86_MUL_MEMBASE_REG:
4022                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4023                         break;
4024                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4025                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4026                         break;
4027                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4028                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4029                         break;
4030                 case OP_AMD64_COMPARE_MEMBASE_REG:
4031                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4032                         break;
4033                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4034                         g_assert (amd64_is_imm32 (ins->inst_imm));
4035                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4036                         break;
4037                 case OP_X86_COMPARE_MEMBASE8_IMM:
4038                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4039                         break;
4040                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4041                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4042                         break;
4043                 case OP_AMD64_COMPARE_REG_MEMBASE:
4044                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4045                         break;
4046
4047                 case OP_AMD64_ADD_REG_MEMBASE:
4048                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4049                         break;
4050                 case OP_AMD64_SUB_REG_MEMBASE:
4051                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4052                         break;
4053                 case OP_AMD64_AND_REG_MEMBASE:
4054                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4055                         break;
4056                 case OP_AMD64_OR_REG_MEMBASE:
4057                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4058                         break;
4059                 case OP_AMD64_XOR_REG_MEMBASE:
4060                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4061                         break;
4062
4063                 case OP_AMD64_ADD_MEMBASE_REG:
4064                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4065                         break;
4066                 case OP_AMD64_SUB_MEMBASE_REG:
4067                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4068                         break;
4069                 case OP_AMD64_AND_MEMBASE_REG:
4070                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4071                         break;
4072                 case OP_AMD64_OR_MEMBASE_REG:
4073                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4074                         break;
4075                 case OP_AMD64_XOR_MEMBASE_REG:
4076                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4077                         break;
4078
4079                 case OP_AMD64_ADD_MEMBASE_IMM:
4080                         g_assert (amd64_is_imm32 (ins->inst_imm));
4081                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4082                         break;
4083                 case OP_AMD64_SUB_MEMBASE_IMM:
4084                         g_assert (amd64_is_imm32 (ins->inst_imm));
4085                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4086                         break;
4087                 case OP_AMD64_AND_MEMBASE_IMM:
4088                         g_assert (amd64_is_imm32 (ins->inst_imm));
4089                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4090                         break;
4091                 case OP_AMD64_OR_MEMBASE_IMM:
4092                         g_assert (amd64_is_imm32 (ins->inst_imm));
4093                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4094                         break;
4095                 case OP_AMD64_XOR_MEMBASE_IMM:
4096                         g_assert (amd64_is_imm32 (ins->inst_imm));
4097                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4098                         break;
4099
4100                 case OP_BREAK:
4101                         amd64_breakpoint (code);
4102                         break;
4103                 case OP_RELAXED_NOP:
4104                         x86_prefix (code, X86_REP_PREFIX);
4105                         x86_nop (code);
4106                         break;
4107                 case OP_HARD_NOP:
4108                         x86_nop (code);
4109                         break;
4110                 case OP_NOP:
4111                 case OP_DUMMY_USE:
4112                 case OP_DUMMY_STORE:
4113                 case OP_DUMMY_ICONST:
4114                 case OP_DUMMY_R8CONST:
4115                 case OP_NOT_REACHED:
4116                 case OP_NOT_NULL:
4117                         break;
4118                 case OP_IL_SEQ_POINT:
4119                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4120                         break;
4121                 case OP_SEQ_POINT: {
4122                         int i;
4123
4124                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4125                                 if (cfg->compile_aot) {
4126                                         MonoInst *var = cfg->arch.ss_tramp_var;
4127                                         guint8 *label;
4128
4129                                         /* Load ss_tramp_var */
4130                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4131                                         /* Load the trampoline address */
4132                                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4133                                         /* Call it if it is non-null */
4134                                         amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4135                                         label = code;
4136                                         amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4137                                         amd64_call_reg (code, AMD64_R11);
4138                                         amd64_patch (label, code);
4139                                 } else {
4140                                         /*
4141                                          * Read from the single stepping trigger page. This will cause a
4142                                          * SIGSEGV when single stepping is enabled.
4143                                          * We do this _before_ the breakpoint, so single stepping after
4144                                          * a breakpoint is hit will step to the next IL offset.
4145                                          */
4146                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
4147
4148                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4149                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4150                                 }
4151                         }
4152
4153                         /*
4154                          * This is the address which is saved in seq points,
4155                          */
4156                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4157
4158                         if (cfg->compile_aot) {
4159                                 guint32 offset = code - cfg->native_code;
4160                                 guint32 val;
4161                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4162                                 guint8 *label;
4163
4164                                 /* Load info var */
4165                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4166                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4167                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4168                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4169                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4170                                 label = code;
4171                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4172                                 /* Call the trampoline */
4173                                 amd64_call_reg (code, AMD64_R11);
4174                                 amd64_patch (label, code);
4175                         } else {
4176                                 /*
4177                                  * A placeholder for a possible breakpoint inserted by
4178                                  * mono_arch_set_breakpoint ().
4179                                  */
4180                                 for (i = 0; i < breakpoint_size; ++i)
4181                                         x86_nop (code);
4182                         }
4183                         /*
4184                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4185                          * to another IL offset.
4186                          */
4187                         x86_nop (code);
4188                         break;
4189                 }
4190                 case OP_ADDCC:
4191                 case OP_LADDCC:
4192                 case OP_LADD:
4193                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4194                         break;
4195                 case OP_ADC:
4196                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4197                         break;
4198                 case OP_ADD_IMM:
4199                 case OP_LADD_IMM:
4200                         g_assert (amd64_is_imm32 (ins->inst_imm));
4201                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4202                         break;
4203                 case OP_ADC_IMM:
4204                         g_assert (amd64_is_imm32 (ins->inst_imm));
4205                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4206                         break;
4207                 case OP_SUBCC:
4208                 case OP_LSUBCC:
4209                 case OP_LSUB:
4210                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4211                         break;
4212                 case OP_SBB:
4213                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4214                         break;
4215                 case OP_SUB_IMM:
4216                 case OP_LSUB_IMM:
4217                         g_assert (amd64_is_imm32 (ins->inst_imm));
4218                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4219                         break;
4220                 case OP_SBB_IMM:
4221                         g_assert (amd64_is_imm32 (ins->inst_imm));
4222                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4223                         break;
4224                 case OP_LAND:
4225                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4226                         break;
4227                 case OP_AND_IMM:
4228                 case OP_LAND_IMM:
4229                         g_assert (amd64_is_imm32 (ins->inst_imm));
4230                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4231                         break;
4232                 case OP_LMUL:
4233                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4234                         break;
4235                 case OP_MUL_IMM:
4236                 case OP_LMUL_IMM:
4237                 case OP_IMUL_IMM: {
4238                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4239
4240                         switch (ins->inst_imm) {
4241                         case 2:
4242                                 /* MOV r1, r2 */
4243                                 /* ADD r1, r1 */
4244                                 if (ins->dreg != ins->sreg1)
4245                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4246                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4247                                 break;
4248                         case 3:
4249                                 /* LEA r1, [r2 + r2*2] */
4250                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4251                                 break;
4252                         case 5:
4253                                 /* LEA r1, [r2 + r2*4] */
4254                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4255                                 break;
4256                         case 6:
4257                                 /* LEA r1, [r2 + r2*2] */
4258                                 /* ADD r1, r1          */
4259                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4260                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4261                                 break;
4262                         case 9:
4263                                 /* LEA r1, [r2 + r2*8] */
4264                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4265                                 break;
4266                         case 10:
4267                                 /* LEA r1, [r2 + r2*4] */
4268                                 /* ADD r1, r1          */
4269                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4270                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4271                                 break;
4272                         case 12:
4273                                 /* LEA r1, [r2 + r2*2] */
4274                                 /* SHL r1, 2           */
4275                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4276                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4277                                 break;
4278                         case 25:
4279                                 /* LEA r1, [r2 + r2*4] */
4280                                 /* LEA r1, [r1 + r1*4] */
4281                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4282                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4283                                 break;
4284                         case 100:
4285                                 /* LEA r1, [r2 + r2*4] */
4286                                 /* SHL r1, 2           */
4287                                 /* LEA r1, [r1 + r1*4] */
4288                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4289                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4290                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4291                                 break;
4292                         default:
4293                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4294                                 break;
4295                         }
4296                         break;
4297                 }
4298                 case OP_LDIV:
4299                 case OP_LREM:
4300 #if defined( __native_client_codegen__ )
4301                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4302                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4303 #endif
4304                         /* Regalloc magic makes the div/rem cases the same */
4305                         if (ins->sreg2 == AMD64_RDX) {
4306                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4307                                 amd64_cdq (code);
4308                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4309                         } else {
4310                                 amd64_cdq (code);
4311                                 amd64_div_reg (code, ins->sreg2, TRUE);
4312                         }
4313                         break;
4314                 case OP_LDIV_UN:
4315                 case OP_LREM_UN:
4316 #if defined( __native_client_codegen__ )
4317                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4318                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4319 #endif
4320                         if (ins->sreg2 == AMD64_RDX) {
4321                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4322                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4323                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4324                         } else {
4325                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4326                                 amd64_div_reg (code, ins->sreg2, FALSE);
4327                         }
4328                         break;
4329                 case OP_IDIV:
4330                 case OP_IREM:
4331 #if defined( __native_client_codegen__ )
4332                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4333                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4334 #endif
4335                         if (ins->sreg2 == AMD64_RDX) {
4336                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4337                                 amd64_cdq_size (code, 4);
4338                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4339                         } else {
4340                                 amd64_cdq_size (code, 4);
4341                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4342                         }
4343                         break;
4344                 case OP_IDIV_UN:
4345                 case OP_IREM_UN:
4346 #if defined( __native_client_codegen__ )
4347                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4348                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4349 #endif
4350                         if (ins->sreg2 == AMD64_RDX) {
4351                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4352                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4353                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4354                         } else {
4355                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4356                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4357                         }
4358                         break;
4359                 case OP_LMUL_OVF:
4360                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4361                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4362                         break;
4363                 case OP_LOR:
4364                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4365                         break;
4366                 case OP_OR_IMM:
4367                 case OP_LOR_IMM:
4368                         g_assert (amd64_is_imm32 (ins->inst_imm));
4369                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4370                         break;
4371                 case OP_LXOR:
4372                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4373                         break;
4374                 case OP_XOR_IMM:
4375                 case OP_LXOR_IMM:
4376                         g_assert (amd64_is_imm32 (ins->inst_imm));
4377                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4378                         break;
4379                 case OP_LSHL:
4380                         g_assert (ins->sreg2 == AMD64_RCX);
4381                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4382                         break;
4383                 case OP_LSHR:
4384                         g_assert (ins->sreg2 == AMD64_RCX);
4385                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4386                         break;
4387                 case OP_SHR_IMM:
4388                 case OP_LSHR_IMM:
4389                         g_assert (amd64_is_imm32 (ins->inst_imm));
4390                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4391                         break;
4392                 case OP_SHR_UN_IMM:
4393                         g_assert (amd64_is_imm32 (ins->inst_imm));
4394                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4395                         break;
4396                 case OP_LSHR_UN_IMM:
4397                         g_assert (amd64_is_imm32 (ins->inst_imm));
4398                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4399                         break;
4400                 case OP_LSHR_UN:
4401                         g_assert (ins->sreg2 == AMD64_RCX);
4402                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4403                         break;
4404                 case OP_SHL_IMM:
4405                 case OP_LSHL_IMM:
4406                         g_assert (amd64_is_imm32 (ins->inst_imm));
4407                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4408                         break;
4409
4410                 case OP_IADDCC:
4411                 case OP_IADD:
4412                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4413                         break;
4414                 case OP_IADC:
4415                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4416                         break;
4417                 case OP_IADD_IMM:
4418                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4419                         break;
4420                 case OP_IADC_IMM:
4421                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4422                         break;
4423                 case OP_ISUBCC:
4424                 case OP_ISUB:
4425                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4426                         break;
4427                 case OP_ISBB:
4428                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4429                         break;
4430                 case OP_ISUB_IMM:
4431                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4432                         break;
4433                 case OP_ISBB_IMM:
4434                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4435                         break;
4436                 case OP_IAND:
4437                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4438                         break;
4439                 case OP_IAND_IMM:
4440                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4441                         break;
4442                 case OP_IOR:
4443                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4444                         break;
4445                 case OP_IOR_IMM:
4446                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4447                         break;
4448                 case OP_IXOR:
4449                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4450                         break;
4451                 case OP_IXOR_IMM:
4452                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4453                         break;
4454                 case OP_INEG:
4455                         amd64_neg_reg_size (code, ins->sreg1, 4);
4456                         break;
4457                 case OP_INOT:
4458                         amd64_not_reg_size (code, ins->sreg1, 4);
4459                         break;
4460                 case OP_ISHL:
4461                         g_assert (ins->sreg2 == AMD64_RCX);
4462                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4463                         break;
4464                 case OP_ISHR:
4465                         g_assert (ins->sreg2 == AMD64_RCX);
4466                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4467                         break;
4468                 case OP_ISHR_IMM:
4469                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4470                         break;
4471                 case OP_ISHR_UN_IMM:
4472                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4473                         break;
4474                 case OP_ISHR_UN:
4475                         g_assert (ins->sreg2 == AMD64_RCX);
4476                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4477                         break;
4478                 case OP_ISHL_IMM:
4479                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4480                         break;
4481                 case OP_IMUL:
4482                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4483                         break;
4484                 case OP_IMUL_OVF:
4485                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4486                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4487                         break;
4488                 case OP_IMUL_OVF_UN:
4489                 case OP_LMUL_OVF_UN: {
4490                         /* the mul operation and the exception check should most likely be split */
4491                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4492                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4493                         /*g_assert (ins->sreg2 == X86_EAX);
4494                         g_assert (ins->dreg == X86_EAX);*/
4495                         if (ins->sreg2 == X86_EAX) {
4496                                 non_eax_reg = ins->sreg1;
4497                         } else if (ins->sreg1 == X86_EAX) {
4498                                 non_eax_reg = ins->sreg2;
4499                         } else {
4500                                 /* no need to save since we're going to store to it anyway */
4501                                 if (ins->dreg != X86_EAX) {
4502                                         saved_eax = TRUE;
4503                                         amd64_push_reg (code, X86_EAX);
4504                                 }
4505                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4506                                 non_eax_reg = ins->sreg2;
4507                         }
4508                         if (ins->dreg == X86_EDX) {
4509                                 if (!saved_eax) {
4510                                         saved_eax = TRUE;
4511                                         amd64_push_reg (code, X86_EAX);
4512                                 }
4513                         } else {
4514                                 saved_edx = TRUE;
4515                                 amd64_push_reg (code, X86_EDX);
4516                         }
4517                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4518                         /* save before the check since pop and mov don't change the flags */
4519                         if (ins->dreg != X86_EAX)
4520                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4521                         if (saved_edx)
4522                                 amd64_pop_reg (code, X86_EDX);
4523                         if (saved_eax)
4524                                 amd64_pop_reg (code, X86_EAX);
4525                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4526                         break;
4527                 }
4528                 case OP_ICOMPARE:
4529                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4530                         break;
4531                 case OP_ICOMPARE_IMM:
4532                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4533                         break;
4534                 case OP_IBEQ:
4535                 case OP_IBLT:
4536                 case OP_IBGT:
4537                 case OP_IBGE:
4538                 case OP_IBLE:
4539                 case OP_LBEQ:
4540                 case OP_LBLT:
4541                 case OP_LBGT:
4542                 case OP_LBGE:
4543                 case OP_LBLE:
4544                 case OP_IBNE_UN:
4545                 case OP_IBLT_UN:
4546                 case OP_IBGT_UN:
4547                 case OP_IBGE_UN:
4548                 case OP_IBLE_UN:
4549                 case OP_LBNE_UN:
4550                 case OP_LBLT_UN:
4551                 case OP_LBGT_UN:
4552                 case OP_LBGE_UN:
4553                 case OP_LBLE_UN:
4554                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4555                         break;
4556
4557                 case OP_CMOV_IEQ:
4558                 case OP_CMOV_IGE:
4559                 case OP_CMOV_IGT:
4560                 case OP_CMOV_ILE:
4561                 case OP_CMOV_ILT:
4562                 case OP_CMOV_INE_UN:
4563                 case OP_CMOV_IGE_UN:
4564                 case OP_CMOV_IGT_UN:
4565                 case OP_CMOV_ILE_UN:
4566                 case OP_CMOV_ILT_UN:
4567                 case OP_CMOV_LEQ:
4568                 case OP_CMOV_LGE:
4569                 case OP_CMOV_LGT:
4570                 case OP_CMOV_LLE:
4571                 case OP_CMOV_LLT:
4572                 case OP_CMOV_LNE_UN:
4573                 case OP_CMOV_LGE_UN:
4574                 case OP_CMOV_LGT_UN:
4575                 case OP_CMOV_LLE_UN:
4576                 case OP_CMOV_LLT_UN:
4577                         g_assert (ins->dreg == ins->sreg1);
4578                         /* This needs to operate on 64 bit values */
4579                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4580                         break;
4581
4582                 case OP_LNOT:
4583                         amd64_not_reg (code, ins->sreg1);
4584                         break;
4585                 case OP_LNEG:
4586                         amd64_neg_reg (code, ins->sreg1);
4587                         break;
4588
4589                 case OP_ICONST:
4590                 case OP_I8CONST:
4591                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4592                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4593                         else
4594                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4595                         break;
4596                 case OP_AOTCONST:
4597                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4598                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4599                         break;
4600                 case OP_JUMP_TABLE:
4601                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4602                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4603                         break;
4604                 case OP_MOVE:
4605                         if (ins->dreg != ins->sreg1)
4606                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4607                         break;
4608                 case OP_AMD64_SET_XMMREG_R4: {
4609                         if (cfg->r4fp) {
4610                                 if (ins->dreg != ins->sreg1)
4611                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4612                         } else {
4613                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4614                         }
4615                         break;
4616                 }
4617                 case OP_AMD64_SET_XMMREG_R8: {
4618                         if (ins->dreg != ins->sreg1)
4619                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4620                         break;
4621                 }
4622                 case OP_TAILCALL: {
4623                         MonoCallInst *call = (MonoCallInst*)ins;
4624                         int i, save_area_offset;
4625
4626                         g_assert (!cfg->method->save_lmf);
4627
4628                         /* Restore callee saved registers */
4629                         save_area_offset = cfg->arch.reg_save_area_offset;
4630                         for (i = 0; i < AMD64_NREG; ++i)
4631                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4632                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4633                                         save_area_offset += 8;
4634                                 }
4635
4636                         if (cfg->arch.omit_fp) {
4637                                 if (cfg->arch.stack_alloc_size)
4638                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4639                                 // FIXME:
4640                                 if (call->stack_usage)
4641                                         NOT_IMPLEMENTED;
4642                         } else {
4643                                 /* Copy arguments on the stack to our argument area */
4644                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4645                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4646                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4647                                 }
4648
4649                                 amd64_leave (code);
4650                         }
4651
4652                         offset = code - cfg->native_code;
4653                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4654                         if (cfg->compile_aot)
4655                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4656                         else
4657                                 amd64_set_reg_template (code, AMD64_R11);
4658                         amd64_jump_reg (code, AMD64_R11);
4659                         ins->flags |= MONO_INST_GC_CALLSITE;
4660                         ins->backend.pc_offset = code - cfg->native_code;
4661                         break;
4662                 }
4663                 case OP_CHECK_THIS:
4664                         /* ensure ins->sreg1 is not NULL */
4665                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4666                         break;
4667                 case OP_ARGLIST: {
4668                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4669                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4670                         break;
4671                 }
4672                 case OP_CALL:
4673                 case OP_FCALL:
4674                 case OP_RCALL:
4675                 case OP_LCALL:
4676                 case OP_VCALL:
4677                 case OP_VCALL2:
4678                 case OP_VOIDCALL:
4679                         call = (MonoCallInst*)ins;
4680                         /*
4681                          * The AMD64 ABI forces callers to know about varargs.
4682                          */
4683                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4684                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4685                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4686                                 /*
4687                                  * Since the unmanaged calling convention doesn't contain a
4688                                  * 'vararg' entry, we have to treat every pinvoke call as a
4689                                  * potential vararg call.
4690                                  */
4691                                 guint32 nregs, i;
4692                                 nregs = 0;
4693                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4694                                         if (call->used_fregs & (1 << i))
4695                                                 nregs ++;
4696                                 if (!nregs)
4697                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4698                                 else
4699                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4700                         }
4701
4702                         if (ins->flags & MONO_INST_HAS_METHOD)
4703                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4704                         else
4705                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4706                         ins->flags |= MONO_INST_GC_CALLSITE;
4707                         ins->backend.pc_offset = code - cfg->native_code;
4708                         code = emit_move_return_value (cfg, ins, code);
4709                         break;
4710                 case OP_FCALL_REG:
4711                 case OP_RCALL_REG:
4712                 case OP_LCALL_REG:
4713                 case OP_VCALL_REG:
4714                 case OP_VCALL2_REG:
4715                 case OP_VOIDCALL_REG:
4716                 case OP_CALL_REG:
4717                         call = (MonoCallInst*)ins;
4718
4719                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4720                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4721                                 ins->sreg1 = AMD64_R11;
4722                         }
4723
4724                         /*
4725                          * The AMD64 ABI forces callers to know about varargs.
4726                          */
4727                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4728                                 if (ins->sreg1 == AMD64_RAX) {
4729                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4730                                         ins->sreg1 = AMD64_R11;
4731                                 }
4732                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4733                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4734                                 /*
4735                                  * Since the unmanaged calling convention doesn't contain a
4736                                  * 'vararg' entry, we have to treat every pinvoke call as a
4737                                  * potential vararg call.
4738                                  */
4739                                 guint32 nregs, i;
4740                                 nregs = 0;
4741                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4742                                         if (call->used_fregs & (1 << i))
4743                                                 nregs ++;
4744                                 if (ins->sreg1 == AMD64_RAX) {
4745                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4746                                         ins->sreg1 = AMD64_R11;
4747                                 }
4748                                 if (!nregs)
4749                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4750                                 else
4751                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4752                         }
4753
4754                         amd64_call_reg (code, ins->sreg1);
4755                         ins->flags |= MONO_INST_GC_CALLSITE;
4756                         ins->backend.pc_offset = code - cfg->native_code;
4757                         code = emit_move_return_value (cfg, ins, code);
4758                         break;
4759                 case OP_FCALL_MEMBASE:
4760                 case OP_RCALL_MEMBASE:
4761                 case OP_LCALL_MEMBASE:
4762                 case OP_VCALL_MEMBASE:
4763                 case OP_VCALL2_MEMBASE:
4764                 case OP_VOIDCALL_MEMBASE:
4765                 case OP_CALL_MEMBASE:
4766                         call = (MonoCallInst*)ins;
4767
4768                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4769                         ins->flags |= MONO_INST_GC_CALLSITE;
4770                         ins->backend.pc_offset = code - cfg->native_code;
4771                         code = emit_move_return_value (cfg, ins, code);
4772                         break;
4773                 case OP_DYN_CALL: {
4774                         int i;
4775                         MonoInst *var = cfg->dyn_call_var;
4776
4777                         g_assert (var->opcode == OP_REGOFFSET);
4778
4779                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4780                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4781                         /* r10 = ftn */
4782                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4783
4784                         /* Save args buffer */
4785                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4786
4787                         /* Set argument registers */
4788                         for (i = 0; i < PARAM_REGS; ++i)
4789                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4790
4791                         /* Make the call */
4792                         amd64_call_reg (code, AMD64_R10);
4793
4794                         ins->flags |= MONO_INST_GC_CALLSITE;
4795                         ins->backend.pc_offset = code - cfg->native_code;
4796
4797                         /* Save result */
4798                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4799                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4800                         break;
4801                 }
4802                 case OP_AMD64_SAVE_SP_TO_LMF: {
4803                         MonoInst *lmf_var = cfg->lmf_var;
4804                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4805                         break;
4806                 }
4807                 case OP_X86_PUSH:
4808                         g_assert_not_reached ();
4809                         amd64_push_reg (code, ins->sreg1);
4810                         break;
4811                 case OP_X86_PUSH_IMM:
4812                         g_assert_not_reached ();
4813                         g_assert (amd64_is_imm32 (ins->inst_imm));
4814                         amd64_push_imm (code, ins->inst_imm);
4815                         break;
4816                 case OP_X86_PUSH_MEMBASE:
4817                         g_assert_not_reached ();
4818                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4819                         break;
4820                 case OP_X86_PUSH_OBJ: {
4821                         int size = ALIGN_TO (ins->inst_imm, 8);
4822
4823                         g_assert_not_reached ();
4824
4825                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4826                         amd64_push_reg (code, AMD64_RDI);
4827                         amd64_push_reg (code, AMD64_RSI);
4828                         amd64_push_reg (code, AMD64_RCX);
4829                         if (ins->inst_offset)
4830                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4831                         else
4832                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4833                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4834                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4835                         amd64_cld (code);
4836                         amd64_prefix (code, X86_REP_PREFIX);
4837                         amd64_movsd (code);
4838                         amd64_pop_reg (code, AMD64_RCX);
4839                         amd64_pop_reg (code, AMD64_RSI);
4840                         amd64_pop_reg (code, AMD64_RDI);
4841                         break;
4842                 }
4843                 case OP_GENERIC_CLASS_INIT: {
4844                         static int byte_offset = -1;
4845                         static guint8 bitmask;
4846                         guint8 *jump;
4847
4848                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4849
4850                         if (byte_offset < 0)
4851                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4852
4853                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4854                         jump = code;
4855                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4856
4857                         code = emit_call (cfg, code, MONO_PATCH_INFO_JIT_ICALL_ADDR, "specific_trampoline_generic_class_init", FALSE);
4858                         ins->flags |= MONO_INST_GC_CALLSITE;
4859                         ins->backend.pc_offset = code - cfg->native_code;
4860
4861                         x86_patch (jump, code);
4862                         break;
4863                 }
4864
4865                 case OP_X86_LEA:
4866                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4867                         break;
4868                 case OP_X86_LEA_MEMBASE:
4869                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4870                         break;
4871                 case OP_X86_XCHG:
4872                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4873                         break;
4874                 case OP_LOCALLOC:
4875                         /* keep alignment */
4876                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4877                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4878                         code = mono_emit_stack_alloc (cfg, code, ins);
4879                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4880                         if (cfg->param_area)
4881                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4882                         break;
4883                 case OP_LOCALLOC_IMM: {
4884                         guint32 size = ins->inst_imm;
4885                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4886
4887                         if (ins->flags & MONO_INST_INIT) {
4888                                 if (size < 64) {
4889                                         int i;
4890
4891                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4892                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4893
4894                                         for (i = 0; i < size; i += 8)
4895                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4896                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4897                                 } else {
4898                                         amd64_mov_reg_imm (code, ins->dreg, size);
4899                                         ins->sreg1 = ins->dreg;
4900
4901                                         code = mono_emit_stack_alloc (cfg, code, ins);
4902                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4903                                 }
4904                         } else {
4905                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4906                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4907                         }
4908                         if (cfg->param_area)
4909                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4910                         break;
4911                 }
4912                 case OP_THROW: {
4913                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4914                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4915                                              (gpointer)"mono_arch_throw_exception", FALSE);
4916                         ins->flags |= MONO_INST_GC_CALLSITE;
4917                         ins->backend.pc_offset = code - cfg->native_code;
4918                         break;
4919                 }
4920                 case OP_RETHROW: {
4921                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4922                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4923                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4924                         ins->flags |= MONO_INST_GC_CALLSITE;
4925                         ins->backend.pc_offset = code - cfg->native_code;
4926                         break;
4927                 }
4928                 case OP_CALL_HANDLER:
4929                         /* Align stack */
4930                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4931                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4932                         amd64_call_imm (code, 0);
4933                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4934                         /* Restore stack alignment */
4935                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4936                         break;
4937                 case OP_START_HANDLER: {
4938                         /* Even though we're saving RSP, use sizeof */
4939                         /* gpointer because spvar is of type IntPtr */
4940                         /* see: mono_create_spvar_for_region */
4941                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4942                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4943
4944                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4945                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4946                                 cfg->param_area) {
4947                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4948                         }
4949                         break;
4950                 }
4951                 case OP_ENDFINALLY: {
4952                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4953                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4954                         amd64_ret (code);
4955                         break;
4956                 }
4957                 case OP_ENDFILTER: {
4958                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4959                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4960                         /* The local allocator will put the result into RAX */
4961                         amd64_ret (code);
4962                         break;
4963                 }
4964                 case OP_GET_EX_OBJ:
4965                         if (ins->dreg != AMD64_RAX)
4966                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4967                         break;
4968                 case OP_LABEL:
4969                         ins->inst_c0 = code - cfg->native_code;
4970                         break;
4971                 case OP_BR:
4972                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4973                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4974                         //break;
4975                                 if (ins->inst_target_bb->native_offset) {
4976                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4977                                 } else {
4978                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4979                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4980                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4981                                                 x86_jump8 (code, 0);
4982                                         else
4983                                                 x86_jump32 (code, 0);
4984                         }
4985                         break;
4986                 case OP_BR_REG:
4987                         amd64_jump_reg (code, ins->sreg1);
4988                         break;
4989                 case OP_ICNEQ:
4990                 case OP_ICGE:
4991                 case OP_ICLE:
4992                 case OP_ICGE_UN:
4993                 case OP_ICLE_UN:
4994
4995                 case OP_CEQ:
4996                 case OP_LCEQ:
4997                 case OP_ICEQ:
4998                 case OP_CLT:
4999                 case OP_LCLT:
5000                 case OP_ICLT:
5001                 case OP_CGT:
5002                 case OP_ICGT:
5003                 case OP_LCGT:
5004                 case OP_CLT_UN:
5005                 case OP_LCLT_UN:
5006                 case OP_ICLT_UN:
5007                 case OP_CGT_UN:
5008                 case OP_LCGT_UN:
5009                 case OP_ICGT_UN:
5010                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5011                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5012                         break;
5013                 case OP_COND_EXC_EQ:
5014                 case OP_COND_EXC_NE_UN:
5015                 case OP_COND_EXC_LT:
5016                 case OP_COND_EXC_LT_UN:
5017                 case OP_COND_EXC_GT:
5018                 case OP_COND_EXC_GT_UN:
5019                 case OP_COND_EXC_GE:
5020                 case OP_COND_EXC_GE_UN:
5021                 case OP_COND_EXC_LE:
5022                 case OP_COND_EXC_LE_UN:
5023                 case OP_COND_EXC_IEQ:
5024                 case OP_COND_EXC_INE_UN:
5025                 case OP_COND_EXC_ILT:
5026                 case OP_COND_EXC_ILT_UN:
5027                 case OP_COND_EXC_IGT:
5028                 case OP_COND_EXC_IGT_UN:
5029                 case OP_COND_EXC_IGE:
5030                 case OP_COND_EXC_IGE_UN:
5031                 case OP_COND_EXC_ILE:
5032                 case OP_COND_EXC_ILE_UN:
5033                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5034                         break;
5035                 case OP_COND_EXC_OV:
5036                 case OP_COND_EXC_NO:
5037                 case OP_COND_EXC_C:
5038                 case OP_COND_EXC_NC:
5039                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5040                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5041                         break;
5042                 case OP_COND_EXC_IOV:
5043                 case OP_COND_EXC_INO:
5044                 case OP_COND_EXC_IC:
5045                 case OP_COND_EXC_INC:
5046                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5047                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5048                         break;
5049
5050                 /* floating point opcodes */
5051                 case OP_R8CONST: {
5052                         double d = *(double *)ins->inst_p0;
5053
5054                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5055                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5056                         }
5057                         else {
5058                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5059                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5060                         }
5061                         break;
5062                 }
5063                 case OP_R4CONST: {
5064                         float f = *(float *)ins->inst_p0;
5065
5066                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5067                                 if (cfg->r4fp)
5068                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5069                                 else
5070                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5071                         }
5072                         else {
5073                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5074                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5075                                 if (!cfg->r4fp)
5076                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5077                         }
5078                         break;
5079                 }
5080                 case OP_STORER8_MEMBASE_REG:
5081                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5082                         break;
5083                 case OP_LOADR8_MEMBASE:
5084                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5085                         break;
5086                 case OP_STORER4_MEMBASE_REG:
5087                         if (cfg->r4fp) {
5088                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5089                         } else {
5090                                 /* This requires a double->single conversion */
5091                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5092                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5093                         }
5094                         break;
5095                 case OP_LOADR4_MEMBASE:
5096                         if (cfg->r4fp) {
5097                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5098                         } else {
5099                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5100                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5101                         }
5102                         break;
5103                 case OP_ICONV_TO_R4:
5104                         if (cfg->r4fp) {
5105                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5106                         } else {
5107                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5108                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5109                         }
5110                         break;
5111                 case OP_ICONV_TO_R8:
5112                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5113                         break;
5114                 case OP_LCONV_TO_R4:
5115                         if (cfg->r4fp) {
5116                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5117                         } else {
5118                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5119                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5120                         }
5121                         break;
5122                 case OP_LCONV_TO_R8:
5123                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5124                         break;
5125                 case OP_FCONV_TO_R4:
5126                         if (cfg->r4fp) {
5127                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5128                         } else {
5129                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5130                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5131                         }
5132                         break;
5133                 case OP_FCONV_TO_I1:
5134                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5135                         break;
5136                 case OP_FCONV_TO_U1:
5137                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5138                         break;
5139                 case OP_FCONV_TO_I2:
5140                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5141                         break;
5142                 case OP_FCONV_TO_U2:
5143                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5144                         break;
5145                 case OP_FCONV_TO_U4:
5146                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5147                         break;
5148                 case OP_FCONV_TO_I4:
5149                 case OP_FCONV_TO_I:
5150                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5151                         break;
5152                 case OP_FCONV_TO_I8:
5153                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5154                         break;
5155
5156                 case OP_RCONV_TO_I1:
5157                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5158                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5159                         break;
5160                 case OP_RCONV_TO_U1:
5161                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5162                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5163                         break;
5164                 case OP_RCONV_TO_I2:
5165                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5166                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5167                         break;
5168                 case OP_RCONV_TO_U2:
5169                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5170                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5171                         break;
5172                 case OP_RCONV_TO_I4:
5173                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5174                         break;
5175                 case OP_RCONV_TO_U4:
5176                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5177                         break;
5178                 case OP_RCONV_TO_I8:
5179                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5180                         break;
5181                 case OP_RCONV_TO_R8:
5182                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5183                         break;
5184                 case OP_RCONV_TO_R4:
5185                         if (ins->dreg != ins->sreg1)
5186                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5187                         break;
5188
5189                 case OP_LCONV_TO_R_UN: {
5190                         guint8 *br [2];
5191
5192                         /* Based on gcc code */
5193                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5194                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5195
5196                         /* Positive case */
5197                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5198                         br [1] = code; x86_jump8 (code, 0);
5199                         amd64_patch (br [0], code);
5200
5201                         /* Negative case */
5202                         /* Save to the red zone */
5203                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5204                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5205                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5206                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5207                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5208                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5209                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5210                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5211                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5212                         /* Restore */
5213                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5214                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5215                         amd64_patch (br [1], code);
5216                         break;
5217                 }
5218                 case OP_LCONV_TO_OVF_U4:
5219                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5220                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5221                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5222                         break;
5223                 case OP_LCONV_TO_OVF_I4_UN:
5224                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5225                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5226                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5227                         break;
5228                 case OP_FMOVE:
5229                         if (ins->dreg != ins->sreg1)
5230                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5231                         break;
5232                 case OP_RMOVE:
5233                         if (ins->dreg != ins->sreg1)
5234                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5235                         break;
5236                 case OP_MOVE_F_TO_I4:
5237                         if (cfg->r4fp) {
5238                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5239                         } else {
5240                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5241                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5242                         }
5243                         break;
5244                 case OP_MOVE_I4_TO_F:
5245                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5246                         if (!cfg->r4fp)
5247                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5248                         break;
5249                 case OP_MOVE_F_TO_I8:
5250                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5251                         break;
5252                 case OP_MOVE_I8_TO_F:
5253                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5254                         break;
5255                 case OP_FADD:
5256                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5257                         break;
5258                 case OP_FSUB:
5259                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5260                         break;
5261                 case OP_FMUL:
5262                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5263                         break;
5264                 case OP_FDIV:
5265                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5266                         break;
5267                 case OP_FNEG: {
5268                         static double r8_0 = -0.0;
5269
5270                         g_assert (ins->sreg1 == ins->dreg);
5271
5272                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5273                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5274                         break;
5275                 }
5276                 case OP_SIN:
5277                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5278                         break;
5279                 case OP_COS:
5280                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5281                         break;
5282                 case OP_ABS: {
5283                         static guint64 d = 0x7fffffffffffffffUL;
5284
5285                         g_assert (ins->sreg1 == ins->dreg);
5286
5287                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5288                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5289                         break;
5290                 }
5291                 case OP_SQRT:
5292                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5293                         break;
5294
5295                 case OP_RADD:
5296                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5297                         break;
5298                 case OP_RSUB:
5299                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5300                         break;
5301                 case OP_RMUL:
5302                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5303                         break;
5304                 case OP_RDIV:
5305                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5306                         break;
5307                 case OP_RNEG: {
5308                         static float r4_0 = -0.0;
5309
5310                         g_assert (ins->sreg1 == ins->dreg);
5311
5312                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5313                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5314                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5315                         break;
5316                 }
5317
5318                 case OP_IMIN:
5319                         g_assert (cfg->opt & MONO_OPT_CMOV);
5320                         g_assert (ins->dreg == ins->sreg1);
5321                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5322                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5323                         break;
5324                 case OP_IMIN_UN:
5325                         g_assert (cfg->opt & MONO_OPT_CMOV);
5326                         g_assert (ins->dreg == ins->sreg1);
5327                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5328                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5329                         break;
5330                 case OP_IMAX:
5331                         g_assert (cfg->opt & MONO_OPT_CMOV);
5332                         g_assert (ins->dreg == ins->sreg1);
5333                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5334                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5335                         break;
5336                 case OP_IMAX_UN:
5337                         g_assert (cfg->opt & MONO_OPT_CMOV);
5338                         g_assert (ins->dreg == ins->sreg1);
5339                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5340                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5341                         break;
5342                 case OP_LMIN:
5343                         g_assert (cfg->opt & MONO_OPT_CMOV);
5344                         g_assert (ins->dreg == ins->sreg1);
5345                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5346                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5347                         break;
5348                 case OP_LMIN_UN:
5349                         g_assert (cfg->opt & MONO_OPT_CMOV);
5350                         g_assert (ins->dreg == ins->sreg1);
5351                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5352                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5353                         break;
5354                 case OP_LMAX:
5355                         g_assert (cfg->opt & MONO_OPT_CMOV);
5356                         g_assert (ins->dreg == ins->sreg1);
5357                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5358                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5359                         break;
5360                 case OP_LMAX_UN:
5361                         g_assert (cfg->opt & MONO_OPT_CMOV);
5362                         g_assert (ins->dreg == ins->sreg1);
5363                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5364                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5365                         break;
5366                 case OP_X86_FPOP:
5367                         break;
5368                 case OP_FCOMPARE:
5369                         /*
5370                          * The two arguments are swapped because the fbranch instructions
5371                          * depend on this for the non-sse case to work.
5372                          */
5373                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5374                         break;
5375                 case OP_RCOMPARE:
5376                         /*
5377                          * FIXME: Get rid of this.
5378                          * The two arguments are swapped because the fbranch instructions
5379                          * depend on this for the non-sse case to work.
5380                          */
5381                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5382                         break;
5383                 case OP_FCNEQ:
5384                 case OP_FCEQ: {
5385                         /* zeroing the register at the start results in
5386                          * shorter and faster code (we can also remove the widening op)
5387                          */
5388                         guchar *unordered_check;
5389
5390                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5391                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5392                         unordered_check = code;
5393                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5394
5395                         if (ins->opcode == OP_FCEQ) {
5396                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5397                                 amd64_patch (unordered_check, code);
5398                         } else {
5399                                 guchar *jump_to_end;
5400                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5401                                 jump_to_end = code;
5402                                 x86_jump8 (code, 0);
5403                                 amd64_patch (unordered_check, code);
5404                                 amd64_inc_reg (code, ins->dreg);
5405                                 amd64_patch (jump_to_end, code);
5406                         }
5407                         break;
5408                 }
5409                 case OP_FCLT:
5410                 case OP_FCLT_UN: {
5411                         /* zeroing the register at the start results in
5412                          * shorter and faster code (we can also remove the widening op)
5413                          */
5414                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5415                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5416                         if (ins->opcode == OP_FCLT_UN) {
5417                                 guchar *unordered_check = code;
5418                                 guchar *jump_to_end;
5419                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5420                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5421                                 jump_to_end = code;
5422                                 x86_jump8 (code, 0);
5423                                 amd64_patch (unordered_check, code);
5424                                 amd64_inc_reg (code, ins->dreg);
5425                                 amd64_patch (jump_to_end, code);
5426                         } else {
5427                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5428                         }
5429                         break;
5430                 }
5431                 case OP_FCLE: {
5432                         guchar *unordered_check;
5433                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5434                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5435                         unordered_check = code;
5436                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5437                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5438                         amd64_patch (unordered_check, code);
5439                         break;
5440                 }
5441                 case OP_FCGT:
5442                 case OP_FCGT_UN: {
5443                         /* zeroing the register at the start results in
5444                          * shorter and faster code (we can also remove the widening op)
5445                          */
5446                         guchar *unordered_check;
5447
5448                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5449                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5450                         if (ins->opcode == OP_FCGT) {
5451                                 unordered_check = code;
5452                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5453                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5454                                 amd64_patch (unordered_check, code);
5455                         } else {
5456                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5457                         }
5458                         break;
5459                 }
5460                 case OP_FCGE: {
5461                         guchar *unordered_check;
5462                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5463                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5464                         unordered_check = code;
5465                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5466                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5467                         amd64_patch (unordered_check, code);
5468                         break;
5469                 }
5470
5471                 case OP_RCEQ:
5472                 case OP_RCGT:
5473                 case OP_RCLT:
5474                 case OP_RCLT_UN:
5475                 case OP_RCGT_UN: {
5476                         int x86_cond;
5477                         gboolean unordered = FALSE;
5478
5479                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5480                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5481
5482                         switch (ins->opcode) {
5483                         case OP_RCEQ:
5484                                 x86_cond = X86_CC_EQ;
5485                                 break;
5486                         case OP_RCGT:
5487                                 x86_cond = X86_CC_LT;
5488                                 break;
5489                         case OP_RCLT:
5490                                 x86_cond = X86_CC_GT;
5491                                 break;
5492                         case OP_RCLT_UN:
5493                                 x86_cond = X86_CC_GT;
5494                                 unordered = TRUE;
5495                                 break;
5496                         case OP_RCGT_UN:
5497                                 x86_cond = X86_CC_LT;
5498                                 unordered = TRUE;
5499                                 break;
5500                         default:
5501                                 g_assert_not_reached ();
5502                                 break;
5503                         }
5504
5505                         if (unordered) {
5506                                 guchar *unordered_check;
5507                                 guchar *jump_to_end;
5508
5509                                 unordered_check = code;
5510                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5511                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5512                                 jump_to_end = code;
5513                                 x86_jump8 (code, 0);
5514                                 amd64_patch (unordered_check, code);
5515                                 amd64_inc_reg (code, ins->dreg);
5516                                 amd64_patch (jump_to_end, code);
5517                         } else {
5518                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5519                         }
5520                         break;
5521                 }
5522                 case OP_FCLT_MEMBASE:
5523                 case OP_FCGT_MEMBASE:
5524                 case OP_FCLT_UN_MEMBASE:
5525                 case OP_FCGT_UN_MEMBASE:
5526                 case OP_FCEQ_MEMBASE: {
5527                         guchar *unordered_check, *jump_to_end;
5528                         int x86_cond;
5529
5530                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5531                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5532
5533                         switch (ins->opcode) {
5534                         case OP_FCEQ_MEMBASE:
5535                                 x86_cond = X86_CC_EQ;
5536                                 break;
5537                         case OP_FCLT_MEMBASE:
5538                         case OP_FCLT_UN_MEMBASE:
5539                                 x86_cond = X86_CC_LT;
5540                                 break;
5541                         case OP_FCGT_MEMBASE:
5542                         case OP_FCGT_UN_MEMBASE:
5543                                 x86_cond = X86_CC_GT;
5544                                 break;
5545                         default:
5546                                 g_assert_not_reached ();
5547                         }
5548
5549                         unordered_check = code;
5550                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5551                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5552
5553                         switch (ins->opcode) {
5554                         case OP_FCEQ_MEMBASE:
5555                         case OP_FCLT_MEMBASE:
5556                         case OP_FCGT_MEMBASE:
5557                                 amd64_patch (unordered_check, code);
5558                                 break;
5559                         case OP_FCLT_UN_MEMBASE:
5560                         case OP_FCGT_UN_MEMBASE:
5561                                 jump_to_end = code;
5562                                 x86_jump8 (code, 0);
5563                                 amd64_patch (unordered_check, code);
5564                                 amd64_inc_reg (code, ins->dreg);
5565                                 amd64_patch (jump_to_end, code);
5566                                 break;
5567                         default:
5568                                 break;
5569                         }
5570                         break;
5571                 }
5572                 case OP_FBEQ: {
5573                         guchar *jump = code;
5574                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5575                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5576                         amd64_patch (jump, code);
5577                         break;
5578                 }
5579                 case OP_FBNE_UN:
5580                         /* Branch if C013 != 100 */
5581                         /* branch if !ZF or (PF|CF) */
5582                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5583                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5584                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5585                         break;
5586                 case OP_FBLT:
5587                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5588                         break;
5589                 case OP_FBLT_UN:
5590                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5591                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5592                         break;
5593                 case OP_FBGT:
5594                 case OP_FBGT_UN:
5595                         if (ins->opcode == OP_FBGT) {
5596                                 guchar *br1;
5597
5598                                 /* skip branch if C1=1 */
5599                                 br1 = code;
5600                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5601                                 /* branch if (C0 | C3) = 1 */
5602                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5603                                 amd64_patch (br1, code);
5604                                 break;
5605                         } else {
5606                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5607                         }
5608                         break;
5609                 case OP_FBGE: {
5610                         /* Branch if C013 == 100 or 001 */
5611                         guchar *br1;
5612
5613                         /* skip branch if C1=1 */
5614                         br1 = code;
5615                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5616                         /* branch if (C0 | C3) = 1 */
5617                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5618                         amd64_patch (br1, code);
5619                         break;
5620                 }
5621                 case OP_FBGE_UN:
5622                         /* Branch if C013 == 000 */
5623                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5624                         break;
5625                 case OP_FBLE: {
5626                         /* Branch if C013=000 or 100 */
5627                         guchar *br1;
5628
5629                         /* skip branch if C1=1 */
5630                         br1 = code;
5631                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5632                         /* branch if C0=0 */
5633                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5634                         amd64_patch (br1, code);
5635                         break;
5636                 }
5637                 case OP_FBLE_UN:
5638                         /* Branch if C013 != 001 */
5639                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5640                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5641                         break;
5642                 case OP_CKFINITE:
5643                         /* Transfer value to the fp stack */
5644                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5645                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5646                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5647
5648                         amd64_push_reg (code, AMD64_RAX);
5649                         amd64_fxam (code);
5650                         amd64_fnstsw (code);
5651                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5652                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5653                         amd64_pop_reg (code, AMD64_RAX);
5654                         amd64_fstp (code, 0);
5655                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5656                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5657                         break;
5658                 case OP_TLS_GET: {
5659                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5660                         break;
5661                 }
5662                 case OP_TLS_GET_REG:
5663                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5664                         break;
5665                 case OP_TLS_SET: {
5666                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5667                         break;
5668                 }
5669                 case OP_TLS_SET_REG: {
5670                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5671                         break;
5672                 }
5673                 case OP_MEMORY_BARRIER: {
5674                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5675                                 x86_mfence (code);
5676                         break;
5677                 }
5678                 case OP_ATOMIC_ADD_I4:
5679                 case OP_ATOMIC_ADD_I8: {
5680                         int dreg = ins->dreg;
5681                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5682
5683                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5684                                 dreg = AMD64_R11;
5685
5686                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5687                         amd64_prefix (code, X86_LOCK_PREFIX);
5688                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5689                         /* dreg contains the old value, add with sreg2 value */
5690                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5691
5692                         if (ins->dreg != dreg)
5693                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5694
5695                         break;
5696                 }
5697                 case OP_ATOMIC_EXCHANGE_I4:
5698                 case OP_ATOMIC_EXCHANGE_I8: {
5699                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5700
5701                         /* LOCK prefix is implied. */
5702                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5703                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5704                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5705                         break;
5706                 }
5707                 case OP_ATOMIC_CAS_I4:
5708                 case OP_ATOMIC_CAS_I8: {
5709                         guint32 size;
5710
5711                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5712                                 size = 8;
5713                         else
5714                                 size = 4;
5715
5716                         /*
5717                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5718                          * an explanation of how this works.
5719                          */
5720                         g_assert (ins->sreg3 == AMD64_RAX);
5721                         g_assert (ins->sreg1 != AMD64_RAX);
5722                         g_assert (ins->sreg1 != ins->sreg2);
5723
5724                         amd64_prefix (code, X86_LOCK_PREFIX);
5725                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5726
5727                         if (ins->dreg != AMD64_RAX)
5728                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5729                         break;
5730                 }
5731                 case OP_ATOMIC_LOAD_I1: {
5732                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5733                         break;
5734                 }
5735                 case OP_ATOMIC_LOAD_U1: {
5736                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5737                         break;
5738                 }
5739                 case OP_ATOMIC_LOAD_I2: {
5740                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5741                         break;
5742                 }
5743                 case OP_ATOMIC_LOAD_U2: {
5744                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5745                         break;
5746                 }
5747                 case OP_ATOMIC_LOAD_I4: {
5748                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5749                         break;
5750                 }
5751                 case OP_ATOMIC_LOAD_U4:
5752                 case OP_ATOMIC_LOAD_I8:
5753                 case OP_ATOMIC_LOAD_U8: {
5754                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5755                         break;
5756                 }
5757                 case OP_ATOMIC_LOAD_R4: {
5758                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5759                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5760                         break;
5761                 }
5762                 case OP_ATOMIC_LOAD_R8: {
5763                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5764                         break;
5765                 }
5766                 case OP_ATOMIC_STORE_I1:
5767                 case OP_ATOMIC_STORE_U1:
5768                 case OP_ATOMIC_STORE_I2:
5769                 case OP_ATOMIC_STORE_U2:
5770                 case OP_ATOMIC_STORE_I4:
5771                 case OP_ATOMIC_STORE_U4:
5772                 case OP_ATOMIC_STORE_I8:
5773                 case OP_ATOMIC_STORE_U8: {
5774                         int size;
5775
5776                         switch (ins->opcode) {
5777                         case OP_ATOMIC_STORE_I1:
5778                         case OP_ATOMIC_STORE_U1:
5779                                 size = 1;
5780                                 break;
5781                         case OP_ATOMIC_STORE_I2:
5782                         case OP_ATOMIC_STORE_U2:
5783                                 size = 2;
5784                                 break;
5785                         case OP_ATOMIC_STORE_I4:
5786                         case OP_ATOMIC_STORE_U4:
5787                                 size = 4;
5788                                 break;
5789                         case OP_ATOMIC_STORE_I8:
5790                         case OP_ATOMIC_STORE_U8:
5791                                 size = 8;
5792                                 break;
5793                         }
5794
5795                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5796
5797                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5798                                 x86_mfence (code);
5799                         break;
5800                 }
5801                 case OP_ATOMIC_STORE_R4: {
5802                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5803                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5804
5805                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5806                                 x86_mfence (code);
5807                         break;
5808                 }
5809                 case OP_ATOMIC_STORE_R8: {
5810                         x86_nop (code);
5811                         x86_nop (code);
5812                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5813                         x86_nop (code);
5814                         x86_nop (code);
5815
5816                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5817                                 x86_mfence (code);
5818                         break;
5819                 }
5820                 case OP_CARD_TABLE_WBARRIER: {
5821                         int ptr = ins->sreg1;
5822                         int value = ins->sreg2;
5823                         guchar *br = 0;
5824                         int nursery_shift, card_table_shift;
5825                         gpointer card_table_mask;
5826                         size_t nursery_size;
5827
5828                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5829                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5830                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5831
5832                         /*If either point to the stack we can simply avoid the WB. This happens due to
5833                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5834                          */
5835                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5836                                 continue;
5837
5838                         /*
5839                          * We need one register we can clobber, we choose EDX and make sreg1
5840                          * fixed EAX to work around limitations in the local register allocator.
5841                          * sreg2 might get allocated to EDX, but that is not a problem since
5842                          * we use it before clobbering EDX.
5843                          */
5844                         g_assert (ins->sreg1 == AMD64_RAX);
5845
5846                         /*
5847                          * This is the code we produce:
5848                          *
5849                          *   edx = value
5850                          *   edx >>= nursery_shift
5851                          *   cmp edx, (nursery_start >> nursery_shift)
5852                          *   jne done
5853                          *   edx = ptr
5854                          *   edx >>= card_table_shift
5855                          *   edx += cardtable
5856                          *   [edx] = 1
5857                          * done:
5858                          */
5859
5860                         if (mono_gc_card_table_nursery_check ()) {
5861                                 if (value != AMD64_RDX)
5862                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5863                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5864                                 if (shifted_nursery_start >> 31) {
5865                                         /*
5866                                          * The value we need to compare against is 64 bits, so we need
5867                                          * another spare register.  We use RBX, which we save and
5868                                          * restore.
5869                                          */
5870                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5871                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5872                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5873                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5874                                 } else {
5875                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5876                                 }
5877                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5878                         }
5879                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5880                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5881                         if (card_table_mask)
5882                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5883
5884                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5885                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5886
5887                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5888
5889                         if (mono_gc_card_table_nursery_check ())
5890                                 x86_patch (br, code);
5891                         break;
5892                 }
5893 #ifdef MONO_ARCH_SIMD_INTRINSICS
5894                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5895                 case OP_ADDPS:
5896                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5897                         break;
5898                 case OP_DIVPS:
5899                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5900                         break;
5901                 case OP_MULPS:
5902                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904                 case OP_SUBPS:
5905                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5906                         break;
5907                 case OP_MAXPS:
5908                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910                 case OP_MINPS:
5911                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5912                         break;
5913                 case OP_COMPPS:
5914                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5915                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5916                         break;
5917                 case OP_ANDPS:
5918                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_ANDNPS:
5921                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923                 case OP_ORPS:
5924                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_XORPS:
5927                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929                 case OP_SQRTPS:
5930                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5931                         break;
5932                 case OP_RSQRTPS:
5933                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5934                         break;
5935                 case OP_RCPPS:
5936                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5937                         break;
5938                 case OP_ADDSUBPS:
5939                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5940                         break;
5941                 case OP_HADDPS:
5942                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5943                         break;
5944                 case OP_HSUBPS:
5945                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5946                         break;
5947                 case OP_DUPPS_HIGH:
5948                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5949                         break;
5950                 case OP_DUPPS_LOW:
5951                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5952                         break;
5953
5954                 case OP_PSHUFLEW_HIGH:
5955                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5956                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5957                         break;
5958                 case OP_PSHUFLEW_LOW:
5959                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5960                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5961                         break;
5962                 case OP_PSHUFLED:
5963                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5964                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5965                         break;
5966                 case OP_SHUFPS:
5967                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5968                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5969                         break;
5970                 case OP_SHUFPD:
5971                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5972                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5973                         break;
5974
5975                 case OP_ADDPD:
5976                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978                 case OP_DIVPD:
5979                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981                 case OP_MULPD:
5982                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984                 case OP_SUBPD:
5985                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5986                         break;
5987                 case OP_MAXPD:
5988                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5989                         break;
5990                 case OP_MINPD:
5991                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5992                         break;
5993                 case OP_COMPPD:
5994                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5995                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5996                         break;
5997                 case OP_ANDPD:
5998                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5999                         break;
6000                 case OP_ANDNPD:
6001                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6002                         break;
6003                 case OP_ORPD:
6004                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6005                         break;
6006                 case OP_XORPD:
6007                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009                 case OP_SQRTPD:
6010                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6011                         break;
6012                 case OP_ADDSUBPD:
6013                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015                 case OP_HADDPD:
6016                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018                 case OP_HSUBPD:
6019                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021                 case OP_DUPPD:
6022                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6023                         break;
6024
6025                 case OP_EXTRACT_MASK:
6026                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6027                         break;
6028
6029                 case OP_PAND:
6030                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_POR:
6033                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_PXOR:
6036                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038
6039                 case OP_PADDB:
6040                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6041                         break;
6042                 case OP_PADDW:
6043                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6044                         break;
6045                 case OP_PADDD:
6046                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6047                         break;
6048                 case OP_PADDQ:
6049                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051
6052                 case OP_PSUBB:
6053                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6054                         break;
6055                 case OP_PSUBW:
6056                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6057                         break;
6058                 case OP_PSUBD:
6059                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6060                         break;
6061                 case OP_PSUBQ:
6062                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6063                         break;
6064
6065                 case OP_PMAXB_UN:
6066                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6067                         break;
6068                 case OP_PMAXW_UN:
6069                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6070                         break;
6071                 case OP_PMAXD_UN:
6072                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6073                         break;
6074
6075                 case OP_PMAXB:
6076                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6077                         break;
6078                 case OP_PMAXW:
6079                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6080                         break;
6081                 case OP_PMAXD:
6082                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6083                         break;
6084
6085                 case OP_PAVGB_UN:
6086                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6087                         break;
6088                 case OP_PAVGW_UN:
6089                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6090                         break;
6091
6092                 case OP_PMINB_UN:
6093                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_PMINW_UN:
6096                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098                 case OP_PMIND_UN:
6099                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6100                         break;
6101
6102                 case OP_PMINB:
6103                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_PMINW:
6106                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108                 case OP_PMIND:
6109                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6110                         break;
6111
6112                 case OP_PCMPEQB:
6113                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_PCMPEQW:
6116                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118                 case OP_PCMPEQD:
6119                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121                 case OP_PCMPEQQ:
6122                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6123                         break;
6124
6125                 case OP_PCMPGTB:
6126                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6127                         break;
6128                 case OP_PCMPGTW:
6129                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131                 case OP_PCMPGTD:
6132                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6133                         break;
6134                 case OP_PCMPGTQ:
6135                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6136                         break;
6137
6138                 case OP_PSUM_ABS_DIFF:
6139                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6140                         break;
6141
6142                 case OP_UNPACK_LOWB:
6143                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6144                         break;
6145                 case OP_UNPACK_LOWW:
6146                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148                 case OP_UNPACK_LOWD:
6149                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6150                         break;
6151                 case OP_UNPACK_LOWQ:
6152                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6153                         break;
6154                 case OP_UNPACK_LOWPS:
6155                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6156                         break;
6157                 case OP_UNPACK_LOWPD:
6158                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6159                         break;
6160
6161                 case OP_UNPACK_HIGHB:
6162                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6163                         break;
6164                 case OP_UNPACK_HIGHW:
6165                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6166                         break;
6167                 case OP_UNPACK_HIGHD:
6168                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6169                         break;
6170                 case OP_UNPACK_HIGHQ:
6171                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6172                         break;
6173                 case OP_UNPACK_HIGHPS:
6174                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6175                         break;
6176                 case OP_UNPACK_HIGHPD:
6177                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6178                         break;
6179
6180                 case OP_PACKW:
6181                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6182                         break;
6183                 case OP_PACKD:
6184                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6185                         break;
6186                 case OP_PACKW_UN:
6187                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6188                         break;
6189                 case OP_PACKD_UN:
6190                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6191                         break;
6192
6193                 case OP_PADDB_SAT_UN:
6194                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6195                         break;
6196                 case OP_PSUBB_SAT_UN:
6197                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6198                         break;
6199                 case OP_PADDW_SAT_UN:
6200                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6201                         break;
6202                 case OP_PSUBW_SAT_UN:
6203                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6204                         break;
6205
6206                 case OP_PADDB_SAT:
6207                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6208                         break;
6209                 case OP_PSUBB_SAT:
6210                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6211                         break;
6212                 case OP_PADDW_SAT:
6213                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6214                         break;
6215                 case OP_PSUBW_SAT:
6216                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6217                         break;
6218
6219                 case OP_PMULW:
6220                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6221                         break;
6222                 case OP_PMULD:
6223                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6224                         break;
6225                 case OP_PMULQ:
6226                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6227                         break;
6228                 case OP_PMULW_HIGH_UN:
6229                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6230                         break;
6231                 case OP_PMULW_HIGH:
6232                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6233                         break;
6234
6235                 case OP_PSHRW:
6236                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6237                         break;
6238                 case OP_PSHRW_REG:
6239                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6240                         break;
6241
6242                 case OP_PSARW:
6243                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6244                         break;
6245                 case OP_PSARW_REG:
6246                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6247                         break;
6248
6249                 case OP_PSHLW:
6250                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6251                         break;
6252                 case OP_PSHLW_REG:
6253                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6254                         break;
6255
6256                 case OP_PSHRD:
6257                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6258                         break;
6259                 case OP_PSHRD_REG:
6260                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6261                         break;
6262
6263                 case OP_PSARD:
6264                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6265                         break;
6266                 case OP_PSARD_REG:
6267                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6268                         break;
6269
6270                 case OP_PSHLD:
6271                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6272                         break;
6273                 case OP_PSHLD_REG:
6274                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6275                         break;
6276
6277                 case OP_PSHRQ:
6278                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6279                         break;
6280                 case OP_PSHRQ_REG:
6281                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6282                         break;
6283
6284                 /*TODO: This is appart of the sse spec but not added
6285                 case OP_PSARQ:
6286                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6287                         break;
6288                 case OP_PSARQ_REG:
6289                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6290                         break;
6291                 */
6292
6293                 case OP_PSHLQ:
6294                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6295                         break;
6296                 case OP_PSHLQ_REG:
6297                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6298                         break;
6299                 case OP_CVTDQ2PD:
6300                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6301                         break;
6302                 case OP_CVTDQ2PS:
6303                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6304                         break;
6305                 case OP_CVTPD2DQ:
6306                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6307                         break;
6308                 case OP_CVTPD2PS:
6309                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6310                         break;
6311                 case OP_CVTPS2DQ:
6312                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6313                         break;
6314                 case OP_CVTPS2PD:
6315                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6316                         break;
6317                 case OP_CVTTPD2DQ:
6318                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6319                         break;
6320                 case OP_CVTTPS2DQ:
6321                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6322                         break;
6323
6324                 case OP_ICONV_TO_X:
6325                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6326                         break;
6327                 case OP_EXTRACT_I4:
6328                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6329                         break;
6330                 case OP_EXTRACT_I8:
6331                         if (ins->inst_c0) {
6332                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6333                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6334                         } else {
6335                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6336                         }
6337                         break;
6338                 case OP_EXTRACT_I1:
6339                 case OP_EXTRACT_U1:
6340                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6341                         if (ins->inst_c0)
6342                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6343                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6344                         break;
6345                 case OP_EXTRACT_I2:
6346                 case OP_EXTRACT_U2:
6347                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6348                         if (ins->inst_c0)
6349                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6350                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6351                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6352                         break;
6353                 case OP_EXTRACT_R8:
6354                         if (ins->inst_c0)
6355                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6356                         else
6357                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6358                         break;
6359                 case OP_INSERT_I2:
6360                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6361                         break;
6362                 case OP_EXTRACTX_U2:
6363                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6364                         break;
6365                 case OP_INSERTX_U1_SLOW:
6366                         /*sreg1 is the extracted ireg (scratch)
6367                         /sreg2 is the to be inserted ireg (scratch)
6368                         /dreg is the xreg to receive the value*/
6369
6370                         /*clear the bits from the extracted word*/
6371                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6372                         /*shift the value to insert if needed*/
6373                         if (ins->inst_c0 & 1)
6374                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6375                         /*join them together*/
6376                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6377                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6378                         break;
6379                 case OP_INSERTX_I4_SLOW:
6380                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6381                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6382                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6383                         break;
6384                 case OP_INSERTX_I8_SLOW:
6385                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6386                         if (ins->inst_c0)
6387                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6388                         else
6389                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6390                         break;
6391
6392                 case OP_INSERTX_R4_SLOW:
6393                         switch (ins->inst_c0) {
6394                         case 0:
6395                                 if (cfg->r4fp)
6396                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6397                                 else
6398                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6399                                 break;
6400                         case 1:
6401                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6402                                 if (cfg->r4fp)
6403                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6404                                 else
6405                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6406                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6407                                 break;
6408                         case 2:
6409                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6410                                 if (cfg->r4fp)
6411                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6412                                 else
6413                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6414                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6415                                 break;
6416                         case 3:
6417                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6418                                 if (cfg->r4fp)
6419                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6420                                 else
6421                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6422                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6423                                 break;
6424                         }
6425                         break;
6426                 case OP_INSERTX_R8_SLOW:
6427                         if (ins->inst_c0)
6428                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6429                         else
6430                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6431                         break;
6432                 case OP_STOREX_MEMBASE_REG:
6433                 case OP_STOREX_MEMBASE:
6434                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6435                         break;
6436                 case OP_LOADX_MEMBASE:
6437                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6438                         break;
6439                 case OP_LOADX_ALIGNED_MEMBASE:
6440                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6441                         break;
6442                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6443                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6444                         break;
6445                 case OP_STOREX_NTA_MEMBASE_REG:
6446                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6447                         break;
6448                 case OP_PREFETCH_MEMBASE:
6449                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6450                         break;
6451
6452                 case OP_XMOVE:
6453                         /*FIXME the peephole pass should have killed this*/
6454                         if (ins->dreg != ins->sreg1)
6455                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6456                         break;
6457                 case OP_XZERO:
6458                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6459                         break;
6460                 case OP_ICONV_TO_R4_RAW:
6461                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6462                         break;
6463
6464                 case OP_FCONV_TO_R8_X:
6465                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6466                         break;
6467
6468                 case OP_XCONV_R8_TO_I4:
6469                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6470                         switch (ins->backend.source_opcode) {
6471                         case OP_FCONV_TO_I1:
6472                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6473                                 break;
6474                         case OP_FCONV_TO_U1:
6475                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6476                                 break;
6477                         case OP_FCONV_TO_I2:
6478                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6479                                 break;
6480                         case OP_FCONV_TO_U2:
6481                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6482                                 break;
6483                         }
6484                         break;
6485
6486                 case OP_EXPAND_I2:
6487                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6488                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6489                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6490                         break;
6491                 case OP_EXPAND_I4:
6492                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6493                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6494                         break;
6495                 case OP_EXPAND_I8:
6496                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6497                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6498                         break;
6499                 case OP_EXPAND_R4:
6500                         if (cfg->r4fp) {
6501                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6502                         } else {
6503                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6504                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6505                         }
6506                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6507                         break;
6508                 case OP_EXPAND_R8:
6509                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6510                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6511                         break;
6512 #endif
6513                 case OP_LIVERANGE_START: {
6514                         if (cfg->verbose_level > 1)
6515                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6516                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6517                         break;
6518                 }
6519                 case OP_LIVERANGE_END: {
6520                         if (cfg->verbose_level > 1)
6521                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6522                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6523                         break;
6524                 }
6525                 case OP_GC_SAFE_POINT: {
6526                         const char *polling_func = NULL;
6527                         int compare_val = 0;
6528                         guint8 *br [1];
6529
6530 #if defined (USE_COOP_GC)
6531                         polling_func = "mono_threads_state_poll";
6532                         compare_val = 1;
6533 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6534                         polling_func = "mono_nacl_gc";
6535                         compare_val = 0xFFFFFFFF;
6536 #endif
6537                         if (!polling_func)
6538                                 break;
6539
6540                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6541                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6542                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6543                         amd64_patch (br[0], code);
6544                         break;
6545                 }
6546
6547                 case OP_GC_LIVENESS_DEF:
6548                 case OP_GC_LIVENESS_USE:
6549                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6550                         ins->backend.pc_offset = code - cfg->native_code;
6551                         break;
6552                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6553                         ins->backend.pc_offset = code - cfg->native_code;
6554                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6555                         break;
6556                 default:
6557                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6558                         g_assert_not_reached ();
6559                 }
6560
6561                 if ((code - cfg->native_code - offset) > max_len) {
6562 #if !defined(__native_client_codegen__)
6563                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6564                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6565                         g_assert_not_reached ();
6566 #endif
6567                 }
6568         }
6569
6570         cfg->code_len = code - cfg->native_code;
6571 }
6572
6573 #endif /* DISABLE_JIT */
6574
6575 void
6576 mono_arch_register_lowlevel_calls (void)
6577 {
6578         /* The signature doesn't matter */
6579         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6580 }
6581
6582 void
6583 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6584 {
6585         unsigned char *ip = ji->ip.i + code;
6586
6587         /*
6588          * Debug code to help track down problems where the target of a near call is
6589          * is not valid.
6590          */
6591         if (amd64_is_near_call (ip)) {
6592                 gint64 disp = (guint8*)target - (guint8*)ip;
6593
6594                 if (!amd64_is_imm32 (disp)) {
6595                         printf ("TYPE: %d\n", ji->type);
6596                         switch (ji->type) {
6597                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6598                                 printf ("V: %s\n", ji->data.name);
6599                                 break;
6600                         case MONO_PATCH_INFO_METHOD_JUMP:
6601                         case MONO_PATCH_INFO_METHOD:
6602                                 printf ("V: %s\n", ji->data.method->name);
6603                                 break;
6604                         default:
6605                                 break;
6606                         }
6607                 }
6608         }
6609
6610         amd64_patch (ip, (gpointer)target);
6611 }
6612
6613 #ifndef DISABLE_JIT
6614
6615 static int
6616 get_max_epilog_size (MonoCompile *cfg)
6617 {
6618         int max_epilog_size = 16;
6619
6620         if (cfg->method->save_lmf)
6621                 max_epilog_size += 256;
6622
6623         if (mono_jit_trace_calls != NULL)
6624                 max_epilog_size += 50;
6625
6626         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6627                 max_epilog_size += 50;
6628
6629         max_epilog_size += (AMD64_NREG * 2);
6630
6631         return max_epilog_size;
6632 }
6633
6634 /*
6635  * This macro is used for testing whenever the unwinder works correctly at every point
6636  * where an async exception can happen.
6637  */
6638 /* This will generate a SIGSEGV at the given point in the code */
6639 #define async_exc_point(code) do { \
6640     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6641          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6642              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6643          cfg->arch.async_point_count ++; \
6644     } \
6645 } while (0)
6646
6647 guint8 *
6648 mono_arch_emit_prolog (MonoCompile *cfg)
6649 {
6650         MonoMethod *method = cfg->method;
6651         MonoBasicBlock *bb;
6652         MonoMethodSignature *sig;
6653         MonoInst *ins;
6654         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6655         guint8 *code;
6656         CallInfo *cinfo;
6657         MonoInst *lmf_var = cfg->lmf_var;
6658         gboolean args_clobbered = FALSE;
6659         gboolean trace = FALSE;
6660 #ifdef __native_client_codegen__
6661         guint alignment_check;
6662 #endif
6663
6664         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6665
6666 #if defined(__default_codegen__)
6667         code = cfg->native_code = g_malloc (cfg->code_size);
6668 #elif defined(__native_client_codegen__)
6669         /* native_code_alloc is not 32-byte aligned, native_code is. */
6670         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6671
6672         /* Align native_code to next nearest kNaclAlignment byte. */
6673         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6674         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6675
6676         code = cfg->native_code;
6677
6678         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6679         g_assert (alignment_check == 0);
6680 #endif
6681
6682         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6683                 trace = TRUE;
6684
6685         /* Amount of stack space allocated by register saving code */
6686         pos = 0;
6687
6688         /* Offset between RSP and the CFA */
6689         cfa_offset = 0;
6690
6691         /*
6692          * The prolog consists of the following parts:
6693          * FP present:
6694          * - push rbp, mov rbp, rsp
6695          * - save callee saved regs using pushes
6696          * - allocate frame
6697          * - save rgctx if needed
6698          * - save lmf if needed
6699          * FP not present:
6700          * - allocate frame
6701          * - save rgctx if needed
6702          * - save lmf if needed
6703          * - save callee saved regs using moves
6704          */
6705
6706         // CFA = sp + 8
6707         cfa_offset = 8;
6708         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6709         // IP saved at CFA - 8
6710         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6711         async_exc_point (code);
6712         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6713
6714         if (!cfg->arch.omit_fp) {
6715                 amd64_push_reg (code, AMD64_RBP);
6716                 cfa_offset += 8;
6717                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6718                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6719                 async_exc_point (code);
6720 #ifdef TARGET_WIN32
6721                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6722 #endif
6723                 /* These are handled automatically by the stack marking code */
6724                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6725
6726                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6727                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6728                 async_exc_point (code);
6729 #ifdef TARGET_WIN32
6730                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6731 #endif
6732         }
6733
6734         /* The param area is always at offset 0 from sp */
6735         /* This needs to be allocated here, since it has to come after the spill area */
6736         if (cfg->param_area) {
6737                 if (cfg->arch.omit_fp)
6738                         // FIXME:
6739                         g_assert_not_reached ();
6740                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6741         }
6742
6743         if (cfg->arch.omit_fp) {
6744                 /*
6745                  * On enter, the stack is misaligned by the pushing of the return
6746                  * address. It is either made aligned by the pushing of %rbp, or by
6747                  * this.
6748                  */
6749                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6750                 if ((alloc_size % 16) == 0) {
6751                         alloc_size += 8;
6752                         /* Mark the padding slot as NOREF */
6753                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6754                 }
6755         } else {
6756                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6757                 if (cfg->stack_offset != alloc_size) {
6758                         /* Mark the padding slot as NOREF */
6759                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6760                 }
6761                 cfg->arch.sp_fp_offset = alloc_size;
6762                 alloc_size -= pos;
6763         }
6764
6765         cfg->arch.stack_alloc_size = alloc_size;
6766
6767         /* Allocate stack frame */
6768         if (alloc_size) {
6769                 /* See mono_emit_stack_alloc */
6770 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6771                 guint32 remaining_size = alloc_size;
6772                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6773                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6774                 guint32 offset = code - cfg->native_code;
6775                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6776                         while (required_code_size >= (cfg->code_size - offset))
6777                                 cfg->code_size *= 2;
6778                         cfg->native_code = mono_realloc_native_code (cfg);
6779                         code = cfg->native_code + offset;
6780                         cfg->stat_code_reallocs++;
6781                 }
6782
6783                 while (remaining_size >= 0x1000) {
6784                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6785                         if (cfg->arch.omit_fp) {
6786                                 cfa_offset += 0x1000;
6787                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6788                         }
6789                         async_exc_point (code);
6790 #ifdef TARGET_WIN32
6791                         if (cfg->arch.omit_fp)
6792                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6793 #endif
6794
6795                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6796                         remaining_size -= 0x1000;
6797                 }
6798                 if (remaining_size) {
6799                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6800                         if (cfg->arch.omit_fp) {
6801                                 cfa_offset += remaining_size;
6802                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6803                                 async_exc_point (code);
6804                         }
6805 #ifdef TARGET_WIN32
6806                         if (cfg->arch.omit_fp)
6807                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6808 #endif
6809                 }
6810 #else
6811                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6812                 if (cfg->arch.omit_fp) {
6813                         cfa_offset += alloc_size;
6814                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6815                         async_exc_point (code);
6816                 }
6817 #endif
6818         }
6819
6820         /* Stack alignment check */
6821 #if 0
6822         {
6823                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6824                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6825                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6826                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6827                 amd64_breakpoint (code);
6828         }
6829 #endif
6830
6831         if (mini_get_debug_options ()->init_stacks) {
6832                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6833
6834                 /* Save registers to the red zone */
6835                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6836                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6837
6838                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6839                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6840                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6841
6842                 amd64_cld (code);
6843 #if defined(__default_codegen__)
6844                 amd64_prefix (code, X86_REP_PREFIX);
6845                 amd64_stosl (code);
6846 #elif defined(__native_client_codegen__)
6847                 /* NaCl stos pseudo-instruction */
6848                 amd64_codegen_pre (code);
6849                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6850                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6851                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6852                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6853                 amd64_prefix (code, X86_REP_PREFIX);
6854                 amd64_stosl (code);
6855                 amd64_codegen_post (code);
6856 #endif /* __native_client_codegen__ */
6857
6858                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6859                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6860         }
6861
6862         /* Save LMF */
6863         if (method->save_lmf)
6864                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6865
6866         /* Save callee saved registers */
6867         if (cfg->arch.omit_fp) {
6868                 save_area_offset = cfg->arch.reg_save_area_offset;
6869                 /* Save caller saved registers after sp is adjusted */
6870                 /* The registers are saved at the bottom of the frame */
6871                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6872         } else {
6873                 /* The registers are saved just below the saved rbp */
6874                 save_area_offset = cfg->arch.reg_save_area_offset;
6875         }
6876
6877         for (i = 0; i < AMD64_NREG; ++i) {
6878                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6879                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6880
6881                         if (cfg->arch.omit_fp) {
6882                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6883                                 /* These are handled automatically by the stack marking code */
6884                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6885                         } else {
6886                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6887                                 // FIXME: GC
6888                         }
6889
6890                         save_area_offset += 8;
6891                         async_exc_point (code);
6892                 }
6893         }
6894
6895         /* store runtime generic context */
6896         if (cfg->rgctx_var) {
6897                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6898                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6899
6900                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6901
6902                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6903                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6904         }
6905
6906         /* compute max_length in order to use short forward jumps */
6907         max_epilog_size = get_max_epilog_size (cfg);
6908         if (cfg->opt & MONO_OPT_BRANCH) {
6909                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6910                         MonoInst *ins;
6911                         int max_length = 0;
6912
6913                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6914                                 max_length += 6;
6915                         /* max alignment for loops */
6916                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6917                                 max_length += LOOP_ALIGNMENT;
6918 #ifdef __native_client_codegen__
6919                         /* max alignment for native client */
6920                         max_length += kNaClAlignment;
6921 #endif
6922
6923                         MONO_BB_FOR_EACH_INS (bb, ins) {
6924 #ifdef __native_client_codegen__
6925                                 {
6926                                         int space_in_block = kNaClAlignment -
6927                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6928                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6929                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6930                                                 max_length += space_in_block;
6931                                         }
6932                                 }
6933 #endif  /*__native_client_codegen__*/
6934                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6935                         }
6936
6937                         /* Take prolog and epilog instrumentation into account */
6938                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6939                                 max_length += max_epilog_size;
6940
6941                         bb->max_length = max_length;
6942                 }
6943         }
6944
6945         sig = mono_method_signature (method);
6946         pos = 0;
6947
6948         cinfo = cfg->arch.cinfo;
6949
6950         if (sig->ret->type != MONO_TYPE_VOID) {
6951                 /* Save volatile arguments to the stack */
6952                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6953                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6954         }
6955
6956         /* Keep this in sync with emit_load_volatile_arguments */
6957         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6958                 ArgInfo *ainfo = cinfo->args + i;
6959
6960                 ins = cfg->args [i];
6961
6962                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6963                         /* Unused arguments */
6964                         continue;
6965
6966                 /* Save volatile arguments to the stack */
6967                 if (ins->opcode != OP_REGVAR) {
6968                         switch (ainfo->storage) {
6969                         case ArgInIReg: {
6970                                 guint32 size = 8;
6971
6972                                 /* FIXME: I1 etc */
6973                                 /*
6974                                 if (stack_offset & 0x1)
6975                                         size = 1;
6976                                 else if (stack_offset & 0x2)
6977                                         size = 2;
6978                                 else if (stack_offset & 0x4)
6979                                         size = 4;
6980                                 else
6981                                         size = 8;
6982                                 */
6983                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6984
6985                                 /*
6986                                  * Save the original location of 'this',
6987                                  * get_generic_info_from_stack_frame () needs this to properly look up
6988                                  * the argument value during the handling of async exceptions.
6989                                  */
6990                                 if (ins == cfg->args [0]) {
6991                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6992                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6993                                 }
6994                                 break;
6995                         }
6996                         case ArgInFloatSSEReg:
6997                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6998                                 break;
6999                         case ArgInDoubleSSEReg:
7000                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7001                                 break;
7002                         case ArgValuetypeInReg:
7003                                 for (quad = 0; quad < 2; quad ++) {
7004                                         switch (ainfo->pair_storage [quad]) {
7005                                         case ArgInIReg:
7006                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7007                                                 break;
7008                                         case ArgInFloatSSEReg:
7009                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7010                                                 break;
7011                                         case ArgInDoubleSSEReg:
7012                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7013                                                 break;
7014                                         case ArgNone:
7015                                                 break;
7016                                         default:
7017                                                 g_assert_not_reached ();
7018                                         }
7019                                 }
7020                                 break;
7021                         case ArgValuetypeAddrInIReg:
7022                                 if (ainfo->pair_storage [0] == ArgInIReg)
7023                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7024                                 break;
7025                         default:
7026                                 break;
7027                         }
7028                 } else {
7029                         /* Argument allocated to (non-volatile) register */
7030                         switch (ainfo->storage) {
7031                         case ArgInIReg:
7032                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7033                                 break;
7034                         case ArgOnStack:
7035                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7036                                 break;
7037                         default:
7038                                 g_assert_not_reached ();
7039                         }
7040
7041                         if (ins == cfg->args [0]) {
7042                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7043                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7044                         }
7045                 }
7046         }
7047
7048         if (cfg->method->save_lmf)
7049                 args_clobbered = TRUE;
7050
7051         if (trace) {
7052                 args_clobbered = TRUE;
7053                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7054         }
7055
7056         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7057                 args_clobbered = TRUE;
7058
7059         /*
7060          * Optimize the common case of the first bblock making a call with the same
7061          * arguments as the method. This works because the arguments are still in their
7062          * original argument registers.
7063          * FIXME: Generalize this
7064          */
7065         if (!args_clobbered) {
7066                 MonoBasicBlock *first_bb = cfg->bb_entry;
7067                 MonoInst *next;
7068                 int filter = FILTER_IL_SEQ_POINT;
7069
7070                 next = mono_bb_first_inst (first_bb, filter);
7071                 if (!next && first_bb->next_bb) {
7072                         first_bb = first_bb->next_bb;
7073                         next = mono_bb_first_inst (first_bb, filter);
7074                 }
7075
7076                 if (first_bb->in_count > 1)
7077                         next = NULL;
7078
7079                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7080                         ArgInfo *ainfo = cinfo->args + i;
7081                         gboolean match = FALSE;
7082
7083                         ins = cfg->args [i];
7084                         if (ins->opcode != OP_REGVAR) {
7085                                 switch (ainfo->storage) {
7086                                 case ArgInIReg: {
7087                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7088                                                 if (next->dreg == ainfo->reg) {
7089                                                         NULLIFY_INS (next);
7090                                                         match = TRUE;
7091                                                 } else {
7092                                                         next->opcode = OP_MOVE;
7093                                                         next->sreg1 = ainfo->reg;
7094                                                         /* Only continue if the instruction doesn't change argument regs */
7095                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7096                                                                 match = TRUE;
7097                                                 }
7098                                         }
7099                                         break;
7100                                 }
7101                                 default:
7102                                         break;
7103                                 }
7104                         } else {
7105                                 /* Argument allocated to (non-volatile) register */
7106                                 switch (ainfo->storage) {
7107                                 case ArgInIReg:
7108                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7109                                                 NULLIFY_INS (next);
7110                                                 match = TRUE;
7111                                         }
7112                                         break;
7113                                 default:
7114                                         break;
7115                                 }
7116                         }
7117
7118                         if (match) {
7119                                 next = mono_inst_next (next, filter);
7120                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7121                                 if (!next)
7122                                         break;
7123                         }
7124                 }
7125         }
7126
7127         if (cfg->gen_sdb_seq_points) {
7128                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7129
7130                 /* Initialize seq_point_info_var */
7131                 if (cfg->compile_aot) {
7132                         /* Initialize the variable from a GOT slot */
7133                         /* Same as OP_AOTCONST */
7134                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7135                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7136                         g_assert (info_var->opcode == OP_REGOFFSET);
7137                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7138                 }
7139
7140                 if (cfg->compile_aot) {
7141                         /* Initialize ss_tramp_var */
7142                         ins = cfg->arch.ss_tramp_var;
7143                         g_assert (ins->opcode == OP_REGOFFSET);
7144
7145                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7146                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7147                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7148                 } else {
7149                         /* Initialize ss_trigger_page_var */
7150                         ins = cfg->arch.ss_trigger_page_var;
7151
7152                         g_assert (ins->opcode == OP_REGOFFSET);
7153
7154                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7155                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7156                 }
7157         }
7158
7159         cfg->code_len = code - cfg->native_code;
7160
7161         g_assert (cfg->code_len < cfg->code_size);
7162
7163         return code;
7164 }
7165
7166 void
7167 mono_arch_emit_epilog (MonoCompile *cfg)
7168 {
7169         MonoMethod *method = cfg->method;
7170         int quad, i;
7171         guint8 *code;
7172         int max_epilog_size;
7173         CallInfo *cinfo;
7174         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7175         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7176
7177         max_epilog_size = get_max_epilog_size (cfg);
7178
7179         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7180                 cfg->code_size *= 2;
7181                 cfg->native_code = mono_realloc_native_code (cfg);
7182                 cfg->stat_code_reallocs++;
7183         }
7184         code = cfg->native_code + cfg->code_len;
7185
7186         cfg->has_unwind_info_for_epilog = TRUE;
7187
7188         /* Mark the start of the epilog */
7189         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7190
7191         /* Save the uwind state which is needed by the out-of-line code */
7192         mono_emit_unwind_op_remember_state (cfg, code);
7193
7194         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7195                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7196
7197         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7198
7199         if (method->save_lmf) {
7200                 /* check if we need to restore protection of the stack after a stack overflow */
7201                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7202                         guint8 *patch;
7203                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7204                         /* we load the value in a separate instruction: this mechanism may be
7205                          * used later as a safer way to do thread interruption
7206                          */
7207                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7208                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7209                         patch = code;
7210                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7211                         /* note that the call trampoline will preserve eax/edx */
7212                         x86_call_reg (code, X86_ECX);
7213                         x86_patch (patch, code);
7214                 } else {
7215                         /* FIXME: maybe save the jit tls in the prolog */
7216                 }
7217                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7218                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7219                 }
7220         }
7221
7222         /* Restore callee saved regs */
7223         for (i = 0; i < AMD64_NREG; ++i) {
7224                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7225                         /* Restore only used_int_regs, not arch.saved_iregs */
7226                         if (cfg->used_int_regs & (1 << i)) {
7227                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7228                                 mono_emit_unwind_op_same_value (cfg, code, i);
7229                                 async_exc_point (code);
7230                         }
7231                         save_area_offset += 8;
7232                 }
7233         }
7234
7235         /* Load returned vtypes into registers if needed */
7236         cinfo = cfg->arch.cinfo;
7237         if (cinfo->ret.storage == ArgValuetypeInReg) {
7238                 ArgInfo *ainfo = &cinfo->ret;
7239                 MonoInst *inst = cfg->ret;
7240
7241                 for (quad = 0; quad < 2; quad ++) {
7242                         switch (ainfo->pair_storage [quad]) {
7243                         case ArgInIReg:
7244                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7245                                 break;
7246                         case ArgInFloatSSEReg:
7247                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7248                                 break;
7249                         case ArgInDoubleSSEReg:
7250                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7251                                 break;
7252                         case ArgNone:
7253                                 break;
7254                         default:
7255                                 g_assert_not_reached ();
7256                         }
7257                 }
7258         }
7259
7260         if (cfg->arch.omit_fp) {
7261                 if (cfg->arch.stack_alloc_size) {
7262                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7263                 }
7264         } else {
7265                 amd64_leave (code);
7266                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7267         }
7268         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7269         async_exc_point (code);
7270         amd64_ret (code);
7271
7272         /* Restore the unwind state to be the same as before the epilog */
7273         mono_emit_unwind_op_restore_state (cfg, code);
7274
7275         cfg->code_len = code - cfg->native_code;
7276
7277         g_assert (cfg->code_len < cfg->code_size);
7278 }
7279
7280 void
7281 mono_arch_emit_exceptions (MonoCompile *cfg)
7282 {
7283         MonoJumpInfo *patch_info;
7284         int nthrows, i;
7285         guint8 *code;
7286         MonoClass *exc_classes [16];
7287         guint8 *exc_throw_start [16], *exc_throw_end [16];
7288         guint32 code_size = 0;
7289
7290         /* Compute needed space */
7291         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7292                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7293                         code_size += 40;
7294                 if (patch_info->type == MONO_PATCH_INFO_R8)
7295                         code_size += 8 + 15; /* sizeof (double) + alignment */
7296                 if (patch_info->type == MONO_PATCH_INFO_R4)
7297                         code_size += 4 + 15; /* sizeof (float) + alignment */
7298                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7299                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7300         }
7301
7302 #ifdef __native_client_codegen__
7303         /* Give us extra room on Native Client.  This could be   */
7304         /* more carefully calculated, but bundle alignment makes */
7305         /* it much trickier, so *2 like other places is good.    */
7306         code_size *= 2;
7307 #endif
7308
7309         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7310                 cfg->code_size *= 2;
7311                 cfg->native_code = mono_realloc_native_code (cfg);
7312                 cfg->stat_code_reallocs++;
7313         }
7314
7315         code = cfg->native_code + cfg->code_len;
7316
7317         /* add code to raise exceptions */
7318         nthrows = 0;
7319         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7320                 switch (patch_info->type) {
7321                 case MONO_PATCH_INFO_EXC: {
7322                         MonoClass *exc_class;
7323                         guint8 *buf, *buf2;
7324                         guint32 throw_ip;
7325
7326                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7327
7328                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7329                         g_assert (exc_class);
7330                         throw_ip = patch_info->ip.i;
7331
7332                         //x86_breakpoint (code);
7333                         /* Find a throw sequence for the same exception class */
7334                         for (i = 0; i < nthrows; ++i)
7335                                 if (exc_classes [i] == exc_class)
7336                                         break;
7337                         if (i < nthrows) {
7338                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7339                                 x86_jump_code (code, exc_throw_start [i]);
7340                                 patch_info->type = MONO_PATCH_INFO_NONE;
7341                         }
7342                         else {
7343                                 buf = code;
7344                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7345                                 buf2 = code;
7346
7347                                 if (nthrows < 16) {
7348                                         exc_classes [nthrows] = exc_class;
7349                                         exc_throw_start [nthrows] = code;
7350                                 }
7351                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7352
7353                                 patch_info->type = MONO_PATCH_INFO_NONE;
7354
7355                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7356
7357                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7358                                 while (buf < buf2)
7359                                         x86_nop (buf);
7360
7361                                 if (nthrows < 16) {
7362                                         exc_throw_end [nthrows] = code;
7363                                         nthrows ++;
7364                                 }
7365                         }
7366                         break;
7367                 }
7368                 default:
7369                         /* do nothing */
7370                         break;
7371                 }
7372                 g_assert(code < cfg->native_code + cfg->code_size);
7373         }
7374
7375         /* Handle relocations with RIP relative addressing */
7376         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7377                 gboolean remove = FALSE;
7378                 guint8 *orig_code = code;
7379
7380                 switch (patch_info->type) {
7381                 case MONO_PATCH_INFO_R8:
7382                 case MONO_PATCH_INFO_R4: {
7383                         guint8 *pos, *patch_pos;
7384                         guint32 target_pos;
7385
7386                         /* The SSE opcodes require a 16 byte alignment */
7387 #if defined(__default_codegen__)
7388                         code = (guint8*)ALIGN_TO (code, 16);
7389 #elif defined(__native_client_codegen__)
7390                         {
7391                                 /* Pad this out with HLT instructions  */
7392                                 /* or we can get garbage bytes emitted */
7393                                 /* which will fail validation          */
7394                                 guint8 *aligned_code;
7395                                 /* extra align to make room for  */
7396                                 /* mov/push below                      */
7397                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7398                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7399                                 /* The technique of hiding data in an  */
7400                                 /* instruction has a problem here: we  */
7401                                 /* need the data aligned to a 16-byte  */
7402                                 /* boundary but the instruction cannot */
7403                                 /* cross the bundle boundary. so only  */
7404                                 /* odd multiples of 16 can be used     */
7405                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7406                                         aligned_code += 16;
7407                                 }
7408                                 while (code < aligned_code) {
7409                                         *(code++) = 0xf4; /* hlt */
7410                                 }
7411                         }
7412 #endif
7413
7414                         pos = cfg->native_code + patch_info->ip.i;
7415                         if (IS_REX (pos [1])) {
7416                                 patch_pos = pos + 5;
7417                                 target_pos = code - pos - 9;
7418                         }
7419                         else {
7420                                 patch_pos = pos + 4;
7421                                 target_pos = code - pos - 8;
7422                         }
7423
7424                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7425 #ifdef __native_client_codegen__
7426                                 /* Hide 64-bit data in a         */
7427                                 /* "mov imm64, r11" instruction. */
7428                                 /* write it before the start of  */
7429                                 /* the data*/
7430                                 *(code-2) = 0x49; /* prefix      */
7431                                 *(code-1) = 0xbb; /* mov X, %r11 */
7432 #endif
7433                                 *(double*)code = *(double*)patch_info->data.target;
7434                                 code += sizeof (double);
7435                         } else {
7436 #ifdef __native_client_codegen__
7437                                 /* Hide 32-bit data in a        */
7438                                 /* "push imm32" instruction.    */
7439                                 *(code-1) = 0x68; /* push */
7440 #endif
7441                                 *(float*)code = *(float*)patch_info->data.target;
7442                                 code += sizeof (float);
7443                         }
7444
7445                         *(guint32*)(patch_pos) = target_pos;
7446
7447                         remove = TRUE;
7448                         break;
7449                 }
7450                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7451                         guint8 *pos;
7452
7453                         if (cfg->compile_aot)
7454                                 continue;
7455
7456                         /*loading is faster against aligned addresses.*/
7457                         code = (guint8*)ALIGN_TO (code, 8);
7458                         memset (orig_code, 0, code - orig_code);
7459
7460                         pos = cfg->native_code + patch_info->ip.i;
7461
7462                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7463                         if (IS_REX (pos [1]))
7464                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7465                         else
7466                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7467
7468                         *(gpointer*)code = (gpointer)patch_info->data.target;
7469                         code += sizeof (gpointer);
7470
7471                         remove = TRUE;
7472                         break;
7473                 }
7474                 default:
7475                         break;
7476                 }
7477
7478                 if (remove) {
7479                         if (patch_info == cfg->patch_info)
7480                                 cfg->patch_info = patch_info->next;
7481                         else {
7482                                 MonoJumpInfo *tmp;
7483
7484                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7485                                         ;
7486                                 tmp->next = patch_info->next;
7487                         }
7488                 }
7489                 g_assert (code < cfg->native_code + cfg->code_size);
7490         }
7491
7492         cfg->code_len = code - cfg->native_code;
7493
7494         g_assert (cfg->code_len < cfg->code_size);
7495
7496 }
7497
7498 #endif /* DISABLE_JIT */
7499
7500 void*
7501 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7502 {
7503         guchar *code = p;
7504         MonoMethodSignature *sig;
7505         MonoInst *inst;
7506         int i, n, stack_area = 0;
7507
7508         /* Keep this in sync with mono_arch_get_argument_info */
7509
7510         if (enable_arguments) {
7511                 /* Allocate a new area on the stack and save arguments there */
7512                 sig = mono_method_signature (cfg->method);
7513
7514                 n = sig->param_count + sig->hasthis;
7515
7516                 stack_area = ALIGN_TO (n * 8, 16);
7517
7518                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7519
7520                 for (i = 0; i < n; ++i) {
7521                         inst = cfg->args [i];
7522
7523                         if (inst->opcode == OP_REGVAR)
7524                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7525                         else {
7526                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7527                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7528                         }
7529                 }
7530         }
7531
7532         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7533         amd64_set_reg_template (code, AMD64_ARG_REG1);
7534         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7535         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7536
7537         if (enable_arguments)
7538                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7539
7540         return code;
7541 }
7542
7543 enum {
7544         SAVE_NONE,
7545         SAVE_STRUCT,
7546         SAVE_EAX,
7547         SAVE_EAX_EDX,
7548         SAVE_XMM
7549 };
7550
7551 void*
7552 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7553 {
7554         guchar *code = p;
7555         int save_mode = SAVE_NONE;
7556         MonoMethod *method = cfg->method;
7557         MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7558         int i;
7559
7560         switch (ret_type->type) {
7561         case MONO_TYPE_VOID:
7562                 /* special case string .ctor icall */
7563                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7564                         save_mode = SAVE_EAX;
7565                 else
7566                         save_mode = SAVE_NONE;
7567                 break;
7568         case MONO_TYPE_I8:
7569         case MONO_TYPE_U8:
7570                 save_mode = SAVE_EAX;
7571                 break;
7572         case MONO_TYPE_R4:
7573         case MONO_TYPE_R8:
7574                 save_mode = SAVE_XMM;
7575                 break;
7576         case MONO_TYPE_GENERICINST:
7577                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7578                         save_mode = SAVE_EAX;
7579                         break;
7580                 }
7581                 /* Fall through */
7582         case MONO_TYPE_VALUETYPE:
7583                 save_mode = SAVE_STRUCT;
7584                 break;
7585         default:
7586                 save_mode = SAVE_EAX;
7587                 break;
7588         }
7589
7590         /* Save the result and copy it into the proper argument register */
7591         switch (save_mode) {
7592         case SAVE_EAX:
7593                 amd64_push_reg (code, AMD64_RAX);
7594                 /* Align stack */
7595                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7596                 if (enable_arguments)
7597                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7598                 break;
7599         case SAVE_STRUCT:
7600                 /* FIXME: */
7601                 if (enable_arguments)
7602                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7603                 break;
7604         case SAVE_XMM:
7605                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7606                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7607                 /* Align stack */
7608                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7609                 /*
7610                  * The result is already in the proper argument register so no copying
7611                  * needed.
7612                  */
7613                 break;
7614         case SAVE_NONE:
7615                 break;
7616         default:
7617                 g_assert_not_reached ();
7618         }
7619
7620         /* Set %al since this is a varargs call */
7621         if (save_mode == SAVE_XMM)
7622                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7623         else
7624                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7625
7626         if (preserve_argument_registers) {
7627                 for (i = 0; i < PARAM_REGS; ++i)
7628                         amd64_push_reg (code, param_regs [i]);
7629         }
7630
7631         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7632         amd64_set_reg_template (code, AMD64_ARG_REG1);
7633         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7634
7635         if (preserve_argument_registers) {
7636                 for (i = PARAM_REGS - 1; i >= 0; --i)
7637                         amd64_pop_reg (code, param_regs [i]);
7638         }
7639
7640         /* Restore result */
7641         switch (save_mode) {
7642         case SAVE_EAX:
7643                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7644                 amd64_pop_reg (code, AMD64_RAX);
7645                 break;
7646         case SAVE_STRUCT:
7647                 /* FIXME: */
7648                 break;
7649         case SAVE_XMM:
7650                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7651                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7652                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7653                 break;
7654         case SAVE_NONE:
7655                 break;
7656         default:
7657                 g_assert_not_reached ();
7658         }
7659
7660         return code;
7661 }
7662
7663 void
7664 mono_arch_flush_icache (guint8 *code, gint size)
7665 {
7666         /* Not needed */
7667 }
7668
7669 void
7670 mono_arch_flush_register_windows (void)
7671 {
7672 }
7673
7674 gboolean
7675 mono_arch_is_inst_imm (gint64 imm)
7676 {
7677         return amd64_is_imm32 (imm);
7678 }
7679
7680 /*
7681  * Determine whenever the trap whose info is in SIGINFO is caused by
7682  * integer overflow.
7683  */
7684 gboolean
7685 mono_arch_is_int_overflow (void *sigctx, void *info)
7686 {
7687         MonoContext ctx;
7688         guint8* rip;
7689         int reg;
7690         gint64 value;
7691
7692         mono_sigctx_to_monoctx (sigctx, &ctx);
7693
7694         rip = (guint8*)ctx.gregs [AMD64_RIP];
7695
7696         if (IS_REX (rip [0])) {
7697                 reg = amd64_rex_b (rip [0]);
7698                 rip ++;
7699         }
7700         else
7701                 reg = 0;
7702
7703         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7704                 /* idiv REG */
7705                 reg += x86_modrm_rm (rip [1]);
7706
7707                 value = ctx.gregs [reg];
7708
7709                 if (value == -1)
7710                         return TRUE;
7711         }
7712
7713         return FALSE;
7714 }
7715
7716 guint32
7717 mono_arch_get_patch_offset (guint8 *code)
7718 {
7719         return 3;
7720 }
7721
7722 /**
7723  * mono_breakpoint_clean_code:
7724  *
7725  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7726  * breakpoints in the original code, they are removed in the copy.
7727  *
7728  * Returns TRUE if no sw breakpoint was present.
7729  */
7730 gboolean
7731 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7732 {
7733         /*
7734          * If method_start is non-NULL we need to perform bound checks, since we access memory
7735          * at code - offset we could go before the start of the method and end up in a different
7736          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7737          * instead.
7738          */
7739         if (!method_start || code - offset >= method_start) {
7740                 memcpy (buf, code - offset, size);
7741         } else {
7742                 int diff = code - method_start;
7743                 memset (buf, 0, size);
7744                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7745         }
7746         return TRUE;
7747 }
7748
7749 #if defined(__native_client_codegen__)
7750 /* For membase calls, we want the base register. for Native Client,  */
7751 /* all indirect calls have the following sequence with the given sizes: */
7752 /* mov %eXX,%eXX                                [2-3]   */
7753 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7754 /* and $0xffffffffffffffe0,%r11d                [4]     */
7755 /* add %r15,%r11                                [3]     */
7756 /* callq *%r11                                  [3]     */
7757
7758
7759 /* Determine if code points to a NaCl call-through-register sequence, */
7760 /* (i.e., the last 3 instructions listed above) */
7761 int
7762 is_nacl_call_reg_sequence(guint8* code)
7763 {
7764         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7765                                "\x4d\x03\xdf"     /* add */
7766                                "\x41\xff\xd3";   /* call */
7767         return memcmp(code, sequence, 10) == 0;
7768 }
7769
7770 /* Determine if code points to the first opcode of the mov membase component */
7771 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7772 /* (there could be a REX prefix before the opcode but it is ignored) */
7773 static int
7774 is_nacl_indirect_call_membase_sequence(guint8* code)
7775 {
7776                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7777         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7778                /* and that src reg = dest reg */
7779                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7780                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7781                IS_REX(code[2]) &&
7782                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7783                /* and has dst of r11 and base of r15 */
7784                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7785                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7786 }
7787 #endif /* __native_client_codegen__ */
7788
7789 int
7790 mono_arch_get_this_arg_reg (guint8 *code)
7791 {
7792         return AMD64_ARG_REG1;
7793 }
7794
7795 gpointer
7796 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7797 {
7798         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7799 }
7800
7801 #define MAX_ARCH_DELEGATE_PARAMS 10
7802
7803 static gpointer
7804 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7805 {
7806         guint8 *code, *start;
7807         int i;
7808
7809         if (has_target) {
7810                 start = code = mono_global_codeman_reserve (64);
7811
7812                 /* Replace the this argument with the target */
7813                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7814                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7815                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7816
7817                 g_assert ((code - start) < 64);
7818         } else {
7819                 start = code = mono_global_codeman_reserve (64);
7820
7821                 if (param_count == 0) {
7822                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7823                 } else {
7824                         /* We have to shift the arguments left */
7825                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7826                         for (i = 0; i < param_count; ++i) {
7827 #ifdef TARGET_WIN32
7828                                 if (i < 3)
7829                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7830                                 else
7831                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7832 #else
7833                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7834 #endif
7835                         }
7836
7837                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7838                 }
7839                 g_assert ((code - start) < 64);
7840         }
7841
7842         nacl_global_codeman_validate (&start, 64, &code);
7843         mono_arch_flush_icache (start, code - start);
7844
7845         if (code_len)
7846                 *code_len = code - start;
7847
7848         if (mono_jit_map_is_enabled ()) {
7849                 char *buff;
7850                 if (has_target)
7851                         buff = (char*)"delegate_invoke_has_target";
7852                 else
7853                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7854                 mono_emit_jit_tramp (start, code - start, buff);
7855                 if (!has_target)
7856                         g_free (buff);
7857         }
7858         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7859
7860         return start;
7861 }
7862
7863 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7864
7865 static gpointer
7866 get_delegate_virtual_invoke_impl (gboolean load_imt_reg, int offset, guint32 *code_len)
7867 {
7868         guint8 *code, *start;
7869         int size = 20;
7870
7871         if (offset / sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7872                 return NULL;
7873
7874         start = code = mono_global_codeman_reserve (size);
7875
7876         /* Replace the this argument with the target */
7877         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7878         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7879
7880         if (load_imt_reg) {
7881                 /* Load the IMT reg */
7882                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7883         }
7884
7885         /* Load the vtable */
7886         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7887         amd64_jump_membase (code, AMD64_RAX, offset);
7888         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7889
7890         if (code_len)
7891                 *code_len = code - start;
7892
7893         return start;
7894 }
7895
7896 /*
7897  * mono_arch_get_delegate_invoke_impls:
7898  *
7899  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7900  * trampolines.
7901  */
7902 GSList*
7903 mono_arch_get_delegate_invoke_impls (void)
7904 {
7905         GSList *res = NULL;
7906         guint8 *code;
7907         guint32 code_len;
7908         int i;
7909         char *tramp_name;
7910
7911         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7912         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7913
7914         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7915                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7916                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7917                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7918                 g_free (tramp_name);
7919         }
7920
7921         for (i = 0; i < MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7922                 code = get_delegate_virtual_invoke_impl (TRUE, i * SIZEOF_VOID_P, &code_len);
7923                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", i);
7924                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7925                 g_free (tramp_name);
7926
7927                 code = get_delegate_virtual_invoke_impl (FALSE, i * SIZEOF_VOID_P, &code_len);
7928                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", i);
7929                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7930                 g_free (tramp_name);
7931         }
7932
7933         return res;
7934 }
7935
7936 gpointer
7937 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7938 {
7939         guint8 *code, *start;
7940         int i;
7941
7942         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7943                 return NULL;
7944
7945         /* FIXME: Support more cases */
7946         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7947                 return NULL;
7948
7949         if (has_target) {
7950                 static guint8* cached = NULL;
7951
7952                 if (cached)
7953                         return cached;
7954
7955                 if (mono_aot_only)
7956                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7957                 else
7958                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7959
7960                 mono_memory_barrier ();
7961
7962                 cached = start;
7963         } else {
7964                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7965                 for (i = 0; i < sig->param_count; ++i)
7966                         if (!mono_is_regsize_var (sig->params [i]))
7967                                 return NULL;
7968                 if (sig->param_count > 4)
7969                         return NULL;
7970
7971                 code = cache [sig->param_count];
7972                 if (code)
7973                         return code;
7974
7975                 if (mono_aot_only) {
7976                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7977                         start = mono_aot_get_trampoline (name);
7978                         g_free (name);
7979                 } else {
7980                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7981                 }
7982
7983                 mono_memory_barrier ();
7984
7985                 cache [sig->param_count] = start;
7986         }
7987
7988         return start;
7989 }
7990
7991 gpointer
7992 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7993 {
7994         return get_delegate_virtual_invoke_impl (load_imt_reg, offset, NULL);
7995 }
7996
7997 void
7998 mono_arch_finish_init (void)
7999 {
8000 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8001         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8002 #endif
8003 }
8004
8005 void
8006 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8007 {
8008 }
8009
8010 #if defined(__default_codegen__)
8011 #define CMP_SIZE (6 + 1)
8012 #define CMP_REG_REG_SIZE (4 + 1)
8013 #define BR_SMALL_SIZE 2
8014 #define BR_LARGE_SIZE 6
8015 #define MOV_REG_IMM_SIZE 10
8016 #define MOV_REG_IMM_32BIT_SIZE 6
8017 #define JUMP_REG_SIZE (2 + 1)
8018 #elif defined(__native_client_codegen__)
8019 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8020 #define CMP_SIZE ((6 + 1) * 2 - 1)
8021 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8022 #define BR_SMALL_SIZE (2 * 2 - 1)
8023 #define BR_LARGE_SIZE (6 * 2 - 1)
8024 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8025 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8026 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8027 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8028 /* Jump membase's size is large and unpredictable    */
8029 /* in native client, just pad it out a whole bundle. */
8030 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8031 #endif
8032
8033 static int
8034 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8035 {
8036         int i, distance = 0;
8037         for (i = start; i < target; ++i)
8038                 distance += imt_entries [i]->chunk_size;
8039         return distance;
8040 }
8041
8042 /*
8043  * LOCKING: called with the domain lock held
8044  */
8045 gpointer
8046 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8047         gpointer fail_tramp)
8048 {
8049         int i;
8050         int size = 0;
8051         guint8 *code, *start;
8052         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8053
8054         for (i = 0; i < count; ++i) {
8055                 MonoIMTCheckItem *item = imt_entries [i];
8056                 if (item->is_equals) {
8057                         if (item->check_target_idx) {
8058                                 if (!item->compare_done) {
8059                                         if (amd64_is_imm32 (item->key))
8060                                                 item->chunk_size += CMP_SIZE;
8061                                         else
8062                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8063                                 }
8064                                 if (item->has_target_code) {
8065                                         item->chunk_size += MOV_REG_IMM_SIZE;
8066                                 } else {
8067                                         if (vtable_is_32bit)
8068                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8069                                         else
8070                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8071 #ifdef __native_client_codegen__
8072                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8073 #endif
8074                                 }
8075                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8076                         } else {
8077                                 if (fail_tramp) {
8078                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8079                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8080                                 } else {
8081                                         if (vtable_is_32bit)
8082                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8083                                         else
8084                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8085                                         item->chunk_size += JUMP_REG_SIZE;
8086                                         /* with assert below:
8087                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8088                                          */
8089 #ifdef __native_client_codegen__
8090                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8091 #endif
8092                                 }
8093                         }
8094                 } else {
8095                         if (amd64_is_imm32 (item->key))
8096                                 item->chunk_size += CMP_SIZE;
8097                         else
8098                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8099                         item->chunk_size += BR_LARGE_SIZE;
8100                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8101                 }
8102                 size += item->chunk_size;
8103         }
8104 #if defined(__native_client__) && defined(__native_client_codegen__)
8105         /* In Native Client, we don't re-use thunks, allocate from the */
8106         /* normal code manager paths. */
8107         code = mono_domain_code_reserve (domain, size);
8108 #else
8109         if (fail_tramp)
8110                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8111         else
8112                 code = mono_domain_code_reserve (domain, size);
8113 #endif
8114         start = code;
8115         for (i = 0; i < count; ++i) {
8116                 MonoIMTCheckItem *item = imt_entries [i];
8117                 item->code_target = code;
8118                 if (item->is_equals) {
8119                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8120
8121                         if (item->check_target_idx || fail_case) {
8122                                 if (!item->compare_done || fail_case) {
8123                                         if (amd64_is_imm32 (item->key))
8124                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8125                                         else {
8126                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8127                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8128                                         }
8129                                 }
8130                                 item->jmp_code = code;
8131                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8132                                 if (item->has_target_code) {
8133                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8134                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8135                                 } else {
8136                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8137                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8138                                 }
8139
8140                                 if (fail_case) {
8141                                         amd64_patch (item->jmp_code, code);
8142                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8143                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8144                                         item->jmp_code = NULL;
8145                                 }
8146                         } else {
8147                                 /* enable the commented code to assert on wrong method */
8148 #if 0
8149                                 if (amd64_is_imm32 (item->key))
8150                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8151                                 else {
8152                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8153                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8154                                 }
8155                                 item->jmp_code = code;
8156                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8157                                 /* See the comment below about R10 */
8158                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8159                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8160                                 amd64_patch (item->jmp_code, code);
8161                                 amd64_breakpoint (code);
8162                                 item->jmp_code = NULL;
8163 #else
8164                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8165                                    needs to be preserved.  R10 needs
8166                                    to be preserved for calls which
8167                                    require a runtime generic context,
8168                                    but interface calls don't. */
8169                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8170                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8171 #endif
8172                         }
8173                 } else {
8174                         if (amd64_is_imm32 (item->key))
8175                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8176                         else {
8177                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8178                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8179                         }
8180                         item->jmp_code = code;
8181                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8182                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8183                         else
8184                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8185                 }
8186                 g_assert (code - item->code_target <= item->chunk_size);
8187         }
8188         /* patch the branches to get to the target items */
8189         for (i = 0; i < count; ++i) {
8190                 MonoIMTCheckItem *item = imt_entries [i];
8191                 if (item->jmp_code) {
8192                         if (item->check_target_idx) {
8193                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8194                         }
8195                 }
8196         }
8197
8198         if (!fail_tramp)
8199                 mono_stats.imt_thunks_size += code - start;
8200         g_assert (code - start <= size);
8201
8202         nacl_domain_code_validate(domain, &start, size, &code);
8203         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8204
8205         return start;
8206 }
8207
8208 MonoMethod*
8209 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8210 {
8211         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8212 }
8213
8214 MonoVTable*
8215 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8216 {
8217         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8218 }
8219
8220 GSList*
8221 mono_arch_get_cie_program (void)
8222 {
8223         GSList *l = NULL;
8224
8225         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8226         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8227
8228         return l;
8229 }
8230
8231 #ifndef DISABLE_JIT
8232
8233 MonoInst*
8234 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8235 {
8236         MonoInst *ins = NULL;
8237         int opcode = 0;
8238
8239         if (cmethod->klass == mono_defaults.math_class) {
8240                 if (strcmp (cmethod->name, "Sin") == 0) {
8241                         opcode = OP_SIN;
8242                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8243                         opcode = OP_COS;
8244                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8245                         opcode = OP_SQRT;
8246                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8247                         opcode = OP_ABS;
8248                 }
8249
8250                 if (opcode && fsig->param_count == 1) {
8251                         MONO_INST_NEW (cfg, ins, opcode);
8252                         ins->type = STACK_R8;
8253                         ins->dreg = mono_alloc_freg (cfg);
8254                         ins->sreg1 = args [0]->dreg;
8255                         MONO_ADD_INS (cfg->cbb, ins);
8256                 }
8257
8258                 opcode = 0;
8259                 if (cfg->opt & MONO_OPT_CMOV) {
8260                         if (strcmp (cmethod->name, "Min") == 0) {
8261                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8262                                         opcode = OP_IMIN;
8263                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8264                                         opcode = OP_IMIN_UN;
8265                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8266                                         opcode = OP_LMIN;
8267                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8268                                         opcode = OP_LMIN_UN;
8269                         } else if (strcmp (cmethod->name, "Max") == 0) {
8270                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8271                                         opcode = OP_IMAX;
8272                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8273                                         opcode = OP_IMAX_UN;
8274                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8275                                         opcode = OP_LMAX;
8276                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8277                                         opcode = OP_LMAX_UN;
8278                         }
8279                 }
8280
8281                 if (opcode && fsig->param_count == 2) {
8282                         MONO_INST_NEW (cfg, ins, opcode);
8283                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8284                         ins->dreg = mono_alloc_ireg (cfg);
8285                         ins->sreg1 = args [0]->dreg;
8286                         ins->sreg2 = args [1]->dreg;
8287                         MONO_ADD_INS (cfg->cbb, ins);
8288                 }
8289
8290 #if 0
8291                 /* OP_FREM is not IEEE compatible */
8292                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8293                         MONO_INST_NEW (cfg, ins, OP_FREM);
8294                         ins->inst_i0 = args [0];
8295                         ins->inst_i1 = args [1];
8296                 }
8297 #endif
8298         }
8299
8300         return ins;
8301 }
8302 #endif
8303
8304 gboolean
8305 mono_arch_print_tree (MonoInst *tree, int arity)
8306 {
8307         return 0;
8308 }
8309
8310 mgreg_t
8311 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8312 {
8313         return ctx->gregs [reg];
8314 }
8315
8316 void
8317 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8318 {
8319         ctx->gregs [reg] = val;
8320 }
8321
8322 gpointer
8323 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8324 {
8325         gpointer *sp, old_value;
8326         char *bp;
8327
8328         /*Load the spvar*/
8329         bp = MONO_CONTEXT_GET_BP (ctx);
8330         sp = *(gpointer*)(bp + clause->exvar_offset);
8331
8332         old_value = *sp;
8333         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8334                 return old_value;
8335
8336         *sp = new_value;
8337
8338         return old_value;
8339 }
8340
8341 /*
8342  * mono_arch_emit_load_aotconst:
8343  *
8344  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8345  * TARGET from the mscorlib GOT in full-aot code.
8346  * On AMD64, the result is placed into R11.
8347  */
8348 guint8*
8349 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8350 {
8351         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8352         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8353
8354         return code;
8355 }
8356
8357 /*
8358  * mono_arch_get_trampolines:
8359  *
8360  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8361  * for AOT.
8362  */
8363 GSList *
8364 mono_arch_get_trampolines (gboolean aot)
8365 {
8366         return mono_amd64_get_exception_trampolines (aot);
8367 }
8368
8369 /* Soft Debug support */
8370 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8371
8372 /*
8373  * mono_arch_set_breakpoint:
8374  *
8375  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8376  * The location should contain code emitted by OP_SEQ_POINT.
8377  */
8378 void
8379 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8380 {
8381         guint8 *code = ip;
8382         guint8 *orig_code = code;
8383
8384         if (ji->from_aot) {
8385                 guint32 native_offset = ip - (guint8*)ji->code_start;
8386                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8387
8388                 g_assert (info->bp_addrs [native_offset] == 0);
8389                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8390         } else {
8391                 /*
8392                  * In production, we will use int3 (has to fix the size in the md
8393                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8394                  * instead.
8395                  */
8396                 g_assert (code [0] == 0x90);
8397                 if (breakpoint_size == 8) {
8398                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8399                 } else {
8400                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8401                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8402                 }
8403
8404                 g_assert (code - orig_code == breakpoint_size);
8405         }
8406 }
8407
8408 /*
8409  * mono_arch_clear_breakpoint:
8410  *
8411  *   Clear the breakpoint at IP.
8412  */
8413 void
8414 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8415 {
8416         guint8 *code = ip;
8417         int i;
8418
8419         if (ji->from_aot) {
8420                 guint32 native_offset = ip - (guint8*)ji->code_start;
8421                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8422
8423                 info->bp_addrs [native_offset] = NULL;
8424         } else {
8425                 for (i = 0; i < breakpoint_size; ++i)
8426                         x86_nop (code);
8427         }
8428 }
8429
8430 gboolean
8431 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8432 {
8433 #ifdef HOST_WIN32
8434         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8435         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8436                 return TRUE;
8437         else
8438                 return FALSE;
8439 #else
8440         siginfo_t* sinfo = (siginfo_t*) info;
8441         /* Sometimes the address is off by 4 */
8442         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8443                 return TRUE;
8444         else
8445                 return FALSE;
8446 #endif
8447 }
8448
8449 /*
8450  * mono_arch_skip_breakpoint:
8451  *
8452  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8453  * we resume, the instruction is not executed again.
8454  */
8455 void
8456 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8457 {
8458         if (ji->from_aot) {
8459                 /* The breakpoint instruction is a call */
8460         } else {
8461                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8462         }
8463 }
8464
8465 /*
8466  * mono_arch_start_single_stepping:
8467  *
8468  *   Start single stepping.
8469  */
8470 void
8471 mono_arch_start_single_stepping (void)
8472 {
8473         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8474         ss_trampoline = mini_get_single_step_trampoline ();
8475 }
8476
8477 /*
8478  * mono_arch_stop_single_stepping:
8479  *
8480  *   Stop single stepping.
8481  */
8482 void
8483 mono_arch_stop_single_stepping (void)
8484 {
8485         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8486         ss_trampoline = NULL;
8487 }
8488
8489 /*
8490  * mono_arch_is_single_step_event:
8491  *
8492  *   Return whenever the machine state in SIGCTX corresponds to a single
8493  * step event.
8494  */
8495 gboolean
8496 mono_arch_is_single_step_event (void *info, void *sigctx)
8497 {
8498 #ifdef HOST_WIN32
8499         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8500         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8501                 return TRUE;
8502         else
8503                 return FALSE;
8504 #else
8505         siginfo_t* sinfo = (siginfo_t*) info;
8506         /* Sometimes the address is off by 4 */
8507         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8508                 return TRUE;
8509         else
8510                 return FALSE;
8511 #endif
8512 }
8513
8514 /*
8515  * mono_arch_skip_single_step:
8516  *
8517  *   Modify CTX so the ip is placed after the single step trigger instruction,
8518  * we resume, the instruction is not executed again.
8519  */
8520 void
8521 mono_arch_skip_single_step (MonoContext *ctx)
8522 {
8523         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8524 }
8525
8526 /*
8527  * mono_arch_create_seq_point_info:
8528  *
8529  *   Return a pointer to a data structure which is used by the sequence
8530  * point implementation in AOTed code.
8531  */
8532 gpointer
8533 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8534 {
8535         SeqPointInfo *info;
8536         MonoJitInfo *ji;
8537
8538         // FIXME: Add a free function
8539
8540         mono_domain_lock (domain);
8541         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8542                                                                 code);
8543         mono_domain_unlock (domain);
8544
8545         if (!info) {
8546                 ji = mono_jit_info_table_find (domain, (char*)code);
8547                 g_assert (ji);
8548
8549                 // FIXME: Optimize the size
8550                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8551
8552                 info->ss_tramp_addr = &ss_trampoline;
8553
8554                 mono_domain_lock (domain);
8555                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8556                                                          code, info);
8557                 mono_domain_unlock (domain);
8558         }
8559
8560         return info;
8561 }
8562
8563 void
8564 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8565 {
8566         ext->lmf.previous_lmf = prev_lmf;
8567         /* Mark that this is a MonoLMFExt */
8568         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8569         ext->lmf.rsp = (gssize)ext;
8570 }
8571
8572 #endif
8573
8574 gboolean
8575 mono_arch_opcode_supported (int opcode)
8576 {
8577         switch (opcode) {
8578         case OP_ATOMIC_ADD_I4:
8579         case OP_ATOMIC_ADD_I8:
8580         case OP_ATOMIC_EXCHANGE_I4:
8581         case OP_ATOMIC_EXCHANGE_I8:
8582         case OP_ATOMIC_CAS_I4:
8583         case OP_ATOMIC_CAS_I8:
8584         case OP_ATOMIC_LOAD_I1:
8585         case OP_ATOMIC_LOAD_I2:
8586         case OP_ATOMIC_LOAD_I4:
8587         case OP_ATOMIC_LOAD_I8:
8588         case OP_ATOMIC_LOAD_U1:
8589         case OP_ATOMIC_LOAD_U2:
8590         case OP_ATOMIC_LOAD_U4:
8591         case OP_ATOMIC_LOAD_U8:
8592         case OP_ATOMIC_LOAD_R4:
8593         case OP_ATOMIC_LOAD_R8:
8594         case OP_ATOMIC_STORE_I1:
8595         case OP_ATOMIC_STORE_I2:
8596         case OP_ATOMIC_STORE_I4:
8597         case OP_ATOMIC_STORE_I8:
8598         case OP_ATOMIC_STORE_U1:
8599         case OP_ATOMIC_STORE_U2:
8600         case OP_ATOMIC_STORE_U4:
8601         case OP_ATOMIC_STORE_U8:
8602         case OP_ATOMIC_STORE_R4:
8603         case OP_ATOMIC_STORE_R8:
8604                 return TRUE;
8605         default:
8606                 return FALSE;
8607         }
8608 }