mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/appdomain.h>
  24 #include <mono/metadata/debug-helpers.h>
  25 #include <mono/metadata/threads.h>
  26 #include <mono/metadata/profiler-private.h>
  27 #include <mono/metadata/mono-debug.h>
  28 #include <mono/metadata/gc-internal.h>
  29 #include <mono/utils/mono-math.h>
  30 #include <mono/utils/mono-mmap.h>
  31 #include <mono/utils/mono-memory-model.h>
  32 #include <mono/utils/mono-tls.h>
  33 #include <mono/utils/mono-hwcap-x86.h>
  34
  35 #include "trace.h"
  36 #include "ir-emit.h"
  37 #include "mini-amd64.h"
  38 #include "cpu-amd64.h"
  39 #include "debugger-agent.h"
  40 #include "mini-gc.h"
  41
  42 #ifdef HOST_WIN32
  43 static gint jit_tls_offset = -1;
  44 #endif
  45
  46 #ifdef MONO_XEN_OPT
  47 static gboolean optimize_for_xen = TRUE;
  48 #else
  49 #define optimize_for_xen 0
  50 #endif
  51
  52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  53
  54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  55
  56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  57
  58 #ifdef HOST_WIN32
  59 /* Under windows, the calling convention is never stdcall */
  60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  61 #else
  62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  63 #endif
  64
  65 /* This mutex protects architecture specific caches */
  66 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  67 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  68 static CRITICAL_SECTION mini_arch_mutex;
  69
  70 MonoBreakpointInfo
  71 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  72
  73 /* Structure used by the sequence points in AOTed code */
  74 typedef struct {
  75         gpointer ss_trigger_page;
  76         gpointer bp_trigger_page;
  77         gpointer bp_addrs [MONO_ZERO_LEN_ARRAY];
  78 } SeqPointInfo;
  79
  80 /*
  81  * The code generated for sequence points reads from this location, which is
  82  * made read-only when single stepping is enabled.
  83  */
  84 static gpointer ss_trigger_page;
  85
  86 /* Enabled breakpoints read from this trigger page */
  87 static gpointer bp_trigger_page;
  88
  89 /* The size of the breakpoint sequence */
  90 static int breakpoint_size;
  91
  92 /* The size of the breakpoint instruction causing the actual fault */
  93 static int breakpoint_fault_size;
  94
  95 /* The size of the single step instruction causing the actual fault */
  96 static int single_step_fault_size;
  97
  98 #ifdef HOST_WIN32
  99 /* On Win64 always reserve first 32 bytes for first four arguments */
 100 #define ARGS_OFFSET 48
 101 #else
 102 #define ARGS_OFFSET 16
 103 #endif
 104 #define GP_SCRATCH_REG AMD64_R11
 105
 106 /*
 107  * AMD64 register usage:
 108  * - callee saved registers are used for global register allocation
 109  * - %r11 is used for materializing 64 bit constants in opcodes
 110  * - the rest is used for local allocation
 111  */
 112
 113 /*
 114  * Floating point comparison results:
 115  *                  ZF PF CF
 116  * A > B            0  0  0
 117  * A < B            0  0  1
 118  * A = B            1  0  0
 119  * A > B            0  0  0
 120  * UNORDERED        1  1  1
 121  */
 122
 123 const char*
 124 mono_arch_regname (int reg)
 125 {
 126         switch (reg) {
 127         case AMD64_RAX: return "%rax";
 128         case AMD64_RBX: return "%rbx";
 129         case AMD64_RCX: return "%rcx";
 130         case AMD64_RDX: return "%rdx";
 131         case AMD64_RSP: return "%rsp";
 132         case AMD64_RBP: return "%rbp";
 133         case AMD64_RDI: return "%rdi";
 134         case AMD64_RSI: return "%rsi";
 135         case AMD64_R8: return "%r8";
 136         case AMD64_R9: return "%r9";
 137         case AMD64_R10: return "%r10";
 138         case AMD64_R11: return "%r11";
 139         case AMD64_R12: return "%r12";
 140         case AMD64_R13: return "%r13";
 141         case AMD64_R14: return "%r14";
 142         case AMD64_R15: return "%r15";
 143         }
 144         return "unknown";
 145 }
 146
 147 static const char * packed_xmmregs [] = {
 148         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 149         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 150 };
 151
 152 static const char * single_xmmregs [] = {
 153         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 154         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 155 };
 156
 157 const char*
 158 mono_arch_fregname (int reg)
 159 {
 160         if (reg < AMD64_XMM_NREG)
 161                 return single_xmmregs [reg];
 162         else
 163                 return "unknown";
 164 }
 165
 166 const char *
 167 mono_arch_xregname (int reg)
 168 {
 169         if (reg < AMD64_XMM_NREG)
 170                 return packed_xmmregs [reg];
 171         else
 172                 return "unknown";
 173 }
 174
 175 static gboolean
 176 debug_omit_fp (void)
 177 {
 178 #if 0
 179         return mono_debug_count ();
 180 #else
 181         return TRUE;
 182 #endif
 183 }
 184
 185 static inline gboolean
 186 amd64_is_near_call (guint8 *code)
 187 {
 188         /* Skip REX */
 189         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 190                 code += 1;
 191
 192         return code [0] == 0xe8;
 193 }
 194
 195 #ifdef __native_client_codegen__
 196
 197 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 198 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 199 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 200 /* We only want to force bundle alignment for the top level instruction,    */
 201 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 202 static MonoNativeTlsKey nacl_instruction_depth;
 203
 204 static MonoNativeTlsKey nacl_rex_tag;
 205 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 206
 207 void
 208 amd64_nacl_clear_legacy_prefix_tag ()
 209 {
 210         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 211 }
 212
 213 void
 214 amd64_nacl_tag_legacy_prefix (guint8* code)
 215 {
 216         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 217                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 218 }
 219
 220 void
 221 amd64_nacl_tag_rex (guint8* code)
 222 {
 223         mono_native_tls_set_value (nacl_rex_tag, code);
 224 }
 225
 226 guint8*
 227 amd64_nacl_get_legacy_prefix_tag ()
 228 {
 229         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 230 }
 231
 232 guint8*
 233 amd64_nacl_get_rex_tag ()
 234 {
 235         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 236 }
 237
 238 /* Increment the instruction "depth" described above */
 239 void
 240 amd64_nacl_instruction_pre ()
 241 {
 242         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 243         depth++;
 244         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 245 }
 246
 247 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 248 /* alignment if depth == 0 (top level instruction)                          */
 249 /* IN: start, end    pointers to instruction beginning and end              */
 250 /* OUT: start, end   pointers to beginning and end after possible alignment */
 251 /* GLOBALS: nacl_instruction_depth     defined above                        */
 252 void
 253 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 254 {
 255         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 256         depth--;
 257         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 258
 259         g_assert ( depth >= 0 );
 260         if (depth == 0) {
 261                 uintptr_t space_in_block;
 262                 uintptr_t instlen;
 263                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 264                 /* if legacy prefix is present, and if it was emitted before */
 265                 /* the start of the instruction sequence, adjust the start   */
 266                 if (prefix != NULL && prefix < *start) {
 267                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 268                         *start = prefix;
 269                 }
 270                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 271                 instlen = (uintptr_t)(*end - *start);
 272                 /* Only check for instructions which are less than        */
 273                 /* kNaClAlignment. The only instructions that should ever */
 274                 /* be that long are call sequences, which are already     */
 275                 /* padded out to align the return to the next bundle.     */
 276                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 277                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 278                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 279                         const size_t length = (size_t)((*end)-(*start));
 280                         g_assert (length < MAX_NACL_INST_LENGTH);
 281
 282                         memcpy (copy_of_instruction, *start, length);
 283                         *start = mono_arch_nacl_pad (*start, space_in_block);
 284                         memcpy (*start, copy_of_instruction, length);
 285                         *end = *start + length;
 286                 }
 287                 amd64_nacl_clear_legacy_prefix_tag ();
 288                 amd64_nacl_tag_rex (NULL);
 289         }
 290 }
 291
 292 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 293 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 294 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 295 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 296 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 297 /* IN:      code                                                            */
 298 /*             pointer to current instruction stream (in the                */
 299 /*             middle of an instruction, after opcode is emitted)           */
 300 /*          basereg/offset/dreg                                             */
 301 /*             operands of normal membase address                           */
 302 /* OUT:     code                                                            */
 303 /*             pointer to the end of the membase/memindex emit              */
 304 /* GLOBALS: nacl_rex_tag                                                    */
 305 /*             position in instruction stream that rex prefix was emitted   */
 306 /*          nacl_legacy_prefix_tag                                          */
 307 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 308 void
 309 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 310 {
 311         gint8 true_basereg = basereg;
 312
 313         /* Cache these values, they might change  */
 314         /* as new instructions are emitted below. */
 315         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 316         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 317
 318         /* 'basereg' is given masked to 0x7 at this point, so check */
 319         /* the rex prefix to see if this is an extended register.   */
 320         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 321                 true_basereg |= 0x8;
 322         }
 323
 324 #define X86_LEA_OPCODE (0x8D)
 325
 326         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 327                 guint8* old_instruction_start;
 328
 329                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 330                 /* 32-bits of the old base register (new index register)     */
 331                 guint8 buf[32];
 332                 guint8* buf_ptr = buf;
 333                 size_t insert_len;
 334
 335                 g_assert (rex_tag != NULL);
 336
 337                 if (IS_REX(*rex_tag)) {
 338                         /* The old rex.B should be the new rex.X */
 339                         if (*rex_tag & AMD64_REX_B) {
 340                                 *rex_tag |= AMD64_REX_X;
 341                         }
 342                         /* Since our new base is %r15 set rex.B */
 343                         *rex_tag |= AMD64_REX_B;
 344                 } else {
 345                         /* Shift the instruction by one byte  */
 346                         /* so we can insert a rex prefix      */
 347                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 348                         *code += 1;
 349                         /* New rex prefix only needs rex.B for %r15 base */
 350                         *rex_tag = AMD64_REX(AMD64_REX_B);
 351                 }
 352
 353                 if (legacy_prefix_tag) {
 354                         old_instruction_start = legacy_prefix_tag;
 355                 } else {
 356                         old_instruction_start = rex_tag;
 357                 }
 358
 359                 /* Clears the upper 32-bits of the previous base register */
 360                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 361                 insert_len = buf_ptr - buf;
 362
 363                 /* Move the old instruction forward to make */
 364                 /* room for 'mov' stored in 'buf_ptr'       */
 365                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 366                 *code += insert_len;
 367                 memcpy (old_instruction_start, buf, insert_len);
 368
 369                 /* Sandboxed replacement for the normal membase_emit */
 370                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 371
 372         } else {
 373                 /* Normal default behavior, emit membase memory location */
 374                 x86_membase_emit_body (*code, dreg, basereg, offset);
 375         }
 376 }
 377
 378
 379 static inline unsigned char*
 380 amd64_skip_nops (unsigned char* code)
 381 {
 382         guint8 in_nop;
 383         do {
 384                 in_nop = 0;
 385                 if (   code[0] == 0x90) {
 386                         in_nop = 1;
 387                         code += 1;
 388                 }
 389                 if (   code[0] == 0x66 && code[1] == 0x90) {
 390                         in_nop = 1;
 391                         code += 2;
 392                 }
 393                 if (code[0] == 0x0f && code[1] == 0x1f
 394                  && code[2] == 0x00) {
 395                         in_nop = 1;
 396                         code += 3;
 397                 }
 398                 if (code[0] == 0x0f && code[1] == 0x1f
 399                  && code[2] == 0x40 && code[3] == 0x00) {
 400                         in_nop = 1;
 401                         code += 4;
 402                 }
 403                 if (code[0] == 0x0f && code[1] == 0x1f
 404                  && code[2] == 0x44 && code[3] == 0x00
 405                  && code[4] == 0x00) {
 406                         in_nop = 1;
 407                         code += 5;
 408                 }
 409                 if (code[0] == 0x66 && code[1] == 0x0f
 410                  && code[2] == 0x1f && code[3] == 0x44
 411                  && code[4] == 0x00 && code[5] == 0x00) {
 412                         in_nop = 1;
 413                         code += 6;
 414                 }
 415                 if (code[0] == 0x0f && code[1] == 0x1f
 416                  && code[2] == 0x80 && code[3] == 0x00
 417                  && code[4] == 0x00 && code[5] == 0x00
 418                  && code[6] == 0x00) {
 419                         in_nop = 1;
 420                         code += 7;
 421                 }
 422                 if (code[0] == 0x0f && code[1] == 0x1f
 423                  && code[2] == 0x84 && code[3] == 0x00
 424                  && code[4] == 0x00 && code[5] == 0x00
 425                  && code[6] == 0x00 && code[7] == 0x00) {
 426                         in_nop = 1;
 427                         code += 8;
 428                 }
 429         } while ( in_nop );
 430         return code;
 431 }
 432
 433 guint8*
 434 mono_arch_nacl_skip_nops (guint8* code)
 435 {
 436   return amd64_skip_nops(code);
 437 }
 438
 439 #endif /*__native_client_codegen__*/
 440
 441 static inline void
 442 amd64_patch (unsigned char* code, gpointer target)
 443 {
 444         guint8 rex = 0;
 445
 446 #ifdef __native_client_codegen__
 447         code = amd64_skip_nops (code);
 448 #endif
 449 #if defined(__native_client_codegen__) && defined(__native_client__)
 450         if (nacl_is_code_address (code)) {
 451                 /* For tail calls, code is patched after being installed */
 452                 /* but not through the normal "patch callsite" method.   */
 453                 unsigned char buf[kNaClAlignment];
 454                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 455                 int ret;
 456                 memcpy (buf, aligned_code, kNaClAlignment);
 457                 /* Patch a temp buffer of bundle size, */
 458                 /* then install to actual location.    */
 459                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 460                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 461                 g_assert (ret == 0);
 462                 return;
 463         }
 464         target = nacl_modify_patch_target (target);
 465 #endif
 466
 467         /* Skip REX */
 468         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 469                 rex = code [0];
 470                 code += 1;
 471         }
 472
 473         if ((code [0] & 0xf8) == 0xb8) {
 474                 /* amd64_set_reg_template */
 475                 *(guint64*)(code + 1) = (guint64)target;
 476         }
 477         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 478                 /* mov 0(%rip), %dreg */
 479                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 480         }
 481         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 482                 /* call *<OFFSET>(%rip) */
 483                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 484         }
 485         else if (code [0] == 0xe8) {
 486                 /* call <DISP> */
 487                 gint64 disp = (guint8*)target - (guint8*)code;
 488                 g_assert (amd64_is_imm32 (disp));
 489                 x86_patch (code, (unsigned char*)target);
 490         }
 491         else
 492                 x86_patch (code, (unsigned char*)target);
 493 }
 494
 495 void
 496 mono_amd64_patch (unsigned char* code, gpointer target)
 497 {
 498         amd64_patch (code, target);
 499 }
 500
 501 typedef enum {
 502         ArgInIReg,
 503         ArgInFloatSSEReg,
 504         ArgInDoubleSSEReg,
 505         ArgOnStack,
 506         ArgValuetypeInReg,
 507         ArgValuetypeAddrInIReg,
 508         ArgNone /* only in pair_storage */
 509 } ArgStorage;
 510
 511 typedef struct {
 512         gint16 offset;
 513         gint8  reg;
 514         ArgStorage storage;
 515
 516         /* Only if storage == ArgValuetypeInReg */
 517         ArgStorage pair_storage [2];
 518         gint8 pair_regs [2];
 519         int nregs;
 520 } ArgInfo;
 521
 522 typedef struct {
 523         int nargs;
 524         guint32 stack_usage;
 525         guint32 reg_usage;
 526         guint32 freg_usage;
 527         gboolean need_stack_align;
 528         gboolean vtype_retaddr;
 529         /* The index of the vret arg in the argument list */
 530         int vret_arg_index;
 531         ArgInfo ret;
 532         ArgInfo sig_cookie;
 533         ArgInfo args [1];
 534 } CallInfo;
 535
 536 #define DEBUG(a) if (cfg->verbose_level > 1) a
 537
 538 #ifdef HOST_WIN32
 539 #define PARAM_REGS 4
 540
 541 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 542
 543 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 544 #else
 545 #define PARAM_REGS 6
 546
 547 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 548
 549  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 550 #endif
 551
 552 static void inline
 553 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 554 {
 555     ainfo->offset = *stack_size;
 556
 557     if (*gr >= PARAM_REGS) {
 558                 ainfo->storage = ArgOnStack;
 559                 /* Since the same stack slot size is used for all arg */
 560                 /*  types, it needs to be big enough to hold them all */
 561                 (*stack_size) += sizeof(mgreg_t);
 562     }
 563     else {
 564                 ainfo->storage = ArgInIReg;
 565                 ainfo->reg = param_regs [*gr];
 566                 (*gr) ++;
 567     }
 568 }
 569
 570 #ifdef HOST_WIN32
 571 #define FLOAT_PARAM_REGS 4
 572 #else
 573 #define FLOAT_PARAM_REGS 8
 574 #endif
 575
 576 static void inline
 577 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 578 {
 579     ainfo->offset = *stack_size;
 580
 581     if (*gr >= FLOAT_PARAM_REGS) {
 582                 ainfo->storage = ArgOnStack;
 583                 /* Since the same stack slot size is used for both float */
 584                 /*  types, it needs to be big enough to hold them both */
 585                 (*stack_size) += sizeof(mgreg_t);
 586     }
 587     else {
 588                 /* A double register */
 589                 if (is_double)
 590                         ainfo->storage = ArgInDoubleSSEReg;
 591                 else
 592                         ainfo->storage = ArgInFloatSSEReg;
 593                 ainfo->reg = *gr;
 594                 (*gr) += 1;
 595     }
 596 }
 597
 598 typedef enum ArgumentClass {
 599         ARG_CLASS_NO_CLASS,
 600         ARG_CLASS_MEMORY,
 601         ARG_CLASS_INTEGER,
 602         ARG_CLASS_SSE
 603 } ArgumentClass;
 604
 605 static ArgumentClass
 606 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 607 {
 608         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 609         MonoType *ptype;
 610
 611         ptype = mini_type_get_underlying_type (gsctx, type);
 612         switch (ptype->type) {
 613         case MONO_TYPE_BOOLEAN:
 614         case MONO_TYPE_CHAR:
 615         case MONO_TYPE_I1:
 616         case MONO_TYPE_U1:
 617         case MONO_TYPE_I2:
 618         case MONO_TYPE_U2:
 619         case MONO_TYPE_I4:
 620         case MONO_TYPE_U4:
 621         case MONO_TYPE_I:
 622         case MONO_TYPE_U:
 623         case MONO_TYPE_STRING:
 624         case MONO_TYPE_OBJECT:
 625         case MONO_TYPE_CLASS:
 626         case MONO_TYPE_SZARRAY:
 627         case MONO_TYPE_PTR:
 628         case MONO_TYPE_FNPTR:
 629         case MONO_TYPE_ARRAY:
 630         case MONO_TYPE_I8:
 631         case MONO_TYPE_U8:
 632                 class2 = ARG_CLASS_INTEGER;
 633                 break;
 634         case MONO_TYPE_R4:
 635         case MONO_TYPE_R8:
 636 #ifdef HOST_WIN32
 637                 class2 = ARG_CLASS_INTEGER;
 638 #else
 639                 class2 = ARG_CLASS_SSE;
 640 #endif
 641                 break;
 642
 643         case MONO_TYPE_TYPEDBYREF:
 644                 g_assert_not_reached ();
 645
 646         case MONO_TYPE_GENERICINST:
 647                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 648                         class2 = ARG_CLASS_INTEGER;
 649                         break;
 650                 }
 651                 /* fall through */
 652         case MONO_TYPE_VALUETYPE: {
 653                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 654                 int i;
 655
 656                 for (i = 0; i < info->num_fields; ++i) {
 657                         class2 = class1;
 658                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 659                 }
 660                 break;
 661         }
 662         default:
 663                 g_assert_not_reached ();
 664         }
 665
 666         /* Merge */
 667         if (class1 == class2)
 668                 ;
 669         else if (class1 == ARG_CLASS_NO_CLASS)
 670                 class1 = class2;
 671         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 672                 class1 = ARG_CLASS_MEMORY;
 673         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 674                 class1 = ARG_CLASS_INTEGER;
 675         else
 676                 class1 = ARG_CLASS_SSE;
 677
 678         return class1;
 679 }
 680 #ifdef __native_client_codegen__
 681
 682 /* Default alignment for Native Client is 32-byte. */
 683 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 684
 685 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 686 /* Check that alignment doesn't cross an alignment boundary.             */
 687 guint8*
 688 mono_arch_nacl_pad(guint8 *code, int pad)
 689 {
 690         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 691
 692         if (pad == 0) return code;
 693         /* assertion: alignment cannot cross a block boundary */
 694         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 695                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 696         while (pad >= kMaxPadding) {
 697                 amd64_padding (code, kMaxPadding);
 698                 pad -= kMaxPadding;
 699         }
 700         if (pad != 0) amd64_padding (code, pad);
 701         return code;
 702 }
 703 #endif
 704
 705 static void
 706 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 707                            gboolean is_return,
 708                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 709 {
 710         guint32 size, quad, nquads, i;
 711         /* Keep track of the size used in each quad so we can */
 712         /* use the right size when copying args/return vars.  */
 713         guint32 quadsize [2] = {8, 8};
 714         ArgumentClass args [2];
 715         MonoMarshalType *info = NULL;
 716         MonoClass *klass;
 717         MonoGenericSharingContext tmp_gsctx;
 718         gboolean pass_on_stack = FALSE;
 719
 720         /*
 721          * The gsctx currently contains no data, it is only used for checking whenever
 722          * open types are allowed, some callers like mono_arch_get_argument_info ()
 723          * don't pass it to us, so work around that.
 724          */
 725         if (!gsctx)
 726                 gsctx = &tmp_gsctx;
 727
 728         klass = mono_class_from_mono_type (type);
 729         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 730 #ifndef HOST_WIN32
 731         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 732                 /* We pass and return vtypes of size 8 in a register */
 733         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 734                 pass_on_stack = TRUE;
 735         }
 736 #else
 737         if (!sig->pinvoke) {
 738                 pass_on_stack = TRUE;
 739         }
 740 #endif
 741
 742         /* If this struct can't be split up naturally into 8-byte */
 743         /* chunks (registers), pass it on the stack.              */
 744         if (sig->pinvoke && !pass_on_stack) {
 745                 guint32 align;
 746                 guint32 field_size;
 747
 748                 info = mono_marshal_load_type_info (klass);
 749                 g_assert(info);
 750                 for (i = 0; i < info->num_fields; ++i) {
 751                         field_size = mono_marshal_type_size (info->fields [i].field->type,
 752                                                            info->fields [i].mspec,
 753                                                            &align, TRUE, klass->unicode);
 754                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
 755                                 pass_on_stack = TRUE;
 756                                 break;
 757                         }
 758                 }
 759         }
 760
 761         if (pass_on_stack) {
 762                 /* Allways pass in memory */
 763                 ainfo->offset = *stack_size;
 764                 *stack_size += ALIGN_TO (size, 8);
 765                 ainfo->storage = ArgOnStack;
 766
 767                 return;
 768         }
 769
 770         /* FIXME: Handle structs smaller than 8 bytes */
 771         //if ((size % 8) != 0)
 772         //      NOT_IMPLEMENTED;
 773
 774         if (size > 8)
 775                 nquads = 2;
 776         else
 777                 nquads = 1;
 778
 779         if (!sig->pinvoke) {
 780                 /* Always pass in 1 or 2 integer registers */
 781                 args [0] = ARG_CLASS_INTEGER;
 782                 args [1] = ARG_CLASS_INTEGER;
 783                 /* Only the simplest cases are supported */
 784                 if (is_return && nquads != 1) {
 785                         args [0] = ARG_CLASS_MEMORY;
 786                         args [1] = ARG_CLASS_MEMORY;
 787                 }
 788         } else {
 789                 /*
 790                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 791                  * The X87 and SSEUP stuff is left out since there are no such types in
 792                  * the CLR.
 793                  */
 794                 info = mono_marshal_load_type_info (klass);
 795                 g_assert (info);
 796
 797 #ifndef HOST_WIN32
 798                 if (info->native_size > 16) {
 799                         ainfo->offset = *stack_size;
 800                         *stack_size += ALIGN_TO (info->native_size, 8);
 801                         ainfo->storage = ArgOnStack;
 802
 803                         return;
 804                 }
 805 #else
 806                 switch (info->native_size) {
 807                 case 1: case 2: case 4: case 8:
 808                         break;
 809                 default:
 810                         if (is_return) {
 811                                 ainfo->storage = ArgOnStack;
 812                                 ainfo->offset = *stack_size;
 813                                 *stack_size += ALIGN_TO (info->native_size, 8);
 814                         }
 815                         else {
 816                                 ainfo->storage = ArgValuetypeAddrInIReg;
 817
 818                                 if (*gr < PARAM_REGS) {
 819                                         ainfo->pair_storage [0] = ArgInIReg;
 820                                         ainfo->pair_regs [0] = param_regs [*gr];
 821                                         (*gr) ++;
 822                                 }
 823                                 else {
 824                                         ainfo->pair_storage [0] = ArgOnStack;
 825                                         ainfo->offset = *stack_size;
 826                                         *stack_size += 8;
 827                                 }
 828                         }
 829
 830                         return;
 831                 }
 832 #endif
 833
 834                 args [0] = ARG_CLASS_NO_CLASS;
 835                 args [1] = ARG_CLASS_NO_CLASS;
 836                 for (quad = 0; quad < nquads; ++quad) {
 837                         int size;
 838                         guint32 align;
 839                         ArgumentClass class1;
 840
 841                         if (info->num_fields == 0)
 842                                 class1 = ARG_CLASS_MEMORY;
 843                         else
 844                                 class1 = ARG_CLASS_NO_CLASS;
 845                         for (i = 0; i < info->num_fields; ++i) {
 846                                 size = mono_marshal_type_size (info->fields [i].field->type,
 847                                                                                            info->fields [i].mspec,
 848                                                                                            &align, TRUE, klass->unicode);
 849                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 850                                         /* Unaligned field */
 851                                         NOT_IMPLEMENTED;
 852                                 }
 853
 854                                 /* Skip fields in other quad */
 855                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 856                                         continue;
 857                                 if ((quad == 1) && (info->fields [i].offset < 8))
 858                                         continue;
 859
 860                                 /* How far into this quad this data extends.*/
 861                                 /* (8 is size of quad) */
 862                                 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
 863
 864                                 class1 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class1);
 865                         }
 866                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 867                         args [quad] = class1;
 868                 }
 869         }
 870
 871         /* Post merger cleanup */
 872         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 873                 args [0] = args [1] = ARG_CLASS_MEMORY;
 874
 875         /* Allocate registers */
 876         {
 877                 int orig_gr = *gr;
 878                 int orig_fr = *fr;
 879
 880                 ainfo->storage = ArgValuetypeInReg;
 881                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 882                 ainfo->nregs = nquads;
 883                 for (quad = 0; quad < nquads; ++quad) {
 884                         switch (args [quad]) {
 885                         case ARG_CLASS_INTEGER:
 886                                 if (*gr >= PARAM_REGS)
 887                                         args [quad] = ARG_CLASS_MEMORY;
 888                                 else {
 889                                         ainfo->pair_storage [quad] = ArgInIReg;
 890                                         if (is_return)
 891                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 892                                         else
 893                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 894                                         (*gr) ++;
 895                                 }
 896                                 break;
 897                         case ARG_CLASS_SSE:
 898                                 if (*fr >= FLOAT_PARAM_REGS)
 899                                         args [quad] = ARG_CLASS_MEMORY;
 900                                 else {
 901                                         if (quadsize[quad] <= 4)
 902                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 903                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 904                                         ainfo->pair_regs [quad] = *fr;
 905                                         (*fr) ++;
 906                                 }
 907                                 break;
 908                         case ARG_CLASS_MEMORY:
 909                                 break;
 910                         default:
 911                                 g_assert_not_reached ();
 912                         }
 913                 }
 914
 915                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 916                         /* Revert possible register assignments */
 917                         *gr = orig_gr;
 918                         *fr = orig_fr;
 919
 920                         ainfo->offset = *stack_size;
 921                         if (sig->pinvoke)
 922                                 *stack_size += ALIGN_TO (info->native_size, 8);
 923                         else
 924                                 *stack_size += nquads * sizeof(mgreg_t);
 925                         ainfo->storage = ArgOnStack;
 926                 }
 927         }
 928 }
 929
 930 /*
 931  * get_call_info:
 932  *
 933  *  Obtain information about a call according to the calling convention.
 934  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 935  * Draft Version 0.23" document for more information.
 936  */
 937 static CallInfo*
 938 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 939 {
 940         guint32 i, gr, fr, pstart;
 941         MonoType *ret_type;
 942         int n = sig->hasthis + sig->param_count;
 943         guint32 stack_size = 0;
 944         CallInfo *cinfo;
 945         gboolean is_pinvoke = sig->pinvoke;
 946
 947         if (mp)
 948                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 949         else
 950                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 951
 952         cinfo->nargs = n;
 953
 954         gr = 0;
 955         fr = 0;
 956
 957         /* return value */
 958         {
 959                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 960                 switch (ret_type->type) {
 961                 case MONO_TYPE_BOOLEAN:
 962                 case MONO_TYPE_I1:
 963                 case MONO_TYPE_U1:
 964                 case MONO_TYPE_I2:
 965                 case MONO_TYPE_U2:
 966                 case MONO_TYPE_CHAR:
 967                 case MONO_TYPE_I4:
 968                 case MONO_TYPE_U4:
 969                 case MONO_TYPE_I:
 970                 case MONO_TYPE_U:
 971                 case MONO_TYPE_PTR:
 972                 case MONO_TYPE_FNPTR:
 973                 case MONO_TYPE_CLASS:
 974                 case MONO_TYPE_OBJECT:
 975                 case MONO_TYPE_SZARRAY:
 976                 case MONO_TYPE_ARRAY:
 977                 case MONO_TYPE_STRING:
 978                         cinfo->ret.storage = ArgInIReg;
 979                         cinfo->ret.reg = AMD64_RAX;
 980                         break;
 981                 case MONO_TYPE_U8:
 982                 case MONO_TYPE_I8:
 983                         cinfo->ret.storage = ArgInIReg;
 984                         cinfo->ret.reg = AMD64_RAX;
 985                         break;
 986                 case MONO_TYPE_R4:
 987                         cinfo->ret.storage = ArgInFloatSSEReg;
 988                         cinfo->ret.reg = AMD64_XMM0;
 989                         break;
 990                 case MONO_TYPE_R8:
 991                         cinfo->ret.storage = ArgInDoubleSSEReg;
 992                         cinfo->ret.reg = AMD64_XMM0;
 993                         break;
 994                 case MONO_TYPE_GENERICINST:
 995                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 996                                 cinfo->ret.storage = ArgInIReg;
 997                                 cinfo->ret.reg = AMD64_RAX;
 998                                 break;
 999                         }
1000                         /* fall through */
1001 #if defined( __native_client_codegen__ )
1002                 case MONO_TYPE_TYPEDBYREF:
1003 #endif
1004                 case MONO_TYPE_VALUETYPE: {
1005                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1006
1007                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1008                         if (cinfo->ret.storage == ArgOnStack) {
1009                                 cinfo->vtype_retaddr = TRUE;
1010                                 /* The caller passes the address where the value is stored */
1011                         }
1012                         break;
1013                 }
1014 #if !defined( __native_client_codegen__ )
1015                 case MONO_TYPE_TYPEDBYREF:
1016                         /* Same as a valuetype with size 24 */
1017                         cinfo->vtype_retaddr = TRUE;
1018                         break;
1019 #endif
1020                 case MONO_TYPE_VOID:
1021                         break;
1022                 default:
1023                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1024                 }
1025         }
1026
1027         pstart = 0;
1028         /*
1029          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1030          * the first argument, allowing 'this' to be always passed in the first arg reg.
1031          * Also do this if the first argument is a reference type, since virtual calls
1032          * are sometimes made using calli without sig->hasthis set, like in the delegate
1033          * invoke wrappers.
1034          */
1035         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1036                 if (sig->hasthis) {
1037                         add_general (&gr, &stack_size, cinfo->args + 0);
1038                 } else {
1039                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1040                         pstart = 1;
1041                 }
1042                 add_general (&gr, &stack_size, &cinfo->ret);
1043                 cinfo->vret_arg_index = 1;
1044         } else {
1045                 /* this */
1046                 if (sig->hasthis)
1047                         add_general (&gr, &stack_size, cinfo->args + 0);
1048
1049                 if (cinfo->vtype_retaddr)
1050                         add_general (&gr, &stack_size, &cinfo->ret);
1051         }
1052
1053         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1054                 gr = PARAM_REGS;
1055                 fr = FLOAT_PARAM_REGS;
1056
1057                 /* Emit the signature cookie just before the implicit arguments */
1058                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1059         }
1060
1061         for (i = pstart; i < sig->param_count; ++i) {
1062                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1063                 MonoType *ptype;
1064
1065 #ifdef HOST_WIN32
1066                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1067                 if (gr > fr)
1068                         fr = gr;
1069                 else if (fr > gr)
1070                         gr = fr;
1071 #endif
1072
1073                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1074                         /* We allways pass the sig cookie on the stack for simplicity */
1075                         /*
1076                          * Prevent implicit arguments + the sig cookie from being passed
1077                          * in registers.
1078                          */
1079                         gr = PARAM_REGS;
1080                         fr = FLOAT_PARAM_REGS;
1081
1082                         /* Emit the signature cookie just before the implicit arguments */
1083                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1084                 }
1085
1086                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1087                 switch (ptype->type) {
1088                 case MONO_TYPE_BOOLEAN:
1089                 case MONO_TYPE_I1:
1090                 case MONO_TYPE_U1:
1091                         add_general (&gr, &stack_size, ainfo);
1092                         break;
1093                 case MONO_TYPE_I2:
1094                 case MONO_TYPE_U2:
1095                 case MONO_TYPE_CHAR:
1096                         add_general (&gr, &stack_size, ainfo);
1097                         break;
1098                 case MONO_TYPE_I4:
1099                 case MONO_TYPE_U4:
1100                         add_general (&gr, &stack_size, ainfo);
1101                         break;
1102                 case MONO_TYPE_I:
1103                 case MONO_TYPE_U:
1104                 case MONO_TYPE_PTR:
1105                 case MONO_TYPE_FNPTR:
1106                 case MONO_TYPE_CLASS:
1107                 case MONO_TYPE_OBJECT:
1108                 case MONO_TYPE_STRING:
1109                 case MONO_TYPE_SZARRAY:
1110                 case MONO_TYPE_ARRAY:
1111                         add_general (&gr, &stack_size, ainfo);
1112                         break;
1113                 case MONO_TYPE_GENERICINST:
1114                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1115                                 add_general (&gr, &stack_size, ainfo);
1116                                 break;
1117                         }
1118                         /* fall through */
1119                 case MONO_TYPE_VALUETYPE:
1120                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1121                         break;
1122                 case MONO_TYPE_TYPEDBYREF:
1123 #if defined( HOST_WIN32 ) || defined( __native_client_codegen__ )
1124                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1125 #else
1126                         stack_size += sizeof (MonoTypedRef);
1127                         ainfo->storage = ArgOnStack;
1128 #endif
1129                         break;
1130                 case MONO_TYPE_U8:
1131                 case MONO_TYPE_I8:
1132                         add_general (&gr, &stack_size, ainfo);
1133                         break;
1134                 case MONO_TYPE_R4:
1135                         add_float (&fr, &stack_size, ainfo, FALSE);
1136                         break;
1137                 case MONO_TYPE_R8:
1138                         add_float (&fr, &stack_size, ainfo, TRUE);
1139                         break;
1140                 default:
1141                         g_assert_not_reached ();
1142                 }
1143         }
1144
1145         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1146                 gr = PARAM_REGS;
1147                 fr = FLOAT_PARAM_REGS;
1148
1149                 /* Emit the signature cookie just before the implicit arguments */
1150                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1151         }
1152
1153 #ifdef HOST_WIN32
1154         // There always is 32 bytes reserved on the stack when calling on Winx64
1155         stack_size += 0x20;
1156 #endif
1157
1158 #ifndef MONO_AMD64_NO_PUSHES
1159         if (stack_size & 0x8) {
1160                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1161                 cinfo->need_stack_align = TRUE;
1162                 stack_size += 8;
1163         }
1164 #endif
1165
1166         cinfo->stack_usage = stack_size;
1167         cinfo->reg_usage = gr;
1168         cinfo->freg_usage = fr;
1169         return cinfo;
1170 }
1171
1172 /*
1173  * mono_arch_get_argument_info:
1174  * @csig:  a method signature
1175  * @param_count: the number of parameters to consider
1176  * @arg_info: an array to store the result infos
1177  *
1178  * Gathers information on parameters such as size, alignment and
1179  * padding. arg_info should be large enought to hold param_count + 1 entries.
1180  *
1181  * Returns the size of the argument area on the stack.
1182  */
1183 int
1184 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1185 {
1186         int k;
1187         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1188         guint32 args_size = cinfo->stack_usage;
1189
1190         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1191         if (csig->hasthis) {
1192                 arg_info [0].offset = 0;
1193         }
1194
1195         for (k = 0; k < param_count; k++) {
1196                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1197                 /* FIXME: */
1198                 arg_info [k + 1].size = 0;
1199         }
1200
1201         g_free (cinfo);
1202
1203         return args_size;
1204 }
1205
1206 gboolean
1207 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1208 {
1209         CallInfo *c1, *c2;
1210         gboolean res;
1211         MonoType *callee_ret;
1212
1213         c1 = get_call_info (NULL, NULL, caller_sig);
1214         c2 = get_call_info (NULL, NULL, callee_sig);
1215         res = c1->stack_usage >= c2->stack_usage;
1216         callee_ret = mini_replace_type (callee_sig->ret);
1217         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1218                 /* An address on the callee's stack is passed as the first argument */
1219                 res = FALSE;
1220
1221         g_free (c1);
1222         g_free (c2);
1223
1224         return res;
1225 }
1226
1227 /*
1228  * Initialize the cpu to execute managed code.
1229  */
1230 void
1231 mono_arch_cpu_init (void)
1232 {
1233 #ifndef _MSC_VER
1234         guint16 fpcw;
1235
1236         /* spec compliance requires running with double precision */
1237         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1238         fpcw &= ~X86_FPCW_PRECC_MASK;
1239         fpcw |= X86_FPCW_PREC_DOUBLE;
1240         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1241         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1242 #else
1243         /* TODO: This is crashing on Win64 right now.
1244         * _control87 (_PC_53, MCW_PC);
1245         */
1246 #endif
1247 }
1248
1249 /*
1250  * Initialize architecture specific code.
1251  */
1252 void
1253 mono_arch_init (void)
1254 {
1255         int flags;
1256
1257         InitializeCriticalSection (&mini_arch_mutex);
1258 #if defined(__native_client_codegen__)
1259         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1260         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1261         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1262         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1263 #endif
1264
1265 #ifdef MONO_ARCH_NOMAP32BIT
1266         flags = MONO_MMAP_READ;
1267         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1268         breakpoint_size = 13;
1269         breakpoint_fault_size = 3;
1270 #else
1271         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1272         /* amd64_mov_reg_mem () */
1273         breakpoint_size = 8;
1274         breakpoint_fault_size = 8;
1275 #endif
1276
1277         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1278         single_step_fault_size = 4;
1279
1280         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1281         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1282         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1283
1284         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1285         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1286         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1287 }
1288
1289 /*
1290  * Cleanup architecture specific code.
1291  */
1292 void
1293 mono_arch_cleanup (void)
1294 {
1295         DeleteCriticalSection (&mini_arch_mutex);
1296 #if defined(__native_client_codegen__)
1297         mono_native_tls_free (nacl_instruction_depth);
1298         mono_native_tls_free (nacl_rex_tag);
1299         mono_native_tls_free (nacl_legacy_prefix_tag);
1300 #endif
1301 }
1302
1303 /*
1304  * This function returns the optimizations supported on this cpu.
1305  */
1306 guint32
1307 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1308 {
1309         guint32 opts = 0;
1310
1311         *exclude_mask = 0;
1312
1313         if (mono_hwcap_x86_has_cmov) {
1314                 opts |= MONO_OPT_CMOV;
1315
1316                 if (mono_hwcap_x86_has_fcmov)
1317                         opts |= MONO_OPT_FCMOV;
1318                 else
1319                         *exclude_mask |= MONO_OPT_FCMOV;
1320         } else {
1321                 *exclude_mask |= MONO_OPT_CMOV;
1322         }
1323
1324         return opts;
1325 }
1326
1327 /*
1328  * This function test for all SSE functions supported.
1329  *
1330  * Returns a bitmask corresponding to all supported versions.
1331  *
1332  */
1333 guint32
1334 mono_arch_cpu_enumerate_simd_versions (void)
1335 {
1336         guint32 sse_opts = 0;
1337
1338         if (mono_hwcap_x86_has_sse1)
1339                 sse_opts |= SIMD_VERSION_SSE1;
1340
1341         if (mono_hwcap_x86_has_sse2)
1342                 sse_opts |= SIMD_VERSION_SSE2;
1343
1344         if (mono_hwcap_x86_has_sse3)
1345                 sse_opts |= SIMD_VERSION_SSE3;
1346
1347         if (mono_hwcap_x86_has_ssse3)
1348                 sse_opts |= SIMD_VERSION_SSSE3;
1349
1350         if (mono_hwcap_x86_has_sse41)
1351                 sse_opts |= SIMD_VERSION_SSE41;
1352
1353         if (mono_hwcap_x86_has_sse42)
1354                 sse_opts |= SIMD_VERSION_SSE42;
1355
1356         if (mono_hwcap_x86_has_sse4a)
1357                 sse_opts |= SIMD_VERSION_SSE4a;
1358
1359         return sse_opts;
1360 }
1361
1362 #ifndef DISABLE_JIT
1363
1364 GList *
1365 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1366 {
1367         GList *vars = NULL;
1368         int i;
1369
1370         for (i = 0; i < cfg->num_varinfo; i++) {
1371                 MonoInst *ins = cfg->varinfo [i];
1372                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1373
1374                 /* unused vars */
1375                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1376                         continue;
1377
1378                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1379                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1380                         continue;
1381
1382                 if (mono_is_regsize_var (ins->inst_vtype)) {
1383                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1384                         g_assert (i == vmv->idx);
1385                         vars = g_list_prepend (vars, vmv);
1386                 }
1387         }
1388
1389         vars = mono_varlist_sort (cfg, vars, 0);
1390
1391         return vars;
1392 }
1393
1394 /**
1395  * mono_arch_compute_omit_fp:
1396  *
1397  *   Determine whenever the frame pointer can be eliminated.
1398  */
1399 static void
1400 mono_arch_compute_omit_fp (MonoCompile *cfg)
1401 {
1402         MonoMethodSignature *sig;
1403         MonoMethodHeader *header;
1404         int i, locals_size;
1405         CallInfo *cinfo;
1406
1407         if (cfg->arch.omit_fp_computed)
1408                 return;
1409
1410         header = cfg->header;
1411
1412         sig = mono_method_signature (cfg->method);
1413
1414         if (!cfg->arch.cinfo)
1415                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1416         cinfo = cfg->arch.cinfo;
1417
1418         /*
1419          * FIXME: Remove some of the restrictions.
1420          */
1421         cfg->arch.omit_fp = TRUE;
1422         cfg->arch.omit_fp_computed = TRUE;
1423
1424 #ifdef __native_client_codegen__
1425         /* NaCl modules may not change the value of RBP, so it cannot be */
1426         /* used as a normal register, but it can be used as a frame pointer*/
1427         cfg->disable_omit_fp = TRUE;
1428         cfg->arch.omit_fp = FALSE;
1429 #endif
1430
1431         if (cfg->disable_omit_fp)
1432                 cfg->arch.omit_fp = FALSE;
1433
1434         if (!debug_omit_fp ())
1435                 cfg->arch.omit_fp = FALSE;
1436         /*
1437         if (cfg->method->save_lmf)
1438                 cfg->arch.omit_fp = FALSE;
1439         */
1440         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1441                 cfg->arch.omit_fp = FALSE;
1442         if (header->num_clauses)
1443                 cfg->arch.omit_fp = FALSE;
1444         if (cfg->param_area)
1445                 cfg->arch.omit_fp = FALSE;
1446         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1447                 cfg->arch.omit_fp = FALSE;
1448         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1449                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1450                 cfg->arch.omit_fp = FALSE;
1451         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1452                 ArgInfo *ainfo = &cinfo->args [i];
1453
1454                 if (ainfo->storage == ArgOnStack) {
1455                         /*
1456                          * The stack offset can only be determined when the frame
1457                          * size is known.
1458                          */
1459                         cfg->arch.omit_fp = FALSE;
1460                 }
1461         }
1462
1463         locals_size = 0;
1464         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1465                 MonoInst *ins = cfg->varinfo [i];
1466                 int ialign;
1467
1468                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1469         }
1470 }
1471
1472 GList *
1473 mono_arch_get_global_int_regs (MonoCompile *cfg)
1474 {
1475         GList *regs = NULL;
1476
1477         mono_arch_compute_omit_fp (cfg);
1478
1479         if (cfg->globalra) {
1480                 if (cfg->arch.omit_fp)
1481                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1482
1483                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1484                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1485                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1486                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1487 #ifndef __native_client_codegen__
1488                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1489 #endif
1490
1491                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1492                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1493                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1494                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1495                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1496                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1497                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1498                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1499         } else {
1500                 if (cfg->arch.omit_fp)
1501                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1502
1503                 /* We use the callee saved registers for global allocation */
1504                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1505                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1506                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1507                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1508 #ifndef __native_client_codegen__
1509                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1510 #endif
1511 #ifdef HOST_WIN32
1512                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1513                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1514 #endif
1515         }
1516
1517         return regs;
1518 }
1519
1520 GList*
1521 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1522 {
1523         GList *regs = NULL;
1524         int i;
1525
1526         /* All XMM registers */
1527         for (i = 0; i < 16; ++i)
1528                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1529
1530         return regs;
1531 }
1532
1533 GList*
1534 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1535 {
1536         static GList *r = NULL;
1537
1538         if (r == NULL) {
1539                 GList *regs = NULL;
1540
1541                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1542                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1543                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1544                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1545                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1546 #ifndef __native_client_codegen__
1547                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1548 #endif
1549
1550                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1551                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1552                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1553                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1554                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1555                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1556                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1557                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1558
1559                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1560         }
1561
1562         return r;
1563 }
1564
1565 GList*
1566 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1567 {
1568         int i;
1569         static GList *r = NULL;
1570
1571         if (r == NULL) {
1572                 GList *regs = NULL;
1573
1574                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1575                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1576
1577                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1578         }
1579
1580         return r;
1581 }
1582
1583 /*
1584  * mono_arch_regalloc_cost:
1585  *
1586  *  Return the cost, in number of memory references, of the action of
1587  * allocating the variable VMV into a register during global register
1588  * allocation.
1589  */
1590 guint32
1591 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1592 {
1593         MonoInst *ins = cfg->varinfo [vmv->idx];
1594
1595         if (cfg->method->save_lmf)
1596                 /* The register is already saved */
1597                 /* substract 1 for the invisible store in the prolog */
1598                 return (ins->opcode == OP_ARG) ? 0 : 1;
1599         else
1600                 /* push+pop */
1601                 return (ins->opcode == OP_ARG) ? 1 : 2;
1602 }
1603
1604 /*
1605  * mono_arch_fill_argument_info:
1606  *
1607  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1608  * of the method.
1609  */
1610 void
1611 mono_arch_fill_argument_info (MonoCompile *cfg)
1612 {
1613         MonoType *sig_ret;
1614         MonoMethodSignature *sig;
1615         MonoMethodHeader *header;
1616         MonoInst *ins;
1617         int i;
1618         CallInfo *cinfo;
1619
1620         header = cfg->header;
1621
1622         sig = mono_method_signature (cfg->method);
1623
1624         cinfo = cfg->arch.cinfo;
1625         sig_ret = mini_replace_type (sig->ret);
1626
1627         /*
1628          * Contrary to mono_arch_allocate_vars (), the information should describe
1629          * where the arguments are at the beginning of the method, not where they can be
1630          * accessed during the execution of the method. The later makes no sense for the
1631          * global register allocator, since a variable can be in more than one location.
1632          */
1633         if (sig_ret->type != MONO_TYPE_VOID) {
1634                 switch (cinfo->ret.storage) {
1635                 case ArgInIReg:
1636                 case ArgInFloatSSEReg:
1637                 case ArgInDoubleSSEReg:
1638                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1639                                 cfg->vret_addr->opcode = OP_REGVAR;
1640                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1641                         }
1642                         else {
1643                                 cfg->ret->opcode = OP_REGVAR;
1644                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1645                         }
1646                         break;
1647                 case ArgValuetypeInReg:
1648                         cfg->ret->opcode = OP_REGOFFSET;
1649                         cfg->ret->inst_basereg = -1;
1650                         cfg->ret->inst_offset = -1;
1651                         break;
1652                 default:
1653                         g_assert_not_reached ();
1654                 }
1655         }
1656
1657         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1658                 ArgInfo *ainfo = &cinfo->args [i];
1659                 MonoType *arg_type;
1660
1661                 ins = cfg->args [i];
1662
1663                 if (sig->hasthis && (i == 0))
1664                         arg_type = &mono_defaults.object_class->byval_arg;
1665                 else
1666                         arg_type = sig->params [i - sig->hasthis];
1667
1668                 switch (ainfo->storage) {
1669                 case ArgInIReg:
1670                 case ArgInFloatSSEReg:
1671                 case ArgInDoubleSSEReg:
1672                         ins->opcode = OP_REGVAR;
1673                         ins->inst_c0 = ainfo->reg;
1674                         break;
1675                 case ArgOnStack:
1676                         ins->opcode = OP_REGOFFSET;
1677                         ins->inst_basereg = -1;
1678                         ins->inst_offset = -1;
1679                         break;
1680                 case ArgValuetypeInReg:
1681                         /* Dummy */
1682                         ins->opcode = OP_NOP;
1683                         break;
1684                 default:
1685                         g_assert_not_reached ();
1686                 }
1687         }
1688 }
1689
1690 void
1691 mono_arch_allocate_vars (MonoCompile *cfg)
1692 {
1693         MonoType *sig_ret;
1694         MonoMethodSignature *sig;
1695         MonoMethodHeader *header;
1696         MonoInst *ins;
1697         int i, offset;
1698         guint32 locals_stack_size, locals_stack_align;
1699         gint32 *offsets;
1700         CallInfo *cinfo;
1701
1702         header = cfg->header;
1703
1704         sig = mono_method_signature (cfg->method);
1705
1706         cinfo = cfg->arch.cinfo;
1707         sig_ret = mini_replace_type (sig->ret);
1708
1709         mono_arch_compute_omit_fp (cfg);
1710
1711         /*
1712          * We use the ABI calling conventions for managed code as well.
1713          * Exception: valuetypes are only sometimes passed or returned in registers.
1714          */
1715
1716         /*
1717          * The stack looks like this:
1718          * <incoming arguments passed on the stack>
1719          * <return value>
1720          * <lmf/caller saved registers>
1721          * <locals>
1722          * <spill area>
1723          * <localloc area>  -> grows dynamically
1724          * <params area>
1725          */
1726
1727         if (cfg->arch.omit_fp) {
1728                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1729                 cfg->frame_reg = AMD64_RSP;
1730                 offset = 0;
1731         } else {
1732                 /* Locals are allocated backwards from %fp */
1733                 cfg->frame_reg = AMD64_RBP;
1734                 offset = 0;
1735         }
1736
1737         if (cfg->method->save_lmf) {
1738                 /* The LMF var is allocated normally */
1739         } else {
1740                 if (cfg->arch.omit_fp)
1741                         cfg->arch.reg_save_area_offset = offset;
1742                 /* Reserve space for callee saved registers */
1743                 for (i = 0; i < AMD64_NREG; ++i)
1744                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1745                                 offset += sizeof(mgreg_t);
1746                         }
1747                 if (!cfg->arch.omit_fp)
1748                         cfg->arch.reg_save_area_offset = -offset;
1749         }
1750
1751         if (sig_ret->type != MONO_TYPE_VOID) {
1752                 switch (cinfo->ret.storage) {
1753                 case ArgInIReg:
1754                 case ArgInFloatSSEReg:
1755                 case ArgInDoubleSSEReg:
1756                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1757                                 if (cfg->globalra) {
1758                                         cfg->vret_addr->opcode = OP_REGVAR;
1759                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1760                                 } else {
1761                                         /* The register is volatile */
1762                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1763                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1764                                         if (cfg->arch.omit_fp) {
1765                                                 cfg->vret_addr->inst_offset = offset;
1766                                                 offset += 8;
1767                                         } else {
1768                                                 offset += 8;
1769                                                 cfg->vret_addr->inst_offset = -offset;
1770                                         }
1771                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1772                                                 printf ("vret_addr =");
1773                                                 mono_print_ins (cfg->vret_addr);
1774                                         }
1775                                 }
1776                         }
1777                         else {
1778                                 cfg->ret->opcode = OP_REGVAR;
1779                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1780                         }
1781                         break;
1782                 case ArgValuetypeInReg:
1783                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1784                         cfg->ret->opcode = OP_REGOFFSET;
1785                         cfg->ret->inst_basereg = cfg->frame_reg;
1786                         if (cfg->arch.omit_fp) {
1787                                 cfg->ret->inst_offset = offset;
1788                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1789                         } else {
1790                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1791                                 cfg->ret->inst_offset = - offset;
1792                         }
1793                         break;
1794                 default:
1795                         g_assert_not_reached ();
1796                 }
1797                 if (!cfg->globalra)
1798                         cfg->ret->dreg = cfg->ret->inst_c0;
1799         }
1800
1801         /* Allocate locals */
1802         if (!cfg->globalra) {
1803                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1804                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1805                         char *mname = mono_method_full_name (cfg->method, TRUE);
1806                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1807                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1808                         g_free (mname);
1809                         return;
1810                 }
1811
1812                 if (locals_stack_align) {
1813                         offset += (locals_stack_align - 1);
1814                         offset &= ~(locals_stack_align - 1);
1815                 }
1816                 if (cfg->arch.omit_fp) {
1817                         cfg->locals_min_stack_offset = offset;
1818                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1819                 } else {
1820                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1821                         cfg->locals_max_stack_offset = - offset;
1822                 }
1823
1824                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1825                         if (offsets [i] != -1) {
1826                                 MonoInst *ins = cfg->varinfo [i];
1827                                 ins->opcode = OP_REGOFFSET;
1828                                 ins->inst_basereg = cfg->frame_reg;
1829                                 if (cfg->arch.omit_fp)
1830                                         ins->inst_offset = (offset + offsets [i]);
1831                                 else
1832                                         ins->inst_offset = - (offset + offsets [i]);
1833                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1834                         }
1835                 }
1836                 offset += locals_stack_size;
1837         }
1838
1839         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1840                 g_assert (!cfg->arch.omit_fp);
1841                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1842                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1843         }
1844
1845         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1846                 ins = cfg->args [i];
1847                 if (ins->opcode != OP_REGVAR) {
1848                         ArgInfo *ainfo = &cinfo->args [i];
1849                         gboolean inreg = TRUE;
1850                         MonoType *arg_type;
1851
1852                         if (sig->hasthis && (i == 0))
1853                                 arg_type = &mono_defaults.object_class->byval_arg;
1854                         else
1855                                 arg_type = sig->params [i - sig->hasthis];
1856
1857                         if (cfg->globalra) {
1858                                 /* The new allocator needs info about the original locations of the arguments */
1859                                 switch (ainfo->storage) {
1860                                 case ArgInIReg:
1861                                 case ArgInFloatSSEReg:
1862                                 case ArgInDoubleSSEReg:
1863                                         ins->opcode = OP_REGVAR;
1864                                         ins->inst_c0 = ainfo->reg;
1865                                         break;
1866                                 case ArgOnStack:
1867                                         g_assert (!cfg->arch.omit_fp);
1868                                         ins->opcode = OP_REGOFFSET;
1869                                         ins->inst_basereg = cfg->frame_reg;
1870                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1871                                         break;
1872                                 case ArgValuetypeInReg:
1873                                         ins->opcode = OP_REGOFFSET;
1874                                         ins->inst_basereg = cfg->frame_reg;
1875                                         /* These arguments are saved to the stack in the prolog */
1876                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1877                                         if (cfg->arch.omit_fp) {
1878                                                 ins->inst_offset = offset;
1879                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1880                                         } else {
1881                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1882                                                 ins->inst_offset = - offset;
1883                                         }
1884                                         break;
1885                                 default:
1886                                         g_assert_not_reached ();
1887                                 }
1888
1889                                 continue;
1890                         }
1891
1892                         /* FIXME: Allocate volatile arguments to registers */
1893                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1894                                 inreg = FALSE;
1895
1896                         /*
1897                          * Under AMD64, all registers used to pass arguments to functions
1898                          * are volatile across calls.
1899                          * FIXME: Optimize this.
1900                          */
1901                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1902                                 inreg = FALSE;
1903
1904                         ins->opcode = OP_REGOFFSET;
1905
1906                         switch (ainfo->storage) {
1907                         case ArgInIReg:
1908                         case ArgInFloatSSEReg:
1909                         case ArgInDoubleSSEReg:
1910                                 if (inreg) {
1911                                         ins->opcode = OP_REGVAR;
1912                                         ins->dreg = ainfo->reg;
1913                                 }
1914                                 break;
1915                         case ArgOnStack:
1916                                 g_assert (!cfg->arch.omit_fp);
1917                                 ins->opcode = OP_REGOFFSET;
1918                                 ins->inst_basereg = cfg->frame_reg;
1919                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1920                                 break;
1921                         case ArgValuetypeInReg:
1922                                 break;
1923                         case ArgValuetypeAddrInIReg: {
1924                                 MonoInst *indir;
1925                                 g_assert (!cfg->arch.omit_fp);
1926
1927                                 MONO_INST_NEW (cfg, indir, 0);
1928                                 indir->opcode = OP_REGOFFSET;
1929                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1930                                         indir->inst_basereg = cfg->frame_reg;
1931                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1932                                         offset += (sizeof (gpointer));
1933                                         indir->inst_offset = - offset;
1934                                 }
1935                                 else {
1936                                         indir->inst_basereg = cfg->frame_reg;
1937                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1938                                 }
1939
1940                                 ins->opcode = OP_VTARG_ADDR;
1941                                 ins->inst_left = indir;
1942
1943                                 break;
1944                         }
1945                         default:
1946                                 NOT_IMPLEMENTED;
1947                         }
1948
1949                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1950                                 ins->opcode = OP_REGOFFSET;
1951                                 ins->inst_basereg = cfg->frame_reg;
1952                                 /* These arguments are saved to the stack in the prolog */
1953                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1954                                 if (cfg->arch.omit_fp) {
1955                                         ins->inst_offset = offset;
1956                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1957                                         // Arguments are yet supported by the stack map creation code
1958                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1959                                 } else {
1960                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1961                                         ins->inst_offset = - offset;
1962                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1963                                 }
1964                         }
1965                 }
1966         }
1967
1968         cfg->stack_offset = offset;
1969 }
1970
1971 void
1972 mono_arch_create_vars (MonoCompile *cfg)
1973 {
1974         MonoMethodSignature *sig;
1975         CallInfo *cinfo;
1976         MonoType *sig_ret;
1977
1978         sig = mono_method_signature (cfg->method);
1979
1980         if (!cfg->arch.cinfo)
1981                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1982         cinfo = cfg->arch.cinfo;
1983
1984         if (cinfo->ret.storage == ArgValuetypeInReg)
1985                 cfg->ret_var_is_local = TRUE;
1986
1987         sig_ret = mini_replace_type (sig->ret);
1988         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1989                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1990                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1991                         printf ("vret_addr = ");
1992                         mono_print_ins (cfg->vret_addr);
1993                 }
1994         }
1995
1996         if (cfg->gen_seq_points) {
1997                 MonoInst *ins;
1998
1999                 if (cfg->compile_aot) {
2000                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2001                         ins->flags |= MONO_INST_VOLATILE;
2002                         cfg->arch.seq_point_info_var = ins;
2003                 }
2004
2005             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2006                 ins->flags |= MONO_INST_VOLATILE;
2007                 cfg->arch.ss_trigger_page_var = ins;
2008         }
2009
2010 #ifdef MONO_AMD64_NO_PUSHES
2011         /*
2012          * When this is set, we pass arguments on the stack by moves, and by allocating
2013          * a bigger stack frame, instead of pushes.
2014          * Pushes complicate exception handling because the arguments on the stack have
2015          * to be popped each time a frame is unwound. They also make fp elimination
2016          * impossible.
2017          * FIXME: This doesn't work inside filter/finally clauses, since those execute
2018          * on a new frame which doesn't include a param area.
2019          */
2020         cfg->arch.no_pushes = TRUE;
2021 #endif
2022
2023         if (cfg->method->save_lmf)
2024                 cfg->create_lmf_var = TRUE;
2025
2026 #if !defined(HOST_WIN32)
2027         if (cfg->method->save_lmf) {
2028                 cfg->lmf_ir = TRUE;
2029                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2030                         cfg->lmf_ir_mono_lmf = TRUE;
2031         }
2032 #endif
2033
2034 #ifndef MONO_AMD64_NO_PUSHES
2035         cfg->arch_eh_jit_info = 1;
2036 #endif
2037 }
2038
2039 static void
2040 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2041 {
2042         MonoInst *ins;
2043
2044         switch (storage) {
2045         case ArgInIReg:
2046                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2047                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2048                 ins->sreg1 = tree->dreg;
2049                 MONO_ADD_INS (cfg->cbb, ins);
2050                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2051                 break;
2052         case ArgInFloatSSEReg:
2053                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2054                 ins->dreg = mono_alloc_freg (cfg);
2055                 ins->sreg1 = tree->dreg;
2056                 MONO_ADD_INS (cfg->cbb, ins);
2057
2058                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2059                 break;
2060         case ArgInDoubleSSEReg:
2061                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2062                 ins->dreg = mono_alloc_freg (cfg);
2063                 ins->sreg1 = tree->dreg;
2064                 MONO_ADD_INS (cfg->cbb, ins);
2065
2066                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2067
2068                 break;
2069         default:
2070                 g_assert_not_reached ();
2071         }
2072 }
2073
2074 static int
2075 arg_storage_to_load_membase (ArgStorage storage)
2076 {
2077         switch (storage) {
2078         case ArgInIReg:
2079 #if defined(__mono_ilp32__)
2080                 return OP_LOADI8_MEMBASE;
2081 #else
2082                 return OP_LOAD_MEMBASE;
2083 #endif
2084         case ArgInDoubleSSEReg:
2085                 return OP_LOADR8_MEMBASE;
2086         case ArgInFloatSSEReg:
2087                 return OP_LOADR4_MEMBASE;
2088         default:
2089                 g_assert_not_reached ();
2090         }
2091
2092         return -1;
2093 }
2094
2095 static void
2096 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2097 {
2098         MonoInst *arg;
2099         MonoMethodSignature *tmp_sig;
2100         int sig_reg;
2101
2102         if (call->tail_call)
2103                 NOT_IMPLEMENTED;
2104
2105         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2106
2107         /*
2108          * mono_ArgIterator_Setup assumes the signature cookie is
2109          * passed first and all the arguments which were before it are
2110          * passed on the stack after the signature. So compensate by
2111          * passing a different signature.
2112          */
2113         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2114         tmp_sig->param_count -= call->signature->sentinelpos;
2115         tmp_sig->sentinelpos = 0;
2116         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2117
2118         sig_reg = mono_alloc_ireg (cfg);
2119         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2120
2121         if (cfg->arch.no_pushes) {
2122                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2123         } else {
2124                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2125                 arg->sreg1 = sig_reg;
2126                 MONO_ADD_INS (cfg->cbb, arg);
2127         }
2128 }
2129
2130 static inline LLVMArgStorage
2131 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2132 {
2133         switch (storage) {
2134         case ArgInIReg:
2135                 return LLVMArgInIReg;
2136         case ArgNone:
2137                 return LLVMArgNone;
2138         default:
2139                 g_assert_not_reached ();
2140                 return LLVMArgNone;
2141         }
2142 }
2143
2144 #ifdef ENABLE_LLVM
2145 LLVMCallInfo*
2146 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2147 {
2148         int i, n;
2149         CallInfo *cinfo;
2150         ArgInfo *ainfo;
2151         int j;
2152         LLVMCallInfo *linfo;
2153         MonoType *t, *sig_ret;
2154
2155         n = sig->param_count + sig->hasthis;
2156         sig_ret = mini_replace_type (sig->ret);
2157
2158         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2159
2160         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2161
2162         /*
2163          * LLVM always uses the native ABI while we use our own ABI, the
2164          * only difference is the handling of vtypes:
2165          * - we only pass/receive them in registers in some cases, and only
2166          *   in 1 or 2 integer registers.
2167          */
2168         if (cinfo->ret.storage == ArgValuetypeInReg) {
2169                 if (sig->pinvoke) {
2170                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2171                         cfg->disable_llvm = TRUE;
2172                         return linfo;
2173                 }
2174
2175                 linfo->ret.storage = LLVMArgVtypeInReg;
2176                 for (j = 0; j < 2; ++j)
2177                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2178         }
2179
2180         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2181                 /* Vtype returned using a hidden argument */
2182                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2183                 linfo->vret_arg_index = cinfo->vret_arg_index;
2184         }
2185
2186         for (i = 0; i < n; ++i) {
2187                 ainfo = cinfo->args + i;
2188
2189                 if (i >= sig->hasthis)
2190                         t = sig->params [i - sig->hasthis];
2191                 else
2192                         t = &mono_defaults.int_class->byval_arg;
2193
2194                 linfo->args [i].storage = LLVMArgNone;
2195
2196                 switch (ainfo->storage) {
2197                 case ArgInIReg:
2198                         linfo->args [i].storage = LLVMArgInIReg;
2199                         break;
2200                 case ArgInDoubleSSEReg:
2201                 case ArgInFloatSSEReg:
2202                         linfo->args [i].storage = LLVMArgInFPReg;
2203                         break;
2204                 case ArgOnStack:
2205                         if (MONO_TYPE_ISSTRUCT (t)) {
2206                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2207                         } else {
2208                                 linfo->args [i].storage = LLVMArgInIReg;
2209                                 if (!t->byref) {
2210                                         if (t->type == MONO_TYPE_R4)
2211                                                 linfo->args [i].storage = LLVMArgInFPReg;
2212                                         else if (t->type == MONO_TYPE_R8)
2213                                                 linfo->args [i].storage = LLVMArgInFPReg;
2214                                 }
2215                         }
2216                         break;
2217                 case ArgValuetypeInReg:
2218                         if (sig->pinvoke) {
2219                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2220                                 cfg->disable_llvm = TRUE;
2221                                 return linfo;
2222                         }
2223
2224                         linfo->args [i].storage = LLVMArgVtypeInReg;
2225                         for (j = 0; j < 2; ++j)
2226                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2227                         break;
2228                 default:
2229                         cfg->exception_message = g_strdup ("ainfo->storage");
2230                         cfg->disable_llvm = TRUE;
2231                         break;
2232                 }
2233         }
2234
2235         return linfo;
2236 }
2237 #endif
2238
2239 void
2240 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2241 {
2242         MonoInst *arg, *in;
2243         MonoMethodSignature *sig;
2244         MonoType *sig_ret;
2245         int i, n, stack_size;
2246         CallInfo *cinfo;
2247         ArgInfo *ainfo;
2248
2249         stack_size = 0;
2250
2251         sig = call->signature;
2252         n = sig->param_count + sig->hasthis;
2253
2254         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2255
2256         sig_ret = sig->ret;
2257
2258         if (COMPILE_LLVM (cfg)) {
2259                 /* We shouldn't be called in the llvm case */
2260                 cfg->disable_llvm = TRUE;
2261                 return;
2262         }
2263
2264         if (cinfo->need_stack_align) {
2265                 if (!cfg->arch.no_pushes)
2266                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2267         }
2268
2269         /*
2270          * Emit all arguments which are passed on the stack to prevent register
2271          * allocation problems.
2272          */
2273         if (cfg->arch.no_pushes) {
2274                 for (i = 0; i < n; ++i) {
2275                         MonoType *t;
2276                         ainfo = cinfo->args + i;
2277
2278                         in = call->args [i];
2279
2280                         if (sig->hasthis && i == 0)
2281                                 t = &mono_defaults.object_class->byval_arg;
2282                         else
2283                                 t = sig->params [i - sig->hasthis];
2284
2285                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2286                                 if (!t->byref) {
2287                                         if (t->type == MONO_TYPE_R4)
2288                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2289                                         else if (t->type == MONO_TYPE_R8)
2290                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2291                                         else
2292                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2293                                 } else {
2294                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2295                                 }
2296                                 if (cfg->compute_gc_maps) {
2297                                         MonoInst *def;
2298
2299                                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2300                                 }
2301                         }
2302                 }
2303         }
2304
2305         /*
2306          * Emit all parameters passed in registers in non-reverse order for better readability
2307          * and to help the optimization in emit_prolog ().
2308          */
2309         for (i = 0; i < n; ++i) {
2310                 ainfo = cinfo->args + i;
2311
2312                 in = call->args [i];
2313
2314                 if (ainfo->storage == ArgInIReg)
2315                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2316         }
2317
2318         for (i = n - 1; i >= 0; --i) {
2319                 ainfo = cinfo->args + i;
2320
2321                 in = call->args [i];
2322
2323                 switch (ainfo->storage) {
2324                 case ArgInIReg:
2325                         /* Already done */
2326                         break;
2327                 case ArgInFloatSSEReg:
2328                 case ArgInDoubleSSEReg:
2329                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2330                         break;
2331                 case ArgOnStack:
2332                 case ArgValuetypeInReg:
2333                 case ArgValuetypeAddrInIReg:
2334                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2335                                 MonoInst *call_inst = (MonoInst*)call;
2336                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2337                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2338                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2339                                 guint32 align;
2340                                 guint32 size;
2341
2342                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2343                                         size = sizeof (MonoTypedRef);
2344                                         align = sizeof (gpointer);
2345                                 }
2346                                 else {
2347                                         if (sig->pinvoke)
2348                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2349                                         else {
2350                                                 /*
2351                                                  * Other backends use mono_type_stack_size (), but that
2352                                                  * aligns the size to 8, which is larger than the size of
2353                                                  * the source, leading to reads of invalid memory if the
2354                                                  * source is at the end of address space.
2355                                                  */
2356                                                 size = mono_class_value_size (in->klass, &align);
2357                                         }
2358                                 }
2359                                 g_assert (in->klass);
2360
2361                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2362                                         /* Avoid asserts in emit_memcpy () */
2363                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2364                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2365                                         /* Continue normally */
2366                                 }
2367
2368                                 if (size > 0) {
2369                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2370                                         arg->sreg1 = in->dreg;
2371                                         arg->klass = in->klass;
2372                                         arg->backend.size = size;
2373                                         arg->inst_p0 = call;
2374                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2375                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2376
2377                                         MONO_ADD_INS (cfg->cbb, arg);
2378                                 }
2379                         } else {
2380                                 if (cfg->arch.no_pushes) {
2381                                         /* Already done */
2382                                 } else {
2383                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2384                                         arg->sreg1 = in->dreg;
2385                                         if (!sig->params [i - sig->hasthis]->byref) {
2386                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2387                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2388                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2389                                                         arg->inst_destbasereg = X86_ESP;
2390                                                         arg->inst_offset = 0;
2391                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2392                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2393                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2394                                                         arg->inst_destbasereg = X86_ESP;
2395                                                         arg->inst_offset = 0;
2396                                                 }
2397                                         }
2398                                         MONO_ADD_INS (cfg->cbb, arg);
2399                                 }
2400                         }
2401                         break;
2402                 default:
2403                         g_assert_not_reached ();
2404                 }
2405
2406                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2407                         /* Emit the signature cookie just before the implicit arguments */
2408                         emit_sig_cookie (cfg, call, cinfo);
2409         }
2410
2411         /* Handle the case where there are no implicit arguments */
2412         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2413                 emit_sig_cookie (cfg, call, cinfo);
2414
2415         sig_ret = mini_replace_type (sig->ret);
2416         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2417                 MonoInst *vtarg;
2418
2419                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2420                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2421                                 /*
2422                                  * Tell the JIT to use a more efficient calling convention: call using
2423                                  * OP_CALL, compute the result location after the call, and save the
2424                                  * result there.
2425                                  */
2426                                 call->vret_in_reg = TRUE;
2427                                 /*
2428                                  * Nullify the instruction computing the vret addr to enable
2429                                  * future optimizations.
2430                                  */
2431                                 if (call->vret_var)
2432                                         NULLIFY_INS (call->vret_var);
2433                         } else {
2434                                 if (call->tail_call)
2435                                         NOT_IMPLEMENTED;
2436                                 /*
2437                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2438                                  * the stack. Push the address here, so the call instruction can
2439                                  * access it.
2440                                  */
2441                                 if (!cfg->arch.vret_addr_loc) {
2442                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2443                                         /* Prevent it from being register allocated or optimized away */
2444                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2445                                 }
2446
2447                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2448                         }
2449                 }
2450                 else {
2451                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2452                         vtarg->sreg1 = call->vret_var->dreg;
2453                         vtarg->dreg = mono_alloc_preg (cfg);
2454                         MONO_ADD_INS (cfg->cbb, vtarg);
2455
2456                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2457                 }
2458         }
2459
2460 #ifdef HOST_WIN32
2461         if (call->inst.opcode != OP_TAILCALL) {
2462                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2463         }
2464 #endif
2465
2466         if (cfg->method->save_lmf) {
2467                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2468                 MONO_ADD_INS (cfg->cbb, arg);
2469         }
2470
2471         call->stack_usage = cinfo->stack_usage;
2472 }
2473
2474 void
2475 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2476 {
2477         MonoInst *arg;
2478         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2479         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2480         int size = ins->backend.size;
2481
2482         if (ainfo->storage == ArgValuetypeInReg) {
2483                 MonoInst *load;
2484                 int part;
2485
2486                 for (part = 0; part < 2; ++part) {
2487                         if (ainfo->pair_storage [part] == ArgNone)
2488                                 continue;
2489
2490                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2491                         load->inst_basereg = src->dreg;
2492                         load->inst_offset = part * sizeof(mgreg_t);
2493
2494                         switch (ainfo->pair_storage [part]) {
2495                         case ArgInIReg:
2496                                 load->dreg = mono_alloc_ireg (cfg);
2497                                 break;
2498                         case ArgInDoubleSSEReg:
2499                         case ArgInFloatSSEReg:
2500                                 load->dreg = mono_alloc_freg (cfg);
2501                                 break;
2502                         default:
2503                                 g_assert_not_reached ();
2504                         }
2505                         MONO_ADD_INS (cfg->cbb, load);
2506
2507                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2508                 }
2509         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2510                 MonoInst *vtaddr, *load;
2511                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2512
2513                 g_assert (!cfg->arch.no_pushes);
2514
2515                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2516                 cfg->has_indirection = TRUE;
2517                 load->inst_p0 = vtaddr;
2518                 vtaddr->flags |= MONO_INST_INDIRECT;
2519                 load->type = STACK_MP;
2520                 load->klass = vtaddr->klass;
2521                 load->dreg = mono_alloc_ireg (cfg);
2522                 MONO_ADD_INS (cfg->cbb, load);
2523                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2524
2525                 if (ainfo->pair_storage [0] == ArgInIReg) {
2526                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2527                         arg->dreg = mono_alloc_ireg (cfg);
2528                         arg->sreg1 = load->dreg;
2529                         arg->inst_imm = 0;
2530                         MONO_ADD_INS (cfg->cbb, arg);
2531                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2532                 } else {
2533                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2534                         arg->sreg1 = load->dreg;
2535                         MONO_ADD_INS (cfg->cbb, arg);
2536                 }
2537         } else {
2538                 if (size == 8) {
2539                         if (cfg->arch.no_pushes) {
2540                                 int dreg = mono_alloc_ireg (cfg);
2541
2542                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2543                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2544                         } else {
2545                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2546                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2547                                 arg->inst_basereg = src->dreg;
2548                                 arg->inst_offset = 0;
2549                                 MONO_ADD_INS (cfg->cbb, arg);
2550                         }
2551                 } else if (size <= 40) {
2552                         if (cfg->arch.no_pushes) {
2553                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2554                         } else {
2555                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2556                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2557                         }
2558                 } else {
2559                         if (cfg->arch.no_pushes) {
2560                                 // FIXME: Code growth
2561                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2562                         } else {
2563                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2564                                 arg->inst_basereg = src->dreg;
2565                                 arg->inst_offset = 0;
2566                                 arg->inst_imm = size;
2567                                 MONO_ADD_INS (cfg->cbb, arg);
2568                         }
2569                 }
2570
2571                 if (cfg->compute_gc_maps) {
2572                         MonoInst *def;
2573                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2574                 }
2575         }
2576 }
2577
2578 void
2579 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2580 {
2581         MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2582
2583         if (ret->type == MONO_TYPE_R4) {
2584                 if (COMPILE_LLVM (cfg))
2585                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2586                 else
2587                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2588                 return;
2589         } else if (ret->type == MONO_TYPE_R8) {
2590                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2591                 return;
2592         }
2593
2594         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2595 }
2596
2597 #endif /* DISABLE_JIT */
2598
2599 #define EMIT_COND_BRANCH(ins,cond,sign) \
2600         if (ins->inst_true_bb->native_offset) { \
2601                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2602         } else { \
2603                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2604                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2605             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2606                         x86_branch8 (code, cond, 0, sign); \
2607                 else \
2608                         x86_branch32 (code, cond, 0, sign); \
2609 }
2610
2611 typedef struct {
2612         MonoMethodSignature *sig;
2613         CallInfo *cinfo;
2614 } ArchDynCallInfo;
2615
2616 typedef struct {
2617         mgreg_t regs [PARAM_REGS];
2618         mgreg_t res;
2619         guint8 *ret;
2620 } DynCallArgs;
2621
2622 static gboolean
2623 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2624 {
2625         int i;
2626
2627 #ifdef HOST_WIN32
2628         return FALSE;
2629 #endif
2630
2631         switch (cinfo->ret.storage) {
2632         case ArgNone:
2633         case ArgInIReg:
2634                 break;
2635         case ArgValuetypeInReg: {
2636                 ArgInfo *ainfo = &cinfo->ret;
2637
2638                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2639                         return FALSE;
2640                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2641                         return FALSE;
2642                 break;
2643         }
2644         default:
2645                 return FALSE;
2646         }
2647
2648         for (i = 0; i < cinfo->nargs; ++i) {
2649                 ArgInfo *ainfo = &cinfo->args [i];
2650                 switch (ainfo->storage) {
2651                 case ArgInIReg:
2652                         break;
2653                 case ArgValuetypeInReg:
2654                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2655                                 return FALSE;
2656                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2657                                 return FALSE;
2658                         break;
2659                 default:
2660                         return FALSE;
2661                 }
2662         }
2663
2664         return TRUE;
2665 }
2666
2667 /*
2668  * mono_arch_dyn_call_prepare:
2669  *
2670  *   Return a pointer to an arch-specific structure which contains information
2671  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2672  * supported for SIG.
2673  * This function is equivalent to ffi_prep_cif in libffi.
2674  */
2675 MonoDynCallInfo*
2676 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2677 {
2678         ArchDynCallInfo *info;
2679         CallInfo *cinfo;
2680
2681         cinfo = get_call_info (NULL, NULL, sig);
2682
2683         if (!dyn_call_supported (sig, cinfo)) {
2684                 g_free (cinfo);
2685                 return NULL;
2686         }
2687
2688         info = g_new0 (ArchDynCallInfo, 1);
2689         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2690         info->sig = sig;
2691         info->cinfo = cinfo;
2692
2693         return (MonoDynCallInfo*)info;
2694 }
2695
2696 /*
2697  * mono_arch_dyn_call_free:
2698  *
2699  *   Free a MonoDynCallInfo structure.
2700  */
2701 void
2702 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2703 {
2704         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2705
2706         g_free (ainfo->cinfo);
2707         g_free (ainfo);
2708 }
2709
2710 #if !defined(__native_client__)
2711 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2712 #define GREG_TO_PTR(greg) (gpointer)(greg)
2713 #else
2714 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2715 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2716 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2717 #endif
2718
2719 /*
2720  * mono_arch_get_start_dyn_call:
2721  *
2722  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2723  * store the result into BUF.
2724  * ARGS should be an array of pointers pointing to the arguments.
2725  * RET should point to a memory buffer large enought to hold the result of the
2726  * call.
2727  * This function should be as fast as possible, any work which does not depend
2728  * on the actual values of the arguments should be done in
2729  * mono_arch_dyn_call_prepare ().
2730  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2731  * libffi.
2732  */
2733 void
2734 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2735 {
2736         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2737         DynCallArgs *p = (DynCallArgs*)buf;
2738         int arg_index, greg, i, pindex;
2739         MonoMethodSignature *sig = dinfo->sig;
2740
2741         g_assert (buf_len >= sizeof (DynCallArgs));
2742
2743         p->res = 0;
2744         p->ret = ret;
2745
2746         arg_index = 0;
2747         greg = 0;
2748         pindex = 0;
2749
2750         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2751                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2752                 if (!sig->hasthis)
2753                         pindex = 1;
2754         }
2755
2756         if (dinfo->cinfo->vtype_retaddr)
2757                 p->regs [greg ++] = PTR_TO_GREG(ret);
2758
2759         for (i = pindex; i < sig->param_count; i++) {
2760                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2761                 gpointer *arg = args [arg_index ++];
2762
2763                 if (t->byref) {
2764                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2765                         continue;
2766                 }
2767
2768                 switch (t->type) {
2769                 case MONO_TYPE_STRING:
2770                 case MONO_TYPE_CLASS:
2771                 case MONO_TYPE_ARRAY:
2772                 case MONO_TYPE_SZARRAY:
2773                 case MONO_TYPE_OBJECT:
2774                 case MONO_TYPE_PTR:
2775                 case MONO_TYPE_I:
2776                 case MONO_TYPE_U:
2777 #if !defined(__mono_ilp32__)
2778                 case MONO_TYPE_I8:
2779                 case MONO_TYPE_U8:
2780 #endif
2781                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2782                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2783                         break;
2784 #if defined(__mono_ilp32__)
2785                 case MONO_TYPE_I8:
2786                 case MONO_TYPE_U8:
2787                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2788                         p->regs [greg ++] = *(guint64*)(arg);
2789                         break;
2790 #endif
2791                 case MONO_TYPE_BOOLEAN:
2792                 case MONO_TYPE_U1:
2793                         p->regs [greg ++] = *(guint8*)(arg);
2794                         break;
2795                 case MONO_TYPE_I1:
2796                         p->regs [greg ++] = *(gint8*)(arg);
2797                         break;
2798                 case MONO_TYPE_I2:
2799                         p->regs [greg ++] = *(gint16*)(arg);
2800                         break;
2801                 case MONO_TYPE_U2:
2802                 case MONO_TYPE_CHAR:
2803                         p->regs [greg ++] = *(guint16*)(arg);
2804                         break;
2805                 case MONO_TYPE_I4:
2806                         p->regs [greg ++] = *(gint32*)(arg);
2807                         break;
2808                 case MONO_TYPE_U4:
2809                         p->regs [greg ++] = *(guint32*)(arg);
2810                         break;
2811                 case MONO_TYPE_GENERICINST:
2812                     if (MONO_TYPE_IS_REFERENCE (t)) {
2813                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2814                                 break;
2815                         } else {
2816                                 /* Fall through */
2817                         }
2818                 case MONO_TYPE_VALUETYPE: {
2819                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2820
2821                         g_assert (ainfo->storage == ArgValuetypeInReg);
2822                         if (ainfo->pair_storage [0] != ArgNone) {
2823                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2824                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2825                         }
2826                         if (ainfo->pair_storage [1] != ArgNone) {
2827                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2828                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2829                         }
2830                         break;
2831                 }
2832                 default:
2833                         g_assert_not_reached ();
2834                 }
2835         }
2836
2837         g_assert (greg <= PARAM_REGS);
2838 }
2839
2840 /*
2841  * mono_arch_finish_dyn_call:
2842  *
2843  *   Store the result of a dyn call into the return value buffer passed to
2844  * start_dyn_call ().
2845  * This function should be as fast as possible, any work which does not depend
2846  * on the actual values of the arguments should be done in
2847  * mono_arch_dyn_call_prepare ().
2848  */
2849 void
2850 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2851 {
2852         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2853         MonoMethodSignature *sig = dinfo->sig;
2854         guint8 *ret = ((DynCallArgs*)buf)->ret;
2855         mgreg_t res = ((DynCallArgs*)buf)->res;
2856         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2857
2858         switch (sig_ret->type) {
2859         case MONO_TYPE_VOID:
2860                 *(gpointer*)ret = NULL;
2861                 break;
2862         case MONO_TYPE_STRING:
2863         case MONO_TYPE_CLASS:
2864         case MONO_TYPE_ARRAY:
2865         case MONO_TYPE_SZARRAY:
2866         case MONO_TYPE_OBJECT:
2867         case MONO_TYPE_I:
2868         case MONO_TYPE_U:
2869         case MONO_TYPE_PTR:
2870                 *(gpointer*)ret = GREG_TO_PTR(res);
2871                 break;
2872         case MONO_TYPE_I1:
2873                 *(gint8*)ret = res;
2874                 break;
2875         case MONO_TYPE_U1:
2876         case MONO_TYPE_BOOLEAN:
2877                 *(guint8*)ret = res;
2878                 break;
2879         case MONO_TYPE_I2:
2880                 *(gint16*)ret = res;
2881                 break;
2882         case MONO_TYPE_U2:
2883         case MONO_TYPE_CHAR:
2884                 *(guint16*)ret = res;
2885                 break;
2886         case MONO_TYPE_I4:
2887                 *(gint32*)ret = res;
2888                 break;
2889         case MONO_TYPE_U4:
2890                 *(guint32*)ret = res;
2891                 break;
2892         case MONO_TYPE_I8:
2893                 *(gint64*)ret = res;
2894                 break;
2895         case MONO_TYPE_U8:
2896                 *(guint64*)ret = res;
2897                 break;
2898         case MONO_TYPE_GENERICINST:
2899                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2900                         *(gpointer*)ret = GREG_TO_PTR(res);
2901                         break;
2902                 } else {
2903                         /* Fall through */
2904                 }
2905         case MONO_TYPE_VALUETYPE:
2906                 if (dinfo->cinfo->vtype_retaddr) {
2907                         /* Nothing to do */
2908                 } else {
2909                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2910
2911                         g_assert (ainfo->storage == ArgValuetypeInReg);
2912
2913                         if (ainfo->pair_storage [0] != ArgNone) {
2914                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2915                                 ((mgreg_t*)ret)[0] = res;
2916                         }
2917
2918                         g_assert (ainfo->pair_storage [1] == ArgNone);
2919                 }
2920                 break;
2921         default:
2922                 g_assert_not_reached ();
2923         }
2924 }
2925
2926 /* emit an exception if condition is fail */
2927 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2928         do {                                                        \
2929                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2930                 if (tins == NULL) {                                                                             \
2931                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2932                                         MONO_PATCH_INFO_EXC, exc_name);  \
2933                         x86_branch32 (code, cond, 0, signed);               \
2934                 } else {        \
2935                         EMIT_COND_BRANCH (tins, cond, signed);  \
2936                 }                       \
2937         } while (0);
2938
2939 #define EMIT_FPCOMPARE(code) do { \
2940         amd64_fcompp (code); \
2941         amd64_fnstsw (code); \
2942 } while (0);
2943
2944 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2945     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2946         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2947         amd64_ ##op (code); \
2948         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2949         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2950 } while (0);
2951
2952 static guint8*
2953 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2954 {
2955         gboolean no_patch = FALSE;
2956
2957         /*
2958          * FIXME: Add support for thunks
2959          */
2960         {
2961                 gboolean near_call = FALSE;
2962
2963                 /*
2964                  * Indirect calls are expensive so try to make a near call if possible.
2965                  * The caller memory is allocated by the code manager so it is
2966                  * guaranteed to be at a 32 bit offset.
2967                  */
2968
2969                 if (patch_type != MONO_PATCH_INFO_ABS) {
2970                         /* The target is in memory allocated using the code manager */
2971                         near_call = TRUE;
2972
2973                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2974                                 if (((MonoMethod*)data)->klass->image->aot_module)
2975                                         /* The callee might be an AOT method */
2976                                         near_call = FALSE;
2977                                 if (((MonoMethod*)data)->dynamic)
2978                                         /* The target is in malloc-ed memory */
2979                                         near_call = FALSE;
2980                         }
2981
2982                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2983                                 /*
2984                                  * The call might go directly to a native function without
2985                                  * the wrapper.
2986                                  */
2987                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2988                                 if (mi) {
2989                                         gconstpointer target = mono_icall_get_wrapper (mi);
2990                                         if ((((guint64)target) >> 32) != 0)
2991                                                 near_call = FALSE;
2992                                 }
2993                         }
2994                 }
2995                 else {
2996                         MonoJumpInfo *jinfo = NULL;
2997
2998                         if (cfg->abs_patches)
2999                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
3000                         if (jinfo) {
3001                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3002                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3003                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3004                                                 near_call = TRUE;
3005                                         no_patch = TRUE;
3006                                 } else {
3007                                         /*
3008                                          * This is not really an optimization, but required because the
3009                                          * generic class init trampolines use R11 to pass the vtable.
3010                                          */
3011                                         near_call = TRUE;
3012                                 }
3013                         } else {
3014                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3015                                 if (info) {
3016                                         if (info->func == info->wrapper) {
3017                                                 /* No wrapper */
3018                                                 if ((((guint64)info->func) >> 32) == 0)
3019                                                         near_call = TRUE;
3020                                         }
3021                                         else {
3022                                                 /* See the comment in mono_codegen () */
3023                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3024                                                         near_call = TRUE;
3025                                         }
3026                                 }
3027                                 else if ((((guint64)data) >> 32) == 0) {
3028                                         near_call = TRUE;
3029                                         no_patch = TRUE;
3030                                 }
3031                         }
3032                 }
3033
3034                 if (cfg->method->dynamic)
3035                         /* These methods are allocated using malloc */
3036                         near_call = FALSE;
3037
3038 #ifdef MONO_ARCH_NOMAP32BIT
3039                 near_call = FALSE;
3040 #endif
3041 #if defined(__native_client__)
3042                 /* Always use near_call == TRUE for Native Client */
3043                 near_call = TRUE;
3044 #endif
3045                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3046                 if (optimize_for_xen)
3047                         near_call = FALSE;
3048
3049                 if (cfg->compile_aot) {
3050                         near_call = TRUE;
3051                         no_patch = TRUE;
3052                 }
3053
3054                 if (near_call) {
3055                         /*
3056                          * Align the call displacement to an address divisible by 4 so it does
3057                          * not span cache lines. This is required for code patching to work on SMP
3058                          * systems.
3059                          */
3060                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3061                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3062                                 amd64_padding (code, pad_size);
3063                         }
3064                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3065                         amd64_call_code (code, 0);
3066                 }
3067                 else {
3068                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3069                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3070                         amd64_call_reg (code, GP_SCRATCH_REG);
3071                 }
3072         }
3073
3074         return code;
3075 }
3076
3077 static inline guint8*
3078 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3079 {
3080 #ifdef HOST_WIN32
3081         if (win64_adjust_stack)
3082                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3083 #endif
3084         code = emit_call_body (cfg, code, patch_type, data);
3085 #ifdef HOST_WIN32
3086         if (win64_adjust_stack)
3087                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3088 #endif
3089
3090         return code;
3091 }
3092
3093 static inline int
3094 store_membase_imm_to_store_membase_reg (int opcode)
3095 {
3096         switch (opcode) {
3097         case OP_STORE_MEMBASE_IMM:
3098                 return OP_STORE_MEMBASE_REG;
3099         case OP_STOREI4_MEMBASE_IMM:
3100                 return OP_STOREI4_MEMBASE_REG;
3101         case OP_STOREI8_MEMBASE_IMM:
3102                 return OP_STOREI8_MEMBASE_REG;
3103         }
3104
3105         return -1;
3106 }
3107
3108 #ifndef DISABLE_JIT
3109
3110 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3111
3112 /*
3113  * mono_arch_peephole_pass_1:
3114  *
3115  *   Perform peephole opts which should/can be performed before local regalloc
3116  */
3117 void
3118 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3119 {
3120         MonoInst *ins, *n;
3121
3122         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3123                 MonoInst *last_ins = ins->prev;
3124
3125                 switch (ins->opcode) {
3126                 case OP_ADD_IMM:
3127                 case OP_IADD_IMM:
3128                 case OP_LADD_IMM:
3129                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3130                                 /*
3131                                  * X86_LEA is like ADD, but doesn't have the
3132                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3133                                  * its operand to 64 bit.
3134                                  */
3135                                 ins->opcode = OP_X86_LEA_MEMBASE;
3136                                 ins->inst_basereg = ins->sreg1;
3137                         }
3138                         break;
3139                 case OP_LXOR:
3140                 case OP_IXOR:
3141                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3142                                 MonoInst *ins2;
3143
3144                                 /*
3145                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3146                                  * the latter has length 2-3 instead of 6 (reverse constant
3147                                  * propagation). These instruction sequences are very common
3148                                  * in the initlocals bblock.
3149                                  */
3150                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3151                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3152                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3153                                                 ins2->sreg1 = ins->dreg;
3154                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3155                                                 /* Continue */
3156                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3157                                                 NULLIFY_INS (ins2);
3158                                                 /* Continue */
3159                                         } else {
3160                                                 break;
3161                                         }
3162                                 }
3163                         }
3164                         break;
3165                 case OP_COMPARE_IMM:
3166                 case OP_LCOMPARE_IMM:
3167                         /* OP_COMPARE_IMM (reg, 0)
3168                          * -->
3169                          * OP_AMD64_TEST_NULL (reg)
3170                          */
3171                         if (!ins->inst_imm)
3172                                 ins->opcode = OP_AMD64_TEST_NULL;
3173                         break;
3174                 case OP_ICOMPARE_IMM:
3175                         if (!ins->inst_imm)
3176                                 ins->opcode = OP_X86_TEST_NULL;
3177                         break;
3178                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3179                         /*
3180                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3181                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3182                          * -->
3183                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3184                          * OP_COMPARE_IMM reg, imm
3185                          *
3186                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3187                          */
3188                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3189                             ins->inst_basereg == last_ins->inst_destbasereg &&
3190                             ins->inst_offset == last_ins->inst_offset) {
3191                                         ins->opcode = OP_ICOMPARE_IMM;
3192                                         ins->sreg1 = last_ins->sreg1;
3193
3194                                         /* check if we can remove cmp reg,0 with test null */
3195                                         if (!ins->inst_imm)
3196                                                 ins->opcode = OP_X86_TEST_NULL;
3197                                 }
3198
3199                         break;
3200                 }
3201
3202                 mono_peephole_ins (bb, ins);
3203         }
3204 }
3205
3206 void
3207 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3208 {
3209         MonoInst *ins, *n;
3210
3211         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3212                 switch (ins->opcode) {
3213                 case OP_ICONST:
3214                 case OP_I8CONST: {
3215                         /* reg = 0 -> XOR (reg, reg) */
3216                         /* XOR sets cflags on x86, so we cant do it always */
3217                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3218                                 ins->opcode = OP_LXOR;
3219                                 ins->sreg1 = ins->dreg;
3220                                 ins->sreg2 = ins->dreg;
3221                                 /* Fall through */
3222                         } else {
3223                                 break;
3224                         }
3225                 }
3226                 case OP_LXOR:
3227                         /*
3228                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3229                          * 0 result into 64 bits.
3230                          */
3231                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3232                                 ins->opcode = OP_IXOR;
3233                         }
3234                         /* Fall through */
3235                 case OP_IXOR:
3236                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3237                                 MonoInst *ins2;
3238
3239                                 /*
3240                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3241                                  * the latter has length 2-3 instead of 6 (reverse constant
3242                                  * propagation). These instruction sequences are very common
3243                                  * in the initlocals bblock.
3244                                  */
3245                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3246                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3247                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3248                                                 ins2->sreg1 = ins->dreg;
3249                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3250                                                 /* Continue */
3251                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3252                                                 NULLIFY_INS (ins2);
3253                                                 /* Continue */
3254                                         } else {
3255                                                 break;
3256                                         }
3257                                 }
3258                         }
3259                         break;
3260                 case OP_IADD_IMM:
3261                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3262                                 ins->opcode = OP_X86_INC_REG;
3263                         break;
3264                 case OP_ISUB_IMM:
3265                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3266                                 ins->opcode = OP_X86_DEC_REG;
3267                         break;
3268                 }
3269
3270                 mono_peephole_ins (bb, ins);
3271         }
3272 }
3273
3274 #define NEW_INS(cfg,ins,dest,op) do {   \
3275                 MONO_INST_NEW ((cfg), (dest), (op)); \
3276         (dest)->cil_code = (ins)->cil_code; \
3277         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3278         } while (0)
3279
3280 /*
3281  * mono_arch_lowering_pass:
3282  *
3283  *  Converts complex opcodes into simpler ones so that each IR instruction
3284  * corresponds to one machine instruction.
3285  */
3286 void
3287 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3288 {
3289         MonoInst *ins, *n, *temp;
3290
3291         /*
3292          * FIXME: Need to add more instructions, but the current machine
3293          * description can't model some parts of the composite instructions like
3294          * cdq.
3295          */
3296         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3297                 switch (ins->opcode) {
3298                 case OP_DIV_IMM:
3299                 case OP_REM_IMM:
3300                 case OP_IDIV_IMM:
3301                 case OP_IDIV_UN_IMM:
3302                 case OP_IREM_UN_IMM:
3303                         mono_decompose_op_imm (cfg, bb, ins);
3304                         break;
3305                 case OP_IREM_IMM:
3306                         /* Keep the opcode if we can implement it efficiently */
3307                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
3308                                 mono_decompose_op_imm (cfg, bb, ins);
3309                         break;
3310                 case OP_COMPARE_IMM:
3311                 case OP_LCOMPARE_IMM:
3312                         if (!amd64_is_imm32 (ins->inst_imm)) {
3313                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3314                                 temp->inst_c0 = ins->inst_imm;
3315                                 temp->dreg = mono_alloc_ireg (cfg);
3316                                 ins->opcode = OP_COMPARE;
3317                                 ins->sreg2 = temp->dreg;
3318                         }
3319                         break;
3320 #ifndef __mono_ilp32__
3321                 case OP_LOAD_MEMBASE:
3322 #endif
3323                 case OP_LOADI8_MEMBASE:
3324 #ifndef __native_client_codegen__
3325                 /*  Don't generate memindex opcodes (to simplify */
3326                 /*  read sandboxing) */
3327                         if (!amd64_is_imm32 (ins->inst_offset)) {
3328                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3329                                 temp->inst_c0 = ins->inst_offset;
3330                                 temp->dreg = mono_alloc_ireg (cfg);
3331                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3332                                 ins->inst_indexreg = temp->dreg;
3333                         }
3334 #endif
3335                         break;
3336 #ifndef __mono_ilp32__
3337                 case OP_STORE_MEMBASE_IMM:
3338 #endif
3339                 case OP_STOREI8_MEMBASE_IMM:
3340                         if (!amd64_is_imm32 (ins->inst_imm)) {
3341                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3342                                 temp->inst_c0 = ins->inst_imm;
3343                                 temp->dreg = mono_alloc_ireg (cfg);
3344                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3345                                 ins->sreg1 = temp->dreg;
3346                         }
3347                         break;
3348 #ifdef MONO_ARCH_SIMD_INTRINSICS
3349                 case OP_EXPAND_I1: {
3350                                 int temp_reg1 = mono_alloc_ireg (cfg);
3351                                 int temp_reg2 = mono_alloc_ireg (cfg);
3352                                 int original_reg = ins->sreg1;
3353
3354                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3355                                 temp->sreg1 = original_reg;
3356                                 temp->dreg = temp_reg1;
3357
3358                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3359                                 temp->sreg1 = temp_reg1;
3360                                 temp->dreg = temp_reg2;
3361                                 temp->inst_imm = 8;
3362
3363                                 NEW_INS (cfg, ins, temp, OP_LOR);
3364                                 temp->sreg1 = temp->dreg = temp_reg2;
3365                                 temp->sreg2 = temp_reg1;
3366
3367                                 ins->opcode = OP_EXPAND_I2;
3368                                 ins->sreg1 = temp_reg2;
3369                         }
3370                         break;
3371 #endif
3372                 default:
3373                         break;
3374                 }
3375         }
3376
3377         bb->max_vreg = cfg->next_vreg;
3378 }
3379
3380 static const int
3381 branch_cc_table [] = {
3382         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3383         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3384         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3385 };
3386
3387 /* Maps CMP_... constants to X86_CC_... constants */
3388 static const int
3389 cc_table [] = {
3390         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3391         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3392 };
3393
3394 static const int
3395 cc_signed_table [] = {
3396         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3397         FALSE, FALSE, FALSE, FALSE
3398 };
3399
3400 /*#include "cprop.c"*/
3401
3402 static unsigned char*
3403 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3404 {
3405         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3406
3407         if (size == 1)
3408                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3409         else if (size == 2)
3410                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3411         return code;
3412 }
3413
3414 static unsigned char*
3415 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3416 {
3417         int sreg = tree->sreg1;
3418         int need_touch = FALSE;
3419
3420 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3421         if (!tree->flags & MONO_INST_INIT)
3422                 need_touch = TRUE;
3423 #endif
3424
3425         if (need_touch) {
3426                 guint8* br[5];
3427
3428                 /*
3429                  * Under Windows:
3430                  * If requested stack size is larger than one page,
3431                  * perform stack-touch operation
3432                  */
3433                 /*
3434                  * Generate stack probe code.
3435                  * Under Windows, it is necessary to allocate one page at a time,
3436                  * "touching" stack after each successful sub-allocation. This is
3437                  * because of the way stack growth is implemented - there is a
3438                  * guard page before the lowest stack page that is currently commited.
3439                  * Stack normally grows sequentially so OS traps access to the
3440                  * guard page and commits more pages when needed.
3441                  */
3442                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3443                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3444
3445                 br[2] = code; /* loop */
3446                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3447                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3448                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3449                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3450                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3451                 amd64_patch (br[3], br[2]);
3452                 amd64_test_reg_reg (code, sreg, sreg);
3453                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3454                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3455
3456                 br[1] = code; x86_jump8 (code, 0);
3457
3458                 amd64_patch (br[0], code);
3459                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3460                 amd64_patch (br[1], code);
3461                 amd64_patch (br[4], code);
3462         }
3463         else
3464                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3465
3466         if (tree->flags & MONO_INST_INIT) {
3467                 int offset = 0;
3468                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3469                         amd64_push_reg (code, AMD64_RAX);
3470                         offset += 8;
3471                 }
3472                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3473                         amd64_push_reg (code, AMD64_RCX);
3474                         offset += 8;
3475                 }
3476                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3477                         amd64_push_reg (code, AMD64_RDI);
3478                         offset += 8;
3479                 }
3480
3481                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3482                 if (sreg != AMD64_RCX)
3483                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3484                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3485
3486                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3487                 if (cfg->param_area && cfg->arch.no_pushes)
3488                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3489                 amd64_cld (code);
3490 #if defined(__default_codegen__)
3491                 amd64_prefix (code, X86_REP_PREFIX);
3492                 amd64_stosl (code);
3493 #elif defined(__native_client_codegen__)
3494                 /* NaCl stos pseudo-instruction */
3495                 amd64_codegen_pre(code);
3496                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3497                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3498                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3499                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3500                 amd64_prefix (code, X86_REP_PREFIX);
3501                 amd64_stosl (code);
3502                 amd64_codegen_post(code);
3503 #endif /* __native_client_codegen__ */
3504
3505                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3506                         amd64_pop_reg (code, AMD64_RDI);
3507                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3508                         amd64_pop_reg (code, AMD64_RCX);
3509                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3510                         amd64_pop_reg (code, AMD64_RAX);
3511         }
3512         return code;
3513 }
3514
3515 static guint8*
3516 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3517 {
3518         CallInfo *cinfo;
3519         guint32 quad;
3520
3521         /* Move return value to the target register */
3522         /* FIXME: do this in the local reg allocator */
3523         switch (ins->opcode) {
3524         case OP_CALL:
3525         case OP_CALL_REG:
3526         case OP_CALL_MEMBASE:
3527         case OP_LCALL:
3528         case OP_LCALL_REG:
3529         case OP_LCALL_MEMBASE:
3530                 g_assert (ins->dreg == AMD64_RAX);
3531                 break;
3532         case OP_FCALL:
3533         case OP_FCALL_REG:
3534         case OP_FCALL_MEMBASE:
3535                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3536                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3537                 }
3538                 else {
3539                         if (ins->dreg != AMD64_XMM0)
3540                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3541                 }
3542                 break;
3543         case OP_VCALL:
3544         case OP_VCALL_REG:
3545         case OP_VCALL_MEMBASE:
3546         case OP_VCALL2:
3547         case OP_VCALL2_REG:
3548         case OP_VCALL2_MEMBASE:
3549                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3550                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3551                         MonoInst *loc = cfg->arch.vret_addr_loc;
3552
3553                         /* Load the destination address */
3554                         g_assert (loc->opcode == OP_REGOFFSET);
3555                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3556
3557                         for (quad = 0; quad < 2; quad ++) {
3558                                 switch (cinfo->ret.pair_storage [quad]) {
3559                                 case ArgInIReg:
3560                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3561                                         break;
3562                                 case ArgInFloatSSEReg:
3563                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3564                                         break;
3565                                 case ArgInDoubleSSEReg:
3566                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3567                                         break;
3568                                 case ArgNone:
3569                                         break;
3570                                 default:
3571                                         NOT_IMPLEMENTED;
3572                                 }
3573                         }
3574                 }
3575                 break;
3576         }
3577
3578         return code;
3579 }
3580
3581 #endif /* DISABLE_JIT */
3582
3583 #ifdef __APPLE__
3584 static int tls_gs_offset;
3585 #endif
3586
3587 gboolean
3588 mono_amd64_have_tls_get (void)
3589 {
3590 #ifdef __APPLE__
3591         static gboolean have_tls_get = FALSE;
3592         static gboolean inited = FALSE;
3593         guint8 *ins;
3594
3595         if (inited)
3596                 return have_tls_get;
3597
3598         ins = (guint8*)pthread_getspecific;
3599
3600         /*
3601          * We're looking for these two instructions:
3602          *
3603          * mov    %gs:[offset](,%rdi,8),%rax
3604          * retq
3605          */
3606         have_tls_get = ins [0] == 0x65 &&
3607                        ins [1] == 0x48 &&
3608                        ins [2] == 0x8b &&
3609                        ins [3] == 0x04 &&
3610                        ins [4] == 0xfd &&
3611                        ins [6] == 0x00 &&
3612                        ins [7] == 0x00 &&
3613                        ins [8] == 0x00 &&
3614                        ins [9] == 0xc3;
3615
3616         inited = TRUE;
3617
3618         tls_gs_offset = ins[5];
3619
3620         return have_tls_get;
3621 #else
3622         return TRUE;
3623 #endif
3624 }
3625
3626 int
3627 mono_amd64_get_tls_gs_offset (void)
3628 {
3629 #ifdef TARGET_OSX
3630         return tls_gs_offset;
3631 #else
3632         g_assert_not_reached ();
3633         return -1;
3634 #endif
3635 }
3636
3637 /*
3638  * mono_amd64_emit_tls_get:
3639  * @code: buffer to store code to
3640  * @dreg: hard register where to place the result
3641  * @tls_offset: offset info
3642  *
3643  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3644  * the dreg register the item in the thread local storage identified
3645  * by tls_offset.
3646  *
3647  * Returns: a pointer to the end of the stored code
3648  */
3649 guint8*
3650 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3651 {
3652 #ifdef HOST_WIN32
3653         g_assert (tls_offset < 64);
3654         x86_prefix (code, X86_GS_PREFIX);
3655         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3656 #elif defined(__APPLE__)
3657         x86_prefix (code, X86_GS_PREFIX);
3658         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3659 #else
3660         if (optimize_for_xen) {
3661                 x86_prefix (code, X86_FS_PREFIX);
3662                 amd64_mov_reg_mem (code, dreg, 0, 8);
3663                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3664         } else {
3665                 x86_prefix (code, X86_FS_PREFIX);
3666                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3667         }
3668 #endif
3669         return code;
3670 }
3671
3672 static guint8*
3673 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3674 {
3675         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3676 #ifdef TARGET_OSX
3677         if (dreg != offset_reg)
3678                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3679         amd64_prefix (code, X86_GS_PREFIX);
3680         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3681 #elif defined(__linux__)
3682         int tmpreg = -1;
3683
3684         if (dreg == offset_reg) {
3685                 /* Use a temporary reg by saving it to the redzone */
3686                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3687                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3688                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3689                 offset_reg = tmpreg;
3690         }
3691         x86_prefix (code, X86_FS_PREFIX);
3692         amd64_mov_reg_mem (code, dreg, 0, 8);
3693         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3694         if (tmpreg != -1)
3695                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3696 #else
3697         g_assert_not_reached ();
3698 #endif
3699         return code;
3700 }
3701
3702 static guint8*
3703 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3704 {
3705 #ifdef HOST_WIN32
3706         g_assert_not_reached ();
3707 #elif defined(__APPLE__)
3708         x86_prefix (code, X86_GS_PREFIX);
3709         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3710 #else
3711         g_assert (!optimize_for_xen);
3712         x86_prefix (code, X86_FS_PREFIX);
3713         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3714 #endif
3715         return code;
3716 }
3717
3718 static guint8*
3719 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3720 {
3721         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3722 #ifdef HOST_WIN32
3723         g_assert_not_reached ();
3724 #elif defined(__APPLE__)
3725         x86_prefix (code, X86_GS_PREFIX);
3726         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3727 #else
3728         x86_prefix (code, X86_FS_PREFIX);
3729         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3730 #endif
3731         return code;
3732 }
3733
3734  /*
3735  * mono_arch_translate_tls_offset:
3736  *
3737  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3738  */
3739 int
3740 mono_arch_translate_tls_offset (int offset)
3741 {
3742 #ifdef __APPLE__
3743         return tls_gs_offset + (offset * 8);
3744 #else
3745         return offset;
3746 #endif
3747 }
3748
3749 /*
3750  * emit_setup_lmf:
3751  *
3752  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3753  */
3754 static guint8*
3755 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3756 {
3757         int i;
3758
3759         /*
3760          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3761          */
3762         /*
3763          * sp is saved right before calls but we need to save it here too so
3764          * async stack walks would work.
3765          */
3766         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3767         /* Skip method (only needed for trampoline LMF frames) */
3768         /* Save callee saved regs */
3769         for (i = 0; i < MONO_MAX_IREGS; ++i) {
3770                 int offset;
3771
3772                 switch (i) {
3773                 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
3774                 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
3775                 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
3776                 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
3777                 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
3778 #ifndef __native_client_codegen__
3779                 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
3780 #endif
3781 #ifdef HOST_WIN32
3782                 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
3783                 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
3784 #endif
3785                 default:
3786                         offset = -1;
3787                         break;
3788                 }
3789
3790                 if (offset != -1) {
3791                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
3792                         if ((cfg->arch.omit_fp || (i != AMD64_RBP)) && cfa_offset != -1)
3793                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
3794                 }
3795         }
3796
3797         /* These can't contain refs */
3798         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3799 #ifdef HOST_WIN32
3800         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3801 #endif
3802         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3803         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3804
3805         /* These are handled automatically by the stack marking code */
3806         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), SLOT_NOREF);
3807         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3808         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), SLOT_NOREF);
3809         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), SLOT_NOREF);
3810         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), SLOT_NOREF);
3811         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), SLOT_NOREF);
3812 #ifdef HOST_WIN32
3813         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), SLOT_NOREF);
3814         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), SLOT_NOREF);
3815 #endif
3816
3817         return code;
3818 }
3819
3820 #ifdef HOST_WIN32
3821 /*
3822  * emit_push_lmf:
3823  *
3824  *   Emit code to push an LMF structure on the LMF stack.
3825  */
3826 static guint8*
3827 emit_push_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, gboolean *args_clobbered)
3828 {
3829         if (jit_tls_offset != -1) {
3830                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, jit_tls_offset);
3831                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
3832         } else {
3833                 /*
3834                  * The call might clobber argument registers, but they are already
3835                  * saved to the stack/global regs.
3836                  */
3837                 if (args_clobbered)
3838                         *args_clobbered = TRUE;
3839                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3840                                                   (gpointer)"mono_get_lmf_addr", TRUE);
3841         }
3842
3843         /* Save lmf_addr */
3844         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3845         /* Save previous_lmf */
3846         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
3847         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3848         /* Set new lmf */
3849         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3850         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
3851
3852         return code;
3853 }
3854 #endif
3855
3856 #ifdef HOST_WIN32
3857 /*
3858  * emit_pop_lmf:
3859  *
3860  *   Emit code to pop an LMF structure from the LMF stack.
3861  */
3862 static guint8*
3863 emit_pop_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
3864 {
3865         /* Restore previous lmf */
3866         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3867         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3868         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
3869
3870         return code;
3871 }
3872 #endif
3873
3874 #define REAL_PRINT_REG(text,reg) \
3875 mono_assert (reg >= 0); \
3876 amd64_push_reg (code, AMD64_RAX); \
3877 amd64_push_reg (code, AMD64_RDX); \
3878 amd64_push_reg (code, AMD64_RCX); \
3879 amd64_push_reg (code, reg); \
3880 amd64_push_imm (code, reg); \
3881 amd64_push_imm (code, text " %d %p\n"); \
3882 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3883 amd64_call_reg (code, AMD64_RAX); \
3884 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3885 amd64_pop_reg (code, AMD64_RCX); \
3886 amd64_pop_reg (code, AMD64_RDX); \
3887 amd64_pop_reg (code, AMD64_RAX);
3888
3889 /* benchmark and set based on cpu */
3890 #define LOOP_ALIGNMENT 8
3891 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3892
3893 #ifndef DISABLE_JIT
3894 void
3895 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3896 {
3897         MonoInst *ins;
3898         MonoCallInst *call;
3899         guint offset;
3900         guint8 *code = cfg->native_code + cfg->code_len;
3901         MonoInst *last_ins = NULL;
3902         guint last_offset = 0;
3903         int max_len;
3904
3905         /* Fix max_offset estimate for each successor bb */
3906         if (cfg->opt & MONO_OPT_BRANCH) {
3907                 int current_offset = cfg->code_len;
3908                 MonoBasicBlock *current_bb;
3909                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3910                         current_bb->max_offset = current_offset;
3911                         current_offset += current_bb->max_length;
3912                 }
3913         }
3914
3915         if (cfg->opt & MONO_OPT_LOOP) {
3916                 int pad, align = LOOP_ALIGNMENT;
3917                 /* set alignment depending on cpu */
3918                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3919                         pad = align - pad;
3920                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3921                         amd64_padding (code, pad);
3922                         cfg->code_len += pad;
3923                         bb->native_offset = cfg->code_len;
3924                 }
3925         }
3926
3927 #if defined(__native_client_codegen__)
3928         /* For Native Client, all indirect call/jump targets must be */
3929         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3930         /* indirectly as well.                                       */
3931         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3932                                       (bb->flags & BB_EXCEPTION_HANDLER);
3933
3934         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3935                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3936                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3937                 cfg->code_len += pad;
3938                 bb->native_offset = cfg->code_len;
3939         }
3940 #endif  /*__native_client_codegen__*/
3941
3942         if (cfg->verbose_level > 2)
3943                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3944
3945         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3946                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3947                 g_assert (!cfg->compile_aot);
3948
3949                 cov->data [bb->dfn].cil_code = bb->cil_code;
3950                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3951                 /* this is not thread save, but good enough */
3952                 amd64_inc_membase (code, AMD64_R11, 0);
3953         }
3954
3955         offset = code - cfg->native_code;
3956
3957         mono_debug_open_block (cfg, bb, offset);
3958
3959     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3960                 x86_breakpoint (code);
3961
3962         MONO_BB_FOR_EACH_INS (bb, ins) {
3963                 offset = code - cfg->native_code;
3964
3965                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3966
3967 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3968
3969                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3970                         cfg->code_size *= 2;
3971                         cfg->native_code = mono_realloc_native_code(cfg);
3972                         code = cfg->native_code + offset;
3973                         cfg->stat_code_reallocs++;
3974                 }
3975
3976                 if (cfg->debug_info)
3977                         mono_debug_record_line_number (cfg, ins, offset);
3978
3979                 switch (ins->opcode) {
3980                 case OP_BIGMUL:
3981                         amd64_mul_reg (code, ins->sreg2, TRUE);
3982                         break;
3983                 case OP_BIGMUL_UN:
3984                         amd64_mul_reg (code, ins->sreg2, FALSE);
3985                         break;
3986                 case OP_X86_SETEQ_MEMBASE:
3987                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3988                         break;
3989                 case OP_STOREI1_MEMBASE_IMM:
3990                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3991                         break;
3992                 case OP_STOREI2_MEMBASE_IMM:
3993                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3994                         break;
3995                 case OP_STOREI4_MEMBASE_IMM:
3996                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3997                         break;
3998                 case OP_STOREI1_MEMBASE_REG:
3999                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
4000                         break;
4001                 case OP_STOREI2_MEMBASE_REG:
4002                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4003                         break;
4004                 /* In AMD64 NaCl, pointers are 4 bytes, */
4005                 /*  so STORE_* != STOREI8_*. Likewise below. */
4006                 case OP_STORE_MEMBASE_REG:
4007                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4008                         break;
4009                 case OP_STOREI8_MEMBASE_REG:
4010                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4011                         break;
4012                 case OP_STOREI4_MEMBASE_REG:
4013                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4014                         break;
4015                 case OP_STORE_MEMBASE_IMM:
4016 #ifndef __native_client_codegen__
4017                         /* In NaCl, this could be a PCONST type, which could */
4018                         /* mean a pointer type was copied directly into the  */
4019                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4020                         /* the value would be 0x00000000FFFFFFFF which is    */
4021                         /* not proper for an imm32 unless you cast it.       */
4022                         g_assert (amd64_is_imm32 (ins->inst_imm));
4023 #endif
4024                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4025                         break;
4026                 case OP_STOREI8_MEMBASE_IMM:
4027                         g_assert (amd64_is_imm32 (ins->inst_imm));
4028                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4029                         break;
4030                 case OP_LOAD_MEM:
4031 #ifdef __mono_ilp32__
4032                         /* In ILP32, pointers are 4 bytes, so separate these */
4033                         /* cases, use literal 8 below where we really want 8 */
4034                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4035                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4036                         break;
4037 #endif
4038                 case OP_LOADI8_MEM:
4039                         // FIXME: Decompose this earlier
4040                         if (amd64_is_imm32 (ins->inst_imm))
4041                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4042                         else {
4043                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4044                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4045                         }
4046                         break;
4047                 case OP_LOADI4_MEM:
4048                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4049                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4050                         break;
4051                 case OP_LOADU4_MEM:
4052                         // FIXME: Decompose this earlier
4053                         if (amd64_is_imm32 (ins->inst_imm))
4054                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4055                         else {
4056                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4057                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4058                         }
4059                         break;
4060                 case OP_LOADU1_MEM:
4061                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4062                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4063                         break;
4064                 case OP_LOADU2_MEM:
4065                         /* For NaCl, pointers are 4 bytes, so separate these */
4066                         /* cases, use literal 8 below where we really want 8 */
4067                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4068                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4069                         break;
4070                 case OP_LOAD_MEMBASE:
4071                         g_assert (amd64_is_imm32 (ins->inst_offset));
4072                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4073                         break;
4074                 case OP_LOADI8_MEMBASE:
4075                         /* Use literal 8 instead of sizeof pointer or */
4076                         /* register, we really want 8 for this opcode */
4077                         g_assert (amd64_is_imm32 (ins->inst_offset));
4078                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4079                         break;
4080                 case OP_LOADI4_MEMBASE:
4081                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4082                         break;
4083                 case OP_LOADU4_MEMBASE:
4084                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4085                         break;
4086                 case OP_LOADU1_MEMBASE:
4087                         /* The cpu zero extends the result into 64 bits */
4088                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4089                         break;
4090                 case OP_LOADI1_MEMBASE:
4091                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4092                         break;
4093                 case OP_LOADU2_MEMBASE:
4094                         /* The cpu zero extends the result into 64 bits */
4095                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4096                         break;
4097                 case OP_LOADI2_MEMBASE:
4098                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4099                         break;
4100                 case OP_AMD64_LOADI8_MEMINDEX:
4101                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4102                         break;
4103                 case OP_LCONV_TO_I1:
4104                 case OP_ICONV_TO_I1:
4105                 case OP_SEXT_I1:
4106                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4107                         break;
4108                 case OP_LCONV_TO_I2:
4109                 case OP_ICONV_TO_I2:
4110                 case OP_SEXT_I2:
4111                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4112                         break;
4113                 case OP_LCONV_TO_U1:
4114                 case OP_ICONV_TO_U1:
4115                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4116                         break;
4117                 case OP_LCONV_TO_U2:
4118                 case OP_ICONV_TO_U2:
4119                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4120                         break;
4121                 case OP_ZEXT_I4:
4122                         /* Clean out the upper word */
4123                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4124                         break;
4125                 case OP_SEXT_I4:
4126                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4127                         break;
4128                 case OP_COMPARE:
4129                 case OP_LCOMPARE:
4130                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4131                         break;
4132                 case OP_COMPARE_IMM:
4133 #if defined(__mono_ilp32__)
4134                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4135                         g_assert (amd64_is_imm32 (ins->inst_imm));
4136                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4137                         break;
4138 #endif
4139                 case OP_LCOMPARE_IMM:
4140                         g_assert (amd64_is_imm32 (ins->inst_imm));
4141                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4142                         break;
4143                 case OP_X86_COMPARE_REG_MEMBASE:
4144                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4145                         break;
4146                 case OP_X86_TEST_NULL:
4147                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4148                         break;
4149                 case OP_AMD64_TEST_NULL:
4150                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4151                         break;
4152
4153                 case OP_X86_ADD_REG_MEMBASE:
4154                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4155                         break;
4156                 case OP_X86_SUB_REG_MEMBASE:
4157                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4158                         break;
4159                 case OP_X86_AND_REG_MEMBASE:
4160                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4161                         break;
4162                 case OP_X86_OR_REG_MEMBASE:
4163                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4164                         break;
4165                 case OP_X86_XOR_REG_MEMBASE:
4166                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4167                         break;
4168
4169                 case OP_X86_ADD_MEMBASE_IMM:
4170                         /* FIXME: Make a 64 version too */
4171                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4172                         break;
4173                 case OP_X86_SUB_MEMBASE_IMM:
4174                         g_assert (amd64_is_imm32 (ins->inst_imm));
4175                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4176                         break;
4177                 case OP_X86_AND_MEMBASE_IMM:
4178                         g_assert (amd64_is_imm32 (ins->inst_imm));
4179                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4180                         break;
4181                 case OP_X86_OR_MEMBASE_IMM:
4182                         g_assert (amd64_is_imm32 (ins->inst_imm));
4183                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4184                         break;
4185                 case OP_X86_XOR_MEMBASE_IMM:
4186                         g_assert (amd64_is_imm32 (ins->inst_imm));
4187                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4188                         break;
4189                 case OP_X86_ADD_MEMBASE_REG:
4190                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4191                         break;
4192                 case OP_X86_SUB_MEMBASE_REG:
4193                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4194                         break;
4195                 case OP_X86_AND_MEMBASE_REG:
4196                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4197                         break;
4198                 case OP_X86_OR_MEMBASE_REG:
4199                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4200                         break;
4201                 case OP_X86_XOR_MEMBASE_REG:
4202                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4203                         break;
4204                 case OP_X86_INC_MEMBASE:
4205                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4206                         break;
4207                 case OP_X86_INC_REG:
4208                         amd64_inc_reg_size (code, ins->dreg, 4);
4209                         break;
4210                 case OP_X86_DEC_MEMBASE:
4211                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4212                         break;
4213                 case OP_X86_DEC_REG:
4214                         amd64_dec_reg_size (code, ins->dreg, 4);
4215                         break;
4216                 case OP_X86_MUL_REG_MEMBASE:
4217                 case OP_X86_MUL_MEMBASE_REG:
4218                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4219                         break;
4220                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4221                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4222                         break;
4223                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4224                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4225                         break;
4226                 case OP_AMD64_COMPARE_MEMBASE_REG:
4227                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4228                         break;
4229                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4230                         g_assert (amd64_is_imm32 (ins->inst_imm));
4231                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4232                         break;
4233                 case OP_X86_COMPARE_MEMBASE8_IMM:
4234                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4235                         break;
4236                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4237                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4238                         break;
4239                 case OP_AMD64_COMPARE_REG_MEMBASE:
4240                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4241                         break;
4242
4243                 case OP_AMD64_ADD_REG_MEMBASE:
4244                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4245                         break;
4246                 case OP_AMD64_SUB_REG_MEMBASE:
4247                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4248                         break;
4249                 case OP_AMD64_AND_REG_MEMBASE:
4250                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4251                         break;
4252                 case OP_AMD64_OR_REG_MEMBASE:
4253                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4254                         break;
4255                 case OP_AMD64_XOR_REG_MEMBASE:
4256                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4257                         break;
4258
4259                 case OP_AMD64_ADD_MEMBASE_REG:
4260                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4261                         break;
4262                 case OP_AMD64_SUB_MEMBASE_REG:
4263                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4264                         break;
4265                 case OP_AMD64_AND_MEMBASE_REG:
4266                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4267                         break;
4268                 case OP_AMD64_OR_MEMBASE_REG:
4269                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4270                         break;
4271                 case OP_AMD64_XOR_MEMBASE_REG:
4272                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4273                         break;
4274
4275                 case OP_AMD64_ADD_MEMBASE_IMM:
4276                         g_assert (amd64_is_imm32 (ins->inst_imm));
4277                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4278                         break;
4279                 case OP_AMD64_SUB_MEMBASE_IMM:
4280                         g_assert (amd64_is_imm32 (ins->inst_imm));
4281                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4282                         break;
4283                 case OP_AMD64_AND_MEMBASE_IMM:
4284                         g_assert (amd64_is_imm32 (ins->inst_imm));
4285                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4286                         break;
4287                 case OP_AMD64_OR_MEMBASE_IMM:
4288                         g_assert (amd64_is_imm32 (ins->inst_imm));
4289                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4290                         break;
4291                 case OP_AMD64_XOR_MEMBASE_IMM:
4292                         g_assert (amd64_is_imm32 (ins->inst_imm));
4293                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4294                         break;
4295
4296                 case OP_BREAK:
4297                         amd64_breakpoint (code);
4298                         break;
4299                 case OP_RELAXED_NOP:
4300                         x86_prefix (code, X86_REP_PREFIX);
4301                         x86_nop (code);
4302                         break;
4303                 case OP_HARD_NOP:
4304                         x86_nop (code);
4305                         break;
4306                 case OP_NOP:
4307                 case OP_DUMMY_USE:
4308                 case OP_DUMMY_STORE:
4309                 case OP_NOT_REACHED:
4310                 case OP_NOT_NULL:
4311                         break;
4312                 case OP_SEQ_POINT: {
4313                         int i;
4314
4315                         /*
4316                          * Read from the single stepping trigger page. This will cause a
4317                          * SIGSEGV when single stepping is enabled.
4318                          * We do this _before_ the breakpoint, so single stepping after
4319                          * a breakpoint is hit will step to the next IL offset.
4320                          */
4321                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4322                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4323
4324                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4325                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4326                         }
4327
4328                         /*
4329                          * This is the address which is saved in seq points,
4330                          */
4331                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4332
4333                         if (cfg->compile_aot) {
4334                                 guint32 offset = code - cfg->native_code;
4335                                 guint32 val;
4336                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4337
4338                                 /* Load info var */
4339                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4340                                 val = ((offset) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4341                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4342                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4343                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4344                         } else {
4345                                 /*
4346                                  * A placeholder for a possible breakpoint inserted by
4347                                  * mono_arch_set_breakpoint ().
4348                                  */
4349                                 for (i = 0; i < breakpoint_size; ++i)
4350                                         x86_nop (code);
4351                         }
4352                         /*
4353                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4354                          * to another IL offset.
4355                          */
4356                         x86_nop (code);
4357                         break;
4358                 }
4359                 case OP_ADDCC:
4360                 case OP_LADDCC:
4361                 case OP_LADD:
4362                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4363                         break;
4364                 case OP_ADC:
4365                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4366                         break;
4367                 case OP_ADD_IMM:
4368                 case OP_LADD_IMM:
4369                         g_assert (amd64_is_imm32 (ins->inst_imm));
4370                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4371                         break;
4372                 case OP_ADC_IMM:
4373                         g_assert (amd64_is_imm32 (ins->inst_imm));
4374                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4375                         break;
4376                 case OP_SUBCC:
4377                 case OP_LSUBCC:
4378                 case OP_LSUB:
4379                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4380                         break;
4381                 case OP_SBB:
4382                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4383                         break;
4384                 case OP_SUB_IMM:
4385                 case OP_LSUB_IMM:
4386                         g_assert (amd64_is_imm32 (ins->inst_imm));
4387                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4388                         break;
4389                 case OP_SBB_IMM:
4390                         g_assert (amd64_is_imm32 (ins->inst_imm));
4391                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4392                         break;
4393                 case OP_LAND:
4394                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4395                         break;
4396                 case OP_AND_IMM:
4397                 case OP_LAND_IMM:
4398                         g_assert (amd64_is_imm32 (ins->inst_imm));
4399                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4400                         break;
4401                 case OP_LMUL:
4402                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4403                         break;
4404                 case OP_MUL_IMM:
4405                 case OP_LMUL_IMM:
4406                 case OP_IMUL_IMM: {
4407                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4408
4409                         switch (ins->inst_imm) {
4410                         case 2:
4411                                 /* MOV r1, r2 */
4412                                 /* ADD r1, r1 */
4413                                 if (ins->dreg != ins->sreg1)
4414                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4415                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4416                                 break;
4417                         case 3:
4418                                 /* LEA r1, [r2 + r2*2] */
4419                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4420                                 break;
4421                         case 5:
4422                                 /* LEA r1, [r2 + r2*4] */
4423                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4424                                 break;
4425                         case 6:
4426                                 /* LEA r1, [r2 + r2*2] */
4427                                 /* ADD r1, r1          */
4428                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4429                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4430                                 break;
4431                         case 9:
4432                                 /* LEA r1, [r2 + r2*8] */
4433                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4434                                 break;
4435                         case 10:
4436                                 /* LEA r1, [r2 + r2*4] */
4437                                 /* ADD r1, r1          */
4438                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4439                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4440                                 break;
4441                         case 12:
4442                                 /* LEA r1, [r2 + r2*2] */
4443                                 /* SHL r1, 2           */
4444                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4445                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4446                                 break;
4447                         case 25:
4448                                 /* LEA r1, [r2 + r2*4] */
4449                                 /* LEA r1, [r1 + r1*4] */
4450                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4451                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4452                                 break;
4453                         case 100:
4454                                 /* LEA r1, [r2 + r2*4] */
4455                                 /* SHL r1, 2           */
4456                                 /* LEA r1, [r1 + r1*4] */
4457                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4458                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4459                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4460                                 break;
4461                         default:
4462                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4463                                 break;
4464                         }
4465                         break;
4466                 }
4467                 case OP_LDIV:
4468                 case OP_LREM:
4469 #if defined( __native_client_codegen__ )
4470                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4471                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4472 #endif
4473                         /* Regalloc magic makes the div/rem cases the same */
4474                         if (ins->sreg2 == AMD64_RDX) {
4475                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4476                                 amd64_cdq (code);
4477                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4478                         } else {
4479                                 amd64_cdq (code);
4480                                 amd64_div_reg (code, ins->sreg2, TRUE);
4481                         }
4482                         break;
4483                 case OP_LDIV_UN:
4484                 case OP_LREM_UN:
4485 #if defined( __native_client_codegen__ )
4486                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4487                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4488 #endif
4489                         if (ins->sreg2 == AMD64_RDX) {
4490                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4491                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4492                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4493                         } else {
4494                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4495                                 amd64_div_reg (code, ins->sreg2, FALSE);
4496                         }
4497                         break;
4498                 case OP_IDIV:
4499                 case OP_IREM:
4500 #if defined( __native_client_codegen__ )
4501                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4502                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4503 #endif
4504                         if (ins->sreg2 == AMD64_RDX) {
4505                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4506                                 amd64_cdq_size (code, 4);
4507                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4508                         } else {
4509                                 amd64_cdq_size (code, 4);
4510                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4511                         }
4512                         break;
4513                 case OP_IDIV_UN:
4514                 case OP_IREM_UN:
4515 #if defined( __native_client_codegen__ )
4516                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4517                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4518 #endif
4519                         if (ins->sreg2 == AMD64_RDX) {
4520                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4521                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4522                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4523                         } else {
4524                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4525                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4526                         }
4527                         break;
4528                 case OP_IREM_IMM: {
4529                         int power = mono_is_power_of_two (ins->inst_imm);
4530
4531                         g_assert (ins->sreg1 == X86_EAX);
4532                         g_assert (ins->dreg == X86_EAX);
4533                         g_assert (power >= 0);
4534
4535                         if (power == 0) {
4536                                 amd64_mov_reg_imm (code, ins->dreg, 0);
4537                                 break;
4538                         }
4539
4540                         /* Based on gcc code */
4541
4542                         /* Add compensation for negative dividents */
4543                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
4544                         if (power > 1)
4545                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
4546                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
4547                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
4548                         /* Compute remainder */
4549                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
4550                         /* Remove compensation */
4551                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
4552                         break;
4553                 }
4554                 case OP_LMUL_OVF:
4555                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4556                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4557                         break;
4558                 case OP_LOR:
4559                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4560                         break;
4561                 case OP_OR_IMM:
4562                 case OP_LOR_IMM:
4563                         g_assert (amd64_is_imm32 (ins->inst_imm));
4564                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4565                         break;
4566                 case OP_LXOR:
4567                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4568                         break;
4569                 case OP_XOR_IMM:
4570                 case OP_LXOR_IMM:
4571                         g_assert (amd64_is_imm32 (ins->inst_imm));
4572                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4573                         break;
4574                 case OP_LSHL:
4575                         g_assert (ins->sreg2 == AMD64_RCX);
4576                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4577                         break;
4578                 case OP_LSHR:
4579                         g_assert (ins->sreg2 == AMD64_RCX);
4580                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4581                         break;
4582                 case OP_SHR_IMM:
4583                         g_assert (amd64_is_imm32 (ins->inst_imm));
4584                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4585                         break;
4586                 case OP_LSHR_IMM:
4587                         g_assert (amd64_is_imm32 (ins->inst_imm));
4588                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4589                         break;
4590                 case OP_SHR_UN_IMM:
4591                         g_assert (amd64_is_imm32 (ins->inst_imm));
4592                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4593                         break;
4594                 case OP_LSHR_UN_IMM:
4595                         g_assert (amd64_is_imm32 (ins->inst_imm));
4596                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4597                         break;
4598                 case OP_LSHR_UN:
4599                         g_assert (ins->sreg2 == AMD64_RCX);
4600                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4601                         break;
4602                 case OP_SHL_IMM:
4603                         g_assert (amd64_is_imm32 (ins->inst_imm));
4604                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4605                         break;
4606                 case OP_LSHL_IMM:
4607                         g_assert (amd64_is_imm32 (ins->inst_imm));
4608                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4609                         break;
4610
4611                 case OP_IADDCC:
4612                 case OP_IADD:
4613                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4614                         break;
4615                 case OP_IADC:
4616                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4617                         break;
4618                 case OP_IADD_IMM:
4619                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4620                         break;
4621                 case OP_IADC_IMM:
4622                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4623                         break;
4624                 case OP_ISUBCC:
4625                 case OP_ISUB:
4626                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4627                         break;
4628                 case OP_ISBB:
4629                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4630                         break;
4631                 case OP_ISUB_IMM:
4632                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4633                         break;
4634                 case OP_ISBB_IMM:
4635                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4636                         break;
4637                 case OP_IAND:
4638                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4639                         break;
4640                 case OP_IAND_IMM:
4641                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4642                         break;
4643                 case OP_IOR:
4644                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4645                         break;
4646                 case OP_IOR_IMM:
4647                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4648                         break;
4649                 case OP_IXOR:
4650                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4651                         break;
4652                 case OP_IXOR_IMM:
4653                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4654                         break;
4655                 case OP_INEG:
4656                         amd64_neg_reg_size (code, ins->sreg1, 4);
4657                         break;
4658                 case OP_INOT:
4659                         amd64_not_reg_size (code, ins->sreg1, 4);
4660                         break;
4661                 case OP_ISHL:
4662                         g_assert (ins->sreg2 == AMD64_RCX);
4663                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4664                         break;
4665                 case OP_ISHR:
4666                         g_assert (ins->sreg2 == AMD64_RCX);
4667                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4668                         break;
4669                 case OP_ISHR_IMM:
4670                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4671                         break;
4672                 case OP_ISHR_UN_IMM:
4673                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4674                         break;
4675                 case OP_ISHR_UN:
4676                         g_assert (ins->sreg2 == AMD64_RCX);
4677                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4678                         break;
4679                 case OP_ISHL_IMM:
4680                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4681                         break;
4682                 case OP_IMUL:
4683                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4684                         break;
4685                 case OP_IMUL_OVF:
4686                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4687                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4688                         break;
4689                 case OP_IMUL_OVF_UN:
4690                 case OP_LMUL_OVF_UN: {
4691                         /* the mul operation and the exception check should most likely be split */
4692                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4693                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4694                         /*g_assert (ins->sreg2 == X86_EAX);
4695                         g_assert (ins->dreg == X86_EAX);*/
4696                         if (ins->sreg2 == X86_EAX) {
4697                                 non_eax_reg = ins->sreg1;
4698                         } else if (ins->sreg1 == X86_EAX) {
4699                                 non_eax_reg = ins->sreg2;
4700                         } else {
4701                                 /* no need to save since we're going to store to it anyway */
4702                                 if (ins->dreg != X86_EAX) {
4703                                         saved_eax = TRUE;
4704                                         amd64_push_reg (code, X86_EAX);
4705                                 }
4706                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4707                                 non_eax_reg = ins->sreg2;
4708                         }
4709                         if (ins->dreg == X86_EDX) {
4710                                 if (!saved_eax) {
4711                                         saved_eax = TRUE;
4712                                         amd64_push_reg (code, X86_EAX);
4713                                 }
4714                         } else {
4715                                 saved_edx = TRUE;
4716                                 amd64_push_reg (code, X86_EDX);
4717                         }
4718                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4719                         /* save before the check since pop and mov don't change the flags */
4720                         if (ins->dreg != X86_EAX)
4721                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4722                         if (saved_edx)
4723                                 amd64_pop_reg (code, X86_EDX);
4724                         if (saved_eax)
4725                                 amd64_pop_reg (code, X86_EAX);
4726                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4727                         break;
4728                 }
4729                 case OP_ICOMPARE:
4730                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4731                         break;
4732                 case OP_ICOMPARE_IMM:
4733                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4734                         break;
4735                 case OP_IBEQ:
4736                 case OP_IBLT:
4737                 case OP_IBGT:
4738                 case OP_IBGE:
4739                 case OP_IBLE:
4740                 case OP_LBEQ:
4741                 case OP_LBLT:
4742                 case OP_LBGT:
4743                 case OP_LBGE:
4744                 case OP_LBLE:
4745                 case OP_IBNE_UN:
4746                 case OP_IBLT_UN:
4747                 case OP_IBGT_UN:
4748                 case OP_IBGE_UN:
4749                 case OP_IBLE_UN:
4750                 case OP_LBNE_UN:
4751                 case OP_LBLT_UN:
4752                 case OP_LBGT_UN:
4753                 case OP_LBGE_UN:
4754                 case OP_LBLE_UN:
4755                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4756                         break;
4757
4758                 case OP_CMOV_IEQ:
4759                 case OP_CMOV_IGE:
4760                 case OP_CMOV_IGT:
4761                 case OP_CMOV_ILE:
4762                 case OP_CMOV_ILT:
4763                 case OP_CMOV_INE_UN:
4764                 case OP_CMOV_IGE_UN:
4765                 case OP_CMOV_IGT_UN:
4766                 case OP_CMOV_ILE_UN:
4767                 case OP_CMOV_ILT_UN:
4768                 case OP_CMOV_LEQ:
4769                 case OP_CMOV_LGE:
4770                 case OP_CMOV_LGT:
4771                 case OP_CMOV_LLE:
4772                 case OP_CMOV_LLT:
4773                 case OP_CMOV_LNE_UN:
4774                 case OP_CMOV_LGE_UN:
4775                 case OP_CMOV_LGT_UN:
4776                 case OP_CMOV_LLE_UN:
4777                 case OP_CMOV_LLT_UN:
4778                         g_assert (ins->dreg == ins->sreg1);
4779                         /* This needs to operate on 64 bit values */
4780                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4781                         break;
4782
4783                 case OP_LNOT:
4784                         amd64_not_reg (code, ins->sreg1);
4785                         break;
4786                 case OP_LNEG:
4787                         amd64_neg_reg (code, ins->sreg1);
4788                         break;
4789
4790                 case OP_ICONST:
4791                 case OP_I8CONST:
4792                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4793                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4794                         else
4795                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4796                         break;
4797                 case OP_AOTCONST:
4798                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4799                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4800                         break;
4801                 case OP_JUMP_TABLE:
4802                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4803                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4804                         break;
4805                 case OP_MOVE:
4806                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4807                         break;
4808                 case OP_AMD64_SET_XMMREG_R4: {
4809                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4810                         break;
4811                 }
4812                 case OP_AMD64_SET_XMMREG_R8: {
4813                         if (ins->dreg != ins->sreg1)
4814                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4815                         break;
4816                 }
4817                 case OP_TAILCALL: {
4818                         MonoCallInst *call = (MonoCallInst*)ins;
4819                         int i, save_area_offset;
4820
4821                         /* FIXME: no tracing support... */
4822                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4823                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, TRUE);
4824
4825                         g_assert (!cfg->method->save_lmf);
4826
4827                         /* Restore callee saved registers */
4828                         save_area_offset = cfg->arch.reg_save_area_offset;
4829                         for (i = 0; i < AMD64_NREG; ++i)
4830                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4831                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4832                                         save_area_offset += 8;
4833                                 }
4834
4835                         if (cfg->arch.omit_fp) {
4836                                 if (cfg->arch.stack_alloc_size)
4837                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4838                                 // FIXME:
4839                                 if (call->stack_usage)
4840                                         NOT_IMPLEMENTED;
4841                         } else {
4842                                 /* Copy arguments on the stack to our argument area */
4843                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4844                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4845                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4846                                 }
4847
4848                                 amd64_leave (code);
4849                         }
4850
4851                         offset = code - cfg->native_code;
4852                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4853                         if (cfg->compile_aot)
4854                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4855                         else
4856                                 amd64_set_reg_template (code, AMD64_R11);
4857                         amd64_jump_reg (code, AMD64_R11);
4858                         ins->flags |= MONO_INST_GC_CALLSITE;
4859                         ins->backend.pc_offset = code - cfg->native_code;
4860                         break;
4861                 }
4862                 case OP_CHECK_THIS:
4863                         /* ensure ins->sreg1 is not NULL */
4864                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4865                         break;
4866                 case OP_ARGLIST: {
4867                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4868                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4869                         break;
4870                 }
4871                 case OP_CALL:
4872                 case OP_FCALL:
4873                 case OP_LCALL:
4874                 case OP_VCALL:
4875                 case OP_VCALL2:
4876                 case OP_VOIDCALL:
4877                         call = (MonoCallInst*)ins;
4878                         /*
4879                          * The AMD64 ABI forces callers to know about varargs.
4880                          */
4881                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4882                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4883                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4884                                 /*
4885                                  * Since the unmanaged calling convention doesn't contain a
4886                                  * 'vararg' entry, we have to treat every pinvoke call as a
4887                                  * potential vararg call.
4888                                  */
4889                                 guint32 nregs, i;
4890                                 nregs = 0;
4891                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4892                                         if (call->used_fregs & (1 << i))
4893                                                 nregs ++;
4894                                 if (!nregs)
4895                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4896                                 else
4897                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4898                         }
4899
4900                         if (ins->flags & MONO_INST_HAS_METHOD)
4901                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4902                         else
4903                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4904                         ins->flags |= MONO_INST_GC_CALLSITE;
4905                         ins->backend.pc_offset = code - cfg->native_code;
4906                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4907                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4908                         code = emit_move_return_value (cfg, ins, code);
4909                         break;
4910                 case OP_FCALL_REG:
4911                 case OP_LCALL_REG:
4912                 case OP_VCALL_REG:
4913                 case OP_VCALL2_REG:
4914                 case OP_VOIDCALL_REG:
4915                 case OP_CALL_REG:
4916                         call = (MonoCallInst*)ins;
4917
4918                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4919                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4920                                 ins->sreg1 = AMD64_R11;
4921                         }
4922
4923                         /*
4924                          * The AMD64 ABI forces callers to know about varargs.
4925                          */
4926                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4927                                 if (ins->sreg1 == AMD64_RAX) {
4928                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4929                                         ins->sreg1 = AMD64_R11;
4930                                 }
4931                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4932                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4933                                 /*
4934                                  * Since the unmanaged calling convention doesn't contain a
4935                                  * 'vararg' entry, we have to treat every pinvoke call as a
4936                                  * potential vararg call.
4937                                  */
4938                                 guint32 nregs, i;
4939                                 nregs = 0;
4940                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4941                                         if (call->used_fregs & (1 << i))
4942                                                 nregs ++;
4943                                 if (ins->sreg1 == AMD64_RAX) {
4944                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4945                                         ins->sreg1 = AMD64_R11;
4946                                 }
4947                                 if (!nregs)
4948                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4949                                 else
4950                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4951                         }
4952
4953                         amd64_call_reg (code, ins->sreg1);
4954                         ins->flags |= MONO_INST_GC_CALLSITE;
4955                         ins->backend.pc_offset = code - cfg->native_code;
4956                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4957                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4958                         code = emit_move_return_value (cfg, ins, code);
4959                         break;
4960                 case OP_FCALL_MEMBASE:
4961                 case OP_LCALL_MEMBASE:
4962                 case OP_VCALL_MEMBASE:
4963                 case OP_VCALL2_MEMBASE:
4964                 case OP_VOIDCALL_MEMBASE:
4965                 case OP_CALL_MEMBASE:
4966                         call = (MonoCallInst*)ins;
4967
4968                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4969                         ins->flags |= MONO_INST_GC_CALLSITE;
4970                         ins->backend.pc_offset = code - cfg->native_code;
4971                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4972                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4973                         code = emit_move_return_value (cfg, ins, code);
4974                         break;
4975                 case OP_DYN_CALL: {
4976                         int i;
4977                         MonoInst *var = cfg->dyn_call_var;
4978
4979                         g_assert (var->opcode == OP_REGOFFSET);
4980
4981                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4982                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4983                         /* r10 = ftn */
4984                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4985
4986                         /* Save args buffer */
4987                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4988
4989                         /* Set argument registers */
4990                         for (i = 0; i < PARAM_REGS; ++i)
4991                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4992
4993                         /* Make the call */
4994                         amd64_call_reg (code, AMD64_R10);
4995
4996                         ins->flags |= MONO_INST_GC_CALLSITE;
4997                         ins->backend.pc_offset = code - cfg->native_code;
4998
4999                         /* Save result */
5000                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5001                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5002                         break;
5003                 }
5004                 case OP_AMD64_SAVE_SP_TO_LMF: {
5005                         MonoInst *lmf_var = cfg->lmf_var;
5006                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5007                         break;
5008                 }
5009                 case OP_X86_PUSH:
5010                         g_assert (!cfg->arch.no_pushes);
5011                         amd64_push_reg (code, ins->sreg1);
5012                         break;
5013                 case OP_X86_PUSH_IMM:
5014                         g_assert (!cfg->arch.no_pushes);
5015                         g_assert (amd64_is_imm32 (ins->inst_imm));
5016                         amd64_push_imm (code, ins->inst_imm);
5017                         break;
5018                 case OP_X86_PUSH_MEMBASE:
5019                         g_assert (!cfg->arch.no_pushes);
5020                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5021                         break;
5022                 case OP_X86_PUSH_OBJ: {
5023                         int size = ALIGN_TO (ins->inst_imm, 8);
5024
5025                         g_assert (!cfg->arch.no_pushes);
5026
5027                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5028                         amd64_push_reg (code, AMD64_RDI);
5029                         amd64_push_reg (code, AMD64_RSI);
5030                         amd64_push_reg (code, AMD64_RCX);
5031                         if (ins->inst_offset)
5032                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5033                         else
5034                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5035                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5036                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5037                         amd64_cld (code);
5038                         amd64_prefix (code, X86_REP_PREFIX);
5039                         amd64_movsd (code);
5040                         amd64_pop_reg (code, AMD64_RCX);
5041                         amd64_pop_reg (code, AMD64_RSI);
5042                         amd64_pop_reg (code, AMD64_RDI);
5043                         break;
5044                 }
5045                 case OP_X86_LEA:
5046                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5047                         break;
5048                 case OP_X86_LEA_MEMBASE:
5049                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5050                         break;
5051                 case OP_X86_XCHG:
5052                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5053                         break;
5054                 case OP_LOCALLOC:
5055                         /* keep alignment */
5056                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5057                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5058                         code = mono_emit_stack_alloc (cfg, code, ins);
5059                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5060                         if (cfg->param_area && cfg->arch.no_pushes)
5061                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5062                         break;
5063                 case OP_LOCALLOC_IMM: {
5064                         guint32 size = ins->inst_imm;
5065                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5066
5067                         if (ins->flags & MONO_INST_INIT) {
5068                                 if (size < 64) {
5069                                         int i;
5070
5071                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5072                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5073
5074                                         for (i = 0; i < size; i += 8)
5075                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5076                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5077                                 } else {
5078                                         amd64_mov_reg_imm (code, ins->dreg, size);
5079                                         ins->sreg1 = ins->dreg;
5080
5081                                         code = mono_emit_stack_alloc (cfg, code, ins);
5082                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5083                                 }
5084                         } else {
5085                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5086                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5087                         }
5088                         if (cfg->param_area && cfg->arch.no_pushes)
5089                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5090                         break;
5091                 }
5092                 case OP_THROW: {
5093                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5094                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5095                                              (gpointer)"mono_arch_throw_exception", FALSE);
5096                         ins->flags |= MONO_INST_GC_CALLSITE;
5097                         ins->backend.pc_offset = code - cfg->native_code;
5098                         break;
5099                 }
5100                 case OP_RETHROW: {
5101                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5102                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5103                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5104                         ins->flags |= MONO_INST_GC_CALLSITE;
5105                         ins->backend.pc_offset = code - cfg->native_code;
5106                         break;
5107                 }
5108                 case OP_CALL_HANDLER:
5109                         /* Align stack */
5110                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5111                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5112                         amd64_call_imm (code, 0);
5113                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5114                         /* Restore stack alignment */
5115                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5116                         break;
5117                 case OP_START_HANDLER: {
5118                         /* Even though we're saving RSP, use sizeof */
5119                         /* gpointer because spvar is of type IntPtr */
5120                         /* see: mono_create_spvar_for_region */
5121                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5122                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5123
5124                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5125                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5126                                 cfg->param_area && cfg->arch.no_pushes) {
5127                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5128                         }
5129                         break;
5130                 }
5131                 case OP_ENDFINALLY: {
5132                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5133                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5134                         amd64_ret (code);
5135                         break;
5136                 }
5137                 case OP_ENDFILTER: {
5138                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5139                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5140                         /* The local allocator will put the result into RAX */
5141                         amd64_ret (code);
5142                         break;
5143                 }
5144
5145                 case OP_LABEL:
5146                         ins->inst_c0 = code - cfg->native_code;
5147                         break;
5148                 case OP_BR:
5149                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5150                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5151                         //break;
5152                                 if (ins->inst_target_bb->native_offset) {
5153                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5154                                 } else {
5155                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5156                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5157                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5158                                                 x86_jump8 (code, 0);
5159                                         else
5160                                                 x86_jump32 (code, 0);
5161                         }
5162                         break;
5163                 case OP_BR_REG:
5164                         amd64_jump_reg (code, ins->sreg1);
5165                         break;
5166                 case OP_ICNEQ:
5167                 case OP_ICGE:
5168                 case OP_ICLE:
5169                 case OP_ICGE_UN:
5170                 case OP_ICLE_UN:
5171
5172                 case OP_CEQ:
5173                 case OP_LCEQ:
5174                 case OP_ICEQ:
5175                 case OP_CLT:
5176                 case OP_LCLT:
5177                 case OP_ICLT:
5178                 case OP_CGT:
5179                 case OP_ICGT:
5180                 case OP_LCGT:
5181                 case OP_CLT_UN:
5182                 case OP_LCLT_UN:
5183                 case OP_ICLT_UN:
5184                 case OP_CGT_UN:
5185                 case OP_LCGT_UN:
5186                 case OP_ICGT_UN:
5187                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5188                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5189                         break;
5190                 case OP_COND_EXC_EQ:
5191                 case OP_COND_EXC_NE_UN:
5192                 case OP_COND_EXC_LT:
5193                 case OP_COND_EXC_LT_UN:
5194                 case OP_COND_EXC_GT:
5195                 case OP_COND_EXC_GT_UN:
5196                 case OP_COND_EXC_GE:
5197                 case OP_COND_EXC_GE_UN:
5198                 case OP_COND_EXC_LE:
5199                 case OP_COND_EXC_LE_UN:
5200                 case OP_COND_EXC_IEQ:
5201                 case OP_COND_EXC_INE_UN:
5202                 case OP_COND_EXC_ILT:
5203                 case OP_COND_EXC_ILT_UN:
5204                 case OP_COND_EXC_IGT:
5205                 case OP_COND_EXC_IGT_UN:
5206                 case OP_COND_EXC_IGE:
5207                 case OP_COND_EXC_IGE_UN:
5208                 case OP_COND_EXC_ILE:
5209                 case OP_COND_EXC_ILE_UN:
5210                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5211                         break;
5212                 case OP_COND_EXC_OV:
5213                 case OP_COND_EXC_NO:
5214                 case OP_COND_EXC_C:
5215                 case OP_COND_EXC_NC:
5216                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5217                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5218                         break;
5219                 case OP_COND_EXC_IOV:
5220                 case OP_COND_EXC_INO:
5221                 case OP_COND_EXC_IC:
5222                 case OP_COND_EXC_INC:
5223                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5224                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5225                         break;
5226
5227                 /* floating point opcodes */
5228                 case OP_R8CONST: {
5229                         double d = *(double *)ins->inst_p0;
5230
5231                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5232                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5233                         }
5234                         else {
5235                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5236                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5237                         }
5238                         break;
5239                 }
5240                 case OP_R4CONST: {
5241                         float f = *(float *)ins->inst_p0;
5242
5243                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5244                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5245                         }
5246                         else {
5247                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5248                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5249                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5250                         }
5251                         break;
5252                 }
5253                 case OP_STORER8_MEMBASE_REG:
5254                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5255                         break;
5256                 case OP_LOADR8_MEMBASE:
5257                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5258                         break;
5259                 case OP_STORER4_MEMBASE_REG:
5260                         /* This requires a double->single conversion */
5261                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5262                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5263                         break;
5264                 case OP_LOADR4_MEMBASE:
5265                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5266                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5267                         break;
5268                 case OP_ICONV_TO_R4:
5269                         amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5270                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5271                         break;
5272                 case OP_ICONV_TO_R8:
5273                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5274                         break;
5275                 case OP_LCONV_TO_R4:
5276                         amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5277                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5278                         break;
5279                 case OP_LCONV_TO_R8:
5280                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5281                         break;
5282                 case OP_FCONV_TO_R4:
5283                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5284                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5285                         break;
5286                 case OP_FCONV_TO_I1:
5287                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5288                         break;
5289                 case OP_FCONV_TO_U1:
5290                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5291                         break;
5292                 case OP_FCONV_TO_I2:
5293                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5294                         break;
5295                 case OP_FCONV_TO_U2:
5296                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5297                         break;
5298                 case OP_FCONV_TO_U4:
5299                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5300                         break;
5301                 case OP_FCONV_TO_I4:
5302                 case OP_FCONV_TO_I:
5303                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5304                         break;
5305                 case OP_FCONV_TO_I8:
5306                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5307                         break;
5308                 case OP_LCONV_TO_R_UN: {
5309                         guint8 *br [2];
5310
5311                         /* Based on gcc code */
5312                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5313                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5314
5315                         /* Positive case */
5316                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5317                         br [1] = code; x86_jump8 (code, 0);
5318                         amd64_patch (br [0], code);
5319
5320                         /* Negative case */
5321                         /* Save to the red zone */
5322                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5323                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5324                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5325                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5326                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5327                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5328                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5329                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5330                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5331                         /* Restore */
5332                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5333                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5334                         amd64_patch (br [1], code);
5335                         break;
5336                 }
5337                 case OP_LCONV_TO_OVF_U4:
5338                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5339                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5340                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5341                         break;
5342                 case OP_LCONV_TO_OVF_I4_UN:
5343                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5344                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5345                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5346                         break;
5347                 case OP_FMOVE:
5348                         if (ins->dreg != ins->sreg1)
5349                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5350                         break;
5351                 case OP_FADD:
5352                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5353                         break;
5354                 case OP_FSUB:
5355                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5356                         break;
5357                 case OP_FMUL:
5358                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5359                         break;
5360                 case OP_FDIV:
5361                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5362                         break;
5363                 case OP_FNEG: {
5364                         static double r8_0 = -0.0;
5365
5366                         g_assert (ins->sreg1 == ins->dreg);
5367
5368                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5369                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5370                         break;
5371                 }
5372                 case OP_SIN:
5373                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5374                         break;
5375                 case OP_COS:
5376                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5377                         break;
5378                 case OP_ABS: {
5379                         static guint64 d = 0x7fffffffffffffffUL;
5380
5381                         g_assert (ins->sreg1 == ins->dreg);
5382
5383                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5384                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5385                         break;
5386                 }
5387                 case OP_SQRT:
5388                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5389                         break;
5390                 case OP_IMIN:
5391                         g_assert (cfg->opt & MONO_OPT_CMOV);
5392                         g_assert (ins->dreg == ins->sreg1);
5393                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5394                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5395                         break;
5396                 case OP_IMIN_UN:
5397                         g_assert (cfg->opt & MONO_OPT_CMOV);
5398                         g_assert (ins->dreg == ins->sreg1);
5399                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5400                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5401                         break;
5402                 case OP_IMAX:
5403                         g_assert (cfg->opt & MONO_OPT_CMOV);
5404                         g_assert (ins->dreg == ins->sreg1);
5405                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5406                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5407                         break;
5408                 case OP_IMAX_UN:
5409                         g_assert (cfg->opt & MONO_OPT_CMOV);
5410                         g_assert (ins->dreg == ins->sreg1);
5411                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5412                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5413                         break;
5414                 case OP_LMIN:
5415                         g_assert (cfg->opt & MONO_OPT_CMOV);
5416                         g_assert (ins->dreg == ins->sreg1);
5417                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5418                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5419                         break;
5420                 case OP_LMIN_UN:
5421                         g_assert (cfg->opt & MONO_OPT_CMOV);
5422                         g_assert (ins->dreg == ins->sreg1);
5423                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5424                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5425                         break;
5426                 case OP_LMAX:
5427                         g_assert (cfg->opt & MONO_OPT_CMOV);
5428                         g_assert (ins->dreg == ins->sreg1);
5429                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5430                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5431                         break;
5432                 case OP_LMAX_UN:
5433                         g_assert (cfg->opt & MONO_OPT_CMOV);
5434                         g_assert (ins->dreg == ins->sreg1);
5435                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5436                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5437                         break;
5438                 case OP_X86_FPOP:
5439                         break;
5440                 case OP_FCOMPARE:
5441                         /*
5442                          * The two arguments are swapped because the fbranch instructions
5443                          * depend on this for the non-sse case to work.
5444                          */
5445                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5446                         break;
5447                 case OP_FCNEQ:
5448                 case OP_FCEQ: {
5449                         /* zeroing the register at the start results in
5450                          * shorter and faster code (we can also remove the widening op)
5451                          */
5452                         guchar *unordered_check;
5453                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5454                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5455                         unordered_check = code;
5456                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5457
5458                         if (ins->opcode == OP_FCEQ) {
5459                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5460                                 amd64_patch (unordered_check, code);
5461                         } else {
5462                                 guchar *jump_to_end;
5463                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5464                                 jump_to_end = code;
5465                                 x86_jump8 (code, 0);
5466                                 amd64_patch (unordered_check, code);
5467                                 amd64_inc_reg (code, ins->dreg);
5468                                 amd64_patch (jump_to_end, code);
5469                         }
5470                         break;
5471                 }
5472                 case OP_FCLT:
5473                 case OP_FCLT_UN:
5474                         /* zeroing the register at the start results in
5475                          * shorter and faster code (we can also remove the widening op)
5476                          */
5477                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5478                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5479                         if (ins->opcode == OP_FCLT_UN) {
5480                                 guchar *unordered_check = code;
5481                                 guchar *jump_to_end;
5482                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5483                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5484                                 jump_to_end = code;
5485                                 x86_jump8 (code, 0);
5486                                 amd64_patch (unordered_check, code);
5487                                 amd64_inc_reg (code, ins->dreg);
5488                                 amd64_patch (jump_to_end, code);
5489                         } else {
5490                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5491                         }
5492                         break;
5493                 case OP_FCLE: {
5494                         guchar *unordered_check;
5495                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5496                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5497                         unordered_check = code;
5498                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5499                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5500                         amd64_patch (unordered_check, code);
5501                         break;
5502                 }
5503                 case OP_FCGT:
5504                 case OP_FCGT_UN: {
5505                         /* zeroing the register at the start results in
5506                          * shorter and faster code (we can also remove the widening op)
5507                          */
5508                         guchar *unordered_check;
5509                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5510                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5511                         if (ins->opcode == OP_FCGT) {
5512                                 unordered_check = code;
5513                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5514                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5515                                 amd64_patch (unordered_check, code);
5516                         } else {
5517                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5518                         }
5519                         break;
5520                 }
5521                 case OP_FCGE: {
5522                         guchar *unordered_check;
5523                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5524                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5525                         unordered_check = code;
5526                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5527                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5528                         amd64_patch (unordered_check, code);
5529                         break;
5530                 }
5531
5532                 case OP_FCLT_MEMBASE:
5533                 case OP_FCGT_MEMBASE:
5534                 case OP_FCLT_UN_MEMBASE:
5535                 case OP_FCGT_UN_MEMBASE:
5536                 case OP_FCEQ_MEMBASE: {
5537                         guchar *unordered_check, *jump_to_end;
5538                         int x86_cond;
5539
5540                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5541                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5542
5543                         switch (ins->opcode) {
5544                         case OP_FCEQ_MEMBASE:
5545                                 x86_cond = X86_CC_EQ;
5546                                 break;
5547                         case OP_FCLT_MEMBASE:
5548                         case OP_FCLT_UN_MEMBASE:
5549                                 x86_cond = X86_CC_LT;
5550                                 break;
5551                         case OP_FCGT_MEMBASE:
5552                         case OP_FCGT_UN_MEMBASE:
5553                                 x86_cond = X86_CC_GT;
5554                                 break;
5555                         default:
5556                                 g_assert_not_reached ();
5557                         }
5558
5559                         unordered_check = code;
5560                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5561                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5562
5563                         switch (ins->opcode) {
5564                         case OP_FCEQ_MEMBASE:
5565                         case OP_FCLT_MEMBASE:
5566                         case OP_FCGT_MEMBASE:
5567                                 amd64_patch (unordered_check, code);
5568                                 break;
5569                         case OP_FCLT_UN_MEMBASE:
5570                         case OP_FCGT_UN_MEMBASE:
5571                                 jump_to_end = code;
5572                                 x86_jump8 (code, 0);
5573                                 amd64_patch (unordered_check, code);
5574                                 amd64_inc_reg (code, ins->dreg);
5575                                 amd64_patch (jump_to_end, code);
5576                                 break;
5577                         default:
5578                                 break;
5579                         }
5580                         break;
5581                 }
5582                 case OP_FBEQ: {
5583                         guchar *jump = code;
5584                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5585                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5586                         amd64_patch (jump, code);
5587                         break;
5588                 }
5589                 case OP_FBNE_UN:
5590                         /* Branch if C013 != 100 */
5591                         /* branch if !ZF or (PF|CF) */
5592                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5593                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5594                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5595                         break;
5596                 case OP_FBLT:
5597                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5598                         break;
5599                 case OP_FBLT_UN:
5600                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5601                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5602                         break;
5603                 case OP_FBGT:
5604                 case OP_FBGT_UN:
5605                         if (ins->opcode == OP_FBGT) {
5606                                 guchar *br1;
5607
5608                                 /* skip branch if C1=1 */
5609                                 br1 = code;
5610                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5611                                 /* branch if (C0 | C3) = 1 */
5612                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5613                                 amd64_patch (br1, code);
5614                                 break;
5615                         } else {
5616                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5617                         }
5618                         break;
5619                 case OP_FBGE: {
5620                         /* Branch if C013 == 100 or 001 */
5621                         guchar *br1;
5622
5623                         /* skip branch if C1=1 */
5624                         br1 = code;
5625                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5626                         /* branch if (C0 | C3) = 1 */
5627                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5628                         amd64_patch (br1, code);
5629                         break;
5630                 }
5631                 case OP_FBGE_UN:
5632                         /* Branch if C013 == 000 */
5633                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5634                         break;
5635                 case OP_FBLE: {
5636                         /* Branch if C013=000 or 100 */
5637                         guchar *br1;
5638
5639                         /* skip branch if C1=1 */
5640                         br1 = code;
5641                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5642                         /* branch if C0=0 */
5643                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5644                         amd64_patch (br1, code);
5645                         break;
5646                 }
5647                 case OP_FBLE_UN:
5648                         /* Branch if C013 != 001 */
5649                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5650                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5651                         break;
5652                 case OP_CKFINITE:
5653                         /* Transfer value to the fp stack */
5654                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5655                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5656                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5657
5658                         amd64_push_reg (code, AMD64_RAX);
5659                         amd64_fxam (code);
5660                         amd64_fnstsw (code);
5661                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5662                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5663                         amd64_pop_reg (code, AMD64_RAX);
5664                         amd64_fstp (code, 0);
5665                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5666                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5667                         break;
5668                 case OP_TLS_GET: {
5669                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5670                         break;
5671                 }
5672                 case OP_TLS_GET_REG:
5673                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5674                         break;
5675                 case OP_TLS_SET: {
5676                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5677                         break;
5678                 }
5679                 case OP_TLS_SET_REG: {
5680                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5681                         break;
5682                 }
5683                 case OP_MEMORY_BARRIER: {
5684                         switch (ins->backend.memory_barrier_kind) {
5685                         case StoreLoadBarrier:
5686                         case FullBarrier:
5687                                 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5688                                 x86_prefix (code, X86_LOCK_PREFIX);
5689                                 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5690                                 break;
5691                         }
5692                         break;
5693                 }
5694                 case OP_ATOMIC_ADD_I4:
5695                 case OP_ATOMIC_ADD_I8: {
5696                         int dreg = ins->dreg;
5697                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5698
5699                         if (dreg == ins->inst_basereg)
5700                                 dreg = AMD64_R11;
5701
5702                         if (dreg != ins->sreg2)
5703                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5704
5705                         x86_prefix (code, X86_LOCK_PREFIX);
5706                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5707
5708                         if (dreg != ins->dreg)
5709                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5710
5711                         break;
5712                 }
5713                 case OP_ATOMIC_ADD_NEW_I4:
5714                 case OP_ATOMIC_ADD_NEW_I8: {
5715                         int dreg = ins->dreg;
5716                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
5717
5718                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5719                                 dreg = AMD64_R11;
5720
5721                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5722                         amd64_prefix (code, X86_LOCK_PREFIX);
5723                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5724                         /* dreg contains the old value, add with sreg2 value */
5725                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5726
5727                         if (ins->dreg != dreg)
5728                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5729
5730                         break;
5731                 }
5732                 case OP_ATOMIC_EXCHANGE_I4:
5733                 case OP_ATOMIC_EXCHANGE_I8: {
5734                         guchar *br[2];
5735                         int sreg2 = ins->sreg2;
5736                         int breg = ins->inst_basereg;
5737                         guint32 size;
5738                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5739
5740                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5741                                 size = 8;
5742                         else
5743                                 size = 4;
5744
5745                         /*
5746                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5747                          * an explanation of how this works.
5748                          */
5749
5750                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5751                          * hack to overcome limits in x86 reg allocator
5752                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5753                          */
5754                         g_assert (ins->dreg == AMD64_RAX);
5755
5756                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5757                                 /* Highly unlikely, but possible */
5758                                 need_push = TRUE;
5759
5760                         /* The pushes invalidate rsp */
5761                         if ((breg == AMD64_RAX) || need_push) {
5762                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5763                                 breg = AMD64_R11;
5764                         }
5765
5766                         /* We need the EAX reg for the comparand */
5767                         if (ins->sreg2 == AMD64_RAX) {
5768                                 if (breg != AMD64_R11) {
5769                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5770                                         sreg2 = AMD64_R11;
5771                                 } else {
5772                                         g_assert (need_push);
5773                                         amd64_push_reg (code, AMD64_RDX);
5774                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5775                                         sreg2 = AMD64_RDX;
5776                                         rdx_pushed = TRUE;
5777                                 }
5778                         }
5779
5780                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5781
5782                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5783                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5784                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5785                         amd64_patch (br [1], br [0]);
5786
5787                         if (rdx_pushed)
5788                                 amd64_pop_reg (code, AMD64_RDX);
5789
5790                         break;
5791                 }
5792                 case OP_ATOMIC_CAS_I4:
5793                 case OP_ATOMIC_CAS_I8: {
5794                         guint32 size;
5795
5796                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5797                                 size = 8;
5798                         else
5799                                 size = 4;
5800
5801                         /*
5802                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5803                          * an explanation of how this works.
5804                          */
5805                         g_assert (ins->sreg3 == AMD64_RAX);
5806                         g_assert (ins->sreg1 != AMD64_RAX);
5807                         g_assert (ins->sreg1 != ins->sreg2);
5808
5809                         amd64_prefix (code, X86_LOCK_PREFIX);
5810                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5811
5812                         if (ins->dreg != AMD64_RAX)
5813                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5814                         break;
5815                 }
5816                 case OP_CARD_TABLE_WBARRIER: {
5817                         int ptr = ins->sreg1;
5818                         int value = ins->sreg2;
5819                         guchar *br = 0;
5820                         int nursery_shift, card_table_shift;
5821                         gpointer card_table_mask;
5822                         size_t nursery_size;
5823
5824                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5825                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5826                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5827
5828                         /*If either point to the stack we can simply avoid the WB. This happens due to
5829                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5830                          */
5831                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5832                                 continue;
5833
5834                         /*
5835                          * We need one register we can clobber, we choose EDX and make sreg1
5836                          * fixed EAX to work around limitations in the local register allocator.
5837                          * sreg2 might get allocated to EDX, but that is not a problem since
5838                          * we use it before clobbering EDX.
5839                          */
5840                         g_assert (ins->sreg1 == AMD64_RAX);
5841
5842                         /*
5843                          * This is the code we produce:
5844                          *
5845                          *   edx = value
5846                          *   edx >>= nursery_shift
5847                          *   cmp edx, (nursery_start >> nursery_shift)
5848                          *   jne done
5849                          *   edx = ptr
5850                          *   edx >>= card_table_shift
5851                          *   edx += cardtable
5852                          *   [edx] = 1
5853                          * done:
5854                          */
5855
5856                         if (mono_gc_card_table_nursery_check ()) {
5857                                 if (value != AMD64_RDX)
5858                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5859                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5860                                 if (shifted_nursery_start >> 31) {
5861                                         /*
5862                                          * The value we need to compare against is 64 bits, so we need
5863                                          * another spare register.  We use RBX, which we save and
5864                                          * restore.
5865                                          */
5866                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5867                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5868                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5869                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5870                                 } else {
5871                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5872                                 }
5873                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5874                         }
5875                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5876                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5877                         if (card_table_mask)
5878                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5879
5880                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5881                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5882
5883                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5884
5885                         if (mono_gc_card_table_nursery_check ())
5886                                 x86_patch (br, code);
5887                         break;
5888                 }
5889 #ifdef MONO_ARCH_SIMD_INTRINSICS
5890                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5891                 case OP_ADDPS:
5892                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5893                         break;
5894                 case OP_DIVPS:
5895                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5896                         break;
5897                 case OP_MULPS:
5898                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5899                         break;
5900                 case OP_SUBPS:
5901                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5902                         break;
5903                 case OP_MAXPS:
5904                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5905                         break;
5906                 case OP_MINPS:
5907                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5908                         break;
5909                 case OP_COMPPS:
5910                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5911                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5912                         break;
5913                 case OP_ANDPS:
5914                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5915                         break;
5916                 case OP_ANDNPS:
5917                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5918                         break;
5919                 case OP_ORPS:
5920                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5921                         break;
5922                 case OP_XORPS:
5923                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5924                         break;
5925                 case OP_SQRTPS:
5926                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5927                         break;
5928                 case OP_RSQRTPS:
5929                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5930                         break;
5931                 case OP_RCPPS:
5932                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5933                         break;
5934                 case OP_ADDSUBPS:
5935                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5936                         break;
5937                 case OP_HADDPS:
5938                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5939                         break;
5940                 case OP_HSUBPS:
5941                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5942                         break;
5943                 case OP_DUPPS_HIGH:
5944                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5945                         break;
5946                 case OP_DUPPS_LOW:
5947                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5948                         break;
5949
5950                 case OP_PSHUFLEW_HIGH:
5951                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5952                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5953                         break;
5954                 case OP_PSHUFLEW_LOW:
5955                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5956                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5957                         break;
5958                 case OP_PSHUFLED:
5959                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5960                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5961                         break;
5962                 case OP_SHUFPS:
5963                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5964                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5965                         break;
5966                 case OP_SHUFPD:
5967                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5968                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5969                         break;
5970
5971                 case OP_ADDPD:
5972                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5973                         break;
5974                 case OP_DIVPD:
5975                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5976                         break;
5977                 case OP_MULPD:
5978                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5979                         break;
5980                 case OP_SUBPD:
5981                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5982                         break;
5983                 case OP_MAXPD:
5984                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5985                         break;
5986                 case OP_MINPD:
5987                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5988                         break;
5989                 case OP_COMPPD:
5990                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5991                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5992                         break;
5993                 case OP_ANDPD:
5994                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5995                         break;
5996                 case OP_ANDNPD:
5997                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5998                         break;
5999                 case OP_ORPD:
6000                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_XORPD:
6003                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005                 case OP_SQRTPD:
6006                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6007                         break;
6008                 case OP_ADDSUBPD:
6009                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011                 case OP_HADDPD:
6012                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014                 case OP_HSUBPD:
6015                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017                 case OP_DUPPD:
6018                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6019                         break;
6020
6021                 case OP_EXTRACT_MASK:
6022                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6023                         break;
6024
6025                 case OP_PAND:
6026                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028                 case OP_POR:
6029                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6030                         break;
6031                 case OP_PXOR:
6032                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034
6035                 case OP_PADDB:
6036                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038                 case OP_PADDW:
6039                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041                 case OP_PADDD:
6042                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044                 case OP_PADDQ:
6045                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047
6048                 case OP_PSUBB:
6049                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051                 case OP_PSUBW:
6052                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054                 case OP_PSUBD:
6055                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_PSUBQ:
6058                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060
6061                 case OP_PMAXB_UN:
6062                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6063                         break;
6064                 case OP_PMAXW_UN:
6065                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067                 case OP_PMAXD_UN:
6068                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070
6071                 case OP_PMAXB:
6072                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6073                         break;
6074                 case OP_PMAXW:
6075                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6076                         break;
6077                 case OP_PMAXD:
6078                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080
6081                 case OP_PAVGB_UN:
6082                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6083                         break;
6084                 case OP_PAVGW_UN:
6085                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6086                         break;
6087
6088                 case OP_PMINB_UN:
6089                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6090                         break;
6091                 case OP_PMINW_UN:
6092                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6093                         break;
6094                 case OP_PMIND_UN:
6095                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6096                         break;
6097
6098                 case OP_PMINB:
6099                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6100                         break;
6101                 case OP_PMINW:
6102                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6103                         break;
6104                 case OP_PMIND:
6105                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6106                         break;
6107
6108                 case OP_PCMPEQB:
6109                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6110                         break;
6111                 case OP_PCMPEQW:
6112                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114                 case OP_PCMPEQD:
6115                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6116                         break;
6117                 case OP_PCMPEQQ:
6118                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6119                         break;
6120
6121                 case OP_PCMPGTB:
6122                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6123                         break;
6124                 case OP_PCMPGTW:
6125                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6126                         break;
6127                 case OP_PCMPGTD:
6128                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6129                         break;
6130                 case OP_PCMPGTQ:
6131                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6132                         break;
6133
6134                 case OP_PSUM_ABS_DIFF:
6135                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6136                         break;
6137
6138                 case OP_UNPACK_LOWB:
6139                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6140                         break;
6141                 case OP_UNPACK_LOWW:
6142                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6143                         break;
6144                 case OP_UNPACK_LOWD:
6145                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6146                         break;
6147                 case OP_UNPACK_LOWQ:
6148                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6149                         break;
6150                 case OP_UNPACK_LOWPS:
6151                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6152                         break;
6153                 case OP_UNPACK_LOWPD:
6154                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6155                         break;
6156
6157                 case OP_UNPACK_HIGHB:
6158                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6159                         break;
6160                 case OP_UNPACK_HIGHW:
6161                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6162                         break;
6163                 case OP_UNPACK_HIGHD:
6164                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6165                         break;
6166                 case OP_UNPACK_HIGHQ:
6167                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6168                         break;
6169                 case OP_UNPACK_HIGHPS:
6170                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6171                         break;
6172                 case OP_UNPACK_HIGHPD:
6173                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6174                         break;
6175
6176                 case OP_PACKW:
6177                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6178                         break;
6179                 case OP_PACKD:
6180                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6181                         break;
6182                 case OP_PACKW_UN:
6183                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6184                         break;
6185                 case OP_PACKD_UN:
6186                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6187                         break;
6188
6189                 case OP_PADDB_SAT_UN:
6190                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6191                         break;
6192                 case OP_PSUBB_SAT_UN:
6193                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6194                         break;
6195                 case OP_PADDW_SAT_UN:
6196                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6197                         break;
6198                 case OP_PSUBW_SAT_UN:
6199                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6200                         break;
6201
6202                 case OP_PADDB_SAT:
6203                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6204                         break;
6205                 case OP_PSUBB_SAT:
6206                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6207                         break;
6208                 case OP_PADDW_SAT:
6209                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6210                         break;
6211                 case OP_PSUBW_SAT:
6212                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6213                         break;
6214
6215                 case OP_PMULW:
6216                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6217                         break;
6218                 case OP_PMULD:
6219                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6220                         break;
6221                 case OP_PMULQ:
6222                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6223                         break;
6224                 case OP_PMULW_HIGH_UN:
6225                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6226                         break;
6227                 case OP_PMULW_HIGH:
6228                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6229                         break;
6230
6231                 case OP_PSHRW:
6232                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6233                         break;
6234                 case OP_PSHRW_REG:
6235                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6236                         break;
6237
6238                 case OP_PSARW:
6239                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6240                         break;
6241                 case OP_PSARW_REG:
6242                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6243                         break;
6244
6245                 case OP_PSHLW:
6246                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6247                         break;
6248                 case OP_PSHLW_REG:
6249                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6250                         break;
6251
6252                 case OP_PSHRD:
6253                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6254                         break;
6255                 case OP_PSHRD_REG:
6256                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6257                         break;
6258
6259                 case OP_PSARD:
6260                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6261                         break;
6262                 case OP_PSARD_REG:
6263                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6264                         break;
6265
6266                 case OP_PSHLD:
6267                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6268                         break;
6269                 case OP_PSHLD_REG:
6270                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6271                         break;
6272
6273                 case OP_PSHRQ:
6274                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6275                         break;
6276                 case OP_PSHRQ_REG:
6277                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6278                         break;
6279
6280                 /*TODO: This is appart of the sse spec but not added
6281                 case OP_PSARQ:
6282                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6283                         break;
6284                 case OP_PSARQ_REG:
6285                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6286                         break;
6287                 */
6288
6289                 case OP_PSHLQ:
6290                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6291                         break;
6292                 case OP_PSHLQ_REG:
6293                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6294                         break;
6295                 case OP_CVTDQ2PD:
6296                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6297                         break;
6298                 case OP_CVTDQ2PS:
6299                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6300                         break;
6301                 case OP_CVTPD2DQ:
6302                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6303                         break;
6304                 case OP_CVTPD2PS:
6305                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6306                         break;
6307                 case OP_CVTPS2DQ:
6308                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6309                         break;
6310                 case OP_CVTPS2PD:
6311                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6312                         break;
6313                 case OP_CVTTPD2DQ:
6314                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6315                         break;
6316                 case OP_CVTTPS2DQ:
6317                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6318                         break;
6319
6320                 case OP_ICONV_TO_X:
6321                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6322                         break;
6323                 case OP_EXTRACT_I4:
6324                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6325                         break;
6326                 case OP_EXTRACT_I8:
6327                         if (ins->inst_c0) {
6328                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6329                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6330                         } else {
6331                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6332                         }
6333                         break;
6334                 case OP_EXTRACT_I1:
6335                 case OP_EXTRACT_U1:
6336                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6337                         if (ins->inst_c0)
6338                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6339                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6340                         break;
6341                 case OP_EXTRACT_I2:
6342                 case OP_EXTRACT_U2:
6343                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6344                         if (ins->inst_c0)
6345                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6346                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6347                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6348                         break;
6349                 case OP_EXTRACT_R8:
6350                         if (ins->inst_c0)
6351                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6352                         else
6353                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6354                         break;
6355                 case OP_INSERT_I2:
6356                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6357                         break;
6358                 case OP_EXTRACTX_U2:
6359                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6360                         break;
6361                 case OP_INSERTX_U1_SLOW:
6362                         /*sreg1 is the extracted ireg (scratch)
6363                         /sreg2 is the to be inserted ireg (scratch)
6364                         /dreg is the xreg to receive the value*/
6365
6366                         /*clear the bits from the extracted word*/
6367                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6368                         /*shift the value to insert if needed*/
6369                         if (ins->inst_c0 & 1)
6370                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6371                         /*join them together*/
6372                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6373                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6374                         break;
6375                 case OP_INSERTX_I4_SLOW:
6376                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6377                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6378                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6379                         break;
6380                 case OP_INSERTX_I8_SLOW:
6381                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6382                         if (ins->inst_c0)
6383                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6384                         else
6385                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6386                         break;
6387
6388                 case OP_INSERTX_R4_SLOW:
6389                         switch (ins->inst_c0) {
6390                         case 0:
6391                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6392                                 break;
6393                         case 1:
6394                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6395                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6396                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6397                                 break;
6398                         case 2:
6399                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6400                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6401                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6402                                 break;
6403                         case 3:
6404                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6405                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6406                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6407                                 break;
6408                         }
6409                         break;
6410                 case OP_INSERTX_R8_SLOW:
6411                         if (ins->inst_c0)
6412                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6413                         else
6414                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6415                         break;
6416                 case OP_STOREX_MEMBASE_REG:
6417                 case OP_STOREX_MEMBASE:
6418                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6419                         break;
6420                 case OP_LOADX_MEMBASE:
6421                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6422                         break;
6423                 case OP_LOADX_ALIGNED_MEMBASE:
6424                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6425                         break;
6426                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6427                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6428                         break;
6429                 case OP_STOREX_NTA_MEMBASE_REG:
6430                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6431                         break;
6432                 case OP_PREFETCH_MEMBASE:
6433                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6434                         break;
6435
6436                 case OP_XMOVE:
6437                         /*FIXME the peephole pass should have killed this*/
6438                         if (ins->dreg != ins->sreg1)
6439                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6440                         break;
6441                 case OP_XZERO:
6442                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6443                         break;
6444                 case OP_ICONV_TO_R8_RAW:
6445                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6446                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6447                         break;
6448
6449                 case OP_FCONV_TO_R8_X:
6450                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6451                         break;
6452
6453                 case OP_XCONV_R8_TO_I4:
6454                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6455                         switch (ins->backend.source_opcode) {
6456                         case OP_FCONV_TO_I1:
6457                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6458                                 break;
6459                         case OP_FCONV_TO_U1:
6460                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6461                                 break;
6462                         case OP_FCONV_TO_I2:
6463                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6464                                 break;
6465                         case OP_FCONV_TO_U2:
6466                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6467                                 break;
6468                         }
6469                         break;
6470
6471                 case OP_EXPAND_I2:
6472                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6473                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6474                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6475                         break;
6476                 case OP_EXPAND_I4:
6477                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6478                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6479                         break;
6480                 case OP_EXPAND_I8:
6481                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6482                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6483                         break;
6484                 case OP_EXPAND_R4:
6485                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6486                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6487                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6488                         break;
6489                 case OP_EXPAND_R8:
6490                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6491                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6492                         break;
6493 #endif
6494                 case OP_LIVERANGE_START: {
6495                         if (cfg->verbose_level > 1)
6496                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6497                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6498                         break;
6499                 }
6500                 case OP_LIVERANGE_END: {
6501                         if (cfg->verbose_level > 1)
6502                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6503                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6504                         break;
6505                 }
6506                 case OP_NACL_GC_SAFE_POINT: {
6507 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6508                         if (cfg->compile_aot)
6509                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6510                         else {
6511                                 guint8 *br [1];
6512
6513                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6514                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6515                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6516                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6517                                 amd64_patch (br[0], code);
6518                         }
6519 #endif
6520                         break;
6521                 }
6522                 case OP_GC_LIVENESS_DEF:
6523                 case OP_GC_LIVENESS_USE:
6524                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6525                         ins->backend.pc_offset = code - cfg->native_code;
6526                         break;
6527                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6528                         ins->backend.pc_offset = code - cfg->native_code;
6529                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6530                         break;
6531                 default:
6532                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6533                         g_assert_not_reached ();
6534                 }
6535
6536                 if ((code - cfg->native_code - offset) > max_len) {
6537 #if !defined(__native_client_codegen__)
6538                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6539                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6540                         g_assert_not_reached ();
6541 #endif
6542                 }
6543
6544                 last_ins = ins;
6545                 last_offset = offset;
6546         }
6547
6548         cfg->code_len = code - cfg->native_code;
6549 }
6550
6551 #endif /* DISABLE_JIT */
6552
6553 void
6554 mono_arch_register_lowlevel_calls (void)
6555 {
6556         /* The signature doesn't matter */
6557         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6558 }
6559
6560 void
6561 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6562 {
6563         MonoJumpInfo *patch_info;
6564         gboolean compile_aot = !run_cctors;
6565
6566         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6567                 unsigned char *ip = patch_info->ip.i + code;
6568                 unsigned char *target;
6569
6570                 if (compile_aot) {
6571                         switch (patch_info->type) {
6572                         case MONO_PATCH_INFO_BB:
6573                         case MONO_PATCH_INFO_LABEL:
6574                                 break;
6575                         default:
6576                                 /* No need to patch these */
6577                                 continue;
6578                         }
6579                 }
6580
6581                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6582
6583                 switch (patch_info->type) {
6584                 case MONO_PATCH_INFO_NONE:
6585                         continue;
6586                 case MONO_PATCH_INFO_METHOD_REL:
6587                 case MONO_PATCH_INFO_R8:
6588                 case MONO_PATCH_INFO_R4:
6589                         g_assert_not_reached ();
6590                         continue;
6591                 case MONO_PATCH_INFO_BB:
6592                         break;
6593                 default:
6594                         break;
6595                 }
6596
6597                 /*
6598                  * Debug code to help track down problems where the target of a near call is
6599                  * is not valid.
6600                  */
6601                 if (amd64_is_near_call (ip)) {
6602                         gint64 disp = (guint8*)target - (guint8*)ip;
6603
6604                         if (!amd64_is_imm32 (disp)) {
6605                                 printf ("TYPE: %d\n", patch_info->type);
6606                                 switch (patch_info->type) {
6607                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6608                                         printf ("V: %s\n", patch_info->data.name);
6609                                         break;
6610                                 case MONO_PATCH_INFO_METHOD_JUMP:
6611                                 case MONO_PATCH_INFO_METHOD:
6612                                         printf ("V: %s\n", patch_info->data.method->name);
6613                                         break;
6614                                 default:
6615                                         break;
6616                                 }
6617                         }
6618                 }
6619
6620                 amd64_patch (ip, (gpointer)target);
6621         }
6622 }
6623
6624 #ifndef DISABLE_JIT
6625
6626 static int
6627 get_max_epilog_size (MonoCompile *cfg)
6628 {
6629         int max_epilog_size = 16;
6630
6631         if (cfg->method->save_lmf)
6632                 max_epilog_size += 256;
6633
6634         if (mono_jit_trace_calls != NULL)
6635                 max_epilog_size += 50;
6636
6637         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6638                 max_epilog_size += 50;
6639
6640         max_epilog_size += (AMD64_NREG * 2);
6641
6642         return max_epilog_size;
6643 }
6644
6645 /*
6646  * This macro is used for testing whenever the unwinder works correctly at every point
6647  * where an async exception can happen.
6648  */
6649 /* This will generate a SIGSEGV at the given point in the code */
6650 #define async_exc_point(code) do { \
6651     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6652          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6653              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6654          cfg->arch.async_point_count ++; \
6655     } \
6656 } while (0)
6657
6658 guint8 *
6659 mono_arch_emit_prolog (MonoCompile *cfg)
6660 {
6661         MonoMethod *method = cfg->method;
6662         MonoBasicBlock *bb;
6663         MonoMethodSignature *sig;
6664         MonoInst *ins;
6665         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6666         guint8 *code;
6667         CallInfo *cinfo;
6668         MonoInst *lmf_var = cfg->lmf_var;
6669         gboolean args_clobbered = FALSE;
6670         gboolean trace = FALSE;
6671 #ifdef __native_client_codegen__
6672         guint alignment_check;
6673 #endif
6674
6675         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
6676
6677 #if defined(__default_codegen__)
6678         code = cfg->native_code = g_malloc (cfg->code_size);
6679 #elif defined(__native_client_codegen__)
6680         /* native_code_alloc is not 32-byte aligned, native_code is. */
6681         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6682
6683         /* Align native_code to next nearest kNaclAlignment byte. */
6684         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6685         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6686
6687         code = cfg->native_code;
6688
6689         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6690         g_assert (alignment_check == 0);
6691 #endif
6692
6693         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6694                 trace = TRUE;
6695
6696         /* Amount of stack space allocated by register saving code */
6697         pos = 0;
6698
6699         /* Offset between RSP and the CFA */
6700         cfa_offset = 0;
6701
6702         /*
6703          * The prolog consists of the following parts:
6704          * FP present:
6705          * - push rbp, mov rbp, rsp
6706          * - save callee saved regs using pushes
6707          * - allocate frame
6708          * - save rgctx if needed
6709          * - save lmf if needed
6710          * FP not present:
6711          * - allocate frame
6712          * - save rgctx if needed
6713          * - save lmf if needed
6714          * - save callee saved regs using moves
6715          */
6716
6717         // CFA = sp + 8
6718         cfa_offset = 8;
6719         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6720         // IP saved at CFA - 8
6721         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6722         async_exc_point (code);
6723         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6724
6725         if (!cfg->arch.omit_fp) {
6726                 amd64_push_reg (code, AMD64_RBP);
6727                 cfa_offset += 8;
6728                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6729                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6730                 async_exc_point (code);
6731 #ifdef HOST_WIN32
6732                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6733 #endif
6734                 /* These are handled automatically by the stack marking code */
6735                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6736
6737                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6738                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6739                 async_exc_point (code);
6740 #ifdef HOST_WIN32
6741                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6742 #endif
6743         }
6744
6745         /* The param area is always at offset 0 from sp */
6746         /* This needs to be allocated here, since it has to come after the spill area */
6747         if (cfg->arch.no_pushes && cfg->param_area) {
6748                 if (cfg->arch.omit_fp)
6749                         // FIXME:
6750                         g_assert_not_reached ();
6751                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6752         }
6753
6754         if (cfg->arch.omit_fp) {
6755                 /*
6756                  * On enter, the stack is misaligned by the pushing of the return
6757                  * address. It is either made aligned by the pushing of %rbp, or by
6758                  * this.
6759                  */
6760                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6761                 if ((alloc_size % 16) == 0) {
6762                         alloc_size += 8;
6763                         /* Mark the padding slot as NOREF */
6764                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6765                 }
6766         } else {
6767                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6768                 if (cfg->stack_offset != alloc_size) {
6769                         /* Mark the padding slot as NOREF */
6770                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6771                 }
6772                 cfg->arch.sp_fp_offset = alloc_size;
6773                 alloc_size -= pos;
6774         }
6775
6776         cfg->arch.stack_alloc_size = alloc_size;
6777
6778         /* Allocate stack frame */
6779         if (alloc_size) {
6780                 /* See mono_emit_stack_alloc */
6781 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6782                 guint32 remaining_size = alloc_size;
6783                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6784                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6785                 guint32 offset = code - cfg->native_code;
6786                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6787                         while (required_code_size >= (cfg->code_size - offset))
6788                                 cfg->code_size *= 2;
6789                         cfg->native_code = mono_realloc_native_code (cfg);
6790                         code = cfg->native_code + offset;
6791                         cfg->stat_code_reallocs++;
6792                 }
6793
6794                 while (remaining_size >= 0x1000) {
6795                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6796                         if (cfg->arch.omit_fp) {
6797                                 cfa_offset += 0x1000;
6798                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6799                         }
6800                         async_exc_point (code);
6801 #ifdef HOST_WIN32
6802                         if (cfg->arch.omit_fp)
6803                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6804 #endif
6805
6806                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6807                         remaining_size -= 0x1000;
6808                 }
6809                 if (remaining_size) {
6810                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6811                         if (cfg->arch.omit_fp) {
6812                                 cfa_offset += remaining_size;
6813                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6814                                 async_exc_point (code);
6815                         }
6816 #ifdef HOST_WIN32
6817                         if (cfg->arch.omit_fp)
6818                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6819 #endif
6820                 }
6821 #else
6822                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6823                 if (cfg->arch.omit_fp) {
6824                         cfa_offset += alloc_size;
6825                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6826                         async_exc_point (code);
6827                 }
6828 #endif
6829         }
6830
6831         /* Stack alignment check */
6832 #if 0
6833         {
6834                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6835                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6836                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6837                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6838                 amd64_breakpoint (code);
6839         }
6840 #endif
6841
6842 #ifndef TARGET_WIN32
6843         if (mini_get_debug_options ()->init_stacks) {
6844                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6845
6846                 /* Save registers to the red zone */
6847                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6848                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6849
6850                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6851                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6852                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6853
6854                 amd64_cld (code);
6855 #if defined(__default_codegen__)
6856                 amd64_prefix (code, X86_REP_PREFIX);
6857                 amd64_stosl (code);
6858 #elif defined(__native_client_codegen__)
6859                 /* NaCl stos pseudo-instruction */
6860                 amd64_codegen_pre (code);
6861                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6862                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6863                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6864                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6865                 amd64_prefix (code, X86_REP_PREFIX);
6866                 amd64_stosl (code);
6867                 amd64_codegen_post (code);
6868 #endif /* __native_client_codegen__ */
6869
6870                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6871                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6872         }
6873 #endif
6874
6875         /* Save LMF */
6876         if (method->save_lmf) {
6877                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6878         }
6879
6880         /* Save callee saved registers */
6881         if (!method->save_lmf) {
6882                 gint32 save_area_offset;
6883
6884                 if (cfg->arch.omit_fp) {
6885                         save_area_offset = cfg->arch.reg_save_area_offset;
6886                         /* Save caller saved registers after sp is adjusted */
6887                         /* The registers are saved at the bottom of the frame */
6888                         /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6889                 } else {
6890                         /* The registers are saved just below the saved rbp */
6891                         save_area_offset = cfg->arch.reg_save_area_offset;
6892                 }
6893
6894                 for (i = 0; i < AMD64_NREG; ++i)
6895                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6896                                 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6897
6898                                 if (cfg->arch.omit_fp) {
6899                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6900                                         /* These are handled automatically by the stack marking code */
6901                                         mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6902                                 } else {
6903                                         mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6904                                         // FIXME: GC
6905                                 }
6906
6907                                 save_area_offset += 8;
6908                                 async_exc_point (code);
6909                         }
6910         }
6911
6912         /* store runtime generic context */
6913         if (cfg->rgctx_var) {
6914                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6915                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6916
6917                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6918
6919                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6920                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6921         }
6922
6923         /* compute max_length in order to use short forward jumps */
6924         max_epilog_size = get_max_epilog_size (cfg);
6925         if (cfg->opt & MONO_OPT_BRANCH) {
6926                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6927                         MonoInst *ins;
6928                         int max_length = 0;
6929
6930                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6931                                 max_length += 6;
6932                         /* max alignment for loops */
6933                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6934                                 max_length += LOOP_ALIGNMENT;
6935 #ifdef __native_client_codegen__
6936                         /* max alignment for native client */
6937                         max_length += kNaClAlignment;
6938 #endif
6939
6940                         MONO_BB_FOR_EACH_INS (bb, ins) {
6941 #ifdef __native_client_codegen__
6942                                 {
6943                                         int space_in_block = kNaClAlignment -
6944                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6945                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6946                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6947                                                 max_length += space_in_block;
6948                                         }
6949                                 }
6950 #endif  /*__native_client_codegen__*/
6951                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6952                         }
6953
6954                         /* Take prolog and epilog instrumentation into account */
6955                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6956                                 max_length += max_epilog_size;
6957
6958                         bb->max_length = max_length;
6959                 }
6960         }
6961
6962         sig = mono_method_signature (method);
6963         pos = 0;
6964
6965         cinfo = cfg->arch.cinfo;
6966
6967         if (sig->ret->type != MONO_TYPE_VOID) {
6968                 /* Save volatile arguments to the stack */
6969                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6970                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6971         }
6972
6973         /* Keep this in sync with emit_load_volatile_arguments */
6974         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6975                 ArgInfo *ainfo = cinfo->args + i;
6976                 gint32 stack_offset;
6977                 MonoType *arg_type;
6978
6979                 ins = cfg->args [i];
6980
6981                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6982                         /* Unused arguments */
6983                         continue;
6984
6985                 if (sig->hasthis && (i == 0))
6986                         arg_type = &mono_defaults.object_class->byval_arg;
6987                 else
6988                         arg_type = sig->params [i - sig->hasthis];
6989
6990                 stack_offset = ainfo->offset + ARGS_OFFSET;
6991
6992                 if (cfg->globalra) {
6993                         /* All the other moves are done by the register allocator */
6994                         switch (ainfo->storage) {
6995                         case ArgInFloatSSEReg:
6996                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6997                                 break;
6998                         case ArgValuetypeInReg:
6999                                 for (quad = 0; quad < 2; quad ++) {
7000                                         switch (ainfo->pair_storage [quad]) {
7001                                         case ArgInIReg:
7002                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7003                                                 break;
7004                                         case ArgInFloatSSEReg:
7005                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7006                                                 break;
7007                                         case ArgInDoubleSSEReg:
7008                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7009                                                 break;
7010                                         case ArgNone:
7011                                                 break;
7012                                         default:
7013                                                 g_assert_not_reached ();
7014                                         }
7015                                 }
7016                                 break;
7017                         default:
7018                                 break;
7019                         }
7020
7021                         continue;
7022                 }
7023
7024                 /* Save volatile arguments to the stack */
7025                 if (ins->opcode != OP_REGVAR) {
7026                         switch (ainfo->storage) {
7027                         case ArgInIReg: {
7028                                 guint32 size = 8;
7029
7030                                 /* FIXME: I1 etc */
7031                                 /*
7032                                 if (stack_offset & 0x1)
7033                                         size = 1;
7034                                 else if (stack_offset & 0x2)
7035                                         size = 2;
7036                                 else if (stack_offset & 0x4)
7037                                         size = 4;
7038                                 else
7039                                         size = 8;
7040                                 */
7041                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7042
7043                                 /*
7044                                  * Save the original location of 'this',
7045                                  * get_generic_info_from_stack_frame () needs this to properly look up
7046                                  * the argument value during the handling of async exceptions.
7047                                  */
7048                                 if (ins == cfg->args [0]) {
7049                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7050                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7051                                 }
7052                                 break;
7053                         }
7054                         case ArgInFloatSSEReg:
7055                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7056                                 break;
7057                         case ArgInDoubleSSEReg:
7058                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7059                                 break;
7060                         case ArgValuetypeInReg:
7061                                 for (quad = 0; quad < 2; quad ++) {
7062                                         switch (ainfo->pair_storage [quad]) {
7063                                         case ArgInIReg:
7064                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7065                                                 break;
7066                                         case ArgInFloatSSEReg:
7067                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7068                                                 break;
7069                                         case ArgInDoubleSSEReg:
7070                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7071                                                 break;
7072                                         case ArgNone:
7073                                                 break;
7074                                         default:
7075                                                 g_assert_not_reached ();
7076                                         }
7077                                 }
7078                                 break;
7079                         case ArgValuetypeAddrInIReg:
7080                                 if (ainfo->pair_storage [0] == ArgInIReg)
7081                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7082                                 break;
7083                         default:
7084                                 break;
7085                         }
7086                 } else {
7087                         /* Argument allocated to (non-volatile) register */
7088                         switch (ainfo->storage) {
7089                         case ArgInIReg:
7090                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7091                                 break;
7092                         case ArgOnStack:
7093                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7094                                 break;
7095                         default:
7096                                 g_assert_not_reached ();
7097                         }
7098
7099                         if (ins == cfg->args [0]) {
7100                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7101                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7102                         }
7103                 }
7104         }
7105
7106 #ifdef HOST_WIN32
7107         if (method->save_lmf) {
7108                 code = emit_push_lmf (cfg, code, lmf_var->inst_offset, &args_clobbered);
7109         }
7110 #else
7111         args_clobbered = TRUE;
7112 #endif
7113
7114         if (trace) {
7115                 args_clobbered = TRUE;
7116                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7117         }
7118
7119         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7120                 args_clobbered = TRUE;
7121
7122         /*
7123          * Optimize the common case of the first bblock making a call with the same
7124          * arguments as the method. This works because the arguments are still in their
7125          * original argument registers.
7126          * FIXME: Generalize this
7127          */
7128         if (!args_clobbered) {
7129                 MonoBasicBlock *first_bb = cfg->bb_entry;
7130                 MonoInst *next;
7131
7132                 next = mono_bb_first_ins (first_bb);
7133                 if (!next && first_bb->next_bb) {
7134                         first_bb = first_bb->next_bb;
7135                         next = mono_bb_first_ins (first_bb);
7136                 }
7137
7138                 if (first_bb->in_count > 1)
7139                         next = NULL;
7140
7141                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7142                         ArgInfo *ainfo = cinfo->args + i;
7143                         gboolean match = FALSE;
7144
7145                         ins = cfg->args [i];
7146                         if (ins->opcode != OP_REGVAR) {
7147                                 switch (ainfo->storage) {
7148                                 case ArgInIReg: {
7149                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7150                                                 if (next->dreg == ainfo->reg) {
7151                                                         NULLIFY_INS (next);
7152                                                         match = TRUE;
7153                                                 } else {
7154                                                         next->opcode = OP_MOVE;
7155                                                         next->sreg1 = ainfo->reg;
7156                                                         /* Only continue if the instruction doesn't change argument regs */
7157                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7158                                                                 match = TRUE;
7159                                                 }
7160                                         }
7161                                         break;
7162                                 }
7163                                 default:
7164                                         break;
7165                                 }
7166                         } else {
7167                                 /* Argument allocated to (non-volatile) register */
7168                                 switch (ainfo->storage) {
7169                                 case ArgInIReg:
7170                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7171                                                 NULLIFY_INS (next);
7172                                                 match = TRUE;
7173                                         }
7174                                         break;
7175                                 default:
7176                                         break;
7177                                 }
7178                         }
7179
7180                         if (match) {
7181                                 next = next->next;
7182                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7183                                 if (!next)
7184                                         break;
7185                         }
7186                 }
7187         }
7188
7189         if (cfg->gen_seq_points) {
7190                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7191
7192                 /* Initialize seq_point_info_var */
7193                 if (cfg->compile_aot) {
7194                         /* Initialize the variable from a GOT slot */
7195                         /* Same as OP_AOTCONST */
7196                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7197                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7198                         g_assert (info_var->opcode == OP_REGOFFSET);
7199                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7200                 }
7201
7202                 /* Initialize ss_trigger_page_var */
7203                 ins = cfg->arch.ss_trigger_page_var;
7204
7205                 g_assert (ins->opcode == OP_REGOFFSET);
7206
7207                 if (cfg->compile_aot) {
7208                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7209                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7210                 } else {
7211                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7212                 }
7213                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7214         }
7215
7216         cfg->code_len = code - cfg->native_code;
7217
7218         g_assert (cfg->code_len < cfg->code_size);
7219
7220         return code;
7221 }
7222
7223 void
7224 mono_arch_emit_epilog (MonoCompile *cfg)
7225 {
7226         MonoMethod *method = cfg->method;
7227         int quad, pos, i;
7228         guint8 *code;
7229         int max_epilog_size;
7230         CallInfo *cinfo;
7231         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7232
7233         max_epilog_size = get_max_epilog_size (cfg);
7234
7235         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7236                 cfg->code_size *= 2;
7237                 cfg->native_code = mono_realloc_native_code (cfg);
7238                 cfg->stat_code_reallocs++;
7239         }
7240
7241         code = cfg->native_code + cfg->code_len;
7242
7243         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7244                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7245
7246         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7247         pos = 0;
7248
7249         if (method->save_lmf) {
7250 #ifdef HOST_WIN32
7251                 code = emit_pop_lmf (cfg, code, lmf_offset);
7252 #endif
7253
7254                 /* check if we need to restore protection of the stack after a stack overflow */
7255                 if (mono_get_jit_tls_offset () != -1) {
7256                         guint8 *patch;
7257                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7258                         /* we load the value in a separate instruction: this mechanism may be
7259                          * used later as a safer way to do thread interruption
7260                          */
7261                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7262                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7263                         patch = code;
7264                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7265                         /* note that the call trampoline will preserve eax/edx */
7266                         x86_call_reg (code, X86_ECX);
7267                         x86_patch (patch, code);
7268                 } else {
7269                         /* FIXME: maybe save the jit tls in the prolog */
7270                 }
7271
7272                 /* Restore caller saved regs */
7273                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7274                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7275                 }
7276                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
7277                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
7278                 }
7279                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
7280                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
7281                 }
7282                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
7283                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
7284                 }
7285                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
7286                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
7287                 }
7288                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
7289 #if defined(__default_codegen__)
7290                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
7291 #elif defined(__native_client_codegen__)
7292                         g_assert_not_reached();
7293 #endif
7294                 }
7295 #ifdef HOST_WIN32
7296                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
7297                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
7298                 }
7299                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
7300                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
7301                 }
7302 #endif
7303         } else {
7304                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7305
7306                 for (i = 0; i < AMD64_NREG; ++i)
7307                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7308                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7309                                 save_area_offset += 8;
7310                         }
7311         }
7312
7313         /* Load returned vtypes into registers if needed */
7314         cinfo = cfg->arch.cinfo;
7315         if (cinfo->ret.storage == ArgValuetypeInReg) {
7316                 ArgInfo *ainfo = &cinfo->ret;
7317                 MonoInst *inst = cfg->ret;
7318
7319                 for (quad = 0; quad < 2; quad ++) {
7320                         switch (ainfo->pair_storage [quad]) {
7321                         case ArgInIReg:
7322                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7323                                 break;
7324                         case ArgInFloatSSEReg:
7325                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7326                                 break;
7327                         case ArgInDoubleSSEReg:
7328                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7329                                 break;
7330                         case ArgNone:
7331                                 break;
7332                         default:
7333                                 g_assert_not_reached ();
7334                         }
7335                 }
7336         }
7337
7338         if (cfg->arch.omit_fp) {
7339                 if (cfg->arch.stack_alloc_size)
7340                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7341         } else {
7342                 amd64_leave (code);
7343         }
7344         async_exc_point (code);
7345         amd64_ret (code);
7346
7347         cfg->code_len = code - cfg->native_code;
7348
7349         g_assert (cfg->code_len < cfg->code_size);
7350 }
7351
7352 void
7353 mono_arch_emit_exceptions (MonoCompile *cfg)
7354 {
7355         MonoJumpInfo *patch_info;
7356         int nthrows, i;
7357         guint8 *code;
7358         MonoClass *exc_classes [16];
7359         guint8 *exc_throw_start [16], *exc_throw_end [16];
7360         guint32 code_size = 0;
7361
7362         /* Compute needed space */
7363         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7364                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7365                         code_size += 40;
7366                 if (patch_info->type == MONO_PATCH_INFO_R8)
7367                         code_size += 8 + 15; /* sizeof (double) + alignment */
7368                 if (patch_info->type == MONO_PATCH_INFO_R4)
7369                         code_size += 4 + 15; /* sizeof (float) + alignment */
7370                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7371                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7372         }
7373
7374 #ifdef __native_client_codegen__
7375         /* Give us extra room on Native Client.  This could be   */
7376         /* more carefully calculated, but bundle alignment makes */
7377         /* it much trickier, so *2 like other places is good.    */
7378         code_size *= 2;
7379 #endif
7380
7381         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7382                 cfg->code_size *= 2;
7383                 cfg->native_code = mono_realloc_native_code (cfg);
7384                 cfg->stat_code_reallocs++;
7385         }
7386
7387         code = cfg->native_code + cfg->code_len;
7388
7389         /* add code to raise exceptions */
7390         nthrows = 0;
7391         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7392                 switch (patch_info->type) {
7393                 case MONO_PATCH_INFO_EXC: {
7394                         MonoClass *exc_class;
7395                         guint8 *buf, *buf2;
7396                         guint32 throw_ip;
7397
7398                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7399
7400                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7401                         g_assert (exc_class);
7402                         throw_ip = patch_info->ip.i;
7403
7404                         //x86_breakpoint (code);
7405                         /* Find a throw sequence for the same exception class */
7406                         for (i = 0; i < nthrows; ++i)
7407                                 if (exc_classes [i] == exc_class)
7408                                         break;
7409                         if (i < nthrows) {
7410                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7411                                 x86_jump_code (code, exc_throw_start [i]);
7412                                 patch_info->type = MONO_PATCH_INFO_NONE;
7413                         }
7414                         else {
7415                                 buf = code;
7416                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7417                                 buf2 = code;
7418
7419                                 if (nthrows < 16) {
7420                                         exc_classes [nthrows] = exc_class;
7421                                         exc_throw_start [nthrows] = code;
7422                                 }
7423                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7424
7425                                 patch_info->type = MONO_PATCH_INFO_NONE;
7426
7427                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7428
7429                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7430                                 while (buf < buf2)
7431                                         x86_nop (buf);
7432
7433                                 if (nthrows < 16) {
7434                                         exc_throw_end [nthrows] = code;
7435                                         nthrows ++;
7436                                 }
7437                         }
7438                         break;
7439                 }
7440                 default:
7441                         /* do nothing */
7442                         break;
7443                 }
7444                 g_assert(code < cfg->native_code + cfg->code_size);
7445         }
7446
7447         /* Handle relocations with RIP relative addressing */
7448         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7449                 gboolean remove = FALSE;
7450                 guint8 *orig_code = code;
7451
7452                 switch (patch_info->type) {
7453                 case MONO_PATCH_INFO_R8:
7454                 case MONO_PATCH_INFO_R4: {
7455                         guint8 *pos, *patch_pos;
7456                         guint32 target_pos;
7457
7458                         /* The SSE opcodes require a 16 byte alignment */
7459 #if defined(__default_codegen__)
7460                         code = (guint8*)ALIGN_TO (code, 16);
7461 #elif defined(__native_client_codegen__)
7462                         {
7463                                 /* Pad this out with HLT instructions  */
7464                                 /* or we can get garbage bytes emitted */
7465                                 /* which will fail validation          */
7466                                 guint8 *aligned_code;
7467                                 /* extra align to make room for  */
7468                                 /* mov/push below                      */
7469                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7470                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7471                                 /* The technique of hiding data in an  */
7472                                 /* instruction has a problem here: we  */
7473                                 /* need the data aligned to a 16-byte  */
7474                                 /* boundary but the instruction cannot */
7475                                 /* cross the bundle boundary. so only  */
7476                                 /* odd multiples of 16 can be used     */
7477                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7478                                         aligned_code += 16;
7479                                 }
7480                                 while (code < aligned_code) {
7481                                         *(code++) = 0xf4; /* hlt */
7482                                 }
7483                         }
7484 #endif
7485
7486                         pos = cfg->native_code + patch_info->ip.i;
7487                         if (IS_REX (pos [1])) {
7488                                 patch_pos = pos + 5;
7489                                 target_pos = code - pos - 9;
7490                         }
7491                         else {
7492                                 patch_pos = pos + 4;
7493                                 target_pos = code - pos - 8;
7494                         }
7495
7496                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7497 #ifdef __native_client_codegen__
7498                                 /* Hide 64-bit data in a         */
7499                                 /* "mov imm64, r11" instruction. */
7500                                 /* write it before the start of  */
7501                                 /* the data*/
7502                                 *(code-2) = 0x49; /* prefix      */
7503                                 *(code-1) = 0xbb; /* mov X, %r11 */
7504 #endif
7505                                 *(double*)code = *(double*)patch_info->data.target;
7506                                 code += sizeof (double);
7507                         } else {
7508 #ifdef __native_client_codegen__
7509                                 /* Hide 32-bit data in a        */
7510                                 /* "push imm32" instruction.    */
7511                                 *(code-1) = 0x68; /* push */
7512 #endif
7513                                 *(float*)code = *(float*)patch_info->data.target;
7514                                 code += sizeof (float);
7515                         }
7516
7517                         *(guint32*)(patch_pos) = target_pos;
7518
7519                         remove = TRUE;
7520                         break;
7521                 }
7522                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7523                         guint8 *pos;
7524
7525                         if (cfg->compile_aot)
7526                                 continue;
7527
7528                         /*loading is faster against aligned addresses.*/
7529                         code = (guint8*)ALIGN_TO (code, 8);
7530                         memset (orig_code, 0, code - orig_code);
7531
7532                         pos = cfg->native_code + patch_info->ip.i;
7533
7534                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7535                         if (IS_REX (pos [1]))
7536                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7537                         else
7538                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7539
7540                         *(gpointer*)code = (gpointer)patch_info->data.target;
7541                         code += sizeof (gpointer);
7542
7543                         remove = TRUE;
7544                         break;
7545                 }
7546                 default:
7547                         break;
7548                 }
7549
7550                 if (remove) {
7551                         if (patch_info == cfg->patch_info)
7552                                 cfg->patch_info = patch_info->next;
7553                         else {
7554                                 MonoJumpInfo *tmp;
7555
7556                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7557                                         ;
7558                                 tmp->next = patch_info->next;
7559                         }
7560                 }
7561                 g_assert (code < cfg->native_code + cfg->code_size);
7562         }
7563
7564         cfg->code_len = code - cfg->native_code;
7565
7566         g_assert (cfg->code_len < cfg->code_size);
7567
7568 }
7569
7570 #endif /* DISABLE_JIT */
7571
7572 void*
7573 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7574 {
7575         guchar *code = p;
7576         CallInfo *cinfo = NULL;
7577         MonoMethodSignature *sig;
7578         MonoInst *inst;
7579         int i, n, stack_area = 0;
7580
7581         /* Keep this in sync with mono_arch_get_argument_info */
7582
7583         if (enable_arguments) {
7584                 /* Allocate a new area on the stack and save arguments there */
7585                 sig = mono_method_signature (cfg->method);
7586
7587                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7588
7589                 n = sig->param_count + sig->hasthis;
7590
7591                 stack_area = ALIGN_TO (n * 8, 16);
7592
7593                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7594
7595                 for (i = 0; i < n; ++i) {
7596                         inst = cfg->args [i];
7597
7598                         if (inst->opcode == OP_REGVAR)
7599                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7600                         else {
7601                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7602                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7603                         }
7604                 }
7605         }
7606
7607         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7608         amd64_set_reg_template (code, AMD64_ARG_REG1);
7609         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7610         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7611
7612         if (enable_arguments)
7613                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7614
7615         return code;
7616 }
7617
7618 enum {
7619         SAVE_NONE,
7620         SAVE_STRUCT,
7621         SAVE_EAX,
7622         SAVE_EAX_EDX,
7623         SAVE_XMM
7624 };
7625
7626 void*
7627 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7628 {
7629         guchar *code = p;
7630         int save_mode = SAVE_NONE;
7631         MonoMethod *method = cfg->method;
7632         MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7633         int i;
7634
7635         switch (ret_type->type) {
7636         case MONO_TYPE_VOID:
7637                 /* special case string .ctor icall */
7638                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7639                         save_mode = SAVE_EAX;
7640                 else
7641                         save_mode = SAVE_NONE;
7642                 break;
7643         case MONO_TYPE_I8:
7644         case MONO_TYPE_U8:
7645                 save_mode = SAVE_EAX;
7646                 break;
7647         case MONO_TYPE_R4:
7648         case MONO_TYPE_R8:
7649                 save_mode = SAVE_XMM;
7650                 break;
7651         case MONO_TYPE_GENERICINST:
7652                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7653                         save_mode = SAVE_EAX;
7654                         break;
7655                 }
7656                 /* Fall through */
7657         case MONO_TYPE_VALUETYPE:
7658                 save_mode = SAVE_STRUCT;
7659                 break;
7660         default:
7661                 save_mode = SAVE_EAX;
7662                 break;
7663         }
7664
7665         /* Save the result and copy it into the proper argument register */
7666         switch (save_mode) {
7667         case SAVE_EAX:
7668                 amd64_push_reg (code, AMD64_RAX);
7669                 /* Align stack */
7670                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7671                 if (enable_arguments)
7672                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7673                 break;
7674         case SAVE_STRUCT:
7675                 /* FIXME: */
7676                 if (enable_arguments)
7677                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7678                 break;
7679         case SAVE_XMM:
7680                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7681                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7682                 /* Align stack */
7683                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7684                 /*
7685                  * The result is already in the proper argument register so no copying
7686                  * needed.
7687                  */
7688                 break;
7689         case SAVE_NONE:
7690                 break;
7691         default:
7692                 g_assert_not_reached ();
7693         }
7694
7695         /* Set %al since this is a varargs call */
7696         if (save_mode == SAVE_XMM)
7697                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7698         else
7699                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7700
7701         if (preserve_argument_registers) {
7702                 for (i = 0; i < PARAM_REGS; ++i)
7703                         amd64_push_reg (code, param_regs [i]);
7704         }
7705
7706         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7707         amd64_set_reg_template (code, AMD64_ARG_REG1);
7708         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7709
7710         if (preserve_argument_registers) {
7711                 for (i = PARAM_REGS - 1; i >= 0; --i)
7712                         amd64_pop_reg (code, param_regs [i]);
7713         }
7714
7715         /* Restore result */
7716         switch (save_mode) {
7717         case SAVE_EAX:
7718                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7719                 amd64_pop_reg (code, AMD64_RAX);
7720                 break;
7721         case SAVE_STRUCT:
7722                 /* FIXME: */
7723                 break;
7724         case SAVE_XMM:
7725                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7726                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7727                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7728                 break;
7729         case SAVE_NONE:
7730                 break;
7731         default:
7732                 g_assert_not_reached ();
7733         }
7734
7735         return code;
7736 }
7737
7738 void
7739 mono_arch_flush_icache (guint8 *code, gint size)
7740 {
7741         /* Not needed */
7742 }
7743
7744 void
7745 mono_arch_flush_register_windows (void)
7746 {
7747 }
7748
7749 gboolean
7750 mono_arch_is_inst_imm (gint64 imm)
7751 {
7752         return amd64_is_imm32 (imm);
7753 }
7754
7755 /*
7756  * Determine whenever the trap whose info is in SIGINFO is caused by
7757  * integer overflow.
7758  */
7759 gboolean
7760 mono_arch_is_int_overflow (void *sigctx, void *info)
7761 {
7762         MonoContext ctx;
7763         guint8* rip;
7764         int reg;
7765         gint64 value;
7766
7767         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7768
7769         rip = (guint8*)ctx.rip;
7770
7771         if (IS_REX (rip [0])) {
7772                 reg = amd64_rex_b (rip [0]);
7773                 rip ++;
7774         }
7775         else
7776                 reg = 0;
7777
7778         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7779                 /* idiv REG */
7780                 reg += x86_modrm_rm (rip [1]);
7781
7782                 switch (reg) {
7783                 case AMD64_RAX:
7784                         value = ctx.rax;
7785                         break;
7786                 case AMD64_RBX:
7787                         value = ctx.rbx;
7788                         break;
7789                 case AMD64_RCX:
7790                         value = ctx.rcx;
7791                         break;
7792                 case AMD64_RDX:
7793                         value = ctx.rdx;
7794                         break;
7795                 case AMD64_RBP:
7796                         value = ctx.rbp;
7797                         break;
7798                 case AMD64_RSP:
7799                         value = ctx.rsp;
7800                         break;
7801                 case AMD64_RSI:
7802                         value = ctx.rsi;
7803                         break;
7804                 case AMD64_RDI:
7805                         value = ctx.rdi;
7806                         break;
7807                 case AMD64_R12:
7808                         value = ctx.r12;
7809                         break;
7810                 case AMD64_R13:
7811                         value = ctx.r13;
7812                         break;
7813                 case AMD64_R14:
7814                         value = ctx.r14;
7815                         break;
7816                 case AMD64_R15:
7817                         value = ctx.r15;
7818                         break;
7819                 default:
7820                         g_assert_not_reached ();
7821                         reg = -1;
7822                 }
7823
7824                 if (value == -1)
7825                         return TRUE;
7826         }
7827
7828         return FALSE;
7829 }
7830
7831 guint32
7832 mono_arch_get_patch_offset (guint8 *code)
7833 {
7834         return 3;
7835 }
7836
7837 /**
7838  * mono_breakpoint_clean_code:
7839  *
7840  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7841  * breakpoints in the original code, they are removed in the copy.
7842  *
7843  * Returns TRUE if no sw breakpoint was present.
7844  */
7845 gboolean
7846 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7847 {
7848         int i;
7849         gboolean can_write = TRUE;
7850         /*
7851          * If method_start is non-NULL we need to perform bound checks, since we access memory
7852          * at code - offset we could go before the start of the method and end up in a different
7853          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7854          * instead.
7855          */
7856         if (!method_start || code - offset >= method_start) {
7857                 memcpy (buf, code - offset, size);
7858         } else {
7859                 int diff = code - method_start;
7860                 memset (buf, 0, size);
7861                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7862         }
7863         code -= offset;
7864         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7865                 int idx = mono_breakpoint_info_index [i];
7866                 guint8 *ptr;
7867                 if (idx < 1)
7868                         continue;
7869                 ptr = mono_breakpoint_info [idx].address;
7870                 if (ptr >= code && ptr < code + size) {
7871                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7872                         can_write = FALSE;
7873                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7874                         buf [ptr - code] = saved_byte;
7875                 }
7876         }
7877         return can_write;
7878 }
7879
7880 #if defined(__native_client_codegen__)
7881 /* For membase calls, we want the base register. for Native Client,  */
7882 /* all indirect calls have the following sequence with the given sizes: */
7883 /* mov %eXX,%eXX                                [2-3]   */
7884 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7885 /* and $0xffffffffffffffe0,%r11d                [4]     */
7886 /* add %r15,%r11                                [3]     */
7887 /* callq *%r11                                  [3]     */
7888
7889
7890 /* Determine if code points to a NaCl call-through-register sequence, */
7891 /* (i.e., the last 3 instructions listed above) */
7892 int
7893 is_nacl_call_reg_sequence(guint8* code)
7894 {
7895         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7896                                "\x4d\x03\xdf"     /* add */
7897                                "\x41\xff\xd3";   /* call */
7898         return memcmp(code, sequence, 10) == 0;
7899 }
7900
7901 /* Determine if code points to the first opcode of the mov membase component */
7902 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7903 /* (there could be a REX prefix before the opcode but it is ignored) */
7904 static int
7905 is_nacl_indirect_call_membase_sequence(guint8* code)
7906 {
7907                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7908         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7909                /* and that src reg = dest reg */
7910                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7911                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7912                IS_REX(code[2]) &&
7913                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7914                /* and has dst of r11 and base of r15 */
7915                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7916                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7917 }
7918 #endif /* __native_client_codegen__ */
7919
7920 int
7921 mono_arch_get_this_arg_reg (guint8 *code)
7922 {
7923         return AMD64_ARG_REG1;
7924 }
7925
7926 gpointer
7927 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7928 {
7929         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7930 }
7931
7932 #define MAX_ARCH_DELEGATE_PARAMS 10
7933
7934 static gpointer
7935 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7936 {
7937         guint8 *code, *start;
7938         int i;
7939
7940         if (has_target) {
7941                 start = code = mono_global_codeman_reserve (64);
7942
7943                 /* Replace the this argument with the target */
7944                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7945                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7946                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7947
7948                 g_assert ((code - start) < 64);
7949         } else {
7950                 start = code = mono_global_codeman_reserve (64);
7951
7952                 if (param_count == 0) {
7953                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7954                 } else {
7955                         /* We have to shift the arguments left */
7956                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7957                         for (i = 0; i < param_count; ++i) {
7958 #ifdef HOST_WIN32
7959                                 if (i < 3)
7960                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7961                                 else
7962                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7963 #else
7964                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7965 #endif
7966                         }
7967
7968                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7969                 }
7970                 g_assert ((code - start) < 64);
7971         }
7972
7973         nacl_global_codeman_validate(&start, 64, &code);
7974
7975         mono_debug_add_delegate_trampoline (start, code - start);
7976
7977         if (code_len)
7978                 *code_len = code - start;
7979
7980
7981         if (mono_jit_map_is_enabled ()) {
7982                 char *buff;
7983                 if (has_target)
7984                         buff = (char*)"delegate_invoke_has_target";
7985                 else
7986                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7987                 mono_emit_jit_tramp (start, code - start, buff);
7988                 if (!has_target)
7989                         g_free (buff);
7990         }
7991
7992         return start;
7993 }
7994
7995 /*
7996  * mono_arch_get_delegate_invoke_impls:
7997  *
7998  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7999  * trampolines.
8000  */
8001 GSList*
8002 mono_arch_get_delegate_invoke_impls (void)
8003 {
8004         GSList *res = NULL;
8005         guint8 *code;
8006         guint32 code_len;
8007         int i;
8008         char *tramp_name;
8009
8010         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
8011         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
8012
8013         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
8014                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
8015                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
8016                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
8017                 g_free (tramp_name);
8018         }
8019
8020         return res;
8021 }
8022
8023 gpointer
8024 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8025 {
8026         guint8 *code, *start;
8027         int i;
8028
8029         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8030                 return NULL;
8031
8032         /* FIXME: Support more cases */
8033         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
8034                 return NULL;
8035
8036         if (has_target) {
8037                 static guint8* cached = NULL;
8038
8039                 if (cached)
8040                         return cached;
8041
8042                 if (mono_aot_only)
8043                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8044                 else
8045                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
8046
8047                 mono_memory_barrier ();
8048
8049                 cached = start;
8050         } else {
8051                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8052                 for (i = 0; i < sig->param_count; ++i)
8053                         if (!mono_is_regsize_var (sig->params [i]))
8054                                 return NULL;
8055                 if (sig->param_count > 4)
8056                         return NULL;
8057
8058                 code = cache [sig->param_count];
8059                 if (code)
8060                         return code;
8061
8062                 if (mono_aot_only) {
8063                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8064                         start = mono_aot_get_trampoline (name);
8065                         g_free (name);
8066                 } else {
8067                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8068                 }
8069
8070                 mono_memory_barrier ();
8071
8072                 cache [sig->param_count] = start;
8073         }
8074
8075         return start;
8076 }
8077 void
8078 mono_arch_finish_init (void)
8079 {
8080 #ifdef HOST_WIN32
8081         /*
8082          * We need to init this multiple times, since when we are first called, the key might not
8083          * be initialized yet.
8084          */
8085         jit_tls_offset = mono_get_jit_tls_key ();
8086
8087         /* Only 64 tls entries can be accessed using inline code */
8088         if (jit_tls_offset >= 64)
8089                 jit_tls_offset = -1;
8090 #else
8091 #ifdef MONO_XEN_OPT
8092         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8093 #endif
8094 #endif
8095 }
8096
8097 void
8098 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8099 {
8100 }
8101
8102 #ifdef MONO_ARCH_HAVE_IMT
8103
8104 #if defined(__default_codegen__)
8105 #define CMP_SIZE (6 + 1)
8106 #define CMP_REG_REG_SIZE (4 + 1)
8107 #define BR_SMALL_SIZE 2
8108 #define BR_LARGE_SIZE 6
8109 #define MOV_REG_IMM_SIZE 10
8110 #define MOV_REG_IMM_32BIT_SIZE 6
8111 #define JUMP_REG_SIZE (2 + 1)
8112 #elif defined(__native_client_codegen__)
8113 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8114 #define CMP_SIZE ((6 + 1) * 2 - 1)
8115 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8116 #define BR_SMALL_SIZE (2 * 2 - 1)
8117 #define BR_LARGE_SIZE (6 * 2 - 1)
8118 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8119 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8120 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8121 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8122 /* Jump membase's size is large and unpredictable    */
8123 /* in native client, just pad it out a whole bundle. */
8124 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8125 #endif
8126
8127 static int
8128 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8129 {
8130         int i, distance = 0;
8131         for (i = start; i < target; ++i)
8132                 distance += imt_entries [i]->chunk_size;
8133         return distance;
8134 }
8135
8136 /*
8137  * LOCKING: called with the domain lock held
8138  */
8139 gpointer
8140 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8141         gpointer fail_tramp)
8142 {
8143         int i;
8144         int size = 0;
8145         guint8 *code, *start;
8146         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8147
8148         for (i = 0; i < count; ++i) {
8149                 MonoIMTCheckItem *item = imt_entries [i];
8150                 if (item->is_equals) {
8151                         if (item->check_target_idx) {
8152                                 if (!item->compare_done) {
8153                                         if (amd64_is_imm32 (item->key))
8154                                                 item->chunk_size += CMP_SIZE;
8155                                         else
8156                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8157                                 }
8158                                 if (item->has_target_code) {
8159                                         item->chunk_size += MOV_REG_IMM_SIZE;
8160                                 } else {
8161                                         if (vtable_is_32bit)
8162                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8163                                         else
8164                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8165 #ifdef __native_client_codegen__
8166                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8167 #endif
8168                                 }
8169                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8170                         } else {
8171                                 if (fail_tramp) {
8172                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8173                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8174                                 } else {
8175                                         if (vtable_is_32bit)
8176                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8177                                         else
8178                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8179                                         item->chunk_size += JUMP_REG_SIZE;
8180                                         /* with assert below:
8181                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8182                                          */
8183 #ifdef __native_client_codegen__
8184                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8185 #endif
8186                                 }
8187                         }
8188                 } else {
8189                         if (amd64_is_imm32 (item->key))
8190                                 item->chunk_size += CMP_SIZE;
8191                         else
8192                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8193                         item->chunk_size += BR_LARGE_SIZE;
8194                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8195                 }
8196                 size += item->chunk_size;
8197         }
8198 #if defined(__native_client__) && defined(__native_client_codegen__)
8199         /* In Native Client, we don't re-use thunks, allocate from the */
8200         /* normal code manager paths. */
8201         code = mono_domain_code_reserve (domain, size);
8202 #else
8203         if (fail_tramp)
8204                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8205         else
8206                 code = mono_domain_code_reserve (domain, size);
8207 #endif
8208         start = code;
8209         for (i = 0; i < count; ++i) {
8210                 MonoIMTCheckItem *item = imt_entries [i];
8211                 item->code_target = code;
8212                 if (item->is_equals) {
8213                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8214
8215                         if (item->check_target_idx || fail_case) {
8216                                 if (!item->compare_done || fail_case) {
8217                                         if (amd64_is_imm32 (item->key))
8218                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8219                                         else {
8220                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8221                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8222                                         }
8223                                 }
8224                                 item->jmp_code = code;
8225                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8226                                 if (item->has_target_code) {
8227                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8228                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8229                                 } else {
8230                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8231                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8232                                 }
8233
8234                                 if (fail_case) {
8235                                         amd64_patch (item->jmp_code, code);
8236                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8237                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8238                                         item->jmp_code = NULL;
8239                                 }
8240                         } else {
8241                                 /* enable the commented code to assert on wrong method */
8242 #if 0
8243                                 if (amd64_is_imm32 (item->key))
8244                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8245                                 else {
8246                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8247                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8248                                 }
8249                                 item->jmp_code = code;
8250                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8251                                 /* See the comment below about R10 */
8252                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8253                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8254                                 amd64_patch (item->jmp_code, code);
8255                                 amd64_breakpoint (code);
8256                                 item->jmp_code = NULL;
8257 #else
8258                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8259                                    needs to be preserved.  R10 needs
8260                                    to be preserved for calls which
8261                                    require a runtime generic context,
8262                                    but interface calls don't. */
8263                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8264                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8265 #endif
8266                         }
8267                 } else {
8268                         if (amd64_is_imm32 (item->key))
8269                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8270                         else {
8271                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8272                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8273                         }
8274                         item->jmp_code = code;
8275                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8276                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8277                         else
8278                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8279                 }
8280                 g_assert (code - item->code_target <= item->chunk_size);
8281         }
8282         /* patch the branches to get to the target items */
8283         for (i = 0; i < count; ++i) {
8284                 MonoIMTCheckItem *item = imt_entries [i];
8285                 if (item->jmp_code) {
8286                         if (item->check_target_idx) {
8287                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8288                         }
8289                 }
8290         }
8291
8292         if (!fail_tramp)
8293                 mono_stats.imt_thunks_size += code - start;
8294         g_assert (code - start <= size);
8295
8296         nacl_domain_code_validate(domain, &start, size, &code);
8297
8298         return start;
8299 }
8300
8301 MonoMethod*
8302 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8303 {
8304         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8305 }
8306 #endif
8307
8308 MonoVTable*
8309 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8310 {
8311         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8312 }
8313
8314 GSList*
8315 mono_arch_get_cie_program (void)
8316 {
8317         GSList *l = NULL;
8318
8319         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8320         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8321
8322         return l;
8323 }
8324
8325 MonoInst*
8326 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8327 {
8328         MonoInst *ins = NULL;
8329         int opcode = 0;
8330
8331         if (cmethod->klass == mono_defaults.math_class) {
8332                 if (strcmp (cmethod->name, "Sin") == 0) {
8333                         opcode = OP_SIN;
8334                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8335                         opcode = OP_COS;
8336                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8337                         opcode = OP_SQRT;
8338                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8339                         opcode = OP_ABS;
8340                 }
8341
8342                 if (opcode) {
8343                         MONO_INST_NEW (cfg, ins, opcode);
8344                         ins->type = STACK_R8;
8345                         ins->dreg = mono_alloc_freg (cfg);
8346                         ins->sreg1 = args [0]->dreg;
8347                         MONO_ADD_INS (cfg->cbb, ins);
8348                 }
8349
8350                 opcode = 0;
8351                 if (cfg->opt & MONO_OPT_CMOV) {
8352                         if (strcmp (cmethod->name, "Min") == 0) {
8353                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8354                                         opcode = OP_IMIN;
8355                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8356                                         opcode = OP_IMIN_UN;
8357                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8358                                         opcode = OP_LMIN;
8359                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8360                                         opcode = OP_LMIN_UN;
8361                         } else if (strcmp (cmethod->name, "Max") == 0) {
8362                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8363                                         opcode = OP_IMAX;
8364                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8365                                         opcode = OP_IMAX_UN;
8366                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8367                                         opcode = OP_LMAX;
8368                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8369                                         opcode = OP_LMAX_UN;
8370                         }
8371                 }
8372
8373                 if (opcode) {
8374                         MONO_INST_NEW (cfg, ins, opcode);
8375                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8376                         ins->dreg = mono_alloc_ireg (cfg);
8377                         ins->sreg1 = args [0]->dreg;
8378                         ins->sreg2 = args [1]->dreg;
8379                         MONO_ADD_INS (cfg->cbb, ins);
8380                 }
8381
8382 #if 0
8383                 /* OP_FREM is not IEEE compatible */
8384                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8385                         MONO_INST_NEW (cfg, ins, OP_FREM);
8386                         ins->inst_i0 = args [0];
8387                         ins->inst_i1 = args [1];
8388                 }
8389 #endif
8390         }
8391
8392         /*
8393          * Can't implement CompareExchange methods this way since they have
8394          * three arguments.
8395          */
8396
8397         return ins;
8398 }
8399
8400 gboolean
8401 mono_arch_print_tree (MonoInst *tree, int arity)
8402 {
8403         return 0;
8404 }
8405
8406 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8407
8408 mgreg_t
8409 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8410 {
8411         switch (reg) {
8412         case AMD64_RCX: return ctx->rcx;
8413         case AMD64_RDX: return ctx->rdx;
8414         case AMD64_RBX: return ctx->rbx;
8415         case AMD64_RBP: return ctx->rbp;
8416         case AMD64_RSP: return ctx->rsp;
8417         default:
8418                 return _CTX_REG (ctx, rax, reg);
8419         }
8420 }
8421
8422 void
8423 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8424 {
8425         switch (reg) {
8426         case AMD64_RCX:
8427                 ctx->rcx = val;
8428                 break;
8429         case AMD64_RDX:
8430                 ctx->rdx = val;
8431                 break;
8432         case AMD64_RBX:
8433                 ctx->rbx = val;
8434                 break;
8435         case AMD64_RBP:
8436                 ctx->rbp = val;
8437                 break;
8438         case AMD64_RSP:
8439                 ctx->rsp = val;
8440                 break;
8441         default:
8442                 _CTX_REG (ctx, rax, reg) = val;
8443         }
8444 }
8445
8446 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8447 gpointer
8448 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8449 {
8450         int offset;
8451         gpointer *sp, old_value;
8452         char *bp;
8453         const unsigned char *handler;
8454
8455         /*Decode the first instruction to figure out where did we store the spvar*/
8456         /*Our jit MUST generate the following:
8457          mov    %rsp, ?(%rbp)
8458
8459          Which is encoded as: REX.W 0x89 mod_rm
8460          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8461                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8462                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8463
8464         FIXME can we generate frameless methods on this case?
8465
8466         */
8467         handler = clause->handler_start;
8468
8469         /*REX.W*/
8470         if (*handler != 0x48)
8471                 return NULL;
8472         ++handler;
8473
8474         /*mov r, r/m */
8475         if (*handler != 0x89)
8476                 return NULL;
8477         ++handler;
8478
8479         if (*handler == 0x65)
8480                 offset = *(signed char*)(handler + 1);
8481         else if (*handler == 0xA5)
8482                 offset = *(int*)(handler + 1);
8483         else
8484                 return NULL;
8485
8486         /*Load the spvar*/
8487         bp = MONO_CONTEXT_GET_BP (ctx);
8488         sp = *(gpointer*)(bp + offset);
8489
8490         old_value = *sp;
8491         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8492                 return old_value;
8493
8494         *sp = new_value;
8495
8496         return old_value;
8497 }
8498
8499 /*
8500  * mono_arch_emit_load_aotconst:
8501  *
8502  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8503  * TARGET from the mscorlib GOT in full-aot code.
8504  * On AMD64, the result is placed into R11.
8505  */
8506 guint8*
8507 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8508 {
8509         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8510         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8511
8512         return code;
8513 }
8514
8515 /*
8516  * mono_arch_get_trampolines:
8517  *
8518  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8519  * for AOT.
8520  */
8521 GSList *
8522 mono_arch_get_trampolines (gboolean aot)
8523 {
8524         return mono_amd64_get_exception_trampolines (aot);
8525 }
8526
8527 /* Soft Debug support */
8528 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8529
8530 /*
8531  * mono_arch_set_breakpoint:
8532  *
8533  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8534  * The location should contain code emitted by OP_SEQ_POINT.
8535  */
8536 void
8537 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8538 {
8539         guint8 *code = ip;
8540         guint8 *orig_code = code;
8541
8542         if (ji->from_aot) {
8543                 guint32 native_offset = ip - (guint8*)ji->code_start;
8544                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8545
8546                 g_assert (info->bp_addrs [native_offset] == 0);
8547                 info->bp_addrs [native_offset] = bp_trigger_page;
8548         } else {
8549                 /*
8550                  * In production, we will use int3 (has to fix the size in the md
8551                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8552                  * instead.
8553                  */
8554                 g_assert (code [0] == 0x90);
8555                 if (breakpoint_size == 8) {
8556                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8557                 } else {
8558                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8559                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8560                 }
8561
8562                 g_assert (code - orig_code == breakpoint_size);
8563         }
8564 }
8565
8566 /*
8567  * mono_arch_clear_breakpoint:
8568  *
8569  *   Clear the breakpoint at IP.
8570  */
8571 void
8572 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8573 {
8574         guint8 *code = ip;
8575         int i;
8576
8577         if (ji->from_aot) {
8578                 guint32 native_offset = ip - (guint8*)ji->code_start;
8579                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8580
8581                 g_assert (info->bp_addrs [native_offset] == 0);
8582                 info->bp_addrs [native_offset] = info;
8583         } else {
8584                 for (i = 0; i < breakpoint_size; ++i)
8585                         x86_nop (code);
8586         }
8587 }
8588
8589 gboolean
8590 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8591 {
8592 #ifdef HOST_WIN32
8593         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8594         return FALSE;
8595 #else
8596         siginfo_t* sinfo = (siginfo_t*) info;
8597         /* Sometimes the address is off by 4 */
8598         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8599                 return TRUE;
8600         else
8601                 return FALSE;
8602 #endif
8603 }
8604
8605 /*
8606  * mono_arch_skip_breakpoint:
8607  *
8608  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8609  * we resume, the instruction is not executed again.
8610  */
8611 void
8612 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8613 {
8614         if (ji->from_aot) {
8615                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8616                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8617         } else {
8618                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8619         }
8620 }
8621
8622 /*
8623  * mono_arch_start_single_stepping:
8624  *
8625  *   Start single stepping.
8626  */
8627 void
8628 mono_arch_start_single_stepping (void)
8629 {
8630         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8631 }
8632
8633 /*
8634  * mono_arch_stop_single_stepping:
8635  *
8636  *   Stop single stepping.
8637  */
8638 void
8639 mono_arch_stop_single_stepping (void)
8640 {
8641         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8642 }
8643
8644 /*
8645  * mono_arch_is_single_step_event:
8646  *
8647  *   Return whenever the machine state in SIGCTX corresponds to a single
8648  * step event.
8649  */
8650 gboolean
8651 mono_arch_is_single_step_event (void *info, void *sigctx)
8652 {
8653 #ifdef HOST_WIN32
8654         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8655         return FALSE;
8656 #else
8657         siginfo_t* sinfo = (siginfo_t*) info;
8658         /* Sometimes the address is off by 4 */
8659         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8660                 return TRUE;
8661         else
8662                 return FALSE;
8663 #endif
8664 }
8665
8666 /*
8667  * mono_arch_skip_single_step:
8668  *
8669  *   Modify CTX so the ip is placed after the single step trigger instruction,
8670  * we resume, the instruction is not executed again.
8671  */
8672 void
8673 mono_arch_skip_single_step (MonoContext *ctx)
8674 {
8675         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8676 }
8677
8678 /*
8679  * mono_arch_create_seq_point_info:
8680  *
8681  *   Return a pointer to a data structure which is used by the sequence
8682  * point implementation in AOTed code.
8683  */
8684 gpointer
8685 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8686 {
8687         SeqPointInfo *info;
8688         MonoJitInfo *ji;
8689         int i;
8690
8691         // FIXME: Add a free function
8692
8693         mono_domain_lock (domain);
8694         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8695                                                                 code);
8696         mono_domain_unlock (domain);
8697
8698         if (!info) {
8699                 ji = mono_jit_info_table_find (domain, (char*)code);
8700                 g_assert (ji);
8701
8702                 // FIXME: Optimize the size
8703                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8704
8705                 info->ss_trigger_page = ss_trigger_page;
8706                 info->bp_trigger_page = bp_trigger_page;
8707                 /* Initialize to a valid address */
8708                 for (i = 0; i < ji->code_size; ++i)
8709                         info->bp_addrs [i] = info;
8710
8711                 mono_domain_lock (domain);
8712                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8713                                                          code, info);
8714                 mono_domain_unlock (domain);
8715         }
8716
8717         return info;
8718 }
8719
8720 void
8721 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8722 {
8723         ext->lmf.previous_lmf = prev_lmf;
8724         /* Mark that this is a MonoLMFExt */
8725         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8726         ext->lmf.rsp = (gssize)ext;
8727 }
8728
8729 #endif