2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/abi-details.h>
24 #include <mono/metadata/appdomain.h>
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/threads.h>
27 #include <mono/metadata/profiler-private.h>
28 #include <mono/metadata/mono-debug.h>
29 #include <mono/metadata/gc-internal.h>
30 #include <mono/utils/mono-math.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-tls.h>
34 #include <mono/utils/mono-hwcap-x86.h>
38 #include "mini-amd64.h"
39 #include "cpu-amd64.h"
40 #include "debugger-agent.h"
44 static gboolean optimize_for_xen = TRUE;
46 #define optimize_for_xen 0
49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
56 /* Under windows, the calling convention is never stdcall */
57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
62 /* This mutex protects architecture specific caches */
63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
65 static mono_mutex_t mini_arch_mutex;
68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
71 * The code generated for sequence points reads from this location, which is
72 * made read-only when single stepping is enabled.
74 static gpointer ss_trigger_page;
76 /* Enabled breakpoints read from this trigger page */
77 static gpointer bp_trigger_page;
79 /* The size of the breakpoint sequence */
80 static int breakpoint_size;
82 /* The size of the breakpoint instruction causing the actual fault */
83 static int breakpoint_fault_size;
85 /* The size of the single step instruction causing the actual fault */
86 static int single_step_fault_size;
88 /* Offset between fp and the first argument in the callee */
89 #define ARGS_OFFSET 16
90 #define GP_SCRATCH_REG AMD64_R11
93 * AMD64 register usage:
94 * - callee saved registers are used for global register allocation
95 * - %r11 is used for materializing 64 bit constants in opcodes
96 * - the rest is used for local allocation
100 * Floating point comparison results:
110 mono_arch_regname (int reg)
113 case AMD64_RAX: return "%rax";
114 case AMD64_RBX: return "%rbx";
115 case AMD64_RCX: return "%rcx";
116 case AMD64_RDX: return "%rdx";
117 case AMD64_RSP: return "%rsp";
118 case AMD64_RBP: return "%rbp";
119 case AMD64_RDI: return "%rdi";
120 case AMD64_RSI: return "%rsi";
121 case AMD64_R8: return "%r8";
122 case AMD64_R9: return "%r9";
123 case AMD64_R10: return "%r10";
124 case AMD64_R11: return "%r11";
125 case AMD64_R12: return "%r12";
126 case AMD64_R13: return "%r13";
127 case AMD64_R14: return "%r14";
128 case AMD64_R15: return "%r15";
133 static const char * packed_xmmregs [] = {
134 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
135 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
138 static const char * single_xmmregs [] = {
139 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
140 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
144 mono_arch_fregname (int reg)
146 if (reg < AMD64_XMM_NREG)
147 return single_xmmregs [reg];
153 mono_arch_xregname (int reg)
155 if (reg < AMD64_XMM_NREG)
156 return packed_xmmregs [reg];
165 return mono_debug_count ();
171 static inline gboolean
172 amd64_is_near_call (guint8 *code)
175 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
178 return code [0] == 0xe8;
181 #ifdef __native_client_codegen__
183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
184 /* for any given instruction. For instance, amd64_call_reg resolves to */
185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
186 /* We only want to force bundle alignment for the top level instruction, */
187 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
188 static MonoNativeTlsKey nacl_instruction_depth;
190 static MonoNativeTlsKey nacl_rex_tag;
191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
194 amd64_nacl_clear_legacy_prefix_tag ()
196 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
200 amd64_nacl_tag_legacy_prefix (guint8* code)
202 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
203 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
207 amd64_nacl_tag_rex (guint8* code)
209 mono_native_tls_set_value (nacl_rex_tag, code);
213 amd64_nacl_get_legacy_prefix_tag ()
215 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
219 amd64_nacl_get_rex_tag ()
221 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
224 /* Increment the instruction "depth" described above */
226 amd64_nacl_instruction_pre ()
228 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
230 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
234 /* alignment if depth == 0 (top level instruction) */
235 /* IN: start, end pointers to instruction beginning and end */
236 /* OUT: start, end pointers to beginning and end after possible alignment */
237 /* GLOBALS: nacl_instruction_depth defined above */
239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
241 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
243 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
245 g_assert ( depth >= 0 );
247 uintptr_t space_in_block;
249 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
250 /* if legacy prefix is present, and if it was emitted before */
251 /* the start of the instruction sequence, adjust the start */
252 if (prefix != NULL && prefix < *start) {
253 g_assert (*start - prefix <= 3);/* only 3 are allowed */
256 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
257 instlen = (uintptr_t)(*end - *start);
258 /* Only check for instructions which are less than */
259 /* kNaClAlignment. The only instructions that should ever */
260 /* be that long are call sequences, which are already */
261 /* padded out to align the return to the next bundle. */
262 if (instlen > space_in_block && instlen < kNaClAlignment) {
263 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
264 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
265 const size_t length = (size_t)((*end)-(*start));
266 g_assert (length < MAX_NACL_INST_LENGTH);
268 memcpy (copy_of_instruction, *start, length);
269 *start = mono_arch_nacl_pad (*start, space_in_block);
270 memcpy (*start, copy_of_instruction, length);
271 *end = *start + length;
273 amd64_nacl_clear_legacy_prefix_tag ();
274 amd64_nacl_tag_rex (NULL);
278 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
279 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
280 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
281 /* make sure the upper 32-bits are cleared, and use that register in the */
282 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
284 /* pointer to current instruction stream (in the */
285 /* middle of an instruction, after opcode is emitted) */
286 /* basereg/offset/dreg */
287 /* operands of normal membase address */
289 /* pointer to the end of the membase/memindex emit */
290 /* GLOBALS: nacl_rex_tag */
291 /* position in instruction stream that rex prefix was emitted */
292 /* nacl_legacy_prefix_tag */
293 /* (possibly NULL) position in instruction of legacy x86 prefix */
295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
297 gint8 true_basereg = basereg;
299 /* Cache these values, they might change */
300 /* as new instructions are emitted below. */
301 guint8* rex_tag = amd64_nacl_get_rex_tag ();
302 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
304 /* 'basereg' is given masked to 0x7 at this point, so check */
305 /* the rex prefix to see if this is an extended register. */
306 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
310 #define X86_LEA_OPCODE (0x8D)
312 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
313 guint8* old_instruction_start;
315 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
316 /* 32-bits of the old base register (new index register) */
318 guint8* buf_ptr = buf;
321 g_assert (rex_tag != NULL);
323 if (IS_REX(*rex_tag)) {
324 /* The old rex.B should be the new rex.X */
325 if (*rex_tag & AMD64_REX_B) {
326 *rex_tag |= AMD64_REX_X;
328 /* Since our new base is %r15 set rex.B */
329 *rex_tag |= AMD64_REX_B;
331 /* Shift the instruction by one byte */
332 /* so we can insert a rex prefix */
333 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
335 /* New rex prefix only needs rex.B for %r15 base */
336 *rex_tag = AMD64_REX(AMD64_REX_B);
339 if (legacy_prefix_tag) {
340 old_instruction_start = legacy_prefix_tag;
342 old_instruction_start = rex_tag;
345 /* Clears the upper 32-bits of the previous base register */
346 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
347 insert_len = buf_ptr - buf;
349 /* Move the old instruction forward to make */
350 /* room for 'mov' stored in 'buf_ptr' */
351 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
353 memcpy (old_instruction_start, buf, insert_len);
355 /* Sandboxed replacement for the normal membase_emit */
356 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
359 /* Normal default behavior, emit membase memory location */
360 x86_membase_emit_body (*code, dreg, basereg, offset);
365 static inline unsigned char*
366 amd64_skip_nops (unsigned char* code)
371 if ( code[0] == 0x90) {
375 if ( code[0] == 0x66 && code[1] == 0x90) {
379 if (code[0] == 0x0f && code[1] == 0x1f
380 && code[2] == 0x00) {
384 if (code[0] == 0x0f && code[1] == 0x1f
385 && code[2] == 0x40 && code[3] == 0x00) {
389 if (code[0] == 0x0f && code[1] == 0x1f
390 && code[2] == 0x44 && code[3] == 0x00
391 && code[4] == 0x00) {
395 if (code[0] == 0x66 && code[1] == 0x0f
396 && code[2] == 0x1f && code[3] == 0x44
397 && code[4] == 0x00 && code[5] == 0x00) {
401 if (code[0] == 0x0f && code[1] == 0x1f
402 && code[2] == 0x80 && code[3] == 0x00
403 && code[4] == 0x00 && code[5] == 0x00
404 && code[6] == 0x00) {
408 if (code[0] == 0x0f && code[1] == 0x1f
409 && code[2] == 0x84 && code[3] == 0x00
410 && code[4] == 0x00 && code[5] == 0x00
411 && code[6] == 0x00 && code[7] == 0x00) {
420 mono_arch_nacl_skip_nops (guint8* code)
422 return amd64_skip_nops(code);
425 #endif /*__native_client_codegen__*/
428 amd64_patch (unsigned char* code, gpointer target)
432 #ifdef __native_client_codegen__
433 code = amd64_skip_nops (code);
435 #if defined(__native_client_codegen__) && defined(__native_client__)
436 if (nacl_is_code_address (code)) {
437 /* For tail calls, code is patched after being installed */
438 /* but not through the normal "patch callsite" method. */
439 unsigned char buf[kNaClAlignment];
440 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
442 memcpy (buf, aligned_code, kNaClAlignment);
443 /* Patch a temp buffer of bundle size, */
444 /* then install to actual location. */
445 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
446 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
450 target = nacl_modify_patch_target (target);
454 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
459 if ((code [0] & 0xf8) == 0xb8) {
460 /* amd64_set_reg_template */
461 *(guint64*)(code + 1) = (guint64)target;
463 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
464 /* mov 0(%rip), %dreg */
465 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
467 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
468 /* call *<OFFSET>(%rip) */
469 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
471 else if (code [0] == 0xe8) {
473 gint64 disp = (guint8*)target - (guint8*)code;
474 g_assert (amd64_is_imm32 (disp));
475 x86_patch (code, (unsigned char*)target);
478 x86_patch (code, (unsigned char*)target);
482 mono_amd64_patch (unsigned char* code, gpointer target)
484 amd64_patch (code, target);
493 ArgValuetypeAddrInIReg,
494 ArgNone /* only in pair_storage */
502 /* Only if storage == ArgValuetypeInReg */
503 ArgStorage pair_storage [2];
505 /* The size of each pair */
515 gboolean need_stack_align;
516 gboolean vtype_retaddr;
517 /* The index of the vret arg in the argument list */
524 #define DEBUG(a) if (cfg->verbose_level > 1) a
527 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
529 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
533 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
537 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
539 ainfo->offset = *stack_size;
541 if (*gr >= PARAM_REGS) {
542 ainfo->storage = ArgOnStack;
543 /* Since the same stack slot size is used for all arg */
544 /* types, it needs to be big enough to hold them all */
545 (*stack_size) += sizeof(mgreg_t);
548 ainfo->storage = ArgInIReg;
549 ainfo->reg = param_regs [*gr];
555 #define FLOAT_PARAM_REGS 4
557 #define FLOAT_PARAM_REGS 8
561 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
563 ainfo->offset = *stack_size;
565 if (*gr >= FLOAT_PARAM_REGS) {
566 ainfo->storage = ArgOnStack;
567 /* Since the same stack slot size is used for both float */
568 /* types, it needs to be big enough to hold them both */
569 (*stack_size) += sizeof(mgreg_t);
572 /* A double register */
574 ainfo->storage = ArgInDoubleSSEReg;
576 ainfo->storage = ArgInFloatSSEReg;
582 typedef enum ArgumentClass {
590 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
592 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
595 ptype = mini_type_get_underlying_type (gsctx, type);
596 switch (ptype->type) {
605 case MONO_TYPE_STRING:
606 case MONO_TYPE_OBJECT:
607 case MONO_TYPE_CLASS:
608 case MONO_TYPE_SZARRAY:
610 case MONO_TYPE_FNPTR:
611 case MONO_TYPE_ARRAY:
614 class2 = ARG_CLASS_INTEGER;
619 class2 = ARG_CLASS_INTEGER;
621 class2 = ARG_CLASS_SSE;
625 case MONO_TYPE_TYPEDBYREF:
626 g_assert_not_reached ();
628 case MONO_TYPE_GENERICINST:
629 if (!mono_type_generic_inst_is_valuetype (ptype)) {
630 class2 = ARG_CLASS_INTEGER;
634 case MONO_TYPE_VALUETYPE: {
635 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
638 for (i = 0; i < info->num_fields; ++i) {
640 class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
645 g_assert_not_reached ();
649 if (class1 == class2)
651 else if (class1 == ARG_CLASS_NO_CLASS)
653 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
654 class1 = ARG_CLASS_MEMORY;
655 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
656 class1 = ARG_CLASS_INTEGER;
658 class1 = ARG_CLASS_SSE;
662 #ifdef __native_client_codegen__
664 /* Default alignment for Native Client is 32-byte. */
665 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
667 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
668 /* Check that alignment doesn't cross an alignment boundary. */
670 mono_arch_nacl_pad(guint8 *code, int pad)
672 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
674 if (pad == 0) return code;
675 /* assertion: alignment cannot cross a block boundary */
676 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
677 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
678 while (pad >= kMaxPadding) {
679 amd64_padding (code, kMaxPadding);
682 if (pad != 0) amd64_padding (code, pad);
688 count_fields_nested (MonoClass *klass)
690 MonoMarshalType *info;
693 info = mono_marshal_load_type_info (klass);
696 for (i = 0; i < info->num_fields; ++i) {
697 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
698 count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
706 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
708 MonoMarshalType *info;
711 info = mono_marshal_load_type_info (klass);
713 for (i = 0; i < info->num_fields; ++i) {
714 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
715 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
717 memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
718 fields [index].offset += offset;
726 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
728 guint32 *gr, guint32 *fr, guint32 *stack_size)
730 guint32 size, quad, nquads, i, nfields;
731 /* Keep track of the size used in each quad so we can */
732 /* use the right size when copying args/return vars. */
733 guint32 quadsize [2] = {8, 8};
734 ArgumentClass args [2];
735 MonoMarshalType *info = NULL;
736 MonoMarshalField *fields = NULL;
738 MonoGenericSharingContext tmp_gsctx;
739 gboolean pass_on_stack = FALSE;
742 * The gsctx currently contains no data, it is only used for checking whenever
743 * open types are allowed, some callers like mono_arch_get_argument_info ()
744 * don't pass it to us, so work around that.
749 klass = mono_class_from_mono_type (type);
750 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
752 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
753 /* We pass and return vtypes of size 8 in a register */
754 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
755 pass_on_stack = TRUE;
759 pass_on_stack = TRUE;
763 /* If this struct can't be split up naturally into 8-byte */
764 /* chunks (registers), pass it on the stack. */
765 if (sig->pinvoke && !pass_on_stack) {
769 info = mono_marshal_load_type_info (klass);
773 * Collect field information recursively to be able to
774 * handle nested structures.
776 nfields = count_fields_nested (klass);
777 fields = g_new0 (MonoMarshalField, nfields);
778 collect_field_info_nested (klass, fields, 0, 0);
780 for (i = 0; i < nfields; ++i) {
781 field_size = mono_marshal_type_size (fields [i].field->type,
783 &align, TRUE, klass->unicode);
784 if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
785 pass_on_stack = TRUE;
792 /* Allways pass in memory */
793 ainfo->offset = *stack_size;
794 *stack_size += ALIGN_TO (size, 8);
795 ainfo->storage = ArgOnStack;
801 /* FIXME: Handle structs smaller than 8 bytes */
802 //if ((size % 8) != 0)
811 int n = mono_class_value_size (klass, NULL);
813 quadsize [0] = n >= 8 ? 8 : n;
814 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
816 /* Always pass in 1 or 2 integer registers */
817 args [0] = ARG_CLASS_INTEGER;
818 args [1] = ARG_CLASS_INTEGER;
819 /* Only the simplest cases are supported */
820 if (is_return && nquads != 1) {
821 args [0] = ARG_CLASS_MEMORY;
822 args [1] = ARG_CLASS_MEMORY;
826 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
827 * The X87 and SSEUP stuff is left out since there are no such types in
834 if (info->native_size > 16) {
835 ainfo->offset = *stack_size;
836 *stack_size += ALIGN_TO (info->native_size, 8);
837 ainfo->storage = ArgOnStack;
843 switch (info->native_size) {
844 case 1: case 2: case 4: case 8:
848 ainfo->storage = ArgOnStack;
849 ainfo->offset = *stack_size;
850 *stack_size += ALIGN_TO (info->native_size, 8);
853 ainfo->storage = ArgValuetypeAddrInIReg;
855 if (*gr < PARAM_REGS) {
856 ainfo->pair_storage [0] = ArgInIReg;
857 ainfo->pair_regs [0] = param_regs [*gr];
861 ainfo->pair_storage [0] = ArgOnStack;
862 ainfo->offset = *stack_size;
872 args [0] = ARG_CLASS_NO_CLASS;
873 args [1] = ARG_CLASS_NO_CLASS;
874 for (quad = 0; quad < nquads; ++quad) {
877 ArgumentClass class1;
880 class1 = ARG_CLASS_MEMORY;
882 class1 = ARG_CLASS_NO_CLASS;
883 for (i = 0; i < nfields; ++i) {
884 size = mono_marshal_type_size (fields [i].field->type,
886 &align, TRUE, klass->unicode);
887 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
888 /* Unaligned field */
892 /* Skip fields in other quad */
893 if ((quad == 0) && (fields [i].offset >= 8))
895 if ((quad == 1) && (fields [i].offset < 8))
898 /* How far into this quad this data extends.*/
899 /* (8 is size of quad) */
900 quadsize [quad] = fields [i].offset + size - (quad * 8);
902 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
904 g_assert (class1 != ARG_CLASS_NO_CLASS);
905 args [quad] = class1;
911 /* Post merger cleanup */
912 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
913 args [0] = args [1] = ARG_CLASS_MEMORY;
915 /* Allocate registers */
920 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
922 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
925 ainfo->storage = ArgValuetypeInReg;
926 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
927 g_assert (quadsize [0] <= 8);
928 g_assert (quadsize [1] <= 8);
929 ainfo->pair_size [0] = quadsize [0];
930 ainfo->pair_size [1] = quadsize [1];
931 ainfo->nregs = nquads;
932 for (quad = 0; quad < nquads; ++quad) {
933 switch (args [quad]) {
934 case ARG_CLASS_INTEGER:
935 if (*gr >= PARAM_REGS)
936 args [quad] = ARG_CLASS_MEMORY;
938 ainfo->pair_storage [quad] = ArgInIReg;
940 ainfo->pair_regs [quad] = return_regs [*gr];
942 ainfo->pair_regs [quad] = param_regs [*gr];
947 if (*fr >= FLOAT_PARAM_REGS)
948 args [quad] = ARG_CLASS_MEMORY;
950 if (quadsize[quad] <= 4)
951 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
952 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
953 ainfo->pair_regs [quad] = *fr;
957 case ARG_CLASS_MEMORY:
960 g_assert_not_reached ();
964 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
965 /* Revert possible register assignments */
969 ainfo->offset = *stack_size;
971 *stack_size += ALIGN_TO (info->native_size, 8);
973 *stack_size += nquads * sizeof(mgreg_t);
974 ainfo->storage = ArgOnStack;
982 * Obtain information about a call according to the calling convention.
983 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
984 * Draft Version 0.23" document for more information.
987 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
989 guint32 i, gr, fr, pstart;
991 int n = sig->hasthis + sig->param_count;
992 guint32 stack_size = 0;
994 gboolean is_pinvoke = sig->pinvoke;
997 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
999 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1007 /* Reserve space where the callee can save the argument registers */
1008 stack_size = 4 * sizeof (mgreg_t);
1012 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1013 switch (ret_type->type) {
1023 case MONO_TYPE_FNPTR:
1024 case MONO_TYPE_CLASS:
1025 case MONO_TYPE_OBJECT:
1026 case MONO_TYPE_SZARRAY:
1027 case MONO_TYPE_ARRAY:
1028 case MONO_TYPE_STRING:
1029 cinfo->ret.storage = ArgInIReg;
1030 cinfo->ret.reg = AMD64_RAX;
1034 cinfo->ret.storage = ArgInIReg;
1035 cinfo->ret.reg = AMD64_RAX;
1038 cinfo->ret.storage = ArgInFloatSSEReg;
1039 cinfo->ret.reg = AMD64_XMM0;
1042 cinfo->ret.storage = ArgInDoubleSSEReg;
1043 cinfo->ret.reg = AMD64_XMM0;
1045 case MONO_TYPE_GENERICINST:
1046 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1047 cinfo->ret.storage = ArgInIReg;
1048 cinfo->ret.reg = AMD64_RAX;
1052 #if defined( __native_client_codegen__ )
1053 case MONO_TYPE_TYPEDBYREF:
1055 case MONO_TYPE_VALUETYPE: {
1056 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1058 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1059 if (cinfo->ret.storage == ArgOnStack) {
1060 cinfo->vtype_retaddr = TRUE;
1061 /* The caller passes the address where the value is stored */
1065 #if !defined( __native_client_codegen__ )
1066 case MONO_TYPE_TYPEDBYREF:
1067 /* Same as a valuetype with size 24 */
1068 cinfo->vtype_retaddr = TRUE;
1071 case MONO_TYPE_VOID:
1074 g_error ("Can't handle as return value 0x%x", ret_type->type);
1079 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1080 * the first argument, allowing 'this' to be always passed in the first arg reg.
1081 * Also do this if the first argument is a reference type, since virtual calls
1082 * are sometimes made using calli without sig->hasthis set, like in the delegate
1085 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1087 add_general (&gr, &stack_size, cinfo->args + 0);
1089 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1092 add_general (&gr, &stack_size, &cinfo->ret);
1093 cinfo->vret_arg_index = 1;
1097 add_general (&gr, &stack_size, cinfo->args + 0);
1099 if (cinfo->vtype_retaddr)
1100 add_general (&gr, &stack_size, &cinfo->ret);
1103 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1105 fr = FLOAT_PARAM_REGS;
1107 /* Emit the signature cookie just before the implicit arguments */
1108 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1111 for (i = pstart; i < sig->param_count; ++i) {
1112 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1116 /* The float param registers and other param registers must be the same index on Windows x64.*/
1123 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1124 /* We allways pass the sig cookie on the stack for simplicity */
1126 * Prevent implicit arguments + the sig cookie from being passed
1130 fr = FLOAT_PARAM_REGS;
1132 /* Emit the signature cookie just before the implicit arguments */
1133 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1136 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1137 switch (ptype->type) {
1140 add_general (&gr, &stack_size, ainfo);
1144 add_general (&gr, &stack_size, ainfo);
1148 add_general (&gr, &stack_size, ainfo);
1153 case MONO_TYPE_FNPTR:
1154 case MONO_TYPE_CLASS:
1155 case MONO_TYPE_OBJECT:
1156 case MONO_TYPE_STRING:
1157 case MONO_TYPE_SZARRAY:
1158 case MONO_TYPE_ARRAY:
1159 add_general (&gr, &stack_size, ainfo);
1161 case MONO_TYPE_GENERICINST:
1162 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1163 add_general (&gr, &stack_size, ainfo);
1167 case MONO_TYPE_VALUETYPE:
1168 case MONO_TYPE_TYPEDBYREF:
1169 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1174 add_general (&gr, &stack_size, ainfo);
1177 add_float (&fr, &stack_size, ainfo, FALSE);
1180 add_float (&fr, &stack_size, ainfo, TRUE);
1183 g_assert_not_reached ();
1187 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1189 fr = FLOAT_PARAM_REGS;
1191 /* Emit the signature cookie just before the implicit arguments */
1192 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1195 cinfo->stack_usage = stack_size;
1196 cinfo->reg_usage = gr;
1197 cinfo->freg_usage = fr;
1202 * mono_arch_get_argument_info:
1203 * @csig: a method signature
1204 * @param_count: the number of parameters to consider
1205 * @arg_info: an array to store the result infos
1207 * Gathers information on parameters such as size, alignment and
1208 * padding. arg_info should be large enought to hold param_count + 1 entries.
1210 * Returns the size of the argument area on the stack.
1213 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1216 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1217 guint32 args_size = cinfo->stack_usage;
1219 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1220 if (csig->hasthis) {
1221 arg_info [0].offset = 0;
1224 for (k = 0; k < param_count; k++) {
1225 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1227 arg_info [k + 1].size = 0;
1236 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1240 MonoType *callee_ret;
1242 c1 = get_call_info (NULL, NULL, caller_sig);
1243 c2 = get_call_info (NULL, NULL, callee_sig);
1244 res = c1->stack_usage >= c2->stack_usage;
1245 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1246 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1247 /* An address on the callee's stack is passed as the first argument */
1257 * Initialize the cpu to execute managed code.
1260 mono_arch_cpu_init (void)
1265 /* spec compliance requires running with double precision */
1266 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1267 fpcw &= ~X86_FPCW_PRECC_MASK;
1268 fpcw |= X86_FPCW_PREC_DOUBLE;
1269 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1270 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1272 /* TODO: This is crashing on Win64 right now.
1273 * _control87 (_PC_53, MCW_PC);
1279 * Initialize architecture specific code.
1282 mono_arch_init (void)
1286 mono_mutex_init_recursive (&mini_arch_mutex);
1287 #if defined(__native_client_codegen__)
1288 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1289 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1290 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1291 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1294 #ifdef MONO_ARCH_NOMAP32BIT
1295 flags = MONO_MMAP_READ;
1296 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1297 breakpoint_size = 13;
1298 breakpoint_fault_size = 3;
1300 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1301 /* amd64_mov_reg_mem () */
1302 breakpoint_size = 8;
1303 breakpoint_fault_size = 8;
1306 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1307 single_step_fault_size = 4;
1309 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1310 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1311 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1313 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1314 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1315 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1319 * Cleanup architecture specific code.
1322 mono_arch_cleanup (void)
1324 mono_mutex_destroy (&mini_arch_mutex);
1325 #if defined(__native_client_codegen__)
1326 mono_native_tls_free (nacl_instruction_depth);
1327 mono_native_tls_free (nacl_rex_tag);
1328 mono_native_tls_free (nacl_legacy_prefix_tag);
1333 * This function returns the optimizations supported on this cpu.
1336 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1342 if (mono_hwcap_x86_has_cmov) {
1343 opts |= MONO_OPT_CMOV;
1345 if (mono_hwcap_x86_has_fcmov)
1346 opts |= MONO_OPT_FCMOV;
1348 *exclude_mask |= MONO_OPT_FCMOV;
1350 *exclude_mask |= MONO_OPT_CMOV;
1357 * This function test for all SSE functions supported.
1359 * Returns a bitmask corresponding to all supported versions.
1363 mono_arch_cpu_enumerate_simd_versions (void)
1365 guint32 sse_opts = 0;
1367 if (mono_hwcap_x86_has_sse1)
1368 sse_opts |= SIMD_VERSION_SSE1;
1370 if (mono_hwcap_x86_has_sse2)
1371 sse_opts |= SIMD_VERSION_SSE2;
1373 if (mono_hwcap_x86_has_sse3)
1374 sse_opts |= SIMD_VERSION_SSE3;
1376 if (mono_hwcap_x86_has_ssse3)
1377 sse_opts |= SIMD_VERSION_SSSE3;
1379 if (mono_hwcap_x86_has_sse41)
1380 sse_opts |= SIMD_VERSION_SSE41;
1382 if (mono_hwcap_x86_has_sse42)
1383 sse_opts |= SIMD_VERSION_SSE42;
1385 if (mono_hwcap_x86_has_sse4a)
1386 sse_opts |= SIMD_VERSION_SSE4a;
1394 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1399 for (i = 0; i < cfg->num_varinfo; i++) {
1400 MonoInst *ins = cfg->varinfo [i];
1401 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1404 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1407 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1408 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1411 if (mono_is_regsize_var (ins->inst_vtype)) {
1412 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1413 g_assert (i == vmv->idx);
1414 vars = g_list_prepend (vars, vmv);
1418 vars = mono_varlist_sort (cfg, vars, 0);
1424 * mono_arch_compute_omit_fp:
1426 * Determine whenever the frame pointer can be eliminated.
1429 mono_arch_compute_omit_fp (MonoCompile *cfg)
1431 MonoMethodSignature *sig;
1432 MonoMethodHeader *header;
1436 if (cfg->arch.omit_fp_computed)
1439 header = cfg->header;
1441 sig = mono_method_signature (cfg->method);
1443 if (!cfg->arch.cinfo)
1444 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1445 cinfo = cfg->arch.cinfo;
1448 * FIXME: Remove some of the restrictions.
1450 cfg->arch.omit_fp = TRUE;
1451 cfg->arch.omit_fp_computed = TRUE;
1453 #ifdef __native_client_codegen__
1454 /* NaCl modules may not change the value of RBP, so it cannot be */
1455 /* used as a normal register, but it can be used as a frame pointer*/
1456 cfg->disable_omit_fp = TRUE;
1457 cfg->arch.omit_fp = FALSE;
1460 if (cfg->disable_omit_fp)
1461 cfg->arch.omit_fp = FALSE;
1463 if (!debug_omit_fp ())
1464 cfg->arch.omit_fp = FALSE;
1466 if (cfg->method->save_lmf)
1467 cfg->arch.omit_fp = FALSE;
1469 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1470 cfg->arch.omit_fp = FALSE;
1471 if (header->num_clauses)
1472 cfg->arch.omit_fp = FALSE;
1473 if (cfg->param_area)
1474 cfg->arch.omit_fp = FALSE;
1475 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1476 cfg->arch.omit_fp = FALSE;
1477 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1478 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1479 cfg->arch.omit_fp = FALSE;
1480 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1481 ArgInfo *ainfo = &cinfo->args [i];
1483 if (ainfo->storage == ArgOnStack) {
1485 * The stack offset can only be determined when the frame
1488 cfg->arch.omit_fp = FALSE;
1493 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1494 MonoInst *ins = cfg->varinfo [i];
1497 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1502 mono_arch_get_global_int_regs (MonoCompile *cfg)
1506 mono_arch_compute_omit_fp (cfg);
1508 if (cfg->globalra) {
1509 if (cfg->arch.omit_fp)
1510 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1512 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1513 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1514 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1515 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1516 #ifndef __native_client_codegen__
1517 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1520 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1521 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1522 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1523 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1524 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1525 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1526 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1527 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1529 if (cfg->arch.omit_fp)
1530 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1532 /* We use the callee saved registers for global allocation */
1533 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1534 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1535 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1536 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1537 #ifndef __native_client_codegen__
1538 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1541 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1542 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1550 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1555 /* All XMM registers */
1556 for (i = 0; i < 16; ++i)
1557 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1563 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1565 static GList *r = NULL;
1570 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1571 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1572 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1573 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1574 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1575 #ifndef __native_client_codegen__
1576 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1579 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1580 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1581 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1582 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1583 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1584 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1585 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1586 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1588 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1595 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1598 static GList *r = NULL;
1603 for (i = 0; i < AMD64_XMM_NREG; ++i)
1604 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1606 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1613 * mono_arch_regalloc_cost:
1615 * Return the cost, in number of memory references, of the action of
1616 * allocating the variable VMV into a register during global register
1620 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1622 MonoInst *ins = cfg->varinfo [vmv->idx];
1624 if (cfg->method->save_lmf)
1625 /* The register is already saved */
1626 /* substract 1 for the invisible store in the prolog */
1627 return (ins->opcode == OP_ARG) ? 0 : 1;
1630 return (ins->opcode == OP_ARG) ? 1 : 2;
1634 * mono_arch_fill_argument_info:
1636 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1640 mono_arch_fill_argument_info (MonoCompile *cfg)
1643 MonoMethodSignature *sig;
1648 sig = mono_method_signature (cfg->method);
1650 cinfo = cfg->arch.cinfo;
1651 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1654 * Contrary to mono_arch_allocate_vars (), the information should describe
1655 * where the arguments are at the beginning of the method, not where they can be
1656 * accessed during the execution of the method. The later makes no sense for the
1657 * global register allocator, since a variable can be in more than one location.
1659 if (sig_ret->type != MONO_TYPE_VOID) {
1660 switch (cinfo->ret.storage) {
1662 case ArgInFloatSSEReg:
1663 case ArgInDoubleSSEReg:
1664 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1665 cfg->vret_addr->opcode = OP_REGVAR;
1666 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1669 cfg->ret->opcode = OP_REGVAR;
1670 cfg->ret->inst_c0 = cinfo->ret.reg;
1673 case ArgValuetypeInReg:
1674 cfg->ret->opcode = OP_REGOFFSET;
1675 cfg->ret->inst_basereg = -1;
1676 cfg->ret->inst_offset = -1;
1679 g_assert_not_reached ();
1683 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1684 ArgInfo *ainfo = &cinfo->args [i];
1686 ins = cfg->args [i];
1688 switch (ainfo->storage) {
1690 case ArgInFloatSSEReg:
1691 case ArgInDoubleSSEReg:
1692 ins->opcode = OP_REGVAR;
1693 ins->inst_c0 = ainfo->reg;
1696 ins->opcode = OP_REGOFFSET;
1697 ins->inst_basereg = -1;
1698 ins->inst_offset = -1;
1700 case ArgValuetypeInReg:
1702 ins->opcode = OP_NOP;
1705 g_assert_not_reached ();
1711 mono_arch_allocate_vars (MonoCompile *cfg)
1714 MonoMethodSignature *sig;
1717 guint32 locals_stack_size, locals_stack_align;
1721 sig = mono_method_signature (cfg->method);
1723 cinfo = cfg->arch.cinfo;
1724 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1726 mono_arch_compute_omit_fp (cfg);
1729 * We use the ABI calling conventions for managed code as well.
1730 * Exception: valuetypes are only sometimes passed or returned in registers.
1734 * The stack looks like this:
1735 * <incoming arguments passed on the stack>
1737 * <lmf/caller saved registers>
1740 * <localloc area> -> grows dynamically
1744 if (cfg->arch.omit_fp) {
1745 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1746 cfg->frame_reg = AMD64_RSP;
1749 /* Locals are allocated backwards from %fp */
1750 cfg->frame_reg = AMD64_RBP;
1754 cfg->arch.saved_iregs = cfg->used_int_regs;
1755 if (cfg->method->save_lmf)
1756 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1757 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1759 if (cfg->arch.omit_fp)
1760 cfg->arch.reg_save_area_offset = offset;
1761 /* Reserve space for callee saved registers */
1762 for (i = 0; i < AMD64_NREG; ++i)
1763 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1764 offset += sizeof(mgreg_t);
1766 if (!cfg->arch.omit_fp)
1767 cfg->arch.reg_save_area_offset = -offset;
1769 if (sig_ret->type != MONO_TYPE_VOID) {
1770 switch (cinfo->ret.storage) {
1772 case ArgInFloatSSEReg:
1773 case ArgInDoubleSSEReg:
1774 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1775 if (cfg->globalra) {
1776 cfg->vret_addr->opcode = OP_REGVAR;
1777 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1779 /* The register is volatile */
1780 cfg->vret_addr->opcode = OP_REGOFFSET;
1781 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1782 if (cfg->arch.omit_fp) {
1783 cfg->vret_addr->inst_offset = offset;
1787 cfg->vret_addr->inst_offset = -offset;
1789 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1790 printf ("vret_addr =");
1791 mono_print_ins (cfg->vret_addr);
1796 cfg->ret->opcode = OP_REGVAR;
1797 cfg->ret->inst_c0 = cinfo->ret.reg;
1800 case ArgValuetypeInReg:
1801 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1802 cfg->ret->opcode = OP_REGOFFSET;
1803 cfg->ret->inst_basereg = cfg->frame_reg;
1804 if (cfg->arch.omit_fp) {
1805 cfg->ret->inst_offset = offset;
1806 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1808 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1809 cfg->ret->inst_offset = - offset;
1813 g_assert_not_reached ();
1816 cfg->ret->dreg = cfg->ret->inst_c0;
1819 /* Allocate locals */
1820 if (!cfg->globalra) {
1821 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1822 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1823 char *mname = mono_method_full_name (cfg->method, TRUE);
1824 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1825 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1830 if (locals_stack_align) {
1831 offset += (locals_stack_align - 1);
1832 offset &= ~(locals_stack_align - 1);
1834 if (cfg->arch.omit_fp) {
1835 cfg->locals_min_stack_offset = offset;
1836 cfg->locals_max_stack_offset = offset + locals_stack_size;
1838 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1839 cfg->locals_max_stack_offset = - offset;
1842 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1843 if (offsets [i] != -1) {
1844 MonoInst *ins = cfg->varinfo [i];
1845 ins->opcode = OP_REGOFFSET;
1846 ins->inst_basereg = cfg->frame_reg;
1847 if (cfg->arch.omit_fp)
1848 ins->inst_offset = (offset + offsets [i]);
1850 ins->inst_offset = - (offset + offsets [i]);
1851 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1854 offset += locals_stack_size;
1857 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1858 g_assert (!cfg->arch.omit_fp);
1859 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1860 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1863 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1864 ins = cfg->args [i];
1865 if (ins->opcode != OP_REGVAR) {
1866 ArgInfo *ainfo = &cinfo->args [i];
1867 gboolean inreg = TRUE;
1869 if (cfg->globalra) {
1870 /* The new allocator needs info about the original locations of the arguments */
1871 switch (ainfo->storage) {
1873 case ArgInFloatSSEReg:
1874 case ArgInDoubleSSEReg:
1875 ins->opcode = OP_REGVAR;
1876 ins->inst_c0 = ainfo->reg;
1879 g_assert (!cfg->arch.omit_fp);
1880 ins->opcode = OP_REGOFFSET;
1881 ins->inst_basereg = cfg->frame_reg;
1882 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1884 case ArgValuetypeInReg:
1885 ins->opcode = OP_REGOFFSET;
1886 ins->inst_basereg = cfg->frame_reg;
1887 /* These arguments are saved to the stack in the prolog */
1888 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1889 if (cfg->arch.omit_fp) {
1890 ins->inst_offset = offset;
1891 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1893 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1894 ins->inst_offset = - offset;
1898 g_assert_not_reached ();
1904 /* FIXME: Allocate volatile arguments to registers */
1905 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1909 * Under AMD64, all registers used to pass arguments to functions
1910 * are volatile across calls.
1911 * FIXME: Optimize this.
1913 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1916 ins->opcode = OP_REGOFFSET;
1918 switch (ainfo->storage) {
1920 case ArgInFloatSSEReg:
1921 case ArgInDoubleSSEReg:
1923 ins->opcode = OP_REGVAR;
1924 ins->dreg = ainfo->reg;
1928 g_assert (!cfg->arch.omit_fp);
1929 ins->opcode = OP_REGOFFSET;
1930 ins->inst_basereg = cfg->frame_reg;
1931 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1933 case ArgValuetypeInReg:
1935 case ArgValuetypeAddrInIReg: {
1937 g_assert (!cfg->arch.omit_fp);
1939 MONO_INST_NEW (cfg, indir, 0);
1940 indir->opcode = OP_REGOFFSET;
1941 if (ainfo->pair_storage [0] == ArgInIReg) {
1942 indir->inst_basereg = cfg->frame_reg;
1943 offset = ALIGN_TO (offset, sizeof (gpointer));
1944 offset += (sizeof (gpointer));
1945 indir->inst_offset = - offset;
1948 indir->inst_basereg = cfg->frame_reg;
1949 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1952 ins->opcode = OP_VTARG_ADDR;
1953 ins->inst_left = indir;
1961 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1962 ins->opcode = OP_REGOFFSET;
1963 ins->inst_basereg = cfg->frame_reg;
1964 /* These arguments are saved to the stack in the prolog */
1965 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1966 if (cfg->arch.omit_fp) {
1967 ins->inst_offset = offset;
1968 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1969 // Arguments are yet supported by the stack map creation code
1970 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1972 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1973 ins->inst_offset = - offset;
1974 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1980 cfg->stack_offset = offset;
1984 mono_arch_create_vars (MonoCompile *cfg)
1986 MonoMethodSignature *sig;
1990 sig = mono_method_signature (cfg->method);
1992 if (!cfg->arch.cinfo)
1993 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1994 cinfo = cfg->arch.cinfo;
1996 if (cinfo->ret.storage == ArgValuetypeInReg)
1997 cfg->ret_var_is_local = TRUE;
1999 sig_ret = mini_get_underlying_type (cfg, sig->ret);
2000 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2001 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2002 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2003 printf ("vret_addr = ");
2004 mono_print_ins (cfg->vret_addr);
2008 if (cfg->gen_seq_points_debug_data) {
2011 if (cfg->compile_aot) {
2012 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2013 ins->flags |= MONO_INST_VOLATILE;
2014 cfg->arch.seq_point_info_var = ins;
2017 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2018 ins->flags |= MONO_INST_VOLATILE;
2019 cfg->arch.ss_trigger_page_var = ins;
2022 if (cfg->method->save_lmf)
2023 cfg->create_lmf_var = TRUE;
2025 if (cfg->method->save_lmf) {
2027 #if !defined(HOST_WIN32)
2028 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2029 cfg->lmf_ir_mono_lmf = TRUE;
2035 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2041 MONO_INST_NEW (cfg, ins, OP_MOVE);
2042 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2043 ins->sreg1 = tree->dreg;
2044 MONO_ADD_INS (cfg->cbb, ins);
2045 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2047 case ArgInFloatSSEReg:
2048 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2049 ins->dreg = mono_alloc_freg (cfg);
2050 ins->sreg1 = tree->dreg;
2051 MONO_ADD_INS (cfg->cbb, ins);
2053 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2055 case ArgInDoubleSSEReg:
2056 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2057 ins->dreg = mono_alloc_freg (cfg);
2058 ins->sreg1 = tree->dreg;
2059 MONO_ADD_INS (cfg->cbb, ins);
2061 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2065 g_assert_not_reached ();
2070 arg_storage_to_load_membase (ArgStorage storage)
2074 #if defined(__mono_ilp32__)
2075 return OP_LOADI8_MEMBASE;
2077 return OP_LOAD_MEMBASE;
2079 case ArgInDoubleSSEReg:
2080 return OP_LOADR8_MEMBASE;
2081 case ArgInFloatSSEReg:
2082 return OP_LOADR4_MEMBASE;
2084 g_assert_not_reached ();
2091 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2093 MonoMethodSignature *tmp_sig;
2096 if (call->tail_call)
2099 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2102 * mono_ArgIterator_Setup assumes the signature cookie is
2103 * passed first and all the arguments which were before it are
2104 * passed on the stack after the signature. So compensate by
2105 * passing a different signature.
2107 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2108 tmp_sig->param_count -= call->signature->sentinelpos;
2109 tmp_sig->sentinelpos = 0;
2110 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2112 sig_reg = mono_alloc_ireg (cfg);
2113 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2115 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2119 static inline LLVMArgStorage
2120 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2124 return LLVMArgInIReg;
2128 g_assert_not_reached ();
2134 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2140 LLVMCallInfo *linfo;
2141 MonoType *t, *sig_ret;
2143 n = sig->param_count + sig->hasthis;
2144 sig_ret = mini_get_underlying_type (cfg, sig->ret);
2146 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2148 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2151 * LLVM always uses the native ABI while we use our own ABI, the
2152 * only difference is the handling of vtypes:
2153 * - we only pass/receive them in registers in some cases, and only
2154 * in 1 or 2 integer registers.
2156 if (cinfo->ret.storage == ArgValuetypeInReg) {
2158 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2159 cfg->disable_llvm = TRUE;
2163 linfo->ret.storage = LLVMArgVtypeInReg;
2164 for (j = 0; j < 2; ++j)
2165 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2168 if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2169 /* Vtype returned using a hidden argument */
2170 linfo->ret.storage = LLVMArgVtypeRetAddr;
2171 linfo->vret_arg_index = cinfo->vret_arg_index;
2174 for (i = 0; i < n; ++i) {
2175 ainfo = cinfo->args + i;
2177 if (i >= sig->hasthis)
2178 t = sig->params [i - sig->hasthis];
2180 t = &mono_defaults.int_class->byval_arg;
2182 linfo->args [i].storage = LLVMArgNone;
2184 switch (ainfo->storage) {
2186 linfo->args [i].storage = LLVMArgInIReg;
2188 case ArgInDoubleSSEReg:
2189 case ArgInFloatSSEReg:
2190 linfo->args [i].storage = LLVMArgInFPReg;
2193 if (MONO_TYPE_ISSTRUCT (t)) {
2194 linfo->args [i].storage = LLVMArgVtypeByVal;
2196 linfo->args [i].storage = LLVMArgInIReg;
2198 if (t->type == MONO_TYPE_R4)
2199 linfo->args [i].storage = LLVMArgInFPReg;
2200 else if (t->type == MONO_TYPE_R8)
2201 linfo->args [i].storage = LLVMArgInFPReg;
2205 case ArgValuetypeInReg:
2207 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2208 cfg->disable_llvm = TRUE;
2212 linfo->args [i].storage = LLVMArgVtypeInReg;
2213 for (j = 0; j < 2; ++j)
2214 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2217 cfg->exception_message = g_strdup ("ainfo->storage");
2218 cfg->disable_llvm = TRUE;
2228 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2231 MonoMethodSignature *sig;
2237 sig = call->signature;
2238 n = sig->param_count + sig->hasthis;
2240 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2244 if (COMPILE_LLVM (cfg)) {
2245 /* We shouldn't be called in the llvm case */
2246 cfg->disable_llvm = TRUE;
2251 * Emit all arguments which are passed on the stack to prevent register
2252 * allocation problems.
2254 for (i = 0; i < n; ++i) {
2256 ainfo = cinfo->args + i;
2258 in = call->args [i];
2260 if (sig->hasthis && i == 0)
2261 t = &mono_defaults.object_class->byval_arg;
2263 t = sig->params [i - sig->hasthis];
2265 t = mini_get_underlying_type (cfg, t);
2266 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2268 if (t->type == MONO_TYPE_R4)
2269 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2270 else if (t->type == MONO_TYPE_R8)
2271 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2273 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2275 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2277 if (cfg->compute_gc_maps) {
2280 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2286 * Emit all parameters passed in registers in non-reverse order for better readability
2287 * and to help the optimization in emit_prolog ().
2289 for (i = 0; i < n; ++i) {
2290 ainfo = cinfo->args + i;
2292 in = call->args [i];
2294 if (ainfo->storage == ArgInIReg)
2295 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2298 for (i = n - 1; i >= 0; --i) {
2299 ainfo = cinfo->args + i;
2301 in = call->args [i];
2303 switch (ainfo->storage) {
2307 case ArgInFloatSSEReg:
2308 case ArgInDoubleSSEReg:
2309 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2312 case ArgValuetypeInReg:
2313 case ArgValuetypeAddrInIReg:
2314 if (ainfo->storage == ArgOnStack && call->tail_call) {
2315 MonoInst *call_inst = (MonoInst*)call;
2316 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2317 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2318 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2322 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2323 size = sizeof (MonoTypedRef);
2324 align = sizeof (gpointer);
2328 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2331 * Other backends use mono_type_stack_size (), but that
2332 * aligns the size to 8, which is larger than the size of
2333 * the source, leading to reads of invalid memory if the
2334 * source is at the end of address space.
2336 size = mono_class_value_size (in->klass, &align);
2339 g_assert (in->klass);
2341 if (ainfo->storage == ArgOnStack && size >= 10000) {
2342 /* Avoid asserts in emit_memcpy () */
2343 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2344 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2345 /* Continue normally */
2349 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2350 arg->sreg1 = in->dreg;
2351 arg->klass = in->klass;
2352 arg->backend.size = size;
2353 arg->inst_p0 = call;
2354 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2355 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2357 MONO_ADD_INS (cfg->cbb, arg);
2362 g_assert_not_reached ();
2365 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2366 /* Emit the signature cookie just before the implicit arguments */
2367 emit_sig_cookie (cfg, call, cinfo);
2370 /* Handle the case where there are no implicit arguments */
2371 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2372 emit_sig_cookie (cfg, call, cinfo);
2374 sig_ret = mini_get_underlying_type (cfg, sig->ret);
2375 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2378 if (cinfo->ret.storage == ArgValuetypeInReg) {
2379 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2381 * Tell the JIT to use a more efficient calling convention: call using
2382 * OP_CALL, compute the result location after the call, and save the
2385 call->vret_in_reg = TRUE;
2387 * Nullify the instruction computing the vret addr to enable
2388 * future optimizations.
2391 NULLIFY_INS (call->vret_var);
2393 if (call->tail_call)
2396 * The valuetype is in RAX:RDX after the call, need to be copied to
2397 * the stack. Push the address here, so the call instruction can
2400 if (!cfg->arch.vret_addr_loc) {
2401 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2402 /* Prevent it from being register allocated or optimized away */
2403 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2406 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2410 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2411 vtarg->sreg1 = call->vret_var->dreg;
2412 vtarg->dreg = mono_alloc_preg (cfg);
2413 MONO_ADD_INS (cfg->cbb, vtarg);
2415 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2419 if (cfg->method->save_lmf) {
2420 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2421 MONO_ADD_INS (cfg->cbb, arg);
2424 call->stack_usage = cinfo->stack_usage;
2428 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2431 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2432 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2433 int size = ins->backend.size;
2435 if (ainfo->storage == ArgValuetypeInReg) {
2439 for (part = 0; part < 2; ++part) {
2440 if (ainfo->pair_storage [part] == ArgNone)
2443 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2444 load->inst_basereg = src->dreg;
2445 load->inst_offset = part * sizeof(mgreg_t);
2447 switch (ainfo->pair_storage [part]) {
2449 load->dreg = mono_alloc_ireg (cfg);
2451 case ArgInDoubleSSEReg:
2452 case ArgInFloatSSEReg:
2453 load->dreg = mono_alloc_freg (cfg);
2456 g_assert_not_reached ();
2458 MONO_ADD_INS (cfg->cbb, load);
2460 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2462 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2463 MonoInst *vtaddr, *load;
2464 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2466 MONO_INST_NEW (cfg, load, OP_LDADDR);
2467 cfg->has_indirection = TRUE;
2468 load->inst_p0 = vtaddr;
2469 vtaddr->flags |= MONO_INST_INDIRECT;
2470 load->type = STACK_MP;
2471 load->klass = vtaddr->klass;
2472 load->dreg = mono_alloc_ireg (cfg);
2473 MONO_ADD_INS (cfg->cbb, load);
2474 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2476 if (ainfo->pair_storage [0] == ArgInIReg) {
2477 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2478 arg->dreg = mono_alloc_ireg (cfg);
2479 arg->sreg1 = load->dreg;
2481 MONO_ADD_INS (cfg->cbb, arg);
2482 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2484 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2488 int dreg = mono_alloc_ireg (cfg);
2490 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2491 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2492 } else if (size <= 40) {
2493 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2495 // FIXME: Code growth
2496 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2499 if (cfg->compute_gc_maps) {
2501 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2507 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2509 MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2511 if (ret->type == MONO_TYPE_R4) {
2512 if (COMPILE_LLVM (cfg))
2513 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2515 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2517 } else if (ret->type == MONO_TYPE_R8) {
2518 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2522 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2525 #endif /* DISABLE_JIT */
2527 #define EMIT_COND_BRANCH(ins,cond,sign) \
2528 if (ins->inst_true_bb->native_offset) { \
2529 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2531 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2532 if ((cfg->opt & MONO_OPT_BRANCH) && \
2533 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2534 x86_branch8 (code, cond, 0, sign); \
2536 x86_branch32 (code, cond, 0, sign); \
2540 MonoMethodSignature *sig;
2545 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2553 switch (cinfo->ret.storage) {
2557 case ArgValuetypeInReg: {
2558 ArgInfo *ainfo = &cinfo->ret;
2560 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2562 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2570 for (i = 0; i < cinfo->nargs; ++i) {
2571 ArgInfo *ainfo = &cinfo->args [i];
2572 switch (ainfo->storage) {
2575 case ArgValuetypeInReg:
2576 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2578 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2590 * mono_arch_dyn_call_prepare:
2592 * Return a pointer to an arch-specific structure which contains information
2593 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2594 * supported for SIG.
2595 * This function is equivalent to ffi_prep_cif in libffi.
2598 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2600 ArchDynCallInfo *info;
2603 cinfo = get_call_info (NULL, NULL, sig);
2605 if (!dyn_call_supported (sig, cinfo)) {
2610 info = g_new0 (ArchDynCallInfo, 1);
2611 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2613 info->cinfo = cinfo;
2615 return (MonoDynCallInfo*)info;
2619 * mono_arch_dyn_call_free:
2621 * Free a MonoDynCallInfo structure.
2624 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2626 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2628 g_free (ainfo->cinfo);
2632 #if !defined(__native_client__)
2633 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2634 #define GREG_TO_PTR(greg) (gpointer)(greg)
2636 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2637 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2638 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2642 * mono_arch_get_start_dyn_call:
2644 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2645 * store the result into BUF.
2646 * ARGS should be an array of pointers pointing to the arguments.
2647 * RET should point to a memory buffer large enought to hold the result of the
2649 * This function should be as fast as possible, any work which does not depend
2650 * on the actual values of the arguments should be done in
2651 * mono_arch_dyn_call_prepare ().
2652 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2656 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2658 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2659 DynCallArgs *p = (DynCallArgs*)buf;
2660 int arg_index, greg, i, pindex;
2661 MonoMethodSignature *sig = dinfo->sig;
2663 g_assert (buf_len >= sizeof (DynCallArgs));
2672 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2673 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2678 if (dinfo->cinfo->vtype_retaddr)
2679 p->regs [greg ++] = PTR_TO_GREG(ret);
2681 for (i = pindex; i < sig->param_count; i++) {
2682 MonoType *t = mini_type_get_underlying_type (NULL, sig->params [i]);
2683 gpointer *arg = args [arg_index ++];
2686 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2691 case MONO_TYPE_STRING:
2692 case MONO_TYPE_CLASS:
2693 case MONO_TYPE_ARRAY:
2694 case MONO_TYPE_SZARRAY:
2695 case MONO_TYPE_OBJECT:
2699 #if !defined(__mono_ilp32__)
2703 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2704 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2706 #if defined(__mono_ilp32__)
2709 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2710 p->regs [greg ++] = *(guint64*)(arg);
2714 p->regs [greg ++] = *(guint8*)(arg);
2717 p->regs [greg ++] = *(gint8*)(arg);
2720 p->regs [greg ++] = *(gint16*)(arg);
2723 p->regs [greg ++] = *(guint16*)(arg);
2726 p->regs [greg ++] = *(gint32*)(arg);
2729 p->regs [greg ++] = *(guint32*)(arg);
2731 case MONO_TYPE_GENERICINST:
2732 if (MONO_TYPE_IS_REFERENCE (t)) {
2733 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2738 case MONO_TYPE_VALUETYPE: {
2739 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2741 g_assert (ainfo->storage == ArgValuetypeInReg);
2742 if (ainfo->pair_storage [0] != ArgNone) {
2743 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2744 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2746 if (ainfo->pair_storage [1] != ArgNone) {
2747 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2748 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2753 g_assert_not_reached ();
2757 g_assert (greg <= PARAM_REGS);
2761 * mono_arch_finish_dyn_call:
2763 * Store the result of a dyn call into the return value buffer passed to
2764 * start_dyn_call ().
2765 * This function should be as fast as possible, any work which does not depend
2766 * on the actual values of the arguments should be done in
2767 * mono_arch_dyn_call_prepare ().
2770 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2772 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2773 MonoMethodSignature *sig = dinfo->sig;
2774 guint8 *ret = ((DynCallArgs*)buf)->ret;
2775 mgreg_t res = ((DynCallArgs*)buf)->res;
2776 MonoType *sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
2778 switch (sig_ret->type) {
2779 case MONO_TYPE_VOID:
2780 *(gpointer*)ret = NULL;
2782 case MONO_TYPE_STRING:
2783 case MONO_TYPE_CLASS:
2784 case MONO_TYPE_ARRAY:
2785 case MONO_TYPE_SZARRAY:
2786 case MONO_TYPE_OBJECT:
2790 *(gpointer*)ret = GREG_TO_PTR(res);
2796 *(guint8*)ret = res;
2799 *(gint16*)ret = res;
2802 *(guint16*)ret = res;
2805 *(gint32*)ret = res;
2808 *(guint32*)ret = res;
2811 *(gint64*)ret = res;
2814 *(guint64*)ret = res;
2816 case MONO_TYPE_GENERICINST:
2817 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2818 *(gpointer*)ret = GREG_TO_PTR(res);
2823 case MONO_TYPE_VALUETYPE:
2824 if (dinfo->cinfo->vtype_retaddr) {
2827 ArgInfo *ainfo = &dinfo->cinfo->ret;
2829 g_assert (ainfo->storage == ArgValuetypeInReg);
2831 if (ainfo->pair_storage [0] != ArgNone) {
2832 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2833 ((mgreg_t*)ret)[0] = res;
2836 g_assert (ainfo->pair_storage [1] == ArgNone);
2840 g_assert_not_reached ();
2844 /* emit an exception if condition is fail */
2845 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2847 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2848 if (tins == NULL) { \
2849 mono_add_patch_info (cfg, code - cfg->native_code, \
2850 MONO_PATCH_INFO_EXC, exc_name); \
2851 x86_branch32 (code, cond, 0, signed); \
2853 EMIT_COND_BRANCH (tins, cond, signed); \
2857 #define EMIT_FPCOMPARE(code) do { \
2858 amd64_fcompp (code); \
2859 amd64_fnstsw (code); \
2862 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2863 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2864 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2865 amd64_ ##op (code); \
2866 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2867 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2871 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2873 gboolean no_patch = FALSE;
2876 * FIXME: Add support for thunks
2879 gboolean near_call = FALSE;
2882 * Indirect calls are expensive so try to make a near call if possible.
2883 * The caller memory is allocated by the code manager so it is
2884 * guaranteed to be at a 32 bit offset.
2887 if (patch_type != MONO_PATCH_INFO_ABS) {
2888 /* The target is in memory allocated using the code manager */
2891 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2892 if (((MonoMethod*)data)->klass->image->aot_module)
2893 /* The callee might be an AOT method */
2895 if (((MonoMethod*)data)->dynamic)
2896 /* The target is in malloc-ed memory */
2900 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2902 * The call might go directly to a native function without
2905 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2907 gconstpointer target = mono_icall_get_wrapper (mi);
2908 if ((((guint64)target) >> 32) != 0)
2914 MonoJumpInfo *jinfo = NULL;
2916 if (cfg->abs_patches)
2917 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2919 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2920 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2921 if (mi && (((guint64)mi->func) >> 32) == 0)
2926 * This is not really an optimization, but required because the
2927 * generic class init trampolines use R11 to pass the vtable.
2932 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2934 if (info->func == info->wrapper) {
2936 if ((((guint64)info->func) >> 32) == 0)
2940 /* See the comment in mono_codegen () */
2941 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2945 else if ((((guint64)data) >> 32) == 0) {
2952 if (cfg->method->dynamic)
2953 /* These methods are allocated using malloc */
2956 #ifdef MONO_ARCH_NOMAP32BIT
2959 #if defined(__native_client__)
2960 /* Always use near_call == TRUE for Native Client */
2963 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2964 if (optimize_for_xen)
2967 if (cfg->compile_aot) {
2974 * Align the call displacement to an address divisible by 4 so it does
2975 * not span cache lines. This is required for code patching to work on SMP
2978 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2979 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2980 amd64_padding (code, pad_size);
2982 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2983 amd64_call_code (code, 0);
2986 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2987 amd64_set_reg_template (code, GP_SCRATCH_REG);
2988 amd64_call_reg (code, GP_SCRATCH_REG);
2995 static inline guint8*
2996 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2999 if (win64_adjust_stack)
3000 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3002 code = emit_call_body (cfg, code, patch_type, data);
3004 if (win64_adjust_stack)
3005 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3012 store_membase_imm_to_store_membase_reg (int opcode)
3015 case OP_STORE_MEMBASE_IMM:
3016 return OP_STORE_MEMBASE_REG;
3017 case OP_STOREI4_MEMBASE_IMM:
3018 return OP_STOREI4_MEMBASE_REG;
3019 case OP_STOREI8_MEMBASE_IMM:
3020 return OP_STOREI8_MEMBASE_REG;
3028 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3031 * mono_arch_peephole_pass_1:
3033 * Perform peephole opts which should/can be performed before local regalloc
3036 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3040 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3041 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3043 switch (ins->opcode) {
3047 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3049 * X86_LEA is like ADD, but doesn't have the
3050 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3051 * its operand to 64 bit.
3053 ins->opcode = OP_X86_LEA_MEMBASE;
3054 ins->inst_basereg = ins->sreg1;
3059 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3063 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3064 * the latter has length 2-3 instead of 6 (reverse constant
3065 * propagation). These instruction sequences are very common
3066 * in the initlocals bblock.
3068 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3069 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3070 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3071 ins2->sreg1 = ins->dreg;
3072 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3074 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3077 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3085 case OP_COMPARE_IMM:
3086 case OP_LCOMPARE_IMM:
3087 /* OP_COMPARE_IMM (reg, 0)
3089 * OP_AMD64_TEST_NULL (reg)
3092 ins->opcode = OP_AMD64_TEST_NULL;
3094 case OP_ICOMPARE_IMM:
3096 ins->opcode = OP_X86_TEST_NULL;
3098 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3100 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3101 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3103 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3104 * OP_COMPARE_IMM reg, imm
3106 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3108 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3109 ins->inst_basereg == last_ins->inst_destbasereg &&
3110 ins->inst_offset == last_ins->inst_offset) {
3111 ins->opcode = OP_ICOMPARE_IMM;
3112 ins->sreg1 = last_ins->sreg1;
3114 /* check if we can remove cmp reg,0 with test null */
3116 ins->opcode = OP_X86_TEST_NULL;
3122 mono_peephole_ins (bb, ins);
3127 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3131 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3132 switch (ins->opcode) {
3135 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3136 /* reg = 0 -> XOR (reg, reg) */
3137 /* XOR sets cflags on x86, so we cant do it always */
3138 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3139 ins->opcode = OP_LXOR;
3140 ins->sreg1 = ins->dreg;
3141 ins->sreg2 = ins->dreg;
3149 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3150 * 0 result into 64 bits.
3152 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3153 ins->opcode = OP_IXOR;
3157 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3161 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3162 * the latter has length 2-3 instead of 6 (reverse constant
3163 * propagation). These instruction sequences are very common
3164 * in the initlocals bblock.
3166 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3167 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3168 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3169 ins2->sreg1 = ins->dreg;
3170 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3172 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3175 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3184 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3185 ins->opcode = OP_X86_INC_REG;
3188 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3189 ins->opcode = OP_X86_DEC_REG;
3193 mono_peephole_ins (bb, ins);
3197 #define NEW_INS(cfg,ins,dest,op) do { \
3198 MONO_INST_NEW ((cfg), (dest), (op)); \
3199 (dest)->cil_code = (ins)->cil_code; \
3200 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3204 * mono_arch_lowering_pass:
3206 * Converts complex opcodes into simpler ones so that each IR instruction
3207 * corresponds to one machine instruction.
3210 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3212 MonoInst *ins, *n, *temp;
3215 * FIXME: Need to add more instructions, but the current machine
3216 * description can't model some parts of the composite instructions like
3219 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3220 switch (ins->opcode) {
3224 case OP_IDIV_UN_IMM:
3225 case OP_IREM_UN_IMM:
3228 mono_decompose_op_imm (cfg, bb, ins);
3230 case OP_COMPARE_IMM:
3231 case OP_LCOMPARE_IMM:
3232 if (!amd64_is_imm32 (ins->inst_imm)) {
3233 NEW_INS (cfg, ins, temp, OP_I8CONST);
3234 temp->inst_c0 = ins->inst_imm;
3235 temp->dreg = mono_alloc_ireg (cfg);
3236 ins->opcode = OP_COMPARE;
3237 ins->sreg2 = temp->dreg;
3240 #ifndef __mono_ilp32__
3241 case OP_LOAD_MEMBASE:
3243 case OP_LOADI8_MEMBASE:
3244 #ifndef __native_client_codegen__
3245 /* Don't generate memindex opcodes (to simplify */
3246 /* read sandboxing) */
3247 if (!amd64_is_imm32 (ins->inst_offset)) {
3248 NEW_INS (cfg, ins, temp, OP_I8CONST);
3249 temp->inst_c0 = ins->inst_offset;
3250 temp->dreg = mono_alloc_ireg (cfg);
3251 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3252 ins->inst_indexreg = temp->dreg;
3256 #ifndef __mono_ilp32__
3257 case OP_STORE_MEMBASE_IMM:
3259 case OP_STOREI8_MEMBASE_IMM:
3260 if (!amd64_is_imm32 (ins->inst_imm)) {
3261 NEW_INS (cfg, ins, temp, OP_I8CONST);
3262 temp->inst_c0 = ins->inst_imm;
3263 temp->dreg = mono_alloc_ireg (cfg);
3264 ins->opcode = OP_STOREI8_MEMBASE_REG;
3265 ins->sreg1 = temp->dreg;
3268 #ifdef MONO_ARCH_SIMD_INTRINSICS
3269 case OP_EXPAND_I1: {
3270 int temp_reg1 = mono_alloc_ireg (cfg);
3271 int temp_reg2 = mono_alloc_ireg (cfg);
3272 int original_reg = ins->sreg1;
3274 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3275 temp->sreg1 = original_reg;
3276 temp->dreg = temp_reg1;
3278 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3279 temp->sreg1 = temp_reg1;
3280 temp->dreg = temp_reg2;
3283 NEW_INS (cfg, ins, temp, OP_LOR);
3284 temp->sreg1 = temp->dreg = temp_reg2;
3285 temp->sreg2 = temp_reg1;
3287 ins->opcode = OP_EXPAND_I2;
3288 ins->sreg1 = temp_reg2;
3297 bb->max_vreg = cfg->next_vreg;
3301 branch_cc_table [] = {
3302 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3303 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3304 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3307 /* Maps CMP_... constants to X86_CC_... constants */
3310 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3311 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3315 cc_signed_table [] = {
3316 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3317 FALSE, FALSE, FALSE, FALSE
3320 /*#include "cprop.c"*/
3322 static unsigned char*
3323 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3326 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3328 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3331 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3333 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3337 static unsigned char*
3338 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3340 int sreg = tree->sreg1;
3341 int need_touch = FALSE;
3343 #if defined(HOST_WIN32)
3345 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3346 if (!tree->flags & MONO_INST_INIT)
3355 * If requested stack size is larger than one page,
3356 * perform stack-touch operation
3359 * Generate stack probe code.
3360 * Under Windows, it is necessary to allocate one page at a time,
3361 * "touching" stack after each successful sub-allocation. This is
3362 * because of the way stack growth is implemented - there is a
3363 * guard page before the lowest stack page that is currently commited.
3364 * Stack normally grows sequentially so OS traps access to the
3365 * guard page and commits more pages when needed.
3367 amd64_test_reg_imm (code, sreg, ~0xFFF);
3368 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3370 br[2] = code; /* loop */
3371 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3372 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3373 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3374 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3375 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3376 amd64_patch (br[3], br[2]);
3377 amd64_test_reg_reg (code, sreg, sreg);
3378 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3379 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3381 br[1] = code; x86_jump8 (code, 0);
3383 amd64_patch (br[0], code);
3384 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3385 amd64_patch (br[1], code);
3386 amd64_patch (br[4], code);
3389 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3391 if (tree->flags & MONO_INST_INIT) {
3393 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3394 amd64_push_reg (code, AMD64_RAX);
3397 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3398 amd64_push_reg (code, AMD64_RCX);
3401 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3402 amd64_push_reg (code, AMD64_RDI);
3406 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3407 if (sreg != AMD64_RCX)
3408 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3409 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3411 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3412 if (cfg->param_area)
3413 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3415 #if defined(__default_codegen__)
3416 amd64_prefix (code, X86_REP_PREFIX);
3418 #elif defined(__native_client_codegen__)
3419 /* NaCl stos pseudo-instruction */
3420 amd64_codegen_pre(code);
3421 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3422 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3423 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3424 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3425 amd64_prefix (code, X86_REP_PREFIX);
3427 amd64_codegen_post(code);
3428 #endif /* __native_client_codegen__ */
3430 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3431 amd64_pop_reg (code, AMD64_RDI);
3432 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3433 amd64_pop_reg (code, AMD64_RCX);
3434 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3435 amd64_pop_reg (code, AMD64_RAX);
3441 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3446 /* Move return value to the target register */
3447 /* FIXME: do this in the local reg allocator */
3448 switch (ins->opcode) {
3451 case OP_CALL_MEMBASE:
3454 case OP_LCALL_MEMBASE:
3455 g_assert (ins->dreg == AMD64_RAX);
3459 case OP_FCALL_MEMBASE: {
3460 MonoType *rtype = mini_get_underlying_type (cfg, ((MonoCallInst*)ins)->signature->ret);
3461 if (rtype->type == MONO_TYPE_R4) {
3462 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3465 if (ins->dreg != AMD64_XMM0)
3466 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3472 case OP_RCALL_MEMBASE:
3473 if (ins->dreg != AMD64_XMM0)
3474 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3478 case OP_VCALL_MEMBASE:
3481 case OP_VCALL2_MEMBASE:
3482 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3483 if (cinfo->ret.storage == ArgValuetypeInReg) {
3484 MonoInst *loc = cfg->arch.vret_addr_loc;
3486 /* Load the destination address */
3487 g_assert (loc->opcode == OP_REGOFFSET);
3488 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3490 for (quad = 0; quad < 2; quad ++) {
3491 switch (cinfo->ret.pair_storage [quad]) {
3493 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3495 case ArgInFloatSSEReg:
3496 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3498 case ArgInDoubleSSEReg:
3499 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3514 #endif /* DISABLE_JIT */
3517 static int tls_gs_offset;
3521 mono_amd64_have_tls_get (void)
3524 static gboolean have_tls_get = FALSE;
3525 static gboolean inited = FALSE;
3529 return have_tls_get;
3531 ins = (guint8*)pthread_getspecific;
3534 * We're looking for these two instructions:
3536 * mov %gs:[offset](,%rdi,8),%rax
3539 have_tls_get = ins [0] == 0x65 &&
3551 tls_gs_offset = ins[5];
3553 return have_tls_get;
3554 #elif defined(TARGET_ANDROID)
3562 mono_amd64_get_tls_gs_offset (void)
3565 return tls_gs_offset;
3567 g_assert_not_reached ();
3573 * mono_amd64_emit_tls_get:
3574 * @code: buffer to store code to
3575 * @dreg: hard register where to place the result
3576 * @tls_offset: offset info
3578 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3579 * the dreg register the item in the thread local storage identified
3582 * Returns: a pointer to the end of the stored code
3585 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3588 if (tls_offset < 64) {
3589 x86_prefix (code, X86_GS_PREFIX);
3590 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3594 g_assert (tls_offset < 0x440);
3595 /* Load TEB->TlsExpansionSlots */
3596 x86_prefix (code, X86_GS_PREFIX);
3597 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3598 amd64_test_reg_reg (code, dreg, dreg);
3600 amd64_branch (code, X86_CC_EQ, code, TRUE);
3601 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3602 amd64_patch (buf [0], code);
3604 #elif defined(__APPLE__)
3605 x86_prefix (code, X86_GS_PREFIX);
3606 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3608 if (optimize_for_xen) {
3609 x86_prefix (code, X86_FS_PREFIX);
3610 amd64_mov_reg_mem (code, dreg, 0, 8);
3611 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3613 x86_prefix (code, X86_FS_PREFIX);
3614 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3621 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3623 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3625 if (dreg != offset_reg)
3626 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3627 amd64_prefix (code, X86_GS_PREFIX);
3628 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3629 #elif defined(__linux__)
3632 if (dreg == offset_reg) {
3633 /* Use a temporary reg by saving it to the redzone */
3634 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3635 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3636 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3637 offset_reg = tmpreg;
3639 x86_prefix (code, X86_FS_PREFIX);
3640 amd64_mov_reg_mem (code, dreg, 0, 8);
3641 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3643 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3645 g_assert_not_reached ();
3651 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3654 g_assert_not_reached ();
3655 #elif defined(__APPLE__)
3656 x86_prefix (code, X86_GS_PREFIX);
3657 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3659 g_assert (!optimize_for_xen);
3660 x86_prefix (code, X86_FS_PREFIX);
3661 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3667 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3669 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3671 g_assert_not_reached ();
3672 #elif defined(__APPLE__)
3673 x86_prefix (code, X86_GS_PREFIX);
3674 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3676 x86_prefix (code, X86_FS_PREFIX);
3677 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3683 * mono_arch_translate_tls_offset:
3685 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3688 mono_arch_translate_tls_offset (int offset)
3691 return tls_gs_offset + (offset * 8);
3700 * Emit code to initialize an LMF structure at LMF_OFFSET.
3703 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3706 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3709 * sp is saved right before calls but we need to save it here too so
3710 * async stack walks would work.
3712 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3714 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3715 if (cfg->arch.omit_fp && cfa_offset != -1)
3716 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3718 /* These can't contain refs */
3719 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3720 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3721 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3722 /* These are handled automatically by the stack marking code */
3723 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3728 #define REAL_PRINT_REG(text,reg) \
3729 mono_assert (reg >= 0); \
3730 amd64_push_reg (code, AMD64_RAX); \
3731 amd64_push_reg (code, AMD64_RDX); \
3732 amd64_push_reg (code, AMD64_RCX); \
3733 amd64_push_reg (code, reg); \
3734 amd64_push_imm (code, reg); \
3735 amd64_push_imm (code, text " %d %p\n"); \
3736 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3737 amd64_call_reg (code, AMD64_RAX); \
3738 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3739 amd64_pop_reg (code, AMD64_RCX); \
3740 amd64_pop_reg (code, AMD64_RDX); \
3741 amd64_pop_reg (code, AMD64_RAX);
3743 /* benchmark and set based on cpu */
3744 #define LOOP_ALIGNMENT 8
3745 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3749 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3754 guint8 *code = cfg->native_code + cfg->code_len;
3757 /* Fix max_offset estimate for each successor bb */
3758 if (cfg->opt & MONO_OPT_BRANCH) {
3759 int current_offset = cfg->code_len;
3760 MonoBasicBlock *current_bb;
3761 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3762 current_bb->max_offset = current_offset;
3763 current_offset += current_bb->max_length;
3767 if (cfg->opt & MONO_OPT_LOOP) {
3768 int pad, align = LOOP_ALIGNMENT;
3769 /* set alignment depending on cpu */
3770 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3772 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3773 amd64_padding (code, pad);
3774 cfg->code_len += pad;
3775 bb->native_offset = cfg->code_len;
3779 #if defined(__native_client_codegen__)
3780 /* For Native Client, all indirect call/jump targets must be */
3781 /* 32-byte aligned. Exception handler blocks are jumped to */
3782 /* indirectly as well. */
3783 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3784 (bb->flags & BB_EXCEPTION_HANDLER);
3786 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3787 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3788 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3789 cfg->code_len += pad;
3790 bb->native_offset = cfg->code_len;
3792 #endif /*__native_client_codegen__*/
3794 if (cfg->verbose_level > 2)
3795 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3797 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3798 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3799 g_assert (!cfg->compile_aot);
3801 cov->data [bb->dfn].cil_code = bb->cil_code;
3802 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3803 /* this is not thread save, but good enough */
3804 amd64_inc_membase (code, AMD64_R11, 0);
3807 offset = code - cfg->native_code;
3809 mono_debug_open_block (cfg, bb, offset);
3811 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3812 x86_breakpoint (code);
3814 MONO_BB_FOR_EACH_INS (bb, ins) {
3815 offset = code - cfg->native_code;
3817 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3819 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3821 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3822 cfg->code_size *= 2;
3823 cfg->native_code = mono_realloc_native_code(cfg);
3824 code = cfg->native_code + offset;
3825 cfg->stat_code_reallocs++;
3828 if (cfg->debug_info)
3829 mono_debug_record_line_number (cfg, ins, offset);
3831 switch (ins->opcode) {
3833 amd64_mul_reg (code, ins->sreg2, TRUE);
3836 amd64_mul_reg (code, ins->sreg2, FALSE);
3838 case OP_X86_SETEQ_MEMBASE:
3839 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3841 case OP_STOREI1_MEMBASE_IMM:
3842 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3844 case OP_STOREI2_MEMBASE_IMM:
3845 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3847 case OP_STOREI4_MEMBASE_IMM:
3848 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3850 case OP_STOREI1_MEMBASE_REG:
3851 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3853 case OP_STOREI2_MEMBASE_REG:
3854 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3856 /* In AMD64 NaCl, pointers are 4 bytes, */
3857 /* so STORE_* != STOREI8_*. Likewise below. */
3858 case OP_STORE_MEMBASE_REG:
3859 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3861 case OP_STOREI8_MEMBASE_REG:
3862 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3864 case OP_STOREI4_MEMBASE_REG:
3865 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3867 case OP_STORE_MEMBASE_IMM:
3868 #ifndef __native_client_codegen__
3869 /* In NaCl, this could be a PCONST type, which could */
3870 /* mean a pointer type was copied directly into the */
3871 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3872 /* the value would be 0x00000000FFFFFFFF which is */
3873 /* not proper for an imm32 unless you cast it. */
3874 g_assert (amd64_is_imm32 (ins->inst_imm));
3876 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3878 case OP_STOREI8_MEMBASE_IMM:
3879 g_assert (amd64_is_imm32 (ins->inst_imm));
3880 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3883 #ifdef __mono_ilp32__
3884 /* In ILP32, pointers are 4 bytes, so separate these */
3885 /* cases, use literal 8 below where we really want 8 */
3886 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3887 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3891 // FIXME: Decompose this earlier
3892 if (amd64_is_imm32 (ins->inst_imm))
3893 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3895 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3896 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3900 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3901 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3904 // FIXME: Decompose this earlier
3905 if (amd64_is_imm32 (ins->inst_imm))
3906 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3908 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3909 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3913 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3914 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3917 /* For NaCl, pointers are 4 bytes, so separate these */
3918 /* cases, use literal 8 below where we really want 8 */
3919 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3920 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3922 case OP_LOAD_MEMBASE:
3923 g_assert (amd64_is_imm32 (ins->inst_offset));
3924 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3926 case OP_LOADI8_MEMBASE:
3927 /* Use literal 8 instead of sizeof pointer or */
3928 /* register, we really want 8 for this opcode */
3929 g_assert (amd64_is_imm32 (ins->inst_offset));
3930 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3932 case OP_LOADI4_MEMBASE:
3933 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3935 case OP_LOADU4_MEMBASE:
3936 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3938 case OP_LOADU1_MEMBASE:
3939 /* The cpu zero extends the result into 64 bits */
3940 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3942 case OP_LOADI1_MEMBASE:
3943 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3945 case OP_LOADU2_MEMBASE:
3946 /* The cpu zero extends the result into 64 bits */
3947 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3949 case OP_LOADI2_MEMBASE:
3950 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3952 case OP_AMD64_LOADI8_MEMINDEX:
3953 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3955 case OP_LCONV_TO_I1:
3956 case OP_ICONV_TO_I1:
3958 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3960 case OP_LCONV_TO_I2:
3961 case OP_ICONV_TO_I2:
3963 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3965 case OP_LCONV_TO_U1:
3966 case OP_ICONV_TO_U1:
3967 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3969 case OP_LCONV_TO_U2:
3970 case OP_ICONV_TO_U2:
3971 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3974 /* Clean out the upper word */
3975 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3978 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3982 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3984 case OP_COMPARE_IMM:
3985 #if defined(__mono_ilp32__)
3986 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3987 g_assert (amd64_is_imm32 (ins->inst_imm));
3988 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3991 case OP_LCOMPARE_IMM:
3992 g_assert (amd64_is_imm32 (ins->inst_imm));
3993 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3995 case OP_X86_COMPARE_REG_MEMBASE:
3996 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3998 case OP_X86_TEST_NULL:
3999 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4001 case OP_AMD64_TEST_NULL:
4002 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4005 case OP_X86_ADD_REG_MEMBASE:
4006 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4008 case OP_X86_SUB_REG_MEMBASE:
4009 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4011 case OP_X86_AND_REG_MEMBASE:
4012 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4014 case OP_X86_OR_REG_MEMBASE:
4015 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4017 case OP_X86_XOR_REG_MEMBASE:
4018 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4021 case OP_X86_ADD_MEMBASE_IMM:
4022 /* FIXME: Make a 64 version too */
4023 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4025 case OP_X86_SUB_MEMBASE_IMM:
4026 g_assert (amd64_is_imm32 (ins->inst_imm));
4027 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4029 case OP_X86_AND_MEMBASE_IMM:
4030 g_assert (amd64_is_imm32 (ins->inst_imm));
4031 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4033 case OP_X86_OR_MEMBASE_IMM:
4034 g_assert (amd64_is_imm32 (ins->inst_imm));
4035 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4037 case OP_X86_XOR_MEMBASE_IMM:
4038 g_assert (amd64_is_imm32 (ins->inst_imm));
4039 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4041 case OP_X86_ADD_MEMBASE_REG:
4042 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4044 case OP_X86_SUB_MEMBASE_REG:
4045 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4047 case OP_X86_AND_MEMBASE_REG:
4048 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4050 case OP_X86_OR_MEMBASE_REG:
4051 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4053 case OP_X86_XOR_MEMBASE_REG:
4054 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4056 case OP_X86_INC_MEMBASE:
4057 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4059 case OP_X86_INC_REG:
4060 amd64_inc_reg_size (code, ins->dreg, 4);
4062 case OP_X86_DEC_MEMBASE:
4063 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4065 case OP_X86_DEC_REG:
4066 amd64_dec_reg_size (code, ins->dreg, 4);
4068 case OP_X86_MUL_REG_MEMBASE:
4069 case OP_X86_MUL_MEMBASE_REG:
4070 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4072 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4073 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4075 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4076 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4078 case OP_AMD64_COMPARE_MEMBASE_REG:
4079 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4081 case OP_AMD64_COMPARE_MEMBASE_IMM:
4082 g_assert (amd64_is_imm32 (ins->inst_imm));
4083 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4085 case OP_X86_COMPARE_MEMBASE8_IMM:
4086 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4088 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4089 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4091 case OP_AMD64_COMPARE_REG_MEMBASE:
4092 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4095 case OP_AMD64_ADD_REG_MEMBASE:
4096 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4098 case OP_AMD64_SUB_REG_MEMBASE:
4099 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4101 case OP_AMD64_AND_REG_MEMBASE:
4102 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4104 case OP_AMD64_OR_REG_MEMBASE:
4105 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4107 case OP_AMD64_XOR_REG_MEMBASE:
4108 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4111 case OP_AMD64_ADD_MEMBASE_REG:
4112 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4114 case OP_AMD64_SUB_MEMBASE_REG:
4115 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4117 case OP_AMD64_AND_MEMBASE_REG:
4118 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4120 case OP_AMD64_OR_MEMBASE_REG:
4121 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4123 case OP_AMD64_XOR_MEMBASE_REG:
4124 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4127 case OP_AMD64_ADD_MEMBASE_IMM:
4128 g_assert (amd64_is_imm32 (ins->inst_imm));
4129 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4131 case OP_AMD64_SUB_MEMBASE_IMM:
4132 g_assert (amd64_is_imm32 (ins->inst_imm));
4133 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4135 case OP_AMD64_AND_MEMBASE_IMM:
4136 g_assert (amd64_is_imm32 (ins->inst_imm));
4137 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4139 case OP_AMD64_OR_MEMBASE_IMM:
4140 g_assert (amd64_is_imm32 (ins->inst_imm));
4141 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4143 case OP_AMD64_XOR_MEMBASE_IMM:
4144 g_assert (amd64_is_imm32 (ins->inst_imm));
4145 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4149 amd64_breakpoint (code);
4151 case OP_RELAXED_NOP:
4152 x86_prefix (code, X86_REP_PREFIX);
4160 case OP_DUMMY_STORE:
4161 case OP_DUMMY_ICONST:
4162 case OP_DUMMY_R8CONST:
4163 case OP_NOT_REACHED:
4166 case OP_IL_SEQ_POINT:
4167 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4169 case OP_SEQ_POINT: {
4173 * Read from the single stepping trigger page. This will cause a
4174 * SIGSEGV when single stepping is enabled.
4175 * We do this _before_ the breakpoint, so single stepping after
4176 * a breakpoint is hit will step to the next IL offset.
4178 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4179 MonoInst *var = cfg->arch.ss_trigger_page_var;
4181 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4182 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4186 * This is the address which is saved in seq points,
4188 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4190 if (cfg->compile_aot) {
4191 guint32 offset = code - cfg->native_code;
4193 MonoInst *info_var = cfg->arch.seq_point_info_var;
4196 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4197 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4198 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4199 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4200 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4203 * A placeholder for a possible breakpoint inserted by
4204 * mono_arch_set_breakpoint ().
4206 for (i = 0; i < breakpoint_size; ++i)
4210 * Add an additional nop so skipping the bp doesn't cause the ip to point
4211 * to another IL offset.
4219 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4222 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4226 g_assert (amd64_is_imm32 (ins->inst_imm));
4227 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4230 g_assert (amd64_is_imm32 (ins->inst_imm));
4231 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4236 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4239 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4243 g_assert (amd64_is_imm32 (ins->inst_imm));
4244 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4247 g_assert (amd64_is_imm32 (ins->inst_imm));
4248 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4251 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4255 g_assert (amd64_is_imm32 (ins->inst_imm));
4256 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4259 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4264 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4266 switch (ins->inst_imm) {
4270 if (ins->dreg != ins->sreg1)
4271 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4272 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4275 /* LEA r1, [r2 + r2*2] */
4276 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4279 /* LEA r1, [r2 + r2*4] */
4280 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4283 /* LEA r1, [r2 + r2*2] */
4285 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4286 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4289 /* LEA r1, [r2 + r2*8] */
4290 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4293 /* LEA r1, [r2 + r2*4] */
4295 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4296 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4299 /* LEA r1, [r2 + r2*2] */
4301 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4302 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4305 /* LEA r1, [r2 + r2*4] */
4306 /* LEA r1, [r1 + r1*4] */
4307 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4308 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4311 /* LEA r1, [r2 + r2*4] */
4313 /* LEA r1, [r1 + r1*4] */
4314 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4315 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4316 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4319 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4326 #if defined( __native_client_codegen__ )
4327 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4328 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4330 /* Regalloc magic makes the div/rem cases the same */
4331 if (ins->sreg2 == AMD64_RDX) {
4332 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4334 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4337 amd64_div_reg (code, ins->sreg2, TRUE);
4342 #if defined( __native_client_codegen__ )
4343 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4344 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4346 if (ins->sreg2 == AMD64_RDX) {
4347 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4348 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4349 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4351 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4352 amd64_div_reg (code, ins->sreg2, FALSE);
4357 #if defined( __native_client_codegen__ )
4358 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4359 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4361 if (ins->sreg2 == AMD64_RDX) {
4362 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4363 amd64_cdq_size (code, 4);
4364 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4366 amd64_cdq_size (code, 4);
4367 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4372 #if defined( __native_client_codegen__ )
4373 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4374 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4376 if (ins->sreg2 == AMD64_RDX) {
4377 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4378 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4379 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4381 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4382 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4386 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4387 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4390 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4394 g_assert (amd64_is_imm32 (ins->inst_imm));
4395 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4398 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4402 g_assert (amd64_is_imm32 (ins->inst_imm));
4403 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4406 g_assert (ins->sreg2 == AMD64_RCX);
4407 amd64_shift_reg (code, X86_SHL, ins->dreg);
4410 g_assert (ins->sreg2 == AMD64_RCX);
4411 amd64_shift_reg (code, X86_SAR, ins->dreg);
4415 g_assert (amd64_is_imm32 (ins->inst_imm));
4416 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4419 g_assert (amd64_is_imm32 (ins->inst_imm));
4420 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4422 case OP_LSHR_UN_IMM:
4423 g_assert (amd64_is_imm32 (ins->inst_imm));
4424 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4427 g_assert (ins->sreg2 == AMD64_RCX);
4428 amd64_shift_reg (code, X86_SHR, ins->dreg);
4432 g_assert (amd64_is_imm32 (ins->inst_imm));
4433 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4438 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4441 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4444 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4447 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4451 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4454 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4457 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4460 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4463 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4466 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4469 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4472 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4475 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4478 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4481 amd64_neg_reg_size (code, ins->sreg1, 4);
4484 amd64_not_reg_size (code, ins->sreg1, 4);
4487 g_assert (ins->sreg2 == AMD64_RCX);
4488 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4491 g_assert (ins->sreg2 == AMD64_RCX);
4492 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4495 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4497 case OP_ISHR_UN_IMM:
4498 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4501 g_assert (ins->sreg2 == AMD64_RCX);
4502 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4505 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4508 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4511 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4512 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4514 case OP_IMUL_OVF_UN:
4515 case OP_LMUL_OVF_UN: {
4516 /* the mul operation and the exception check should most likely be split */
4517 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4518 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4519 /*g_assert (ins->sreg2 == X86_EAX);
4520 g_assert (ins->dreg == X86_EAX);*/
4521 if (ins->sreg2 == X86_EAX) {
4522 non_eax_reg = ins->sreg1;
4523 } else if (ins->sreg1 == X86_EAX) {
4524 non_eax_reg = ins->sreg2;
4526 /* no need to save since we're going to store to it anyway */
4527 if (ins->dreg != X86_EAX) {
4529 amd64_push_reg (code, X86_EAX);
4531 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4532 non_eax_reg = ins->sreg2;
4534 if (ins->dreg == X86_EDX) {
4537 amd64_push_reg (code, X86_EAX);
4541 amd64_push_reg (code, X86_EDX);
4543 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4544 /* save before the check since pop and mov don't change the flags */
4545 if (ins->dreg != X86_EAX)
4546 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4548 amd64_pop_reg (code, X86_EDX);
4550 amd64_pop_reg (code, X86_EAX);
4551 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4555 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4557 case OP_ICOMPARE_IMM:
4558 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4580 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4588 case OP_CMOV_INE_UN:
4589 case OP_CMOV_IGE_UN:
4590 case OP_CMOV_IGT_UN:
4591 case OP_CMOV_ILE_UN:
4592 case OP_CMOV_ILT_UN:
4598 case OP_CMOV_LNE_UN:
4599 case OP_CMOV_LGE_UN:
4600 case OP_CMOV_LGT_UN:
4601 case OP_CMOV_LLE_UN:
4602 case OP_CMOV_LLT_UN:
4603 g_assert (ins->dreg == ins->sreg1);
4604 /* This needs to operate on 64 bit values */
4605 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4609 amd64_not_reg (code, ins->sreg1);
4612 amd64_neg_reg (code, ins->sreg1);
4617 if ((((guint64)ins->inst_c0) >> 32) == 0)
4618 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4620 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4623 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4624 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4627 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4628 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4631 if (ins->dreg != ins->sreg1)
4632 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4634 case OP_AMD64_SET_XMMREG_R4: {
4636 if (ins->dreg != ins->sreg1)
4637 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4639 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4643 case OP_AMD64_SET_XMMREG_R8: {
4644 if (ins->dreg != ins->sreg1)
4645 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4649 MonoCallInst *call = (MonoCallInst*)ins;
4650 int i, save_area_offset;
4652 g_assert (!cfg->method->save_lmf);
4654 /* Restore callee saved registers */
4655 save_area_offset = cfg->arch.reg_save_area_offset;
4656 for (i = 0; i < AMD64_NREG; ++i)
4657 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4658 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4659 save_area_offset += 8;
4662 if (cfg->arch.omit_fp) {
4663 if (cfg->arch.stack_alloc_size)
4664 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4666 if (call->stack_usage)
4669 /* Copy arguments on the stack to our argument area */
4670 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4671 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4672 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4678 offset = code - cfg->native_code;
4679 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4680 if (cfg->compile_aot)
4681 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4683 amd64_set_reg_template (code, AMD64_R11);
4684 amd64_jump_reg (code, AMD64_R11);
4685 ins->flags |= MONO_INST_GC_CALLSITE;
4686 ins->backend.pc_offset = code - cfg->native_code;
4690 /* ensure ins->sreg1 is not NULL */
4691 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4694 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4695 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4705 call = (MonoCallInst*)ins;
4707 * The AMD64 ABI forces callers to know about varargs.
4709 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4710 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4711 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4713 * Since the unmanaged calling convention doesn't contain a
4714 * 'vararg' entry, we have to treat every pinvoke call as a
4715 * potential vararg call.
4719 for (i = 0; i < AMD64_XMM_NREG; ++i)
4720 if (call->used_fregs & (1 << i))
4723 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4725 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4728 if (ins->flags & MONO_INST_HAS_METHOD)
4729 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4731 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4732 ins->flags |= MONO_INST_GC_CALLSITE;
4733 ins->backend.pc_offset = code - cfg->native_code;
4734 code = emit_move_return_value (cfg, ins, code);
4741 case OP_VOIDCALL_REG:
4743 call = (MonoCallInst*)ins;
4745 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4746 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4747 ins->sreg1 = AMD64_R11;
4751 * The AMD64 ABI forces callers to know about varargs.
4753 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4754 if (ins->sreg1 == AMD64_RAX) {
4755 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4756 ins->sreg1 = AMD64_R11;
4758 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4759 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4761 * Since the unmanaged calling convention doesn't contain a
4762 * 'vararg' entry, we have to treat every pinvoke call as a
4763 * potential vararg call.
4767 for (i = 0; i < AMD64_XMM_NREG; ++i)
4768 if (call->used_fregs & (1 << i))
4770 if (ins->sreg1 == AMD64_RAX) {
4771 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4772 ins->sreg1 = AMD64_R11;
4775 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4777 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4780 amd64_call_reg (code, ins->sreg1);
4781 ins->flags |= MONO_INST_GC_CALLSITE;
4782 ins->backend.pc_offset = code - cfg->native_code;
4783 code = emit_move_return_value (cfg, ins, code);
4785 case OP_FCALL_MEMBASE:
4786 case OP_RCALL_MEMBASE:
4787 case OP_LCALL_MEMBASE:
4788 case OP_VCALL_MEMBASE:
4789 case OP_VCALL2_MEMBASE:
4790 case OP_VOIDCALL_MEMBASE:
4791 case OP_CALL_MEMBASE:
4792 call = (MonoCallInst*)ins;
4794 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4795 ins->flags |= MONO_INST_GC_CALLSITE;
4796 ins->backend.pc_offset = code - cfg->native_code;
4797 code = emit_move_return_value (cfg, ins, code);
4801 MonoInst *var = cfg->dyn_call_var;
4803 g_assert (var->opcode == OP_REGOFFSET);
4805 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4806 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4808 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4810 /* Save args buffer */
4811 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4813 /* Set argument registers */
4814 for (i = 0; i < PARAM_REGS; ++i)
4815 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4818 amd64_call_reg (code, AMD64_R10);
4820 ins->flags |= MONO_INST_GC_CALLSITE;
4821 ins->backend.pc_offset = code - cfg->native_code;
4824 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4825 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4828 case OP_AMD64_SAVE_SP_TO_LMF: {
4829 MonoInst *lmf_var = cfg->lmf_var;
4830 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4834 g_assert_not_reached ();
4835 amd64_push_reg (code, ins->sreg1);
4837 case OP_X86_PUSH_IMM:
4838 g_assert_not_reached ();
4839 g_assert (amd64_is_imm32 (ins->inst_imm));
4840 amd64_push_imm (code, ins->inst_imm);
4842 case OP_X86_PUSH_MEMBASE:
4843 g_assert_not_reached ();
4844 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4846 case OP_X86_PUSH_OBJ: {
4847 int size = ALIGN_TO (ins->inst_imm, 8);
4849 g_assert_not_reached ();
4851 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4852 amd64_push_reg (code, AMD64_RDI);
4853 amd64_push_reg (code, AMD64_RSI);
4854 amd64_push_reg (code, AMD64_RCX);
4855 if (ins->inst_offset)
4856 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4858 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4859 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4860 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4862 amd64_prefix (code, X86_REP_PREFIX);
4864 amd64_pop_reg (code, AMD64_RCX);
4865 amd64_pop_reg (code, AMD64_RSI);
4866 amd64_pop_reg (code, AMD64_RDI);
4870 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4872 case OP_X86_LEA_MEMBASE:
4873 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4876 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4879 /* keep alignment */
4880 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4881 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4882 code = mono_emit_stack_alloc (cfg, code, ins);
4883 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4884 if (cfg->param_area)
4885 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4887 case OP_LOCALLOC_IMM: {
4888 guint32 size = ins->inst_imm;
4889 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4891 if (ins->flags & MONO_INST_INIT) {
4895 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4896 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4898 for (i = 0; i < size; i += 8)
4899 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4900 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4902 amd64_mov_reg_imm (code, ins->dreg, size);
4903 ins->sreg1 = ins->dreg;
4905 code = mono_emit_stack_alloc (cfg, code, ins);
4906 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4909 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4910 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4912 if (cfg->param_area)
4913 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4917 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4918 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4919 (gpointer)"mono_arch_throw_exception", FALSE);
4920 ins->flags |= MONO_INST_GC_CALLSITE;
4921 ins->backend.pc_offset = code - cfg->native_code;
4925 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4926 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4927 (gpointer)"mono_arch_rethrow_exception", FALSE);
4928 ins->flags |= MONO_INST_GC_CALLSITE;
4929 ins->backend.pc_offset = code - cfg->native_code;
4932 case OP_CALL_HANDLER:
4934 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4935 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4936 amd64_call_imm (code, 0);
4937 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4938 /* Restore stack alignment */
4939 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4941 case OP_START_HANDLER: {
4942 /* Even though we're saving RSP, use sizeof */
4943 /* gpointer because spvar is of type IntPtr */
4944 /* see: mono_create_spvar_for_region */
4945 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4946 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4948 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4949 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4951 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4955 case OP_ENDFINALLY: {
4956 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4957 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4961 case OP_ENDFILTER: {
4962 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4963 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4964 /* The local allocator will put the result into RAX */
4970 ins->inst_c0 = code - cfg->native_code;
4973 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4974 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4976 if (ins->inst_target_bb->native_offset) {
4977 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4979 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4980 if ((cfg->opt & MONO_OPT_BRANCH) &&
4981 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4982 x86_jump8 (code, 0);
4984 x86_jump32 (code, 0);
4988 amd64_jump_reg (code, ins->sreg1);
5011 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5012 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5014 case OP_COND_EXC_EQ:
5015 case OP_COND_EXC_NE_UN:
5016 case OP_COND_EXC_LT:
5017 case OP_COND_EXC_LT_UN:
5018 case OP_COND_EXC_GT:
5019 case OP_COND_EXC_GT_UN:
5020 case OP_COND_EXC_GE:
5021 case OP_COND_EXC_GE_UN:
5022 case OP_COND_EXC_LE:
5023 case OP_COND_EXC_LE_UN:
5024 case OP_COND_EXC_IEQ:
5025 case OP_COND_EXC_INE_UN:
5026 case OP_COND_EXC_ILT:
5027 case OP_COND_EXC_ILT_UN:
5028 case OP_COND_EXC_IGT:
5029 case OP_COND_EXC_IGT_UN:
5030 case OP_COND_EXC_IGE:
5031 case OP_COND_EXC_IGE_UN:
5032 case OP_COND_EXC_ILE:
5033 case OP_COND_EXC_ILE_UN:
5034 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5036 case OP_COND_EXC_OV:
5037 case OP_COND_EXC_NO:
5039 case OP_COND_EXC_NC:
5040 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5041 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5043 case OP_COND_EXC_IOV:
5044 case OP_COND_EXC_INO:
5045 case OP_COND_EXC_IC:
5046 case OP_COND_EXC_INC:
5047 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5048 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5051 /* floating point opcodes */
5053 double d = *(double *)ins->inst_p0;
5055 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5056 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5059 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5060 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5065 float f = *(float *)ins->inst_p0;
5067 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5069 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5071 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5074 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5075 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5077 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5081 case OP_STORER8_MEMBASE_REG:
5082 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5084 case OP_LOADR8_MEMBASE:
5085 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5087 case OP_STORER4_MEMBASE_REG:
5089 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5091 /* This requires a double->single conversion */
5092 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5093 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5096 case OP_LOADR4_MEMBASE:
5098 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5100 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5101 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5104 case OP_ICONV_TO_R4:
5106 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5108 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5109 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5112 case OP_ICONV_TO_R8:
5113 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5115 case OP_LCONV_TO_R4:
5117 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5119 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5120 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5123 case OP_LCONV_TO_R8:
5124 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5126 case OP_FCONV_TO_R4:
5128 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5130 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5131 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5134 case OP_FCONV_TO_I1:
5135 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5137 case OP_FCONV_TO_U1:
5138 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5140 case OP_FCONV_TO_I2:
5141 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5143 case OP_FCONV_TO_U2:
5144 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5146 case OP_FCONV_TO_U4:
5147 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5149 case OP_FCONV_TO_I4:
5151 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5153 case OP_FCONV_TO_I8:
5154 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5157 case OP_RCONV_TO_I1:
5158 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5159 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5161 case OP_RCONV_TO_U1:
5162 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5163 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5165 case OP_RCONV_TO_I2:
5166 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5167 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5169 case OP_RCONV_TO_U2:
5170 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5171 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5173 case OP_RCONV_TO_I4:
5174 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5176 case OP_RCONV_TO_U4:
5177 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5179 case OP_RCONV_TO_I8:
5180 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5182 case OP_RCONV_TO_R8:
5183 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5185 case OP_RCONV_TO_R4:
5186 if (ins->dreg != ins->sreg1)
5187 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5190 case OP_LCONV_TO_R_UN: {
5193 /* Based on gcc code */
5194 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5195 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5198 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5199 br [1] = code; x86_jump8 (code, 0);
5200 amd64_patch (br [0], code);
5203 /* Save to the red zone */
5204 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5205 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5206 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5207 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5208 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5209 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5210 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5211 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5212 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5214 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5215 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5216 amd64_patch (br [1], code);
5219 case OP_LCONV_TO_OVF_U4:
5220 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5221 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5222 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5224 case OP_LCONV_TO_OVF_I4_UN:
5225 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5226 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5227 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5230 if (ins->dreg != ins->sreg1)
5231 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5234 if (ins->dreg != ins->sreg1)
5235 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5237 case OP_MOVE_F_TO_I4:
5239 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5241 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5242 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5245 case OP_MOVE_I4_TO_F:
5246 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5248 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5250 case OP_MOVE_F_TO_I8:
5251 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5253 case OP_MOVE_I8_TO_F:
5254 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5257 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5260 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5263 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5266 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5269 static double r8_0 = -0.0;
5271 g_assert (ins->sreg1 == ins->dreg);
5273 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5274 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5278 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5281 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5284 static guint64 d = 0x7fffffffffffffffUL;
5286 g_assert (ins->sreg1 == ins->dreg);
5288 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5289 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5293 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5297 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5300 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5303 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5306 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5309 static float r4_0 = -0.0;
5311 g_assert (ins->sreg1 == ins->dreg);
5313 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5314 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5315 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5320 g_assert (cfg->opt & MONO_OPT_CMOV);
5321 g_assert (ins->dreg == ins->sreg1);
5322 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5323 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5326 g_assert (cfg->opt & MONO_OPT_CMOV);
5327 g_assert (ins->dreg == ins->sreg1);
5328 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5329 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5332 g_assert (cfg->opt & MONO_OPT_CMOV);
5333 g_assert (ins->dreg == ins->sreg1);
5334 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5335 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5338 g_assert (cfg->opt & MONO_OPT_CMOV);
5339 g_assert (ins->dreg == ins->sreg1);
5340 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5341 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5344 g_assert (cfg->opt & MONO_OPT_CMOV);
5345 g_assert (ins->dreg == ins->sreg1);
5346 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5347 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5350 g_assert (cfg->opt & MONO_OPT_CMOV);
5351 g_assert (ins->dreg == ins->sreg1);
5352 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5353 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5356 g_assert (cfg->opt & MONO_OPT_CMOV);
5357 g_assert (ins->dreg == ins->sreg1);
5358 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5359 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5362 g_assert (cfg->opt & MONO_OPT_CMOV);
5363 g_assert (ins->dreg == ins->sreg1);
5364 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5365 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5371 * The two arguments are swapped because the fbranch instructions
5372 * depend on this for the non-sse case to work.
5374 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5378 * FIXME: Get rid of this.
5379 * The two arguments are swapped because the fbranch instructions
5380 * depend on this for the non-sse case to work.
5382 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5386 /* zeroing the register at the start results in
5387 * shorter and faster code (we can also remove the widening op)
5389 guchar *unordered_check;
5391 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5392 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5393 unordered_check = code;
5394 x86_branch8 (code, X86_CC_P, 0, FALSE);
5396 if (ins->opcode == OP_FCEQ) {
5397 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5398 amd64_patch (unordered_check, code);
5400 guchar *jump_to_end;
5401 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5403 x86_jump8 (code, 0);
5404 amd64_patch (unordered_check, code);
5405 amd64_inc_reg (code, ins->dreg);
5406 amd64_patch (jump_to_end, code);
5412 /* zeroing the register at the start results in
5413 * shorter and faster code (we can also remove the widening op)
5415 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5416 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5417 if (ins->opcode == OP_FCLT_UN) {
5418 guchar *unordered_check = code;
5419 guchar *jump_to_end;
5420 x86_branch8 (code, X86_CC_P, 0, FALSE);
5421 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5423 x86_jump8 (code, 0);
5424 amd64_patch (unordered_check, code);
5425 amd64_inc_reg (code, ins->dreg);
5426 amd64_patch (jump_to_end, code);
5428 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5433 guchar *unordered_check;
5434 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5435 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5436 unordered_check = code;
5437 x86_branch8 (code, X86_CC_P, 0, FALSE);
5438 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5439 amd64_patch (unordered_check, code);
5444 /* zeroing the register at the start results in
5445 * shorter and faster code (we can also remove the widening op)
5447 guchar *unordered_check;
5449 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5450 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5451 if (ins->opcode == OP_FCGT) {
5452 unordered_check = code;
5453 x86_branch8 (code, X86_CC_P, 0, FALSE);
5454 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5455 amd64_patch (unordered_check, code);
5457 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5462 guchar *unordered_check;
5463 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5464 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5465 unordered_check = code;
5466 x86_branch8 (code, X86_CC_P, 0, FALSE);
5467 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5468 amd64_patch (unordered_check, code);
5478 gboolean unordered = FALSE;
5480 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5481 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5483 switch (ins->opcode) {
5485 x86_cond = X86_CC_EQ;
5488 x86_cond = X86_CC_LT;
5491 x86_cond = X86_CC_GT;
5494 x86_cond = X86_CC_GT;
5498 x86_cond = X86_CC_LT;
5502 g_assert_not_reached ();
5507 guchar *unordered_check;
5508 guchar *jump_to_end;
5510 unordered_check = code;
5511 x86_branch8 (code, X86_CC_P, 0, FALSE);
5512 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5514 x86_jump8 (code, 0);
5515 amd64_patch (unordered_check, code);
5516 amd64_inc_reg (code, ins->dreg);
5517 amd64_patch (jump_to_end, code);
5519 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5523 case OP_FCLT_MEMBASE:
5524 case OP_FCGT_MEMBASE:
5525 case OP_FCLT_UN_MEMBASE:
5526 case OP_FCGT_UN_MEMBASE:
5527 case OP_FCEQ_MEMBASE: {
5528 guchar *unordered_check, *jump_to_end;
5531 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5532 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5534 switch (ins->opcode) {
5535 case OP_FCEQ_MEMBASE:
5536 x86_cond = X86_CC_EQ;
5538 case OP_FCLT_MEMBASE:
5539 case OP_FCLT_UN_MEMBASE:
5540 x86_cond = X86_CC_LT;
5542 case OP_FCGT_MEMBASE:
5543 case OP_FCGT_UN_MEMBASE:
5544 x86_cond = X86_CC_GT;
5547 g_assert_not_reached ();
5550 unordered_check = code;
5551 x86_branch8 (code, X86_CC_P, 0, FALSE);
5552 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5554 switch (ins->opcode) {
5555 case OP_FCEQ_MEMBASE:
5556 case OP_FCLT_MEMBASE:
5557 case OP_FCGT_MEMBASE:
5558 amd64_patch (unordered_check, code);
5560 case OP_FCLT_UN_MEMBASE:
5561 case OP_FCGT_UN_MEMBASE:
5563 x86_jump8 (code, 0);
5564 amd64_patch (unordered_check, code);
5565 amd64_inc_reg (code, ins->dreg);
5566 amd64_patch (jump_to_end, code);
5574 guchar *jump = code;
5575 x86_branch8 (code, X86_CC_P, 0, TRUE);
5576 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5577 amd64_patch (jump, code);
5581 /* Branch if C013 != 100 */
5582 /* branch if !ZF or (PF|CF) */
5583 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5584 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5585 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5588 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5591 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5592 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5596 if (ins->opcode == OP_FBGT) {
5599 /* skip branch if C1=1 */
5601 x86_branch8 (code, X86_CC_P, 0, FALSE);
5602 /* branch if (C0 | C3) = 1 */
5603 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5604 amd64_patch (br1, code);
5607 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5611 /* Branch if C013 == 100 or 001 */
5614 /* skip branch if C1=1 */
5616 x86_branch8 (code, X86_CC_P, 0, FALSE);
5617 /* branch if (C0 | C3) = 1 */
5618 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5619 amd64_patch (br1, code);
5623 /* Branch if C013 == 000 */
5624 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5627 /* Branch if C013=000 or 100 */
5630 /* skip branch if C1=1 */
5632 x86_branch8 (code, X86_CC_P, 0, FALSE);
5633 /* branch if C0=0 */
5634 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5635 amd64_patch (br1, code);
5639 /* Branch if C013 != 001 */
5640 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5641 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5644 /* Transfer value to the fp stack */
5645 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5646 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5647 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5649 amd64_push_reg (code, AMD64_RAX);
5651 amd64_fnstsw (code);
5652 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5653 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5654 amd64_pop_reg (code, AMD64_RAX);
5655 amd64_fstp (code, 0);
5656 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5657 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5660 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5663 case OP_TLS_GET_REG:
5664 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5667 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5670 case OP_TLS_SET_REG: {
5671 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5674 case OP_MEMORY_BARRIER: {
5675 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5679 case OP_ATOMIC_ADD_I4:
5680 case OP_ATOMIC_ADD_I8: {
5681 int dreg = ins->dreg;
5682 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5684 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5687 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5688 amd64_prefix (code, X86_LOCK_PREFIX);
5689 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5690 /* dreg contains the old value, add with sreg2 value */
5691 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5693 if (ins->dreg != dreg)
5694 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5698 case OP_ATOMIC_EXCHANGE_I4:
5699 case OP_ATOMIC_EXCHANGE_I8: {
5700 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5702 /* LOCK prefix is implied. */
5703 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5704 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5705 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5708 case OP_ATOMIC_CAS_I4:
5709 case OP_ATOMIC_CAS_I8: {
5712 if (ins->opcode == OP_ATOMIC_CAS_I8)
5718 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5719 * an explanation of how this works.
5721 g_assert (ins->sreg3 == AMD64_RAX);
5722 g_assert (ins->sreg1 != AMD64_RAX);
5723 g_assert (ins->sreg1 != ins->sreg2);
5725 amd64_prefix (code, X86_LOCK_PREFIX);
5726 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5728 if (ins->dreg != AMD64_RAX)
5729 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5732 case OP_ATOMIC_LOAD_I1: {
5733 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5736 case OP_ATOMIC_LOAD_U1: {
5737 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5740 case OP_ATOMIC_LOAD_I2: {
5741 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5744 case OP_ATOMIC_LOAD_U2: {
5745 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5748 case OP_ATOMIC_LOAD_I4: {
5749 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5752 case OP_ATOMIC_LOAD_U4:
5753 case OP_ATOMIC_LOAD_I8:
5754 case OP_ATOMIC_LOAD_U8: {
5755 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5758 case OP_ATOMIC_LOAD_R4: {
5759 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5760 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5763 case OP_ATOMIC_LOAD_R8: {
5764 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5767 case OP_ATOMIC_STORE_I1:
5768 case OP_ATOMIC_STORE_U1:
5769 case OP_ATOMIC_STORE_I2:
5770 case OP_ATOMIC_STORE_U2:
5771 case OP_ATOMIC_STORE_I4:
5772 case OP_ATOMIC_STORE_U4:
5773 case OP_ATOMIC_STORE_I8:
5774 case OP_ATOMIC_STORE_U8: {
5777 switch (ins->opcode) {
5778 case OP_ATOMIC_STORE_I1:
5779 case OP_ATOMIC_STORE_U1:
5782 case OP_ATOMIC_STORE_I2:
5783 case OP_ATOMIC_STORE_U2:
5786 case OP_ATOMIC_STORE_I4:
5787 case OP_ATOMIC_STORE_U4:
5790 case OP_ATOMIC_STORE_I8:
5791 case OP_ATOMIC_STORE_U8:
5796 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5798 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5802 case OP_ATOMIC_STORE_R4: {
5803 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5804 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5806 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5810 case OP_ATOMIC_STORE_R8: {
5813 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5817 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5821 case OP_CARD_TABLE_WBARRIER: {
5822 int ptr = ins->sreg1;
5823 int value = ins->sreg2;
5825 int nursery_shift, card_table_shift;
5826 gpointer card_table_mask;
5827 size_t nursery_size;
5829 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5830 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5831 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5833 /*If either point to the stack we can simply avoid the WB. This happens due to
5834 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5836 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5840 * We need one register we can clobber, we choose EDX and make sreg1
5841 * fixed EAX to work around limitations in the local register allocator.
5842 * sreg2 might get allocated to EDX, but that is not a problem since
5843 * we use it before clobbering EDX.
5845 g_assert (ins->sreg1 == AMD64_RAX);
5848 * This is the code we produce:
5851 * edx >>= nursery_shift
5852 * cmp edx, (nursery_start >> nursery_shift)
5855 * edx >>= card_table_shift
5861 if (mono_gc_card_table_nursery_check ()) {
5862 if (value != AMD64_RDX)
5863 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5864 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5865 if (shifted_nursery_start >> 31) {
5867 * The value we need to compare against is 64 bits, so we need
5868 * another spare register. We use RBX, which we save and
5871 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5872 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5873 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5874 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5876 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5878 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5880 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5881 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5882 if (card_table_mask)
5883 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5885 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5886 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5888 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5890 if (mono_gc_card_table_nursery_check ())
5891 x86_patch (br, code);
5894 #ifdef MONO_ARCH_SIMD_INTRINSICS
5895 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5897 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5900 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5903 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5906 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5909 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5912 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5915 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5916 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5919 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5922 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5925 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5928 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5931 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5934 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5937 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5940 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5943 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5946 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5949 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5952 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5955 case OP_PSHUFLEW_HIGH:
5956 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5957 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5959 case OP_PSHUFLEW_LOW:
5960 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5961 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5964 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5965 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5968 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5969 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5972 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5973 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5977 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5980 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5983 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5986 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5989 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5992 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5995 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5996 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5999 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6002 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6005 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6008 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6011 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6014 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6017 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6020 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6023 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6026 case OP_EXTRACT_MASK:
6027 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6031 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6034 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6037 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6041 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6044 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6047 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6050 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6054 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6057 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6060 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6063 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6067 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6070 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6073 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6077 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6080 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6083 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6087 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6090 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6094 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6097 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6100 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6104 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6107 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6110 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6114 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6117 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6120 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6123 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6127 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6130 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6133 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6136 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6139 case OP_PSUM_ABS_DIFF:
6140 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6143 case OP_UNPACK_LOWB:
6144 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6146 case OP_UNPACK_LOWW:
6147 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6149 case OP_UNPACK_LOWD:
6150 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6152 case OP_UNPACK_LOWQ:
6153 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6155 case OP_UNPACK_LOWPS:
6156 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6158 case OP_UNPACK_LOWPD:
6159 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6162 case OP_UNPACK_HIGHB:
6163 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6165 case OP_UNPACK_HIGHW:
6166 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6168 case OP_UNPACK_HIGHD:
6169 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6171 case OP_UNPACK_HIGHQ:
6172 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6174 case OP_UNPACK_HIGHPS:
6175 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6177 case OP_UNPACK_HIGHPD:
6178 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6182 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6185 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6188 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6191 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6194 case OP_PADDB_SAT_UN:
6195 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6197 case OP_PSUBB_SAT_UN:
6198 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6200 case OP_PADDW_SAT_UN:
6201 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6203 case OP_PSUBW_SAT_UN:
6204 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6208 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6211 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6214 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6217 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6221 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6224 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6227 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6229 case OP_PMULW_HIGH_UN:
6230 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6233 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6237 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6240 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6244 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6247 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6251 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6254 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6258 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6261 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6265 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6268 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6272 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6275 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6279 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6282 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6285 /*TODO: This is appart of the sse spec but not added
6287 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6290 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6295 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6298 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6301 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6304 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6307 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6310 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6313 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6316 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6319 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6322 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6326 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6329 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6333 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6334 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6336 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6341 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6343 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6344 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6348 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6350 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6351 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6352 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6356 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6358 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6361 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6363 case OP_EXTRACTX_U2:
6364 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6366 case OP_INSERTX_U1_SLOW:
6367 /*sreg1 is the extracted ireg (scratch)
6368 /sreg2 is the to be inserted ireg (scratch)
6369 /dreg is the xreg to receive the value*/
6371 /*clear the bits from the extracted word*/
6372 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6373 /*shift the value to insert if needed*/
6374 if (ins->inst_c0 & 1)
6375 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6376 /*join them together*/
6377 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6378 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6380 case OP_INSERTX_I4_SLOW:
6381 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6382 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6383 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6385 case OP_INSERTX_I8_SLOW:
6386 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6388 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6390 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6393 case OP_INSERTX_R4_SLOW:
6394 switch (ins->inst_c0) {
6397 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6399 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6402 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6404 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6406 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6407 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6410 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6412 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6414 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6415 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6418 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6420 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6422 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6423 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6427 case OP_INSERTX_R8_SLOW:
6429 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6431 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6433 case OP_STOREX_MEMBASE_REG:
6434 case OP_STOREX_MEMBASE:
6435 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6437 case OP_LOADX_MEMBASE:
6438 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6440 case OP_LOADX_ALIGNED_MEMBASE:
6441 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6443 case OP_STOREX_ALIGNED_MEMBASE_REG:
6444 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6446 case OP_STOREX_NTA_MEMBASE_REG:
6447 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6449 case OP_PREFETCH_MEMBASE:
6450 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6454 /*FIXME the peephole pass should have killed this*/
6455 if (ins->dreg != ins->sreg1)
6456 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6459 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6461 case OP_ICONV_TO_R4_RAW:
6462 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6465 case OP_FCONV_TO_R8_X:
6466 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6469 case OP_XCONV_R8_TO_I4:
6470 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6471 switch (ins->backend.source_opcode) {
6472 case OP_FCONV_TO_I1:
6473 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6475 case OP_FCONV_TO_U1:
6476 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6478 case OP_FCONV_TO_I2:
6479 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6481 case OP_FCONV_TO_U2:
6482 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6488 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6489 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6490 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6493 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6494 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6497 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6498 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6502 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6504 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6505 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6507 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6510 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6511 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6514 case OP_LIVERANGE_START: {
6515 if (cfg->verbose_level > 1)
6516 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6517 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6520 case OP_LIVERANGE_END: {
6521 if (cfg->verbose_level > 1)
6522 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6523 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6526 case OP_NACL_GC_SAFE_POINT: {
6527 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6528 if (cfg->compile_aot)
6529 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6533 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6534 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6535 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6536 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6537 amd64_patch (br[0], code);
6542 case OP_GC_LIVENESS_DEF:
6543 case OP_GC_LIVENESS_USE:
6544 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6545 ins->backend.pc_offset = code - cfg->native_code;
6547 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6548 ins->backend.pc_offset = code - cfg->native_code;
6549 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6552 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6553 g_assert_not_reached ();
6556 if ((code - cfg->native_code - offset) > max_len) {
6557 #if !defined(__native_client_codegen__)
6558 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6559 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6560 g_assert_not_reached ();
6565 cfg->code_len = code - cfg->native_code;
6568 #endif /* DISABLE_JIT */
6571 mono_arch_register_lowlevel_calls (void)
6573 /* The signature doesn't matter */
6574 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6578 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6580 MonoJumpInfo *patch_info;
6581 gboolean compile_aot = !run_cctors;
6583 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6584 unsigned char *ip = patch_info->ip.i + code;
6585 unsigned char *target;
6588 switch (patch_info->type) {
6589 case MONO_PATCH_INFO_BB:
6590 case MONO_PATCH_INFO_LABEL:
6593 /* No need to patch these */
6598 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6600 switch (patch_info->type) {
6601 case MONO_PATCH_INFO_NONE:
6603 case MONO_PATCH_INFO_METHOD_REL:
6604 case MONO_PATCH_INFO_R8:
6605 case MONO_PATCH_INFO_R4:
6606 g_assert_not_reached ();
6608 case MONO_PATCH_INFO_BB:
6615 * Debug code to help track down problems where the target of a near call is
6618 if (amd64_is_near_call (ip)) {
6619 gint64 disp = (guint8*)target - (guint8*)ip;
6621 if (!amd64_is_imm32 (disp)) {
6622 printf ("TYPE: %d\n", patch_info->type);
6623 switch (patch_info->type) {
6624 case MONO_PATCH_INFO_INTERNAL_METHOD:
6625 printf ("V: %s\n", patch_info->data.name);
6627 case MONO_PATCH_INFO_METHOD_JUMP:
6628 case MONO_PATCH_INFO_METHOD:
6629 printf ("V: %s\n", patch_info->data.method->name);
6637 amd64_patch (ip, (gpointer)target);
6644 get_max_epilog_size (MonoCompile *cfg)
6646 int max_epilog_size = 16;
6648 if (cfg->method->save_lmf)
6649 max_epilog_size += 256;
6651 if (mono_jit_trace_calls != NULL)
6652 max_epilog_size += 50;
6654 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6655 max_epilog_size += 50;
6657 max_epilog_size += (AMD64_NREG * 2);
6659 return max_epilog_size;
6663 * This macro is used for testing whenever the unwinder works correctly at every point
6664 * where an async exception can happen.
6666 /* This will generate a SIGSEGV at the given point in the code */
6667 #define async_exc_point(code) do { \
6668 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6669 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6670 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6671 cfg->arch.async_point_count ++; \
6676 mono_arch_emit_prolog (MonoCompile *cfg)
6678 MonoMethod *method = cfg->method;
6680 MonoMethodSignature *sig;
6682 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6685 MonoInst *lmf_var = cfg->lmf_var;
6686 gboolean args_clobbered = FALSE;
6687 gboolean trace = FALSE;
6688 #ifdef __native_client_codegen__
6689 guint alignment_check;
6692 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6694 #if defined(__default_codegen__)
6695 code = cfg->native_code = g_malloc (cfg->code_size);
6696 #elif defined(__native_client_codegen__)
6697 /* native_code_alloc is not 32-byte aligned, native_code is. */
6698 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6700 /* Align native_code to next nearest kNaclAlignment byte. */
6701 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6702 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6704 code = cfg->native_code;
6706 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6707 g_assert (alignment_check == 0);
6710 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6713 /* Amount of stack space allocated by register saving code */
6716 /* Offset between RSP and the CFA */
6720 * The prolog consists of the following parts:
6722 * - push rbp, mov rbp, rsp
6723 * - save callee saved regs using pushes
6725 * - save rgctx if needed
6726 * - save lmf if needed
6729 * - save rgctx if needed
6730 * - save lmf if needed
6731 * - save callee saved regs using moves
6736 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6737 // IP saved at CFA - 8
6738 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6739 async_exc_point (code);
6740 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6742 if (!cfg->arch.omit_fp) {
6743 amd64_push_reg (code, AMD64_RBP);
6745 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6746 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6747 async_exc_point (code);
6749 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6751 /* These are handled automatically by the stack marking code */
6752 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6754 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6755 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6756 async_exc_point (code);
6758 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6762 /* The param area is always at offset 0 from sp */
6763 /* This needs to be allocated here, since it has to come after the spill area */
6764 if (cfg->param_area) {
6765 if (cfg->arch.omit_fp)
6767 g_assert_not_reached ();
6768 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6771 if (cfg->arch.omit_fp) {
6773 * On enter, the stack is misaligned by the pushing of the return
6774 * address. It is either made aligned by the pushing of %rbp, or by
6777 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6778 if ((alloc_size % 16) == 0) {
6780 /* Mark the padding slot as NOREF */
6781 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6784 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6785 if (cfg->stack_offset != alloc_size) {
6786 /* Mark the padding slot as NOREF */
6787 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6789 cfg->arch.sp_fp_offset = alloc_size;
6793 cfg->arch.stack_alloc_size = alloc_size;
6795 /* Allocate stack frame */
6797 /* See mono_emit_stack_alloc */
6798 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6799 guint32 remaining_size = alloc_size;
6800 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6801 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6802 guint32 offset = code - cfg->native_code;
6803 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6804 while (required_code_size >= (cfg->code_size - offset))
6805 cfg->code_size *= 2;
6806 cfg->native_code = mono_realloc_native_code (cfg);
6807 code = cfg->native_code + offset;
6808 cfg->stat_code_reallocs++;
6811 while (remaining_size >= 0x1000) {
6812 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6813 if (cfg->arch.omit_fp) {
6814 cfa_offset += 0x1000;
6815 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6817 async_exc_point (code);
6819 if (cfg->arch.omit_fp)
6820 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6823 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6824 remaining_size -= 0x1000;
6826 if (remaining_size) {
6827 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6828 if (cfg->arch.omit_fp) {
6829 cfa_offset += remaining_size;
6830 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6831 async_exc_point (code);
6834 if (cfg->arch.omit_fp)
6835 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6839 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6840 if (cfg->arch.omit_fp) {
6841 cfa_offset += alloc_size;
6842 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6843 async_exc_point (code);
6848 /* Stack alignment check */
6851 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6852 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6853 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6854 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6855 amd64_breakpoint (code);
6859 if (mini_get_debug_options ()->init_stacks) {
6860 /* Fill the stack frame with a dummy value to force deterministic behavior */
6862 /* Save registers to the red zone */
6863 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6864 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6866 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6867 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6868 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6871 #if defined(__default_codegen__)
6872 amd64_prefix (code, X86_REP_PREFIX);
6874 #elif defined(__native_client_codegen__)
6875 /* NaCl stos pseudo-instruction */
6876 amd64_codegen_pre (code);
6877 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6878 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6879 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6880 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6881 amd64_prefix (code, X86_REP_PREFIX);
6883 amd64_codegen_post (code);
6884 #endif /* __native_client_codegen__ */
6886 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6887 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6891 if (method->save_lmf)
6892 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6894 /* Save callee saved registers */
6895 if (cfg->arch.omit_fp) {
6896 save_area_offset = cfg->arch.reg_save_area_offset;
6897 /* Save caller saved registers after sp is adjusted */
6898 /* The registers are saved at the bottom of the frame */
6899 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6901 /* The registers are saved just below the saved rbp */
6902 save_area_offset = cfg->arch.reg_save_area_offset;
6905 for (i = 0; i < AMD64_NREG; ++i) {
6906 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6907 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6909 if (cfg->arch.omit_fp) {
6910 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6911 /* These are handled automatically by the stack marking code */
6912 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6914 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6918 save_area_offset += 8;
6919 async_exc_point (code);
6923 /* store runtime generic context */
6924 if (cfg->rgctx_var) {
6925 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6926 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6928 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6930 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6931 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6934 /* compute max_length in order to use short forward jumps */
6935 max_epilog_size = get_max_epilog_size (cfg);
6936 if (cfg->opt & MONO_OPT_BRANCH) {
6937 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6941 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6943 /* max alignment for loops */
6944 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6945 max_length += LOOP_ALIGNMENT;
6946 #ifdef __native_client_codegen__
6947 /* max alignment for native client */
6948 max_length += kNaClAlignment;
6951 MONO_BB_FOR_EACH_INS (bb, ins) {
6952 #ifdef __native_client_codegen__
6954 int space_in_block = kNaClAlignment -
6955 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6956 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6957 if (space_in_block < max_len && max_len < kNaClAlignment) {
6958 max_length += space_in_block;
6961 #endif /*__native_client_codegen__*/
6962 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6965 /* Take prolog and epilog instrumentation into account */
6966 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6967 max_length += max_epilog_size;
6969 bb->max_length = max_length;
6973 sig = mono_method_signature (method);
6976 cinfo = cfg->arch.cinfo;
6978 if (sig->ret->type != MONO_TYPE_VOID) {
6979 /* Save volatile arguments to the stack */
6980 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6981 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6984 /* Keep this in sync with emit_load_volatile_arguments */
6985 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6986 ArgInfo *ainfo = cinfo->args + i;
6988 ins = cfg->args [i];
6990 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6991 /* Unused arguments */
6994 if (cfg->globalra) {
6995 /* All the other moves are done by the register allocator */
6996 switch (ainfo->storage) {
6997 case ArgInFloatSSEReg:
6998 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
7000 case ArgValuetypeInReg:
7001 for (quad = 0; quad < 2; quad ++) {
7002 switch (ainfo->pair_storage [quad]) {
7004 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7006 case ArgInFloatSSEReg:
7007 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7009 case ArgInDoubleSSEReg:
7010 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7015 g_assert_not_reached ();
7026 /* Save volatile arguments to the stack */
7027 if (ins->opcode != OP_REGVAR) {
7028 switch (ainfo->storage) {
7034 if (stack_offset & 0x1)
7036 else if (stack_offset & 0x2)
7038 else if (stack_offset & 0x4)
7043 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7046 * Save the original location of 'this',
7047 * get_generic_info_from_stack_frame () needs this to properly look up
7048 * the argument value during the handling of async exceptions.
7050 if (ins == cfg->args [0]) {
7051 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7052 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7056 case ArgInFloatSSEReg:
7057 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7059 case ArgInDoubleSSEReg:
7060 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7062 case ArgValuetypeInReg:
7063 for (quad = 0; quad < 2; quad ++) {
7064 switch (ainfo->pair_storage [quad]) {
7066 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7068 case ArgInFloatSSEReg:
7069 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7071 case ArgInDoubleSSEReg:
7072 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7077 g_assert_not_reached ();
7081 case ArgValuetypeAddrInIReg:
7082 if (ainfo->pair_storage [0] == ArgInIReg)
7083 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7089 /* Argument allocated to (non-volatile) register */
7090 switch (ainfo->storage) {
7092 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7095 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7098 g_assert_not_reached ();
7101 if (ins == cfg->args [0]) {
7102 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7103 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7108 if (cfg->method->save_lmf)
7109 args_clobbered = TRUE;
7112 args_clobbered = TRUE;
7113 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7116 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7117 args_clobbered = TRUE;
7120 * Optimize the common case of the first bblock making a call with the same
7121 * arguments as the method. This works because the arguments are still in their
7122 * original argument registers.
7123 * FIXME: Generalize this
7125 if (!args_clobbered) {
7126 MonoBasicBlock *first_bb = cfg->bb_entry;
7128 int filter = FILTER_IL_SEQ_POINT;
7130 next = mono_bb_first_inst (first_bb, filter);
7131 if (!next && first_bb->next_bb) {
7132 first_bb = first_bb->next_bb;
7133 next = mono_bb_first_inst (first_bb, filter);
7136 if (first_bb->in_count > 1)
7139 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7140 ArgInfo *ainfo = cinfo->args + i;
7141 gboolean match = FALSE;
7143 ins = cfg->args [i];
7144 if (ins->opcode != OP_REGVAR) {
7145 switch (ainfo->storage) {
7147 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7148 if (next->dreg == ainfo->reg) {
7152 next->opcode = OP_MOVE;
7153 next->sreg1 = ainfo->reg;
7154 /* Only continue if the instruction doesn't change argument regs */
7155 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7165 /* Argument allocated to (non-volatile) register */
7166 switch (ainfo->storage) {
7168 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7179 next = mono_inst_next (next, filter);
7180 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7187 if (cfg->gen_seq_points_debug_data) {
7188 MonoInst *info_var = cfg->arch.seq_point_info_var;
7190 /* Initialize seq_point_info_var */
7191 if (cfg->compile_aot) {
7192 /* Initialize the variable from a GOT slot */
7193 /* Same as OP_AOTCONST */
7194 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7195 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7196 g_assert (info_var->opcode == OP_REGOFFSET);
7197 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7200 /* Initialize ss_trigger_page_var */
7201 ins = cfg->arch.ss_trigger_page_var;
7203 g_assert (ins->opcode == OP_REGOFFSET);
7205 if (cfg->compile_aot) {
7206 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7207 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7209 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7211 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7214 cfg->code_len = code - cfg->native_code;
7216 g_assert (cfg->code_len < cfg->code_size);
7222 mono_arch_emit_epilog (MonoCompile *cfg)
7224 MonoMethod *method = cfg->method;
7227 int max_epilog_size;
7229 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7230 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7232 max_epilog_size = get_max_epilog_size (cfg);
7234 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7235 cfg->code_size *= 2;
7236 cfg->native_code = mono_realloc_native_code (cfg);
7237 cfg->stat_code_reallocs++;
7239 code = cfg->native_code + cfg->code_len;
7241 cfg->has_unwind_info_for_epilog = TRUE;
7243 /* Mark the start of the epilog */
7244 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7246 /* Save the uwind state which is needed by the out-of-line code */
7247 mono_emit_unwind_op_remember_state (cfg, code);
7249 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7250 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7252 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7254 if (method->save_lmf) {
7255 /* check if we need to restore protection of the stack after a stack overflow */
7256 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7258 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7259 /* we load the value in a separate instruction: this mechanism may be
7260 * used later as a safer way to do thread interruption
7262 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7263 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7265 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7266 /* note that the call trampoline will preserve eax/edx */
7267 x86_call_reg (code, X86_ECX);
7268 x86_patch (patch, code);
7270 /* FIXME: maybe save the jit tls in the prolog */
7272 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7273 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7277 /* Restore callee saved regs */
7278 for (i = 0; i < AMD64_NREG; ++i) {
7279 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7280 /* Restore only used_int_regs, not arch.saved_iregs */
7281 if (cfg->used_int_regs & (1 << i)) {
7282 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7283 mono_emit_unwind_op_same_value (cfg, code, i);
7284 async_exc_point (code);
7286 save_area_offset += 8;
7290 /* Load returned vtypes into registers if needed */
7291 cinfo = cfg->arch.cinfo;
7292 if (cinfo->ret.storage == ArgValuetypeInReg) {
7293 ArgInfo *ainfo = &cinfo->ret;
7294 MonoInst *inst = cfg->ret;
7296 for (quad = 0; quad < 2; quad ++) {
7297 switch (ainfo->pair_storage [quad]) {
7299 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7301 case ArgInFloatSSEReg:
7302 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7304 case ArgInDoubleSSEReg:
7305 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7310 g_assert_not_reached ();
7315 if (cfg->arch.omit_fp) {
7316 if (cfg->arch.stack_alloc_size) {
7317 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7321 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7323 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7324 async_exc_point (code);
7327 /* Restore the unwind state to be the same as before the epilog */
7328 mono_emit_unwind_op_restore_state (cfg, code);
7330 cfg->code_len = code - cfg->native_code;
7332 g_assert (cfg->code_len < cfg->code_size);
7336 mono_arch_emit_exceptions (MonoCompile *cfg)
7338 MonoJumpInfo *patch_info;
7341 MonoClass *exc_classes [16];
7342 guint8 *exc_throw_start [16], *exc_throw_end [16];
7343 guint32 code_size = 0;
7345 /* Compute needed space */
7346 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7347 if (patch_info->type == MONO_PATCH_INFO_EXC)
7349 if (patch_info->type == MONO_PATCH_INFO_R8)
7350 code_size += 8 + 15; /* sizeof (double) + alignment */
7351 if (patch_info->type == MONO_PATCH_INFO_R4)
7352 code_size += 4 + 15; /* sizeof (float) + alignment */
7353 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7354 code_size += 8 + 7; /*sizeof (void*) + alignment */
7357 #ifdef __native_client_codegen__
7358 /* Give us extra room on Native Client. This could be */
7359 /* more carefully calculated, but bundle alignment makes */
7360 /* it much trickier, so *2 like other places is good. */
7364 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7365 cfg->code_size *= 2;
7366 cfg->native_code = mono_realloc_native_code (cfg);
7367 cfg->stat_code_reallocs++;
7370 code = cfg->native_code + cfg->code_len;
7372 /* add code to raise exceptions */
7374 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7375 switch (patch_info->type) {
7376 case MONO_PATCH_INFO_EXC: {
7377 MonoClass *exc_class;
7381 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7383 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7384 g_assert (exc_class);
7385 throw_ip = patch_info->ip.i;
7387 //x86_breakpoint (code);
7388 /* Find a throw sequence for the same exception class */
7389 for (i = 0; i < nthrows; ++i)
7390 if (exc_classes [i] == exc_class)
7393 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7394 x86_jump_code (code, exc_throw_start [i]);
7395 patch_info->type = MONO_PATCH_INFO_NONE;
7399 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7403 exc_classes [nthrows] = exc_class;
7404 exc_throw_start [nthrows] = code;
7406 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7408 patch_info->type = MONO_PATCH_INFO_NONE;
7410 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7412 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7417 exc_throw_end [nthrows] = code;
7427 g_assert(code < cfg->native_code + cfg->code_size);
7430 /* Handle relocations with RIP relative addressing */
7431 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7432 gboolean remove = FALSE;
7433 guint8 *orig_code = code;
7435 switch (patch_info->type) {
7436 case MONO_PATCH_INFO_R8:
7437 case MONO_PATCH_INFO_R4: {
7438 guint8 *pos, *patch_pos;
7441 /* The SSE opcodes require a 16 byte alignment */
7442 #if defined(__default_codegen__)
7443 code = (guint8*)ALIGN_TO (code, 16);
7444 #elif defined(__native_client_codegen__)
7446 /* Pad this out with HLT instructions */
7447 /* or we can get garbage bytes emitted */
7448 /* which will fail validation */
7449 guint8 *aligned_code;
7450 /* extra align to make room for */
7451 /* mov/push below */
7452 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7453 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7454 /* The technique of hiding data in an */
7455 /* instruction has a problem here: we */
7456 /* need the data aligned to a 16-byte */
7457 /* boundary but the instruction cannot */
7458 /* cross the bundle boundary. so only */
7459 /* odd multiples of 16 can be used */
7460 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7463 while (code < aligned_code) {
7464 *(code++) = 0xf4; /* hlt */
7469 pos = cfg->native_code + patch_info->ip.i;
7470 if (IS_REX (pos [1])) {
7471 patch_pos = pos + 5;
7472 target_pos = code - pos - 9;
7475 patch_pos = pos + 4;
7476 target_pos = code - pos - 8;
7479 if (patch_info->type == MONO_PATCH_INFO_R8) {
7480 #ifdef __native_client_codegen__
7481 /* Hide 64-bit data in a */
7482 /* "mov imm64, r11" instruction. */
7483 /* write it before the start of */
7485 *(code-2) = 0x49; /* prefix */
7486 *(code-1) = 0xbb; /* mov X, %r11 */
7488 *(double*)code = *(double*)patch_info->data.target;
7489 code += sizeof (double);
7491 #ifdef __native_client_codegen__
7492 /* Hide 32-bit data in a */
7493 /* "push imm32" instruction. */
7494 *(code-1) = 0x68; /* push */
7496 *(float*)code = *(float*)patch_info->data.target;
7497 code += sizeof (float);
7500 *(guint32*)(patch_pos) = target_pos;
7505 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7508 if (cfg->compile_aot)
7511 /*loading is faster against aligned addresses.*/
7512 code = (guint8*)ALIGN_TO (code, 8);
7513 memset (orig_code, 0, code - orig_code);
7515 pos = cfg->native_code + patch_info->ip.i;
7517 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7518 if (IS_REX (pos [1]))
7519 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7521 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7523 *(gpointer*)code = (gpointer)patch_info->data.target;
7524 code += sizeof (gpointer);
7534 if (patch_info == cfg->patch_info)
7535 cfg->patch_info = patch_info->next;
7539 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7541 tmp->next = patch_info->next;
7544 g_assert (code < cfg->native_code + cfg->code_size);
7547 cfg->code_len = code - cfg->native_code;
7549 g_assert (cfg->code_len < cfg->code_size);
7553 #endif /* DISABLE_JIT */
7556 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7559 MonoMethodSignature *sig;
7561 int i, n, stack_area = 0;
7563 /* Keep this in sync with mono_arch_get_argument_info */
7565 if (enable_arguments) {
7566 /* Allocate a new area on the stack and save arguments there */
7567 sig = mono_method_signature (cfg->method);
7569 n = sig->param_count + sig->hasthis;
7571 stack_area = ALIGN_TO (n * 8, 16);
7573 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7575 for (i = 0; i < n; ++i) {
7576 inst = cfg->args [i];
7578 if (inst->opcode == OP_REGVAR)
7579 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7581 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7582 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7587 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7588 amd64_set_reg_template (code, AMD64_ARG_REG1);
7589 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7590 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7592 if (enable_arguments)
7593 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7607 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7610 int save_mode = SAVE_NONE;
7611 MonoMethod *method = cfg->method;
7612 MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7615 switch (ret_type->type) {
7616 case MONO_TYPE_VOID:
7617 /* special case string .ctor icall */
7618 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7619 save_mode = SAVE_EAX;
7621 save_mode = SAVE_NONE;
7625 save_mode = SAVE_EAX;
7629 save_mode = SAVE_XMM;
7631 case MONO_TYPE_GENERICINST:
7632 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7633 save_mode = SAVE_EAX;
7637 case MONO_TYPE_VALUETYPE:
7638 save_mode = SAVE_STRUCT;
7641 save_mode = SAVE_EAX;
7645 /* Save the result and copy it into the proper argument register */
7646 switch (save_mode) {
7648 amd64_push_reg (code, AMD64_RAX);
7650 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7651 if (enable_arguments)
7652 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7656 if (enable_arguments)
7657 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7660 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7661 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7663 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7665 * The result is already in the proper argument register so no copying
7672 g_assert_not_reached ();
7675 /* Set %al since this is a varargs call */
7676 if (save_mode == SAVE_XMM)
7677 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7679 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7681 if (preserve_argument_registers) {
7682 for (i = 0; i < PARAM_REGS; ++i)
7683 amd64_push_reg (code, param_regs [i]);
7686 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7687 amd64_set_reg_template (code, AMD64_ARG_REG1);
7688 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7690 if (preserve_argument_registers) {
7691 for (i = PARAM_REGS - 1; i >= 0; --i)
7692 amd64_pop_reg (code, param_regs [i]);
7695 /* Restore result */
7696 switch (save_mode) {
7698 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7699 amd64_pop_reg (code, AMD64_RAX);
7705 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7706 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7707 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7712 g_assert_not_reached ();
7719 mono_arch_flush_icache (guint8 *code, gint size)
7725 mono_arch_flush_register_windows (void)
7730 mono_arch_is_inst_imm (gint64 imm)
7732 return amd64_is_imm32 (imm);
7736 * Determine whenever the trap whose info is in SIGINFO is caused by
7740 mono_arch_is_int_overflow (void *sigctx, void *info)
7747 mono_sigctx_to_monoctx (sigctx, &ctx);
7749 rip = (guint8*)ctx.rip;
7751 if (IS_REX (rip [0])) {
7752 reg = amd64_rex_b (rip [0]);
7758 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7760 reg += x86_modrm_rm (rip [1]);
7800 g_assert_not_reached ();
7812 mono_arch_get_patch_offset (guint8 *code)
7818 * mono_breakpoint_clean_code:
7820 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7821 * breakpoints in the original code, they are removed in the copy.
7823 * Returns TRUE if no sw breakpoint was present.
7826 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7829 * If method_start is non-NULL we need to perform bound checks, since we access memory
7830 * at code - offset we could go before the start of the method and end up in a different
7831 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7834 if (!method_start || code - offset >= method_start) {
7835 memcpy (buf, code - offset, size);
7837 int diff = code - method_start;
7838 memset (buf, 0, size);
7839 memcpy (buf + offset - diff, method_start, diff + size - offset);
7844 #if defined(__native_client_codegen__)
7845 /* For membase calls, we want the base register. for Native Client, */
7846 /* all indirect calls have the following sequence with the given sizes: */
7847 /* mov %eXX,%eXX [2-3] */
7848 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7849 /* and $0xffffffffffffffe0,%r11d [4] */
7850 /* add %r15,%r11 [3] */
7851 /* callq *%r11 [3] */
7854 /* Determine if code points to a NaCl call-through-register sequence, */
7855 /* (i.e., the last 3 instructions listed above) */
7857 is_nacl_call_reg_sequence(guint8* code)
7859 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7860 "\x4d\x03\xdf" /* add */
7861 "\x41\xff\xd3"; /* call */
7862 return memcmp(code, sequence, 10) == 0;
7865 /* Determine if code points to the first opcode of the mov membase component */
7866 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7867 /* (there could be a REX prefix before the opcode but it is ignored) */
7869 is_nacl_indirect_call_membase_sequence(guint8* code)
7871 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7872 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7873 /* and that src reg = dest reg */
7874 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7875 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7877 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7878 /* and has dst of r11 and base of r15 */
7879 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7880 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7882 #endif /* __native_client_codegen__ */
7885 mono_arch_get_this_arg_reg (guint8 *code)
7887 return AMD64_ARG_REG1;
7891 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7893 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7896 #define MAX_ARCH_DELEGATE_PARAMS 10
7899 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7901 guint8 *code, *start;
7905 start = code = mono_global_codeman_reserve (64);
7907 /* Replace the this argument with the target */
7908 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7909 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7910 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7912 g_assert ((code - start) < 64);
7914 start = code = mono_global_codeman_reserve (64);
7916 if (param_count == 0) {
7917 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7919 /* We have to shift the arguments left */
7920 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7921 for (i = 0; i < param_count; ++i) {
7924 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7926 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7928 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7932 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7934 g_assert ((code - start) < 64);
7937 nacl_global_codeman_validate (&start, 64, &code);
7938 mono_arch_flush_icache (start, code - start);
7941 *code_len = code - start;
7943 if (mono_jit_map_is_enabled ()) {
7946 buff = (char*)"delegate_invoke_has_target";
7948 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7949 mono_emit_jit_tramp (start, code - start, buff);
7953 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7959 * mono_arch_get_delegate_invoke_impls:
7961 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7965 mono_arch_get_delegate_invoke_impls (void)
7973 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7974 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7976 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7977 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7978 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7979 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7980 g_free (tramp_name);
7987 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7989 guint8 *code, *start;
7992 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7995 /* FIXME: Support more cases */
7996 if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
8000 static guint8* cached = NULL;
8006 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8008 start = get_delegate_invoke_impl (TRUE, 0, NULL);
8010 mono_memory_barrier ();
8014 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8015 for (i = 0; i < sig->param_count; ++i)
8016 if (!mono_is_regsize_var (sig->params [i]))
8018 if (sig->param_count > 4)
8021 code = cache [sig->param_count];
8025 if (mono_aot_only) {
8026 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8027 start = mono_aot_get_trampoline (name);
8030 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8033 mono_memory_barrier ();
8035 cache [sig->param_count] = start;
8042 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8044 guint8 *code, *start;
8047 start = code = mono_global_codeman_reserve (size);
8049 /* Replace the this argument with the target */
8050 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8051 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8054 /* Load the IMT reg */
8055 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8058 /* Load the vtable */
8059 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8060 amd64_jump_membase (code, AMD64_RAX, offset);
8061 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8067 mono_arch_finish_init (void)
8069 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8070 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8075 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8079 #if defined(__default_codegen__)
8080 #define CMP_SIZE (6 + 1)
8081 #define CMP_REG_REG_SIZE (4 + 1)
8082 #define BR_SMALL_SIZE 2
8083 #define BR_LARGE_SIZE 6
8084 #define MOV_REG_IMM_SIZE 10
8085 #define MOV_REG_IMM_32BIT_SIZE 6
8086 #define JUMP_REG_SIZE (2 + 1)
8087 #elif defined(__native_client_codegen__)
8088 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8089 #define CMP_SIZE ((6 + 1) * 2 - 1)
8090 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8091 #define BR_SMALL_SIZE (2 * 2 - 1)
8092 #define BR_LARGE_SIZE (6 * 2 - 1)
8093 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8094 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8095 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8096 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8097 /* Jump membase's size is large and unpredictable */
8098 /* in native client, just pad it out a whole bundle. */
8099 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8103 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8105 int i, distance = 0;
8106 for (i = start; i < target; ++i)
8107 distance += imt_entries [i]->chunk_size;
8112 * LOCKING: called with the domain lock held
8115 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8116 gpointer fail_tramp)
8120 guint8 *code, *start;
8121 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8123 for (i = 0; i < count; ++i) {
8124 MonoIMTCheckItem *item = imt_entries [i];
8125 if (item->is_equals) {
8126 if (item->check_target_idx) {
8127 if (!item->compare_done) {
8128 if (amd64_is_imm32 (item->key))
8129 item->chunk_size += CMP_SIZE;
8131 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8133 if (item->has_target_code) {
8134 item->chunk_size += MOV_REG_IMM_SIZE;
8136 if (vtable_is_32bit)
8137 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8139 item->chunk_size += MOV_REG_IMM_SIZE;
8140 #ifdef __native_client_codegen__
8141 item->chunk_size += JUMP_MEMBASE_SIZE;
8144 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8147 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8148 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8150 if (vtable_is_32bit)
8151 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8153 item->chunk_size += MOV_REG_IMM_SIZE;
8154 item->chunk_size += JUMP_REG_SIZE;
8155 /* with assert below:
8156 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8158 #ifdef __native_client_codegen__
8159 item->chunk_size += JUMP_MEMBASE_SIZE;
8164 if (amd64_is_imm32 (item->key))
8165 item->chunk_size += CMP_SIZE;
8167 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8168 item->chunk_size += BR_LARGE_SIZE;
8169 imt_entries [item->check_target_idx]->compare_done = TRUE;
8171 size += item->chunk_size;
8173 #if defined(__native_client__) && defined(__native_client_codegen__)
8174 /* In Native Client, we don't re-use thunks, allocate from the */
8175 /* normal code manager paths. */
8176 code = mono_domain_code_reserve (domain, size);
8179 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8181 code = mono_domain_code_reserve (domain, size);
8184 for (i = 0; i < count; ++i) {
8185 MonoIMTCheckItem *item = imt_entries [i];
8186 item->code_target = code;
8187 if (item->is_equals) {
8188 gboolean fail_case = !item->check_target_idx && fail_tramp;
8190 if (item->check_target_idx || fail_case) {
8191 if (!item->compare_done || fail_case) {
8192 if (amd64_is_imm32 (item->key))
8193 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8195 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8196 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8199 item->jmp_code = code;
8200 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8201 if (item->has_target_code) {
8202 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8203 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8205 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8206 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8210 amd64_patch (item->jmp_code, code);
8211 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8212 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8213 item->jmp_code = NULL;
8216 /* enable the commented code to assert on wrong method */
8218 if (amd64_is_imm32 (item->key))
8219 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8221 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8222 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8224 item->jmp_code = code;
8225 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8226 /* See the comment below about R10 */
8227 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8228 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8229 amd64_patch (item->jmp_code, code);
8230 amd64_breakpoint (code);
8231 item->jmp_code = NULL;
8233 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8234 needs to be preserved. R10 needs
8235 to be preserved for calls which
8236 require a runtime generic context,
8237 but interface calls don't. */
8238 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8239 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8243 if (amd64_is_imm32 (item->key))
8244 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8246 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8247 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8249 item->jmp_code = code;
8250 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8251 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8253 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8255 g_assert (code - item->code_target <= item->chunk_size);
8257 /* patch the branches to get to the target items */
8258 for (i = 0; i < count; ++i) {
8259 MonoIMTCheckItem *item = imt_entries [i];
8260 if (item->jmp_code) {
8261 if (item->check_target_idx) {
8262 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8268 mono_stats.imt_thunks_size += code - start;
8269 g_assert (code - start <= size);
8271 nacl_domain_code_validate(domain, &start, size, &code);
8272 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8278 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8280 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8284 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8286 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8290 mono_arch_get_cie_program (void)
8294 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8295 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8303 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8305 MonoInst *ins = NULL;
8308 if (cmethod->klass == mono_defaults.math_class) {
8309 if (strcmp (cmethod->name, "Sin") == 0) {
8311 } else if (strcmp (cmethod->name, "Cos") == 0) {
8313 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8315 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8319 if (opcode && fsig->param_count == 1) {
8320 MONO_INST_NEW (cfg, ins, opcode);
8321 ins->type = STACK_R8;
8322 ins->dreg = mono_alloc_freg (cfg);
8323 ins->sreg1 = args [0]->dreg;
8324 MONO_ADD_INS (cfg->cbb, ins);
8328 if (cfg->opt & MONO_OPT_CMOV) {
8329 if (strcmp (cmethod->name, "Min") == 0) {
8330 if (fsig->params [0]->type == MONO_TYPE_I4)
8332 if (fsig->params [0]->type == MONO_TYPE_U4)
8333 opcode = OP_IMIN_UN;
8334 else if (fsig->params [0]->type == MONO_TYPE_I8)
8336 else if (fsig->params [0]->type == MONO_TYPE_U8)
8337 opcode = OP_LMIN_UN;
8338 } else if (strcmp (cmethod->name, "Max") == 0) {
8339 if (fsig->params [0]->type == MONO_TYPE_I4)
8341 if (fsig->params [0]->type == MONO_TYPE_U4)
8342 opcode = OP_IMAX_UN;
8343 else if (fsig->params [0]->type == MONO_TYPE_I8)
8345 else if (fsig->params [0]->type == MONO_TYPE_U8)
8346 opcode = OP_LMAX_UN;
8350 if (opcode && fsig->param_count == 2) {
8351 MONO_INST_NEW (cfg, ins, opcode);
8352 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8353 ins->dreg = mono_alloc_ireg (cfg);
8354 ins->sreg1 = args [0]->dreg;
8355 ins->sreg2 = args [1]->dreg;
8356 MONO_ADD_INS (cfg->cbb, ins);
8360 /* OP_FREM is not IEEE compatible */
8361 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8362 MONO_INST_NEW (cfg, ins, OP_FREM);
8363 ins->inst_i0 = args [0];
8364 ins->inst_i1 = args [1];
8374 mono_arch_print_tree (MonoInst *tree, int arity)
8379 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8382 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8385 case AMD64_RCX: return ctx->rcx;
8386 case AMD64_RDX: return ctx->rdx;
8387 case AMD64_RBX: return ctx->rbx;
8388 case AMD64_RBP: return ctx->rbp;
8389 case AMD64_RSP: return ctx->rsp;
8391 return _CTX_REG (ctx, rax, reg);
8396 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8415 _CTX_REG (ctx, rax, reg) = val;
8420 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8422 gpointer *sp, old_value;
8426 bp = MONO_CONTEXT_GET_BP (ctx);
8427 sp = *(gpointer*)(bp + clause->exvar_offset);
8430 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8439 * mono_arch_emit_load_aotconst:
8441 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8442 * TARGET from the mscorlib GOT in full-aot code.
8443 * On AMD64, the result is placed into R11.
8446 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8448 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8449 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8455 * mono_arch_get_trampolines:
8457 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8461 mono_arch_get_trampolines (gboolean aot)
8463 return mono_amd64_get_exception_trampolines (aot);
8466 /* Soft Debug support */
8467 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8470 * mono_arch_set_breakpoint:
8472 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8473 * The location should contain code emitted by OP_SEQ_POINT.
8476 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8479 guint8 *orig_code = code;
8482 guint32 native_offset = ip - (guint8*)ji->code_start;
8483 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8485 g_assert (info->bp_addrs [native_offset] == 0);
8486 info->bp_addrs [native_offset] = bp_trigger_page;
8489 * In production, we will use int3 (has to fix the size in the md
8490 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8493 g_assert (code [0] == 0x90);
8494 if (breakpoint_size == 8) {
8495 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8497 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8498 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8501 g_assert (code - orig_code == breakpoint_size);
8506 * mono_arch_clear_breakpoint:
8508 * Clear the breakpoint at IP.
8511 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8517 guint32 native_offset = ip - (guint8*)ji->code_start;
8518 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8520 g_assert (info->bp_addrs [native_offset] == 0);
8521 info->bp_addrs [native_offset] = info;
8523 for (i = 0; i < breakpoint_size; ++i)
8529 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8532 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8533 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8538 siginfo_t* sinfo = (siginfo_t*) info;
8539 /* Sometimes the address is off by 4 */
8540 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8548 * mono_arch_skip_breakpoint:
8550 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8551 * we resume, the instruction is not executed again.
8554 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8557 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8558 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8560 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8565 * mono_arch_start_single_stepping:
8567 * Start single stepping.
8570 mono_arch_start_single_stepping (void)
8572 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8576 * mono_arch_stop_single_stepping:
8578 * Stop single stepping.
8581 mono_arch_stop_single_stepping (void)
8583 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8587 * mono_arch_is_single_step_event:
8589 * Return whenever the machine state in SIGCTX corresponds to a single
8593 mono_arch_is_single_step_event (void *info, void *sigctx)
8596 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8597 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8602 siginfo_t* sinfo = (siginfo_t*) info;
8603 /* Sometimes the address is off by 4 */
8604 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8612 * mono_arch_skip_single_step:
8614 * Modify CTX so the ip is placed after the single step trigger instruction,
8615 * we resume, the instruction is not executed again.
8618 mono_arch_skip_single_step (MonoContext *ctx)
8620 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8624 * mono_arch_create_seq_point_info:
8626 * Return a pointer to a data structure which is used by the sequence
8627 * point implementation in AOTed code.
8630 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8636 // FIXME: Add a free function
8638 mono_domain_lock (domain);
8639 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8641 mono_domain_unlock (domain);
8644 ji = mono_jit_info_table_find (domain, (char*)code);
8647 // FIXME: Optimize the size
8648 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8650 info->ss_trigger_page = ss_trigger_page;
8651 info->bp_trigger_page = bp_trigger_page;
8652 /* Initialize to a valid address */
8653 for (i = 0; i < ji->code_size; ++i)
8654 info->bp_addrs [i] = info;
8656 mono_domain_lock (domain);
8657 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8659 mono_domain_unlock (domain);
8666 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8668 ext->lmf.previous_lmf = prev_lmf;
8669 /* Mark that this is a MonoLMFExt */
8670 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8671 ext->lmf.rsp = (gssize)ext;
8677 mono_arch_opcode_supported (int opcode)
8680 case OP_ATOMIC_ADD_I4:
8681 case OP_ATOMIC_ADD_I8:
8682 case OP_ATOMIC_EXCHANGE_I4:
8683 case OP_ATOMIC_EXCHANGE_I8:
8684 case OP_ATOMIC_CAS_I4:
8685 case OP_ATOMIC_CAS_I8:
8686 case OP_ATOMIC_LOAD_I1:
8687 case OP_ATOMIC_LOAD_I2:
8688 case OP_ATOMIC_LOAD_I4:
8689 case OP_ATOMIC_LOAD_I8:
8690 case OP_ATOMIC_LOAD_U1:
8691 case OP_ATOMIC_LOAD_U2:
8692 case OP_ATOMIC_LOAD_U4:
8693 case OP_ATOMIC_LOAD_U8:
8694 case OP_ATOMIC_LOAD_R4:
8695 case OP_ATOMIC_LOAD_R8:
8696 case OP_ATOMIC_STORE_I1:
8697 case OP_ATOMIC_STORE_I2:
8698 case OP_ATOMIC_STORE_I4:
8699 case OP_ATOMIC_STORE_I8:
8700 case OP_ATOMIC_STORE_U1:
8701 case OP_ATOMIC_STORE_U2:
8702 case OP_ATOMIC_STORE_U4:
8703 case OP_ATOMIC_STORE_U8:
8704 case OP_ATOMIC_STORE_R4:
8705 case OP_ATOMIC_STORE_R8: