mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *   Johan Lorensson (lateralusx.github@gmail.com)
  12  *
  13  * (C) 2003 Ximian, Inc.
  14  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  15  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  16  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  17  */
  18 #include "mini.h"
  19 #include <string.h>
  20 #include <math.h>
  21 #ifdef HAVE_UNISTD_H
  22 #include <unistd.h>
  23 #endif
  24
  25 #include <mono/metadata/abi-details.h>
  26 #include <mono/metadata/appdomain.h>
  27 #include <mono/metadata/debug-helpers.h>
  28 #include <mono/metadata/threads.h>
  29 #include <mono/metadata/profiler-private.h>
  30 #include <mono/metadata/mono-debug.h>
  31 #include <mono/metadata/gc-internals.h>
  32 #include <mono/utils/mono-math.h>
  33 #include <mono/utils/mono-mmap.h>
  34 #include <mono/utils/mono-memory-model.h>
  35 #include <mono/utils/mono-tls.h>
  36 #include <mono/utils/mono-hwcap.h>
  37 #include <mono/utils/mono-threads.h>
  38
  39 #include "trace.h"
  40 #include "ir-emit.h"
  41 #include "mini-amd64.h"
  42 #include "cpu-amd64.h"
  43 #include "debugger-agent.h"
  44 #include "mini-gc.h"
  45
  46 #ifdef MONO_XEN_OPT
  47 static gboolean optimize_for_xen = TRUE;
  48 #else
  49 #define optimize_for_xen 0
  50 #endif
  51
  52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  53
  54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  55
  56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  57
  58 #ifdef TARGET_WIN32
  59 /* Under windows, the calling convention is never stdcall */
  60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  61 #else
  62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  63 #endif
  64
  65 /* This mutex protects architecture specific caches */
  66 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  67 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  68 static mono_mutex_t mini_arch_mutex;
  69
  70 /* The single step trampoline */
  71 static gpointer ss_trampoline;
  72
  73 /* The breakpoint trampoline */
  74 static gpointer bp_trampoline;
  75
  76 /* Offset between fp and the first argument in the callee */
  77 #define ARGS_OFFSET 16
  78 #define GP_SCRATCH_REG AMD64_R11
  79
  80 /*
  81  * AMD64 register usage:
  82  * - callee saved registers are used for global register allocation
  83  * - %r11 is used for materializing 64 bit constants in opcodes
  84  * - the rest is used for local allocation
  85  */
  86
  87 /*
  88  * Floating point comparison results:
  89  *                  ZF PF CF
  90  * A > B            0  0  0
  91  * A < B            0  0  1
  92  * A = B            1  0  0
  93  * A > B            0  0  0
  94  * UNORDERED        1  1  1
  95  */
  96
  97 const char*
  98 mono_arch_regname (int reg)
  99 {
 100         switch (reg) {
 101         case AMD64_RAX: return "%rax";
 102         case AMD64_RBX: return "%rbx";
 103         case AMD64_RCX: return "%rcx";
 104         case AMD64_RDX: return "%rdx";
 105         case AMD64_RSP: return "%rsp";
 106         case AMD64_RBP: return "%rbp";
 107         case AMD64_RDI: return "%rdi";
 108         case AMD64_RSI: return "%rsi";
 109         case AMD64_R8: return "%r8";
 110         case AMD64_R9: return "%r9";
 111         case AMD64_R10: return "%r10";
 112         case AMD64_R11: return "%r11";
 113         case AMD64_R12: return "%r12";
 114         case AMD64_R13: return "%r13";
 115         case AMD64_R14: return "%r14";
 116         case AMD64_R15: return "%r15";
 117         }
 118         return "unknown";
 119 }
 120
 121 static const char * packed_xmmregs [] = {
 122         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 123         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 124 };
 125
 126 static const char * single_xmmregs [] = {
 127         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 128         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 129 };
 130
 131 const char*
 132 mono_arch_fregname (int reg)
 133 {
 134         if (reg < AMD64_XMM_NREG)
 135                 return single_xmmregs [reg];
 136         else
 137                 return "unknown";
 138 }
 139
 140 const char *
 141 mono_arch_xregname (int reg)
 142 {
 143         if (reg < AMD64_XMM_NREG)
 144                 return packed_xmmregs [reg];
 145         else
 146                 return "unknown";
 147 }
 148
 149 static gboolean
 150 debug_omit_fp (void)
 151 {
 152 #if 0
 153         return mono_debug_count ();
 154 #else
 155         return TRUE;
 156 #endif
 157 }
 158
 159 static inline gboolean
 160 amd64_is_near_call (guint8 *code)
 161 {
 162         /* Skip REX */
 163         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 164                 code += 1;
 165
 166         return code [0] == 0xe8;
 167 }
 168
 169 static inline gboolean
 170 amd64_use_imm32 (gint64 val)
 171 {
 172         if (mini_get_debug_options()->single_imm_size)
 173                 return FALSE;
 174
 175         return amd64_is_imm32 (val);
 176 }
 177
 178 static void
 179 amd64_patch (unsigned char* code, gpointer target)
 180 {
 181         guint8 rex = 0;
 182
 183         /* Skip REX */
 184         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 185                 rex = code [0];
 186                 code += 1;
 187         }
 188
 189         if ((code [0] & 0xf8) == 0xb8) {
 190                 /* amd64_set_reg_template */
 191                 *(guint64*)(code + 1) = (guint64)target;
 192         }
 193         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 194                 /* mov 0(%rip), %dreg */
 195                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 196         }
 197         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 198                 /* call *<OFFSET>(%rip) */
 199                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 200         }
 201         else if (code [0] == 0xe8) {
 202                 /* call <DISP> */
 203                 gint64 disp = (guint8*)target - (guint8*)code;
 204                 g_assert (amd64_is_imm32 (disp));
 205                 x86_patch (code, (unsigned char*)target);
 206         }
 207         else
 208                 x86_patch (code, (unsigned char*)target);
 209 }
 210
 211 void
 212 mono_amd64_patch (unsigned char* code, gpointer target)
 213 {
 214         amd64_patch (code, target);
 215 }
 216
 217 #define DEBUG(a) if (cfg->verbose_level > 1) a
 218
 219 static void inline
 220 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 221 {
 222     ainfo->offset = *stack_size;
 223
 224     if (*gr >= PARAM_REGS) {
 225                 ainfo->storage = ArgOnStack;
 226                 ainfo->arg_size = sizeof (mgreg_t);
 227                 /* Since the same stack slot size is used for all arg */
 228                 /*  types, it needs to be big enough to hold them all */
 229                 (*stack_size) += sizeof(mgreg_t);
 230     }
 231     else {
 232                 ainfo->storage = ArgInIReg;
 233                 ainfo->reg = param_regs [*gr];
 234                 (*gr) ++;
 235     }
 236 }
 237
 238 static void inline
 239 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 240 {
 241     ainfo->offset = *stack_size;
 242
 243     if (*gr >= FLOAT_PARAM_REGS) {
 244                 ainfo->storage = ArgOnStack;
 245                 ainfo->arg_size = sizeof (mgreg_t);
 246                 /* Since the same stack slot size is used for both float */
 247                 /*  types, it needs to be big enough to hold them both */
 248                 (*stack_size) += sizeof(mgreg_t);
 249     }
 250     else {
 251                 /* A double register */
 252                 if (is_double)
 253                         ainfo->storage = ArgInDoubleSSEReg;
 254                 else
 255                         ainfo->storage = ArgInFloatSSEReg;
 256                 ainfo->reg = *gr;
 257                 (*gr) += 1;
 258     }
 259 }
 260
 261 typedef enum ArgumentClass {
 262         ARG_CLASS_NO_CLASS,
 263         ARG_CLASS_MEMORY,
 264         ARG_CLASS_INTEGER,
 265         ARG_CLASS_SSE
 266 } ArgumentClass;
 267
 268 static ArgumentClass
 269 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 270 {
 271         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 272         MonoType *ptype;
 273
 274         ptype = mini_get_underlying_type (type);
 275         switch (ptype->type) {
 276         case MONO_TYPE_I1:
 277         case MONO_TYPE_U1:
 278         case MONO_TYPE_I2:
 279         case MONO_TYPE_U2:
 280         case MONO_TYPE_I4:
 281         case MONO_TYPE_U4:
 282         case MONO_TYPE_I:
 283         case MONO_TYPE_U:
 284         case MONO_TYPE_STRING:
 285         case MONO_TYPE_OBJECT:
 286         case MONO_TYPE_CLASS:
 287         case MONO_TYPE_SZARRAY:
 288         case MONO_TYPE_PTR:
 289         case MONO_TYPE_FNPTR:
 290         case MONO_TYPE_ARRAY:
 291         case MONO_TYPE_I8:
 292         case MONO_TYPE_U8:
 293                 class2 = ARG_CLASS_INTEGER;
 294                 break;
 295         case MONO_TYPE_R4:
 296         case MONO_TYPE_R8:
 297 #ifdef TARGET_WIN32
 298                 class2 = ARG_CLASS_INTEGER;
 299 #else
 300                 class2 = ARG_CLASS_SSE;
 301 #endif
 302                 break;
 303
 304         case MONO_TYPE_TYPEDBYREF:
 305                 g_assert_not_reached ();
 306
 307         case MONO_TYPE_GENERICINST:
 308                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 309                         class2 = ARG_CLASS_INTEGER;
 310                         break;
 311                 }
 312                 /* fall through */
 313         case MONO_TYPE_VALUETYPE: {
 314                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 315                 int i;
 316
 317                 for (i = 0; i < info->num_fields; ++i) {
 318                         class2 = class1;
 319                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 320                 }
 321                 break;
 322         }
 323         default:
 324                 g_assert_not_reached ();
 325         }
 326
 327         /* Merge */
 328         if (class1 == class2)
 329                 ;
 330         else if (class1 == ARG_CLASS_NO_CLASS)
 331                 class1 = class2;
 332         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 333                 class1 = ARG_CLASS_MEMORY;
 334         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 335                 class1 = ARG_CLASS_INTEGER;
 336         else
 337                 class1 = ARG_CLASS_SSE;
 338
 339         return class1;
 340 }
 341
 342 typedef struct {
 343         MonoType *type;
 344         int size, offset;
 345 } StructFieldInfo;
 346
 347 /*
 348  * collect_field_info_nested:
 349  *
 350  *   Collect field info from KLASS recursively into FIELDS.
 351  */
 352 static void
 353 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
 354 {
 355         MonoMarshalType *info;
 356         int i;
 357
 358         if (pinvoke) {
 359                 info = mono_marshal_load_type_info (klass);
 360                 g_assert(info);
 361                 for (i = 0; i < info->num_fields; ++i) {
 362                         if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 363                                 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
 364                         } else {
 365                                 guint32 align;
 366                                 StructFieldInfo f;
 367
 368                                 f.type = info->fields [i].field->type;
 369                                 f.size = mono_marshal_type_size (info->fields [i].field->type,
 370                                                                                                                            info->fields [i].mspec,
 371                                                                                                                            &align, TRUE, unicode);
 372                                 f.offset = offset + info->fields [i].offset;
 373                                 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
 374                                         /* This can happen with .pack directives eg. 'fixed' arrays */
 375                                         if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
 376                                                 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
 377                                                 g_array_append_val (fields_array, f);
 378                                                 while (f.size + f.offset < info->native_size) {
 379                                                         f.offset += f.size;
 380                                                         g_array_append_val (fields_array, f);
 381                                                 }
 382                                         } else {
 383                                                 f.size = info->native_size - f.offset;
 384                                                 g_array_append_val (fields_array, f);
 385                                         }
 386                                 } else {
 387                                         g_array_append_val (fields_array, f);
 388                                 }
 389                         }
 390                 }
 391         } else {
 392                 gpointer iter;
 393                 MonoClassField *field;
 394
 395                 iter = NULL;
 396                 while ((field = mono_class_get_fields (klass, &iter))) {
 397                         if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
 398                                 continue;
 399                         if (MONO_TYPE_ISSTRUCT (field->type)) {
 400                                 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
 401                         } else {
 402                                 int align;
 403                                 StructFieldInfo f;
 404
 405                                 f.type = field->type;
 406                                 f.size = mono_type_size (field->type, &align);
 407                                 f.offset = field->offset - sizeof (MonoObject) + offset;
 408
 409                                 g_array_append_val (fields_array, f);
 410                         }
 411                 }
 412         }
 413 }
 414
 415 #ifdef TARGET_WIN32
 416
 417 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
 418 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
 419
 420 static gboolean
 421 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
 422 {
 423         gboolean result = FALSE;
 424
 425         assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
 426         assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
 427
 428         arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 429         arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
 430         arg_info->pair_size [0] = 0;
 431         arg_info->pair_size [1] = 0;
 432         arg_info->nregs = 0;
 433
 434         if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
 435                 /* Pass parameter in integer register. */
 436                 arg_info->pair_storage [0] = ArgInIReg;
 437                 arg_info->pair_regs [0] = int_regs [*current_int_reg];
 438                 (*current_int_reg) ++;
 439                 result = TRUE;
 440         } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
 441                 /* Pass parameter in float register. */
 442                 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
 443                 arg_info->pair_regs [0] = float_regs [*current_float_reg];
 444                 (*current_float_reg) ++;
 445                 result = TRUE;
 446         }
 447
 448         if (result == TRUE) {
 449                 arg_info->pair_size [0] = arg_size;
 450                 arg_info->nregs = 1;
 451         }
 452
 453         return result;
 454 }
 455
 456 static inline gboolean
 457 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 458 {
 459         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
 460 }
 461
 462 static inline gboolean
 463 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 464 {
 465         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
 466 }
 467
 468 static void
 469 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
 470                                                                           guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 471 {
 472         /* Windows x64 value type ABI.
 473         *
 474         * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
 475         *
 476         * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
 477         *    Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
 478         * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 479         *    Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
 480         *
 481         * Return values:  https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
 482         *
 483         * Integers/Float types smaller than or equal to 8 bytes
 484         *    Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
 485         * Properly sized struct/unions (1,2,4,8)
 486         *    Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
 487         * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 488         *    Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
 489         */
 490
 491         assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 492
 493         if (!is_return) {
 494
 495                 /* Parameter cases. */
 496                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 497                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 498
 499                         /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
 500                         arg_info->storage = ArgValuetypeInReg;
 501                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 502                                 /* No more registers, fallback passing parameter on stack as value. */
 503                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 504
 505                                 /* Passing value directly on stack, so use size of value. */
 506                                 arg_info->storage = ArgOnStack;
 507                                 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 508                                 arg_info->offset = *stack_size;
 509                                 arg_info->arg_size = arg_size;
 510                                 *stack_size += arg_size;
 511                         }
 512                 } else {
 513                         /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
 514                         arg_info->storage = ArgValuetypeAddrInIReg;
 515                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 516                                 /* No more registers, fallback passing address to parameter on stack. */
 517                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 518
 519                                 /* Passing an address to value on stack, so use size of register as argument size. */
 520                                 arg_info->storage = ArgValuetypeAddrOnStack;
 521                                 arg_size = sizeof (mgreg_t);
 522                                 arg_info->offset = *stack_size;
 523                                 arg_info->arg_size = arg_size;
 524                                 *stack_size += arg_size;
 525                         }
 526                 }
 527         } else {
 528                 /* Return value cases. */
 529                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 530                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 531
 532                         /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
 533                         arg_info->storage = ArgValuetypeInReg;
 534                         allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 535
 536                         /* Only RAX/XMM0 should be used to return valuetype. */
 537                         assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
 538                 } else {
 539                         /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
 540                         arg_info->storage = ArgValuetypeAddrInIReg;
 541                         allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 542
 543                         /* Only RAX should be used to return valuetype address. */
 544                         assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
 545
 546                         arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 547                         arg_info->offset = *stack_size;
 548                         *stack_size += arg_size;
 549                 }
 550         }
 551 }
 552
 553 static void
 554 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
 555 {
 556         *arg_size = 0;
 557         *arg_class = ARG_CLASS_NO_CLASS;
 558
 559         assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
 560
 561         if (pinvoke) {
 562                 /* Calculate argument class type and size of marshalled type. */
 563                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 564                 *arg_size = info->native_size;
 565         } else {
 566                 /* Calculate argument class type and size of managed type. */
 567                 *arg_size = mono_class_value_size (klass, NULL);
 568         }
 569
 570         /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
 571         *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
 572
 573         if (*arg_class == ARG_CLASS_MEMORY) {
 574                 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
 575                 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
 576         }
 577
 578         /*
 579         * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
 580         * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
 581         * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
 582         * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
 583         * it must be represented in call and cannot be dropped.
 584         */
 585         if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
 586                 arg_info->pass_empty_struct = TRUE;
 587                 *arg_size = SIZEOF_REGISTER;
 588                 *arg_class = ARG_CLASS_INTEGER;
 589         }
 590
 591         assert (*arg_class != ARG_CLASS_NO_CLASS);
 592 }
 593
 594 static void
 595 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
 596                                                 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 597 {
 598         guint32 arg_size = SIZEOF_REGISTER;
 599         MonoClass *klass = NULL;
 600         ArgumentClass arg_class;
 601
 602         assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 603
 604         klass = mono_class_from_mono_type (type);
 605         get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
 606
 607         /* Only drop value type if its not an empty struct as input that must be represented in call */
 608         if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
 609                 arg_info->storage = ArgValuetypeInReg;
 610                 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 611         } else {
 612                 /* Alocate storage for value type. */
 613                 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
 614         }
 615 }
 616
 617 #endif /* TARGET_WIN32 */
 618
 619 static void
 620 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 621                            gboolean is_return,
 622                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 623 {
 624 #ifdef TARGET_WIN32
 625         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 626 #else
 627         guint32 size, quad, nquads, i, nfields;
 628         /* Keep track of the size used in each quad so we can */
 629         /* use the right size when copying args/return vars.  */
 630         guint32 quadsize [2] = {8, 8};
 631         ArgumentClass args [2];
 632         StructFieldInfo *fields = NULL;
 633         GArray *fields_array;
 634         MonoClass *klass;
 635         gboolean pass_on_stack = FALSE;
 636         int struct_size;
 637
 638         klass = mono_class_from_mono_type (type);
 639         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 640
 641         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 642                 /* We pass and return vtypes of size 8 in a register */
 643         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 644                 pass_on_stack = TRUE;
 645         }
 646
 647         /* If this struct can't be split up naturally into 8-byte */
 648         /* chunks (registers), pass it on the stack.              */
 649         if (sig->pinvoke) {
 650                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 651                 g_assert (info);
 652                 struct_size = info->native_size;
 653         } else {
 654                 struct_size = mono_class_value_size (klass, NULL);
 655         }
 656         /*
 657          * Collect field information recursively to be able to
 658          * handle nested structures.
 659          */
 660         fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
 661         collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
 662         fields = (StructFieldInfo*)fields_array->data;
 663         nfields = fields_array->len;
 664
 665         for (i = 0; i < nfields; ++i) {
 666                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 667                         pass_on_stack = TRUE;
 668                         break;
 669                 }
 670         }
 671
 672         if (size == 0) {
 673                 ainfo->storage = ArgValuetypeInReg;
 674                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 675                 return;
 676         }
 677
 678         if (pass_on_stack) {
 679                 /* Allways pass in memory */
 680                 ainfo->offset = *stack_size;
 681                 *stack_size += ALIGN_TO (size, 8);
 682                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 683                 if (!is_return)
 684                         ainfo->arg_size = ALIGN_TO (size, 8);
 685
 686                 g_array_free (fields_array, TRUE);
 687                 return;
 688         }
 689
 690         if (size > 8)
 691                 nquads = 2;
 692         else
 693                 nquads = 1;
 694
 695         if (!sig->pinvoke) {
 696                 int n = mono_class_value_size (klass, NULL);
 697
 698                 quadsize [0] = n >= 8 ? 8 : n;
 699                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 700
 701                 /* Always pass in 1 or 2 integer registers */
 702                 args [0] = ARG_CLASS_INTEGER;
 703                 args [1] = ARG_CLASS_INTEGER;
 704                 /* Only the simplest cases are supported */
 705                 if (is_return && nquads != 1) {
 706                         args [0] = ARG_CLASS_MEMORY;
 707                         args [1] = ARG_CLASS_MEMORY;
 708                 }
 709         } else {
 710                 /*
 711                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 712                  * The X87 and SSEUP stuff is left out since there are no such types in
 713                  * the CLR.
 714                  */
 715                 if (!nfields) {
 716                         ainfo->storage = ArgValuetypeInReg;
 717                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 718                         return;
 719                 }
 720
 721                 if (struct_size > 16) {
 722                         ainfo->offset = *stack_size;
 723                         *stack_size += ALIGN_TO (struct_size, 8);
 724                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 725                         if (!is_return)
 726                                 ainfo->arg_size = ALIGN_TO (struct_size, 8);
 727
 728                         g_array_free (fields_array, TRUE);
 729                         return;
 730                 }
 731
 732                 args [0] = ARG_CLASS_NO_CLASS;
 733                 args [1] = ARG_CLASS_NO_CLASS;
 734                 for (quad = 0; quad < nquads; ++quad) {
 735                         ArgumentClass class1;
 736
 737                         if (nfields == 0)
 738                                 class1 = ARG_CLASS_MEMORY;
 739                         else
 740                                 class1 = ARG_CLASS_NO_CLASS;
 741                         for (i = 0; i < nfields; ++i) {
 742                                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 743                                         /* Unaligned field */
 744                                         NOT_IMPLEMENTED;
 745                                 }
 746
 747                                 /* Skip fields in other quad */
 748                                 if ((quad == 0) && (fields [i].offset >= 8))
 749                                         continue;
 750                                 if ((quad == 1) && (fields [i].offset < 8))
 751                                         continue;
 752
 753                                 /* How far into this quad this data extends.*/
 754                                 /* (8 is size of quad) */
 755                                 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
 756
 757                                 class1 = merge_argument_class_from_type (fields [i].type, class1);
 758                         }
 759                         /* Empty structs have a nonzero size, causing this assert to be hit */
 760                         if (sig->pinvoke)
 761                                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 762                         args [quad] = class1;
 763                 }
 764         }
 765
 766         g_array_free (fields_array, TRUE);
 767
 768         /* Post merger cleanup */
 769         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 770                 args [0] = args [1] = ARG_CLASS_MEMORY;
 771
 772         /* Allocate registers */
 773         {
 774                 int orig_gr = *gr;
 775                 int orig_fr = *fr;
 776
 777                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 778                         quadsize [0] ++;
 779                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 780                         quadsize [1] ++;
 781
 782                 ainfo->storage = ArgValuetypeInReg;
 783                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 784                 g_assert (quadsize [0] <= 8);
 785                 g_assert (quadsize [1] <= 8);
 786                 ainfo->pair_size [0] = quadsize [0];
 787                 ainfo->pair_size [1] = quadsize [1];
 788                 ainfo->nregs = nquads;
 789                 for (quad = 0; quad < nquads; ++quad) {
 790                         switch (args [quad]) {
 791                         case ARG_CLASS_INTEGER:
 792                                 if (*gr >= PARAM_REGS)
 793                                         args [quad] = ARG_CLASS_MEMORY;
 794                                 else {
 795                                         ainfo->pair_storage [quad] = ArgInIReg;
 796                                         if (is_return)
 797                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 798                                         else
 799                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 800                                         (*gr) ++;
 801                                 }
 802                                 break;
 803                         case ARG_CLASS_SSE:
 804                                 if (*fr >= FLOAT_PARAM_REGS)
 805                                         args [quad] = ARG_CLASS_MEMORY;
 806                                 else {
 807                                         if (quadsize[quad] <= 4)
 808                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 809                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 810                                         ainfo->pair_regs [quad] = *fr;
 811                                         (*fr) ++;
 812                                 }
 813                                 break;
 814                         case ARG_CLASS_MEMORY:
 815                                 break;
 816                         case ARG_CLASS_NO_CLASS:
 817                                 break;
 818                         default:
 819                                 g_assert_not_reached ();
 820                         }
 821                 }
 822
 823                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 824                         int arg_size;
 825                         /* Revert possible register assignments */
 826                         *gr = orig_gr;
 827                         *fr = orig_fr;
 828
 829                         ainfo->offset = *stack_size;
 830                         if (sig->pinvoke)
 831                                 arg_size = ALIGN_TO (struct_size, 8);
 832                         else
 833                                 arg_size = nquads * sizeof(mgreg_t);
 834                         *stack_size += arg_size;
 835                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 836                         if (!is_return)
 837                                 ainfo->arg_size = arg_size;
 838                 }
 839         }
 840 #endif /* !TARGET_WIN32 */
 841 }
 842
 843 /*
 844  * get_call_info:
 845  *
 846  * Obtain information about a call according to the calling convention.
 847  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 848  * Draft Version 0.23" document for more information.
 849  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 850  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 851  */
 852 static CallInfo*
 853 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 854 {
 855         guint32 i, gr, fr, pstart;
 856         MonoType *ret_type;
 857         int n = sig->hasthis + sig->param_count;
 858         guint32 stack_size = 0;
 859         CallInfo *cinfo;
 860         gboolean is_pinvoke = sig->pinvoke;
 861
 862         if (mp)
 863                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 864         else
 865                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 866
 867         cinfo->nargs = n;
 868         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 869
 870         gr = 0;
 871         fr = 0;
 872
 873 #ifdef TARGET_WIN32
 874         /* Reserve space where the callee can save the argument registers */
 875         stack_size = 4 * sizeof (mgreg_t);
 876 #endif
 877
 878         /* return value */
 879         ret_type = mini_get_underlying_type (sig->ret);
 880         switch (ret_type->type) {
 881         case MONO_TYPE_I1:
 882         case MONO_TYPE_U1:
 883         case MONO_TYPE_I2:
 884         case MONO_TYPE_U2:
 885         case MONO_TYPE_I4:
 886         case MONO_TYPE_U4:
 887         case MONO_TYPE_I:
 888         case MONO_TYPE_U:
 889         case MONO_TYPE_PTR:
 890         case MONO_TYPE_FNPTR:
 891         case MONO_TYPE_CLASS:
 892         case MONO_TYPE_OBJECT:
 893         case MONO_TYPE_SZARRAY:
 894         case MONO_TYPE_ARRAY:
 895         case MONO_TYPE_STRING:
 896                 cinfo->ret.storage = ArgInIReg;
 897                 cinfo->ret.reg = AMD64_RAX;
 898                 break;
 899         case MONO_TYPE_U8:
 900         case MONO_TYPE_I8:
 901                 cinfo->ret.storage = ArgInIReg;
 902                 cinfo->ret.reg = AMD64_RAX;
 903                 break;
 904         case MONO_TYPE_R4:
 905                 cinfo->ret.storage = ArgInFloatSSEReg;
 906                 cinfo->ret.reg = AMD64_XMM0;
 907                 break;
 908         case MONO_TYPE_R8:
 909                 cinfo->ret.storage = ArgInDoubleSSEReg;
 910                 cinfo->ret.reg = AMD64_XMM0;
 911                 break;
 912         case MONO_TYPE_GENERICINST:
 913                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 914                         cinfo->ret.storage = ArgInIReg;
 915                         cinfo->ret.reg = AMD64_RAX;
 916                         break;
 917                 }
 918                 if (mini_is_gsharedvt_type (ret_type)) {
 919                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 920                         break;
 921                 }
 922                 /* fall through */
 923         case MONO_TYPE_VALUETYPE:
 924         case MONO_TYPE_TYPEDBYREF: {
 925                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 926
 927                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 928                 g_assert (cinfo->ret.storage != ArgInIReg);
 929                 break;
 930         }
 931         case MONO_TYPE_VAR:
 932         case MONO_TYPE_MVAR:
 933                 g_assert (mini_is_gsharedvt_type (ret_type));
 934                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 935                 break;
 936         case MONO_TYPE_VOID:
 937                 break;
 938         default:
 939                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 940         }
 941
 942         pstart = 0;
 943         /*
 944          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 945          * the first argument, allowing 'this' to be always passed in the first arg reg.
 946          * Also do this if the first argument is a reference type, since virtual calls
 947          * are sometimes made using calli without sig->hasthis set, like in the delegate
 948          * invoke wrappers.
 949          */
 950         ArgStorage ret_storage = cinfo->ret.storage;
 951         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 952                 if (sig->hasthis) {
 953                         add_general (&gr, &stack_size, cinfo->args + 0);
 954                 } else {
 955                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 956                         pstart = 1;
 957                 }
 958                 add_general (&gr, &stack_size, &cinfo->ret);
 959                 cinfo->ret.storage = ret_storage;
 960                 cinfo->vret_arg_index = 1;
 961         } else {
 962                 /* this */
 963                 if (sig->hasthis)
 964                         add_general (&gr, &stack_size, cinfo->args + 0);
 965
 966                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 967                         add_general (&gr, &stack_size, &cinfo->ret);
 968                         cinfo->ret.storage = ret_storage;
 969                 }
 970         }
 971
 972         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 973                 gr = PARAM_REGS;
 974                 fr = FLOAT_PARAM_REGS;
 975
 976                 /* Emit the signature cookie just before the implicit arguments */
 977                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 978         }
 979
 980         for (i = pstart; i < sig->param_count; ++i) {
 981                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 982                 MonoType *ptype;
 983
 984 #ifdef TARGET_WIN32
 985                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 986                 if (gr > fr)
 987                         fr = gr;
 988                 else if (fr > gr)
 989                         gr = fr;
 990 #endif
 991
 992                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 993                         /* We allways pass the sig cookie on the stack for simplicity */
 994                         /*
 995                          * Prevent implicit arguments + the sig cookie from being passed
 996                          * in registers.
 997                          */
 998                         gr = PARAM_REGS;
 999                         fr = FLOAT_PARAM_REGS;
1000
1001                         /* Emit the signature cookie just before the implicit arguments */
1002                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1003                 }
1004
1005                 ptype = mini_get_underlying_type (sig->params [i]);
1006                 switch (ptype->type) {
1007                 case MONO_TYPE_I1:
1008                 case MONO_TYPE_U1:
1009                         add_general (&gr, &stack_size, ainfo);
1010                         break;
1011                 case MONO_TYPE_I2:
1012                 case MONO_TYPE_U2:
1013                         add_general (&gr, &stack_size, ainfo);
1014                         break;
1015                 case MONO_TYPE_I4:
1016                 case MONO_TYPE_U4:
1017                         add_general (&gr, &stack_size, ainfo);
1018                         break;
1019                 case MONO_TYPE_I:
1020                 case MONO_TYPE_U:
1021                 case MONO_TYPE_PTR:
1022                 case MONO_TYPE_FNPTR:
1023                 case MONO_TYPE_CLASS:
1024                 case MONO_TYPE_OBJECT:
1025                 case MONO_TYPE_STRING:
1026                 case MONO_TYPE_SZARRAY:
1027                 case MONO_TYPE_ARRAY:
1028                         add_general (&gr, &stack_size, ainfo);
1029                         break;
1030                 case MONO_TYPE_GENERICINST:
1031                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1032                                 add_general (&gr, &stack_size, ainfo);
1033                                 break;
1034                         }
1035                         if (mini_is_gsharedvt_variable_type (ptype)) {
1036                                 /* gsharedvt arguments are passed by ref */
1037                                 add_general (&gr, &stack_size, ainfo);
1038                                 if (ainfo->storage == ArgInIReg)
1039                                         ainfo->storage = ArgGSharedVtInReg;
1040                                 else
1041                                         ainfo->storage = ArgGSharedVtOnStack;
1042                                 break;
1043                         }
1044                         /* fall through */
1045                 case MONO_TYPE_VALUETYPE:
1046                 case MONO_TYPE_TYPEDBYREF:
1047                         add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1048                         break;
1049                 case MONO_TYPE_U8:
1050
1051                 case MONO_TYPE_I8:
1052                         add_general (&gr, &stack_size, ainfo);
1053                         break;
1054                 case MONO_TYPE_R4:
1055                         add_float (&fr, &stack_size, ainfo, FALSE);
1056                         break;
1057                 case MONO_TYPE_R8:
1058                         add_float (&fr, &stack_size, ainfo, TRUE);
1059                         break;
1060                 case MONO_TYPE_VAR:
1061                 case MONO_TYPE_MVAR:
1062                         /* gsharedvt arguments are passed by ref */
1063                         g_assert (mini_is_gsharedvt_type (ptype));
1064                         add_general (&gr, &stack_size, ainfo);
1065                         if (ainfo->storage == ArgInIReg)
1066                                 ainfo->storage = ArgGSharedVtInReg;
1067                         else
1068                                 ainfo->storage = ArgGSharedVtOnStack;
1069                         break;
1070                 default:
1071                         g_assert_not_reached ();
1072                 }
1073         }
1074
1075         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1076                 gr = PARAM_REGS;
1077                 fr = FLOAT_PARAM_REGS;
1078
1079                 /* Emit the signature cookie just before the implicit arguments */
1080                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1081         }
1082
1083         cinfo->stack_usage = stack_size;
1084         cinfo->reg_usage = gr;
1085         cinfo->freg_usage = fr;
1086         return cinfo;
1087 }
1088
1089 /*
1090  * mono_arch_get_argument_info:
1091  * @csig:  a method signature
1092  * @param_count: the number of parameters to consider
1093  * @arg_info: an array to store the result infos
1094  *
1095  * Gathers information on parameters such as size, alignment and
1096  * padding. arg_info should be large enought to hold param_count + 1 entries.
1097  *
1098  * Returns the size of the argument area on the stack.
1099  */
1100 int
1101 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1102 {
1103         int k;
1104         CallInfo *cinfo = get_call_info (NULL, csig);
1105         guint32 args_size = cinfo->stack_usage;
1106
1107         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1108         if (csig->hasthis) {
1109                 arg_info [0].offset = 0;
1110         }
1111
1112         for (k = 0; k < param_count; k++) {
1113                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1114                 /* FIXME: */
1115                 arg_info [k + 1].size = 0;
1116         }
1117
1118         g_free (cinfo);
1119
1120         return args_size;
1121 }
1122
1123 gboolean
1124 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1125 {
1126         CallInfo *c1, *c2;
1127         gboolean res;
1128         MonoType *callee_ret;
1129
1130         c1 = get_call_info (NULL, caller_sig);
1131         c2 = get_call_info (NULL, callee_sig);
1132         res = c1->stack_usage >= c2->stack_usage;
1133         callee_ret = mini_get_underlying_type (callee_sig->ret);
1134         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1135                 /* An address on the callee's stack is passed as the first argument */
1136                 res = FALSE;
1137
1138         g_free (c1);
1139         g_free (c2);
1140
1141         return res;
1142 }
1143
1144 /*
1145  * Initialize the cpu to execute managed code.
1146  */
1147 void
1148 mono_arch_cpu_init (void)
1149 {
1150 #ifndef _MSC_VER
1151         guint16 fpcw;
1152
1153         /* spec compliance requires running with double precision */
1154         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1155         fpcw &= ~X86_FPCW_PRECC_MASK;
1156         fpcw |= X86_FPCW_PREC_DOUBLE;
1157         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1158         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1159 #else
1160         /* TODO: This is crashing on Win64 right now.
1161         * _control87 (_PC_53, MCW_PC);
1162         */
1163 #endif
1164 }
1165
1166 /*
1167  * Initialize architecture specific code.
1168  */
1169 void
1170 mono_arch_init (void)
1171 {
1172         mono_os_mutex_init_recursive (&mini_arch_mutex);
1173
1174         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1175         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1176         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1177         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1178         mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1179
1180 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1181         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1182 #endif
1183
1184         if (!mono_aot_only)
1185                 bp_trampoline = mini_get_breakpoint_trampoline ();
1186 }
1187
1188 /*
1189  * Cleanup architecture specific code.
1190  */
1191 void
1192 mono_arch_cleanup (void)
1193 {
1194         mono_os_mutex_destroy (&mini_arch_mutex);
1195 }
1196
1197 /*
1198  * This function returns the optimizations supported on this cpu.
1199  */
1200 guint32
1201 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1202 {
1203         guint32 opts = 0;
1204
1205         *exclude_mask = 0;
1206
1207         if (mono_hwcap_x86_has_cmov) {
1208                 opts |= MONO_OPT_CMOV;
1209
1210                 if (mono_hwcap_x86_has_fcmov)
1211                         opts |= MONO_OPT_FCMOV;
1212                 else
1213                         *exclude_mask |= MONO_OPT_FCMOV;
1214         } else {
1215                 *exclude_mask |= MONO_OPT_CMOV;
1216         }
1217
1218 #ifdef TARGET_WIN32
1219         /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1220         /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1221         /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1222         /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1223         /* will now have a reference to an argument that won't be fully decomposed. */
1224         *exclude_mask |= MONO_OPT_SIMD;
1225 #endif
1226
1227         return opts;
1228 }
1229
1230 /*
1231  * This function test for all SSE functions supported.
1232  *
1233  * Returns a bitmask corresponding to all supported versions.
1234  *
1235  */
1236 guint32
1237 mono_arch_cpu_enumerate_simd_versions (void)
1238 {
1239         guint32 sse_opts = 0;
1240
1241         if (mono_hwcap_x86_has_sse1)
1242                 sse_opts |= SIMD_VERSION_SSE1;
1243
1244         if (mono_hwcap_x86_has_sse2)
1245                 sse_opts |= SIMD_VERSION_SSE2;
1246
1247         if (mono_hwcap_x86_has_sse3)
1248                 sse_opts |= SIMD_VERSION_SSE3;
1249
1250         if (mono_hwcap_x86_has_ssse3)
1251                 sse_opts |= SIMD_VERSION_SSSE3;
1252
1253         if (mono_hwcap_x86_has_sse41)
1254                 sse_opts |= SIMD_VERSION_SSE41;
1255
1256         if (mono_hwcap_x86_has_sse42)
1257                 sse_opts |= SIMD_VERSION_SSE42;
1258
1259         if (mono_hwcap_x86_has_sse4a)
1260                 sse_opts |= SIMD_VERSION_SSE4a;
1261
1262         return sse_opts;
1263 }
1264
1265 #ifndef DISABLE_JIT
1266
1267 GList *
1268 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1269 {
1270         GList *vars = NULL;
1271         int i;
1272
1273         for (i = 0; i < cfg->num_varinfo; i++) {
1274                 MonoInst *ins = cfg->varinfo [i];
1275                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1276
1277                 /* unused vars */
1278                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1279                         continue;
1280
1281                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1282                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1283                         continue;
1284
1285                 if (mono_is_regsize_var (ins->inst_vtype)) {
1286                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1287                         g_assert (i == vmv->idx);
1288                         vars = g_list_prepend (vars, vmv);
1289                 }
1290         }
1291
1292         vars = mono_varlist_sort (cfg, vars, 0);
1293
1294         return vars;
1295 }
1296
1297 /**
1298  * mono_arch_compute_omit_fp:
1299  *
1300  *   Determine whenever the frame pointer can be eliminated.
1301  */
1302 static void
1303 mono_arch_compute_omit_fp (MonoCompile *cfg)
1304 {
1305         MonoMethodSignature *sig;
1306         MonoMethodHeader *header;
1307         int i, locals_size;
1308         CallInfo *cinfo;
1309
1310         if (cfg->arch.omit_fp_computed)
1311                 return;
1312
1313         header = cfg->header;
1314
1315         sig = mono_method_signature (cfg->method);
1316
1317         if (!cfg->arch.cinfo)
1318                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1319         cinfo = (CallInfo *)cfg->arch.cinfo;
1320
1321         /*
1322          * FIXME: Remove some of the restrictions.
1323          */
1324         cfg->arch.omit_fp = TRUE;
1325         cfg->arch.omit_fp_computed = TRUE;
1326
1327         if (cfg->disable_omit_fp)
1328                 cfg->arch.omit_fp = FALSE;
1329
1330         if (!debug_omit_fp ())
1331                 cfg->arch.omit_fp = FALSE;
1332         /*
1333         if (cfg->method->save_lmf)
1334                 cfg->arch.omit_fp = FALSE;
1335         */
1336         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1337                 cfg->arch.omit_fp = FALSE;
1338         if (header->num_clauses)
1339                 cfg->arch.omit_fp = FALSE;
1340         if (cfg->param_area)
1341                 cfg->arch.omit_fp = FALSE;
1342         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1343                 cfg->arch.omit_fp = FALSE;
1344         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1345                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1346                 cfg->arch.omit_fp = FALSE;
1347         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1348                 ArgInfo *ainfo = &cinfo->args [i];
1349
1350                 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1351                         /*
1352                          * The stack offset can only be determined when the frame
1353                          * size is known.
1354                          */
1355                         cfg->arch.omit_fp = FALSE;
1356                 }
1357         }
1358
1359         locals_size = 0;
1360         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1361                 MonoInst *ins = cfg->varinfo [i];
1362                 int ialign;
1363
1364                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1365         }
1366 }
1367
1368 GList *
1369 mono_arch_get_global_int_regs (MonoCompile *cfg)
1370 {
1371         GList *regs = NULL;
1372
1373         mono_arch_compute_omit_fp (cfg);
1374
1375         if (cfg->arch.omit_fp)
1376                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1377
1378         /* We use the callee saved registers for global allocation */
1379         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1380         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1381         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1382         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1383         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1384 #ifdef TARGET_WIN32
1385         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1386         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1387 #endif
1388
1389         return regs;
1390 }
1391
1392 GList*
1393 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1394 {
1395         GList *regs = NULL;
1396         int i;
1397
1398         /* All XMM registers */
1399         for (i = 0; i < 16; ++i)
1400                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1401
1402         return regs;
1403 }
1404
1405 GList*
1406 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1407 {
1408         static GList *r = NULL;
1409
1410         if (r == NULL) {
1411                 GList *regs = NULL;
1412
1413                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1414                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1415                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1416                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1417                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1418                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1419
1420                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1421                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1422                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1423                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1424                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1425                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1426                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1427                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1428
1429                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1430         }
1431
1432         return r;
1433 }
1434
1435 GList*
1436 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1437 {
1438         int i;
1439         static GList *r = NULL;
1440
1441         if (r == NULL) {
1442                 GList *regs = NULL;
1443
1444                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1445                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1446
1447                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1448         }
1449
1450         return r;
1451 }
1452
1453 /*
1454  * mono_arch_regalloc_cost:
1455  *
1456  *  Return the cost, in number of memory references, of the action of
1457  * allocating the variable VMV into a register during global register
1458  * allocation.
1459  */
1460 guint32
1461 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1462 {
1463         MonoInst *ins = cfg->varinfo [vmv->idx];
1464
1465         if (cfg->method->save_lmf)
1466                 /* The register is already saved */
1467                 /* substract 1 for the invisible store in the prolog */
1468                 return (ins->opcode == OP_ARG) ? 0 : 1;
1469         else
1470                 /* push+pop */
1471                 return (ins->opcode == OP_ARG) ? 1 : 2;
1472 }
1473
1474 /*
1475  * mono_arch_fill_argument_info:
1476  *
1477  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1478  * of the method.
1479  */
1480 void
1481 mono_arch_fill_argument_info (MonoCompile *cfg)
1482 {
1483         MonoType *sig_ret;
1484         MonoMethodSignature *sig;
1485         MonoInst *ins;
1486         int i;
1487         CallInfo *cinfo;
1488
1489         sig = mono_method_signature (cfg->method);
1490
1491         cinfo = (CallInfo *)cfg->arch.cinfo;
1492         sig_ret = mini_get_underlying_type (sig->ret);
1493
1494         /*
1495          * Contrary to mono_arch_allocate_vars (), the information should describe
1496          * where the arguments are at the beginning of the method, not where they can be
1497          * accessed during the execution of the method. The later makes no sense for the
1498          * global register allocator, since a variable can be in more than one location.
1499          */
1500         switch (cinfo->ret.storage) {
1501         case ArgInIReg:
1502         case ArgInFloatSSEReg:
1503         case ArgInDoubleSSEReg:
1504                 cfg->ret->opcode = OP_REGVAR;
1505                 cfg->ret->inst_c0 = cinfo->ret.reg;
1506                 break;
1507         case ArgValuetypeInReg:
1508                 cfg->ret->opcode = OP_REGOFFSET;
1509                 cfg->ret->inst_basereg = -1;
1510                 cfg->ret->inst_offset = -1;
1511                 break;
1512         case ArgNone:
1513                 break;
1514         default:
1515                 g_assert_not_reached ();
1516         }
1517
1518         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1519                 ArgInfo *ainfo = &cinfo->args [i];
1520
1521                 ins = cfg->args [i];
1522
1523                 switch (ainfo->storage) {
1524                 case ArgInIReg:
1525                 case ArgInFloatSSEReg:
1526                 case ArgInDoubleSSEReg:
1527                         ins->opcode = OP_REGVAR;
1528                         ins->inst_c0 = ainfo->reg;
1529                         break;
1530                 case ArgOnStack:
1531                         ins->opcode = OP_REGOFFSET;
1532                         ins->inst_basereg = -1;
1533                         ins->inst_offset = -1;
1534                         break;
1535                 case ArgValuetypeInReg:
1536                         /* Dummy */
1537                         ins->opcode = OP_NOP;
1538                         break;
1539                 default:
1540                         g_assert_not_reached ();
1541                 }
1542         }
1543 }
1544
1545 void
1546 mono_arch_allocate_vars (MonoCompile *cfg)
1547 {
1548         MonoType *sig_ret;
1549         MonoMethodSignature *sig;
1550         MonoInst *ins;
1551         int i, offset;
1552         guint32 locals_stack_size, locals_stack_align;
1553         gint32 *offsets;
1554         CallInfo *cinfo;
1555
1556         sig = mono_method_signature (cfg->method);
1557
1558         cinfo = (CallInfo *)cfg->arch.cinfo;
1559         sig_ret = mini_get_underlying_type (sig->ret);
1560
1561         mono_arch_compute_omit_fp (cfg);
1562
1563         /*
1564          * We use the ABI calling conventions for managed code as well.
1565          * Exception: valuetypes are only sometimes passed or returned in registers.
1566          */
1567
1568         /*
1569          * The stack looks like this:
1570          * <incoming arguments passed on the stack>
1571          * <return value>
1572          * <lmf/caller saved registers>
1573          * <locals>
1574          * <spill area>
1575          * <localloc area>  -> grows dynamically
1576          * <params area>
1577          */
1578
1579         if (cfg->arch.omit_fp) {
1580                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1581                 cfg->frame_reg = AMD64_RSP;
1582                 offset = 0;
1583         } else {
1584                 /* Locals are allocated backwards from %fp */
1585                 cfg->frame_reg = AMD64_RBP;
1586                 offset = 0;
1587         }
1588
1589         cfg->arch.saved_iregs = cfg->used_int_regs;
1590         if (cfg->method->save_lmf) {
1591                 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1592                 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1593                 cfg->arch.saved_iregs |= iregs_to_save;
1594         }
1595
1596         if (cfg->arch.omit_fp)
1597                 cfg->arch.reg_save_area_offset = offset;
1598         /* Reserve space for callee saved registers */
1599         for (i = 0; i < AMD64_NREG; ++i)
1600                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1601                         offset += sizeof(mgreg_t);
1602                 }
1603         if (!cfg->arch.omit_fp)
1604                 cfg->arch.reg_save_area_offset = -offset;
1605
1606         if (sig_ret->type != MONO_TYPE_VOID) {
1607                 switch (cinfo->ret.storage) {
1608                 case ArgInIReg:
1609                 case ArgInFloatSSEReg:
1610                 case ArgInDoubleSSEReg:
1611                         cfg->ret->opcode = OP_REGVAR;
1612                         cfg->ret->inst_c0 = cinfo->ret.reg;
1613                         cfg->ret->dreg = cinfo->ret.reg;
1614                         break;
1615                 case ArgValuetypeAddrInIReg:
1616                 case ArgGsharedvtVariableInReg:
1617                         /* The register is volatile */
1618                         cfg->vret_addr->opcode = OP_REGOFFSET;
1619                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1620                         if (cfg->arch.omit_fp) {
1621                                 cfg->vret_addr->inst_offset = offset;
1622                                 offset += 8;
1623                         } else {
1624                                 offset += 8;
1625                                 cfg->vret_addr->inst_offset = -offset;
1626                         }
1627                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1628                                 printf ("vret_addr =");
1629                                 mono_print_ins (cfg->vret_addr);
1630                         }
1631                         break;
1632                 case ArgValuetypeInReg:
1633                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1634                         cfg->ret->opcode = OP_REGOFFSET;
1635                         cfg->ret->inst_basereg = cfg->frame_reg;
1636                         if (cfg->arch.omit_fp) {
1637                                 cfg->ret->inst_offset = offset;
1638                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1639                         } else {
1640                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1641                                 cfg->ret->inst_offset = - offset;
1642                         }
1643                         break;
1644                 default:
1645                         g_assert_not_reached ();
1646                 }
1647         }
1648
1649         /* Allocate locals */
1650         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1651         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1652                 char *mname = mono_method_full_name (cfg->method, TRUE);
1653                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1654                 g_free (mname);
1655                 return;
1656         }
1657
1658         if (locals_stack_align) {
1659                 offset += (locals_stack_align - 1);
1660                 offset &= ~(locals_stack_align - 1);
1661         }
1662         if (cfg->arch.omit_fp) {
1663                 cfg->locals_min_stack_offset = offset;
1664                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1665         } else {
1666                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1667                 cfg->locals_max_stack_offset = - offset;
1668         }
1669
1670         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1671                 if (offsets [i] != -1) {
1672                         MonoInst *ins = cfg->varinfo [i];
1673                         ins->opcode = OP_REGOFFSET;
1674                         ins->inst_basereg = cfg->frame_reg;
1675                         if (cfg->arch.omit_fp)
1676                                 ins->inst_offset = (offset + offsets [i]);
1677                         else
1678                                 ins->inst_offset = - (offset + offsets [i]);
1679                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1680                 }
1681         }
1682         offset += locals_stack_size;
1683
1684         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1685                 g_assert (!cfg->arch.omit_fp);
1686                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1687                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1688         }
1689
1690         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1691                 ins = cfg->args [i];
1692                 if (ins->opcode != OP_REGVAR) {
1693                         ArgInfo *ainfo = &cinfo->args [i];
1694                         gboolean inreg = TRUE;
1695
1696                         /* FIXME: Allocate volatile arguments to registers */
1697                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1698                                 inreg = FALSE;
1699
1700                         /*
1701                          * Under AMD64, all registers used to pass arguments to functions
1702                          * are volatile across calls.
1703                          * FIXME: Optimize this.
1704                          */
1705                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1706                                 inreg = FALSE;
1707
1708                         ins->opcode = OP_REGOFFSET;
1709
1710                         switch (ainfo->storage) {
1711                         case ArgInIReg:
1712                         case ArgInFloatSSEReg:
1713                         case ArgInDoubleSSEReg:
1714                         case ArgGSharedVtInReg:
1715                                 if (inreg) {
1716                                         ins->opcode = OP_REGVAR;
1717                                         ins->dreg = ainfo->reg;
1718                                 }
1719                                 break;
1720                         case ArgOnStack:
1721                         case ArgGSharedVtOnStack:
1722                                 g_assert (!cfg->arch.omit_fp);
1723                                 ins->opcode = OP_REGOFFSET;
1724                                 ins->inst_basereg = cfg->frame_reg;
1725                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1726                                 break;
1727                         case ArgValuetypeInReg:
1728                                 break;
1729                         case ArgValuetypeAddrInIReg:
1730                         case ArgValuetypeAddrOnStack: {
1731                                 MonoInst *indir;
1732                                 g_assert (!cfg->arch.omit_fp);
1733                                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1734                                 MONO_INST_NEW (cfg, indir, 0);
1735
1736                                 indir->opcode = OP_REGOFFSET;
1737                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1738                                         indir->inst_basereg = cfg->frame_reg;
1739                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1740                                         offset += (sizeof (gpointer));
1741                                         indir->inst_offset = - offset;
1742                                 }
1743                                 else {
1744                                         indir->inst_basereg = cfg->frame_reg;
1745                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1746                                 }
1747
1748                                 ins->opcode = OP_VTARG_ADDR;
1749                                 ins->inst_left = indir;
1750
1751                                 break;
1752                         }
1753                         default:
1754                                 NOT_IMPLEMENTED;
1755                         }
1756
1757                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1758                                 ins->opcode = OP_REGOFFSET;
1759                                 ins->inst_basereg = cfg->frame_reg;
1760                                 /* These arguments are saved to the stack in the prolog */
1761                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1762                                 if (cfg->arch.omit_fp) {
1763                                         ins->inst_offset = offset;
1764                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1765                                         // Arguments are yet supported by the stack map creation code
1766                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1767                                 } else {
1768                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1769                                         ins->inst_offset = - offset;
1770                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1771                                 }
1772                         }
1773                 }
1774         }
1775
1776         cfg->stack_offset = offset;
1777 }
1778
1779 void
1780 mono_arch_create_vars (MonoCompile *cfg)
1781 {
1782         MonoMethodSignature *sig;
1783         CallInfo *cinfo;
1784         MonoType *sig_ret;
1785
1786         sig = mono_method_signature (cfg->method);
1787
1788         if (!cfg->arch.cinfo)
1789                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1790         cinfo = (CallInfo *)cfg->arch.cinfo;
1791
1792         if (cinfo->ret.storage == ArgValuetypeInReg)
1793                 cfg->ret_var_is_local = TRUE;
1794
1795         sig_ret = mini_get_underlying_type (sig->ret);
1796         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1797                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1798                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1799                         printf ("vret_addr = ");
1800                         mono_print_ins (cfg->vret_addr);
1801                 }
1802         }
1803
1804         if (cfg->gen_sdb_seq_points) {
1805                 MonoInst *ins;
1806
1807                 if (cfg->compile_aot) {
1808                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1809                         ins->flags |= MONO_INST_VOLATILE;
1810                         cfg->arch.seq_point_info_var = ins;
1811                 }
1812                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1813                 ins->flags |= MONO_INST_VOLATILE;
1814                 cfg->arch.ss_tramp_var = ins;
1815
1816                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1817                 ins->flags |= MONO_INST_VOLATILE;
1818                 cfg->arch.bp_tramp_var = ins;
1819         }
1820
1821         if (cfg->method->save_lmf)
1822                 cfg->create_lmf_var = TRUE;
1823
1824         if (cfg->method->save_lmf) {
1825                 cfg->lmf_ir = TRUE;
1826 #if !defined(TARGET_WIN32)
1827                 if (!optimize_for_xen)
1828                         cfg->lmf_ir_mono_lmf = TRUE;
1829 #endif
1830         }
1831 }
1832
1833 static void
1834 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1835 {
1836         MonoInst *ins;
1837
1838         switch (storage) {
1839         case ArgInIReg:
1840                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1841                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1842                 ins->sreg1 = tree->dreg;
1843                 MONO_ADD_INS (cfg->cbb, ins);
1844                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1845                 break;
1846         case ArgInFloatSSEReg:
1847                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1848                 ins->dreg = mono_alloc_freg (cfg);
1849                 ins->sreg1 = tree->dreg;
1850                 MONO_ADD_INS (cfg->cbb, ins);
1851
1852                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1853                 break;
1854         case ArgInDoubleSSEReg:
1855                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1856                 ins->dreg = mono_alloc_freg (cfg);
1857                 ins->sreg1 = tree->dreg;
1858                 MONO_ADD_INS (cfg->cbb, ins);
1859
1860                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1861
1862                 break;
1863         default:
1864                 g_assert_not_reached ();
1865         }
1866 }
1867
1868 static int
1869 arg_storage_to_load_membase (ArgStorage storage)
1870 {
1871         switch (storage) {
1872         case ArgInIReg:
1873 #if defined(__mono_ilp32__)
1874                 return OP_LOADI8_MEMBASE;
1875 #else
1876                 return OP_LOAD_MEMBASE;
1877 #endif
1878         case ArgInDoubleSSEReg:
1879                 return OP_LOADR8_MEMBASE;
1880         case ArgInFloatSSEReg:
1881                 return OP_LOADR4_MEMBASE;
1882         default:
1883                 g_assert_not_reached ();
1884         }
1885
1886         return -1;
1887 }
1888
1889 static void
1890 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1891 {
1892         MonoMethodSignature *tmp_sig;
1893         int sig_reg;
1894
1895         if (call->tail_call)
1896                 NOT_IMPLEMENTED;
1897
1898         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1899
1900         /*
1901          * mono_ArgIterator_Setup assumes the signature cookie is
1902          * passed first and all the arguments which were before it are
1903          * passed on the stack after the signature. So compensate by
1904          * passing a different signature.
1905          */
1906         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1907         tmp_sig->param_count -= call->signature->sentinelpos;
1908         tmp_sig->sentinelpos = 0;
1909         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1910
1911         sig_reg = mono_alloc_ireg (cfg);
1912         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1913
1914         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1915 }
1916
1917 #ifdef ENABLE_LLVM
1918 static inline LLVMArgStorage
1919 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1920 {
1921         switch (storage) {
1922         case ArgInIReg:
1923                 return LLVMArgInIReg;
1924         case ArgNone:
1925                 return LLVMArgNone;
1926         case ArgGSharedVtInReg:
1927         case ArgGSharedVtOnStack:
1928                 return LLVMArgGSharedVt;
1929         default:
1930                 g_assert_not_reached ();
1931                 return LLVMArgNone;
1932         }
1933 }
1934
1935 LLVMCallInfo*
1936 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1937 {
1938         int i, n;
1939         CallInfo *cinfo;
1940         ArgInfo *ainfo;
1941         int j;
1942         LLVMCallInfo *linfo;
1943         MonoType *t, *sig_ret;
1944
1945         n = sig->param_count + sig->hasthis;
1946         sig_ret = mini_get_underlying_type (sig->ret);
1947
1948         cinfo = get_call_info (cfg->mempool, sig);
1949
1950         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1951
1952         /*
1953          * LLVM always uses the native ABI while we use our own ABI, the
1954          * only difference is the handling of vtypes:
1955          * - we only pass/receive them in registers in some cases, and only
1956          *   in 1 or 2 integer registers.
1957          */
1958         switch (cinfo->ret.storage) {
1959         case ArgNone:
1960                 linfo->ret.storage = LLVMArgNone;
1961                 break;
1962         case ArgInIReg:
1963         case ArgInFloatSSEReg:
1964         case ArgInDoubleSSEReg:
1965                 linfo->ret.storage = LLVMArgNormal;
1966                 break;
1967         case ArgValuetypeInReg: {
1968                 ainfo = &cinfo->ret;
1969
1970                 if (sig->pinvoke &&
1971                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1972                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1973                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1974                         cfg->disable_llvm = TRUE;
1975                         return linfo;
1976                 }
1977
1978                 linfo->ret.storage = LLVMArgVtypeInReg;
1979                 for (j = 0; j < 2; ++j)
1980                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1981                 break;
1982         }
1983         case ArgValuetypeAddrInIReg:
1984         case ArgGsharedvtVariableInReg:
1985                 /* Vtype returned using a hidden argument */
1986                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1987                 linfo->vret_arg_index = cinfo->vret_arg_index;
1988                 break;
1989         default:
1990                 g_assert_not_reached ();
1991                 break;
1992         }
1993
1994         for (i = 0; i < n; ++i) {
1995                 ainfo = cinfo->args + i;
1996
1997                 if (i >= sig->hasthis)
1998                         t = sig->params [i - sig->hasthis];
1999                 else
2000                         t = &mono_defaults.int_class->byval_arg;
2001                 t = mini_type_get_underlying_type (t);
2002
2003                 linfo->args [i].storage = LLVMArgNone;
2004
2005                 switch (ainfo->storage) {
2006                 case ArgInIReg:
2007                         linfo->args [i].storage = LLVMArgNormal;
2008                         break;
2009                 case ArgInDoubleSSEReg:
2010                 case ArgInFloatSSEReg:
2011                         linfo->args [i].storage = LLVMArgNormal;
2012                         break;
2013                 case ArgOnStack:
2014                         if (MONO_TYPE_ISSTRUCT (t))
2015                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2016                         else
2017                                 linfo->args [i].storage = LLVMArgNormal;
2018                         break;
2019                 case ArgValuetypeInReg:
2020                         if (sig->pinvoke &&
2021                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2022                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2023                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2024                                 cfg->disable_llvm = TRUE;
2025                                 return linfo;
2026                         }
2027
2028                         linfo->args [i].storage = LLVMArgVtypeInReg;
2029                         for (j = 0; j < 2; ++j)
2030                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2031                         break;
2032                 case ArgGSharedVtInReg:
2033                 case ArgGSharedVtOnStack:
2034                         linfo->args [i].storage = LLVMArgGSharedVt;
2035                         break;
2036                 default:
2037                         cfg->exception_message = g_strdup ("ainfo->storage");
2038                         cfg->disable_llvm = TRUE;
2039                         break;
2040                 }
2041         }
2042
2043         return linfo;
2044 }
2045 #endif
2046
2047 void
2048 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2049 {
2050         MonoInst *arg, *in;
2051         MonoMethodSignature *sig;
2052         MonoType *sig_ret;
2053         int i, n;
2054         CallInfo *cinfo;
2055         ArgInfo *ainfo;
2056
2057         sig = call->signature;
2058         n = sig->param_count + sig->hasthis;
2059
2060         cinfo = get_call_info (cfg->mempool, sig);
2061
2062         sig_ret = sig->ret;
2063
2064         if (COMPILE_LLVM (cfg)) {
2065                 /* We shouldn't be called in the llvm case */
2066                 cfg->disable_llvm = TRUE;
2067                 return;
2068         }
2069
2070         /*
2071          * Emit all arguments which are passed on the stack to prevent register
2072          * allocation problems.
2073          */
2074         for (i = 0; i < n; ++i) {
2075                 MonoType *t;
2076                 ainfo = cinfo->args + i;
2077
2078                 in = call->args [i];
2079
2080                 if (sig->hasthis && i == 0)
2081                         t = &mono_defaults.object_class->byval_arg;
2082                 else
2083                         t = sig->params [i - sig->hasthis];
2084
2085                 t = mini_get_underlying_type (t);
2086                 //XXX what about ArgGSharedVtOnStack here?
2087                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2088                         if (!t->byref) {
2089                                 if (t->type == MONO_TYPE_R4)
2090                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2091                                 else if (t->type == MONO_TYPE_R8)
2092                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2093                                 else
2094                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2095                         } else {
2096                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2097                         }
2098                         if (cfg->compute_gc_maps) {
2099                                 MonoInst *def;
2100
2101                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2102                         }
2103                 }
2104         }
2105
2106         /*
2107          * Emit all parameters passed in registers in non-reverse order for better readability
2108          * and to help the optimization in emit_prolog ().
2109          */
2110         for (i = 0; i < n; ++i) {
2111                 ainfo = cinfo->args + i;
2112
2113                 in = call->args [i];
2114
2115                 if (ainfo->storage == ArgInIReg)
2116                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2117         }
2118
2119         for (i = n - 1; i >= 0; --i) {
2120                 MonoType *t;
2121
2122                 ainfo = cinfo->args + i;
2123
2124                 in = call->args [i];
2125
2126                 if (sig->hasthis && i == 0)
2127                         t = &mono_defaults.object_class->byval_arg;
2128                 else
2129                         t = sig->params [i - sig->hasthis];
2130                 t = mini_get_underlying_type (t);
2131
2132                 switch (ainfo->storage) {
2133                 case ArgInIReg:
2134                         /* Already done */
2135                         break;
2136                 case ArgInFloatSSEReg:
2137                 case ArgInDoubleSSEReg:
2138                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2139                         break;
2140                 case ArgOnStack:
2141                 case ArgValuetypeInReg:
2142                 case ArgValuetypeAddrInIReg:
2143                 case ArgValuetypeAddrOnStack:
2144                 case ArgGSharedVtInReg:
2145                 case ArgGSharedVtOnStack: {
2146                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2147                                 /* Already emitted above */
2148                                 break;
2149                         //FIXME what about ArgGSharedVtOnStack ?
2150                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2151                                 MonoInst *call_inst = (MonoInst*)call;
2152                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2153                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2154                                 break;
2155                         }
2156
2157                         guint32 align;
2158                         guint32 size;
2159
2160                         if (sig->pinvoke)
2161                                 size = mono_type_native_stack_size (t, &align);
2162                         else {
2163                                 /*
2164                                  * Other backends use mono_type_stack_size (), but that
2165                                  * aligns the size to 8, which is larger than the size of
2166                                  * the source, leading to reads of invalid memory if the
2167                                  * source is at the end of address space.
2168                                  */
2169                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2170                         }
2171
2172                         if (size >= 10000) {
2173                                 /* Avoid asserts in emit_memcpy () */
2174                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2175                                 /* Continue normally */
2176                         }
2177
2178                         if (size > 0 || ainfo->pass_empty_struct) {
2179                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2180                                 arg->sreg1 = in->dreg;
2181                                 arg->klass = mono_class_from_mono_type (t);
2182                                 arg->backend.size = size;
2183                                 arg->inst_p0 = call;
2184                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2185                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2186
2187                                 MONO_ADD_INS (cfg->cbb, arg);
2188                         }
2189                         break;
2190                 }
2191                 default:
2192                         g_assert_not_reached ();
2193                 }
2194
2195                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2196                         /* Emit the signature cookie just before the implicit arguments */
2197                         emit_sig_cookie (cfg, call, cinfo);
2198         }
2199
2200         /* Handle the case where there are no implicit arguments */
2201         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2202                 emit_sig_cookie (cfg, call, cinfo);
2203
2204         switch (cinfo->ret.storage) {
2205         case ArgValuetypeInReg:
2206                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2207                         /*
2208                          * Tell the JIT to use a more efficient calling convention: call using
2209                          * OP_CALL, compute the result location after the call, and save the
2210                          * result there.
2211                          */
2212                         call->vret_in_reg = TRUE;
2213                         /*
2214                          * Nullify the instruction computing the vret addr to enable
2215                          * future optimizations.
2216                          */
2217                         if (call->vret_var)
2218                                 NULLIFY_INS (call->vret_var);
2219                 } else {
2220                         if (call->tail_call)
2221                                 NOT_IMPLEMENTED;
2222                         /*
2223                          * The valuetype is in RAX:RDX after the call, need to be copied to
2224                          * the stack. Push the address here, so the call instruction can
2225                          * access it.
2226                          */
2227                         if (!cfg->arch.vret_addr_loc) {
2228                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2229                                 /* Prevent it from being register allocated or optimized away */
2230                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2231                         }
2232
2233                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2234                 }
2235                 break;
2236         case ArgValuetypeAddrInIReg:
2237         case ArgGsharedvtVariableInReg: {
2238                 MonoInst *vtarg;
2239                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2240                 vtarg->sreg1 = call->vret_var->dreg;
2241                 vtarg->dreg = mono_alloc_preg (cfg);
2242                 MONO_ADD_INS (cfg->cbb, vtarg);
2243
2244                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2245                 break;
2246         }
2247         default:
2248                 break;
2249         }
2250
2251         if (cfg->method->save_lmf) {
2252                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2253                 MONO_ADD_INS (cfg->cbb, arg);
2254         }
2255
2256         call->stack_usage = cinfo->stack_usage;
2257 }
2258
2259 void
2260 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2261 {
2262         MonoInst *arg;
2263         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2264         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2265         int size = ins->backend.size;
2266
2267         switch (ainfo->storage) {
2268         case ArgValuetypeInReg: {
2269                 MonoInst *load;
2270                 int part;
2271
2272                 for (part = 0; part < 2; ++part) {
2273                         if (ainfo->pair_storage [part] == ArgNone)
2274                                 continue;
2275
2276                         if (ainfo->pass_empty_struct) {
2277                                 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2278                                 NEW_ICONST (cfg, load, 0);
2279                         }
2280                         else {
2281                                 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2282                                 load->inst_basereg = src->dreg;
2283                                 load->inst_offset = part * sizeof(mgreg_t);
2284
2285                                 switch (ainfo->pair_storage [part]) {
2286                                 case ArgInIReg:
2287                                         load->dreg = mono_alloc_ireg (cfg);
2288                                         break;
2289                                 case ArgInDoubleSSEReg:
2290                                 case ArgInFloatSSEReg:
2291                                         load->dreg = mono_alloc_freg (cfg);
2292                                         break;
2293                                 default:
2294                                         g_assert_not_reached ();
2295                                 }
2296                         }
2297
2298                         MONO_ADD_INS (cfg->cbb, load);
2299
2300                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2301                 }
2302                 break;
2303         }
2304         case ArgValuetypeAddrInIReg:
2305         case ArgValuetypeAddrOnStack: {
2306                 MonoInst *vtaddr, *load;
2307
2308                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2309
2310                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2311
2312                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2313                 cfg->has_indirection = TRUE;
2314                 load->inst_p0 = vtaddr;
2315                 vtaddr->flags |= MONO_INST_INDIRECT;
2316                 load->type = STACK_MP;
2317                 load->klass = vtaddr->klass;
2318                 load->dreg = mono_alloc_ireg (cfg);
2319                 MONO_ADD_INS (cfg->cbb, load);
2320                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2321
2322                 if (ainfo->pair_storage [0] == ArgInIReg) {
2323                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2324                         arg->dreg = mono_alloc_ireg (cfg);
2325                         arg->sreg1 = load->dreg;
2326                         arg->inst_imm = 0;
2327                         MONO_ADD_INS (cfg->cbb, arg);
2328                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2329                 } else {
2330                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2331                 }
2332                 break;
2333         }
2334         case ArgGSharedVtInReg:
2335                 /* Pass by addr */
2336                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2337                 break;
2338         case ArgGSharedVtOnStack:
2339                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2340                 break;
2341         default:
2342                 if (size == 8) {
2343                         int dreg = mono_alloc_ireg (cfg);
2344
2345                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2346                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2347                 } else if (size <= 40) {
2348                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2349                 } else {
2350                         // FIXME: Code growth
2351                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2352                 }
2353
2354                 if (cfg->compute_gc_maps) {
2355                         MonoInst *def;
2356                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2357                 }
2358         }
2359 }
2360
2361 void
2362 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2363 {
2364         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2365
2366         if (ret->type == MONO_TYPE_R4) {
2367                 if (COMPILE_LLVM (cfg))
2368                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2369                 else
2370                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2371                 return;
2372         } else if (ret->type == MONO_TYPE_R8) {
2373                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2374                 return;
2375         }
2376
2377         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2378 }
2379
2380 #endif /* DISABLE_JIT */
2381
2382 #define EMIT_COND_BRANCH(ins,cond,sign) \
2383         if (ins->inst_true_bb->native_offset) { \
2384                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2385         } else { \
2386                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2387                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2388             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2389                         x86_branch8 (code, cond, 0, sign); \
2390                 else \
2391                         x86_branch32 (code, cond, 0, sign); \
2392 }
2393
2394 typedef struct {
2395         MonoMethodSignature *sig;
2396         CallInfo *cinfo;
2397 } ArchDynCallInfo;
2398
2399 static gboolean
2400 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2401 {
2402         int i;
2403
2404         switch (cinfo->ret.storage) {
2405         case ArgNone:
2406         case ArgInIReg:
2407         case ArgInFloatSSEReg:
2408         case ArgInDoubleSSEReg:
2409         case ArgValuetypeAddrInIReg:
2410         case ArgValuetypeInReg:
2411                 break;
2412         default:
2413                 return FALSE;
2414         }
2415
2416         for (i = 0; i < cinfo->nargs; ++i) {
2417                 ArgInfo *ainfo = &cinfo->args [i];
2418                 switch (ainfo->storage) {
2419                 case ArgInIReg:
2420                 case ArgInFloatSSEReg:
2421                 case ArgInDoubleSSEReg:
2422                 case ArgValuetypeInReg:
2423                         break;
2424                 case ArgOnStack:
2425                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2426                                 return FALSE;
2427                         break;
2428                 default:
2429                         return FALSE;
2430                 }
2431         }
2432
2433         return TRUE;
2434 }
2435
2436 /*
2437  * mono_arch_dyn_call_prepare:
2438  *
2439  *   Return a pointer to an arch-specific structure which contains information
2440  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2441  * supported for SIG.
2442  * This function is equivalent to ffi_prep_cif in libffi.
2443  */
2444 MonoDynCallInfo*
2445 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2446 {
2447         ArchDynCallInfo *info;
2448         CallInfo *cinfo;
2449
2450         cinfo = get_call_info (NULL, sig);
2451
2452         if (!dyn_call_supported (sig, cinfo)) {
2453                 g_free (cinfo);
2454                 return NULL;
2455         }
2456
2457         info = g_new0 (ArchDynCallInfo, 1);
2458         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2459         info->sig = sig;
2460         info->cinfo = cinfo;
2461
2462         return (MonoDynCallInfo*)info;
2463 }
2464
2465 /*
2466  * mono_arch_dyn_call_free:
2467  *
2468  *   Free a MonoDynCallInfo structure.
2469  */
2470 void
2471 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2472 {
2473         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2474
2475         g_free (ainfo->cinfo);
2476         g_free (ainfo);
2477 }
2478
2479 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2480 #define GREG_TO_PTR(greg) (gpointer)(greg)
2481
2482 /*
2483  * mono_arch_get_start_dyn_call:
2484  *
2485  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2486  * store the result into BUF.
2487  * ARGS should be an array of pointers pointing to the arguments.
2488  * RET should point to a memory buffer large enought to hold the result of the
2489  * call.
2490  * This function should be as fast as possible, any work which does not depend
2491  * on the actual values of the arguments should be done in
2492  * mono_arch_dyn_call_prepare ().
2493  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2494  * libffi.
2495  */
2496 void
2497 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2498 {
2499         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2500         DynCallArgs *p = (DynCallArgs*)buf;
2501         int arg_index, greg, freg, i, pindex;
2502         MonoMethodSignature *sig = dinfo->sig;
2503         int buffer_offset = 0;
2504         static int param_reg_to_index [16];
2505         static gboolean param_reg_to_index_inited;
2506
2507         if (!param_reg_to_index_inited) {
2508                 for (i = 0; i < PARAM_REGS; ++i)
2509                         param_reg_to_index [param_regs [i]] = i;
2510                 mono_memory_barrier ();
2511                 param_reg_to_index_inited = 1;
2512         }
2513
2514         g_assert (buf_len >= sizeof (DynCallArgs));
2515
2516         p->res = 0;
2517         p->ret = ret;
2518
2519         arg_index = 0;
2520         greg = 0;
2521         freg = 0;
2522         pindex = 0;
2523
2524         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2525                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2526                 if (!sig->hasthis)
2527                         pindex = 1;
2528         }
2529
2530         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2531                 p->regs [greg ++] = PTR_TO_GREG(ret);
2532
2533         for (; pindex < sig->param_count; pindex++) {
2534                 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2535                 gpointer *arg = args [arg_index ++];
2536                 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2537                 int slot;
2538
2539                 if (ainfo->storage == ArgOnStack) {
2540                         slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2541                 } else {
2542                         slot = param_reg_to_index [ainfo->reg];
2543                 }
2544
2545                 if (t->byref) {
2546                         p->regs [slot] = PTR_TO_GREG(*(arg));
2547                         greg ++;
2548                         continue;
2549                 }
2550
2551                 switch (t->type) {
2552                 case MONO_TYPE_STRING:
2553                 case MONO_TYPE_CLASS:
2554                 case MONO_TYPE_ARRAY:
2555                 case MONO_TYPE_SZARRAY:
2556                 case MONO_TYPE_OBJECT:
2557                 case MONO_TYPE_PTR:
2558                 case MONO_TYPE_I:
2559                 case MONO_TYPE_U:
2560 #if !defined(__mono_ilp32__)
2561                 case MONO_TYPE_I8:
2562                 case MONO_TYPE_U8:
2563 #endif
2564                         p->regs [slot] = PTR_TO_GREG(*(arg));
2565                         break;
2566 #if defined(__mono_ilp32__)
2567                 case MONO_TYPE_I8:
2568                 case MONO_TYPE_U8:
2569                         p->regs [slot] = *(guint64*)(arg);
2570                         break;
2571 #endif
2572                 case MONO_TYPE_U1:
2573                         p->regs [slot] = *(guint8*)(arg);
2574                         break;
2575                 case MONO_TYPE_I1:
2576                         p->regs [slot] = *(gint8*)(arg);
2577                         break;
2578                 case MONO_TYPE_I2:
2579                         p->regs [slot] = *(gint16*)(arg);
2580                         break;
2581                 case MONO_TYPE_U2:
2582                         p->regs [slot] = *(guint16*)(arg);
2583                         break;
2584                 case MONO_TYPE_I4:
2585                         p->regs [slot] = *(gint32*)(arg);
2586                         break;
2587                 case MONO_TYPE_U4:
2588                         p->regs [slot] = *(guint32*)(arg);
2589                         break;
2590                 case MONO_TYPE_R4: {
2591                         double d;
2592
2593                         *(float*)&d = *(float*)(arg);
2594                         p->has_fp = 1;
2595                         p->fregs [freg ++] = d;
2596                         break;
2597                 }
2598                 case MONO_TYPE_R8:
2599                         p->has_fp = 1;
2600                         p->fregs [freg ++] = *(double*)(arg);
2601                         break;
2602                 case MONO_TYPE_GENERICINST:
2603                     if (MONO_TYPE_IS_REFERENCE (t)) {
2604                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2605                                 break;
2606                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2607                                         MonoClass *klass = mono_class_from_mono_type (t);
2608                                         guint8 *nullable_buf;
2609                                         int size;
2610
2611                                         size = mono_class_value_size (klass, NULL);
2612                                         nullable_buf = p->buffer + buffer_offset;
2613                                         buffer_offset += size;
2614                                         g_assert (buffer_offset <= 256);
2615
2616                                         /* The argument pointed to by arg is either a boxed vtype or null */
2617                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2618
2619                                         arg = (gpointer*)nullable_buf;
2620                                         /* Fall though */
2621
2622                         } else {
2623                                 /* Fall through */
2624                         }
2625                 case MONO_TYPE_VALUETYPE: {
2626                         switch (ainfo->storage) {
2627                         case ArgValuetypeInReg:
2628                                 for (i = 0; i < 2; ++i) {
2629                                         switch (ainfo->pair_storage [i]) {
2630                                         case ArgNone:
2631                                                 break;
2632                                         case ArgInIReg:
2633                                                 slot = param_reg_to_index [ainfo->pair_regs [i]];
2634                                                 p->regs [slot] = ((mgreg_t*)(arg))[i];
2635                                                 break;
2636                                         case ArgInDoubleSSEReg:
2637                                                 p->has_fp = 1;
2638                                                 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2639                                                 break;
2640                                         default:
2641                                                 g_assert_not_reached ();
2642                                                 break;
2643                                         }
2644                                 }
2645                                 break;
2646                         case ArgOnStack:
2647                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2648                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2649                                 break;
2650                         default:
2651                                 g_assert_not_reached ();
2652                                 break;
2653                         }
2654                         break;
2655                 }
2656                 default:
2657                         g_assert_not_reached ();
2658                 }
2659         }
2660 }
2661
2662 /*
2663  * mono_arch_finish_dyn_call:
2664  *
2665  *   Store the result of a dyn call into the return value buffer passed to
2666  * start_dyn_call ().
2667  * This function should be as fast as possible, any work which does not depend
2668  * on the actual values of the arguments should be done in
2669  * mono_arch_dyn_call_prepare ().
2670  */
2671 void
2672 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2673 {
2674         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2675         MonoMethodSignature *sig = dinfo->sig;
2676         DynCallArgs *dargs = (DynCallArgs*)buf;
2677         guint8 *ret = dargs->ret;
2678         mgreg_t res = dargs->res;
2679         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2680         int i;
2681
2682         switch (sig_ret->type) {
2683         case MONO_TYPE_VOID:
2684                 *(gpointer*)ret = NULL;
2685                 break;
2686         case MONO_TYPE_STRING:
2687         case MONO_TYPE_CLASS:
2688         case MONO_TYPE_ARRAY:
2689         case MONO_TYPE_SZARRAY:
2690         case MONO_TYPE_OBJECT:
2691         case MONO_TYPE_I:
2692         case MONO_TYPE_U:
2693         case MONO_TYPE_PTR:
2694                 *(gpointer*)ret = GREG_TO_PTR(res);
2695                 break;
2696         case MONO_TYPE_I1:
2697                 *(gint8*)ret = res;
2698                 break;
2699         case MONO_TYPE_U1:
2700                 *(guint8*)ret = res;
2701                 break;
2702         case MONO_TYPE_I2:
2703                 *(gint16*)ret = res;
2704                 break;
2705         case MONO_TYPE_U2:
2706                 *(guint16*)ret = res;
2707                 break;
2708         case MONO_TYPE_I4:
2709                 *(gint32*)ret = res;
2710                 break;
2711         case MONO_TYPE_U4:
2712                 *(guint32*)ret = res;
2713                 break;
2714         case MONO_TYPE_I8:
2715                 *(gint64*)ret = res;
2716                 break;
2717         case MONO_TYPE_U8:
2718                 *(guint64*)ret = res;
2719                 break;
2720         case MONO_TYPE_R4:
2721                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2722                 break;
2723         case MONO_TYPE_R8:
2724                 *(double*)ret = dargs->fregs [0];
2725                 break;
2726         case MONO_TYPE_GENERICINST:
2727                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2728                         *(gpointer*)ret = GREG_TO_PTR(res);
2729                         break;
2730                 } else {
2731                         /* Fall through */
2732                 }
2733         case MONO_TYPE_VALUETYPE:
2734                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2735                         /* Nothing to do */
2736                 } else {
2737                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2738
2739                         g_assert (ainfo->storage == ArgValuetypeInReg);
2740
2741                         for (i = 0; i < 2; ++i) {
2742                                 switch (ainfo->pair_storage [0]) {
2743                                 case ArgInIReg:
2744                                         ((mgreg_t*)ret)[i] = res;
2745                                         break;
2746                                 case ArgInDoubleSSEReg:
2747                                         ((double*)ret)[i] = dargs->fregs [i];
2748                                         break;
2749                                 case ArgNone:
2750                                         break;
2751                                 default:
2752                                         g_assert_not_reached ();
2753                                         break;
2754                                 }
2755                         }
2756                 }
2757                 break;
2758         default:
2759                 g_assert_not_reached ();
2760         }
2761 }
2762
2763 /* emit an exception if condition is fail */
2764 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2765         do {                                                        \
2766                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2767                 if (tins == NULL) {                                                                             \
2768                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2769                                         MONO_PATCH_INFO_EXC, exc_name);  \
2770                         x86_branch32 (code, cond, 0, signed);               \
2771                 } else {        \
2772                         EMIT_COND_BRANCH (tins, cond, signed);  \
2773                 }                       \
2774         } while (0);
2775
2776 #define EMIT_FPCOMPARE(code) do { \
2777         amd64_fcompp (code); \
2778         amd64_fnstsw (code); \
2779 } while (0);
2780
2781 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2782     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2783         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2784         amd64_ ##op (code); \
2785         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2786         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2787 } while (0);
2788
2789 static guint8*
2790 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2791 {
2792         gboolean no_patch = FALSE;
2793
2794         /*
2795          * FIXME: Add support for thunks
2796          */
2797         {
2798                 gboolean near_call = FALSE;
2799
2800                 /*
2801                  * Indirect calls are expensive so try to make a near call if possible.
2802                  * The caller memory is allocated by the code manager so it is
2803                  * guaranteed to be at a 32 bit offset.
2804                  */
2805
2806                 if (patch_type != MONO_PATCH_INFO_ABS) {
2807                         /* The target is in memory allocated using the code manager */
2808                         near_call = TRUE;
2809
2810                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2811                                 if (((MonoMethod*)data)->klass->image->aot_module)
2812                                         /* The callee might be an AOT method */
2813                                         near_call = FALSE;
2814                                 if (((MonoMethod*)data)->dynamic)
2815                                         /* The target is in malloc-ed memory */
2816                                         near_call = FALSE;
2817                         }
2818
2819                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2820                                 /*
2821                                  * The call might go directly to a native function without
2822                                  * the wrapper.
2823                                  */
2824                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2825                                 if (mi) {
2826                                         gconstpointer target = mono_icall_get_wrapper (mi);
2827                                         if ((((guint64)target) >> 32) != 0)
2828                                                 near_call = FALSE;
2829                                 }
2830                         }
2831                 }
2832                 else {
2833                         MonoJumpInfo *jinfo = NULL;
2834
2835                         if (cfg->abs_patches)
2836                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2837                         if (jinfo) {
2838                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2839                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2840                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2841                                                 near_call = TRUE;
2842                                         no_patch = TRUE;
2843                                 } else {
2844                                         /*
2845                                          * This is not really an optimization, but required because the
2846                                          * generic class init trampolines use R11 to pass the vtable.
2847                                          */
2848                                         near_call = TRUE;
2849                                 }
2850                         } else {
2851                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2852                                 if (info) {
2853                                         if (info->func == info->wrapper) {
2854                                                 /* No wrapper */
2855                                                 if ((((guint64)info->func) >> 32) == 0)
2856                                                         near_call = TRUE;
2857                                         }
2858                                         else {
2859                                                 /* See the comment in mono_codegen () */
2860                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2861                                                         near_call = TRUE;
2862                                         }
2863                                 }
2864                                 else if ((((guint64)data) >> 32) == 0) {
2865                                         near_call = TRUE;
2866                                         no_patch = TRUE;
2867                                 }
2868                         }
2869                 }
2870
2871                 if (cfg->method->dynamic)
2872                         /* These methods are allocated using malloc */
2873                         near_call = FALSE;
2874
2875 #ifdef MONO_ARCH_NOMAP32BIT
2876                 near_call = FALSE;
2877 #endif
2878                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2879                 if (optimize_for_xen)
2880                         near_call = FALSE;
2881
2882                 if (cfg->compile_aot) {
2883                         near_call = TRUE;
2884                         no_patch = TRUE;
2885                 }
2886
2887                 if (near_call) {
2888                         /*
2889                          * Align the call displacement to an address divisible by 4 so it does
2890                          * not span cache lines. This is required for code patching to work on SMP
2891                          * systems.
2892                          */
2893                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2894                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2895                                 amd64_padding (code, pad_size);
2896                         }
2897                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2898                         amd64_call_code (code, 0);
2899                 }
2900                 else {
2901                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2902                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2903                         amd64_call_reg (code, GP_SCRATCH_REG);
2904                 }
2905         }
2906
2907         return code;
2908 }
2909
2910 static inline guint8*
2911 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2912 {
2913 #ifdef TARGET_WIN32
2914         if (win64_adjust_stack)
2915                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2916 #endif
2917         code = emit_call_body (cfg, code, patch_type, data);
2918 #ifdef TARGET_WIN32
2919         if (win64_adjust_stack)
2920                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2921 #endif
2922
2923         return code;
2924 }
2925
2926 static inline int
2927 store_membase_imm_to_store_membase_reg (int opcode)
2928 {
2929         switch (opcode) {
2930         case OP_STORE_MEMBASE_IMM:
2931                 return OP_STORE_MEMBASE_REG;
2932         case OP_STOREI4_MEMBASE_IMM:
2933                 return OP_STOREI4_MEMBASE_REG;
2934         case OP_STOREI8_MEMBASE_IMM:
2935                 return OP_STOREI8_MEMBASE_REG;
2936         }
2937
2938         return -1;
2939 }
2940
2941 #ifndef DISABLE_JIT
2942
2943 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2944
2945 /*
2946  * mono_arch_peephole_pass_1:
2947  *
2948  *   Perform peephole opts which should/can be performed before local regalloc
2949  */
2950 void
2951 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2952 {
2953         MonoInst *ins, *n;
2954
2955         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2956                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2957
2958                 switch (ins->opcode) {
2959                 case OP_ADD_IMM:
2960                 case OP_IADD_IMM:
2961                 case OP_LADD_IMM:
2962                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2963                                 /*
2964                                  * X86_LEA is like ADD, but doesn't have the
2965                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2966                                  * its operand to 64 bit.
2967                                  */
2968                                 ins->opcode = OP_X86_LEA_MEMBASE;
2969                                 ins->inst_basereg = ins->sreg1;
2970                         }
2971                         break;
2972                 case OP_LXOR:
2973                 case OP_IXOR:
2974                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2975                                 MonoInst *ins2;
2976
2977                                 /*
2978                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2979                                  * the latter has length 2-3 instead of 6 (reverse constant
2980                                  * propagation). These instruction sequences are very common
2981                                  * in the initlocals bblock.
2982                                  */
2983                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2984                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2985                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2986                                                 ins2->sreg1 = ins->dreg;
2987                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2988                                                 /* Continue */
2989                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2990                                                 NULLIFY_INS (ins2);
2991                                                 /* Continue */
2992                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2993                                                 /* Continue */
2994                                         } else {
2995                                                 break;
2996                                         }
2997                                 }
2998                         }
2999                         break;
3000                 case OP_COMPARE_IMM:
3001                 case OP_LCOMPARE_IMM:
3002                         /* OP_COMPARE_IMM (reg, 0)
3003                          * -->
3004                          * OP_AMD64_TEST_NULL (reg)
3005                          */
3006                         if (!ins->inst_imm)
3007                                 ins->opcode = OP_AMD64_TEST_NULL;
3008                         break;
3009                 case OP_ICOMPARE_IMM:
3010                         if (!ins->inst_imm)
3011                                 ins->opcode = OP_X86_TEST_NULL;
3012                         break;
3013                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3014                         /*
3015                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3016                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3017                          * -->
3018                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3019                          * OP_COMPARE_IMM reg, imm
3020                          *
3021                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3022                          */
3023                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3024                             ins->inst_basereg == last_ins->inst_destbasereg &&
3025                             ins->inst_offset == last_ins->inst_offset) {
3026                                         ins->opcode = OP_ICOMPARE_IMM;
3027                                         ins->sreg1 = last_ins->sreg1;
3028
3029                                         /* check if we can remove cmp reg,0 with test null */
3030                                         if (!ins->inst_imm)
3031                                                 ins->opcode = OP_X86_TEST_NULL;
3032                                 }
3033
3034                         break;
3035                 }
3036
3037                 mono_peephole_ins (bb, ins);
3038         }
3039 }
3040
3041 void
3042 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3043 {
3044         MonoInst *ins, *n;
3045
3046         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3047                 switch (ins->opcode) {
3048                 case OP_ICONST:
3049                 case OP_I8CONST: {
3050                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3051                         /* reg = 0 -> XOR (reg, reg) */
3052                         /* XOR sets cflags on x86, so we cant do it always */
3053                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3054                                 ins->opcode = OP_LXOR;
3055                                 ins->sreg1 = ins->dreg;
3056                                 ins->sreg2 = ins->dreg;
3057                                 /* Fall through */
3058                         } else {
3059                                 break;
3060                         }
3061                 }
3062                 case OP_LXOR:
3063                         /*
3064                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3065                          * 0 result into 64 bits.
3066                          */
3067                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3068                                 ins->opcode = OP_IXOR;
3069                         }
3070                         /* Fall through */
3071                 case OP_IXOR:
3072                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3073                                 MonoInst *ins2;
3074
3075                                 /*
3076                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3077                                  * the latter has length 2-3 instead of 6 (reverse constant
3078                                  * propagation). These instruction sequences are very common
3079                                  * in the initlocals bblock.
3080                                  */
3081                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3082                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3083                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3084                                                 ins2->sreg1 = ins->dreg;
3085                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3086                                                 /* Continue */
3087                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3088                                                 NULLIFY_INS (ins2);
3089                                                 /* Continue */
3090                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3091                                                 /* Continue */
3092                                         } else {
3093                                                 break;
3094                                         }
3095                                 }
3096                         }
3097                         break;
3098                 case OP_IADD_IMM:
3099                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3100                                 ins->opcode = OP_X86_INC_REG;
3101                         break;
3102                 case OP_ISUB_IMM:
3103                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3104                                 ins->opcode = OP_X86_DEC_REG;
3105                         break;
3106                 }
3107
3108                 mono_peephole_ins (bb, ins);
3109         }
3110 }
3111
3112 #define NEW_INS(cfg,ins,dest,op) do {   \
3113                 MONO_INST_NEW ((cfg), (dest), (op)); \
3114         (dest)->cil_code = (ins)->cil_code; \
3115         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3116         } while (0)
3117
3118 /*
3119  * mono_arch_lowering_pass:
3120  *
3121  *  Converts complex opcodes into simpler ones so that each IR instruction
3122  * corresponds to one machine instruction.
3123  */
3124 void
3125 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3126 {
3127         MonoInst *ins, *n, *temp;
3128
3129         /*
3130          * FIXME: Need to add more instructions, but the current machine
3131          * description can't model some parts of the composite instructions like
3132          * cdq.
3133          */
3134         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3135                 switch (ins->opcode) {
3136                 case OP_DIV_IMM:
3137                 case OP_REM_IMM:
3138                 case OP_IDIV_IMM:
3139                 case OP_IDIV_UN_IMM:
3140                 case OP_IREM_UN_IMM:
3141                 case OP_LREM_IMM:
3142                 case OP_IREM_IMM:
3143                         mono_decompose_op_imm (cfg, bb, ins);
3144                         break;
3145                 case OP_COMPARE_IMM:
3146                 case OP_LCOMPARE_IMM:
3147                         if (!amd64_use_imm32 (ins->inst_imm)) {
3148                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3149                                 temp->inst_c0 = ins->inst_imm;
3150                                 temp->dreg = mono_alloc_ireg (cfg);
3151                                 ins->opcode = OP_COMPARE;
3152                                 ins->sreg2 = temp->dreg;
3153                         }
3154                         break;
3155 #ifndef __mono_ilp32__
3156                 case OP_LOAD_MEMBASE:
3157 #endif
3158                 case OP_LOADI8_MEMBASE:
3159                 /*  Don't generate memindex opcodes (to simplify */
3160                 /*  read sandboxing) */
3161                         if (!amd64_use_imm32 (ins->inst_offset)) {
3162                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3163                                 temp->inst_c0 = ins->inst_offset;
3164                                 temp->dreg = mono_alloc_ireg (cfg);
3165                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3166                                 ins->inst_indexreg = temp->dreg;
3167                         }
3168                         break;
3169 #ifndef __mono_ilp32__
3170                 case OP_STORE_MEMBASE_IMM:
3171 #endif
3172                 case OP_STOREI8_MEMBASE_IMM:
3173                         if (!amd64_use_imm32 (ins->inst_imm)) {
3174                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3175                                 temp->inst_c0 = ins->inst_imm;
3176                                 temp->dreg = mono_alloc_ireg (cfg);
3177                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3178                                 ins->sreg1 = temp->dreg;
3179                         }
3180                         break;
3181 #ifdef MONO_ARCH_SIMD_INTRINSICS
3182                 case OP_EXPAND_I1: {
3183                                 int temp_reg1 = mono_alloc_ireg (cfg);
3184                                 int temp_reg2 = mono_alloc_ireg (cfg);
3185                                 int original_reg = ins->sreg1;
3186
3187                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3188                                 temp->sreg1 = original_reg;
3189                                 temp->dreg = temp_reg1;
3190
3191                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3192                                 temp->sreg1 = temp_reg1;
3193                                 temp->dreg = temp_reg2;
3194                                 temp->inst_imm = 8;
3195
3196                                 NEW_INS (cfg, ins, temp, OP_LOR);
3197                                 temp->sreg1 = temp->dreg = temp_reg2;
3198                                 temp->sreg2 = temp_reg1;
3199
3200                                 ins->opcode = OP_EXPAND_I2;
3201                                 ins->sreg1 = temp_reg2;
3202                         }
3203                         break;
3204 #endif
3205                 default:
3206                         break;
3207                 }
3208         }
3209
3210         bb->max_vreg = cfg->next_vreg;
3211 }
3212
3213 static const int
3214 branch_cc_table [] = {
3215         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3216         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3217         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3218 };
3219
3220 /* Maps CMP_... constants to X86_CC_... constants */
3221 static const int
3222 cc_table [] = {
3223         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3224         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3225 };
3226
3227 static const int
3228 cc_signed_table [] = {
3229         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3230         FALSE, FALSE, FALSE, FALSE
3231 };
3232
3233 /*#include "cprop.c"*/
3234
3235 static unsigned char*
3236 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3237 {
3238         if (size == 8)
3239                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3240         else
3241                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3242
3243         if (size == 1)
3244                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3245         else if (size == 2)
3246                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3247         return code;
3248 }
3249
3250 static unsigned char*
3251 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3252 {
3253         int sreg = tree->sreg1;
3254         int need_touch = FALSE;
3255
3256 #if defined(TARGET_WIN32)
3257         need_touch = TRUE;
3258 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3259         if (!tree->flags & MONO_INST_INIT)
3260                 need_touch = TRUE;
3261 #endif
3262
3263         if (need_touch) {
3264                 guint8* br[5];
3265
3266                 /*
3267                  * Under Windows:
3268                  * If requested stack size is larger than one page,
3269                  * perform stack-touch operation
3270                  */
3271                 /*
3272                  * Generate stack probe code.
3273                  * Under Windows, it is necessary to allocate one page at a time,
3274                  * "touching" stack after each successful sub-allocation. This is
3275                  * because of the way stack growth is implemented - there is a
3276                  * guard page before the lowest stack page that is currently commited.
3277                  * Stack normally grows sequentially so OS traps access to the
3278                  * guard page and commits more pages when needed.
3279                  */
3280                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3281                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3282
3283                 br[2] = code; /* loop */
3284                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3285                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3286                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3287                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3288                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3289                 amd64_patch (br[3], br[2]);
3290                 amd64_test_reg_reg (code, sreg, sreg);
3291                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3292                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3293
3294                 br[1] = code; x86_jump8 (code, 0);
3295
3296                 amd64_patch (br[0], code);
3297                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3298                 amd64_patch (br[1], code);
3299                 amd64_patch (br[4], code);
3300         }
3301         else
3302                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3303
3304         if (tree->flags & MONO_INST_INIT) {
3305                 int offset = 0;
3306                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3307                         amd64_push_reg (code, AMD64_RAX);
3308                         offset += 8;
3309                 }
3310                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3311                         amd64_push_reg (code, AMD64_RCX);
3312                         offset += 8;
3313                 }
3314                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3315                         amd64_push_reg (code, AMD64_RDI);
3316                         offset += 8;
3317                 }
3318
3319                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3320                 if (sreg != AMD64_RCX)
3321                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3322                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3323
3324                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3325                 if (cfg->param_area)
3326                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3327                 amd64_cld (code);
3328                 amd64_prefix (code, X86_REP_PREFIX);
3329                 amd64_stosl (code);
3330
3331                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3332                         amd64_pop_reg (code, AMD64_RDI);
3333                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3334                         amd64_pop_reg (code, AMD64_RCX);
3335                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3336                         amd64_pop_reg (code, AMD64_RAX);
3337         }
3338         return code;
3339 }
3340
3341 static guint8*
3342 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3343 {
3344         CallInfo *cinfo;
3345         guint32 quad;
3346
3347         /* Move return value to the target register */
3348         /* FIXME: do this in the local reg allocator */
3349         switch (ins->opcode) {
3350         case OP_CALL:
3351         case OP_CALL_REG:
3352         case OP_CALL_MEMBASE:
3353         case OP_LCALL:
3354         case OP_LCALL_REG:
3355         case OP_LCALL_MEMBASE:
3356                 g_assert (ins->dreg == AMD64_RAX);
3357                 break;
3358         case OP_FCALL:
3359         case OP_FCALL_REG:
3360         case OP_FCALL_MEMBASE: {
3361                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3362                 if (rtype->type == MONO_TYPE_R4) {
3363                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3364                 }
3365                 else {
3366                         if (ins->dreg != AMD64_XMM0)
3367                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3368                 }
3369                 break;
3370         }
3371         case OP_RCALL:
3372         case OP_RCALL_REG:
3373         case OP_RCALL_MEMBASE:
3374                 if (ins->dreg != AMD64_XMM0)
3375                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3376                 break;
3377         case OP_VCALL:
3378         case OP_VCALL_REG:
3379         case OP_VCALL_MEMBASE:
3380         case OP_VCALL2:
3381         case OP_VCALL2_REG:
3382         case OP_VCALL2_MEMBASE:
3383                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3384                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3385                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3386
3387                         /* Load the destination address */
3388                         g_assert (loc->opcode == OP_REGOFFSET);
3389                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3390
3391                         for (quad = 0; quad < 2; quad ++) {
3392                                 switch (cinfo->ret.pair_storage [quad]) {
3393                                 case ArgInIReg:
3394                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3395                                         break;
3396                                 case ArgInFloatSSEReg:
3397                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3398                                         break;
3399                                 case ArgInDoubleSSEReg:
3400                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3401                                         break;
3402                                 case ArgNone:
3403                                         break;
3404                                 default:
3405                                         NOT_IMPLEMENTED;
3406                                 }
3407                         }
3408                 }
3409                 break;
3410         }
3411
3412         return code;
3413 }
3414
3415 #endif /* DISABLE_JIT */
3416
3417 #ifdef TARGET_MACH
3418 static int tls_gs_offset;
3419 #endif
3420
3421 gboolean
3422 mono_arch_have_fast_tls (void)
3423 {
3424 #ifdef TARGET_MACH
3425         static gboolean have_fast_tls = FALSE;
3426         static gboolean inited = FALSE;
3427         guint8 *ins;
3428
3429         if (mini_get_debug_options ()->use_fallback_tls)
3430                 return FALSE;
3431
3432         if (inited)
3433                 return have_fast_tls;
3434
3435         ins = (guint8*)pthread_getspecific;
3436
3437         /*
3438          * We're looking for these two instructions:
3439          *
3440          * mov    %gs:[offset](,%rdi,8),%rax
3441          * retq
3442          */
3443         have_fast_tls = ins [0] == 0x65 &&
3444                        ins [1] == 0x48 &&
3445                        ins [2] == 0x8b &&
3446                        ins [3] == 0x04 &&
3447                        ins [4] == 0xfd &&
3448                        ins [6] == 0x00 &&
3449                        ins [7] == 0x00 &&
3450                        ins [8] == 0x00 &&
3451                        ins [9] == 0xc3;
3452
3453         tls_gs_offset = ins[5];
3454
3455         /*
3456          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3457          * For that version we're looking for these instructions:
3458          *
3459          * pushq  %rbp
3460          * movq   %rsp, %rbp
3461          * mov    %gs:[offset](,%rdi,8),%rax
3462          * popq   %rbp
3463          * retq
3464          */
3465         if (!have_fast_tls) {
3466                 have_fast_tls = ins [0] == 0x55 &&
3467                                ins [1] == 0x48 &&
3468                                ins [2] == 0x89 &&
3469                                ins [3] == 0xe5 &&
3470                                ins [4] == 0x65 &&
3471                                ins [5] == 0x48 &&
3472                                ins [6] == 0x8b &&
3473                                ins [7] == 0x04 &&
3474                                ins [8] == 0xfd &&
3475                                ins [10] == 0x00 &&
3476                                ins [11] == 0x00 &&
3477                                ins [12] == 0x00 &&
3478                                ins [13] == 0x5d &&
3479                                ins [14] == 0xc3;
3480
3481                 tls_gs_offset = ins[9];
3482         }
3483         inited = TRUE;
3484
3485         return have_fast_tls;
3486 #elif defined(TARGET_ANDROID)
3487         return FALSE;
3488 #else
3489         if (mini_get_debug_options ()->use_fallback_tls)
3490                 return FALSE;
3491         return TRUE;
3492 #endif
3493 }
3494
3495 /*
3496  * mono_amd64_emit_tls_get:
3497  * @code: buffer to store code to
3498  * @dreg: hard register where to place the result
3499  * @tls_offset: offset info
3500  *
3501  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3502  * the dreg register the item in the thread local storage identified
3503  * by tls_offset.
3504  *
3505  * Returns: a pointer to the end of the stored code
3506  */
3507 static guint8*
3508 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3509 {
3510 #ifdef TARGET_WIN32
3511         if (tls_offset < 64) {
3512                 x86_prefix (code, X86_GS_PREFIX);
3513                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3514         } else {
3515                 guint8 *buf [16];
3516
3517                 g_assert (tls_offset < 0x440);
3518                 /* Load TEB->TlsExpansionSlots */
3519                 x86_prefix (code, X86_GS_PREFIX);
3520                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3521                 amd64_test_reg_reg (code, dreg, dreg);
3522                 buf [0] = code;
3523                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3524                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3525                 amd64_patch (buf [0], code);
3526         }
3527 #elif defined(TARGET_MACH)
3528         x86_prefix (code, X86_GS_PREFIX);
3529         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3530 #else
3531         if (optimize_for_xen) {
3532                 x86_prefix (code, X86_FS_PREFIX);
3533                 amd64_mov_reg_mem (code, dreg, 0, 8);
3534                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3535         } else {
3536                 x86_prefix (code, X86_FS_PREFIX);
3537                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3538         }
3539 #endif
3540         return code;
3541 }
3542
3543 static guint8*
3544 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3545 {
3546 #ifdef TARGET_WIN32
3547         g_assert_not_reached ();
3548 #elif defined(TARGET_MACH)
3549         x86_prefix (code, X86_GS_PREFIX);
3550         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3551 #else
3552         g_assert (!optimize_for_xen);
3553         x86_prefix (code, X86_FS_PREFIX);
3554         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3555 #endif
3556         return code;
3557 }
3558
3559 /*
3560  * emit_setup_lmf:
3561  *
3562  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3563  */
3564 static guint8*
3565 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3566 {
3567         /*
3568          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3569          */
3570         /*
3571          * sp is saved right before calls but we need to save it here too so
3572          * async stack walks would work.
3573          */
3574         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3575         /* Save rbp */
3576         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3577         if (cfg->arch.omit_fp && cfa_offset != -1)
3578                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3579
3580         /* These can't contain refs */
3581         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3582         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3583         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3584         /* These are handled automatically by the stack marking code */
3585         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3586
3587         return code;
3588 }
3589
3590 #ifdef TARGET_WIN32
3591
3592 #define TEB_LAST_ERROR_OFFSET 0x068
3593
3594 static guint8*
3595 emit_get_last_error (guint8* code, int dreg)
3596 {
3597         /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3598         x86_prefix (code, X86_GS_PREFIX);
3599         amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3600
3601         return code;
3602 }
3603
3604 #else
3605
3606 static guint8*
3607 emit_get_last_error (guint8* code, int dreg)
3608 {
3609         g_assert_not_reached ();
3610 }
3611
3612 #endif
3613
3614 /* benchmark and set based on cpu */
3615 #define LOOP_ALIGNMENT 8
3616 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3617
3618 #ifndef DISABLE_JIT
3619 void
3620 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3621 {
3622         MonoInst *ins;
3623         MonoCallInst *call;
3624         guint offset;
3625         guint8 *code = cfg->native_code + cfg->code_len;
3626         int max_len;
3627
3628         /* Fix max_offset estimate for each successor bb */
3629         if (cfg->opt & MONO_OPT_BRANCH) {
3630                 int current_offset = cfg->code_len;
3631                 MonoBasicBlock *current_bb;
3632                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3633                         current_bb->max_offset = current_offset;
3634                         current_offset += current_bb->max_length;
3635                 }
3636         }
3637
3638         if (cfg->opt & MONO_OPT_LOOP) {
3639                 int pad, align = LOOP_ALIGNMENT;
3640                 /* set alignment depending on cpu */
3641                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3642                         pad = align - pad;
3643                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3644                         amd64_padding (code, pad);
3645                         cfg->code_len += pad;
3646                         bb->native_offset = cfg->code_len;
3647                 }
3648         }
3649
3650         if (cfg->verbose_level > 2)
3651                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3652
3653         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3654                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3655                 g_assert (!cfg->compile_aot);
3656
3657                 cov->data [bb->dfn].cil_code = bb->cil_code;
3658                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3659                 /* this is not thread save, but good enough */
3660                 amd64_inc_membase (code, AMD64_R11, 0);
3661         }
3662
3663         offset = code - cfg->native_code;
3664
3665         mono_debug_open_block (cfg, bb, offset);
3666
3667     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3668                 x86_breakpoint (code);
3669
3670         MONO_BB_FOR_EACH_INS (bb, ins) {
3671                 offset = code - cfg->native_code;
3672
3673                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3674
3675 #define EXTRA_CODE_SPACE (16)
3676
3677                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3678                         cfg->code_size *= 2;
3679                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3680                         code = cfg->native_code + offset;
3681                         cfg->stat_code_reallocs++;
3682                 }
3683
3684                 if (cfg->debug_info)
3685                         mono_debug_record_line_number (cfg, ins, offset);
3686
3687                 switch (ins->opcode) {
3688                 case OP_BIGMUL:
3689                         amd64_mul_reg (code, ins->sreg2, TRUE);
3690                         break;
3691                 case OP_BIGMUL_UN:
3692                         amd64_mul_reg (code, ins->sreg2, FALSE);
3693                         break;
3694                 case OP_X86_SETEQ_MEMBASE:
3695                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3696                         break;
3697                 case OP_STOREI1_MEMBASE_IMM:
3698                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3699                         break;
3700                 case OP_STOREI2_MEMBASE_IMM:
3701                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3702                         break;
3703                 case OP_STOREI4_MEMBASE_IMM:
3704                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3705                         break;
3706                 case OP_STOREI1_MEMBASE_REG:
3707                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3708                         break;
3709                 case OP_STOREI2_MEMBASE_REG:
3710                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3711                         break;
3712                 /* In AMD64 NaCl, pointers are 4 bytes, */
3713                 /*  so STORE_* != STOREI8_*. Likewise below. */
3714                 case OP_STORE_MEMBASE_REG:
3715                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3716                         break;
3717                 case OP_STOREI8_MEMBASE_REG:
3718                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3719                         break;
3720                 case OP_STOREI4_MEMBASE_REG:
3721                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3722                         break;
3723                 case OP_STORE_MEMBASE_IMM:
3724                         /* In NaCl, this could be a PCONST type, which could */
3725                         /* mean a pointer type was copied directly into the  */
3726                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3727                         /* the value would be 0x00000000FFFFFFFF which is    */
3728                         /* not proper for an imm32 unless you cast it.       */
3729                         g_assert (amd64_is_imm32 (ins->inst_imm));
3730                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3731                         break;
3732                 case OP_STOREI8_MEMBASE_IMM:
3733                         g_assert (amd64_is_imm32 (ins->inst_imm));
3734                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3735                         break;
3736                 case OP_LOAD_MEM:
3737 #ifdef __mono_ilp32__
3738                         /* In ILP32, pointers are 4 bytes, so separate these */
3739                         /* cases, use literal 8 below where we really want 8 */
3740                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3741                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3742                         break;
3743 #endif
3744                 case OP_LOADI8_MEM:
3745                         // FIXME: Decompose this earlier
3746                         if (amd64_use_imm32 (ins->inst_imm))
3747                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3748                         else {
3749                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3750                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3751                         }
3752                         break;
3753                 case OP_LOADI4_MEM:
3754                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3755                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3756                         break;
3757                 case OP_LOADU4_MEM:
3758                         // FIXME: Decompose this earlier
3759                         if (amd64_use_imm32 (ins->inst_imm))
3760                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3761                         else {
3762                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3763                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3764                         }
3765                         break;
3766                 case OP_LOADU1_MEM:
3767                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3768                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3769                         break;
3770                 case OP_LOADU2_MEM:
3771                         /* For NaCl, pointers are 4 bytes, so separate these */
3772                         /* cases, use literal 8 below where we really want 8 */
3773                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3774                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3775                         break;
3776                 case OP_LOAD_MEMBASE:
3777                         g_assert (amd64_is_imm32 (ins->inst_offset));
3778                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3779                         break;
3780                 case OP_LOADI8_MEMBASE:
3781                         /* Use literal 8 instead of sizeof pointer or */
3782                         /* register, we really want 8 for this opcode */
3783                         g_assert (amd64_is_imm32 (ins->inst_offset));
3784                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3785                         break;
3786                 case OP_LOADI4_MEMBASE:
3787                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3788                         break;
3789                 case OP_LOADU4_MEMBASE:
3790                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3791                         break;
3792                 case OP_LOADU1_MEMBASE:
3793                         /* The cpu zero extends the result into 64 bits */
3794                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3795                         break;
3796                 case OP_LOADI1_MEMBASE:
3797                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3798                         break;
3799                 case OP_LOADU2_MEMBASE:
3800                         /* The cpu zero extends the result into 64 bits */
3801                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3802                         break;
3803                 case OP_LOADI2_MEMBASE:
3804                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3805                         break;
3806                 case OP_AMD64_LOADI8_MEMINDEX:
3807                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3808                         break;
3809                 case OP_LCONV_TO_I1:
3810                 case OP_ICONV_TO_I1:
3811                 case OP_SEXT_I1:
3812                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3813                         break;
3814                 case OP_LCONV_TO_I2:
3815                 case OP_ICONV_TO_I2:
3816                 case OP_SEXT_I2:
3817                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3818                         break;
3819                 case OP_LCONV_TO_U1:
3820                 case OP_ICONV_TO_U1:
3821                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3822                         break;
3823                 case OP_LCONV_TO_U2:
3824                 case OP_ICONV_TO_U2:
3825                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3826                         break;
3827                 case OP_ZEXT_I4:
3828                         /* Clean out the upper word */
3829                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3830                         break;
3831                 case OP_SEXT_I4:
3832                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3833                         break;
3834                 case OP_COMPARE:
3835                 case OP_LCOMPARE:
3836                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3837                         break;
3838                 case OP_COMPARE_IMM:
3839 #if defined(__mono_ilp32__)
3840                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3841                         g_assert (amd64_is_imm32 (ins->inst_imm));
3842                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3843                         break;
3844 #endif
3845                 case OP_LCOMPARE_IMM:
3846                         g_assert (amd64_is_imm32 (ins->inst_imm));
3847                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3848                         break;
3849                 case OP_X86_COMPARE_REG_MEMBASE:
3850                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3851                         break;
3852                 case OP_X86_TEST_NULL:
3853                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3854                         break;
3855                 case OP_AMD64_TEST_NULL:
3856                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3857                         break;
3858
3859                 case OP_X86_ADD_REG_MEMBASE:
3860                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3861                         break;
3862                 case OP_X86_SUB_REG_MEMBASE:
3863                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3864                         break;
3865                 case OP_X86_AND_REG_MEMBASE:
3866                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3867                         break;
3868                 case OP_X86_OR_REG_MEMBASE:
3869                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3870                         break;
3871                 case OP_X86_XOR_REG_MEMBASE:
3872                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3873                         break;
3874
3875                 case OP_X86_ADD_MEMBASE_IMM:
3876                         /* FIXME: Make a 64 version too */
3877                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3878                         break;
3879                 case OP_X86_SUB_MEMBASE_IMM:
3880                         g_assert (amd64_is_imm32 (ins->inst_imm));
3881                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3882                         break;
3883                 case OP_X86_AND_MEMBASE_IMM:
3884                         g_assert (amd64_is_imm32 (ins->inst_imm));
3885                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3886                         break;
3887                 case OP_X86_OR_MEMBASE_IMM:
3888                         g_assert (amd64_is_imm32 (ins->inst_imm));
3889                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3890                         break;
3891                 case OP_X86_XOR_MEMBASE_IMM:
3892                         g_assert (amd64_is_imm32 (ins->inst_imm));
3893                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3894                         break;
3895                 case OP_X86_ADD_MEMBASE_REG:
3896                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3897                         break;
3898                 case OP_X86_SUB_MEMBASE_REG:
3899                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3900                         break;
3901                 case OP_X86_AND_MEMBASE_REG:
3902                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3903                         break;
3904                 case OP_X86_OR_MEMBASE_REG:
3905                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3906                         break;
3907                 case OP_X86_XOR_MEMBASE_REG:
3908                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3909                         break;
3910                 case OP_X86_INC_MEMBASE:
3911                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3912                         break;
3913                 case OP_X86_INC_REG:
3914                         amd64_inc_reg_size (code, ins->dreg, 4);
3915                         break;
3916                 case OP_X86_DEC_MEMBASE:
3917                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3918                         break;
3919                 case OP_X86_DEC_REG:
3920                         amd64_dec_reg_size (code, ins->dreg, 4);
3921                         break;
3922                 case OP_X86_MUL_REG_MEMBASE:
3923                 case OP_X86_MUL_MEMBASE_REG:
3924                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3925                         break;
3926                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3927                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3928                         break;
3929                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3930                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3931                         break;
3932                 case OP_AMD64_COMPARE_MEMBASE_REG:
3933                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3934                         break;
3935                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3936                         g_assert (amd64_is_imm32 (ins->inst_imm));
3937                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3938                         break;
3939                 case OP_X86_COMPARE_MEMBASE8_IMM:
3940                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3941                         break;
3942                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3943                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3944                         break;
3945                 case OP_AMD64_COMPARE_REG_MEMBASE:
3946                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3947                         break;
3948
3949                 case OP_AMD64_ADD_REG_MEMBASE:
3950                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3951                         break;
3952                 case OP_AMD64_SUB_REG_MEMBASE:
3953                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3954                         break;
3955                 case OP_AMD64_AND_REG_MEMBASE:
3956                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3957                         break;
3958                 case OP_AMD64_OR_REG_MEMBASE:
3959                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3960                         break;
3961                 case OP_AMD64_XOR_REG_MEMBASE:
3962                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3963                         break;
3964
3965                 case OP_AMD64_ADD_MEMBASE_REG:
3966                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3967                         break;
3968                 case OP_AMD64_SUB_MEMBASE_REG:
3969                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3970                         break;
3971                 case OP_AMD64_AND_MEMBASE_REG:
3972                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3973                         break;
3974                 case OP_AMD64_OR_MEMBASE_REG:
3975                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3976                         break;
3977                 case OP_AMD64_XOR_MEMBASE_REG:
3978                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3979                         break;
3980
3981                 case OP_AMD64_ADD_MEMBASE_IMM:
3982                         g_assert (amd64_is_imm32 (ins->inst_imm));
3983                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3984                         break;
3985                 case OP_AMD64_SUB_MEMBASE_IMM:
3986                         g_assert (amd64_is_imm32 (ins->inst_imm));
3987                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3988                         break;
3989                 case OP_AMD64_AND_MEMBASE_IMM:
3990                         g_assert (amd64_is_imm32 (ins->inst_imm));
3991                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3992                         break;
3993                 case OP_AMD64_OR_MEMBASE_IMM:
3994                         g_assert (amd64_is_imm32 (ins->inst_imm));
3995                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3996                         break;
3997                 case OP_AMD64_XOR_MEMBASE_IMM:
3998                         g_assert (amd64_is_imm32 (ins->inst_imm));
3999                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4000                         break;
4001
4002                 case OP_BREAK:
4003                         amd64_breakpoint (code);
4004                         break;
4005                 case OP_RELAXED_NOP:
4006                         x86_prefix (code, X86_REP_PREFIX);
4007                         x86_nop (code);
4008                         break;
4009                 case OP_HARD_NOP:
4010                         x86_nop (code);
4011                         break;
4012                 case OP_NOP:
4013                 case OP_DUMMY_USE:
4014                 case OP_DUMMY_STORE:
4015                 case OP_DUMMY_ICONST:
4016                 case OP_DUMMY_R8CONST:
4017                 case OP_NOT_REACHED:
4018                 case OP_NOT_NULL:
4019                         break;
4020                 case OP_IL_SEQ_POINT:
4021                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4022                         break;
4023                 case OP_SEQ_POINT: {
4024                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4025                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4026                                 guint8 *label;
4027
4028                                 /* Load ss_tramp_var */
4029                                 /* This is equal to &ss_trampoline */
4030                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4031                                 /* Load the trampoline address */
4032                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4033                                 /* Call it if it is non-null */
4034                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4035                                 label = code;
4036                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4037                                 amd64_call_reg (code, AMD64_R11);
4038                                 amd64_patch (label, code);
4039                         }
4040
4041                         /*
4042                          * This is the address which is saved in seq points,
4043                          */
4044                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4045
4046                         if (cfg->compile_aot) {
4047                                 guint32 offset = code - cfg->native_code;
4048                                 guint32 val;
4049                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4050                                 guint8 *label;
4051
4052                                 /* Load info var */
4053                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4054                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4055                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4056                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4057                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4058                                 label = code;
4059                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4060                                 /* Call the trampoline */
4061                                 amd64_call_reg (code, AMD64_R11);
4062                                 amd64_patch (label, code);
4063                         } else {
4064                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4065                                 guint8 *label;
4066
4067                                 /*
4068                                  * Emit a test+branch against a constant, the constant will be overwritten
4069                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4070                                  */
4071                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4072                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4073                                 label = code;
4074                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4075
4076                                 g_assert (var);
4077                                 g_assert (var->opcode == OP_REGOFFSET);
4078                                 /* Load bp_tramp_var */
4079                                 /* This is equal to &bp_trampoline */
4080                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4081                                 /* Call the trampoline */
4082                                 amd64_call_membase (code, AMD64_R11, 0);
4083                                 amd64_patch (label, code);
4084                         }
4085                         /*
4086                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4087                          * to another IL offset.
4088                          */
4089                         x86_nop (code);
4090                         break;
4091                 }
4092                 case OP_ADDCC:
4093                 case OP_LADDCC:
4094                 case OP_LADD:
4095                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4096                         break;
4097                 case OP_ADC:
4098                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4099                         break;
4100                 case OP_ADD_IMM:
4101                 case OP_LADD_IMM:
4102                         g_assert (amd64_is_imm32 (ins->inst_imm));
4103                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4104                         break;
4105                 case OP_ADC_IMM:
4106                         g_assert (amd64_is_imm32 (ins->inst_imm));
4107                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4108                         break;
4109                 case OP_SUBCC:
4110                 case OP_LSUBCC:
4111                 case OP_LSUB:
4112                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4113                         break;
4114                 case OP_SBB:
4115                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4116                         break;
4117                 case OP_SUB_IMM:
4118                 case OP_LSUB_IMM:
4119                         g_assert (amd64_is_imm32 (ins->inst_imm));
4120                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4121                         break;
4122                 case OP_SBB_IMM:
4123                         g_assert (amd64_is_imm32 (ins->inst_imm));
4124                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4125                         break;
4126                 case OP_LAND:
4127                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4128                         break;
4129                 case OP_AND_IMM:
4130                 case OP_LAND_IMM:
4131                         g_assert (amd64_is_imm32 (ins->inst_imm));
4132                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4133                         break;
4134                 case OP_LMUL:
4135                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4136                         break;
4137                 case OP_MUL_IMM:
4138                 case OP_LMUL_IMM:
4139                 case OP_IMUL_IMM: {
4140                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4141
4142                         switch (ins->inst_imm) {
4143                         case 2:
4144                                 /* MOV r1, r2 */
4145                                 /* ADD r1, r1 */
4146                                 if (ins->dreg != ins->sreg1)
4147                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4148                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4149                                 break;
4150                         case 3:
4151                                 /* LEA r1, [r2 + r2*2] */
4152                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4153                                 break;
4154                         case 5:
4155                                 /* LEA r1, [r2 + r2*4] */
4156                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4157                                 break;
4158                         case 6:
4159                                 /* LEA r1, [r2 + r2*2] */
4160                                 /* ADD r1, r1          */
4161                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4162                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4163                                 break;
4164                         case 9:
4165                                 /* LEA r1, [r2 + r2*8] */
4166                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4167                                 break;
4168                         case 10:
4169                                 /* LEA r1, [r2 + r2*4] */
4170                                 /* ADD r1, r1          */
4171                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4172                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4173                                 break;
4174                         case 12:
4175                                 /* LEA r1, [r2 + r2*2] */
4176                                 /* SHL r1, 2           */
4177                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4178                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4179                                 break;
4180                         case 25:
4181                                 /* LEA r1, [r2 + r2*4] */
4182                                 /* LEA r1, [r1 + r1*4] */
4183                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4184                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4185                                 break;
4186                         case 100:
4187                                 /* LEA r1, [r2 + r2*4] */
4188                                 /* SHL r1, 2           */
4189                                 /* LEA r1, [r1 + r1*4] */
4190                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4191                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4192                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4193                                 break;
4194                         default:
4195                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4196                                 break;
4197                         }
4198                         break;
4199                 }
4200                 case OP_LDIV:
4201                 case OP_LREM:
4202                         /* Regalloc magic makes the div/rem cases the same */
4203                         if (ins->sreg2 == AMD64_RDX) {
4204                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4205                                 amd64_cdq (code);
4206                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4207                         } else {
4208                                 amd64_cdq (code);
4209                                 amd64_div_reg (code, ins->sreg2, TRUE);
4210                         }
4211                         break;
4212                 case OP_LDIV_UN:
4213                 case OP_LREM_UN:
4214                         if (ins->sreg2 == AMD64_RDX) {
4215                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4216                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4217                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4218                         } else {
4219                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4220                                 amd64_div_reg (code, ins->sreg2, FALSE);
4221                         }
4222                         break;
4223                 case OP_IDIV:
4224                 case OP_IREM:
4225                         if (ins->sreg2 == AMD64_RDX) {
4226                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4227                                 amd64_cdq_size (code, 4);
4228                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4229                         } else {
4230                                 amd64_cdq_size (code, 4);
4231                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4232                         }
4233                         break;
4234                 case OP_IDIV_UN:
4235                 case OP_IREM_UN:
4236                         if (ins->sreg2 == AMD64_RDX) {
4237                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4238                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4239                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4240                         } else {
4241                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4242                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4243                         }
4244                         break;
4245                 case OP_LMUL_OVF:
4246                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4247                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4248                         break;
4249                 case OP_LOR:
4250                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4251                         break;
4252                 case OP_OR_IMM:
4253                 case OP_LOR_IMM:
4254                         g_assert (amd64_is_imm32 (ins->inst_imm));
4255                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4256                         break;
4257                 case OP_LXOR:
4258                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4259                         break;
4260                 case OP_XOR_IMM:
4261                 case OP_LXOR_IMM:
4262                         g_assert (amd64_is_imm32 (ins->inst_imm));
4263                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4264                         break;
4265                 case OP_LSHL:
4266                         g_assert (ins->sreg2 == AMD64_RCX);
4267                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4268                         break;
4269                 case OP_LSHR:
4270                         g_assert (ins->sreg2 == AMD64_RCX);
4271                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4272                         break;
4273                 case OP_SHR_IMM:
4274                 case OP_LSHR_IMM:
4275                         g_assert (amd64_is_imm32 (ins->inst_imm));
4276                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4277                         break;
4278                 case OP_SHR_UN_IMM:
4279                         g_assert (amd64_is_imm32 (ins->inst_imm));
4280                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4281                         break;
4282                 case OP_LSHR_UN_IMM:
4283                         g_assert (amd64_is_imm32 (ins->inst_imm));
4284                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4285                         break;
4286                 case OP_LSHR_UN:
4287                         g_assert (ins->sreg2 == AMD64_RCX);
4288                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4289                         break;
4290                 case OP_SHL_IMM:
4291                 case OP_LSHL_IMM:
4292                         g_assert (amd64_is_imm32 (ins->inst_imm));
4293                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4294                         break;
4295
4296                 case OP_IADDCC:
4297                 case OP_IADD:
4298                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4299                         break;
4300                 case OP_IADC:
4301                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4302                         break;
4303                 case OP_IADD_IMM:
4304                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4305                         break;
4306                 case OP_IADC_IMM:
4307                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4308                         break;
4309                 case OP_ISUBCC:
4310                 case OP_ISUB:
4311                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4312                         break;
4313                 case OP_ISBB:
4314                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4315                         break;
4316                 case OP_ISUB_IMM:
4317                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4318                         break;
4319                 case OP_ISBB_IMM:
4320                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4321                         break;
4322                 case OP_IAND:
4323                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4324                         break;
4325                 case OP_IAND_IMM:
4326                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4327                         break;
4328                 case OP_IOR:
4329                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4330                         break;
4331                 case OP_IOR_IMM:
4332                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4333                         break;
4334                 case OP_IXOR:
4335                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4336                         break;
4337                 case OP_IXOR_IMM:
4338                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4339                         break;
4340                 case OP_INEG:
4341                         amd64_neg_reg_size (code, ins->sreg1, 4);
4342                         break;
4343                 case OP_INOT:
4344                         amd64_not_reg_size (code, ins->sreg1, 4);
4345                         break;
4346                 case OP_ISHL:
4347                         g_assert (ins->sreg2 == AMD64_RCX);
4348                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4349                         break;
4350                 case OP_ISHR:
4351                         g_assert (ins->sreg2 == AMD64_RCX);
4352                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4353                         break;
4354                 case OP_ISHR_IMM:
4355                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4356                         break;
4357                 case OP_ISHR_UN_IMM:
4358                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4359                         break;
4360                 case OP_ISHR_UN:
4361                         g_assert (ins->sreg2 == AMD64_RCX);
4362                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4363                         break;
4364                 case OP_ISHL_IMM:
4365                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4366                         break;
4367                 case OP_IMUL:
4368                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4369                         break;
4370                 case OP_IMUL_OVF:
4371                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4372                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4373                         break;
4374                 case OP_IMUL_OVF_UN:
4375                 case OP_LMUL_OVF_UN: {
4376                         /* the mul operation and the exception check should most likely be split */
4377                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4378                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4379                         /*g_assert (ins->sreg2 == X86_EAX);
4380                         g_assert (ins->dreg == X86_EAX);*/
4381                         if (ins->sreg2 == X86_EAX) {
4382                                 non_eax_reg = ins->sreg1;
4383                         } else if (ins->sreg1 == X86_EAX) {
4384                                 non_eax_reg = ins->sreg2;
4385                         } else {
4386                                 /* no need to save since we're going to store to it anyway */
4387                                 if (ins->dreg != X86_EAX) {
4388                                         saved_eax = TRUE;
4389                                         amd64_push_reg (code, X86_EAX);
4390                                 }
4391                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4392                                 non_eax_reg = ins->sreg2;
4393                         }
4394                         if (ins->dreg == X86_EDX) {
4395                                 if (!saved_eax) {
4396                                         saved_eax = TRUE;
4397                                         amd64_push_reg (code, X86_EAX);
4398                                 }
4399                         } else {
4400                                 saved_edx = TRUE;
4401                                 amd64_push_reg (code, X86_EDX);
4402                         }
4403                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4404                         /* save before the check since pop and mov don't change the flags */
4405                         if (ins->dreg != X86_EAX)
4406                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4407                         if (saved_edx)
4408                                 amd64_pop_reg (code, X86_EDX);
4409                         if (saved_eax)
4410                                 amd64_pop_reg (code, X86_EAX);
4411                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4412                         break;
4413                 }
4414                 case OP_ICOMPARE:
4415                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4416                         break;
4417                 case OP_ICOMPARE_IMM:
4418                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4419                         break;
4420                 case OP_IBEQ:
4421                 case OP_IBLT:
4422                 case OP_IBGT:
4423                 case OP_IBGE:
4424                 case OP_IBLE:
4425                 case OP_LBEQ:
4426                 case OP_LBLT:
4427                 case OP_LBGT:
4428                 case OP_LBGE:
4429                 case OP_LBLE:
4430                 case OP_IBNE_UN:
4431                 case OP_IBLT_UN:
4432                 case OP_IBGT_UN:
4433                 case OP_IBGE_UN:
4434                 case OP_IBLE_UN:
4435                 case OP_LBNE_UN:
4436                 case OP_LBLT_UN:
4437                 case OP_LBGT_UN:
4438                 case OP_LBGE_UN:
4439                 case OP_LBLE_UN:
4440                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4441                         break;
4442
4443                 case OP_CMOV_IEQ:
4444                 case OP_CMOV_IGE:
4445                 case OP_CMOV_IGT:
4446                 case OP_CMOV_ILE:
4447                 case OP_CMOV_ILT:
4448                 case OP_CMOV_INE_UN:
4449                 case OP_CMOV_IGE_UN:
4450                 case OP_CMOV_IGT_UN:
4451                 case OP_CMOV_ILE_UN:
4452                 case OP_CMOV_ILT_UN:
4453                 case OP_CMOV_LEQ:
4454                 case OP_CMOV_LGE:
4455                 case OP_CMOV_LGT:
4456                 case OP_CMOV_LLE:
4457                 case OP_CMOV_LLT:
4458                 case OP_CMOV_LNE_UN:
4459                 case OP_CMOV_LGE_UN:
4460                 case OP_CMOV_LGT_UN:
4461                 case OP_CMOV_LLE_UN:
4462                 case OP_CMOV_LLT_UN:
4463                         g_assert (ins->dreg == ins->sreg1);
4464                         /* This needs to operate on 64 bit values */
4465                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4466                         break;
4467
4468                 case OP_LNOT:
4469                         amd64_not_reg (code, ins->sreg1);
4470                         break;
4471                 case OP_LNEG:
4472                         amd64_neg_reg (code, ins->sreg1);
4473                         break;
4474
4475                 case OP_ICONST:
4476                 case OP_I8CONST:
4477                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4478                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4479                         else
4480                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4481                         break;
4482                 case OP_AOTCONST:
4483                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4484                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4485                         break;
4486                 case OP_JUMP_TABLE:
4487                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4488                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4489                         break;
4490                 case OP_MOVE:
4491                         if (ins->dreg != ins->sreg1)
4492                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4493                         break;
4494                 case OP_AMD64_SET_XMMREG_R4: {
4495                         if (cfg->r4fp) {
4496                                 if (ins->dreg != ins->sreg1)
4497                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4498                         } else {
4499                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4500                         }
4501                         break;
4502                 }
4503                 case OP_AMD64_SET_XMMREG_R8: {
4504                         if (ins->dreg != ins->sreg1)
4505                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4506                         break;
4507                 }
4508                 case OP_TAILCALL: {
4509                         MonoCallInst *call = (MonoCallInst*)ins;
4510                         int i, save_area_offset;
4511
4512                         g_assert (!cfg->method->save_lmf);
4513
4514                         /* Restore callee saved registers */
4515                         save_area_offset = cfg->arch.reg_save_area_offset;
4516                         for (i = 0; i < AMD64_NREG; ++i)
4517                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4518                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4519                                         save_area_offset += 8;
4520                                 }
4521
4522                         if (cfg->arch.omit_fp) {
4523                                 if (cfg->arch.stack_alloc_size)
4524                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4525                                 // FIXME:
4526                                 if (call->stack_usage)
4527                                         NOT_IMPLEMENTED;
4528                         } else {
4529                                 /* Copy arguments on the stack to our argument area */
4530                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4531                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4532                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4533                                 }
4534
4535                                 amd64_leave (code);
4536                         }
4537
4538                         offset = code - cfg->native_code;
4539                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4540                         if (cfg->compile_aot)
4541                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4542                         else
4543                                 amd64_set_reg_template (code, AMD64_R11);
4544                         amd64_jump_reg (code, AMD64_R11);
4545                         ins->flags |= MONO_INST_GC_CALLSITE;
4546                         ins->backend.pc_offset = code - cfg->native_code;
4547                         break;
4548                 }
4549                 case OP_CHECK_THIS:
4550                         /* ensure ins->sreg1 is not NULL */
4551                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4552                         break;
4553                 case OP_ARGLIST: {
4554                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4555                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4556                         break;
4557                 }
4558                 case OP_CALL:
4559                 case OP_FCALL:
4560                 case OP_RCALL:
4561                 case OP_LCALL:
4562                 case OP_VCALL:
4563                 case OP_VCALL2:
4564                 case OP_VOIDCALL:
4565                         call = (MonoCallInst*)ins;
4566                         /*
4567                          * The AMD64 ABI forces callers to know about varargs.
4568                          */
4569                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4570                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4571                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4572                                 /*
4573                                  * Since the unmanaged calling convention doesn't contain a
4574                                  * 'vararg' entry, we have to treat every pinvoke call as a
4575                                  * potential vararg call.
4576                                  */
4577                                 guint32 nregs, i;
4578                                 nregs = 0;
4579                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4580                                         if (call->used_fregs & (1 << i))
4581                                                 nregs ++;
4582                                 if (!nregs)
4583                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4584                                 else
4585                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4586                         }
4587
4588                         if (ins->flags & MONO_INST_HAS_METHOD)
4589                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4590                         else
4591                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4592                         ins->flags |= MONO_INST_GC_CALLSITE;
4593                         ins->backend.pc_offset = code - cfg->native_code;
4594                         code = emit_move_return_value (cfg, ins, code);
4595                         break;
4596                 case OP_FCALL_REG:
4597                 case OP_RCALL_REG:
4598                 case OP_LCALL_REG:
4599                 case OP_VCALL_REG:
4600                 case OP_VCALL2_REG:
4601                 case OP_VOIDCALL_REG:
4602                 case OP_CALL_REG:
4603                         call = (MonoCallInst*)ins;
4604
4605                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4606                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4607                                 ins->sreg1 = AMD64_R11;
4608                         }
4609
4610                         /*
4611                          * The AMD64 ABI forces callers to know about varargs.
4612                          */
4613                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4614                                 if (ins->sreg1 == AMD64_RAX) {
4615                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4616                                         ins->sreg1 = AMD64_R11;
4617                                 }
4618                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4619                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4620                                 /*
4621                                  * Since the unmanaged calling convention doesn't contain a
4622                                  * 'vararg' entry, we have to treat every pinvoke call as a
4623                                  * potential vararg call.
4624                                  */
4625                                 guint32 nregs, i;
4626                                 nregs = 0;
4627                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4628                                         if (call->used_fregs & (1 << i))
4629                                                 nregs ++;
4630                                 if (ins->sreg1 == AMD64_RAX) {
4631                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4632                                         ins->sreg1 = AMD64_R11;
4633                                 }
4634                                 if (!nregs)
4635                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4636                                 else
4637                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4638                         }
4639
4640                         amd64_call_reg (code, ins->sreg1);
4641                         ins->flags |= MONO_INST_GC_CALLSITE;
4642                         ins->backend.pc_offset = code - cfg->native_code;
4643                         code = emit_move_return_value (cfg, ins, code);
4644                         break;
4645                 case OP_FCALL_MEMBASE:
4646                 case OP_RCALL_MEMBASE:
4647                 case OP_LCALL_MEMBASE:
4648                 case OP_VCALL_MEMBASE:
4649                 case OP_VCALL2_MEMBASE:
4650                 case OP_VOIDCALL_MEMBASE:
4651                 case OP_CALL_MEMBASE:
4652                         call = (MonoCallInst*)ins;
4653
4654                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4655                         ins->flags |= MONO_INST_GC_CALLSITE;
4656                         ins->backend.pc_offset = code - cfg->native_code;
4657                         code = emit_move_return_value (cfg, ins, code);
4658                         break;
4659                 case OP_DYN_CALL: {
4660                         int i;
4661                         MonoInst *var = cfg->dyn_call_var;
4662                         guint8 *label;
4663
4664                         g_assert (var->opcode == OP_REGOFFSET);
4665
4666                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4667                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4668                         /* r10 = ftn */
4669                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4670
4671                         /* Save args buffer */
4672                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4673
4674                         /* Set fp arg regs */
4675                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4676                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4677                         label = code;
4678                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4679                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4680                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4681                         amd64_patch (label, code);
4682
4683                         /* Set stack args */
4684                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4685                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4686                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4687                         }
4688
4689                         /* Set argument registers */
4690                         for (i = 0; i < PARAM_REGS; ++i)
4691                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4692
4693                         /* Make the call */
4694                         amd64_call_reg (code, AMD64_R10);
4695
4696                         ins->flags |= MONO_INST_GC_CALLSITE;
4697                         ins->backend.pc_offset = code - cfg->native_code;
4698
4699                         /* Save result */
4700                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4701                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4702                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4703                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4704                         break;
4705                 }
4706                 case OP_AMD64_SAVE_SP_TO_LMF: {
4707                         MonoInst *lmf_var = cfg->lmf_var;
4708                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4709                         break;
4710                 }
4711                 case OP_X86_PUSH:
4712                         g_assert_not_reached ();
4713                         amd64_push_reg (code, ins->sreg1);
4714                         break;
4715                 case OP_X86_PUSH_IMM:
4716                         g_assert_not_reached ();
4717                         g_assert (amd64_is_imm32 (ins->inst_imm));
4718                         amd64_push_imm (code, ins->inst_imm);
4719                         break;
4720                 case OP_X86_PUSH_MEMBASE:
4721                         g_assert_not_reached ();
4722                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4723                         break;
4724                 case OP_X86_PUSH_OBJ: {
4725                         int size = ALIGN_TO (ins->inst_imm, 8);
4726
4727                         g_assert_not_reached ();
4728
4729                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4730                         amd64_push_reg (code, AMD64_RDI);
4731                         amd64_push_reg (code, AMD64_RSI);
4732                         amd64_push_reg (code, AMD64_RCX);
4733                         if (ins->inst_offset)
4734                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4735                         else
4736                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4737                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4738                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4739                         amd64_cld (code);
4740                         amd64_prefix (code, X86_REP_PREFIX);
4741                         amd64_movsd (code);
4742                         amd64_pop_reg (code, AMD64_RCX);
4743                         amd64_pop_reg (code, AMD64_RSI);
4744                         amd64_pop_reg (code, AMD64_RDI);
4745                         break;
4746                 }
4747                 case OP_GENERIC_CLASS_INIT: {
4748                         guint8 *jump;
4749
4750                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4751
4752                         amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4753                         jump = code;
4754                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4755
4756                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4757                         ins->flags |= MONO_INST_GC_CALLSITE;
4758                         ins->backend.pc_offset = code - cfg->native_code;
4759
4760                         x86_patch (jump, code);
4761                         break;
4762                 }
4763
4764                 case OP_X86_LEA:
4765                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4766                         break;
4767                 case OP_X86_LEA_MEMBASE:
4768                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4769                         break;
4770                 case OP_X86_XCHG:
4771                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4772                         break;
4773                 case OP_LOCALLOC:
4774                         /* keep alignment */
4775                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4776                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4777                         code = mono_emit_stack_alloc (cfg, code, ins);
4778                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4779                         if (cfg->param_area)
4780                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4781                         break;
4782                 case OP_LOCALLOC_IMM: {
4783                         guint32 size = ins->inst_imm;
4784                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4785
4786                         if (ins->flags & MONO_INST_INIT) {
4787                                 if (size < 64) {
4788                                         int i;
4789
4790                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4791                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4792
4793                                         for (i = 0; i < size; i += 8)
4794                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4795                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4796                                 } else {
4797                                         amd64_mov_reg_imm (code, ins->dreg, size);
4798                                         ins->sreg1 = ins->dreg;
4799
4800                                         code = mono_emit_stack_alloc (cfg, code, ins);
4801                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4802                                 }
4803                         } else {
4804                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4805                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4806                         }
4807                         if (cfg->param_area)
4808                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4809                         break;
4810                 }
4811                 case OP_THROW: {
4812                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4813                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4814                                              (gpointer)"mono_arch_throw_exception", FALSE);
4815                         ins->flags |= MONO_INST_GC_CALLSITE;
4816                         ins->backend.pc_offset = code - cfg->native_code;
4817                         break;
4818                 }
4819                 case OP_RETHROW: {
4820                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4821                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4822                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4823                         ins->flags |= MONO_INST_GC_CALLSITE;
4824                         ins->backend.pc_offset = code - cfg->native_code;
4825                         break;
4826                 }
4827                 case OP_CALL_HANDLER:
4828                         /* Align stack */
4829                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4830                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4831                         amd64_call_imm (code, 0);
4832                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4833                         /* Restore stack alignment */
4834                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4835                         break;
4836                 case OP_START_HANDLER: {
4837                         /* Even though we're saving RSP, use sizeof */
4838                         /* gpointer because spvar is of type IntPtr */
4839                         /* see: mono_create_spvar_for_region */
4840                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4841                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4842
4843                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4844                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4845                                 cfg->param_area) {
4846                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4847                         }
4848                         break;
4849                 }
4850                 case OP_ENDFINALLY: {
4851                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4852                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4853                         amd64_ret (code);
4854                         break;
4855                 }
4856                 case OP_ENDFILTER: {
4857                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4858                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4859                         /* The local allocator will put the result into RAX */
4860                         amd64_ret (code);
4861                         break;
4862                 }
4863                 case OP_GET_EX_OBJ:
4864                         if (ins->dreg != AMD64_RAX)
4865                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4866                         break;
4867                 case OP_LABEL:
4868                         ins->inst_c0 = code - cfg->native_code;
4869                         break;
4870                 case OP_BR:
4871                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4872                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4873                         //break;
4874                                 if (ins->inst_target_bb->native_offset) {
4875                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4876                                 } else {
4877                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4878                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4879                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4880                                                 x86_jump8 (code, 0);
4881                                         else
4882                                                 x86_jump32 (code, 0);
4883                         }
4884                         break;
4885                 case OP_BR_REG:
4886                         amd64_jump_reg (code, ins->sreg1);
4887                         break;
4888                 case OP_ICNEQ:
4889                 case OP_ICGE:
4890                 case OP_ICLE:
4891                 case OP_ICGE_UN:
4892                 case OP_ICLE_UN:
4893
4894                 case OP_CEQ:
4895                 case OP_LCEQ:
4896                 case OP_ICEQ:
4897                 case OP_CLT:
4898                 case OP_LCLT:
4899                 case OP_ICLT:
4900                 case OP_CGT:
4901                 case OP_ICGT:
4902                 case OP_LCGT:
4903                 case OP_CLT_UN:
4904                 case OP_LCLT_UN:
4905                 case OP_ICLT_UN:
4906                 case OP_CGT_UN:
4907                 case OP_LCGT_UN:
4908                 case OP_ICGT_UN:
4909                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4910                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4911                         break;
4912                 case OP_COND_EXC_EQ:
4913                 case OP_COND_EXC_NE_UN:
4914                 case OP_COND_EXC_LT:
4915                 case OP_COND_EXC_LT_UN:
4916                 case OP_COND_EXC_GT:
4917                 case OP_COND_EXC_GT_UN:
4918                 case OP_COND_EXC_GE:
4919                 case OP_COND_EXC_GE_UN:
4920                 case OP_COND_EXC_LE:
4921                 case OP_COND_EXC_LE_UN:
4922                 case OP_COND_EXC_IEQ:
4923                 case OP_COND_EXC_INE_UN:
4924                 case OP_COND_EXC_ILT:
4925                 case OP_COND_EXC_ILT_UN:
4926                 case OP_COND_EXC_IGT:
4927                 case OP_COND_EXC_IGT_UN:
4928                 case OP_COND_EXC_IGE:
4929                 case OP_COND_EXC_IGE_UN:
4930                 case OP_COND_EXC_ILE:
4931                 case OP_COND_EXC_ILE_UN:
4932                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4933                         break;
4934                 case OP_COND_EXC_OV:
4935                 case OP_COND_EXC_NO:
4936                 case OP_COND_EXC_C:
4937                 case OP_COND_EXC_NC:
4938                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4939                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4940                         break;
4941                 case OP_COND_EXC_IOV:
4942                 case OP_COND_EXC_INO:
4943                 case OP_COND_EXC_IC:
4944                 case OP_COND_EXC_INC:
4945                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4946                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4947                         break;
4948
4949                 /* floating point opcodes */
4950                 case OP_R8CONST: {
4951                         double d = *(double *)ins->inst_p0;
4952
4953                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4954                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4955                         }
4956                         else {
4957                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4958                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4959                         }
4960                         break;
4961                 }
4962                 case OP_R4CONST: {
4963                         float f = *(float *)ins->inst_p0;
4964
4965                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4966                                 if (cfg->r4fp)
4967                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4968                                 else
4969                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4970                         }
4971                         else {
4972                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4973                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4974                                 if (!cfg->r4fp)
4975                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4976                         }
4977                         break;
4978                 }
4979                 case OP_STORER8_MEMBASE_REG:
4980                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4981                         break;
4982                 case OP_LOADR8_MEMBASE:
4983                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4984                         break;
4985                 case OP_STORER4_MEMBASE_REG:
4986                         if (cfg->r4fp) {
4987                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4988                         } else {
4989                                 /* This requires a double->single conversion */
4990                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
4991                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
4992                         }
4993                         break;
4994                 case OP_LOADR4_MEMBASE:
4995                         if (cfg->r4fp) {
4996                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4997                         } else {
4998                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4999                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5000                         }
5001                         break;
5002                 case OP_ICONV_TO_R4:
5003                         if (cfg->r4fp) {
5004                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5005                         } else {
5006                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5007                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5008                         }
5009                         break;
5010                 case OP_ICONV_TO_R8:
5011                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5012                         break;
5013                 case OP_LCONV_TO_R4:
5014                         if (cfg->r4fp) {
5015                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5016                         } else {
5017                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5018                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5019                         }
5020                         break;
5021                 case OP_LCONV_TO_R8:
5022                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5023                         break;
5024                 case OP_FCONV_TO_R4:
5025                         if (cfg->r4fp) {
5026                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5027                         } else {
5028                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5029                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5030                         }
5031                         break;
5032                 case OP_FCONV_TO_I1:
5033                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5034                         break;
5035                 case OP_FCONV_TO_U1:
5036                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5037                         break;
5038                 case OP_FCONV_TO_I2:
5039                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5040                         break;
5041                 case OP_FCONV_TO_U2:
5042                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5043                         break;
5044                 case OP_FCONV_TO_U4:
5045                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5046                         break;
5047                 case OP_FCONV_TO_I4:
5048                 case OP_FCONV_TO_I:
5049                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5050                         break;
5051                 case OP_FCONV_TO_I8:
5052                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5053                         break;
5054
5055                 case OP_RCONV_TO_I1:
5056                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5057                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5058                         break;
5059                 case OP_RCONV_TO_U1:
5060                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5061                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5062                         break;
5063                 case OP_RCONV_TO_I2:
5064                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5065                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5066                         break;
5067                 case OP_RCONV_TO_U2:
5068                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5069                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5070                         break;
5071                 case OP_RCONV_TO_I4:
5072                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5073                         break;
5074                 case OP_RCONV_TO_U4:
5075                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5076                         break;
5077                 case OP_RCONV_TO_I8:
5078                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5079                         break;
5080                 case OP_RCONV_TO_R8:
5081                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5082                         break;
5083                 case OP_RCONV_TO_R4:
5084                         if (ins->dreg != ins->sreg1)
5085                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5086                         break;
5087
5088                 case OP_LCONV_TO_R_UN: {
5089                         guint8 *br [2];
5090
5091                         /* Based on gcc code */
5092                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5093                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5094
5095                         /* Positive case */
5096                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5097                         br [1] = code; x86_jump8 (code, 0);
5098                         amd64_patch (br [0], code);
5099
5100                         /* Negative case */
5101                         /* Save to the red zone */
5102                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5103                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5104                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5105                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5106                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5107                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5108                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5109                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5110                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5111                         /* Restore */
5112                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5113                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5114                         amd64_patch (br [1], code);
5115                         break;
5116                 }
5117                 case OP_LCONV_TO_OVF_U4:
5118                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5119                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5120                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5121                         break;
5122                 case OP_LCONV_TO_OVF_I4_UN:
5123                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5124                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5125                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5126                         break;
5127                 case OP_FMOVE:
5128                         if (ins->dreg != ins->sreg1)
5129                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5130                         break;
5131                 case OP_RMOVE:
5132                         if (ins->dreg != ins->sreg1)
5133                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5134                         break;
5135                 case OP_MOVE_F_TO_I4:
5136                         if (cfg->r4fp) {
5137                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5138                         } else {
5139                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5140                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5141                         }
5142                         break;
5143                 case OP_MOVE_I4_TO_F:
5144                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5145                         if (!cfg->r4fp)
5146                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5147                         break;
5148                 case OP_MOVE_F_TO_I8:
5149                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5150                         break;
5151                 case OP_MOVE_I8_TO_F:
5152                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5153                         break;
5154                 case OP_FADD:
5155                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5156                         break;
5157                 case OP_FSUB:
5158                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5159                         break;
5160                 case OP_FMUL:
5161                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5162                         break;
5163                 case OP_FDIV:
5164                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5165                         break;
5166                 case OP_FNEG: {
5167                         static double r8_0 = -0.0;
5168
5169                         g_assert (ins->sreg1 == ins->dreg);
5170
5171                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5172                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5173                         break;
5174                 }
5175                 case OP_SIN:
5176                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5177                         break;
5178                 case OP_COS:
5179                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5180                         break;
5181                 case OP_ABS: {
5182                         static guint64 d = 0x7fffffffffffffffUL;
5183
5184                         g_assert (ins->sreg1 == ins->dreg);
5185
5186                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5187                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5188                         break;
5189                 }
5190                 case OP_SQRT:
5191                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5192                         break;
5193
5194                 case OP_RADD:
5195                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5196                         break;
5197                 case OP_RSUB:
5198                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5199                         break;
5200                 case OP_RMUL:
5201                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5202                         break;
5203                 case OP_RDIV:
5204                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5205                         break;
5206                 case OP_RNEG: {
5207                         static float r4_0 = -0.0;
5208
5209                         g_assert (ins->sreg1 == ins->dreg);
5210
5211                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5212                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5213                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5214                         break;
5215                 }
5216
5217                 case OP_IMIN:
5218                         g_assert (cfg->opt & MONO_OPT_CMOV);
5219                         g_assert (ins->dreg == ins->sreg1);
5220                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5221                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5222                         break;
5223                 case OP_IMIN_UN:
5224                         g_assert (cfg->opt & MONO_OPT_CMOV);
5225                         g_assert (ins->dreg == ins->sreg1);
5226                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5227                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5228                         break;
5229                 case OP_IMAX:
5230                         g_assert (cfg->opt & MONO_OPT_CMOV);
5231                         g_assert (ins->dreg == ins->sreg1);
5232                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5233                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5234                         break;
5235                 case OP_IMAX_UN:
5236                         g_assert (cfg->opt & MONO_OPT_CMOV);
5237                         g_assert (ins->dreg == ins->sreg1);
5238                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5239                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5240                         break;
5241                 case OP_LMIN:
5242                         g_assert (cfg->opt & MONO_OPT_CMOV);
5243                         g_assert (ins->dreg == ins->sreg1);
5244                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5245                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5246                         break;
5247                 case OP_LMIN_UN:
5248                         g_assert (cfg->opt & MONO_OPT_CMOV);
5249                         g_assert (ins->dreg == ins->sreg1);
5250                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5251                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5252                         break;
5253                 case OP_LMAX:
5254                         g_assert (cfg->opt & MONO_OPT_CMOV);
5255                         g_assert (ins->dreg == ins->sreg1);
5256                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5257                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5258                         break;
5259                 case OP_LMAX_UN:
5260                         g_assert (cfg->opt & MONO_OPT_CMOV);
5261                         g_assert (ins->dreg == ins->sreg1);
5262                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5263                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5264                         break;
5265                 case OP_X86_FPOP:
5266                         break;
5267                 case OP_FCOMPARE:
5268                         /*
5269                          * The two arguments are swapped because the fbranch instructions
5270                          * depend on this for the non-sse case to work.
5271                          */
5272                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5273                         break;
5274                 case OP_RCOMPARE:
5275                         /*
5276                          * FIXME: Get rid of this.
5277                          * The two arguments are swapped because the fbranch instructions
5278                          * depend on this for the non-sse case to work.
5279                          */
5280                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5281                         break;
5282                 case OP_FCNEQ:
5283                 case OP_FCEQ: {
5284                         /* zeroing the register at the start results in
5285                          * shorter and faster code (we can also remove the widening op)
5286                          */
5287                         guchar *unordered_check;
5288
5289                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5290                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5291                         unordered_check = code;
5292                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5293
5294                         if (ins->opcode == OP_FCEQ) {
5295                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5296                                 amd64_patch (unordered_check, code);
5297                         } else {
5298                                 guchar *jump_to_end;
5299                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5300                                 jump_to_end = code;
5301                                 x86_jump8 (code, 0);
5302                                 amd64_patch (unordered_check, code);
5303                                 amd64_inc_reg (code, ins->dreg);
5304                                 amd64_patch (jump_to_end, code);
5305                         }
5306                         break;
5307                 }
5308                 case OP_FCLT:
5309                 case OP_FCLT_UN: {
5310                         /* zeroing the register at the start results in
5311                          * shorter and faster code (we can also remove the widening op)
5312                          */
5313                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5314                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5315                         if (ins->opcode == OP_FCLT_UN) {
5316                                 guchar *unordered_check = code;
5317                                 guchar *jump_to_end;
5318                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5319                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5320                                 jump_to_end = code;
5321                                 x86_jump8 (code, 0);
5322                                 amd64_patch (unordered_check, code);
5323                                 amd64_inc_reg (code, ins->dreg);
5324                                 amd64_patch (jump_to_end, code);
5325                         } else {
5326                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5327                         }
5328                         break;
5329                 }
5330                 case OP_FCLE: {
5331                         guchar *unordered_check;
5332                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5333                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5334                         unordered_check = code;
5335                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5336                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5337                         amd64_patch (unordered_check, code);
5338                         break;
5339                 }
5340                 case OP_FCGT:
5341                 case OP_FCGT_UN: {
5342                         /* zeroing the register at the start results in
5343                          * shorter and faster code (we can also remove the widening op)
5344                          */
5345                         guchar *unordered_check;
5346
5347                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5348                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5349                         if (ins->opcode == OP_FCGT) {
5350                                 unordered_check = code;
5351                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5352                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5353                                 amd64_patch (unordered_check, code);
5354                         } else {
5355                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5356                         }
5357                         break;
5358                 }
5359                 case OP_FCGE: {
5360                         guchar *unordered_check;
5361                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5362                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5363                         unordered_check = code;
5364                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5365                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5366                         amd64_patch (unordered_check, code);
5367                         break;
5368                 }
5369
5370                 case OP_RCEQ:
5371                 case OP_RCGT:
5372                 case OP_RCLT:
5373                 case OP_RCLT_UN:
5374                 case OP_RCGT_UN: {
5375                         int x86_cond;
5376                         gboolean unordered = FALSE;
5377
5378                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5379                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5380
5381                         switch (ins->opcode) {
5382                         case OP_RCEQ:
5383                                 x86_cond = X86_CC_EQ;
5384                                 break;
5385                         case OP_RCGT:
5386                                 x86_cond = X86_CC_LT;
5387                                 break;
5388                         case OP_RCLT:
5389                                 x86_cond = X86_CC_GT;
5390                                 break;
5391                         case OP_RCLT_UN:
5392                                 x86_cond = X86_CC_GT;
5393                                 unordered = TRUE;
5394                                 break;
5395                         case OP_RCGT_UN:
5396                                 x86_cond = X86_CC_LT;
5397                                 unordered = TRUE;
5398                                 break;
5399                         default:
5400                                 g_assert_not_reached ();
5401                                 break;
5402                         }
5403
5404                         if (unordered) {
5405                                 guchar *unordered_check;
5406                                 guchar *jump_to_end;
5407
5408                                 unordered_check = code;
5409                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5410                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5411                                 jump_to_end = code;
5412                                 x86_jump8 (code, 0);
5413                                 amd64_patch (unordered_check, code);
5414                                 amd64_inc_reg (code, ins->dreg);
5415                                 amd64_patch (jump_to_end, code);
5416                         } else {
5417                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5418                         }
5419                         break;
5420                 }
5421                 case OP_FCLT_MEMBASE:
5422                 case OP_FCGT_MEMBASE:
5423                 case OP_FCLT_UN_MEMBASE:
5424                 case OP_FCGT_UN_MEMBASE:
5425                 case OP_FCEQ_MEMBASE: {
5426                         guchar *unordered_check, *jump_to_end;
5427                         int x86_cond;
5428
5429                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5430                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5431
5432                         switch (ins->opcode) {
5433                         case OP_FCEQ_MEMBASE:
5434                                 x86_cond = X86_CC_EQ;
5435                                 break;
5436                         case OP_FCLT_MEMBASE:
5437                         case OP_FCLT_UN_MEMBASE:
5438                                 x86_cond = X86_CC_LT;
5439                                 break;
5440                         case OP_FCGT_MEMBASE:
5441                         case OP_FCGT_UN_MEMBASE:
5442                                 x86_cond = X86_CC_GT;
5443                                 break;
5444                         default:
5445                                 g_assert_not_reached ();
5446                         }
5447
5448                         unordered_check = code;
5449                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5450                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5451
5452                         switch (ins->opcode) {
5453                         case OP_FCEQ_MEMBASE:
5454                         case OP_FCLT_MEMBASE:
5455                         case OP_FCGT_MEMBASE:
5456                                 amd64_patch (unordered_check, code);
5457                                 break;
5458                         case OP_FCLT_UN_MEMBASE:
5459                         case OP_FCGT_UN_MEMBASE:
5460                                 jump_to_end = code;
5461                                 x86_jump8 (code, 0);
5462                                 amd64_patch (unordered_check, code);
5463                                 amd64_inc_reg (code, ins->dreg);
5464                                 amd64_patch (jump_to_end, code);
5465                                 break;
5466                         default:
5467                                 break;
5468                         }
5469                         break;
5470                 }
5471                 case OP_FBEQ: {
5472                         guchar *jump = code;
5473                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5474                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5475                         amd64_patch (jump, code);
5476                         break;
5477                 }
5478                 case OP_FBNE_UN:
5479                         /* Branch if C013 != 100 */
5480                         /* branch if !ZF or (PF|CF) */
5481                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5482                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5483                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5484                         break;
5485                 case OP_FBLT:
5486                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5487                         break;
5488                 case OP_FBLT_UN:
5489                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5490                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5491                         break;
5492                 case OP_FBGT:
5493                 case OP_FBGT_UN:
5494                         if (ins->opcode == OP_FBGT) {
5495                                 guchar *br1;
5496
5497                                 /* skip branch if C1=1 */
5498                                 br1 = code;
5499                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5500                                 /* branch if (C0 | C3) = 1 */
5501                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5502                                 amd64_patch (br1, code);
5503                                 break;
5504                         } else {
5505                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5506                         }
5507                         break;
5508                 case OP_FBGE: {
5509                         /* Branch if C013 == 100 or 001 */
5510                         guchar *br1;
5511
5512                         /* skip branch if C1=1 */
5513                         br1 = code;
5514                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5515                         /* branch if (C0 | C3) = 1 */
5516                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5517                         amd64_patch (br1, code);
5518                         break;
5519                 }
5520                 case OP_FBGE_UN:
5521                         /* Branch if C013 == 000 */
5522                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5523                         break;
5524                 case OP_FBLE: {
5525                         /* Branch if C013=000 or 100 */
5526                         guchar *br1;
5527
5528                         /* skip branch if C1=1 */
5529                         br1 = code;
5530                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5531                         /* branch if C0=0 */
5532                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5533                         amd64_patch (br1, code);
5534                         break;
5535                 }
5536                 case OP_FBLE_UN:
5537                         /* Branch if C013 != 001 */
5538                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5539                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5540                         break;
5541                 case OP_CKFINITE:
5542                         /* Transfer value to the fp stack */
5543                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5544                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5545                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5546
5547                         amd64_push_reg (code, AMD64_RAX);
5548                         amd64_fxam (code);
5549                         amd64_fnstsw (code);
5550                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5551                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5552                         amd64_pop_reg (code, AMD64_RAX);
5553                         amd64_fstp (code, 0);
5554                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5555                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5556                         break;
5557                 case OP_TLS_GET: {
5558                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5559                         break;
5560                 }
5561                 case OP_TLS_SET: {
5562                         code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5563                         break;
5564                 }
5565                 case OP_MEMORY_BARRIER: {
5566                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5567                                 x86_mfence (code);
5568                         break;
5569                 }
5570                 case OP_ATOMIC_ADD_I4:
5571                 case OP_ATOMIC_ADD_I8: {
5572                         int dreg = ins->dreg;
5573                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5574
5575                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5576                                 dreg = AMD64_R11;
5577
5578                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5579                         amd64_prefix (code, X86_LOCK_PREFIX);
5580                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5581                         /* dreg contains the old value, add with sreg2 value */
5582                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5583
5584                         if (ins->dreg != dreg)
5585                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5586
5587                         break;
5588                 }
5589                 case OP_ATOMIC_EXCHANGE_I4:
5590                 case OP_ATOMIC_EXCHANGE_I8: {
5591                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5592
5593                         /* LOCK prefix is implied. */
5594                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5595                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5596                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5597                         break;
5598                 }
5599                 case OP_ATOMIC_CAS_I4:
5600                 case OP_ATOMIC_CAS_I8: {
5601                         guint32 size;
5602
5603                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5604                                 size = 8;
5605                         else
5606                                 size = 4;
5607
5608                         /*
5609                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5610                          * an explanation of how this works.
5611                          */
5612                         g_assert (ins->sreg3 == AMD64_RAX);
5613                         g_assert (ins->sreg1 != AMD64_RAX);
5614                         g_assert (ins->sreg1 != ins->sreg2);
5615
5616                         amd64_prefix (code, X86_LOCK_PREFIX);
5617                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5618
5619                         if (ins->dreg != AMD64_RAX)
5620                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5621                         break;
5622                 }
5623                 case OP_ATOMIC_LOAD_I1: {
5624                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5625                         break;
5626                 }
5627                 case OP_ATOMIC_LOAD_U1: {
5628                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5629                         break;
5630                 }
5631                 case OP_ATOMIC_LOAD_I2: {
5632                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5633                         break;
5634                 }
5635                 case OP_ATOMIC_LOAD_U2: {
5636                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5637                         break;
5638                 }
5639                 case OP_ATOMIC_LOAD_I4: {
5640                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5641                         break;
5642                 }
5643                 case OP_ATOMIC_LOAD_U4:
5644                 case OP_ATOMIC_LOAD_I8:
5645                 case OP_ATOMIC_LOAD_U8: {
5646                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5647                         break;
5648                 }
5649                 case OP_ATOMIC_LOAD_R4: {
5650                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5651                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5652                         break;
5653                 }
5654                 case OP_ATOMIC_LOAD_R8: {
5655                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5656                         break;
5657                 }
5658                 case OP_ATOMIC_STORE_I1:
5659                 case OP_ATOMIC_STORE_U1:
5660                 case OP_ATOMIC_STORE_I2:
5661                 case OP_ATOMIC_STORE_U2:
5662                 case OP_ATOMIC_STORE_I4:
5663                 case OP_ATOMIC_STORE_U4:
5664                 case OP_ATOMIC_STORE_I8:
5665                 case OP_ATOMIC_STORE_U8: {
5666                         int size;
5667
5668                         switch (ins->opcode) {
5669                         case OP_ATOMIC_STORE_I1:
5670                         case OP_ATOMIC_STORE_U1:
5671                                 size = 1;
5672                                 break;
5673                         case OP_ATOMIC_STORE_I2:
5674                         case OP_ATOMIC_STORE_U2:
5675                                 size = 2;
5676                                 break;
5677                         case OP_ATOMIC_STORE_I4:
5678                         case OP_ATOMIC_STORE_U4:
5679                                 size = 4;
5680                                 break;
5681                         case OP_ATOMIC_STORE_I8:
5682                         case OP_ATOMIC_STORE_U8:
5683                                 size = 8;
5684                                 break;
5685                         }
5686
5687                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5688
5689                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5690                                 x86_mfence (code);
5691                         break;
5692                 }
5693                 case OP_ATOMIC_STORE_R4: {
5694                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5695                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5696
5697                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5698                                 x86_mfence (code);
5699                         break;
5700                 }
5701                 case OP_ATOMIC_STORE_R8: {
5702                         x86_nop (code);
5703                         x86_nop (code);
5704                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5705                         x86_nop (code);
5706                         x86_nop (code);
5707
5708                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5709                                 x86_mfence (code);
5710                         break;
5711                 }
5712                 case OP_CARD_TABLE_WBARRIER: {
5713                         int ptr = ins->sreg1;
5714                         int value = ins->sreg2;
5715                         guchar *br = 0;
5716                         int nursery_shift, card_table_shift;
5717                         gpointer card_table_mask;
5718                         size_t nursery_size;
5719
5720                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5721                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5722                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5723
5724                         /*If either point to the stack we can simply avoid the WB. This happens due to
5725                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5726                          */
5727                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5728                                 continue;
5729
5730                         /*
5731                          * We need one register we can clobber, we choose EDX and make sreg1
5732                          * fixed EAX to work around limitations in the local register allocator.
5733                          * sreg2 might get allocated to EDX, but that is not a problem since
5734                          * we use it before clobbering EDX.
5735                          */
5736                         g_assert (ins->sreg1 == AMD64_RAX);
5737
5738                         /*
5739                          * This is the code we produce:
5740                          *
5741                          *   edx = value
5742                          *   edx >>= nursery_shift
5743                          *   cmp edx, (nursery_start >> nursery_shift)
5744                          *   jne done
5745                          *   edx = ptr
5746                          *   edx >>= card_table_shift
5747                          *   edx += cardtable
5748                          *   [edx] = 1
5749                          * done:
5750                          */
5751
5752                         if (mono_gc_card_table_nursery_check ()) {
5753                                 if (value != AMD64_RDX)
5754                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5755                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5756                                 if (shifted_nursery_start >> 31) {
5757                                         /*
5758                                          * The value we need to compare against is 64 bits, so we need
5759                                          * another spare register.  We use RBX, which we save and
5760                                          * restore.
5761                                          */
5762                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5763                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5764                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5765                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5766                                 } else {
5767                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5768                                 }
5769                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5770                         }
5771                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5772                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5773                         if (card_table_mask)
5774                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5775
5776                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5777                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5778
5779                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5780
5781                         if (mono_gc_card_table_nursery_check ())
5782                                 x86_patch (br, code);
5783                         break;
5784                 }
5785 #ifdef MONO_ARCH_SIMD_INTRINSICS
5786                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5787                 case OP_ADDPS:
5788                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5789                         break;
5790                 case OP_DIVPS:
5791                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5792                         break;
5793                 case OP_MULPS:
5794                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5795                         break;
5796                 case OP_SUBPS:
5797                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5798                         break;
5799                 case OP_MAXPS:
5800                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5801                         break;
5802                 case OP_MINPS:
5803                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5804                         break;
5805                 case OP_COMPPS:
5806                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5807                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5808                         break;
5809                 case OP_ANDPS:
5810                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5811                         break;
5812                 case OP_ANDNPS:
5813                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5814                         break;
5815                 case OP_ORPS:
5816                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5817                         break;
5818                 case OP_XORPS:
5819                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5820                         break;
5821                 case OP_SQRTPS:
5822                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5823                         break;
5824                 case OP_RSQRTPS:
5825                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5826                         break;
5827                 case OP_RCPPS:
5828                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5829                         break;
5830                 case OP_ADDSUBPS:
5831                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5832                         break;
5833                 case OP_HADDPS:
5834                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5835                         break;
5836                 case OP_HSUBPS:
5837                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5838                         break;
5839                 case OP_DUPPS_HIGH:
5840                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5841                         break;
5842                 case OP_DUPPS_LOW:
5843                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5844                         break;
5845
5846                 case OP_PSHUFLEW_HIGH:
5847                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5848                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5849                         break;
5850                 case OP_PSHUFLEW_LOW:
5851                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5852                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5853                         break;
5854                 case OP_PSHUFLED:
5855                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5856                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5857                         break;
5858                 case OP_SHUFPS:
5859                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5860                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5861                         break;
5862                 case OP_SHUFPD:
5863                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5864                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5865                         break;
5866
5867                 case OP_ADDPD:
5868                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5869                         break;
5870                 case OP_DIVPD:
5871                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5872                         break;
5873                 case OP_MULPD:
5874                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5875                         break;
5876                 case OP_SUBPD:
5877                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5878                         break;
5879                 case OP_MAXPD:
5880                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5881                         break;
5882                 case OP_MINPD:
5883                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5884                         break;
5885                 case OP_COMPPD:
5886                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5887                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5888                         break;
5889                 case OP_ANDPD:
5890                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5891                         break;
5892                 case OP_ANDNPD:
5893                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5894                         break;
5895                 case OP_ORPD:
5896                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5897                         break;
5898                 case OP_XORPD:
5899                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5900                         break;
5901                 case OP_SQRTPD:
5902                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5903                         break;
5904                 case OP_ADDSUBPD:
5905                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5906                         break;
5907                 case OP_HADDPD:
5908                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5909                         break;
5910                 case OP_HSUBPD:
5911                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5912                         break;
5913                 case OP_DUPPD:
5914                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5915                         break;
5916
5917                 case OP_EXTRACT_MASK:
5918                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5919                         break;
5920
5921                 case OP_PAND:
5922                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5923                         break;
5924                 case OP_POR:
5925                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5926                         break;
5927                 case OP_PXOR:
5928                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5929                         break;
5930
5931                 case OP_PADDB:
5932                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5933                         break;
5934                 case OP_PADDW:
5935                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5936                         break;
5937                 case OP_PADDD:
5938                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5939                         break;
5940                 case OP_PADDQ:
5941                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5942                         break;
5943
5944                 case OP_PSUBB:
5945                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5946                         break;
5947                 case OP_PSUBW:
5948                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5949                         break;
5950                 case OP_PSUBD:
5951                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5952                         break;
5953                 case OP_PSUBQ:
5954                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5955                         break;
5956
5957                 case OP_PMAXB_UN:
5958                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5959                         break;
5960                 case OP_PMAXW_UN:
5961                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5962                         break;
5963                 case OP_PMAXD_UN:
5964                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5965                         break;
5966
5967                 case OP_PMAXB:
5968                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5969                         break;
5970                 case OP_PMAXW:
5971                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5972                         break;
5973                 case OP_PMAXD:
5974                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5975                         break;
5976
5977                 case OP_PAVGB_UN:
5978                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5979                         break;
5980                 case OP_PAVGW_UN:
5981                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5982                         break;
5983
5984                 case OP_PMINB_UN:
5985                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5986                         break;
5987                 case OP_PMINW_UN:
5988                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5989                         break;
5990                 case OP_PMIND_UN:
5991                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5992                         break;
5993
5994                 case OP_PMINB:
5995                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5996                         break;
5997                 case OP_PMINW:
5998                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5999                         break;
6000                 case OP_PMIND:
6001                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6002                         break;
6003
6004                 case OP_PCMPEQB:
6005                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007                 case OP_PCMPEQW:
6008                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6009                         break;
6010                 case OP_PCMPEQD:
6011                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6012                         break;
6013                 case OP_PCMPEQQ:
6014                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6015                         break;
6016
6017                 case OP_PCMPGTB:
6018                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6019                         break;
6020                 case OP_PCMPGTW:
6021                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6022                         break;
6023                 case OP_PCMPGTD:
6024                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6025                         break;
6026                 case OP_PCMPGTQ:
6027                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6028                         break;
6029
6030                 case OP_PSUM_ABS_DIFF:
6031                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6032                         break;
6033
6034                 case OP_UNPACK_LOWB:
6035                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_UNPACK_LOWW:
6038                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040                 case OP_UNPACK_LOWD:
6041                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043                 case OP_UNPACK_LOWQ:
6044                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6045                         break;
6046                 case OP_UNPACK_LOWPS:
6047                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049                 case OP_UNPACK_LOWPD:
6050                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6051                         break;
6052
6053                 case OP_UNPACK_HIGHB:
6054                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6055                         break;
6056                 case OP_UNPACK_HIGHW:
6057                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6058                         break;
6059                 case OP_UNPACK_HIGHD:
6060                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062                 case OP_UNPACK_HIGHQ:
6063                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6064                         break;
6065                 case OP_UNPACK_HIGHPS:
6066                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6067                         break;
6068                 case OP_UNPACK_HIGHPD:
6069                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6070                         break;
6071
6072                 case OP_PACKW:
6073                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6074                         break;
6075                 case OP_PACKD:
6076                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6077                         break;
6078                 case OP_PACKW_UN:
6079                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6080                         break;
6081                 case OP_PACKD_UN:
6082                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6083                         break;
6084
6085                 case OP_PADDB_SAT_UN:
6086                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6087                         break;
6088                 case OP_PSUBB_SAT_UN:
6089                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6090                         break;
6091                 case OP_PADDW_SAT_UN:
6092                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6093                         break;
6094                 case OP_PSUBW_SAT_UN:
6095                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6096                         break;
6097
6098                 case OP_PADDB_SAT:
6099                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6100                         break;
6101                 case OP_PSUBB_SAT:
6102                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6103                         break;
6104                 case OP_PADDW_SAT:
6105                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6106                         break;
6107                 case OP_PSUBW_SAT:
6108                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6109                         break;
6110
6111                 case OP_PMULW:
6112                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114                 case OP_PMULD:
6115                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6116                         break;
6117                 case OP_PMULQ:
6118                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6119                         break;
6120                 case OP_PMULW_HIGH_UN:
6121                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6122                         break;
6123                 case OP_PMULW_HIGH:
6124                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6125                         break;
6126
6127                 case OP_PSHRW:
6128                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6129                         break;
6130                 case OP_PSHRW_REG:
6131                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6132                         break;
6133
6134                 case OP_PSARW:
6135                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6136                         break;
6137                 case OP_PSARW_REG:
6138                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6139                         break;
6140
6141                 case OP_PSHLW:
6142                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6143                         break;
6144                 case OP_PSHLW_REG:
6145                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6146                         break;
6147
6148                 case OP_PSHRD:
6149                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6150                         break;
6151                 case OP_PSHRD_REG:
6152                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6153                         break;
6154
6155                 case OP_PSARD:
6156                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6157                         break;
6158                 case OP_PSARD_REG:
6159                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6160                         break;
6161
6162                 case OP_PSHLD:
6163                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6164                         break;
6165                 case OP_PSHLD_REG:
6166                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6167                         break;
6168
6169                 case OP_PSHRQ:
6170                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6171                         break;
6172                 case OP_PSHRQ_REG:
6173                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6174                         break;
6175
6176                 /*TODO: This is appart of the sse spec but not added
6177                 case OP_PSARQ:
6178                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6179                         break;
6180                 case OP_PSARQ_REG:
6181                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6182                         break;
6183                 */
6184
6185                 case OP_PSHLQ:
6186                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6187                         break;
6188                 case OP_PSHLQ_REG:
6189                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6190                         break;
6191                 case OP_CVTDQ2PD:
6192                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6193                         break;
6194                 case OP_CVTDQ2PS:
6195                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6196                         break;
6197                 case OP_CVTPD2DQ:
6198                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6199                         break;
6200                 case OP_CVTPD2PS:
6201                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6202                         break;
6203                 case OP_CVTPS2DQ:
6204                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6205                         break;
6206                 case OP_CVTPS2PD:
6207                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6208                         break;
6209                 case OP_CVTTPD2DQ:
6210                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6211                         break;
6212                 case OP_CVTTPS2DQ:
6213                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6214                         break;
6215
6216                 case OP_ICONV_TO_X:
6217                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6218                         break;
6219                 case OP_EXTRACT_I4:
6220                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6221                         break;
6222                 case OP_EXTRACT_I8:
6223                         if (ins->inst_c0) {
6224                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6225                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6226                         } else {
6227                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6228                         }
6229                         break;
6230                 case OP_EXTRACT_I1:
6231                 case OP_EXTRACT_U1:
6232                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6233                         if (ins->inst_c0)
6234                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6235                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6236                         break;
6237                 case OP_EXTRACT_I2:
6238                 case OP_EXTRACT_U2:
6239                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6240                         if (ins->inst_c0)
6241                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6242                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6243                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6244                         break;
6245                 case OP_EXTRACT_R8:
6246                         if (ins->inst_c0)
6247                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6248                         else
6249                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6250                         break;
6251                 case OP_INSERT_I2:
6252                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6253                         break;
6254                 case OP_EXTRACTX_U2:
6255                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6256                         break;
6257                 case OP_INSERTX_U1_SLOW:
6258                         /*sreg1 is the extracted ireg (scratch)
6259                         /sreg2 is the to be inserted ireg (scratch)
6260                         /dreg is the xreg to receive the value*/
6261
6262                         /*clear the bits from the extracted word*/
6263                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6264                         /*shift the value to insert if needed*/
6265                         if (ins->inst_c0 & 1)
6266                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6267                         /*join them together*/
6268                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6269                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6270                         break;
6271                 case OP_INSERTX_I4_SLOW:
6272                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6273                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6274                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6275                         break;
6276                 case OP_INSERTX_I8_SLOW:
6277                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6278                         if (ins->inst_c0)
6279                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6280                         else
6281                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6282                         break;
6283
6284                 case OP_INSERTX_R4_SLOW:
6285                         switch (ins->inst_c0) {
6286                         case 0:
6287                                 if (cfg->r4fp)
6288                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6289                                 else
6290                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6291                                 break;
6292                         case 1:
6293                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6294                                 if (cfg->r4fp)
6295                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6296                                 else
6297                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6298                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6299                                 break;
6300                         case 2:
6301                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6302                                 if (cfg->r4fp)
6303                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6304                                 else
6305                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6306                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6307                                 break;
6308                         case 3:
6309                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6310                                 if (cfg->r4fp)
6311                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6312                                 else
6313                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6314                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6315                                 break;
6316                         }
6317                         break;
6318                 case OP_INSERTX_R8_SLOW:
6319                         if (ins->inst_c0)
6320                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6321                         else
6322                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6323                         break;
6324                 case OP_STOREX_MEMBASE_REG:
6325                 case OP_STOREX_MEMBASE:
6326                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6327                         break;
6328                 case OP_LOADX_MEMBASE:
6329                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6330                         break;
6331                 case OP_LOADX_ALIGNED_MEMBASE:
6332                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6333                         break;
6334                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6335                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6336                         break;
6337                 case OP_STOREX_NTA_MEMBASE_REG:
6338                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6339                         break;
6340                 case OP_PREFETCH_MEMBASE:
6341                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6342                         break;
6343
6344                 case OP_XMOVE:
6345                         /*FIXME the peephole pass should have killed this*/
6346                         if (ins->dreg != ins->sreg1)
6347                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6348                         break;
6349                 case OP_XZERO:
6350                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6351                         break;
6352                 case OP_XONES:
6353                         amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6354                         break;
6355                 case OP_ICONV_TO_R4_RAW:
6356                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6357                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6358                         break;
6359
6360                 case OP_FCONV_TO_R8_X:
6361                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6362                         break;
6363
6364                 case OP_XCONV_R8_TO_I4:
6365                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6366                         switch (ins->backend.source_opcode) {
6367                         case OP_FCONV_TO_I1:
6368                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6369                                 break;
6370                         case OP_FCONV_TO_U1:
6371                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6372                                 break;
6373                         case OP_FCONV_TO_I2:
6374                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6375                                 break;
6376                         case OP_FCONV_TO_U2:
6377                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6378                                 break;
6379                         }
6380                         break;
6381
6382                 case OP_EXPAND_I2:
6383                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6384                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6385                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6386                         break;
6387                 case OP_EXPAND_I4:
6388                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6389                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6390                         break;
6391                 case OP_EXPAND_I8:
6392                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6393                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6394                         break;
6395                 case OP_EXPAND_R4:
6396                         if (cfg->r4fp) {
6397                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6398                         } else {
6399                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6400                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6401                         }
6402                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6403                         break;
6404                 case OP_EXPAND_R8:
6405                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6406                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6407                         break;
6408 #endif
6409                 case OP_LIVERANGE_START: {
6410                         if (cfg->verbose_level > 1)
6411                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6412                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6413                         break;
6414                 }
6415                 case OP_LIVERANGE_END: {
6416                         if (cfg->verbose_level > 1)
6417                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6418                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6419                         break;
6420                 }
6421                 case OP_GC_SAFE_POINT: {
6422                         guint8 *br [1];
6423
6424                         g_assert (mono_threads_is_coop_enabled ());
6425
6426                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6427                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6428                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6429                         amd64_patch (br[0], code);
6430                         break;
6431                 }
6432
6433                 case OP_GC_LIVENESS_DEF:
6434                 case OP_GC_LIVENESS_USE:
6435                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6436                         ins->backend.pc_offset = code - cfg->native_code;
6437                         break;
6438                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6439                         ins->backend.pc_offset = code - cfg->native_code;
6440                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6441                         break;
6442                 case OP_GET_LAST_ERROR:
6443                         emit_get_last_error(code, ins->dreg);
6444                         break;
6445                 default:
6446                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6447                         g_assert_not_reached ();
6448                 }
6449
6450                 if ((code - cfg->native_code - offset) > max_len) {
6451                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6452                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6453                         g_assert_not_reached ();
6454                 }
6455         }
6456
6457         cfg->code_len = code - cfg->native_code;
6458 }
6459
6460 #endif /* DISABLE_JIT */
6461
6462 void
6463 mono_arch_register_lowlevel_calls (void)
6464 {
6465         /* The signature doesn't matter */
6466         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6467 }
6468
6469 void
6470 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6471 {
6472         unsigned char *ip = ji->ip.i + code;
6473
6474         /*
6475          * Debug code to help track down problems where the target of a near call is
6476          * is not valid.
6477          */
6478         if (amd64_is_near_call (ip)) {
6479                 gint64 disp = (guint8*)target - (guint8*)ip;
6480
6481                 if (!amd64_is_imm32 (disp)) {
6482                         printf ("TYPE: %d\n", ji->type);
6483                         switch (ji->type) {
6484                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6485                                 printf ("V: %s\n", ji->data.name);
6486                                 break;
6487                         case MONO_PATCH_INFO_METHOD_JUMP:
6488                         case MONO_PATCH_INFO_METHOD:
6489                                 printf ("V: %s\n", ji->data.method->name);
6490                                 break;
6491                         default:
6492                                 break;
6493                         }
6494                 }
6495         }
6496
6497         amd64_patch (ip, (gpointer)target);
6498 }
6499
6500 #ifndef DISABLE_JIT
6501
6502 static int
6503 get_max_epilog_size (MonoCompile *cfg)
6504 {
6505         int max_epilog_size = 16;
6506
6507         if (cfg->method->save_lmf)
6508                 max_epilog_size += 256;
6509
6510         if (mono_jit_trace_calls != NULL)
6511                 max_epilog_size += 50;
6512
6513         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6514                 max_epilog_size += 50;
6515
6516         max_epilog_size += (AMD64_NREG * 2);
6517
6518         return max_epilog_size;
6519 }
6520
6521 /*
6522  * This macro is used for testing whenever the unwinder works correctly at every point
6523  * where an async exception can happen.
6524  */
6525 /* This will generate a SIGSEGV at the given point in the code */
6526 #define async_exc_point(code) do { \
6527     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6528          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6529              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6530          cfg->arch.async_point_count ++; \
6531     } \
6532 } while (0)
6533
6534 guint8 *
6535 mono_arch_emit_prolog (MonoCompile *cfg)
6536 {
6537         MonoMethod *method = cfg->method;
6538         MonoBasicBlock *bb;
6539         MonoMethodSignature *sig;
6540         MonoInst *ins;
6541         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6542         guint8 *code;
6543         CallInfo *cinfo;
6544         MonoInst *lmf_var = cfg->lmf_var;
6545         gboolean args_clobbered = FALSE;
6546         gboolean trace = FALSE;
6547
6548         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6549
6550         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6551
6552         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6553                 trace = TRUE;
6554
6555         /* Amount of stack space allocated by register saving code */
6556         pos = 0;
6557
6558         /* Offset between RSP and the CFA */
6559         cfa_offset = 0;
6560
6561         /*
6562          * The prolog consists of the following parts:
6563          * FP present:
6564          * - push rbp, mov rbp, rsp
6565          * - save callee saved regs using pushes
6566          * - allocate frame
6567          * - save rgctx if needed
6568          * - save lmf if needed
6569          * FP not present:
6570          * - allocate frame
6571          * - save rgctx if needed
6572          * - save lmf if needed
6573          * - save callee saved regs using moves
6574          */
6575
6576         // CFA = sp + 8
6577         cfa_offset = 8;
6578         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6579         // IP saved at CFA - 8
6580         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6581         async_exc_point (code);
6582         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6583
6584         if (!cfg->arch.omit_fp) {
6585                 amd64_push_reg (code, AMD64_RBP);
6586                 cfa_offset += 8;
6587                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6588                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6589                 async_exc_point (code);
6590 #ifdef TARGET_WIN32
6591                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6592 #endif
6593                 /* These are handled automatically by the stack marking code */
6594                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6595
6596                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6597                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6598                 async_exc_point (code);
6599 #ifdef TARGET_WIN32
6600                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6601 #endif
6602         }
6603
6604         /* The param area is always at offset 0 from sp */
6605         /* This needs to be allocated here, since it has to come after the spill area */
6606         if (cfg->param_area) {
6607                 if (cfg->arch.omit_fp)
6608                         // FIXME:
6609                         g_assert_not_reached ();
6610                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6611         }
6612
6613         if (cfg->arch.omit_fp) {
6614                 /*
6615                  * On enter, the stack is misaligned by the pushing of the return
6616                  * address. It is either made aligned by the pushing of %rbp, or by
6617                  * this.
6618                  */
6619                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6620                 if ((alloc_size % 16) == 0) {
6621                         alloc_size += 8;
6622                         /* Mark the padding slot as NOREF */
6623                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6624                 }
6625         } else {
6626                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6627                 if (cfg->stack_offset != alloc_size) {
6628                         /* Mark the padding slot as NOREF */
6629                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6630                 }
6631                 cfg->arch.sp_fp_offset = alloc_size;
6632                 alloc_size -= pos;
6633         }
6634
6635         cfg->arch.stack_alloc_size = alloc_size;
6636
6637         /* Allocate stack frame */
6638         if (alloc_size) {
6639                 /* See mono_emit_stack_alloc */
6640 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6641                 guint32 remaining_size = alloc_size;
6642                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6643                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6644                 guint32 offset = code - cfg->native_code;
6645                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6646                         while (required_code_size >= (cfg->code_size - offset))
6647                                 cfg->code_size *= 2;
6648                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6649                         code = cfg->native_code + offset;
6650                         cfg->stat_code_reallocs++;
6651                 }
6652
6653                 while (remaining_size >= 0x1000) {
6654                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6655                         if (cfg->arch.omit_fp) {
6656                                 cfa_offset += 0x1000;
6657                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6658                         }
6659                         async_exc_point (code);
6660 #ifdef TARGET_WIN32
6661                         if (cfg->arch.omit_fp)
6662                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6663 #endif
6664
6665                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6666                         remaining_size -= 0x1000;
6667                 }
6668                 if (remaining_size) {
6669                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6670                         if (cfg->arch.omit_fp) {
6671                                 cfa_offset += remaining_size;
6672                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6673                                 async_exc_point (code);
6674                         }
6675 #ifdef TARGET_WIN32
6676                         if (cfg->arch.omit_fp)
6677                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6678 #endif
6679                 }
6680 #else
6681                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6682                 if (cfg->arch.omit_fp) {
6683                         cfa_offset += alloc_size;
6684                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6685                         async_exc_point (code);
6686                 }
6687 #endif
6688         }
6689
6690         /* Stack alignment check */
6691 #if 0
6692         {
6693                 guint8 *buf;
6694
6695                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6696                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6697                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6698                 buf = code;
6699                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6700                 amd64_breakpoint (code);
6701                 amd64_patch (buf, code);
6702         }
6703 #endif
6704
6705         if (mini_get_debug_options ()->init_stacks) {
6706                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6707
6708                 /* Save registers to the red zone */
6709                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6710                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6711
6712                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6713                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6714                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6715
6716                 amd64_cld (code);
6717                 amd64_prefix (code, X86_REP_PREFIX);
6718                 amd64_stosl (code);
6719
6720                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6721                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6722         }
6723
6724         /* Save LMF */
6725         if (method->save_lmf)
6726                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6727
6728         /* Save callee saved registers */
6729         if (cfg->arch.omit_fp) {
6730                 save_area_offset = cfg->arch.reg_save_area_offset;
6731                 /* Save caller saved registers after sp is adjusted */
6732                 /* The registers are saved at the bottom of the frame */
6733                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6734         } else {
6735                 /* The registers are saved just below the saved rbp */
6736                 save_area_offset = cfg->arch.reg_save_area_offset;
6737         }
6738
6739         for (i = 0; i < AMD64_NREG; ++i) {
6740                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6741                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6742
6743                         if (cfg->arch.omit_fp) {
6744                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6745                                 /* These are handled automatically by the stack marking code */
6746                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6747                         } else {
6748                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6749                                 // FIXME: GC
6750                         }
6751
6752                         save_area_offset += 8;
6753                         async_exc_point (code);
6754                 }
6755         }
6756
6757         /* store runtime generic context */
6758         if (cfg->rgctx_var) {
6759                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6760                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6761
6762                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6763
6764                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6765                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6766         }
6767
6768         /* compute max_length in order to use short forward jumps */
6769         max_epilog_size = get_max_epilog_size (cfg);
6770         if (cfg->opt & MONO_OPT_BRANCH) {
6771                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6772                         MonoInst *ins;
6773                         int max_length = 0;
6774
6775                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6776                                 max_length += 6;
6777                         /* max alignment for loops */
6778                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6779                                 max_length += LOOP_ALIGNMENT;
6780
6781                         MONO_BB_FOR_EACH_INS (bb, ins) {
6782                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6783                         }
6784
6785                         /* Take prolog and epilog instrumentation into account */
6786                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6787                                 max_length += max_epilog_size;
6788
6789                         bb->max_length = max_length;
6790                 }
6791         }
6792
6793         sig = mono_method_signature (method);
6794         pos = 0;
6795
6796         cinfo = (CallInfo *)cfg->arch.cinfo;
6797
6798         if (sig->ret->type != MONO_TYPE_VOID) {
6799                 /* Save volatile arguments to the stack */
6800                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6801                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6802         }
6803
6804         /* Keep this in sync with emit_load_volatile_arguments */
6805         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6806                 ArgInfo *ainfo = cinfo->args + i;
6807
6808                 ins = cfg->args [i];
6809
6810                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6811                         /* Unused arguments */
6812                         continue;
6813
6814                 /* Save volatile arguments to the stack */
6815                 if (ins->opcode != OP_REGVAR) {
6816                         switch (ainfo->storage) {
6817                         case ArgInIReg: {
6818                                 guint32 size = 8;
6819
6820                                 /* FIXME: I1 etc */
6821                                 /*
6822                                 if (stack_offset & 0x1)
6823                                         size = 1;
6824                                 else if (stack_offset & 0x2)
6825                                         size = 2;
6826                                 else if (stack_offset & 0x4)
6827                                         size = 4;
6828                                 else
6829                                         size = 8;
6830                                 */
6831                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6832
6833                                 /*
6834                                  * Save the original location of 'this',
6835                                  * get_generic_info_from_stack_frame () needs this to properly look up
6836                                  * the argument value during the handling of async exceptions.
6837                                  */
6838                                 if (ins == cfg->args [0]) {
6839                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6840                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6841                                 }
6842                                 break;
6843                         }
6844                         case ArgInFloatSSEReg:
6845                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6846                                 break;
6847                         case ArgInDoubleSSEReg:
6848                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6849                                 break;
6850                         case ArgValuetypeInReg:
6851                                 for (quad = 0; quad < 2; quad ++) {
6852                                         switch (ainfo->pair_storage [quad]) {
6853                                         case ArgInIReg:
6854                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6855                                                 break;
6856                                         case ArgInFloatSSEReg:
6857                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6858                                                 break;
6859                                         case ArgInDoubleSSEReg:
6860                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6861                                                 break;
6862                                         case ArgNone:
6863                                                 break;
6864                                         default:
6865                                                 g_assert_not_reached ();
6866                                         }
6867                                 }
6868                                 break;
6869                         case ArgValuetypeAddrInIReg:
6870                                 if (ainfo->pair_storage [0] == ArgInIReg)
6871                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6872                                 break;
6873                         case ArgValuetypeAddrOnStack:
6874                                 break;
6875                         case ArgGSharedVtInReg:
6876                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6877                                 break;
6878                         default:
6879                                 break;
6880                         }
6881                 } else {
6882                         /* Argument allocated to (non-volatile) register */
6883                         switch (ainfo->storage) {
6884                         case ArgInIReg:
6885                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6886                                 break;
6887                         case ArgOnStack:
6888                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6889                                 break;
6890                         default:
6891                                 g_assert_not_reached ();
6892                         }
6893
6894                         if (ins == cfg->args [0]) {
6895                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6896                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6897                         }
6898                 }
6899         }
6900
6901         if (cfg->method->save_lmf)
6902                 args_clobbered = TRUE;
6903
6904         if (trace) {
6905                 args_clobbered = TRUE;
6906                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6907         }
6908
6909         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6910                 args_clobbered = TRUE;
6911
6912         /*
6913          * Optimize the common case of the first bblock making a call with the same
6914          * arguments as the method. This works because the arguments are still in their
6915          * original argument registers.
6916          * FIXME: Generalize this
6917          */
6918         if (!args_clobbered) {
6919                 MonoBasicBlock *first_bb = cfg->bb_entry;
6920                 MonoInst *next;
6921                 int filter = FILTER_IL_SEQ_POINT;
6922
6923                 next = mono_bb_first_inst (first_bb, filter);
6924                 if (!next && first_bb->next_bb) {
6925                         first_bb = first_bb->next_bb;
6926                         next = mono_bb_first_inst (first_bb, filter);
6927                 }
6928
6929                 if (first_bb->in_count > 1)
6930                         next = NULL;
6931
6932                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6933                         ArgInfo *ainfo = cinfo->args + i;
6934                         gboolean match = FALSE;
6935
6936                         ins = cfg->args [i];
6937                         if (ins->opcode != OP_REGVAR) {
6938                                 switch (ainfo->storage) {
6939                                 case ArgInIReg: {
6940                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6941                                                 if (next->dreg == ainfo->reg) {
6942                                                         NULLIFY_INS (next);
6943                                                         match = TRUE;
6944                                                 } else {
6945                                                         next->opcode = OP_MOVE;
6946                                                         next->sreg1 = ainfo->reg;
6947                                                         /* Only continue if the instruction doesn't change argument regs */
6948                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6949                                                                 match = TRUE;
6950                                                 }
6951                                         }
6952                                         break;
6953                                 }
6954                                 default:
6955                                         break;
6956                                 }
6957                         } else {
6958                                 /* Argument allocated to (non-volatile) register */
6959                                 switch (ainfo->storage) {
6960                                 case ArgInIReg:
6961                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6962                                                 NULLIFY_INS (next);
6963                                                 match = TRUE;
6964                                         }
6965                                         break;
6966                                 default:
6967                                         break;
6968                                 }
6969                         }
6970
6971                         if (match) {
6972                                 next = mono_inst_next (next, filter);
6973                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6974                                 if (!next)
6975                                         break;
6976                         }
6977                 }
6978         }
6979
6980         if (cfg->gen_sdb_seq_points) {
6981                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
6982
6983                 /* Initialize seq_point_info_var */
6984                 if (cfg->compile_aot) {
6985                         /* Initialize the variable from a GOT slot */
6986                         /* Same as OP_AOTCONST */
6987                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
6988                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
6989                         g_assert (info_var->opcode == OP_REGOFFSET);
6990                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
6991                 }
6992
6993                 if (cfg->compile_aot) {
6994                         /* Initialize ss_tramp_var */
6995                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
6996                         g_assert (ins->opcode == OP_REGOFFSET);
6997
6998                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
6999                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7000                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7001                 } else {
7002                         /* Initialize ss_tramp_var */
7003                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7004                         g_assert (ins->opcode == OP_REGOFFSET);
7005
7006                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7007                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7008
7009                         /* Initialize bp_tramp_var */
7010                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7011                         g_assert (ins->opcode == OP_REGOFFSET);
7012
7013                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7014                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7015                 }
7016         }
7017
7018         cfg->code_len = code - cfg->native_code;
7019
7020         g_assert (cfg->code_len < cfg->code_size);
7021
7022         return code;
7023 }
7024
7025 void
7026 mono_arch_emit_epilog (MonoCompile *cfg)
7027 {
7028         MonoMethod *method = cfg->method;
7029         int quad, i;
7030         guint8 *code;
7031         int max_epilog_size;
7032         CallInfo *cinfo;
7033         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7034         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7035
7036         max_epilog_size = get_max_epilog_size (cfg);
7037
7038         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7039                 cfg->code_size *= 2;
7040                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7041                 cfg->stat_code_reallocs++;
7042         }
7043         code = cfg->native_code + cfg->code_len;
7044
7045         cfg->has_unwind_info_for_epilog = TRUE;
7046
7047         /* Mark the start of the epilog */
7048         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7049
7050         /* Save the uwind state which is needed by the out-of-line code */
7051         mono_emit_unwind_op_remember_state (cfg, code);
7052
7053         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7054                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7055
7056         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7057
7058         if (method->save_lmf) {
7059                 /* check if we need to restore protection of the stack after a stack overflow */
7060                 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7061                         guint8 *patch;
7062                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7063                         /* we load the value in a separate instruction: this mechanism may be
7064                          * used later as a safer way to do thread interruption
7065                          */
7066                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7067                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7068                         patch = code;
7069                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7070                         /* note that the call trampoline will preserve eax/edx */
7071                         x86_call_reg (code, X86_ECX);
7072                         x86_patch (patch, code);
7073                 } else {
7074                         /* FIXME: maybe save the jit tls in the prolog */
7075                 }
7076                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7077                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7078                 }
7079         }
7080
7081         /* Restore callee saved regs */
7082         for (i = 0; i < AMD64_NREG; ++i) {
7083                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7084                         /* Restore only used_int_regs, not arch.saved_iregs */
7085 #if defined(MONO_SUPPORT_TASKLETS)
7086                         int restore_reg=1;
7087 #else
7088                         int restore_reg=(cfg->used_int_regs & (1 << i));
7089 #endif
7090                         if (restore_reg) {
7091                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7092                                 mono_emit_unwind_op_same_value (cfg, code, i);
7093                                 async_exc_point (code);
7094                         }
7095                         save_area_offset += 8;
7096                 }
7097         }
7098
7099         /* Load returned vtypes into registers if needed */
7100         cinfo = (CallInfo *)cfg->arch.cinfo;
7101         if (cinfo->ret.storage == ArgValuetypeInReg) {
7102                 ArgInfo *ainfo = &cinfo->ret;
7103                 MonoInst *inst = cfg->ret;
7104
7105                 for (quad = 0; quad < 2; quad ++) {
7106                         switch (ainfo->pair_storage [quad]) {
7107                         case ArgInIReg:
7108                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7109                                 break;
7110                         case ArgInFloatSSEReg:
7111                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7112                                 break;
7113                         case ArgInDoubleSSEReg:
7114                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7115                                 break;
7116                         case ArgNone:
7117                                 break;
7118                         default:
7119                                 g_assert_not_reached ();
7120                         }
7121                 }
7122         }
7123
7124         if (cfg->arch.omit_fp) {
7125                 if (cfg->arch.stack_alloc_size) {
7126                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7127                 }
7128         } else {
7129                 amd64_leave (code);
7130                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7131         }
7132         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7133         async_exc_point (code);
7134         amd64_ret (code);
7135
7136         /* Restore the unwind state to be the same as before the epilog */
7137         mono_emit_unwind_op_restore_state (cfg, code);
7138
7139         cfg->code_len = code - cfg->native_code;
7140
7141         g_assert (cfg->code_len < cfg->code_size);
7142 }
7143
7144 void
7145 mono_arch_emit_exceptions (MonoCompile *cfg)
7146 {
7147         MonoJumpInfo *patch_info;
7148         int nthrows, i;
7149         guint8 *code;
7150         MonoClass *exc_classes [16];
7151         guint8 *exc_throw_start [16], *exc_throw_end [16];
7152         guint32 code_size = 0;
7153
7154         /* Compute needed space */
7155         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7156                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7157                         code_size += 40;
7158                 if (patch_info->type == MONO_PATCH_INFO_R8)
7159                         code_size += 8 + 15; /* sizeof (double) + alignment */
7160                 if (patch_info->type == MONO_PATCH_INFO_R4)
7161                         code_size += 4 + 15; /* sizeof (float) + alignment */
7162                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7163                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7164         }
7165
7166         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7167                 cfg->code_size *= 2;
7168                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7169                 cfg->stat_code_reallocs++;
7170         }
7171
7172         code = cfg->native_code + cfg->code_len;
7173
7174         /* add code to raise exceptions */
7175         nthrows = 0;
7176         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7177                 switch (patch_info->type) {
7178                 case MONO_PATCH_INFO_EXC: {
7179                         MonoClass *exc_class;
7180                         guint8 *buf, *buf2;
7181                         guint32 throw_ip;
7182
7183                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7184
7185                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7186                         throw_ip = patch_info->ip.i;
7187
7188                         //x86_breakpoint (code);
7189                         /* Find a throw sequence for the same exception class */
7190                         for (i = 0; i < nthrows; ++i)
7191                                 if (exc_classes [i] == exc_class)
7192                                         break;
7193                         if (i < nthrows) {
7194                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7195                                 x86_jump_code (code, exc_throw_start [i]);
7196                                 patch_info->type = MONO_PATCH_INFO_NONE;
7197                         }
7198                         else {
7199                                 buf = code;
7200                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7201                                 buf2 = code;
7202
7203                                 if (nthrows < 16) {
7204                                         exc_classes [nthrows] = exc_class;
7205                                         exc_throw_start [nthrows] = code;
7206                                 }
7207                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7208
7209                                 patch_info->type = MONO_PATCH_INFO_NONE;
7210
7211                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7212
7213                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7214                                 while (buf < buf2)
7215                                         x86_nop (buf);
7216
7217                                 if (nthrows < 16) {
7218                                         exc_throw_end [nthrows] = code;
7219                                         nthrows ++;
7220                                 }
7221                         }
7222                         break;
7223                 }
7224                 default:
7225                         /* do nothing */
7226                         break;
7227                 }
7228                 g_assert(code < cfg->native_code + cfg->code_size);
7229         }
7230
7231         /* Handle relocations with RIP relative addressing */
7232         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7233                 gboolean remove = FALSE;
7234                 guint8 *orig_code = code;
7235
7236                 switch (patch_info->type) {
7237                 case MONO_PATCH_INFO_R8:
7238                 case MONO_PATCH_INFO_R4: {
7239                         guint8 *pos, *patch_pos;
7240                         guint32 target_pos;
7241
7242                         /* The SSE opcodes require a 16 byte alignment */
7243                         code = (guint8*)ALIGN_TO (code, 16);
7244
7245                         pos = cfg->native_code + patch_info->ip.i;
7246                         if (IS_REX (pos [1])) {
7247                                 patch_pos = pos + 5;
7248                                 target_pos = code - pos - 9;
7249                         }
7250                         else {
7251                                 patch_pos = pos + 4;
7252                                 target_pos = code - pos - 8;
7253                         }
7254
7255                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7256                                 *(double*)code = *(double*)patch_info->data.target;
7257                                 code += sizeof (double);
7258                         } else {
7259                                 *(float*)code = *(float*)patch_info->data.target;
7260                                 code += sizeof (float);
7261                         }
7262
7263                         *(guint32*)(patch_pos) = target_pos;
7264
7265                         remove = TRUE;
7266                         break;
7267                 }
7268                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7269                         guint8 *pos;
7270
7271                         if (cfg->compile_aot)
7272                                 continue;
7273
7274                         /*loading is faster against aligned addresses.*/
7275                         code = (guint8*)ALIGN_TO (code, 8);
7276                         memset (orig_code, 0, code - orig_code);
7277
7278                         pos = cfg->native_code + patch_info->ip.i;
7279
7280                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7281                         if (IS_REX (pos [1]))
7282                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7283                         else
7284                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7285
7286                         *(gpointer*)code = (gpointer)patch_info->data.target;
7287                         code += sizeof (gpointer);
7288
7289                         remove = TRUE;
7290                         break;
7291                 }
7292                 default:
7293                         break;
7294                 }
7295
7296                 if (remove) {
7297                         if (patch_info == cfg->patch_info)
7298                                 cfg->patch_info = patch_info->next;
7299                         else {
7300                                 MonoJumpInfo *tmp;
7301
7302                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7303                                         ;
7304                                 tmp->next = patch_info->next;
7305                         }
7306                 }
7307                 g_assert (code < cfg->native_code + cfg->code_size);
7308         }
7309
7310         cfg->code_len = code - cfg->native_code;
7311
7312         g_assert (cfg->code_len < cfg->code_size);
7313
7314 }
7315
7316 #endif /* DISABLE_JIT */
7317
7318 void*
7319 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7320 {
7321         guchar *code = (guchar *)p;
7322         MonoMethodSignature *sig;
7323         MonoInst *inst;
7324         int i, n, stack_area = 0;
7325
7326         /* Keep this in sync with mono_arch_get_argument_info */
7327
7328         if (enable_arguments) {
7329                 /* Allocate a new area on the stack and save arguments there */
7330                 sig = mono_method_signature (cfg->method);
7331
7332                 n = sig->param_count + sig->hasthis;
7333
7334                 stack_area = ALIGN_TO (n * 8, 16);
7335
7336                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7337
7338                 for (i = 0; i < n; ++i) {
7339                         inst = cfg->args [i];
7340
7341                         if (inst->opcode == OP_REGVAR)
7342                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7343                         else {
7344                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7345                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7346                         }
7347                 }
7348         }
7349
7350         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7351         amd64_set_reg_template (code, AMD64_ARG_REG1);
7352         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7353         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7354
7355         if (enable_arguments)
7356                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7357
7358         return code;
7359 }
7360
7361 enum {
7362         SAVE_NONE,
7363         SAVE_STRUCT,
7364         SAVE_EAX,
7365         SAVE_EAX_EDX,
7366         SAVE_XMM
7367 };
7368
7369 void*
7370 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7371 {
7372         guchar *code = (guchar *)p;
7373         int save_mode = SAVE_NONE;
7374         MonoMethod *method = cfg->method;
7375         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7376         int i;
7377
7378         switch (ret_type->type) {
7379         case MONO_TYPE_VOID:
7380                 /* special case string .ctor icall */
7381                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7382                         save_mode = SAVE_EAX;
7383                 else
7384                         save_mode = SAVE_NONE;
7385                 break;
7386         case MONO_TYPE_I8:
7387         case MONO_TYPE_U8:
7388                 save_mode = SAVE_EAX;
7389                 break;
7390         case MONO_TYPE_R4:
7391         case MONO_TYPE_R8:
7392                 save_mode = SAVE_XMM;
7393                 break;
7394         case MONO_TYPE_GENERICINST:
7395                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7396                         save_mode = SAVE_EAX;
7397                         break;
7398                 }
7399                 /* Fall through */
7400         case MONO_TYPE_VALUETYPE:
7401                 save_mode = SAVE_STRUCT;
7402                 break;
7403         default:
7404                 save_mode = SAVE_EAX;
7405                 break;
7406         }
7407
7408         /* Save the result and copy it into the proper argument register */
7409         switch (save_mode) {
7410         case SAVE_EAX:
7411                 amd64_push_reg (code, AMD64_RAX);
7412                 /* Align stack */
7413                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7414                 if (enable_arguments)
7415                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7416                 break;
7417         case SAVE_STRUCT:
7418                 /* FIXME: */
7419                 if (enable_arguments)
7420                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7421                 break;
7422         case SAVE_XMM:
7423                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7424                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7425                 /* Align stack */
7426                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7427                 /*
7428                  * The result is already in the proper argument register so no copying
7429                  * needed.
7430                  */
7431                 break;
7432         case SAVE_NONE:
7433                 break;
7434         default:
7435                 g_assert_not_reached ();
7436         }
7437
7438         /* Set %al since this is a varargs call */
7439         if (save_mode == SAVE_XMM)
7440                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7441         else
7442                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7443
7444         if (preserve_argument_registers) {
7445                 for (i = 0; i < PARAM_REGS; ++i)
7446                         amd64_push_reg (code, param_regs [i]);
7447         }
7448
7449         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7450         amd64_set_reg_template (code, AMD64_ARG_REG1);
7451         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7452
7453         if (preserve_argument_registers) {
7454                 for (i = PARAM_REGS - 1; i >= 0; --i)
7455                         amd64_pop_reg (code, param_regs [i]);
7456         }
7457
7458         /* Restore result */
7459         switch (save_mode) {
7460         case SAVE_EAX:
7461                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7462                 amd64_pop_reg (code, AMD64_RAX);
7463                 break;
7464         case SAVE_STRUCT:
7465                 /* FIXME: */
7466                 break;
7467         case SAVE_XMM:
7468                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7469                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7470                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7471                 break;
7472         case SAVE_NONE:
7473                 break;
7474         default:
7475                 g_assert_not_reached ();
7476         }
7477
7478         return code;
7479 }
7480
7481 void
7482 mono_arch_flush_icache (guint8 *code, gint size)
7483 {
7484         /* Not needed */
7485 }
7486
7487 void
7488 mono_arch_flush_register_windows (void)
7489 {
7490 }
7491
7492 gboolean
7493 mono_arch_is_inst_imm (gint64 imm)
7494 {
7495         return amd64_use_imm32 (imm);
7496 }
7497
7498 /*
7499  * Determine whenever the trap whose info is in SIGINFO is caused by
7500  * integer overflow.
7501  */
7502 gboolean
7503 mono_arch_is_int_overflow (void *sigctx, void *info)
7504 {
7505         MonoContext ctx;
7506         guint8* rip;
7507         int reg;
7508         gint64 value;
7509
7510         mono_sigctx_to_monoctx (sigctx, &ctx);
7511
7512         rip = (guint8*)ctx.gregs [AMD64_RIP];
7513
7514         if (IS_REX (rip [0])) {
7515                 reg = amd64_rex_b (rip [0]);
7516                 rip ++;
7517         }
7518         else
7519                 reg = 0;
7520
7521         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7522                 /* idiv REG */
7523                 reg += x86_modrm_rm (rip [1]);
7524
7525                 value = ctx.gregs [reg];
7526
7527                 if (value == -1)
7528                         return TRUE;
7529         }
7530
7531         return FALSE;
7532 }
7533
7534 guint32
7535 mono_arch_get_patch_offset (guint8 *code)
7536 {
7537         return 3;
7538 }
7539
7540 /**
7541  * mono_breakpoint_clean_code:
7542  *
7543  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7544  * breakpoints in the original code, they are removed in the copy.
7545  *
7546  * Returns TRUE if no sw breakpoint was present.
7547  */
7548 gboolean
7549 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7550 {
7551         /*
7552          * If method_start is non-NULL we need to perform bound checks, since we access memory
7553          * at code - offset we could go before the start of the method and end up in a different
7554          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7555          * instead.
7556          */
7557         if (!method_start || code - offset >= method_start) {
7558                 memcpy (buf, code - offset, size);
7559         } else {
7560                 int diff = code - method_start;
7561                 memset (buf, 0, size);
7562                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7563         }
7564         return TRUE;
7565 }
7566
7567 int
7568 mono_arch_get_this_arg_reg (guint8 *code)
7569 {
7570         return AMD64_ARG_REG1;
7571 }
7572
7573 gpointer
7574 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7575 {
7576         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7577 }
7578
7579 #define MAX_ARCH_DELEGATE_PARAMS 10
7580
7581 static gpointer
7582 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7583 {
7584         guint8 *code, *start;
7585         GSList *unwind_ops = NULL;
7586         int i;
7587
7588         unwind_ops = mono_arch_get_cie_program ();
7589
7590         if (has_target) {
7591                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7592
7593                 /* Replace the this argument with the target */
7594                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7595                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7596                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7597
7598                 g_assert ((code - start) < 64);
7599         } else {
7600                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7601
7602                 if (param_count == 0) {
7603                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7604                 } else {
7605                         /* We have to shift the arguments left */
7606                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7607                         for (i = 0; i < param_count; ++i) {
7608 #ifdef TARGET_WIN32
7609                                 if (i < 3)
7610                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7611                                 else
7612                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7613 #else
7614                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7615 #endif
7616                         }
7617
7618                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7619                 }
7620                 g_assert ((code - start) < 64);
7621         }
7622
7623         mono_arch_flush_icache (start, code - start);
7624
7625         if (has_target) {
7626                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7627         } else {
7628                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7629                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7630                 g_free (name);
7631         }
7632
7633         if (mono_jit_map_is_enabled ()) {
7634                 char *buff;
7635                 if (has_target)
7636                         buff = (char*)"delegate_invoke_has_target";
7637                 else
7638                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7639                 mono_emit_jit_tramp (start, code - start, buff);
7640                 if (!has_target)
7641                         g_free (buff);
7642         }
7643         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7644
7645         return start;
7646 }
7647
7648 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7649
7650 static gpointer
7651 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7652 {
7653         guint8 *code, *start;
7654         int size = 20;
7655         char *tramp_name;
7656         GSList *unwind_ops;
7657
7658         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7659                 return NULL;
7660
7661         start = code = (guint8 *)mono_global_codeman_reserve (size);
7662
7663         unwind_ops = mono_arch_get_cie_program ();
7664
7665         /* Replace the this argument with the target */
7666         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7667         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7668
7669         if (load_imt_reg) {
7670                 /* Load the IMT reg */
7671                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7672         }
7673
7674         /* Load the vtable */
7675         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7676         amd64_jump_membase (code, AMD64_RAX, offset);
7677         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7678
7679         tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7680         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7681         g_free (tramp_name);
7682
7683         return start;
7684 }
7685
7686 /*
7687  * mono_arch_get_delegate_invoke_impls:
7688  *
7689  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7690  * trampolines.
7691  */
7692 GSList*
7693 mono_arch_get_delegate_invoke_impls (void)
7694 {
7695         GSList *res = NULL;
7696         MonoTrampInfo *info;
7697         int i;
7698
7699         get_delegate_invoke_impl (&info, TRUE, 0);
7700         res = g_slist_prepend (res, info);
7701
7702         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7703                 get_delegate_invoke_impl (&info, FALSE, i);
7704                 res = g_slist_prepend (res, info);
7705         }
7706
7707         for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7708                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7709                 res = g_slist_prepend (res, info);
7710         }
7711
7712         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7713                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7714                 res = g_slist_prepend (res, info);
7715                 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7716                 res = g_slist_prepend (res, info);
7717         }
7718
7719         return res;
7720 }
7721
7722 gpointer
7723 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7724 {
7725         guint8 *code, *start;
7726         int i;
7727
7728         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7729                 return NULL;
7730
7731         /* FIXME: Support more cases */
7732         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7733                 return NULL;
7734
7735         if (has_target) {
7736                 static guint8* cached = NULL;
7737
7738                 if (cached)
7739                         return cached;
7740
7741                 if (mono_aot_only) {
7742                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7743                 } else {
7744                         MonoTrampInfo *info;
7745                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7746                         mono_tramp_info_register (info, NULL);
7747                 }
7748
7749                 mono_memory_barrier ();
7750
7751                 cached = start;
7752         } else {
7753                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7754                 for (i = 0; i < sig->param_count; ++i)
7755                         if (!mono_is_regsize_var (sig->params [i]))
7756                                 return NULL;
7757                 if (sig->param_count > 4)
7758                         return NULL;
7759
7760                 code = cache [sig->param_count];
7761                 if (code)
7762                         return code;
7763
7764                 if (mono_aot_only) {
7765                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7766                         start = (guint8 *)mono_aot_get_trampoline (name);
7767                         g_free (name);
7768                 } else {
7769                         MonoTrampInfo *info;
7770                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7771                         mono_tramp_info_register (info, NULL);
7772                 }
7773
7774                 mono_memory_barrier ();
7775
7776                 cache [sig->param_count] = start;
7777         }
7778
7779         return start;
7780 }
7781
7782 gpointer
7783 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7784 {
7785         MonoTrampInfo *info;
7786         gpointer code;
7787
7788         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7789         if (code)
7790                 mono_tramp_info_register (info, NULL);
7791         return code;
7792 }
7793
7794 void
7795 mono_arch_finish_init (void)
7796 {
7797 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7798         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7799 #endif
7800 }
7801
7802 void
7803 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7804 {
7805 }
7806
7807 #define CMP_SIZE (6 + 1)
7808 #define CMP_REG_REG_SIZE (4 + 1)
7809 #define BR_SMALL_SIZE 2
7810 #define BR_LARGE_SIZE 6
7811 #define MOV_REG_IMM_SIZE 10
7812 #define MOV_REG_IMM_32BIT_SIZE 6
7813 #define JUMP_REG_SIZE (2 + 1)
7814
7815 static int
7816 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7817 {
7818         int i, distance = 0;
7819         for (i = start; i < target; ++i)
7820                 distance += imt_entries [i]->chunk_size;
7821         return distance;
7822 }
7823
7824 /*
7825  * LOCKING: called with the domain lock held
7826  */
7827 gpointer
7828 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7829         gpointer fail_tramp)
7830 {
7831         int i;
7832         int size = 0;
7833         guint8 *code, *start;
7834         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7835         GSList *unwind_ops;
7836
7837         for (i = 0; i < count; ++i) {
7838                 MonoIMTCheckItem *item = imt_entries [i];
7839                 if (item->is_equals) {
7840                         if (item->check_target_idx) {
7841                                 if (!item->compare_done) {
7842                                         if (amd64_use_imm32 ((gint64)item->key))
7843                                                 item->chunk_size += CMP_SIZE;
7844                                         else
7845                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7846                                 }
7847                                 if (item->has_target_code) {
7848                                         item->chunk_size += MOV_REG_IMM_SIZE;
7849                                 } else {
7850                                         if (vtable_is_32bit)
7851                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7852                                         else
7853                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7854                                 }
7855                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7856                         } else {
7857                                 if (fail_tramp) {
7858                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7859                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7860                                 } else {
7861                                         if (vtable_is_32bit)
7862                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7863                                         else
7864                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7865                                         item->chunk_size += JUMP_REG_SIZE;
7866                                         /* with assert below:
7867                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7868                                          */
7869                                 }
7870                         }
7871                 } else {
7872                         if (amd64_use_imm32 ((gint64)item->key))
7873                                 item->chunk_size += CMP_SIZE;
7874                         else
7875                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7876                         item->chunk_size += BR_LARGE_SIZE;
7877                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7878                 }
7879                 size += item->chunk_size;
7880         }
7881         if (fail_tramp)
7882                 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size);
7883         else
7884                 code = (guint8 *)mono_domain_code_reserve (domain, size);
7885         start = code;
7886
7887         unwind_ops = mono_arch_get_cie_program ();
7888
7889         for (i = 0; i < count; ++i) {
7890                 MonoIMTCheckItem *item = imt_entries [i];
7891                 item->code_target = code;
7892                 if (item->is_equals) {
7893                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7894
7895                         if (item->check_target_idx || fail_case) {
7896                                 if (!item->compare_done || fail_case) {
7897                                         if (amd64_use_imm32 ((gint64)item->key))
7898                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7899                                         else {
7900                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7901                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7902                                         }
7903                                 }
7904                                 item->jmp_code = code;
7905                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7906                                 if (item->has_target_code) {
7907                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7908                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7909                                 } else {
7910                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7911                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7912                                 }
7913
7914                                 if (fail_case) {
7915                                         amd64_patch (item->jmp_code, code);
7916                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7917                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7918                                         item->jmp_code = NULL;
7919                                 }
7920                         } else {
7921                                 /* enable the commented code to assert on wrong method */
7922 #if 0
7923                                 if (amd64_is_imm32 (item->key))
7924                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7925                                 else {
7926                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7927                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7928                                 }
7929                                 item->jmp_code = code;
7930                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7931                                 /* See the comment below about R10 */
7932                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7933                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7934                                 amd64_patch (item->jmp_code, code);
7935                                 amd64_breakpoint (code);
7936                                 item->jmp_code = NULL;
7937 #else
7938                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7939                                    needs to be preserved.  R10 needs
7940                                    to be preserved for calls which
7941                                    require a runtime generic context,
7942                                    but interface calls don't. */
7943                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7944                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7945 #endif
7946                         }
7947                 } else {
7948                         if (amd64_use_imm32 ((gint64)item->key))
7949                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
7950                         else {
7951                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
7952                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7953                         }
7954                         item->jmp_code = code;
7955                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7956                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7957                         else
7958                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7959                 }
7960                 g_assert (code - item->code_target <= item->chunk_size);
7961         }
7962         /* patch the branches to get to the target items */
7963         for (i = 0; i < count; ++i) {
7964                 MonoIMTCheckItem *item = imt_entries [i];
7965                 if (item->jmp_code) {
7966                         if (item->check_target_idx) {
7967                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7968                         }
7969                 }
7970         }
7971
7972         if (!fail_tramp)
7973                 mono_stats.imt_trampolines_size += code - start;
7974         g_assert (code - start <= size);
7975
7976         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7977
7978         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
7979
7980         return start;
7981 }
7982
7983 MonoMethod*
7984 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7985 {
7986         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7987 }
7988
7989 MonoVTable*
7990 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7991 {
7992         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7993 }
7994
7995 GSList*
7996 mono_arch_get_cie_program (void)
7997 {
7998         GSList *l = NULL;
7999
8000         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8001         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8002
8003         return l;
8004 }
8005
8006 #ifndef DISABLE_JIT
8007
8008 MonoInst*
8009 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8010 {
8011         MonoInst *ins = NULL;
8012         int opcode = 0;
8013
8014         if (cmethod->klass == mono_defaults.math_class) {
8015                 if (strcmp (cmethod->name, "Sin") == 0) {
8016                         opcode = OP_SIN;
8017                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8018                         opcode = OP_COS;
8019                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8020                         opcode = OP_SQRT;
8021                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8022                         opcode = OP_ABS;
8023                 }
8024
8025                 if (opcode && fsig->param_count == 1) {
8026                         MONO_INST_NEW (cfg, ins, opcode);
8027                         ins->type = STACK_R8;
8028                         ins->dreg = mono_alloc_freg (cfg);
8029                         ins->sreg1 = args [0]->dreg;
8030                         MONO_ADD_INS (cfg->cbb, ins);
8031                 }
8032
8033                 opcode = 0;
8034                 if (cfg->opt & MONO_OPT_CMOV) {
8035                         if (strcmp (cmethod->name, "Min") == 0) {
8036                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8037                                         opcode = OP_IMIN;
8038                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8039                                         opcode = OP_IMIN_UN;
8040                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8041                                         opcode = OP_LMIN;
8042                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8043                                         opcode = OP_LMIN_UN;
8044                         } else if (strcmp (cmethod->name, "Max") == 0) {
8045                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8046                                         opcode = OP_IMAX;
8047                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8048                                         opcode = OP_IMAX_UN;
8049                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8050                                         opcode = OP_LMAX;
8051                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8052                                         opcode = OP_LMAX_UN;
8053                         }
8054                 }
8055
8056                 if (opcode && fsig->param_count == 2) {
8057                         MONO_INST_NEW (cfg, ins, opcode);
8058                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8059                         ins->dreg = mono_alloc_ireg (cfg);
8060                         ins->sreg1 = args [0]->dreg;
8061                         ins->sreg2 = args [1]->dreg;
8062                         MONO_ADD_INS (cfg->cbb, ins);
8063                 }
8064
8065 #if 0
8066                 /* OP_FREM is not IEEE compatible */
8067                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8068                         MONO_INST_NEW (cfg, ins, OP_FREM);
8069                         ins->inst_i0 = args [0];
8070                         ins->inst_i1 = args [1];
8071                 }
8072 #endif
8073         }
8074
8075         return ins;
8076 }
8077 #endif
8078
8079 gboolean
8080 mono_arch_print_tree (MonoInst *tree, int arity)
8081 {
8082         return 0;
8083 }
8084
8085 mgreg_t
8086 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8087 {
8088         return ctx->gregs [reg];
8089 }
8090
8091 void
8092 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8093 {
8094         ctx->gregs [reg] = val;
8095 }
8096
8097 gpointer
8098 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8099 {
8100         gpointer *sp, old_value;
8101         char *bp;
8102
8103         /*Load the spvar*/
8104         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8105         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8106
8107         old_value = *sp;
8108         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8109                 return old_value;
8110
8111         *sp = new_value;
8112
8113         return old_value;
8114 }
8115
8116 /*
8117  * mono_arch_emit_load_aotconst:
8118  *
8119  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8120  * TARGET from the mscorlib GOT in full-aot code.
8121  * On AMD64, the result is placed into R11.
8122  */
8123 guint8*
8124 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8125 {
8126         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8127         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8128
8129         return code;
8130 }
8131
8132 /*
8133  * mono_arch_get_trampolines:
8134  *
8135  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8136  * for AOT.
8137  */
8138 GSList *
8139 mono_arch_get_trampolines (gboolean aot)
8140 {
8141         return mono_amd64_get_exception_trampolines (aot);
8142 }
8143
8144 /* Soft Debug support */
8145 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8146
8147 /*
8148  * mono_arch_set_breakpoint:
8149  *
8150  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8151  * The location should contain code emitted by OP_SEQ_POINT.
8152  */
8153 void
8154 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8155 {
8156         guint8 *code = ip;
8157
8158         if (ji->from_aot) {
8159                 guint32 native_offset = ip - (guint8*)ji->code_start;
8160                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8161
8162                 g_assert (info->bp_addrs [native_offset] == 0);
8163                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8164         } else {
8165                 /* ip points to a mov r11, 0 */
8166                 g_assert (code [0] == 0x41);
8167                 g_assert (code [1] == 0xbb);
8168                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8169         }
8170 }
8171
8172 /*
8173  * mono_arch_clear_breakpoint:
8174  *
8175  *   Clear the breakpoint at IP.
8176  */
8177 void
8178 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8179 {
8180         guint8 *code = ip;
8181
8182         if (ji->from_aot) {
8183                 guint32 native_offset = ip - (guint8*)ji->code_start;
8184                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8185
8186                 info->bp_addrs [native_offset] = NULL;
8187         } else {
8188                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8189         }
8190 }
8191
8192 gboolean
8193 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8194 {
8195         /* We use soft breakpoints on amd64 */
8196         return FALSE;
8197 }
8198
8199 /*
8200  * mono_arch_skip_breakpoint:
8201  *
8202  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8203  * we resume, the instruction is not executed again.
8204  */
8205 void
8206 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8207 {
8208         g_assert_not_reached ();
8209 }
8210
8211 /*
8212  * mono_arch_start_single_stepping:
8213  *
8214  *   Start single stepping.
8215  */
8216 void
8217 mono_arch_start_single_stepping (void)
8218 {
8219         ss_trampoline = mini_get_single_step_trampoline ();
8220 }
8221
8222 /*
8223  * mono_arch_stop_single_stepping:
8224  *
8225  *   Stop single stepping.
8226  */
8227 void
8228 mono_arch_stop_single_stepping (void)
8229 {
8230         ss_trampoline = NULL;
8231 }
8232
8233 /*
8234  * mono_arch_is_single_step_event:
8235  *
8236  *   Return whenever the machine state in SIGCTX corresponds to a single
8237  * step event.
8238  */
8239 gboolean
8240 mono_arch_is_single_step_event (void *info, void *sigctx)
8241 {
8242         /* We use soft breakpoints on amd64 */
8243         return FALSE;
8244 }
8245
8246 /*
8247  * mono_arch_skip_single_step:
8248  *
8249  *   Modify CTX so the ip is placed after the single step trigger instruction,
8250  * we resume, the instruction is not executed again.
8251  */
8252 void
8253 mono_arch_skip_single_step (MonoContext *ctx)
8254 {
8255         g_assert_not_reached ();
8256 }
8257
8258 /*
8259  * mono_arch_create_seq_point_info:
8260  *
8261  *   Return a pointer to a data structure which is used by the sequence
8262  * point implementation in AOTed code.
8263  */
8264 gpointer
8265 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8266 {
8267         SeqPointInfo *info;
8268         MonoJitInfo *ji;
8269
8270         // FIXME: Add a free function
8271
8272         mono_domain_lock (domain);
8273         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8274                                                                 code);
8275         mono_domain_unlock (domain);
8276
8277         if (!info) {
8278                 ji = mono_jit_info_table_find (domain, (char*)code);
8279                 g_assert (ji);
8280
8281                 // FIXME: Optimize the size
8282                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8283
8284                 info->ss_tramp_addr = &ss_trampoline;
8285
8286                 mono_domain_lock (domain);
8287                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8288                                                          code, info);
8289                 mono_domain_unlock (domain);
8290         }
8291
8292         return info;
8293 }
8294
8295 void
8296 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8297 {
8298         ext->lmf.previous_lmf = prev_lmf;
8299         /* Mark that this is a MonoLMFExt */
8300         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8301         ext->lmf.rsp = (gssize)ext;
8302 }
8303
8304 #endif
8305
8306 gboolean
8307 mono_arch_opcode_supported (int opcode)
8308 {
8309         switch (opcode) {
8310         case OP_ATOMIC_ADD_I4:
8311         case OP_ATOMIC_ADD_I8:
8312         case OP_ATOMIC_EXCHANGE_I4:
8313         case OP_ATOMIC_EXCHANGE_I8:
8314         case OP_ATOMIC_CAS_I4:
8315         case OP_ATOMIC_CAS_I8:
8316         case OP_ATOMIC_LOAD_I1:
8317         case OP_ATOMIC_LOAD_I2:
8318         case OP_ATOMIC_LOAD_I4:
8319         case OP_ATOMIC_LOAD_I8:
8320         case OP_ATOMIC_LOAD_U1:
8321         case OP_ATOMIC_LOAD_U2:
8322         case OP_ATOMIC_LOAD_U4:
8323         case OP_ATOMIC_LOAD_U8:
8324         case OP_ATOMIC_LOAD_R4:
8325         case OP_ATOMIC_LOAD_R8:
8326         case OP_ATOMIC_STORE_I1:
8327         case OP_ATOMIC_STORE_I2:
8328         case OP_ATOMIC_STORE_I4:
8329         case OP_ATOMIC_STORE_I8:
8330         case OP_ATOMIC_STORE_U1:
8331         case OP_ATOMIC_STORE_U2:
8332         case OP_ATOMIC_STORE_U4:
8333         case OP_ATOMIC_STORE_U8:
8334         case OP_ATOMIC_STORE_R4:
8335         case OP_ATOMIC_STORE_R8:
8336                 return TRUE;
8337         default:
8338                 return FALSE;
8339         }
8340 }
8341
8342 CallInfo*
8343 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8344 {
8345         return get_call_info (mp, sig);
8346 }