mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27 #include <mono/utils/mono-mmap.h>
  28
  29 #include "trace.h"
  30 #include "ir-emit.h"
  31 #include "mini-amd64.h"
  32 #include "cpu-amd64.h"
  33 #include "debugger-agent.h"
  34
  35 /*
  36  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  37  * method-to-ir.c.
  38  */
  39 #define MONO_ARCH_IMT_REG AMD64_R11
  40
  41 static gint lmf_tls_offset = -1;
  42 static gint lmf_addr_tls_offset = -1;
  43 static gint appdomain_tls_offset = -1;
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef HOST_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* amd64_mov_reg_imm () */
  65 #define BREAKPOINT_SIZE 8
  66
  67 /* This mutex protects architecture specific caches */
  68 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  69 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  70 static CRITICAL_SECTION mini_arch_mutex;
  71
  72 MonoBreakpointInfo
  73 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  74
  75 /*
  76  * The code generated for sequence points reads from this location, which is
  77  * made read-only when single stepping is enabled.
  78  */
  79 static gpointer ss_trigger_page;
  80
  81 /* Enabled breakpoints read from this trigger page */
  82 static gpointer bp_trigger_page;
  83
  84 #ifdef HOST_WIN32
  85 /* On Win64 always reserve first 32 bytes for first four arguments */
  86 #define ARGS_OFFSET 48
  87 #else
  88 #define ARGS_OFFSET 16
  89 #endif
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 G_GNUC_UNUSED static void
 162 break_count (void)
 163 {
 164 }
 165
 166 G_GNUC_UNUSED static gboolean
 167 debug_count (void)
 168 {
 169         static int count = 0;
 170         count ++;
 171
 172         if (!getenv ("COUNT"))
 173                 return TRUE;
 174
 175         if (count == atoi (getenv ("COUNT"))) {
 176                 break_count ();
 177         }
 178
 179         if (count > atoi (getenv ("COUNT"))) {
 180                 return FALSE;
 181         }
 182
 183         return TRUE;
 184 }
 185
 186 static gboolean
 187 debug_omit_fp (void)
 188 {
 189 #if 0
 190         return debug_count ();
 191 #else
 192         return TRUE;
 193 #endif
 194 }
 195
 196 static inline gboolean
 197 amd64_is_near_call (guint8 *code)
 198 {
 199         /* Skip REX */
 200         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 201                 code += 1;
 202
 203         return code [0] == 0xe8;
 204 }
 205
 206 static inline void
 207 amd64_patch (unsigned char* code, gpointer target)
 208 {
 209         guint8 rex = 0;
 210
 211         /* Skip REX */
 212         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 213                 rex = code [0];
 214                 code += 1;
 215         }
 216
 217         if ((code [0] & 0xf8) == 0xb8) {
 218                 /* amd64_set_reg_template */
 219                 *(guint64*)(code + 1) = (guint64)target;
 220         }
 221         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 222                 /* mov 0(%rip), %dreg */
 223                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 224         }
 225         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 226                 /* call *<OFFSET>(%rip) */
 227                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 228         }
 229         else if ((code [0] == 0xe8)) {
 230                 /* call <DISP> */
 231                 gint64 disp = (guint8*)target - (guint8*)code;
 232                 g_assert (amd64_is_imm32 (disp));
 233                 x86_patch (code, (unsigned char*)target);
 234         }
 235         else
 236                 x86_patch (code, (unsigned char*)target);
 237 }
 238
 239 void
 240 mono_amd64_patch (unsigned char* code, gpointer target)
 241 {
 242         amd64_patch (code, target);
 243 }
 244
 245 typedef enum {
 246         ArgInIReg,
 247         ArgInFloatSSEReg,
 248         ArgInDoubleSSEReg,
 249         ArgOnStack,
 250         ArgValuetypeInReg,
 251         ArgValuetypeAddrInIReg,
 252         ArgNone /* only in pair_storage */
 253 } ArgStorage;
 254
 255 typedef struct {
 256         gint16 offset;
 257         gint8  reg;
 258         ArgStorage storage;
 259
 260         /* Only if storage == ArgValuetypeInReg */
 261         ArgStorage pair_storage [2];
 262         gint8 pair_regs [2];
 263 } ArgInfo;
 264
 265 typedef struct {
 266         int nargs;
 267         guint32 stack_usage;
 268         guint32 reg_usage;
 269         guint32 freg_usage;
 270         gboolean need_stack_align;
 271         gboolean vtype_retaddr;
 272         ArgInfo ret;
 273         ArgInfo sig_cookie;
 274         ArgInfo args [1];
 275 } CallInfo;
 276
 277 #define DEBUG(a) if (cfg->verbose_level > 1) a
 278
 279 #ifdef HOST_WIN32
 280 #define PARAM_REGS 4
 281
 282 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 283
 284 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 285 #else
 286 #define PARAM_REGS 6
 287
 288 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 289
 290  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 291 #endif
 292
 293 static void inline
 294 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 295 {
 296     ainfo->offset = *stack_size;
 297
 298     if (*gr >= PARAM_REGS) {
 299                 ainfo->storage = ArgOnStack;
 300                 (*stack_size) += sizeof (gpointer);
 301     }
 302     else {
 303                 ainfo->storage = ArgInIReg;
 304                 ainfo->reg = param_regs [*gr];
 305                 (*gr) ++;
 306     }
 307 }
 308
 309 #ifdef HOST_WIN32
 310 #define FLOAT_PARAM_REGS 4
 311 #else
 312 #define FLOAT_PARAM_REGS 8
 313 #endif
 314
 315 static void inline
 316 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 317 {
 318     ainfo->offset = *stack_size;
 319
 320     if (*gr >= FLOAT_PARAM_REGS) {
 321                 ainfo->storage = ArgOnStack;
 322                 (*stack_size) += sizeof (gpointer);
 323     }
 324     else {
 325                 /* A double register */
 326                 if (is_double)
 327                         ainfo->storage = ArgInDoubleSSEReg;
 328                 else
 329                         ainfo->storage = ArgInFloatSSEReg;
 330                 ainfo->reg = *gr;
 331                 (*gr) += 1;
 332     }
 333 }
 334
 335 typedef enum ArgumentClass {
 336         ARG_CLASS_NO_CLASS,
 337         ARG_CLASS_MEMORY,
 338         ARG_CLASS_INTEGER,
 339         ARG_CLASS_SSE
 340 } ArgumentClass;
 341
 342 static ArgumentClass
 343 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 344 {
 345         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 346         MonoType *ptype;
 347
 348         ptype = mini_type_get_underlying_type (NULL, type);
 349         switch (ptype->type) {
 350         case MONO_TYPE_BOOLEAN:
 351         case MONO_TYPE_CHAR:
 352         case MONO_TYPE_I1:
 353         case MONO_TYPE_U1:
 354         case MONO_TYPE_I2:
 355         case MONO_TYPE_U2:
 356         case MONO_TYPE_I4:
 357         case MONO_TYPE_U4:
 358         case MONO_TYPE_I:
 359         case MONO_TYPE_U:
 360         case MONO_TYPE_STRING:
 361         case MONO_TYPE_OBJECT:
 362         case MONO_TYPE_CLASS:
 363         case MONO_TYPE_SZARRAY:
 364         case MONO_TYPE_PTR:
 365         case MONO_TYPE_FNPTR:
 366         case MONO_TYPE_ARRAY:
 367         case MONO_TYPE_I8:
 368         case MONO_TYPE_U8:
 369                 class2 = ARG_CLASS_INTEGER;
 370                 break;
 371         case MONO_TYPE_R4:
 372         case MONO_TYPE_R8:
 373 #ifdef HOST_WIN32
 374                 class2 = ARG_CLASS_INTEGER;
 375 #else
 376                 class2 = ARG_CLASS_SSE;
 377 #endif
 378                 break;
 379
 380         case MONO_TYPE_TYPEDBYREF:
 381                 g_assert_not_reached ();
 382
 383         case MONO_TYPE_GENERICINST:
 384                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 385                         class2 = ARG_CLASS_INTEGER;
 386                         break;
 387                 }
 388                 /* fall through */
 389         case MONO_TYPE_VALUETYPE: {
 390                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 391                 int i;
 392
 393                 for (i = 0; i < info->num_fields; ++i) {
 394                         class2 = class1;
 395                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 396                 }
 397                 break;
 398         }
 399         default:
 400                 g_assert_not_reached ();
 401         }
 402
 403         /* Merge */
 404         if (class1 == class2)
 405                 ;
 406         else if (class1 == ARG_CLASS_NO_CLASS)
 407                 class1 = class2;
 408         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 409                 class1 = ARG_CLASS_MEMORY;
 410         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 411                 class1 = ARG_CLASS_INTEGER;
 412         else
 413                 class1 = ARG_CLASS_SSE;
 414
 415         return class1;
 416 }
 417
 418 static void
 419 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 420                            gboolean is_return,
 421                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 422 {
 423         guint32 size, quad, nquads, i;
 424         ArgumentClass args [2];
 425         MonoMarshalType *info = NULL;
 426         MonoClass *klass;
 427         MonoGenericSharingContext tmp_gsctx;
 428         gboolean pass_on_stack = FALSE;
 429
 430         /*
 431          * The gsctx currently contains no data, it is only used for checking whenever
 432          * open types are allowed, some callers like mono_arch_get_argument_info ()
 433          * don't pass it to us, so work around that.
 434          */
 435         if (!gsctx)
 436                 gsctx = &tmp_gsctx;
 437
 438         klass = mono_class_from_mono_type (type);
 439         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 440 #ifndef HOST_WIN32
 441         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 442                 /* We pass and return vtypes of size 8 in a register */
 443         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 444                 pass_on_stack = TRUE;
 445         }
 446 #else
 447         if (!sig->pinvoke) {
 448                 pass_on_stack = TRUE;
 449         }
 450 #endif
 451
 452         if (pass_on_stack) {
 453                 /* Allways pass in memory */
 454                 ainfo->offset = *stack_size;
 455                 *stack_size += ALIGN_TO (size, 8);
 456                 ainfo->storage = ArgOnStack;
 457
 458                 return;
 459         }
 460
 461         /* FIXME: Handle structs smaller than 8 bytes */
 462         //if ((size % 8) != 0)
 463         //      NOT_IMPLEMENTED;
 464
 465         if (size > 8)
 466                 nquads = 2;
 467         else
 468                 nquads = 1;
 469
 470         if (!sig->pinvoke) {
 471                 /* Always pass in 1 or 2 integer registers */
 472                 args [0] = ARG_CLASS_INTEGER;
 473                 args [1] = ARG_CLASS_INTEGER;
 474                 /* Only the simplest cases are supported */
 475                 if (is_return && nquads != 1) {
 476                         args [0] = ARG_CLASS_MEMORY;
 477                         args [1] = ARG_CLASS_MEMORY;
 478                 }
 479         } else {
 480                 /*
 481                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 482                  * The X87 and SSEUP stuff is left out since there are no such types in
 483                  * the CLR.
 484                  */
 485                 info = mono_marshal_load_type_info (klass);
 486                 g_assert (info);
 487
 488 #ifndef HOST_WIN32
 489                 if (info->native_size > 16) {
 490                         ainfo->offset = *stack_size;
 491                         *stack_size += ALIGN_TO (info->native_size, 8);
 492                         ainfo->storage = ArgOnStack;
 493
 494                         return;
 495                 }
 496 #else
 497                 switch (info->native_size) {
 498                 case 1: case 2: case 4: case 8:
 499                         break;
 500                 default:
 501                         if (is_return) {
 502                                 ainfo->storage = ArgOnStack;
 503                                 ainfo->offset = *stack_size;
 504                                 *stack_size += ALIGN_TO (info->native_size, 8);
 505                         }
 506                         else {
 507                                 ainfo->storage = ArgValuetypeAddrInIReg;
 508
 509                                 if (*gr < PARAM_REGS) {
 510                                         ainfo->pair_storage [0] = ArgInIReg;
 511                                         ainfo->pair_regs [0] = param_regs [*gr];
 512                                         (*gr) ++;
 513                                 }
 514                                 else {
 515                                         ainfo->pair_storage [0] = ArgOnStack;
 516                                         ainfo->offset = *stack_size;
 517                                         *stack_size += 8;
 518                                 }
 519                         }
 520
 521                         return;
 522                 }
 523 #endif
 524
 525                 args [0] = ARG_CLASS_NO_CLASS;
 526                 args [1] = ARG_CLASS_NO_CLASS;
 527                 for (quad = 0; quad < nquads; ++quad) {
 528                         int size;
 529                         guint32 align;
 530                         ArgumentClass class1;
 531
 532                         if (info->num_fields == 0)
 533                                 class1 = ARG_CLASS_MEMORY;
 534                         else
 535                                 class1 = ARG_CLASS_NO_CLASS;
 536                         for (i = 0; i < info->num_fields; ++i) {
 537                                 size = mono_marshal_type_size (info->fields [i].field->type,
 538                                                                                            info->fields [i].mspec,
 539                                                                                            &align, TRUE, klass->unicode);
 540                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 541                                         /* Unaligned field */
 542                                         NOT_IMPLEMENTED;
 543                                 }
 544
 545                                 /* Skip fields in other quad */
 546                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 547                                         continue;
 548                                 if ((quad == 1) && (info->fields [i].offset < 8))
 549                                         continue;
 550
 551                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 552                         }
 553                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 554                         args [quad] = class1;
 555                 }
 556         }
 557
 558         /* Post merger cleanup */
 559         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 560                 args [0] = args [1] = ARG_CLASS_MEMORY;
 561
 562         /* Allocate registers */
 563         {
 564                 int orig_gr = *gr;
 565                 int orig_fr = *fr;
 566
 567                 ainfo->storage = ArgValuetypeInReg;
 568                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 569                 for (quad = 0; quad < nquads; ++quad) {
 570                         switch (args [quad]) {
 571                         case ARG_CLASS_INTEGER:
 572                                 if (*gr >= PARAM_REGS)
 573                                         args [quad] = ARG_CLASS_MEMORY;
 574                                 else {
 575                                         ainfo->pair_storage [quad] = ArgInIReg;
 576                                         if (is_return)
 577                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 578                                         else
 579                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 580                                         (*gr) ++;
 581                                 }
 582                                 break;
 583                         case ARG_CLASS_SSE:
 584                                 if (*fr >= FLOAT_PARAM_REGS)
 585                                         args [quad] = ARG_CLASS_MEMORY;
 586                                 else {
 587                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 588                                         ainfo->pair_regs [quad] = *fr;
 589                                         (*fr) ++;
 590                                 }
 591                                 break;
 592                         case ARG_CLASS_MEMORY:
 593                                 break;
 594                         default:
 595                                 g_assert_not_reached ();
 596                         }
 597                 }
 598
 599                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 600                         /* Revert possible register assignments */
 601                         *gr = orig_gr;
 602                         *fr = orig_fr;
 603
 604                         ainfo->offset = *stack_size;
 605                         if (sig->pinvoke)
 606                                 *stack_size += ALIGN_TO (info->native_size, 8);
 607                         else
 608                                 *stack_size += nquads * sizeof (gpointer);
 609                         ainfo->storage = ArgOnStack;
 610                 }
 611         }
 612 }
 613
 614 /*
 615  * get_call_info:
 616  *
 617  *  Obtain information about a call according to the calling convention.
 618  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 619  * Draft Version 0.23" document for more information.
 620  */
 621 static CallInfo*
 622 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 623 {
 624         guint32 i, gr, fr;
 625         MonoType *ret_type;
 626         int n = sig->hasthis + sig->param_count;
 627         guint32 stack_size = 0;
 628         CallInfo *cinfo;
 629
 630         if (mp)
 631                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 632         else
 633                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 634
 635         cinfo->nargs = n;
 636
 637         gr = 0;
 638         fr = 0;
 639
 640         /* return value */
 641         {
 642                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 643                 switch (ret_type->type) {
 644                 case MONO_TYPE_BOOLEAN:
 645                 case MONO_TYPE_I1:
 646                 case MONO_TYPE_U1:
 647                 case MONO_TYPE_I2:
 648                 case MONO_TYPE_U2:
 649                 case MONO_TYPE_CHAR:
 650                 case MONO_TYPE_I4:
 651                 case MONO_TYPE_U4:
 652                 case MONO_TYPE_I:
 653                 case MONO_TYPE_U:
 654                 case MONO_TYPE_PTR:
 655                 case MONO_TYPE_FNPTR:
 656                 case MONO_TYPE_CLASS:
 657                 case MONO_TYPE_OBJECT:
 658                 case MONO_TYPE_SZARRAY:
 659                 case MONO_TYPE_ARRAY:
 660                 case MONO_TYPE_STRING:
 661                         cinfo->ret.storage = ArgInIReg;
 662                         cinfo->ret.reg = AMD64_RAX;
 663                         break;
 664                 case MONO_TYPE_U8:
 665                 case MONO_TYPE_I8:
 666                         cinfo->ret.storage = ArgInIReg;
 667                         cinfo->ret.reg = AMD64_RAX;
 668                         break;
 669                 case MONO_TYPE_R4:
 670                         cinfo->ret.storage = ArgInFloatSSEReg;
 671                         cinfo->ret.reg = AMD64_XMM0;
 672                         break;
 673                 case MONO_TYPE_R8:
 674                         cinfo->ret.storage = ArgInDoubleSSEReg;
 675                         cinfo->ret.reg = AMD64_XMM0;
 676                         break;
 677                 case MONO_TYPE_GENERICINST:
 678                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 679                                 cinfo->ret.storage = ArgInIReg;
 680                                 cinfo->ret.reg = AMD64_RAX;
 681                                 break;
 682                         }
 683                         /* fall through */
 684                 case MONO_TYPE_VALUETYPE: {
 685                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 686
 687                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 688                         if (cinfo->ret.storage == ArgOnStack) {
 689                                 cinfo->vtype_retaddr = TRUE;
 690                                 /* The caller passes the address where the value is stored */
 691                                 add_general (&gr, &stack_size, &cinfo->ret);
 692                         }
 693                         break;
 694                 }
 695                 case MONO_TYPE_TYPEDBYREF:
 696                         /* Same as a valuetype with size 24 */
 697                         add_general (&gr, &stack_size, &cinfo->ret);
 698                         ;
 699                         break;
 700                 case MONO_TYPE_VOID:
 701                         break;
 702                 default:
 703                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 704                 }
 705         }
 706
 707         /* this */
 708         if (sig->hasthis)
 709                 add_general (&gr, &stack_size, cinfo->args + 0);
 710
 711         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 712                 gr = PARAM_REGS;
 713                 fr = FLOAT_PARAM_REGS;
 714
 715                 /* Emit the signature cookie just before the implicit arguments */
 716                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 717         }
 718
 719         for (i = 0; i < sig->param_count; ++i) {
 720                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 721                 MonoType *ptype;
 722
 723 #ifdef HOST_WIN32
 724                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 725                 if (gr > fr)
 726                         fr = gr;
 727                 else if (fr > gr)
 728                         gr = fr;
 729 #endif
 730
 731                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 732                         /* We allways pass the sig cookie on the stack for simplicity */
 733                         /*
 734                          * Prevent implicit arguments + the sig cookie from being passed
 735                          * in registers.
 736                          */
 737                         gr = PARAM_REGS;
 738                         fr = FLOAT_PARAM_REGS;
 739
 740                         /* Emit the signature cookie just before the implicit arguments */
 741                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 742                 }
 743
 744                 if (sig->params [i]->byref) {
 745                         add_general (&gr, &stack_size, ainfo);
 746                         continue;
 747                 }
 748                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 749                 switch (ptype->type) {
 750                 case MONO_TYPE_BOOLEAN:
 751                 case MONO_TYPE_I1:
 752                 case MONO_TYPE_U1:
 753                         add_general (&gr, &stack_size, ainfo);
 754                         break;
 755                 case MONO_TYPE_I2:
 756                 case MONO_TYPE_U2:
 757                 case MONO_TYPE_CHAR:
 758                         add_general (&gr, &stack_size, ainfo);
 759                         break;
 760                 case MONO_TYPE_I4:
 761                 case MONO_TYPE_U4:
 762                         add_general (&gr, &stack_size, ainfo);
 763                         break;
 764                 case MONO_TYPE_I:
 765                 case MONO_TYPE_U:
 766                 case MONO_TYPE_PTR:
 767                 case MONO_TYPE_FNPTR:
 768                 case MONO_TYPE_CLASS:
 769                 case MONO_TYPE_OBJECT:
 770                 case MONO_TYPE_STRING:
 771                 case MONO_TYPE_SZARRAY:
 772                 case MONO_TYPE_ARRAY:
 773                         add_general (&gr, &stack_size, ainfo);
 774                         break;
 775                 case MONO_TYPE_GENERICINST:
 776                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 777                                 add_general (&gr, &stack_size, ainfo);
 778                                 break;
 779                         }
 780                         /* fall through */
 781                 case MONO_TYPE_VALUETYPE:
 782                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 783                         break;
 784                 case MONO_TYPE_TYPEDBYREF:
 785 #ifdef HOST_WIN32
 786                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 787 #else
 788                         stack_size += sizeof (MonoTypedRef);
 789                         ainfo->storage = ArgOnStack;
 790 #endif
 791                         break;
 792                 case MONO_TYPE_U8:
 793                 case MONO_TYPE_I8:
 794                         add_general (&gr, &stack_size, ainfo);
 795                         break;
 796                 case MONO_TYPE_R4:
 797                         add_float (&fr, &stack_size, ainfo, FALSE);
 798                         break;
 799                 case MONO_TYPE_R8:
 800                         add_float (&fr, &stack_size, ainfo, TRUE);
 801                         break;
 802                 default:
 803                         g_assert_not_reached ();
 804                 }
 805         }
 806
 807         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 808                 gr = PARAM_REGS;
 809                 fr = FLOAT_PARAM_REGS;
 810
 811                 /* Emit the signature cookie just before the implicit arguments */
 812                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 813         }
 814
 815 #ifdef HOST_WIN32
 816         // There always is 32 bytes reserved on the stack when calling on Winx64
 817         stack_size += 0x20;
 818 #endif
 819
 820         if (stack_size & 0x8) {
 821                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 822                 cinfo->need_stack_align = TRUE;
 823                 stack_size += 8;
 824         }
 825
 826         cinfo->stack_usage = stack_size;
 827         cinfo->reg_usage = gr;
 828         cinfo->freg_usage = fr;
 829         return cinfo;
 830 }
 831
 832 /*
 833  * mono_arch_get_argument_info:
 834  * @csig:  a method signature
 835  * @param_count: the number of parameters to consider
 836  * @arg_info: an array to store the result infos
 837  *
 838  * Gathers information on parameters such as size, alignment and
 839  * padding. arg_info should be large enought to hold param_count + 1 entries.
 840  *
 841  * Returns the size of the argument area on the stack.
 842  */
 843 int
 844 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 845 {
 846         int k;
 847         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 848         guint32 args_size = cinfo->stack_usage;
 849
 850         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 851         if (csig->hasthis) {
 852                 arg_info [0].offset = 0;
 853         }
 854
 855         for (k = 0; k < param_count; k++) {
 856                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 857                 /* FIXME: */
 858                 arg_info [k + 1].size = 0;
 859         }
 860
 861         g_free (cinfo);
 862
 863         return args_size;
 864 }
 865
 866 static int
 867 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 868 {
 869 #ifndef _MSC_VER
 870         __asm__ __volatile__ ("cpuid"
 871                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 872                 : "a" (id));
 873 #else
 874         int info[4];
 875         __cpuid(info, id);
 876         *p_eax = info[0];
 877         *p_ebx = info[1];
 878         *p_ecx = info[2];
 879         *p_edx = info[3];
 880 #endif
 881         return 1;
 882 }
 883
 884 /*
 885  * Initialize the cpu to execute managed code.
 886  */
 887 void
 888 mono_arch_cpu_init (void)
 889 {
 890 #ifndef _MSC_VER
 891         guint16 fpcw;
 892
 893         /* spec compliance requires running with double precision */
 894         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 895         fpcw &= ~X86_FPCW_PRECC_MASK;
 896         fpcw |= X86_FPCW_PREC_DOUBLE;
 897         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 898         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 899 #else
 900         /* TODO: This is crashing on Win64 right now.
 901         * _control87 (_PC_53, MCW_PC);
 902         */
 903 #endif
 904 }
 905
 906 /*
 907  * Initialize architecture specific code.
 908  */
 909 void
 910 mono_arch_init (void)
 911 {
 912         InitializeCriticalSection (&mini_arch_mutex);
 913
 914         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 915         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 916         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 917 }
 918
 919 /*
 920  * Cleanup architecture specific code.
 921  */
 922 void
 923 mono_arch_cleanup (void)
 924 {
 925         DeleteCriticalSection (&mini_arch_mutex);
 926 }
 927
 928 /*
 929  * This function returns the optimizations supported on this cpu.
 930  */
 931 guint32
 932 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 933 {
 934         int eax, ebx, ecx, edx;
 935         guint32 opts = 0;
 936
 937         /* FIXME: AMD64 */
 938
 939         *exclude_mask = 0;
 940         /* Feature Flags function, flags returned in EDX. */
 941         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 942                 if (edx & (1 << 15)) {
 943                         opts |= MONO_OPT_CMOV;
 944                         if (edx & 1)
 945                                 opts |= MONO_OPT_FCMOV;
 946                         else
 947                                 *exclude_mask |= MONO_OPT_FCMOV;
 948                 } else
 949                         *exclude_mask |= MONO_OPT_CMOV;
 950         }
 951
 952         return opts;
 953 }
 954
 955 /*
 956  * This function test for all SSE functions supported.
 957  *
 958  * Returns a bitmask corresponding to all supported versions.
 959  *
 960  */
 961 guint32
 962 mono_arch_cpu_enumerate_simd_versions (void)
 963 {
 964         int eax, ebx, ecx, edx;
 965         guint32 sse_opts = 0;
 966
 967         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 968                 if (edx & (1 << 25))
 969                         sse_opts |= 1 << SIMD_VERSION_SSE1;
 970                 if (edx & (1 << 26))
 971                         sse_opts |= 1 << SIMD_VERSION_SSE2;
 972                 if (ecx & (1 << 0))
 973                         sse_opts |= 1 << SIMD_VERSION_SSE3;
 974                 if (ecx & (1 << 9))
 975                         sse_opts |= 1 << SIMD_VERSION_SSSE3;
 976                 if (ecx & (1 << 19))
 977                         sse_opts |= 1 << SIMD_VERSION_SSE41;
 978                 if (ecx & (1 << 20))
 979                         sse_opts |= 1 << SIMD_VERSION_SSE42;
 980         }
 981
 982         /* Yes, all this needs to be done to check for sse4a.
 983            See: "Amd: CPUID Specification"
 984          */
 985         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
 986                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
 987                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
 988                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
 989                         if (ecx & (1 << 6))
 990                                 sse_opts |= 1 << SIMD_VERSION_SSE4a;
 991                 }
 992         }
 993
 994         return sse_opts;
 995 }
 996
 997 GList *
 998 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 999 {
1000         GList *vars = NULL;
1001         int i;
1002
1003         for (i = 0; i < cfg->num_varinfo; i++) {
1004                 MonoInst *ins = cfg->varinfo [i];
1005                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1006
1007                 /* unused vars */
1008                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1009                         continue;
1010
1011                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1012                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1013                         continue;
1014
1015                 if (mono_is_regsize_var (ins->inst_vtype)) {
1016                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1017                         g_assert (i == vmv->idx);
1018                         vars = g_list_prepend (vars, vmv);
1019                 }
1020         }
1021
1022         vars = mono_varlist_sort (cfg, vars, 0);
1023
1024         return vars;
1025 }
1026
1027 /**
1028  * mono_arch_compute_omit_fp:
1029  *
1030  *   Determine whenever the frame pointer can be eliminated.
1031  */
1032 static void
1033 mono_arch_compute_omit_fp (MonoCompile *cfg)
1034 {
1035         MonoMethodSignature *sig;
1036         MonoMethodHeader *header;
1037         int i, locals_size;
1038         CallInfo *cinfo;
1039
1040         if (cfg->arch.omit_fp_computed)
1041                 return;
1042
1043         header = mono_method_get_header (cfg->method);
1044
1045         sig = mono_method_signature (cfg->method);
1046
1047         if (!cfg->arch.cinfo)
1048                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1049         cinfo = cfg->arch.cinfo;
1050
1051         /*
1052          * FIXME: Remove some of the restrictions.
1053          */
1054         cfg->arch.omit_fp = TRUE;
1055         cfg->arch.omit_fp_computed = TRUE;
1056
1057         if (cfg->disable_omit_fp)
1058                 cfg->arch.omit_fp = FALSE;
1059
1060         if (!debug_omit_fp ())
1061                 cfg->arch.omit_fp = FALSE;
1062         /*
1063         if (cfg->method->save_lmf)
1064                 cfg->arch.omit_fp = FALSE;
1065         */
1066         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1067                 cfg->arch.omit_fp = FALSE;
1068         if (header->num_clauses)
1069                 cfg->arch.omit_fp = FALSE;
1070         if (cfg->param_area)
1071                 cfg->arch.omit_fp = FALSE;
1072         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1073                 cfg->arch.omit_fp = FALSE;
1074         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1075                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1076                 cfg->arch.omit_fp = FALSE;
1077         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1078                 ArgInfo *ainfo = &cinfo->args [i];
1079
1080                 if (ainfo->storage == ArgOnStack) {
1081                         /*
1082                          * The stack offset can only be determined when the frame
1083                          * size is known.
1084                          */
1085                         cfg->arch.omit_fp = FALSE;
1086                 }
1087         }
1088
1089         locals_size = 0;
1090         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1091                 MonoInst *ins = cfg->varinfo [i];
1092                 int ialign;
1093
1094                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1095         }
1096 }
1097
1098 GList *
1099 mono_arch_get_global_int_regs (MonoCompile *cfg)
1100 {
1101         GList *regs = NULL;
1102
1103         mono_arch_compute_omit_fp (cfg);
1104
1105         if (cfg->globalra) {
1106                 if (cfg->arch.omit_fp)
1107                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1108
1109                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1110                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1111                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1112                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1113                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1114
1115                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1116                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1117                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1118                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1119                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1120                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1121                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1122                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1123         } else {
1124                 if (cfg->arch.omit_fp)
1125                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1126
1127                 /* We use the callee saved registers for global allocation */
1128                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1129                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1130                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1131                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1132                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1133 #ifdef HOST_WIN32
1134                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1135                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1136 #endif
1137         }
1138
1139         return regs;
1140 }
1141
1142 GList*
1143 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1144 {
1145         GList *regs = NULL;
1146         int i;
1147
1148         /* All XMM registers */
1149         for (i = 0; i < 16; ++i)
1150                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1151
1152         return regs;
1153 }
1154
1155 GList*
1156 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1157 {
1158         static GList *r = NULL;
1159
1160         if (r == NULL) {
1161                 GList *regs = NULL;
1162
1163                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1164                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1165                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1166                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1167                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1168                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1169
1170                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1171                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1172                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1173                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1174                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1175                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1176                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1177                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1178
1179                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1180         }
1181
1182         return r;
1183 }
1184
1185 GList*
1186 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1187 {
1188         int i;
1189         static GList *r = NULL;
1190
1191         if (r == NULL) {
1192                 GList *regs = NULL;
1193
1194                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1195                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1196
1197                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1198         }
1199
1200         return r;
1201 }
1202
1203 /*
1204  * mono_arch_regalloc_cost:
1205  *
1206  *  Return the cost, in number of memory references, of the action of
1207  * allocating the variable VMV into a register during global register
1208  * allocation.
1209  */
1210 guint32
1211 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1212 {
1213         MonoInst *ins = cfg->varinfo [vmv->idx];
1214
1215         if (cfg->method->save_lmf)
1216                 /* The register is already saved */
1217                 /* substract 1 for the invisible store in the prolog */
1218                 return (ins->opcode == OP_ARG) ? 0 : 1;
1219         else
1220                 /* push+pop */
1221                 return (ins->opcode == OP_ARG) ? 1 : 2;
1222 }
1223
1224 /*
1225  * mono_arch_fill_argument_info:
1226  *
1227  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1228  * of the method.
1229  */
1230 void
1231 mono_arch_fill_argument_info (MonoCompile *cfg)
1232 {
1233         MonoMethodSignature *sig;
1234         MonoMethodHeader *header;
1235         MonoInst *ins;
1236         int i;
1237         CallInfo *cinfo;
1238
1239         header = mono_method_get_header (cfg->method);
1240
1241         sig = mono_method_signature (cfg->method);
1242
1243         cinfo = cfg->arch.cinfo;
1244
1245         /*
1246          * Contrary to mono_arch_allocate_vars (), the information should describe
1247          * where the arguments are at the beginning of the method, not where they can be
1248          * accessed during the execution of the method. The later makes no sense for the
1249          * global register allocator, since a variable can be in more than one location.
1250          */
1251         if (sig->ret->type != MONO_TYPE_VOID) {
1252                 switch (cinfo->ret.storage) {
1253                 case ArgInIReg:
1254                 case ArgInFloatSSEReg:
1255                 case ArgInDoubleSSEReg:
1256                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1257                                 cfg->vret_addr->opcode = OP_REGVAR;
1258                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1259                         }
1260                         else {
1261                                 cfg->ret->opcode = OP_REGVAR;
1262                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1263                         }
1264                         break;
1265                 case ArgValuetypeInReg:
1266                         cfg->ret->opcode = OP_REGOFFSET;
1267                         cfg->ret->inst_basereg = -1;
1268                         cfg->ret->inst_offset = -1;
1269                         break;
1270                 default:
1271                         g_assert_not_reached ();
1272                 }
1273         }
1274
1275         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1276                 ArgInfo *ainfo = &cinfo->args [i];
1277                 MonoType *arg_type;
1278
1279                 ins = cfg->args [i];
1280
1281                 if (sig->hasthis && (i == 0))
1282                         arg_type = &mono_defaults.object_class->byval_arg;
1283                 else
1284                         arg_type = sig->params [i - sig->hasthis];
1285
1286                 switch (ainfo->storage) {
1287                 case ArgInIReg:
1288                 case ArgInFloatSSEReg:
1289                 case ArgInDoubleSSEReg:
1290                         ins->opcode = OP_REGVAR;
1291                         ins->inst_c0 = ainfo->reg;
1292                         break;
1293                 case ArgOnStack:
1294                         ins->opcode = OP_REGOFFSET;
1295                         ins->inst_basereg = -1;
1296                         ins->inst_offset = -1;
1297                         break;
1298                 case ArgValuetypeInReg:
1299                         /* Dummy */
1300                         ins->opcode = OP_NOP;
1301                         break;
1302                 default:
1303                         g_assert_not_reached ();
1304                 }
1305         }
1306 }
1307
1308 void
1309 mono_arch_allocate_vars (MonoCompile *cfg)
1310 {
1311         MonoMethodSignature *sig;
1312         MonoMethodHeader *header;
1313         MonoInst *ins;
1314         int i, offset;
1315         guint32 locals_stack_size, locals_stack_align;
1316         gint32 *offsets;
1317         CallInfo *cinfo;
1318
1319         header = mono_method_get_header (cfg->method);
1320
1321         sig = mono_method_signature (cfg->method);
1322
1323         cinfo = cfg->arch.cinfo;
1324
1325         mono_arch_compute_omit_fp (cfg);
1326
1327         /*
1328          * We use the ABI calling conventions for managed code as well.
1329          * Exception: valuetypes are only sometimes passed or returned in registers.
1330          */
1331
1332         /*
1333          * The stack looks like this:
1334          * <incoming arguments passed on the stack>
1335          * <return value>
1336          * <lmf/caller saved registers>
1337          * <locals>
1338          * <spill area>
1339          * <localloc area>  -> grows dynamically
1340          * <params area>
1341          */
1342
1343         if (cfg->arch.omit_fp) {
1344                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1345                 cfg->frame_reg = AMD64_RSP;
1346                 offset = 0;
1347         } else {
1348                 /* Locals are allocated backwards from %fp */
1349                 cfg->frame_reg = AMD64_RBP;
1350                 offset = 0;
1351         }
1352
1353         if (cfg->method->save_lmf) {
1354                 /* Reserve stack space for saving LMF */
1355                 if (cfg->arch.omit_fp) {
1356                         cfg->arch.lmf_offset = offset;
1357                         offset += sizeof (MonoLMF);
1358                 }
1359                 else {
1360                         offset += sizeof (MonoLMF);
1361                         cfg->arch.lmf_offset = -offset;
1362                 }
1363         } else {
1364                 if (cfg->arch.omit_fp)
1365                         cfg->arch.reg_save_area_offset = offset;
1366                 /* Reserve space for caller saved registers */
1367                 for (i = 0; i < AMD64_NREG; ++i)
1368                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1369                                 offset += sizeof (gpointer);
1370                         }
1371         }
1372
1373         if (sig->ret->type != MONO_TYPE_VOID) {
1374                 switch (cinfo->ret.storage) {
1375                 case ArgInIReg:
1376                 case ArgInFloatSSEReg:
1377                 case ArgInDoubleSSEReg:
1378                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1379                                 if (cfg->globalra) {
1380                                         cfg->vret_addr->opcode = OP_REGVAR;
1381                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1382                                 } else {
1383                                         /* The register is volatile */
1384                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1385                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1386                                         if (cfg->arch.omit_fp) {
1387                                                 cfg->vret_addr->inst_offset = offset;
1388                                                 offset += 8;
1389                                         } else {
1390                                                 offset += 8;
1391                                                 cfg->vret_addr->inst_offset = -offset;
1392                                         }
1393                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1394                                                 printf ("vret_addr =");
1395                                                 mono_print_ins (cfg->vret_addr);
1396                                         }
1397                                 }
1398                         }
1399                         else {
1400                                 cfg->ret->opcode = OP_REGVAR;
1401                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1402                         }
1403                         break;
1404                 case ArgValuetypeInReg:
1405                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1406                         cfg->ret->opcode = OP_REGOFFSET;
1407                         cfg->ret->inst_basereg = cfg->frame_reg;
1408                         if (cfg->arch.omit_fp) {
1409                                 cfg->ret->inst_offset = offset;
1410                                 offset += 16;
1411                         } else {
1412                                 offset += 16;
1413                                 cfg->ret->inst_offset = - offset;
1414                         }
1415                         break;
1416                 default:
1417                         g_assert_not_reached ();
1418                 }
1419                 if (!cfg->globalra)
1420                         cfg->ret->dreg = cfg->ret->inst_c0;
1421         }
1422
1423         /* Allocate locals */
1424         if (!cfg->globalra) {
1425                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1426                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1427                         char *mname = mono_method_full_name (cfg->method, TRUE);
1428                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1429                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1430                         g_free (mname);
1431                         return;
1432                 }
1433
1434                 if (locals_stack_align) {
1435                         offset += (locals_stack_align - 1);
1436                         offset &= ~(locals_stack_align - 1);
1437                 }
1438                 if (cfg->arch.omit_fp) {
1439                         cfg->locals_min_stack_offset = offset;
1440                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1441                 } else {
1442                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1443                         cfg->locals_max_stack_offset = - offset;
1444                 }
1445
1446                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1447                         if (offsets [i] != -1) {
1448                                 MonoInst *ins = cfg->varinfo [i];
1449                                 ins->opcode = OP_REGOFFSET;
1450                                 ins->inst_basereg = cfg->frame_reg;
1451                                 if (cfg->arch.omit_fp)
1452                                         ins->inst_offset = (offset + offsets [i]);
1453                                 else
1454                                         ins->inst_offset = - (offset + offsets [i]);
1455                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1456                         }
1457                 }
1458                 offset += locals_stack_size;
1459         }
1460
1461         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1462                 g_assert (!cfg->arch.omit_fp);
1463                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1464                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1465         }
1466
1467         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1468                 ins = cfg->args [i];
1469                 if (ins->opcode != OP_REGVAR) {
1470                         ArgInfo *ainfo = &cinfo->args [i];
1471                         gboolean inreg = TRUE;
1472                         MonoType *arg_type;
1473
1474                         if (sig->hasthis && (i == 0))
1475                                 arg_type = &mono_defaults.object_class->byval_arg;
1476                         else
1477                                 arg_type = sig->params [i - sig->hasthis];
1478
1479                         if (cfg->globalra) {
1480                                 /* The new allocator needs info about the original locations of the arguments */
1481                                 switch (ainfo->storage) {
1482                                 case ArgInIReg:
1483                                 case ArgInFloatSSEReg:
1484                                 case ArgInDoubleSSEReg:
1485                                         ins->opcode = OP_REGVAR;
1486                                         ins->inst_c0 = ainfo->reg;
1487                                         break;
1488                                 case ArgOnStack:
1489                                         g_assert (!cfg->arch.omit_fp);
1490                                         ins->opcode = OP_REGOFFSET;
1491                                         ins->inst_basereg = cfg->frame_reg;
1492                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1493                                         break;
1494                                 case ArgValuetypeInReg:
1495                                         ins->opcode = OP_REGOFFSET;
1496                                         ins->inst_basereg = cfg->frame_reg;
1497                                         /* These arguments are saved to the stack in the prolog */
1498                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1499                                         if (cfg->arch.omit_fp) {
1500                                                 ins->inst_offset = offset;
1501                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1502                                         } else {
1503                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1504                                                 ins->inst_offset = - offset;
1505                                         }
1506                                         break;
1507                                 default:
1508                                         g_assert_not_reached ();
1509                                 }
1510
1511                                 continue;
1512                         }
1513
1514                         /* FIXME: Allocate volatile arguments to registers */
1515                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1516                                 inreg = FALSE;
1517
1518                         /*
1519                          * Under AMD64, all registers used to pass arguments to functions
1520                          * are volatile across calls.
1521                          * FIXME: Optimize this.
1522                          */
1523                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1524                                 inreg = FALSE;
1525
1526                         ins->opcode = OP_REGOFFSET;
1527
1528                         switch (ainfo->storage) {
1529                         case ArgInIReg:
1530                         case ArgInFloatSSEReg:
1531                         case ArgInDoubleSSEReg:
1532                                 if (inreg) {
1533                                         ins->opcode = OP_REGVAR;
1534                                         ins->dreg = ainfo->reg;
1535                                 }
1536                                 break;
1537                         case ArgOnStack:
1538                                 g_assert (!cfg->arch.omit_fp);
1539                                 ins->opcode = OP_REGOFFSET;
1540                                 ins->inst_basereg = cfg->frame_reg;
1541                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1542                                 break;
1543                         case ArgValuetypeInReg:
1544                                 break;
1545                         case ArgValuetypeAddrInIReg: {
1546                                 MonoInst *indir;
1547                                 g_assert (!cfg->arch.omit_fp);
1548
1549                                 MONO_INST_NEW (cfg, indir, 0);
1550                                 indir->opcode = OP_REGOFFSET;
1551                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1552                                         indir->inst_basereg = cfg->frame_reg;
1553                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1554                                         offset += (sizeof (gpointer));
1555                                         indir->inst_offset = - offset;
1556                                 }
1557                                 else {
1558                                         indir->inst_basereg = cfg->frame_reg;
1559                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1560                                 }
1561
1562                                 ins->opcode = OP_VTARG_ADDR;
1563                                 ins->inst_left = indir;
1564
1565                                 break;
1566                         }
1567                         default:
1568                                 NOT_IMPLEMENTED;
1569                         }
1570
1571                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1572                                 ins->opcode = OP_REGOFFSET;
1573                                 ins->inst_basereg = cfg->frame_reg;
1574                                 /* These arguments are saved to the stack in the prolog */
1575                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1576                                 if (cfg->arch.omit_fp) {
1577                                         ins->inst_offset = offset;
1578                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1579                                         // Arguments are yet supported by the stack map creation code
1580                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1581                                 } else {
1582                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1583                                         ins->inst_offset = - offset;
1584                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1585                                 }
1586                         }
1587                 }
1588         }
1589
1590         cfg->stack_offset = offset;
1591 }
1592
1593 void
1594 mono_arch_create_vars (MonoCompile *cfg)
1595 {
1596         MonoMethodSignature *sig;
1597         CallInfo *cinfo;
1598
1599         sig = mono_method_signature (cfg->method);
1600
1601         if (!cfg->arch.cinfo)
1602                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1603         cinfo = cfg->arch.cinfo;
1604
1605         if (cinfo->ret.storage == ArgValuetypeInReg)
1606                 cfg->ret_var_is_local = TRUE;
1607
1608         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1609                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1610                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1611                         printf ("vret_addr = ");
1612                         mono_print_ins (cfg->vret_addr);
1613                 }
1614         }
1615
1616 #ifdef MONO_AMD64_NO_PUSHES
1617         /*
1618          * When this is set, we pass arguments on the stack by moves, and by allocating
1619          * a bigger stack frame, instead of pushes.
1620          * Pushes complicate exception handling because the arguments on the stack have
1621          * to be popped each time a frame is unwound. They also make fp elimination
1622          * impossible.
1623          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1624          * on a new frame which doesn't include a param area.
1625          */
1626         cfg->arch.no_pushes = TRUE;
1627 #endif
1628 }
1629
1630 static void
1631 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1632 {
1633         MonoInst *ins;
1634
1635         switch (storage) {
1636         case ArgInIReg:
1637                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1638                 ins->dreg = mono_alloc_ireg (cfg);
1639                 ins->sreg1 = tree->dreg;
1640                 MONO_ADD_INS (cfg->cbb, ins);
1641                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1642                 break;
1643         case ArgInFloatSSEReg:
1644                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1645                 ins->dreg = mono_alloc_freg (cfg);
1646                 ins->sreg1 = tree->dreg;
1647                 MONO_ADD_INS (cfg->cbb, ins);
1648
1649                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1650                 break;
1651         case ArgInDoubleSSEReg:
1652                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1653                 ins->dreg = mono_alloc_freg (cfg);
1654                 ins->sreg1 = tree->dreg;
1655                 MONO_ADD_INS (cfg->cbb, ins);
1656
1657                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1658
1659                 break;
1660         default:
1661                 g_assert_not_reached ();
1662         }
1663 }
1664
1665 static int
1666 arg_storage_to_load_membase (ArgStorage storage)
1667 {
1668         switch (storage) {
1669         case ArgInIReg:
1670                 return OP_LOAD_MEMBASE;
1671         case ArgInDoubleSSEReg:
1672                 return OP_LOADR8_MEMBASE;
1673         case ArgInFloatSSEReg:
1674                 return OP_LOADR4_MEMBASE;
1675         default:
1676                 g_assert_not_reached ();
1677         }
1678
1679         return -1;
1680 }
1681
1682 static void
1683 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1684 {
1685         MonoInst *arg;
1686         MonoMethodSignature *tmp_sig;
1687         MonoInst *sig_arg;
1688
1689         if (call->tail_call)
1690                 NOT_IMPLEMENTED;
1691
1692         /* FIXME: Add support for signature tokens to AOT */
1693         cfg->disable_aot = TRUE;
1694
1695         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1696
1697         /*
1698          * mono_ArgIterator_Setup assumes the signature cookie is
1699          * passed first and all the arguments which were before it are
1700          * passed on the stack after the signature. So compensate by
1701          * passing a different signature.
1702          */
1703         tmp_sig = mono_metadata_signature_dup (call->signature);
1704         tmp_sig->param_count -= call->signature->sentinelpos;
1705         tmp_sig->sentinelpos = 0;
1706         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1707
1708         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1709         sig_arg->dreg = mono_alloc_ireg (cfg);
1710         sig_arg->inst_p0 = tmp_sig;
1711         MONO_ADD_INS (cfg->cbb, sig_arg);
1712
1713         if (cfg->arch.no_pushes) {
1714                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1715         } else {
1716                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1717                 arg->sreg1 = sig_arg->dreg;
1718                 MONO_ADD_INS (cfg->cbb, arg);
1719         }
1720 }
1721
1722 static inline LLVMArgStorage
1723 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1724 {
1725         switch (storage) {
1726         case ArgInIReg:
1727                 return LLVMArgInIReg;
1728         case ArgNone:
1729                 return LLVMArgNone;
1730         default:
1731                 g_assert_not_reached ();
1732                 return LLVMArgNone;
1733         }
1734 }
1735
1736 #ifdef ENABLE_LLVM
1737 LLVMCallInfo*
1738 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1739 {
1740         int i, n;
1741         CallInfo *cinfo;
1742         ArgInfo *ainfo;
1743         int j;
1744         LLVMCallInfo *linfo;
1745
1746         n = sig->param_count + sig->hasthis;
1747
1748         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1749
1750         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1751
1752         /*
1753          * LLVM always uses the native ABI while we use our own ABI, the
1754          * only difference is the handling of vtypes:
1755          * - we only pass/receive them in registers in some cases, and only
1756          *   in 1 or 2 integer registers.
1757          */
1758         if (cinfo->ret.storage == ArgValuetypeInReg) {
1759                 if (sig->pinvoke) {
1760                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1761                         cfg->disable_llvm = TRUE;
1762                         return linfo;
1763                 }
1764
1765                 linfo->ret.storage = LLVMArgVtypeInReg;
1766                 for (j = 0; j < 2; ++j)
1767                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1768         }
1769
1770         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1771                 /* Vtype returned using a hidden argument */
1772                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1773         }
1774
1775         for (i = 0; i < n; ++i) {
1776                 ainfo = cinfo->args + i;
1777
1778                 linfo->args [i].storage = LLVMArgNone;
1779
1780                 switch (ainfo->storage) {
1781                 case ArgInIReg:
1782                         linfo->args [i].storage = LLVMArgInIReg;
1783                         break;
1784                 case ArgInDoubleSSEReg:
1785                 case ArgInFloatSSEReg:
1786                         linfo->args [i].storage = LLVMArgInFPReg;
1787                         break;
1788                 case ArgOnStack:
1789                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1790                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1791                         } else {
1792                                 linfo->args [i].storage = LLVMArgInIReg;
1793                                 if (!sig->params [i - sig->hasthis]->byref) {
1794                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1795                                                 linfo->args [i].storage = LLVMArgInFPReg;
1796                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1797                                                 linfo->args [i].storage = LLVMArgInFPReg;
1798                                         }
1799                                 }
1800                         }
1801                         break;
1802                 case ArgValuetypeInReg:
1803                         if (sig->pinvoke) {
1804                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1805                                 cfg->disable_llvm = TRUE;
1806                                 return linfo;
1807                         }
1808
1809                         linfo->args [i].storage = LLVMArgVtypeInReg;
1810                         for (j = 0; j < 2; ++j)
1811                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1812                         break;
1813                 default:
1814                         cfg->exception_message = g_strdup ("ainfo->storage");
1815                         cfg->disable_llvm = TRUE;
1816                         break;
1817                 }
1818         }
1819
1820         return linfo;
1821 }
1822 #endif
1823
1824 void
1825 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1826 {
1827         MonoInst *arg, *in;
1828         MonoMethodSignature *sig;
1829         int i, n, stack_size;
1830         CallInfo *cinfo;
1831         ArgInfo *ainfo;
1832
1833         stack_size = 0;
1834
1835         sig = call->signature;
1836         n = sig->param_count + sig->hasthis;
1837
1838         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1839
1840         if (COMPILE_LLVM (cfg)) {
1841                 /* We shouldn't be called in the llvm case */
1842                 cfg->disable_llvm = TRUE;
1843                 return;
1844         }
1845
1846         if (cinfo->need_stack_align) {
1847                 if (!cfg->arch.no_pushes)
1848                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1849         }
1850
1851         /*
1852          * Emit all arguments which are passed on the stack to prevent register
1853          * allocation problems.
1854          */
1855         if (cfg->arch.no_pushes) {
1856                 for (i = 0; i < n; ++i) {
1857                         MonoType *t;
1858                         ainfo = cinfo->args + i;
1859
1860                         in = call->args [i];
1861
1862                         if (sig->hasthis && i == 0)
1863                                 t = &mono_defaults.object_class->byval_arg;
1864                         else
1865                                 t = sig->params [i - sig->hasthis];
1866
1867                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1868                                 if (!t->byref) {
1869                                         if (t->type == MONO_TYPE_R4)
1870                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1871                                         else if (t->type == MONO_TYPE_R8)
1872                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1873                                         else
1874                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1875                                 } else {
1876                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1877                                 }
1878                         }
1879                 }
1880         }
1881
1882         /*
1883          * Emit all parameters passed in registers in non-reverse order for better readability
1884          * and to help the optimization in emit_prolog ().
1885          */
1886         for (i = 0; i < n; ++i) {
1887                 ainfo = cinfo->args + i;
1888
1889                 in = call->args [i];
1890
1891                 if (ainfo->storage == ArgInIReg)
1892                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1893         }
1894
1895         for (i = n - 1; i >= 0; --i) {
1896                 ainfo = cinfo->args + i;
1897
1898                 in = call->args [i];
1899
1900                 switch (ainfo->storage) {
1901                 case ArgInIReg:
1902                         /* Already done */
1903                         break;
1904                 case ArgInFloatSSEReg:
1905                 case ArgInDoubleSSEReg:
1906                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1907                         break;
1908                 case ArgOnStack:
1909                 case ArgValuetypeInReg:
1910                 case ArgValuetypeAddrInIReg:
1911                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1912                                 MonoInst *call_inst = (MonoInst*)call;
1913                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1914                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1915                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1916                                 guint32 align;
1917                                 guint32 size;
1918
1919                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1920                                         size = sizeof (MonoTypedRef);
1921                                         align = sizeof (gpointer);
1922                                 }
1923                                 else {
1924                                         if (sig->pinvoke)
1925                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1926                                         else {
1927                                                 /*
1928                                                  * Other backends use mono_type_stack_size (), but that
1929                                                  * aligns the size to 8, which is larger than the size of
1930                                                  * the source, leading to reads of invalid memory if the
1931                                                  * source is at the end of address space.
1932                                                  */
1933                                                 size = mono_class_value_size (in->klass, &align);
1934                                         }
1935                                 }
1936                                 g_assert (in->klass);
1937
1938                                 if (size > 0) {
1939                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1940                                         arg->sreg1 = in->dreg;
1941                                         arg->klass = in->klass;
1942                                         arg->backend.size = size;
1943                                         arg->inst_p0 = call;
1944                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1945                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1946
1947                                         MONO_ADD_INS (cfg->cbb, arg);
1948                                 }
1949                         } else {
1950                                 if (cfg->arch.no_pushes) {
1951                                         /* Already done */
1952                                 } else {
1953                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1954                                         arg->sreg1 = in->dreg;
1955                                         if (!sig->params [i - sig->hasthis]->byref) {
1956                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1957                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1958                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
1959                                                         arg->inst_destbasereg = X86_ESP;
1960                                                         arg->inst_offset = 0;
1961                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1962                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1963                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
1964                                                         arg->inst_destbasereg = X86_ESP;
1965                                                         arg->inst_offset = 0;
1966                                                 }
1967                                         }
1968                                         MONO_ADD_INS (cfg->cbb, arg);
1969                                 }
1970                         }
1971                         break;
1972                 default:
1973                         g_assert_not_reached ();
1974                 }
1975
1976                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1977                         /* Emit the signature cookie just before the implicit arguments */
1978                         emit_sig_cookie (cfg, call, cinfo);
1979         }
1980
1981         /* Handle the case where there are no implicit arguments */
1982         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1983                 emit_sig_cookie (cfg, call, cinfo);
1984
1985         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1986                 MonoInst *vtarg;
1987
1988                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1989                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1990                                 /*
1991                                  * Tell the JIT to use a more efficient calling convention: call using
1992                                  * OP_CALL, compute the result location after the call, and save the
1993                                  * result there.
1994                                  */
1995                                 call->vret_in_reg = TRUE;
1996                                 /*
1997                                  * Nullify the instruction computing the vret addr to enable
1998                                  * future optimizations.
1999                                  */
2000                                 if (call->vret_var)
2001                                         NULLIFY_INS (call->vret_var);
2002                         } else {
2003                                 if (call->tail_call)
2004                                         NOT_IMPLEMENTED;
2005                                 /*
2006                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2007                                  * the stack. Push the address here, so the call instruction can
2008                                  * access it.
2009                                  */
2010                                 if (!cfg->arch.vret_addr_loc) {
2011                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2012                                         /* Prevent it from being register allocated or optimized away */
2013                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2014                                 }
2015
2016                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2017                         }
2018                 }
2019                 else {
2020                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2021                         vtarg->sreg1 = call->vret_var->dreg;
2022                         vtarg->dreg = mono_alloc_preg (cfg);
2023                         MONO_ADD_INS (cfg->cbb, vtarg);
2024
2025                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2026                 }
2027         }
2028
2029 #ifdef HOST_WIN32
2030         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2031                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2032         }
2033 #endif
2034
2035         if (cfg->method->save_lmf) {
2036                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2037                 MONO_ADD_INS (cfg->cbb, arg);
2038         }
2039
2040         call->stack_usage = cinfo->stack_usage;
2041 }
2042
2043 void
2044 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2045 {
2046         MonoInst *arg;
2047         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2048         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2049         int size = ins->backend.size;
2050
2051         if (ainfo->storage == ArgValuetypeInReg) {
2052                 MonoInst *load;
2053                 int part;
2054
2055                 for (part = 0; part < 2; ++part) {
2056                         if (ainfo->pair_storage [part] == ArgNone)
2057                                 continue;
2058
2059                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2060                         load->inst_basereg = src->dreg;
2061                         load->inst_offset = part * sizeof (gpointer);
2062
2063                         switch (ainfo->pair_storage [part]) {
2064                         case ArgInIReg:
2065                                 load->dreg = mono_alloc_ireg (cfg);
2066                                 break;
2067                         case ArgInDoubleSSEReg:
2068                         case ArgInFloatSSEReg:
2069                                 load->dreg = mono_alloc_freg (cfg);
2070                                 break;
2071                         default:
2072                                 g_assert_not_reached ();
2073                         }
2074                         MONO_ADD_INS (cfg->cbb, load);
2075
2076                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2077                 }
2078         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2079                 MonoInst *vtaddr, *load;
2080                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2081
2082                 g_assert (!cfg->arch.no_pushes);
2083
2084                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2085                 load->inst_p0 = vtaddr;
2086                 vtaddr->flags |= MONO_INST_INDIRECT;
2087                 load->type = STACK_MP;
2088                 load->klass = vtaddr->klass;
2089                 load->dreg = mono_alloc_ireg (cfg);
2090                 MONO_ADD_INS (cfg->cbb, load);
2091                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2092
2093                 if (ainfo->pair_storage [0] == ArgInIReg) {
2094                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2095                         arg->dreg = mono_alloc_ireg (cfg);
2096                         arg->sreg1 = load->dreg;
2097                         arg->inst_imm = 0;
2098                         MONO_ADD_INS (cfg->cbb, arg);
2099                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2100                 } else {
2101                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2102                         arg->sreg1 = load->dreg;
2103                         MONO_ADD_INS (cfg->cbb, arg);
2104                 }
2105         } else {
2106                 if (size == 8) {
2107                         if (cfg->arch.no_pushes) {
2108                                 int dreg = mono_alloc_ireg (cfg);
2109
2110                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2111                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2112                         } else {
2113                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2114                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2115                                 arg->inst_basereg = src->dreg;
2116                                 arg->inst_offset = 0;
2117                                 MONO_ADD_INS (cfg->cbb, arg);
2118                         }
2119                 } else if (size <= 40) {
2120                         if (cfg->arch.no_pushes) {
2121                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2122                         } else {
2123                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2124                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2125                         }
2126                 } else {
2127                         if (cfg->arch.no_pushes) {
2128                                 // FIXME: Code growth
2129                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2130                         } else {
2131                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2132                                 arg->inst_basereg = src->dreg;
2133                                 arg->inst_offset = 0;
2134                                 arg->inst_imm = size;
2135                                 MONO_ADD_INS (cfg->cbb, arg);
2136                         }
2137                 }
2138         }
2139 }
2140
2141 void
2142 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2143 {
2144         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2145
2146         if (!ret->byref) {
2147                 if (ret->type == MONO_TYPE_R4) {
2148                         if (COMPILE_LLVM (cfg))
2149                                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2150                         else
2151                                 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2152                         return;
2153                 } else if (ret->type == MONO_TYPE_R8) {
2154                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2155                         return;
2156                 }
2157         }
2158
2159         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2160 }
2161
2162 #define EMIT_COND_BRANCH(ins,cond,sign) \
2163         if (ins->inst_true_bb->native_offset) { \
2164                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2165         } else { \
2166                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2167                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2168             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2169                         x86_branch8 (code, cond, 0, sign); \
2170                 else \
2171                         x86_branch32 (code, cond, 0, sign); \
2172 }
2173
2174 typedef struct {
2175         MonoMethodSignature *sig;
2176         CallInfo *cinfo;
2177 } ArchDynCallInfo;
2178
2179 typedef struct {
2180         mgreg_t regs [PARAM_REGS];
2181         mgreg_t res;
2182         guint8 *ret;
2183 } DynCallArgs;
2184
2185 static gboolean
2186 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2187 {
2188         int i;
2189
2190 #ifdef HOST_WIN32
2191         return FALSE;
2192 #endif
2193
2194         switch (cinfo->ret.storage) {
2195         case ArgNone:
2196         case ArgInIReg:
2197                 break;
2198         case ArgValuetypeInReg: {
2199                 ArgInfo *ainfo = &cinfo->ret;
2200
2201                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2202                         return FALSE;
2203                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2204                         return FALSE;
2205                 break;
2206         }
2207         default:
2208                 return FALSE;
2209         }
2210
2211         for (i = 0; i < cinfo->nargs; ++i) {
2212                 ArgInfo *ainfo = &cinfo->args [i];
2213                 switch (ainfo->storage) {
2214                 case ArgInIReg:
2215                         break;
2216                 case ArgValuetypeInReg:
2217                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2218                                 return FALSE;
2219                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2220                                 return FALSE;
2221                         break;
2222                 default:
2223                         return FALSE;
2224                 }
2225         }
2226
2227         return TRUE;
2228 }
2229
2230 /*
2231  * mono_arch_dyn_call_prepare:
2232  *
2233  *   Return a pointer to an arch-specific structure which contains information
2234  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2235  * supported for SIG.
2236  * This function is equivalent to ffi_prep_cif in libffi.
2237  */
2238 MonoDynCallInfo*
2239 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2240 {
2241         ArchDynCallInfo *info;
2242         CallInfo *cinfo;
2243
2244         cinfo = get_call_info (NULL, NULL, sig, FALSE);
2245
2246         if (!dyn_call_supported (sig, cinfo)) {
2247                 g_free (cinfo);
2248                 return NULL;
2249         }
2250
2251         info = g_new0 (ArchDynCallInfo, 1);
2252         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2253         info->sig = sig;
2254         info->cinfo = cinfo;
2255
2256         return (MonoDynCallInfo*)info;
2257 }
2258
2259 /*
2260  * mono_arch_dyn_call_free:
2261  *
2262  *   Free a MonoDynCallInfo structure.
2263  */
2264 void
2265 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2266 {
2267         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2268
2269         g_free (ainfo->cinfo);
2270         g_free (ainfo);
2271 }
2272
2273 /*
2274  * mono_arch_get_start_dyn_call:
2275  *
2276  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2277  * store the result into BUF.
2278  * ARGS should be an array of pointers pointing to the arguments.
2279  * RET should point to a memory buffer large enought to hold the result of the
2280  * call.
2281  * This function should be as fast as possible, any work which does not depend
2282  * on the actual values of the arguments should be done in
2283  * mono_arch_dyn_call_prepare ().
2284  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2285  * libffi.
2286  */
2287 void
2288 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2289 {
2290         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2291         DynCallArgs *p = (DynCallArgs*)buf;
2292         int arg_index, greg, i;
2293         MonoMethodSignature *sig = dinfo->sig;
2294
2295         g_assert (buf_len >= sizeof (DynCallArgs));
2296
2297         p->res = 0;
2298         p->ret = ret;
2299
2300         arg_index = 0;
2301         greg = 0;
2302
2303         if (dinfo->cinfo->vtype_retaddr)
2304                 p->regs [greg ++] = (mgreg_t)ret;
2305
2306         if (sig->hasthis) {
2307                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2308         }
2309
2310         for (i = 0; i < sig->param_count; i++) {
2311                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2312                 gpointer *arg = args [arg_index ++];
2313
2314                 if (t->byref) {
2315                         p->regs [greg ++] = (mgreg_t)*(arg);
2316                         continue;
2317                 }
2318
2319                 switch (t->type) {
2320                 case MONO_TYPE_STRING:
2321                 case MONO_TYPE_CLASS:
2322                 case MONO_TYPE_ARRAY:
2323                 case MONO_TYPE_SZARRAY:
2324                 case MONO_TYPE_OBJECT:
2325                 case MONO_TYPE_PTR:
2326                 case MONO_TYPE_I:
2327                 case MONO_TYPE_U:
2328                 case MONO_TYPE_I8:
2329                 case MONO_TYPE_U8:
2330                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2331                         p->regs [greg ++] = (mgreg_t)*(arg);
2332                         break;
2333                 case MONO_TYPE_BOOLEAN:
2334                 case MONO_TYPE_U1:
2335                         p->regs [greg ++] = *(guint8*)(arg);
2336                         break;
2337                 case MONO_TYPE_I1:
2338                         p->regs [greg ++] = *(gint8*)(arg);
2339                         break;
2340                 case MONO_TYPE_I2:
2341                         p->regs [greg ++] = *(gint16*)(arg);
2342                         break;
2343                 case MONO_TYPE_U2:
2344                 case MONO_TYPE_CHAR:
2345                         p->regs [greg ++] = *(guint16*)(arg);
2346                         break;
2347                 case MONO_TYPE_I4:
2348                         p->regs [greg ++] = *(gint32*)(arg);
2349                         break;
2350                 case MONO_TYPE_U4:
2351                         p->regs [greg ++] = *(guint32*)(arg);
2352                         break;
2353                 case MONO_TYPE_GENERICINST:
2354                     if (MONO_TYPE_IS_REFERENCE (t)) {
2355                                 p->regs [greg ++] = (mgreg_t)*(arg);
2356                                 break;
2357                         } else {
2358                                 /* Fall through */
2359                         }
2360                 case MONO_TYPE_VALUETYPE: {
2361                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2362
2363                         g_assert (ainfo->storage == ArgValuetypeInReg);
2364                         if (ainfo->pair_storage [0] != ArgNone) {
2365                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2366                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2367                         }
2368                         if (ainfo->pair_storage [1] != ArgNone) {
2369                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2370                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2371                         }
2372                         break;
2373                 }
2374                 default:
2375                         g_assert_not_reached ();
2376                 }
2377         }
2378
2379         g_assert (greg <= PARAM_REGS);
2380 }
2381
2382 /*
2383  * mono_arch_finish_dyn_call:
2384  *
2385  *   Store the result of a dyn call into the return value buffer passed to
2386  * start_dyn_call ().
2387  * This function should be as fast as possible, any work which does not depend
2388  * on the actual values of the arguments should be done in
2389  * mono_arch_dyn_call_prepare ().
2390  */
2391 void
2392 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2393 {
2394         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2395         MonoMethodSignature *sig = dinfo->sig;
2396         guint8 *ret = ((DynCallArgs*)buf)->ret;
2397         mgreg_t res = ((DynCallArgs*)buf)->res;
2398
2399         switch (mono_type_get_underlying_type (sig->ret)->type) {
2400         case MONO_TYPE_VOID:
2401                 *(gpointer*)ret = NULL;
2402                 break;
2403         case MONO_TYPE_STRING:
2404         case MONO_TYPE_CLASS:
2405         case MONO_TYPE_ARRAY:
2406         case MONO_TYPE_SZARRAY:
2407         case MONO_TYPE_OBJECT:
2408         case MONO_TYPE_I:
2409         case MONO_TYPE_U:
2410         case MONO_TYPE_PTR:
2411                 *(gpointer*)ret = (gpointer)res;
2412                 break;
2413         case MONO_TYPE_I1:
2414                 *(gint8*)ret = res;
2415                 break;
2416         case MONO_TYPE_U1:
2417         case MONO_TYPE_BOOLEAN:
2418                 *(guint8*)ret = res;
2419                 break;
2420         case MONO_TYPE_I2:
2421                 *(gint16*)ret = res;
2422                 break;
2423         case MONO_TYPE_U2:
2424         case MONO_TYPE_CHAR:
2425                 *(guint16*)ret = res;
2426                 break;
2427         case MONO_TYPE_I4:
2428                 *(gint32*)ret = res;
2429                 break;
2430         case MONO_TYPE_U4:
2431                 *(guint32*)ret = res;
2432                 break;
2433         case MONO_TYPE_I8:
2434                 *(gint64*)ret = res;
2435                 break;
2436         case MONO_TYPE_U8:
2437                 *(guint64*)ret = res;
2438                 break;
2439         case MONO_TYPE_GENERICINST:
2440                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2441                         *(gpointer*)ret = (gpointer)res;
2442                         break;
2443                 } else {
2444                         /* Fall through */
2445                 }
2446         case MONO_TYPE_VALUETYPE:
2447                 if (dinfo->cinfo->vtype_retaddr) {
2448                         /* Nothing to do */
2449                 } else {
2450                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2451
2452                         g_assert (ainfo->storage == ArgValuetypeInReg);
2453
2454                         if (ainfo->pair_storage [0] != ArgNone) {
2455                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2456                                 ((mgreg_t*)ret)[0] = res;
2457                         }
2458
2459                         g_assert (ainfo->pair_storage [1] == ArgNone);
2460                 }
2461                 break;
2462         default:
2463                 g_assert_not_reached ();
2464         }
2465 }
2466
2467 /* emit an exception if condition is fail */
2468 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2469         do {                                                        \
2470                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2471                 if (tins == NULL) {                                                                             \
2472                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2473                                         MONO_PATCH_INFO_EXC, exc_name);  \
2474                         x86_branch32 (code, cond, 0, signed);               \
2475                 } else {        \
2476                         EMIT_COND_BRANCH (tins, cond, signed);  \
2477                 }                       \
2478         } while (0);
2479
2480 #define EMIT_FPCOMPARE(code) do { \
2481         amd64_fcompp (code); \
2482         amd64_fnstsw (code); \
2483 } while (0);
2484
2485 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2486     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2487         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2488         amd64_ ##op (code); \
2489         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2490         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2491 } while (0);
2492
2493 static guint8*
2494 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2495 {
2496         gboolean no_patch = FALSE;
2497
2498         /*
2499          * FIXME: Add support for thunks
2500          */
2501         {
2502                 gboolean near_call = FALSE;
2503
2504                 /*
2505                  * Indirect calls are expensive so try to make a near call if possible.
2506                  * The caller memory is allocated by the code manager so it is
2507                  * guaranteed to be at a 32 bit offset.
2508                  */
2509
2510                 if (patch_type != MONO_PATCH_INFO_ABS) {
2511                         /* The target is in memory allocated using the code manager */
2512                         near_call = TRUE;
2513
2514                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2515                                 if (((MonoMethod*)data)->klass->image->aot_module)
2516                                         /* The callee might be an AOT method */
2517                                         near_call = FALSE;
2518                                 if (((MonoMethod*)data)->dynamic)
2519                                         /* The target is in malloc-ed memory */
2520                                         near_call = FALSE;
2521                         }
2522
2523                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2524                                 /*
2525                                  * The call might go directly to a native function without
2526                                  * the wrapper.
2527                                  */
2528                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2529                                 if (mi) {
2530                                         gconstpointer target = mono_icall_get_wrapper (mi);
2531                                         if ((((guint64)target) >> 32) != 0)
2532                                                 near_call = FALSE;
2533                                 }
2534                         }
2535                 }
2536                 else {
2537                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2538                                 /*
2539                                  * This is not really an optimization, but required because the
2540                                  * generic class init trampolines use R11 to pass the vtable.
2541                                  */
2542                                 near_call = TRUE;
2543                         } else {
2544                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2545                                 if (info) {
2546                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2547                                                 strstr (cfg->method->name, info->name)) {
2548                                                 /* A call to the wrapped function */
2549                                                 if ((((guint64)data) >> 32) == 0)
2550                                                         near_call = TRUE;
2551                                                 no_patch = TRUE;
2552                                         }
2553                                         else if (info->func == info->wrapper) {
2554                                                 /* No wrapper */
2555                                                 if ((((guint64)info->func) >> 32) == 0)
2556                                                         near_call = TRUE;
2557                                         }
2558                                         else {
2559                                                 /* See the comment in mono_codegen () */
2560                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2561                                                         near_call = TRUE;
2562                                         }
2563                                 }
2564                                 else if ((((guint64)data) >> 32) == 0) {
2565                                         near_call = TRUE;
2566                                         no_patch = TRUE;
2567                                 }
2568                         }
2569                 }
2570
2571                 if (cfg->method->dynamic)
2572                         /* These methods are allocated using malloc */
2573                         near_call = FALSE;
2574
2575                 if (cfg->compile_aot) {
2576                         near_call = TRUE;
2577                         no_patch = TRUE;
2578                 }
2579
2580 #ifdef MONO_ARCH_NOMAP32BIT
2581                 near_call = FALSE;
2582 #endif
2583
2584                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2585                 if (optimize_for_xen)
2586                         near_call = FALSE;
2587
2588                 if (near_call) {
2589                         /*
2590                          * Align the call displacement to an address divisible by 4 so it does
2591                          * not span cache lines. This is required for code patching to work on SMP
2592                          * systems.
2593                          */
2594                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2595                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2596                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2597                         amd64_call_code (code, 0);
2598                 }
2599                 else {
2600                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2601                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2602                         amd64_call_reg (code, GP_SCRATCH_REG);
2603                 }
2604         }
2605
2606         return code;
2607 }
2608
2609 static inline guint8*
2610 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2611 {
2612 #ifdef HOST_WIN32
2613         if (win64_adjust_stack)
2614                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2615 #endif
2616         code = emit_call_body (cfg, code, patch_type, data);
2617 #ifdef HOST_WIN32
2618         if (win64_adjust_stack)
2619                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2620 #endif
2621
2622         return code;
2623 }
2624
2625 static inline int
2626 store_membase_imm_to_store_membase_reg (int opcode)
2627 {
2628         switch (opcode) {
2629         case OP_STORE_MEMBASE_IMM:
2630                 return OP_STORE_MEMBASE_REG;
2631         case OP_STOREI4_MEMBASE_IMM:
2632                 return OP_STOREI4_MEMBASE_REG;
2633         case OP_STOREI8_MEMBASE_IMM:
2634                 return OP_STOREI8_MEMBASE_REG;
2635         }
2636
2637         return -1;
2638 }
2639
2640 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2641
2642 /*
2643  * mono_arch_peephole_pass_1:
2644  *
2645  *   Perform peephole opts which should/can be performed before local regalloc
2646  */
2647 void
2648 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2649 {
2650         MonoInst *ins, *n;
2651
2652         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2653                 MonoInst *last_ins = ins->prev;
2654
2655                 switch (ins->opcode) {
2656                 case OP_ADD_IMM:
2657                 case OP_IADD_IMM:
2658                 case OP_LADD_IMM:
2659                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2660                                 /*
2661                                  * X86_LEA is like ADD, but doesn't have the
2662                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2663                                  * its operand to 64 bit.
2664                                  */
2665                                 ins->opcode = OP_X86_LEA_MEMBASE;
2666                                 ins->inst_basereg = ins->sreg1;
2667                         }
2668                         break;
2669                 case OP_LXOR:
2670                 case OP_IXOR:
2671                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2672                                 MonoInst *ins2;
2673
2674                                 /*
2675                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2676                                  * the latter has length 2-3 instead of 6 (reverse constant
2677                                  * propagation). These instruction sequences are very common
2678                                  * in the initlocals bblock.
2679                                  */
2680                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2681                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2682                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2683                                                 ins2->sreg1 = ins->dreg;
2684                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2685                                                 /* Continue */
2686                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2687                                                 NULLIFY_INS (ins2);
2688                                                 /* Continue */
2689                                         } else {
2690                                                 break;
2691                                         }
2692                                 }
2693                         }
2694                         break;
2695                 case OP_COMPARE_IMM:
2696                 case OP_LCOMPARE_IMM:
2697                         /* OP_COMPARE_IMM (reg, 0)
2698                          * -->
2699                          * OP_AMD64_TEST_NULL (reg)
2700                          */
2701                         if (!ins->inst_imm)
2702                                 ins->opcode = OP_AMD64_TEST_NULL;
2703                         break;
2704                 case OP_ICOMPARE_IMM:
2705                         if (!ins->inst_imm)
2706                                 ins->opcode = OP_X86_TEST_NULL;
2707                         break;
2708                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2709                         /*
2710                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2711                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2712                          * -->
2713                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2714                          * OP_COMPARE_IMM reg, imm
2715                          *
2716                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2717                          */
2718                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2719                             ins->inst_basereg == last_ins->inst_destbasereg &&
2720                             ins->inst_offset == last_ins->inst_offset) {
2721                                         ins->opcode = OP_ICOMPARE_IMM;
2722                                         ins->sreg1 = last_ins->sreg1;
2723
2724                                         /* check if we can remove cmp reg,0 with test null */
2725                                         if (!ins->inst_imm)
2726                                                 ins->opcode = OP_X86_TEST_NULL;
2727                                 }
2728
2729                         break;
2730                 }
2731
2732                 mono_peephole_ins (bb, ins);
2733         }
2734 }
2735
2736 void
2737 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2738 {
2739         MonoInst *ins, *n;
2740
2741         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2742                 switch (ins->opcode) {
2743                 case OP_ICONST:
2744                 case OP_I8CONST: {
2745                         /* reg = 0 -> XOR (reg, reg) */
2746                         /* XOR sets cflags on x86, so we cant do it always */
2747                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2748                                 ins->opcode = OP_LXOR;
2749                                 ins->sreg1 = ins->dreg;
2750                                 ins->sreg2 = ins->dreg;
2751                                 /* Fall through */
2752                         } else {
2753                                 break;
2754                         }
2755                 }
2756                 case OP_LXOR:
2757                         /*
2758                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2759                          * 0 result into 64 bits.
2760                          */
2761                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2762                                 ins->opcode = OP_IXOR;
2763                         }
2764                         /* Fall through */
2765                 case OP_IXOR:
2766                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2767                                 MonoInst *ins2;
2768
2769                                 /*
2770                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2771                                  * the latter has length 2-3 instead of 6 (reverse constant
2772                                  * propagation). These instruction sequences are very common
2773                                  * in the initlocals bblock.
2774                                  */
2775                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2776                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2777                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2778                                                 ins2->sreg1 = ins->dreg;
2779                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2780                                                 /* Continue */
2781                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2782                                                 NULLIFY_INS (ins2);
2783                                                 /* Continue */
2784                                         } else {
2785                                                 break;
2786                                         }
2787                                 }
2788                         }
2789                         break;
2790                 case OP_IADD_IMM:
2791                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2792                                 ins->opcode = OP_X86_INC_REG;
2793                         break;
2794                 case OP_ISUB_IMM:
2795                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2796                                 ins->opcode = OP_X86_DEC_REG;
2797                         break;
2798                 }
2799
2800                 mono_peephole_ins (bb, ins);
2801         }
2802 }
2803
2804 #define NEW_INS(cfg,ins,dest,op) do {   \
2805                 MONO_INST_NEW ((cfg), (dest), (op)); \
2806         (dest)->cil_code = (ins)->cil_code; \
2807         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2808         } while (0)
2809
2810 /*
2811  * mono_arch_lowering_pass:
2812  *
2813  *  Converts complex opcodes into simpler ones so that each IR instruction
2814  * corresponds to one machine instruction.
2815  */
2816 void
2817 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2818 {
2819         MonoInst *ins, *n, *temp;
2820
2821         /*
2822          * FIXME: Need to add more instructions, but the current machine
2823          * description can't model some parts of the composite instructions like
2824          * cdq.
2825          */
2826         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2827                 switch (ins->opcode) {
2828                 case OP_DIV_IMM:
2829                 case OP_REM_IMM:
2830                 case OP_IDIV_IMM:
2831                 case OP_IDIV_UN_IMM:
2832                 case OP_IREM_UN_IMM:
2833                         mono_decompose_op_imm (cfg, bb, ins);
2834                         break;
2835                 case OP_IREM_IMM:
2836                         /* Keep the opcode if we can implement it efficiently */
2837                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2838                                 mono_decompose_op_imm (cfg, bb, ins);
2839                         break;
2840                 case OP_COMPARE_IMM:
2841                 case OP_LCOMPARE_IMM:
2842                         if (!amd64_is_imm32 (ins->inst_imm)) {
2843                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2844                                 temp->inst_c0 = ins->inst_imm;
2845                                 temp->dreg = mono_alloc_ireg (cfg);
2846                                 ins->opcode = OP_COMPARE;
2847                                 ins->sreg2 = temp->dreg;
2848                         }
2849                         break;
2850                 case OP_LOAD_MEMBASE:
2851                 case OP_LOADI8_MEMBASE:
2852                         if (!amd64_is_imm32 (ins->inst_offset)) {
2853                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2854                                 temp->inst_c0 = ins->inst_offset;
2855                                 temp->dreg = mono_alloc_ireg (cfg);
2856                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2857                                 ins->inst_indexreg = temp->dreg;
2858                         }
2859                         break;
2860                 case OP_STORE_MEMBASE_IMM:
2861                 case OP_STOREI8_MEMBASE_IMM:
2862                         if (!amd64_is_imm32 (ins->inst_imm)) {
2863                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2864                                 temp->inst_c0 = ins->inst_imm;
2865                                 temp->dreg = mono_alloc_ireg (cfg);
2866                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2867                                 ins->sreg1 = temp->dreg;
2868                         }
2869                         break;
2870 #ifdef MONO_ARCH_SIMD_INTRINSICS
2871                 case OP_EXPAND_I1: {
2872                                 int temp_reg1 = mono_alloc_ireg (cfg);
2873                                 int temp_reg2 = mono_alloc_ireg (cfg);
2874                                 int original_reg = ins->sreg1;
2875
2876                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2877                                 temp->sreg1 = original_reg;
2878                                 temp->dreg = temp_reg1;
2879
2880                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2881                                 temp->sreg1 = temp_reg1;
2882                                 temp->dreg = temp_reg2;
2883                                 temp->inst_imm = 8;
2884
2885                                 NEW_INS (cfg, ins, temp, OP_LOR);
2886                                 temp->sreg1 = temp->dreg = temp_reg2;
2887                                 temp->sreg2 = temp_reg1;
2888
2889                                 ins->opcode = OP_EXPAND_I2;
2890                                 ins->sreg1 = temp_reg2;
2891                         }
2892                         break;
2893 #endif
2894                 default:
2895                         break;
2896                 }
2897         }
2898
2899         bb->max_vreg = cfg->next_vreg;
2900 }
2901
2902 static const int
2903 branch_cc_table [] = {
2904         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2905         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2906         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2907 };
2908
2909 /* Maps CMP_... constants to X86_CC_... constants */
2910 static const int
2911 cc_table [] = {
2912         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2913         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2914 };
2915
2916 static const int
2917 cc_signed_table [] = {
2918         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2919         FALSE, FALSE, FALSE, FALSE
2920 };
2921
2922 /*#include "cprop.c"*/
2923
2924 static unsigned char*
2925 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2926 {
2927         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2928
2929         if (size == 1)
2930                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2931         else if (size == 2)
2932                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2933         return code;
2934 }
2935
2936 static unsigned char*
2937 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2938 {
2939         int sreg = tree->sreg1;
2940         int need_touch = FALSE;
2941
2942 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2943         if (!tree->flags & MONO_INST_INIT)
2944                 need_touch = TRUE;
2945 #endif
2946
2947         if (need_touch) {
2948                 guint8* br[5];
2949
2950                 /*
2951                  * Under Windows:
2952                  * If requested stack size is larger than one page,
2953                  * perform stack-touch operation
2954                  */
2955                 /*
2956                  * Generate stack probe code.
2957                  * Under Windows, it is necessary to allocate one page at a time,
2958                  * "touching" stack after each successful sub-allocation. This is
2959                  * because of the way stack growth is implemented - there is a
2960                  * guard page before the lowest stack page that is currently commited.
2961                  * Stack normally grows sequentially so OS traps access to the
2962                  * guard page and commits more pages when needed.
2963                  */
2964                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2965                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2966
2967                 br[2] = code; /* loop */
2968                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2969                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2970                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2971                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2972                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2973                 amd64_patch (br[3], br[2]);
2974                 amd64_test_reg_reg (code, sreg, sreg);
2975                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2976                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2977
2978                 br[1] = code; x86_jump8 (code, 0);
2979
2980                 amd64_patch (br[0], code);
2981                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2982                 amd64_patch (br[1], code);
2983                 amd64_patch (br[4], code);
2984         }
2985         else
2986                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2987
2988         if (tree->flags & MONO_INST_INIT) {
2989                 int offset = 0;
2990                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2991                         amd64_push_reg (code, AMD64_RAX);
2992                         offset += 8;
2993                 }
2994                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2995                         amd64_push_reg (code, AMD64_RCX);
2996                         offset += 8;
2997                 }
2998                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2999                         amd64_push_reg (code, AMD64_RDI);
3000                         offset += 8;
3001                 }
3002
3003                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3004                 if (sreg != AMD64_RCX)
3005                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3006                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3007
3008                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3009                 if (cfg->param_area && cfg->arch.no_pushes)
3010                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3011                 amd64_cld (code);
3012                 amd64_prefix (code, X86_REP_PREFIX);
3013                 amd64_stosl (code);
3014
3015                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3016                         amd64_pop_reg (code, AMD64_RDI);
3017                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3018                         amd64_pop_reg (code, AMD64_RCX);
3019                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3020                         amd64_pop_reg (code, AMD64_RAX);
3021         }
3022         return code;
3023 }
3024
3025 static guint8*
3026 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3027 {
3028         CallInfo *cinfo;
3029         guint32 quad;
3030
3031         /* Move return value to the target register */
3032         /* FIXME: do this in the local reg allocator */
3033         switch (ins->opcode) {
3034         case OP_CALL:
3035         case OP_CALL_REG:
3036         case OP_CALL_MEMBASE:
3037         case OP_LCALL:
3038         case OP_LCALL_REG:
3039         case OP_LCALL_MEMBASE:
3040                 g_assert (ins->dreg == AMD64_RAX);
3041                 break;
3042         case OP_FCALL:
3043         case OP_FCALL_REG:
3044         case OP_FCALL_MEMBASE:
3045                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3046                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3047                 }
3048                 else {
3049                         if (ins->dreg != AMD64_XMM0)
3050                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3051                 }
3052                 break;
3053         case OP_VCALL:
3054         case OP_VCALL_REG:
3055         case OP_VCALL_MEMBASE:
3056         case OP_VCALL2:
3057         case OP_VCALL2_REG:
3058         case OP_VCALL2_MEMBASE:
3059                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3060                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3061                         MonoInst *loc = cfg->arch.vret_addr_loc;
3062
3063                         /* Load the destination address */
3064                         g_assert (loc->opcode == OP_REGOFFSET);
3065                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3066
3067                         for (quad = 0; quad < 2; quad ++) {
3068                                 switch (cinfo->ret.pair_storage [quad]) {
3069                                 case ArgInIReg:
3070                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3071                                         break;
3072                                 case ArgInFloatSSEReg:
3073                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3074                                         break;
3075                                 case ArgInDoubleSSEReg:
3076                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3077                                         break;
3078                                 case ArgNone:
3079                                         break;
3080                                 default:
3081                                         NOT_IMPLEMENTED;
3082                                 }
3083                         }
3084                 }
3085                 break;
3086         }
3087
3088         return code;
3089 }
3090
3091 /*
3092  * mono_amd64_emit_tls_get:
3093  * @code: buffer to store code to
3094  * @dreg: hard register where to place the result
3095  * @tls_offset: offset info
3096  *
3097  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3098  * the dreg register the item in the thread local storage identified
3099  * by tls_offset.
3100  *
3101  * Returns: a pointer to the end of the stored code
3102  */
3103 guint8*
3104 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3105 {
3106 #ifdef HOST_WIN32
3107         g_assert (tls_offset < 64);
3108         x86_prefix (code, X86_GS_PREFIX);
3109         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3110 #else
3111         if (optimize_for_xen) {
3112                 x86_prefix (code, X86_FS_PREFIX);
3113                 amd64_mov_reg_mem (code, dreg, 0, 8);
3114                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3115         } else {
3116                 x86_prefix (code, X86_FS_PREFIX);
3117                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3118         }
3119 #endif
3120         return code;
3121 }
3122
3123 #define REAL_PRINT_REG(text,reg) \
3124 mono_assert (reg >= 0); \
3125 amd64_push_reg (code, AMD64_RAX); \
3126 amd64_push_reg (code, AMD64_RDX); \
3127 amd64_push_reg (code, AMD64_RCX); \
3128 amd64_push_reg (code, reg); \
3129 amd64_push_imm (code, reg); \
3130 amd64_push_imm (code, text " %d %p\n"); \
3131 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3132 amd64_call_reg (code, AMD64_RAX); \
3133 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3134 amd64_pop_reg (code, AMD64_RCX); \
3135 amd64_pop_reg (code, AMD64_RDX); \
3136 amd64_pop_reg (code, AMD64_RAX);
3137
3138 /* benchmark and set based on cpu */
3139 #define LOOP_ALIGNMENT 8
3140 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3141
3142 #ifndef DISABLE_JIT
3143
3144 void
3145 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3146 {
3147         MonoInst *ins;
3148         MonoCallInst *call;
3149         guint offset;
3150         guint8 *code = cfg->native_code + cfg->code_len;
3151         MonoInst *last_ins = NULL;
3152         guint last_offset = 0;
3153         int max_len;
3154
3155         /* Fix max_offset estimate for each successor bb */
3156         if (cfg->opt & MONO_OPT_BRANCH) {
3157                 int current_offset = cfg->code_len;
3158                 MonoBasicBlock *current_bb;
3159                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3160                         current_bb->max_offset = current_offset;
3161                         current_offset += current_bb->max_length;
3162                 }
3163         }
3164
3165         if (cfg->opt & MONO_OPT_LOOP) {
3166                 int pad, align = LOOP_ALIGNMENT;
3167                 /* set alignment depending on cpu */
3168                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3169                         pad = align - pad;
3170                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3171                         amd64_padding (code, pad);
3172                         cfg->code_len += pad;
3173                         bb->native_offset = cfg->code_len;
3174                 }
3175         }
3176
3177         if (cfg->verbose_level > 2)
3178                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3179
3180         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3181                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3182                 g_assert (!cfg->compile_aot);
3183
3184                 cov->data [bb->dfn].cil_code = bb->cil_code;
3185                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3186                 /* this is not thread save, but good enough */
3187                 amd64_inc_membase (code, AMD64_R11, 0);
3188         }
3189
3190         offset = code - cfg->native_code;
3191
3192         mono_debug_open_block (cfg, bb, offset);
3193
3194     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3195                 x86_breakpoint (code);
3196
3197         MONO_BB_FOR_EACH_INS (bb, ins) {
3198                 offset = code - cfg->native_code;
3199
3200                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3201
3202                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3203                         cfg->code_size *= 2;
3204                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3205                         code = cfg->native_code + offset;
3206                         mono_jit_stats.code_reallocs++;
3207                 }
3208
3209                 if (cfg->debug_info)
3210                         mono_debug_record_line_number (cfg, ins, offset);
3211
3212                 switch (ins->opcode) {
3213                 case OP_BIGMUL:
3214                         amd64_mul_reg (code, ins->sreg2, TRUE);
3215                         break;
3216                 case OP_BIGMUL_UN:
3217                         amd64_mul_reg (code, ins->sreg2, FALSE);
3218                         break;
3219                 case OP_X86_SETEQ_MEMBASE:
3220                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3221                         break;
3222                 case OP_STOREI1_MEMBASE_IMM:
3223                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3224                         break;
3225                 case OP_STOREI2_MEMBASE_IMM:
3226                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3227                         break;
3228                 case OP_STOREI4_MEMBASE_IMM:
3229                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3230                         break;
3231                 case OP_STOREI1_MEMBASE_REG:
3232                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3233                         break;
3234                 case OP_STOREI2_MEMBASE_REG:
3235                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3236                         break;
3237                 case OP_STORE_MEMBASE_REG:
3238                 case OP_STOREI8_MEMBASE_REG:
3239                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3240                         break;
3241                 case OP_STOREI4_MEMBASE_REG:
3242                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3243                         break;
3244                 case OP_STORE_MEMBASE_IMM:
3245                 case OP_STOREI8_MEMBASE_IMM:
3246                         g_assert (amd64_is_imm32 (ins->inst_imm));
3247                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3248                         break;
3249                 case OP_LOAD_MEM:
3250                 case OP_LOADI8_MEM:
3251                         // FIXME: Decompose this earlier
3252                         if (amd64_is_imm32 (ins->inst_imm))
3253                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3254                         else {
3255                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3256                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3257                         }
3258                         break;
3259                 case OP_LOADI4_MEM:
3260                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3261                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3262                         break;
3263                 case OP_LOADU4_MEM:
3264                         // FIXME: Decompose this earlier
3265                         if (amd64_is_imm32 (ins->inst_imm))
3266                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3267                         else {
3268                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3269                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3270                         }
3271                         break;
3272                 case OP_LOADU1_MEM:
3273                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3274                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3275                         break;
3276                 case OP_LOADU2_MEM:
3277                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3278                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3279                         break;
3280                 case OP_LOAD_MEMBASE:
3281                 case OP_LOADI8_MEMBASE:
3282                         g_assert (amd64_is_imm32 (ins->inst_offset));
3283                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3284                         break;
3285                 case OP_LOADI4_MEMBASE:
3286                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3287                         break;
3288                 case OP_LOADU4_MEMBASE:
3289                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3290                         break;
3291                 case OP_LOADU1_MEMBASE:
3292                         /* The cpu zero extends the result into 64 bits */
3293                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3294                         break;
3295                 case OP_LOADI1_MEMBASE:
3296                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3297                         break;
3298                 case OP_LOADU2_MEMBASE:
3299                         /* The cpu zero extends the result into 64 bits */
3300                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3301                         break;
3302                 case OP_LOADI2_MEMBASE:
3303                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3304                         break;
3305                 case OP_AMD64_LOADI8_MEMINDEX:
3306                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3307                         break;
3308                 case OP_LCONV_TO_I1:
3309                 case OP_ICONV_TO_I1:
3310                 case OP_SEXT_I1:
3311                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3312                         break;
3313                 case OP_LCONV_TO_I2:
3314                 case OP_ICONV_TO_I2:
3315                 case OP_SEXT_I2:
3316                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3317                         break;
3318                 case OP_LCONV_TO_U1:
3319                 case OP_ICONV_TO_U1:
3320                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3321                         break;
3322                 case OP_LCONV_TO_U2:
3323                 case OP_ICONV_TO_U2:
3324                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3325                         break;
3326                 case OP_ZEXT_I4:
3327                         /* Clean out the upper word */
3328                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3329                         break;
3330                 case OP_SEXT_I4:
3331                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3332                         break;
3333                 case OP_COMPARE:
3334                 case OP_LCOMPARE:
3335                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3336                         break;
3337                 case OP_COMPARE_IMM:
3338                 case OP_LCOMPARE_IMM:
3339                         g_assert (amd64_is_imm32 (ins->inst_imm));
3340                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3341                         break;
3342                 case OP_X86_COMPARE_REG_MEMBASE:
3343                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3344                         break;
3345                 case OP_X86_TEST_NULL:
3346                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3347                         break;
3348                 case OP_AMD64_TEST_NULL:
3349                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3350                         break;
3351
3352                 case OP_X86_ADD_REG_MEMBASE:
3353                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3354                         break;
3355                 case OP_X86_SUB_REG_MEMBASE:
3356                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3357                         break;
3358                 case OP_X86_AND_REG_MEMBASE:
3359                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3360                         break;
3361                 case OP_X86_OR_REG_MEMBASE:
3362                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3363                         break;
3364                 case OP_X86_XOR_REG_MEMBASE:
3365                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3366                         break;
3367
3368                 case OP_X86_ADD_MEMBASE_IMM:
3369                         /* FIXME: Make a 64 version too */
3370                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3371                         break;
3372                 case OP_X86_SUB_MEMBASE_IMM:
3373                         g_assert (amd64_is_imm32 (ins->inst_imm));
3374                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3375                         break;
3376                 case OP_X86_AND_MEMBASE_IMM:
3377                         g_assert (amd64_is_imm32 (ins->inst_imm));
3378                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3379                         break;
3380                 case OP_X86_OR_MEMBASE_IMM:
3381                         g_assert (amd64_is_imm32 (ins->inst_imm));
3382                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3383                         break;
3384                 case OP_X86_XOR_MEMBASE_IMM:
3385                         g_assert (amd64_is_imm32 (ins->inst_imm));
3386                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3387                         break;
3388                 case OP_X86_ADD_MEMBASE_REG:
3389                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3390                         break;
3391                 case OP_X86_SUB_MEMBASE_REG:
3392                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3393                         break;
3394                 case OP_X86_AND_MEMBASE_REG:
3395                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3396                         break;
3397                 case OP_X86_OR_MEMBASE_REG:
3398                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3399                         break;
3400                 case OP_X86_XOR_MEMBASE_REG:
3401                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3402                         break;
3403                 case OP_X86_INC_MEMBASE:
3404                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3405                         break;
3406                 case OP_X86_INC_REG:
3407                         amd64_inc_reg_size (code, ins->dreg, 4);
3408                         break;
3409                 case OP_X86_DEC_MEMBASE:
3410                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3411                         break;
3412                 case OP_X86_DEC_REG:
3413                         amd64_dec_reg_size (code, ins->dreg, 4);
3414                         break;
3415                 case OP_X86_MUL_REG_MEMBASE:
3416                 case OP_X86_MUL_MEMBASE_REG:
3417                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3418                         break;
3419                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3420                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3421                         break;
3422                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3423                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3424                         break;
3425                 case OP_AMD64_COMPARE_MEMBASE_REG:
3426                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3427                         break;
3428                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3429                         g_assert (amd64_is_imm32 (ins->inst_imm));
3430                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3431                         break;
3432                 case OP_X86_COMPARE_MEMBASE8_IMM:
3433                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3434                         break;
3435                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3436                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3437                         break;
3438                 case OP_AMD64_COMPARE_REG_MEMBASE:
3439                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3440                         break;
3441
3442                 case OP_AMD64_ADD_REG_MEMBASE:
3443                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3444                         break;
3445                 case OP_AMD64_SUB_REG_MEMBASE:
3446                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3447                         break;
3448                 case OP_AMD64_AND_REG_MEMBASE:
3449                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3450                         break;
3451                 case OP_AMD64_OR_REG_MEMBASE:
3452                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3453                         break;
3454                 case OP_AMD64_XOR_REG_MEMBASE:
3455                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3456                         break;
3457
3458                 case OP_AMD64_ADD_MEMBASE_REG:
3459                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3460                         break;
3461                 case OP_AMD64_SUB_MEMBASE_REG:
3462                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3463                         break;
3464                 case OP_AMD64_AND_MEMBASE_REG:
3465                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3466                         break;
3467                 case OP_AMD64_OR_MEMBASE_REG:
3468                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3469                         break;
3470                 case OP_AMD64_XOR_MEMBASE_REG:
3471                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3472                         break;
3473
3474                 case OP_AMD64_ADD_MEMBASE_IMM:
3475                         g_assert (amd64_is_imm32 (ins->inst_imm));
3476                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3477                         break;
3478                 case OP_AMD64_SUB_MEMBASE_IMM:
3479                         g_assert (amd64_is_imm32 (ins->inst_imm));
3480                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3481                         break;
3482                 case OP_AMD64_AND_MEMBASE_IMM:
3483                         g_assert (amd64_is_imm32 (ins->inst_imm));
3484                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3485                         break;
3486                 case OP_AMD64_OR_MEMBASE_IMM:
3487                         g_assert (amd64_is_imm32 (ins->inst_imm));
3488                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3489                         break;
3490                 case OP_AMD64_XOR_MEMBASE_IMM:
3491                         g_assert (amd64_is_imm32 (ins->inst_imm));
3492                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3493                         break;
3494
3495                 case OP_BREAK:
3496                         amd64_breakpoint (code);
3497                         break;
3498                 case OP_RELAXED_NOP:
3499                         x86_prefix (code, X86_REP_PREFIX);
3500                         x86_nop (code);
3501                         break;
3502                 case OP_HARD_NOP:
3503                         x86_nop (code);
3504                         break;
3505                 case OP_NOP:
3506                 case OP_DUMMY_USE:
3507                 case OP_DUMMY_STORE:
3508                 case OP_NOT_REACHED:
3509                 case OP_NOT_NULL:
3510                         break;
3511                 case OP_SEQ_POINT: {
3512                         int i, il_offset;
3513
3514                         if (cfg->compile_aot)
3515                                 NOT_IMPLEMENTED;
3516
3517                         /*
3518                          * Read from the single stepping trigger page. This will cause a
3519                          * SIGSEGV when single stepping is enabled.
3520                          * We do this _before_ the breakpoint, so single stepping after
3521                          * a breakpoint is hit will step to the next IL offset.
3522                          */
3523                         g_assert (((guint64)ss_trigger_page >> 32) == 0);
3524
3525                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
3526                                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3527
3528                         il_offset = ins->inst_imm;
3529
3530                         if (!cfg->seq_points)
3531                                 cfg->seq_points = g_ptr_array_new ();
3532                         g_ptr_array_add (cfg->seq_points, GUINT_TO_POINTER (il_offset));
3533                         g_ptr_array_add (cfg->seq_points, GUINT_TO_POINTER (code - cfg->native_code));
3534                         /*
3535                          * A placeholder for a possible breakpoint inserted by
3536                          * mono_arch_set_breakpoint ().
3537                          */
3538                         for (i = 0; i < BREAKPOINT_SIZE; ++i)
3539                                 x86_nop (code);
3540                         break;
3541                 }
3542                 case OP_ADDCC:
3543                 case OP_LADD:
3544                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3545                         break;
3546                 case OP_ADC:
3547                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3548                         break;
3549                 case OP_ADD_IMM:
3550                 case OP_LADD_IMM:
3551                         g_assert (amd64_is_imm32 (ins->inst_imm));
3552                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3553                         break;
3554                 case OP_ADC_IMM:
3555                         g_assert (amd64_is_imm32 (ins->inst_imm));
3556                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3557                         break;
3558                 case OP_SUBCC:
3559                 case OP_LSUB:
3560                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3561                         break;
3562                 case OP_SBB:
3563                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3564                         break;
3565                 case OP_SUB_IMM:
3566                 case OP_LSUB_IMM:
3567                         g_assert (amd64_is_imm32 (ins->inst_imm));
3568                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3569                         break;
3570                 case OP_SBB_IMM:
3571                         g_assert (amd64_is_imm32 (ins->inst_imm));
3572                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3573                         break;
3574                 case OP_LAND:
3575                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3576                         break;
3577                 case OP_AND_IMM:
3578                 case OP_LAND_IMM:
3579                         g_assert (amd64_is_imm32 (ins->inst_imm));
3580                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3581                         break;
3582                 case OP_LMUL:
3583                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3584                         break;
3585                 case OP_MUL_IMM:
3586                 case OP_LMUL_IMM:
3587                 case OP_IMUL_IMM: {
3588                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3589
3590                         switch (ins->inst_imm) {
3591                         case 2:
3592                                 /* MOV r1, r2 */
3593                                 /* ADD r1, r1 */
3594                                 if (ins->dreg != ins->sreg1)
3595                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3596                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3597                                 break;
3598                         case 3:
3599                                 /* LEA r1, [r2 + r2*2] */
3600                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3601                                 break;
3602                         case 5:
3603                                 /* LEA r1, [r2 + r2*4] */
3604                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3605                                 break;
3606                         case 6:
3607                                 /* LEA r1, [r2 + r2*2] */
3608                                 /* ADD r1, r1          */
3609                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3610                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3611                                 break;
3612                         case 9:
3613                                 /* LEA r1, [r2 + r2*8] */
3614                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3615                                 break;
3616                         case 10:
3617                                 /* LEA r1, [r2 + r2*4] */
3618                                 /* ADD r1, r1          */
3619                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3620                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3621                                 break;
3622                         case 12:
3623                                 /* LEA r1, [r2 + r2*2] */
3624                                 /* SHL r1, 2           */
3625                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3626                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3627                                 break;
3628                         case 25:
3629                                 /* LEA r1, [r2 + r2*4] */
3630                                 /* LEA r1, [r1 + r1*4] */
3631                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3632                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3633                                 break;
3634                         case 100:
3635                                 /* LEA r1, [r2 + r2*4] */
3636                                 /* SHL r1, 2           */
3637                                 /* LEA r1, [r1 + r1*4] */
3638                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3639                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3640                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3641                                 break;
3642                         default:
3643                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3644                                 break;
3645                         }
3646                         break;
3647                 }
3648                 case OP_LDIV:
3649                 case OP_LREM:
3650                         /* Regalloc magic makes the div/rem cases the same */
3651                         if (ins->sreg2 == AMD64_RDX) {
3652                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3653                                 amd64_cdq (code);
3654                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3655                         } else {
3656                                 amd64_cdq (code);
3657                                 amd64_div_reg (code, ins->sreg2, TRUE);
3658                         }
3659                         break;
3660                 case OP_LDIV_UN:
3661                 case OP_LREM_UN:
3662                         if (ins->sreg2 == AMD64_RDX) {
3663                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3664                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3665                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3666                         } else {
3667                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3668                                 amd64_div_reg (code, ins->sreg2, FALSE);
3669                         }
3670                         break;
3671                 case OP_IDIV:
3672                 case OP_IREM:
3673                         if (ins->sreg2 == AMD64_RDX) {
3674                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3675                                 amd64_cdq_size (code, 4);
3676                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3677                         } else {
3678                                 amd64_cdq_size (code, 4);
3679                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3680                         }
3681                         break;
3682                 case OP_IDIV_UN:
3683                 case OP_IREM_UN:
3684                         if (ins->sreg2 == AMD64_RDX) {
3685                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3686                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3687                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3688                         } else {
3689                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3690                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3691                         }
3692                         break;
3693                 case OP_IREM_IMM: {
3694                         int power = mono_is_power_of_two (ins->inst_imm);
3695
3696                         g_assert (ins->sreg1 == X86_EAX);
3697                         g_assert (ins->dreg == X86_EAX);
3698                         g_assert (power >= 0);
3699
3700                         if (power == 0) {
3701                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3702                                 break;
3703                         }
3704
3705                         /* Based on gcc code */
3706
3707                         /* Add compensation for negative dividents */
3708                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3709                         if (power > 1)
3710                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3711                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3712                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3713                         /* Compute remainder */
3714                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3715                         /* Remove compensation */
3716                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3717                         break;
3718                 }
3719                 case OP_LMUL_OVF:
3720                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3721                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3722                         break;
3723                 case OP_LOR:
3724                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3725                         break;
3726                 case OP_OR_IMM:
3727                 case OP_LOR_IMM:
3728                         g_assert (amd64_is_imm32 (ins->inst_imm));
3729                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3730                         break;
3731                 case OP_LXOR:
3732                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3733                         break;
3734                 case OP_XOR_IMM:
3735                 case OP_LXOR_IMM:
3736                         g_assert (amd64_is_imm32 (ins->inst_imm));
3737                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3738                         break;
3739                 case OP_LSHL:
3740                         g_assert (ins->sreg2 == AMD64_RCX);
3741                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3742                         break;
3743                 case OP_LSHR:
3744                         g_assert (ins->sreg2 == AMD64_RCX);
3745                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3746                         break;
3747                 case OP_SHR_IMM:
3748                         g_assert (amd64_is_imm32 (ins->inst_imm));
3749                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3750                         break;
3751                 case OP_LSHR_IMM:
3752                         g_assert (amd64_is_imm32 (ins->inst_imm));
3753                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3754                         break;
3755                 case OP_SHR_UN_IMM:
3756                         g_assert (amd64_is_imm32 (ins->inst_imm));
3757                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3758                         break;
3759                 case OP_LSHR_UN_IMM:
3760                         g_assert (amd64_is_imm32 (ins->inst_imm));
3761                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3762                         break;
3763                 case OP_LSHR_UN:
3764                         g_assert (ins->sreg2 == AMD64_RCX);
3765                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3766                         break;
3767                 case OP_SHL_IMM:
3768                         g_assert (amd64_is_imm32 (ins->inst_imm));
3769                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3770                         break;
3771                 case OP_LSHL_IMM:
3772                         g_assert (amd64_is_imm32 (ins->inst_imm));
3773                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3774                         break;
3775
3776                 case OP_IADDCC:
3777                 case OP_IADD:
3778                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3779                         break;
3780                 case OP_IADC:
3781                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3782                         break;
3783                 case OP_IADD_IMM:
3784                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3785                         break;
3786                 case OP_IADC_IMM:
3787                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3788                         break;
3789                 case OP_ISUBCC:
3790                 case OP_ISUB:
3791                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3792                         break;
3793                 case OP_ISBB:
3794                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3795                         break;
3796                 case OP_ISUB_IMM:
3797                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3798                         break;
3799                 case OP_ISBB_IMM:
3800                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3801                         break;
3802                 case OP_IAND:
3803                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3804                         break;
3805                 case OP_IAND_IMM:
3806                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3807                         break;
3808                 case OP_IOR:
3809                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3810                         break;
3811                 case OP_IOR_IMM:
3812                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3813                         break;
3814                 case OP_IXOR:
3815                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3816                         break;
3817                 case OP_IXOR_IMM:
3818                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3819                         break;
3820                 case OP_INEG:
3821                         amd64_neg_reg_size (code, ins->sreg1, 4);
3822                         break;
3823                 case OP_INOT:
3824                         amd64_not_reg_size (code, ins->sreg1, 4);
3825                         break;
3826                 case OP_ISHL:
3827                         g_assert (ins->sreg2 == AMD64_RCX);
3828                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3829                         break;
3830                 case OP_ISHR:
3831                         g_assert (ins->sreg2 == AMD64_RCX);
3832                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3833                         break;
3834                 case OP_ISHR_IMM:
3835                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3836                         break;
3837                 case OP_ISHR_UN_IMM:
3838                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3839                         break;
3840                 case OP_ISHR_UN:
3841                         g_assert (ins->sreg2 == AMD64_RCX);
3842                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3843                         break;
3844                 case OP_ISHL_IMM:
3845                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3846                         break;
3847                 case OP_IMUL:
3848                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3849                         break;
3850                 case OP_IMUL_OVF:
3851                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3852                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3853                         break;
3854                 case OP_IMUL_OVF_UN:
3855                 case OP_LMUL_OVF_UN: {
3856                         /* the mul operation and the exception check should most likely be split */
3857                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3858                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3859                         /*g_assert (ins->sreg2 == X86_EAX);
3860                         g_assert (ins->dreg == X86_EAX);*/
3861                         if (ins->sreg2 == X86_EAX) {
3862                                 non_eax_reg = ins->sreg1;
3863                         } else if (ins->sreg1 == X86_EAX) {
3864                                 non_eax_reg = ins->sreg2;
3865                         } else {
3866                                 /* no need to save since we're going to store to it anyway */
3867                                 if (ins->dreg != X86_EAX) {
3868                                         saved_eax = TRUE;
3869                                         amd64_push_reg (code, X86_EAX);
3870                                 }
3871                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3872                                 non_eax_reg = ins->sreg2;
3873                         }
3874                         if (ins->dreg == X86_EDX) {
3875                                 if (!saved_eax) {
3876                                         saved_eax = TRUE;
3877                                         amd64_push_reg (code, X86_EAX);
3878                                 }
3879                         } else {
3880                                 saved_edx = TRUE;
3881                                 amd64_push_reg (code, X86_EDX);
3882                         }
3883                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3884                         /* save before the check since pop and mov don't change the flags */
3885                         if (ins->dreg != X86_EAX)
3886                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3887                         if (saved_edx)
3888                                 amd64_pop_reg (code, X86_EDX);
3889                         if (saved_eax)
3890                                 amd64_pop_reg (code, X86_EAX);
3891                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3892                         break;
3893                 }
3894                 case OP_ICOMPARE:
3895                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3896                         break;
3897                 case OP_ICOMPARE_IMM:
3898                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3899                         break;
3900                 case OP_IBEQ:
3901                 case OP_IBLT:
3902                 case OP_IBGT:
3903                 case OP_IBGE:
3904                 case OP_IBLE:
3905                 case OP_LBEQ:
3906                 case OP_LBLT:
3907                 case OP_LBGT:
3908                 case OP_LBGE:
3909                 case OP_LBLE:
3910                 case OP_IBNE_UN:
3911                 case OP_IBLT_UN:
3912                 case OP_IBGT_UN:
3913                 case OP_IBGE_UN:
3914                 case OP_IBLE_UN:
3915                 case OP_LBNE_UN:
3916                 case OP_LBLT_UN:
3917                 case OP_LBGT_UN:
3918                 case OP_LBGE_UN:
3919                 case OP_LBLE_UN:
3920                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3921                         break;
3922
3923                 case OP_CMOV_IEQ:
3924                 case OP_CMOV_IGE:
3925                 case OP_CMOV_IGT:
3926                 case OP_CMOV_ILE:
3927                 case OP_CMOV_ILT:
3928                 case OP_CMOV_INE_UN:
3929                 case OP_CMOV_IGE_UN:
3930                 case OP_CMOV_IGT_UN:
3931                 case OP_CMOV_ILE_UN:
3932                 case OP_CMOV_ILT_UN:
3933                 case OP_CMOV_LEQ:
3934                 case OP_CMOV_LGE:
3935                 case OP_CMOV_LGT:
3936                 case OP_CMOV_LLE:
3937                 case OP_CMOV_LLT:
3938                 case OP_CMOV_LNE_UN:
3939                 case OP_CMOV_LGE_UN:
3940                 case OP_CMOV_LGT_UN:
3941                 case OP_CMOV_LLE_UN:
3942                 case OP_CMOV_LLT_UN:
3943                         g_assert (ins->dreg == ins->sreg1);
3944                         /* This needs to operate on 64 bit values */
3945                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3946                         break;
3947
3948                 case OP_LNOT:
3949                         amd64_not_reg (code, ins->sreg1);
3950                         break;
3951                 case OP_LNEG:
3952                         amd64_neg_reg (code, ins->sreg1);
3953                         break;
3954
3955                 case OP_ICONST:
3956                 case OP_I8CONST:
3957                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3958                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3959                         else
3960                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3961                         break;
3962                 case OP_AOTCONST:
3963                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3964                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3965                         break;
3966                 case OP_JUMP_TABLE:
3967                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3968                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3969                         break;
3970                 case OP_MOVE:
3971                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3972                         break;
3973                 case OP_AMD64_SET_XMMREG_R4: {
3974                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3975                         break;
3976                 }
3977                 case OP_AMD64_SET_XMMREG_R8: {
3978                         if (ins->dreg != ins->sreg1)
3979                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3980                         break;
3981                 }
3982                 case OP_TAILCALL: {
3983                         /*
3984                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3985                          * Keep in sync with the code in emit_epilog.
3986                          */
3987                         int pos = 0, i;
3988
3989                         /* FIXME: no tracing support... */
3990                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3991                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
3992
3993                         g_assert (!cfg->method->save_lmf);
3994
3995                         if (cfg->arch.omit_fp) {
3996                                 guint32 save_offset = 0;
3997                                 /* Pop callee-saved registers */
3998                                 for (i = 0; i < AMD64_NREG; ++i)
3999                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4000                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4001                                                 save_offset += 8;
4002                                         }
4003                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4004                         }
4005                         else {
4006                                 for (i = 0; i < AMD64_NREG; ++i)
4007                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4008                                                 pos -= sizeof (gpointer);
4009
4010                                 if (pos)
4011                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4012
4013                                 /* Pop registers in reverse order */
4014                                 for (i = AMD64_NREG - 1; i > 0; --i)
4015                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4016                                                 amd64_pop_reg (code, i);
4017                                         }
4018
4019                                 amd64_leave (code);
4020                         }
4021
4022                         offset = code - cfg->native_code;
4023                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4024                         if (cfg->compile_aot)
4025                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4026                         else
4027                                 amd64_set_reg_template (code, AMD64_R11);
4028                         amd64_jump_reg (code, AMD64_R11);
4029                         break;
4030                 }
4031                 case OP_CHECK_THIS:
4032                         /* ensure ins->sreg1 is not NULL */
4033                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4034                         break;
4035                 case OP_ARGLIST: {
4036                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4037                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4038                         break;
4039                 }
4040                 case OP_CALL:
4041                 case OP_FCALL:
4042                 case OP_LCALL:
4043                 case OP_VCALL:
4044                 case OP_VCALL2:
4045                 case OP_VOIDCALL:
4046                         call = (MonoCallInst*)ins;
4047                         /*
4048                          * The AMD64 ABI forces callers to know about varargs.
4049                          */
4050                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4051                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4052                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4053                                 /*
4054                                  * Since the unmanaged calling convention doesn't contain a
4055                                  * 'vararg' entry, we have to treat every pinvoke call as a
4056                                  * potential vararg call.
4057                                  */
4058                                 guint32 nregs, i;
4059                                 nregs = 0;
4060                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4061                                         if (call->used_fregs & (1 << i))
4062                                                 nregs ++;
4063                                 if (!nregs)
4064                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4065                                 else
4066                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4067                         }
4068
4069                         if (ins->flags & MONO_INST_HAS_METHOD)
4070                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4071                         else
4072                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4073                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4074                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4075                         code = emit_move_return_value (cfg, ins, code);
4076                         break;
4077                 case OP_FCALL_REG:
4078                 case OP_LCALL_REG:
4079                 case OP_VCALL_REG:
4080                 case OP_VCALL2_REG:
4081                 case OP_VOIDCALL_REG:
4082                 case OP_CALL_REG:
4083                         call = (MonoCallInst*)ins;
4084
4085                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4086                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4087                                 ins->sreg1 = AMD64_R11;
4088                         }
4089
4090                         /*
4091                          * The AMD64 ABI forces callers to know about varargs.
4092                          */
4093                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4094                                 if (ins->sreg1 == AMD64_RAX) {
4095                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4096                                         ins->sreg1 = AMD64_R11;
4097                                 }
4098                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4099                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4100                                 /*
4101                                  * Since the unmanaged calling convention doesn't contain a
4102                                  * 'vararg' entry, we have to treat every pinvoke call as a
4103                                  * potential vararg call.
4104                                  */
4105                                 guint32 nregs, i;
4106                                 nregs = 0;
4107                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4108                                         if (call->used_fregs & (1 << i))
4109                                                 nregs ++;
4110                                 if (ins->sreg1 == AMD64_RAX) {
4111                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4112                                         ins->sreg1 = AMD64_R11;
4113                                 }
4114                                 if (!nregs)
4115                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4116                                 else
4117                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4118                         }
4119
4120                         amd64_call_reg (code, ins->sreg1);
4121                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4122                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4123                         code = emit_move_return_value (cfg, ins, code);
4124                         break;
4125                 case OP_FCALL_MEMBASE:
4126                 case OP_LCALL_MEMBASE:
4127                 case OP_VCALL_MEMBASE:
4128                 case OP_VCALL2_MEMBASE:
4129                 case OP_VOIDCALL_MEMBASE:
4130                 case OP_CALL_MEMBASE:
4131                         call = (MonoCallInst*)ins;
4132
4133                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4134                                 /*
4135                                  * Can't use R11 because it is clobbered by the trampoline
4136                                  * code, and the reg value is needed by get_vcall_slot_addr.
4137                                  */
4138                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4139                                 ins->sreg1 = AMD64_RAX;
4140                         }
4141
4142                         /*
4143                          * Emit a few nops to simplify get_vcall_slot ().
4144                          */
4145                         amd64_nop (code);
4146                         amd64_nop (code);
4147                         amd64_nop (code);
4148
4149                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4150                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4151                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4152                         code = emit_move_return_value (cfg, ins, code);
4153                         break;
4154                 case OP_DYN_CALL: {
4155                         int i;
4156                         MonoInst *var = cfg->dyn_call_var;
4157
4158                         g_assert (var->opcode == OP_REGOFFSET);
4159
4160                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4161                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4162                         /* r10 = ftn */
4163                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4164
4165                         /* Save args buffer */
4166                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4167
4168                         /* Set argument registers */
4169                         for (i = 0; i < PARAM_REGS; ++i)
4170                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4171
4172                         /* Make the call */
4173                         amd64_call_reg (code, AMD64_R10);
4174
4175                         /* Save result */
4176                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4177                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4178                         break;
4179                 }
4180                 case OP_AMD64_SAVE_SP_TO_LMF:
4181                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4182                         break;
4183                 case OP_X86_PUSH:
4184                         g_assert (!cfg->arch.no_pushes);
4185                         amd64_push_reg (code, ins->sreg1);
4186                         break;
4187                 case OP_X86_PUSH_IMM:
4188                         g_assert (!cfg->arch.no_pushes);
4189                         g_assert (amd64_is_imm32 (ins->inst_imm));
4190                         amd64_push_imm (code, ins->inst_imm);
4191                         break;
4192                 case OP_X86_PUSH_MEMBASE:
4193                         g_assert (!cfg->arch.no_pushes);
4194                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4195                         break;
4196                 case OP_X86_PUSH_OBJ: {
4197                         int size = ALIGN_TO (ins->inst_imm, 8);
4198
4199                         g_assert (!cfg->arch.no_pushes);
4200
4201                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4202                         amd64_push_reg (code, AMD64_RDI);
4203                         amd64_push_reg (code, AMD64_RSI);
4204                         amd64_push_reg (code, AMD64_RCX);
4205                         if (ins->inst_offset)
4206                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4207                         else
4208                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4209                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4210                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4211                         amd64_cld (code);
4212                         amd64_prefix (code, X86_REP_PREFIX);
4213                         amd64_movsd (code);
4214                         amd64_pop_reg (code, AMD64_RCX);
4215                         amd64_pop_reg (code, AMD64_RSI);
4216                         amd64_pop_reg (code, AMD64_RDI);
4217                         break;
4218                 }
4219                 case OP_X86_LEA:
4220                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4221                         break;
4222                 case OP_X86_LEA_MEMBASE:
4223                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4224                         break;
4225                 case OP_X86_XCHG:
4226                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4227                         break;
4228                 case OP_LOCALLOC:
4229                         /* keep alignment */
4230                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4231                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4232                         code = mono_emit_stack_alloc (cfg, code, ins);
4233                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4234                         if (cfg->param_area && cfg->arch.no_pushes)
4235                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4236                         break;
4237                 case OP_LOCALLOC_IMM: {
4238                         guint32 size = ins->inst_imm;
4239                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4240
4241                         if (ins->flags & MONO_INST_INIT) {
4242                                 if (size < 64) {
4243                                         int i;
4244
4245                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4246                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4247
4248                                         for (i = 0; i < size; i += 8)
4249                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4250                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4251                                 } else {
4252                                         amd64_mov_reg_imm (code, ins->dreg, size);
4253                                         ins->sreg1 = ins->dreg;
4254
4255                                         code = mono_emit_stack_alloc (cfg, code, ins);
4256                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4257                                 }
4258                         } else {
4259                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4260                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4261                         }
4262                         if (cfg->param_area && cfg->arch.no_pushes)
4263                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4264                         break;
4265                 }
4266                 case OP_THROW: {
4267                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4268                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4269                                              (gpointer)"mono_arch_throw_exception", FALSE);
4270                         break;
4271                 }
4272                 case OP_RETHROW: {
4273                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4274                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4275                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4276                         break;
4277                 }
4278                 case OP_CALL_HANDLER:
4279                         /* Align stack */
4280                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4281                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4282                         amd64_call_imm (code, 0);
4283                         /* Restore stack alignment */
4284                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4285                         break;
4286                 case OP_START_HANDLER: {
4287                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4288                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4289
4290                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4291                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4292                                 cfg->param_area && cfg->arch.no_pushes) {
4293                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4294                         }
4295                         break;
4296                 }
4297                 case OP_ENDFINALLY: {
4298                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4299                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4300                         amd64_ret (code);
4301                         break;
4302                 }
4303                 case OP_ENDFILTER: {
4304                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4305                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4306                         /* The local allocator will put the result into RAX */
4307                         amd64_ret (code);
4308                         break;
4309                 }
4310
4311                 case OP_LABEL:
4312                         ins->inst_c0 = code - cfg->native_code;
4313                         break;
4314                 case OP_BR:
4315                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4316                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4317                         //break;
4318                                 if (ins->inst_target_bb->native_offset) {
4319                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4320                                 } else {
4321                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4322                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4323                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4324                                                 x86_jump8 (code, 0);
4325                                         else
4326                                                 x86_jump32 (code, 0);
4327                         }
4328                         break;
4329                 case OP_BR_REG:
4330                         amd64_jump_reg (code, ins->sreg1);
4331                         break;
4332                 case OP_CEQ:
4333                 case OP_LCEQ:
4334                 case OP_ICEQ:
4335                 case OP_CLT:
4336                 case OP_LCLT:
4337                 case OP_ICLT:
4338                 case OP_CGT:
4339                 case OP_ICGT:
4340                 case OP_LCGT:
4341                 case OP_CLT_UN:
4342                 case OP_LCLT_UN:
4343                 case OP_ICLT_UN:
4344                 case OP_CGT_UN:
4345                 case OP_LCGT_UN:
4346                 case OP_ICGT_UN:
4347                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4348                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4349                         break;
4350                 case OP_COND_EXC_EQ:
4351                 case OP_COND_EXC_NE_UN:
4352                 case OP_COND_EXC_LT:
4353                 case OP_COND_EXC_LT_UN:
4354                 case OP_COND_EXC_GT:
4355                 case OP_COND_EXC_GT_UN:
4356                 case OP_COND_EXC_GE:
4357                 case OP_COND_EXC_GE_UN:
4358                 case OP_COND_EXC_LE:
4359                 case OP_COND_EXC_LE_UN:
4360                 case OP_COND_EXC_IEQ:
4361                 case OP_COND_EXC_INE_UN:
4362                 case OP_COND_EXC_ILT:
4363                 case OP_COND_EXC_ILT_UN:
4364                 case OP_COND_EXC_IGT:
4365                 case OP_COND_EXC_IGT_UN:
4366                 case OP_COND_EXC_IGE:
4367                 case OP_COND_EXC_IGE_UN:
4368                 case OP_COND_EXC_ILE:
4369                 case OP_COND_EXC_ILE_UN:
4370                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4371                         break;
4372                 case OP_COND_EXC_OV:
4373                 case OP_COND_EXC_NO:
4374                 case OP_COND_EXC_C:
4375                 case OP_COND_EXC_NC:
4376                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4377                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4378                         break;
4379                 case OP_COND_EXC_IOV:
4380                 case OP_COND_EXC_INO:
4381                 case OP_COND_EXC_IC:
4382                 case OP_COND_EXC_INC:
4383                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4384                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4385                         break;
4386
4387                 /* floating point opcodes */
4388                 case OP_R8CONST: {
4389                         double d = *(double *)ins->inst_p0;
4390
4391                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4392                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4393                         }
4394                         else {
4395                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4396                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4397                         }
4398                         break;
4399                 }
4400                 case OP_R4CONST: {
4401                         float f = *(float *)ins->inst_p0;
4402
4403                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4404                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4405                         }
4406                         else {
4407                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4408                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4409                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4410                         }
4411                         break;
4412                 }
4413                 case OP_STORER8_MEMBASE_REG:
4414                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4415                         break;
4416                 case OP_LOADR8_MEMBASE:
4417                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4418                         break;
4419                 case OP_STORER4_MEMBASE_REG:
4420                         /* This requires a double->single conversion */
4421                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4422                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4423                         break;
4424                 case OP_LOADR4_MEMBASE:
4425                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4426                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4427                         break;
4428                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4429                 case OP_ICONV_TO_R8:
4430                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4431                         break;
4432                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4433                 case OP_LCONV_TO_R8:
4434                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4435                         break;
4436                 case OP_FCONV_TO_R4:
4437                         /* FIXME: nothing to do ?? */
4438                         break;
4439                 case OP_FCONV_TO_I1:
4440                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4441                         break;
4442                 case OP_FCONV_TO_U1:
4443                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4444                         break;
4445                 case OP_FCONV_TO_I2:
4446                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4447                         break;
4448                 case OP_FCONV_TO_U2:
4449                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4450                         break;
4451                 case OP_FCONV_TO_U4:
4452                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4453                         break;
4454                 case OP_FCONV_TO_I4:
4455                 case OP_FCONV_TO_I:
4456                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4457                         break;
4458                 case OP_FCONV_TO_I8:
4459                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4460                         break;
4461                 case OP_LCONV_TO_R_UN: {
4462                         guint8 *br [2];
4463
4464                         /* Based on gcc code */
4465                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4466                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4467
4468                         /* Positive case */
4469                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4470                         br [1] = code; x86_jump8 (code, 0);
4471                         amd64_patch (br [0], code);
4472
4473                         /* Negative case */
4474                         /* Save to the red zone */
4475                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4476                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4477                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4478                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4479                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4480                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4481                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4482                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4483                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4484                         /* Restore */
4485                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4486                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4487                         amd64_patch (br [1], code);
4488                         break;
4489                 }
4490                 case OP_LCONV_TO_OVF_U4:
4491                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4492                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4493                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4494                         break;
4495                 case OP_LCONV_TO_OVF_I4_UN:
4496                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4497                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4498                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4499                         break;
4500                 case OP_FMOVE:
4501                         if (ins->dreg != ins->sreg1)
4502                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4503                         break;
4504                 case OP_FADD:
4505                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4506                         break;
4507                 case OP_FSUB:
4508                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4509                         break;
4510                 case OP_FMUL:
4511                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4512                         break;
4513                 case OP_FDIV:
4514                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4515                         break;
4516                 case OP_FNEG: {
4517                         static double r8_0 = -0.0;
4518
4519                         g_assert (ins->sreg1 == ins->dreg);
4520
4521                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4522                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4523                         break;
4524                 }
4525                 case OP_SIN:
4526                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4527                         break;
4528                 case OP_COS:
4529                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4530                         break;
4531                 case OP_ABS: {
4532                         static guint64 d = 0x7fffffffffffffffUL;
4533
4534                         g_assert (ins->sreg1 == ins->dreg);
4535
4536                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4537                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4538                         break;
4539                 }
4540                 case OP_SQRT:
4541                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4542                         break;
4543                 case OP_IMIN:
4544                         g_assert (cfg->opt & MONO_OPT_CMOV);
4545                         g_assert (ins->dreg == ins->sreg1);
4546                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4547                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4548                         break;
4549                 case OP_IMIN_UN:
4550                         g_assert (cfg->opt & MONO_OPT_CMOV);
4551                         g_assert (ins->dreg == ins->sreg1);
4552                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4553                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4554                         break;
4555                 case OP_IMAX:
4556                         g_assert (cfg->opt & MONO_OPT_CMOV);
4557                         g_assert (ins->dreg == ins->sreg1);
4558                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4559                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4560                         break;
4561                 case OP_IMAX_UN:
4562                         g_assert (cfg->opt & MONO_OPT_CMOV);
4563                         g_assert (ins->dreg == ins->sreg1);
4564                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4565                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4566                         break;
4567                 case OP_LMIN:
4568                         g_assert (cfg->opt & MONO_OPT_CMOV);
4569                         g_assert (ins->dreg == ins->sreg1);
4570                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4571                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4572                         break;
4573                 case OP_LMIN_UN:
4574                         g_assert (cfg->opt & MONO_OPT_CMOV);
4575                         g_assert (ins->dreg == ins->sreg1);
4576                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4577                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4578                         break;
4579                 case OP_LMAX:
4580                         g_assert (cfg->opt & MONO_OPT_CMOV);
4581                         g_assert (ins->dreg == ins->sreg1);
4582                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4583                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4584                         break;
4585                 case OP_LMAX_UN:
4586                         g_assert (cfg->opt & MONO_OPT_CMOV);
4587                         g_assert (ins->dreg == ins->sreg1);
4588                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4589                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4590                         break;
4591                 case OP_X86_FPOP:
4592                         break;
4593                 case OP_FCOMPARE:
4594                         /*
4595                          * The two arguments are swapped because the fbranch instructions
4596                          * depend on this for the non-sse case to work.
4597                          */
4598                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4599                         break;
4600                 case OP_FCEQ: {
4601                         /* zeroing the register at the start results in
4602                          * shorter and faster code (we can also remove the widening op)
4603                          */
4604                         guchar *unordered_check;
4605                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4606                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4607                         unordered_check = code;
4608                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4609                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4610                         amd64_patch (unordered_check, code);
4611                         break;
4612                 }
4613                 case OP_FCLT:
4614                 case OP_FCLT_UN:
4615                         /* zeroing the register at the start results in
4616                          * shorter and faster code (we can also remove the widening op)
4617                          */
4618                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4619                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4620                         if (ins->opcode == OP_FCLT_UN) {
4621                                 guchar *unordered_check = code;
4622                                 guchar *jump_to_end;
4623                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4624                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4625                                 jump_to_end = code;
4626                                 x86_jump8 (code, 0);
4627                                 amd64_patch (unordered_check, code);
4628                                 amd64_inc_reg (code, ins->dreg);
4629                                 amd64_patch (jump_to_end, code);
4630                         } else {
4631                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4632                         }
4633                         break;
4634                 case OP_FCGT:
4635                 case OP_FCGT_UN: {
4636                         /* zeroing the register at the start results in
4637                          * shorter and faster code (we can also remove the widening op)
4638                          */
4639                         guchar *unordered_check;
4640                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4641                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4642                         if (ins->opcode == OP_FCGT) {
4643                                 unordered_check = code;
4644                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4645                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4646                                 amd64_patch (unordered_check, code);
4647                         } else {
4648                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4649                         }
4650                         break;
4651                 }
4652                 case OP_FCLT_MEMBASE:
4653                 case OP_FCGT_MEMBASE:
4654                 case OP_FCLT_UN_MEMBASE:
4655                 case OP_FCGT_UN_MEMBASE:
4656                 case OP_FCEQ_MEMBASE: {
4657                         guchar *unordered_check, *jump_to_end;
4658                         int x86_cond;
4659
4660                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4661                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4662
4663                         switch (ins->opcode) {
4664                         case OP_FCEQ_MEMBASE:
4665                                 x86_cond = X86_CC_EQ;
4666                                 break;
4667                         case OP_FCLT_MEMBASE:
4668                         case OP_FCLT_UN_MEMBASE:
4669                                 x86_cond = X86_CC_LT;
4670                                 break;
4671                         case OP_FCGT_MEMBASE:
4672                         case OP_FCGT_UN_MEMBASE:
4673                                 x86_cond = X86_CC_GT;
4674                                 break;
4675                         default:
4676                                 g_assert_not_reached ();
4677                         }
4678
4679                         unordered_check = code;
4680                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4681                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4682
4683                         switch (ins->opcode) {
4684                         case OP_FCEQ_MEMBASE:
4685                         case OP_FCLT_MEMBASE:
4686                         case OP_FCGT_MEMBASE:
4687                                 amd64_patch (unordered_check, code);
4688                                 break;
4689                         case OP_FCLT_UN_MEMBASE:
4690                         case OP_FCGT_UN_MEMBASE:
4691                                 jump_to_end = code;
4692                                 x86_jump8 (code, 0);
4693                                 amd64_patch (unordered_check, code);
4694                                 amd64_inc_reg (code, ins->dreg);
4695                                 amd64_patch (jump_to_end, code);
4696                                 break;
4697                         default:
4698                                 break;
4699                         }
4700                         break;
4701                 }
4702                 case OP_FBEQ: {
4703                         guchar *jump = code;
4704                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4705                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4706                         amd64_patch (jump, code);
4707                         break;
4708                 }
4709                 case OP_FBNE_UN:
4710                         /* Branch if C013 != 100 */
4711                         /* branch if !ZF or (PF|CF) */
4712                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4713                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4714                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4715                         break;
4716                 case OP_FBLT:
4717                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4718                         break;
4719                 case OP_FBLT_UN:
4720                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4721                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4722                         break;
4723                 case OP_FBGT:
4724                 case OP_FBGT_UN:
4725                         if (ins->opcode == OP_FBGT) {
4726                                 guchar *br1;
4727
4728                                 /* skip branch if C1=1 */
4729                                 br1 = code;
4730                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4731                                 /* branch if (C0 | C3) = 1 */
4732                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4733                                 amd64_patch (br1, code);
4734                                 break;
4735                         } else {
4736                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4737                         }
4738                         break;
4739                 case OP_FBGE: {
4740                         /* Branch if C013 == 100 or 001 */
4741                         guchar *br1;
4742
4743                         /* skip branch if C1=1 */
4744                         br1 = code;
4745                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4746                         /* branch if (C0 | C3) = 1 */
4747                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4748                         amd64_patch (br1, code);
4749                         break;
4750                 }
4751                 case OP_FBGE_UN:
4752                         /* Branch if C013 == 000 */
4753                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4754                         break;
4755                 case OP_FBLE: {
4756                         /* Branch if C013=000 or 100 */
4757                         guchar *br1;
4758
4759                         /* skip branch if C1=1 */
4760                         br1 = code;
4761                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4762                         /* branch if C0=0 */
4763                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4764                         amd64_patch (br1, code);
4765                         break;
4766                 }
4767                 case OP_FBLE_UN:
4768                         /* Branch if C013 != 001 */
4769                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4770                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4771                         break;
4772                 case OP_CKFINITE:
4773                         /* Transfer value to the fp stack */
4774                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4775                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4776                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4777
4778                         amd64_push_reg (code, AMD64_RAX);
4779                         amd64_fxam (code);
4780                         amd64_fnstsw (code);
4781                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4782                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4783                         amd64_pop_reg (code, AMD64_RAX);
4784                         amd64_fstp (code, 0);
4785                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4786                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4787                         break;
4788                 case OP_TLS_GET: {
4789                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4790                         break;
4791                 }
4792                 case OP_MEMORY_BARRIER: {
4793                         /* Not needed on amd64 */
4794                         break;
4795                 }
4796                 case OP_ATOMIC_ADD_I4:
4797                 case OP_ATOMIC_ADD_I8: {
4798                         int dreg = ins->dreg;
4799                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4800
4801                         if (dreg == ins->inst_basereg)
4802                                 dreg = AMD64_R11;
4803
4804                         if (dreg != ins->sreg2)
4805                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4806
4807                         x86_prefix (code, X86_LOCK_PREFIX);
4808                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4809
4810                         if (dreg != ins->dreg)
4811                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4812
4813                         break;
4814                 }
4815                 case OP_ATOMIC_ADD_NEW_I4:
4816                 case OP_ATOMIC_ADD_NEW_I8: {
4817                         int dreg = ins->dreg;
4818                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4819
4820                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4821                                 dreg = AMD64_R11;
4822
4823                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4824                         amd64_prefix (code, X86_LOCK_PREFIX);
4825                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4826                         /* dreg contains the old value, add with sreg2 value */
4827                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4828
4829                         if (ins->dreg != dreg)
4830                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4831
4832                         break;
4833                 }
4834                 case OP_ATOMIC_EXCHANGE_I4:
4835                 case OP_ATOMIC_EXCHANGE_I8: {
4836                         guchar *br[2];
4837                         int sreg2 = ins->sreg2;
4838                         int breg = ins->inst_basereg;
4839                         guint32 size;
4840                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4841
4842                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4843                                 size = 8;
4844                         else
4845                                 size = 4;
4846
4847                         /*
4848                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4849                          * an explanation of how this works.
4850                          */
4851
4852                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4853                          * hack to overcome limits in x86 reg allocator
4854                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4855                          */
4856                         g_assert (ins->dreg == AMD64_RAX);
4857
4858                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4859                                 /* Highly unlikely, but possible */
4860                                 need_push = TRUE;
4861
4862                         /* The pushes invalidate rsp */
4863                         if ((breg == AMD64_RAX) || need_push) {
4864                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4865                                 breg = AMD64_R11;
4866                         }
4867
4868                         /* We need the EAX reg for the comparand */
4869                         if (ins->sreg2 == AMD64_RAX) {
4870                                 if (breg != AMD64_R11) {
4871                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4872                                         sreg2 = AMD64_R11;
4873                                 } else {
4874                                         g_assert (need_push);
4875                                         amd64_push_reg (code, AMD64_RDX);
4876                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4877                                         sreg2 = AMD64_RDX;
4878                                         rdx_pushed = TRUE;
4879                                 }
4880                         }
4881
4882                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4883
4884                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4885                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4886                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4887                         amd64_patch (br [1], br [0]);
4888
4889                         if (rdx_pushed)
4890                                 amd64_pop_reg (code, AMD64_RDX);
4891
4892                         break;
4893                 }
4894                 case OP_ATOMIC_CAS_I4:
4895                 case OP_ATOMIC_CAS_I8: {
4896                         guint32 size;
4897
4898                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4899                                 size = 8;
4900                         else
4901                                 size = 4;
4902
4903                         /*
4904                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4905                          * an explanation of how this works.
4906                          */
4907                         g_assert (ins->sreg3 == AMD64_RAX);
4908                         g_assert (ins->sreg1 != AMD64_RAX);
4909                         g_assert (ins->sreg1 != ins->sreg2);
4910
4911                         amd64_prefix (code, X86_LOCK_PREFIX);
4912                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4913
4914                         if (ins->dreg != AMD64_RAX)
4915                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4916                         break;
4917                 }
4918 #ifdef MONO_ARCH_SIMD_INTRINSICS
4919                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4920                 case OP_ADDPS:
4921                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4922                         break;
4923                 case OP_DIVPS:
4924                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4925                         break;
4926                 case OP_MULPS:
4927                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4928                         break;
4929                 case OP_SUBPS:
4930                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4931                         break;
4932                 case OP_MAXPS:
4933                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4934                         break;
4935                 case OP_MINPS:
4936                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4937                         break;
4938                 case OP_COMPPS:
4939                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4940                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4941                         break;
4942                 case OP_ANDPS:
4943                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
4944                         break;
4945                 case OP_ANDNPS:
4946                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
4947                         break;
4948                 case OP_ORPS:
4949                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
4950                         break;
4951                 case OP_XORPS:
4952                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
4953                         break;
4954                 case OP_SQRTPS:
4955                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4956                         break;
4957                 case OP_RSQRTPS:
4958                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4959                         break;
4960                 case OP_RCPPS:
4961                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
4962                         break;
4963                 case OP_ADDSUBPS:
4964                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4965                         break;
4966                 case OP_HADDPS:
4967                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
4968                         break;
4969                 case OP_HSUBPS:
4970                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4971                         break;
4972                 case OP_DUPPS_HIGH:
4973                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
4974                         break;
4975                 case OP_DUPPS_LOW:
4976                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
4977                         break;
4978
4979                 case OP_PSHUFLEW_HIGH:
4980                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4981                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4982                         break;
4983                 case OP_PSHUFLEW_LOW:
4984                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4985                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4986                         break;
4987                 case OP_PSHUFLED:
4988                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4989                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4990                         break;
4991
4992                 case OP_ADDPD:
4993                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
4994                         break;
4995                 case OP_DIVPD:
4996                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
4997                         break;
4998                 case OP_MULPD:
4999                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5000                         break;
5001                 case OP_SUBPD:
5002                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5003                         break;
5004                 case OP_MAXPD:
5005                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5006                         break;
5007                 case OP_MINPD:
5008                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5009                         break;
5010                 case OP_COMPPD:
5011                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5012                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5013                         break;
5014                 case OP_ANDPD:
5015                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5016                         break;
5017                 case OP_ANDNPD:
5018                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5019                         break;
5020                 case OP_ORPD:
5021                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5022                         break;
5023                 case OP_XORPD:
5024                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5025                         break;
5026                 case OP_SQRTPD:
5027                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5028                         break;
5029                 case OP_ADDSUBPD:
5030                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5031                         break;
5032                 case OP_HADDPD:
5033                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5034                         break;
5035                 case OP_HSUBPD:
5036                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5037                         break;
5038                 case OP_DUPPD:
5039                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5040                         break;
5041
5042                 case OP_EXTRACT_MASK:
5043                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5044                         break;
5045
5046                 case OP_PAND:
5047                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5048                         break;
5049                 case OP_POR:
5050                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5051                         break;
5052                 case OP_PXOR:
5053                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5054                         break;
5055
5056                 case OP_PADDB:
5057                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5058                         break;
5059                 case OP_PADDW:
5060                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5061                         break;
5062                 case OP_PADDD:
5063                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5064                         break;
5065                 case OP_PADDQ:
5066                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5067                         break;
5068
5069                 case OP_PSUBB:
5070                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5071                         break;
5072                 case OP_PSUBW:
5073                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5074                         break;
5075                 case OP_PSUBD:
5076                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5077                         break;
5078                 case OP_PSUBQ:
5079                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5080                         break;
5081
5082                 case OP_PMAXB_UN:
5083                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5084                         break;
5085                 case OP_PMAXW_UN:
5086                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5087                         break;
5088                 case OP_PMAXD_UN:
5089                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5090                         break;
5091
5092                 case OP_PMAXB:
5093                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5094                         break;
5095                 case OP_PMAXW:
5096                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5097                         break;
5098                 case OP_PMAXD:
5099                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5100                         break;
5101
5102                 case OP_PAVGB_UN:
5103                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5104                         break;
5105                 case OP_PAVGW_UN:
5106                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5107                         break;
5108
5109                 case OP_PMINB_UN:
5110                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5111                         break;
5112                 case OP_PMINW_UN:
5113                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5114                         break;
5115                 case OP_PMIND_UN:
5116                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5117                         break;
5118
5119                 case OP_PMINB:
5120                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5121                         break;
5122                 case OP_PMINW:
5123                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5124                         break;
5125                 case OP_PMIND:
5126                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5127                         break;
5128
5129                 case OP_PCMPEQB:
5130                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5131                         break;
5132                 case OP_PCMPEQW:
5133                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5134                         break;
5135                 case OP_PCMPEQD:
5136                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5137                         break;
5138                 case OP_PCMPEQQ:
5139                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5140                         break;
5141
5142                 case OP_PCMPGTB:
5143                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5144                         break;
5145                 case OP_PCMPGTW:
5146                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5147                         break;
5148                 case OP_PCMPGTD:
5149                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5150                         break;
5151                 case OP_PCMPGTQ:
5152                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5153                         break;
5154
5155                 case OP_PSUM_ABS_DIFF:
5156                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5157                         break;
5158
5159                 case OP_UNPACK_LOWB:
5160                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5161                         break;
5162                 case OP_UNPACK_LOWW:
5163                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5164                         break;
5165                 case OP_UNPACK_LOWD:
5166                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5167                         break;
5168                 case OP_UNPACK_LOWQ:
5169                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5170                         break;
5171                 case OP_UNPACK_LOWPS:
5172                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5173                         break;
5174                 case OP_UNPACK_LOWPD:
5175                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5176                         break;
5177
5178                 case OP_UNPACK_HIGHB:
5179                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5180                         break;
5181                 case OP_UNPACK_HIGHW:
5182                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5183                         break;
5184                 case OP_UNPACK_HIGHD:
5185                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5186                         break;
5187                 case OP_UNPACK_HIGHQ:
5188                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5189                         break;
5190                 case OP_UNPACK_HIGHPS:
5191                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5192                         break;
5193                 case OP_UNPACK_HIGHPD:
5194                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5195                         break;
5196
5197                 case OP_PACKW:
5198                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5199                         break;
5200                 case OP_PACKD:
5201                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5202                         break;
5203                 case OP_PACKW_UN:
5204                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5205                         break;
5206                 case OP_PACKD_UN:
5207                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5208                         break;
5209
5210                 case OP_PADDB_SAT_UN:
5211                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5212                         break;
5213                 case OP_PSUBB_SAT_UN:
5214                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5215                         break;
5216                 case OP_PADDW_SAT_UN:
5217                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5218                         break;
5219                 case OP_PSUBW_SAT_UN:
5220                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5221                         break;
5222
5223                 case OP_PADDB_SAT:
5224                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5225                         break;
5226                 case OP_PSUBB_SAT:
5227                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5228                         break;
5229                 case OP_PADDW_SAT:
5230                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5231                         break;
5232                 case OP_PSUBW_SAT:
5233                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5234                         break;
5235
5236                 case OP_PMULW:
5237                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5238                         break;
5239                 case OP_PMULD:
5240                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5241                         break;
5242                 case OP_PMULQ:
5243                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5244                         break;
5245                 case OP_PMULW_HIGH_UN:
5246                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5247                         break;
5248                 case OP_PMULW_HIGH:
5249                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5250                         break;
5251
5252                 case OP_PSHRW:
5253                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5254                         break;
5255                 case OP_PSHRW_REG:
5256                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5257                         break;
5258
5259                 case OP_PSARW:
5260                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5261                         break;
5262                 case OP_PSARW_REG:
5263                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5264                         break;
5265
5266                 case OP_PSHLW:
5267                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5268                         break;
5269                 case OP_PSHLW_REG:
5270                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5271                         break;
5272
5273                 case OP_PSHRD:
5274                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5275                         break;
5276                 case OP_PSHRD_REG:
5277                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5278                         break;
5279
5280                 case OP_PSARD:
5281                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5282                         break;
5283                 case OP_PSARD_REG:
5284                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5285                         break;
5286
5287                 case OP_PSHLD:
5288                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5289                         break;
5290                 case OP_PSHLD_REG:
5291                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5292                         break;
5293
5294                 case OP_PSHRQ:
5295                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5296                         break;
5297                 case OP_PSHRQ_REG:
5298                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5299                         break;
5300
5301                 /*TODO: This is appart of the sse spec but not added
5302                 case OP_PSARQ:
5303                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5304                         break;
5305                 case OP_PSARQ_REG:
5306                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5307                         break;
5308                 */
5309
5310                 case OP_PSHLQ:
5311                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5312                         break;
5313                 case OP_PSHLQ_REG:
5314                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5315                         break;
5316
5317                 case OP_ICONV_TO_X:
5318                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5319                         break;
5320                 case OP_EXTRACT_I4:
5321                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5322                         break;
5323                 case OP_EXTRACT_I8:
5324                         if (ins->inst_c0) {
5325                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5326                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5327                         } else {
5328                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5329                         }
5330                         break;
5331                 case OP_EXTRACT_I1:
5332                 case OP_EXTRACT_U1:
5333                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5334                         if (ins->inst_c0)
5335                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5336                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5337                         break;
5338                 case OP_EXTRACT_I2:
5339                 case OP_EXTRACT_U2:
5340                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5341                         if (ins->inst_c0)
5342                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5343                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5344                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5345                         break;
5346                 case OP_EXTRACT_R8:
5347                         if (ins->inst_c0)
5348                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5349                         else
5350                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5351                         break;
5352                 case OP_INSERT_I2:
5353                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5354                         break;
5355                 case OP_EXTRACTX_U2:
5356                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5357                         break;
5358                 case OP_INSERTX_U1_SLOW:
5359                         /*sreg1 is the extracted ireg (scratch)
5360                         /sreg2 is the to be inserted ireg (scratch)
5361                         /dreg is the xreg to receive the value*/
5362
5363                         /*clear the bits from the extracted word*/
5364                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5365                         /*shift the value to insert if needed*/
5366                         if (ins->inst_c0 & 1)
5367                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5368                         /*join them together*/
5369                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5370                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5371                         break;
5372                 case OP_INSERTX_I4_SLOW:
5373                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5374                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5375                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5376                         break;
5377                 case OP_INSERTX_I8_SLOW:
5378                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5379                         if (ins->inst_c0)
5380                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5381                         else
5382                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5383                         break;
5384
5385                 case OP_INSERTX_R4_SLOW:
5386                         switch (ins->inst_c0) {
5387                         case 0:
5388                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5389                                 break;
5390                         case 1:
5391                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5392                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5393                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5394                                 break;
5395                         case 2:
5396                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5397                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5398                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5399                                 break;
5400                         case 3:
5401                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5402                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5403                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5404                                 break;
5405                         }
5406                         break;
5407                 case OP_INSERTX_R8_SLOW:
5408                         if (ins->inst_c0)
5409                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5410                         else
5411                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5412                         break;
5413                 case OP_STOREX_MEMBASE_REG:
5414                 case OP_STOREX_MEMBASE:
5415                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5416                         break;
5417                 case OP_LOADX_MEMBASE:
5418                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5419                         break;
5420                 case OP_LOADX_ALIGNED_MEMBASE:
5421                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5422                         break;
5423                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5424                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5425                         break;
5426                 case OP_STOREX_NTA_MEMBASE_REG:
5427                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5428                         break;
5429                 case OP_PREFETCH_MEMBASE:
5430                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5431                         break;
5432
5433                 case OP_XMOVE:
5434                         /*FIXME the peephole pass should have killed this*/
5435                         if (ins->dreg != ins->sreg1)
5436                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5437                         break;
5438                 case OP_XZERO:
5439                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5440                         break;
5441                 case OP_ICONV_TO_R8_RAW:
5442                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5443                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5444                         break;
5445
5446                 case OP_FCONV_TO_R8_X:
5447                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5448                         break;
5449
5450                 case OP_XCONV_R8_TO_I4:
5451                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5452                         switch (ins->backend.source_opcode) {
5453                         case OP_FCONV_TO_I1:
5454                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5455                                 break;
5456                         case OP_FCONV_TO_U1:
5457                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5458                                 break;
5459                         case OP_FCONV_TO_I2:
5460                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5461                                 break;
5462                         case OP_FCONV_TO_U2:
5463                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5464                                 break;
5465                         }
5466                         break;
5467
5468                 case OP_EXPAND_I2:
5469                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5470                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5471                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5472                         break;
5473                 case OP_EXPAND_I4:
5474                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5475                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5476                         break;
5477                 case OP_EXPAND_I8:
5478                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5479                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5480                         break;
5481                 case OP_EXPAND_R4:
5482                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5483                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5484                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5485                         break;
5486                 case OP_EXPAND_R8:
5487                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5488                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5489                         break;
5490 #endif
5491                 case OP_LIVERANGE_START: {
5492                         if (cfg->verbose_level > 1)
5493                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5494                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5495                         break;
5496                 }
5497                 case OP_LIVERANGE_END: {
5498                         if (cfg->verbose_level > 1)
5499                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5500                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5501                         break;
5502                 }
5503                 default:
5504                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5505                         g_assert_not_reached ();
5506                 }
5507
5508                 if ((code - cfg->native_code - offset) > max_len) {
5509                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5510                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5511                         g_assert_not_reached ();
5512                 }
5513
5514                 last_ins = ins;
5515                 last_offset = offset;
5516         }
5517
5518         cfg->code_len = code - cfg->native_code;
5519 }
5520
5521 #endif /* DISABLE_JIT */
5522
5523 void
5524 mono_arch_register_lowlevel_calls (void)
5525 {
5526         /* The signature doesn't matter */
5527         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5528 }
5529
5530 void
5531 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5532 {
5533         MonoJumpInfo *patch_info;
5534         gboolean compile_aot = !run_cctors;
5535
5536         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5537                 unsigned char *ip = patch_info->ip.i + code;
5538                 unsigned char *target;
5539
5540                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5541
5542                 if (compile_aot) {
5543                         switch (patch_info->type) {
5544                         case MONO_PATCH_INFO_BB:
5545                         case MONO_PATCH_INFO_LABEL:
5546                                 break;
5547                         default:
5548                                 /* No need to patch these */
5549                                 continue;
5550                         }
5551                 }
5552
5553                 switch (patch_info->type) {
5554                 case MONO_PATCH_INFO_NONE:
5555                         continue;
5556                 case MONO_PATCH_INFO_METHOD_REL:
5557                 case MONO_PATCH_INFO_R8:
5558                 case MONO_PATCH_INFO_R4:
5559                         g_assert_not_reached ();
5560                         continue;
5561                 case MONO_PATCH_INFO_BB:
5562                         break;
5563                 default:
5564                         break;
5565                 }
5566
5567                 /*
5568                  * Debug code to help track down problems where the target of a near call is
5569                  * is not valid.
5570                  */
5571                 if (amd64_is_near_call (ip)) {
5572                         gint64 disp = (guint8*)target - (guint8*)ip;
5573
5574                         if (!amd64_is_imm32 (disp)) {
5575                                 printf ("TYPE: %d\n", patch_info->type);
5576                                 switch (patch_info->type) {
5577                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5578                                         printf ("V: %s\n", patch_info->data.name);
5579                                         break;
5580                                 case MONO_PATCH_INFO_METHOD_JUMP:
5581                                 case MONO_PATCH_INFO_METHOD:
5582                                         printf ("V: %s\n", patch_info->data.method->name);
5583                                         break;
5584                                 default:
5585                                         break;
5586                                 }
5587                         }
5588                 }
5589
5590                 amd64_patch (ip, (gpointer)target);
5591         }
5592 }
5593
5594 static int
5595 get_max_epilog_size (MonoCompile *cfg)
5596 {
5597         int max_epilog_size = 16;
5598
5599         if (cfg->method->save_lmf)
5600                 max_epilog_size += 256;
5601
5602         if (mono_jit_trace_calls != NULL)
5603                 max_epilog_size += 50;
5604
5605         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5606                 max_epilog_size += 50;
5607
5608         max_epilog_size += (AMD64_NREG * 2);
5609
5610         return max_epilog_size;
5611 }
5612
5613 /*
5614  * This macro is used for testing whenever the unwinder works correctly at every point
5615  * where an async exception can happen.
5616  */
5617 /* This will generate a SIGSEGV at the given point in the code */
5618 #define async_exc_point(code) do { \
5619     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5620          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5621              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5622          cfg->arch.async_point_count ++; \
5623     } \
5624 } while (0)
5625
5626 guint8 *
5627 mono_arch_emit_prolog (MonoCompile *cfg)
5628 {
5629         MonoMethod *method = cfg->method;
5630         MonoBasicBlock *bb;
5631         MonoMethodSignature *sig;
5632         MonoInst *ins;
5633         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5634         guint8 *code;
5635         CallInfo *cinfo;
5636         gint32 lmf_offset = cfg->arch.lmf_offset;
5637         gboolean args_clobbered = FALSE;
5638         gboolean trace = FALSE;
5639
5640         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
5641
5642         code = cfg->native_code = g_malloc (cfg->code_size);
5643
5644         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5645                 trace = TRUE;
5646
5647         /* Amount of stack space allocated by register saving code */
5648         pos = 0;
5649
5650         /* Offset between RSP and the CFA */
5651         cfa_offset = 0;
5652
5653         /*
5654          * The prolog consists of the following parts:
5655          * FP present:
5656          * - push rbp, mov rbp, rsp
5657          * - save callee saved regs using pushes
5658          * - allocate frame
5659          * - save rgctx if needed
5660          * - save lmf if needed
5661          * FP not present:
5662          * - allocate frame
5663          * - save rgctx if needed
5664          * - save lmf if needed
5665          * - save callee saved regs using moves
5666          */
5667
5668         // CFA = sp + 8
5669         cfa_offset = 8;
5670         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5671         // IP saved at CFA - 8
5672         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5673         async_exc_point (code);
5674
5675         if (!cfg->arch.omit_fp) {
5676                 amd64_push_reg (code, AMD64_RBP);
5677                 cfa_offset += 8;
5678                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5679                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5680                 async_exc_point (code);
5681 #ifdef HOST_WIN32
5682                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5683 #endif
5684
5685                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5686                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5687                 async_exc_point (code);
5688 #ifdef HOST_WIN32
5689                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5690 #endif
5691         }
5692
5693         /* Save callee saved registers */
5694         if (!cfg->arch.omit_fp && !method->save_lmf) {
5695                 int offset = cfa_offset;
5696
5697                 for (i = 0; i < AMD64_NREG; ++i)
5698                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5699                                 amd64_push_reg (code, i);
5700                                 pos += sizeof (gpointer);
5701                                 offset += 8;
5702                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5703                                 async_exc_point (code);
5704                         }
5705         }
5706
5707         /* The param area is always at offset 0 from sp */
5708         /* This needs to be allocated here, since it has to come after the spill area */
5709         if (cfg->arch.no_pushes && cfg->param_area) {
5710                 if (cfg->arch.omit_fp)
5711                         // FIXME:
5712                         g_assert_not_reached ();
5713                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5714         }
5715
5716         if (cfg->arch.omit_fp) {
5717                 /*
5718                  * On enter, the stack is misaligned by the the pushing of the return
5719                  * address. It is either made aligned by the pushing of %rbp, or by
5720                  * this.
5721                  */
5722                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5723                 if ((alloc_size % 16) == 0)
5724                         alloc_size += 8;
5725         } else {
5726                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5727
5728                 alloc_size -= pos;
5729         }
5730
5731         cfg->arch.stack_alloc_size = alloc_size;
5732
5733         /* Allocate stack frame */
5734         if (alloc_size) {
5735                 /* See mono_emit_stack_alloc */
5736 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5737                 guint32 remaining_size = alloc_size;
5738                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5739                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5740                 guint32 offset = code - cfg->native_code;
5741                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5742                         while (required_code_size >= (cfg->code_size - offset))
5743                                 cfg->code_size *= 2;
5744                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5745                         code = cfg->native_code + offset;
5746                         mono_jit_stats.code_reallocs++;
5747                 }
5748
5749                 while (remaining_size >= 0x1000) {
5750                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5751                         if (cfg->arch.omit_fp) {
5752                                 cfa_offset += 0x1000;
5753                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5754                         }
5755                         async_exc_point (code);
5756 #ifdef HOST_WIN32
5757                         if (cfg->arch.omit_fp)
5758                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5759 #endif
5760
5761                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5762                         remaining_size -= 0x1000;
5763                 }
5764                 if (remaining_size) {
5765                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5766                         if (cfg->arch.omit_fp) {
5767                                 cfa_offset += remaining_size;
5768                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5769                                 async_exc_point (code);
5770                         }
5771 #ifdef HOST_WIN32
5772                         if (cfg->arch.omit_fp)
5773                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5774 #endif
5775                 }
5776 #else
5777                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5778                 if (cfg->arch.omit_fp) {
5779                         cfa_offset += alloc_size;
5780                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5781                         async_exc_point (code);
5782                 }
5783 #endif
5784         }
5785
5786         /* Stack alignment check */
5787 #if 0
5788         {
5789                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5790                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5791                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5792                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5793                 amd64_breakpoint (code);
5794         }
5795 #endif
5796
5797         /* Save LMF */
5798         if (method->save_lmf) {
5799                 /*
5800                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5801                  */
5802                 /* sp is saved right before calls */
5803                 /* Skip method (only needed for trampoline LMF frames) */
5804                 /* Save callee saved regs */
5805                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5806                         int offset;
5807
5808                         switch (i) {
5809                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5810                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5811                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5812                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5813                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5814                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5815 #ifdef HOST_WIN32
5816                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5817                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5818 #endif
5819                         default:
5820                                 offset = -1;
5821                                 break;
5822                         }
5823
5824                         if (offset != -1) {
5825                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5826                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5827                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5828                         }
5829                 }
5830         }
5831
5832         /* Save callee saved registers */
5833         if (cfg->arch.omit_fp && !method->save_lmf) {
5834                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5835
5836                 /* Save caller saved registers after sp is adjusted */
5837                 /* The registers are saved at the bottom of the frame */
5838                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5839                 for (i = 0; i < AMD64_NREG; ++i)
5840                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5841                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5842                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5843                                 save_area_offset += 8;
5844                                 async_exc_point (code);
5845                         }
5846         }
5847
5848         /* store runtime generic context */
5849         if (cfg->rgctx_var) {
5850                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5851                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5852
5853                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5854         }
5855
5856         /* compute max_length in order to use short forward jumps */
5857         max_epilog_size = get_max_epilog_size (cfg);
5858         if (cfg->opt & MONO_OPT_BRANCH) {
5859                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5860                         MonoInst *ins;
5861                         int max_length = 0;
5862
5863                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5864                                 max_length += 6;
5865                         /* max alignment for loops */
5866                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5867                                 max_length += LOOP_ALIGNMENT;
5868
5869                         MONO_BB_FOR_EACH_INS (bb, ins) {
5870                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5871                         }
5872
5873                         /* Take prolog and epilog instrumentation into account */
5874                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5875                                 max_length += max_epilog_size;
5876
5877                         bb->max_length = max_length;
5878                 }
5879         }
5880
5881         sig = mono_method_signature (method);
5882         pos = 0;
5883
5884         cinfo = cfg->arch.cinfo;
5885
5886         if (sig->ret->type != MONO_TYPE_VOID) {
5887                 /* Save volatile arguments to the stack */
5888                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5889                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5890         }
5891
5892         /* Keep this in sync with emit_load_volatile_arguments */
5893         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5894                 ArgInfo *ainfo = cinfo->args + i;
5895                 gint32 stack_offset;
5896                 MonoType *arg_type;
5897
5898                 ins = cfg->args [i];
5899
5900                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5901                         /* Unused arguments */
5902                         continue;
5903
5904                 if (sig->hasthis && (i == 0))
5905                         arg_type = &mono_defaults.object_class->byval_arg;
5906                 else
5907                         arg_type = sig->params [i - sig->hasthis];
5908
5909                 stack_offset = ainfo->offset + ARGS_OFFSET;
5910
5911                 if (cfg->globalra) {
5912                         /* All the other moves are done by the register allocator */
5913                         switch (ainfo->storage) {
5914                         case ArgInFloatSSEReg:
5915                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5916                                 break;
5917                         case ArgValuetypeInReg:
5918                                 for (quad = 0; quad < 2; quad ++) {
5919                                         switch (ainfo->pair_storage [quad]) {
5920                                         case ArgInIReg:
5921                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5922                                                 break;
5923                                         case ArgInFloatSSEReg:
5924                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5925                                                 break;
5926                                         case ArgInDoubleSSEReg:
5927                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5928                                                 break;
5929                                         case ArgNone:
5930                                                 break;
5931                                         default:
5932                                                 g_assert_not_reached ();
5933                                         }
5934                                 }
5935                                 break;
5936                         default:
5937                                 break;
5938                         }
5939
5940                         continue;
5941                 }
5942
5943                 /* Save volatile arguments to the stack */
5944                 if (ins->opcode != OP_REGVAR) {
5945                         switch (ainfo->storage) {
5946                         case ArgInIReg: {
5947                                 guint32 size = 8;
5948
5949                                 /* FIXME: I1 etc */
5950                                 /*
5951                                 if (stack_offset & 0x1)
5952                                         size = 1;
5953                                 else if (stack_offset & 0x2)
5954                                         size = 2;
5955                                 else if (stack_offset & 0x4)
5956                                         size = 4;
5957                                 else
5958                                         size = 8;
5959                                 */
5960                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5961                                 break;
5962                         }
5963                         case ArgInFloatSSEReg:
5964                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5965                                 break;
5966                         case ArgInDoubleSSEReg:
5967                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5968                                 break;
5969                         case ArgValuetypeInReg:
5970                                 for (quad = 0; quad < 2; quad ++) {
5971                                         switch (ainfo->pair_storage [quad]) {
5972                                         case ArgInIReg:
5973                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5974                                                 break;
5975                                         case ArgInFloatSSEReg:
5976                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5977                                                 break;
5978                                         case ArgInDoubleSSEReg:
5979                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5980                                                 break;
5981                                         case ArgNone:
5982                                                 break;
5983                                         default:
5984                                                 g_assert_not_reached ();
5985                                         }
5986                                 }
5987                                 break;
5988                         case ArgValuetypeAddrInIReg:
5989                                 if (ainfo->pair_storage [0] == ArgInIReg)
5990                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5991                                 break;
5992                         default:
5993                                 break;
5994                         }
5995                 } else {
5996                         /* Argument allocated to (non-volatile) register */
5997                         switch (ainfo->storage) {
5998                         case ArgInIReg:
5999                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6000                                 break;
6001                         case ArgOnStack:
6002                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6003                                 break;
6004                         default:
6005                                 g_assert_not_reached ();
6006                         }
6007                 }
6008         }
6009
6010         /* Might need to attach the thread to the JIT  or change the domain for the callback */
6011         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6012                 guint64 domain = (guint64)cfg->domain;
6013
6014                 args_clobbered = TRUE;
6015
6016                 /*
6017                  * The call might clobber argument registers, but they are already
6018                  * saved to the stack/global regs.
6019                  */
6020                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6021                         guint8 *buf, *no_domain_branch;
6022
6023                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6024                         if (cfg->compile_aot) {
6025                                 /* AOT code is only used in the root domain */
6026                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6027                         } else {
6028                                 if ((domain >> 32) == 0)
6029                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6030                                 else
6031                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6032                         }
6033                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6034                         no_domain_branch = code;
6035                         x86_branch8 (code, X86_CC_NE, 0, 0);
6036                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6037                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6038                         buf = code;
6039                         x86_branch8 (code, X86_CC_NE, 0, 0);
6040                         amd64_patch (no_domain_branch, code);
6041                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6042                                           (gpointer)"mono_jit_thread_attach", TRUE);
6043                         amd64_patch (buf, code);
6044 #ifdef HOST_WIN32
6045                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6046                         /* FIXME: Add a separate key for LMF to avoid this */
6047                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6048 #endif
6049                 } else {
6050                         g_assert (!cfg->compile_aot);
6051                         if (cfg->compile_aot) {
6052                                 /* AOT code is only used in the root domain */
6053                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6054                         } else {
6055                                 if ((domain >> 32) == 0)
6056                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6057                                 else
6058                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6059                         }
6060                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6061                                           (gpointer)"mono_jit_thread_attach", TRUE);
6062                 }
6063         }
6064
6065         if (method->save_lmf) {
6066                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6067                         /*
6068                          * Optimized version which uses the mono_lmf TLS variable instead of
6069                          * indirection through the mono_lmf_addr TLS variable.
6070                          */
6071                         /* %rax = previous_lmf */
6072                         x86_prefix (code, X86_FS_PREFIX);
6073                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6074
6075                         /* Save previous_lmf */
6076                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6077                         /* Set new lmf */
6078                         if (lmf_offset == 0) {
6079                                 x86_prefix (code, X86_FS_PREFIX);
6080                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6081                         } else {
6082                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6083                                 x86_prefix (code, X86_FS_PREFIX);
6084                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6085                         }
6086                 } else {
6087                         if (lmf_addr_tls_offset != -1) {
6088                                 /* Load lmf quicky using the FS register */
6089                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6090 #ifdef HOST_WIN32
6091                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6092                                 /* FIXME: Add a separate key for LMF to avoid this */
6093                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6094 #endif
6095                         }
6096                         else {
6097                                 /*
6098                                  * The call might clobber argument registers, but they are already
6099                                  * saved to the stack/global regs.
6100                                  */
6101                                 args_clobbered = TRUE;
6102                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6103                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6104                         }
6105
6106                         /* Save lmf_addr */
6107                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6108                         /* Save previous_lmf */
6109                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6110                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6111                         /* Set new lmf */
6112                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6113                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6114                 }
6115         }
6116
6117         if (trace) {
6118                 args_clobbered = TRUE;
6119                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6120         }
6121
6122         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6123                 args_clobbered = TRUE;
6124
6125         /*
6126          * Optimize the common case of the first bblock making a call with the same
6127          * arguments as the method. This works because the arguments are still in their
6128          * original argument registers.
6129          * FIXME: Generalize this
6130          */
6131         if (!args_clobbered) {
6132                 MonoBasicBlock *first_bb = cfg->bb_entry;
6133                 MonoInst *next;
6134
6135                 next = mono_bb_first_ins (first_bb);
6136                 if (!next && first_bb->next_bb) {
6137                         first_bb = first_bb->next_bb;
6138                         next = mono_bb_first_ins (first_bb);
6139                 }
6140
6141                 if (first_bb->in_count > 1)
6142                         next = NULL;
6143
6144                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6145                         ArgInfo *ainfo = cinfo->args + i;
6146                         gboolean match = FALSE;
6147
6148                         ins = cfg->args [i];
6149                         if (ins->opcode != OP_REGVAR) {
6150                                 switch (ainfo->storage) {
6151                                 case ArgInIReg: {
6152                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6153                                                 if (next->dreg == ainfo->reg) {
6154                                                         NULLIFY_INS (next);
6155                                                         match = TRUE;
6156                                                 } else {
6157                                                         next->opcode = OP_MOVE;
6158                                                         next->sreg1 = ainfo->reg;
6159                                                         /* Only continue if the instruction doesn't change argument regs */
6160                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6161                                                                 match = TRUE;
6162                                                 }
6163                                         }
6164                                         break;
6165                                 }
6166                                 default:
6167                                         break;
6168                                 }
6169                         } else {
6170                                 /* Argument allocated to (non-volatile) register */
6171                                 switch (ainfo->storage) {
6172                                 case ArgInIReg:
6173                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6174                                                 NULLIFY_INS (next);
6175                                                 match = TRUE;
6176                                         }
6177                                         break;
6178                                 default:
6179                                         break;
6180                                 }
6181                         }
6182
6183                         if (match) {
6184                                 next = next->next;
6185                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6186                                 if (!next)
6187                                         break;
6188                         }
6189                 }
6190         }
6191
6192         cfg->code_len = code - cfg->native_code;
6193
6194         g_assert (cfg->code_len < cfg->code_size);
6195
6196         return code;
6197 }
6198
6199 void
6200 mono_arch_emit_epilog (MonoCompile *cfg)
6201 {
6202         MonoMethod *method = cfg->method;
6203         int quad, pos, i;
6204         guint8 *code;
6205         int max_epilog_size;
6206         CallInfo *cinfo;
6207         gint32 lmf_offset = cfg->arch.lmf_offset;
6208
6209         max_epilog_size = get_max_epilog_size (cfg);
6210
6211         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6212                 cfg->code_size *= 2;
6213                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6214                 mono_jit_stats.code_reallocs++;
6215         }
6216
6217         code = cfg->native_code + cfg->code_len;
6218
6219         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6220                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6221
6222         /* the code restoring the registers must be kept in sync with OP_JMP */
6223         pos = 0;
6224
6225         if (method->save_lmf) {
6226                 /* check if we need to restore protection of the stack after a stack overflow */
6227                 if (mono_get_jit_tls_offset () != -1) {
6228                         guint8 *patch;
6229                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6230                         /* we load the value in a separate instruction: this mechanism may be
6231                          * used later as a safer way to do thread interruption
6232                          */
6233                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6234                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6235                         patch = code;
6236                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6237                         /* note that the call trampoline will preserve eax/edx */
6238                         x86_call_reg (code, X86_ECX);
6239                         x86_patch (patch, code);
6240                 } else {
6241                         /* FIXME: maybe save the jit tls in the prolog */
6242                 }
6243                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6244                         /*
6245                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6246                          * through the mono_lmf_addr TLS variable.
6247                          */
6248                         /* reg = previous_lmf */
6249                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6250                         x86_prefix (code, X86_FS_PREFIX);
6251                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6252                 } else {
6253                         /* Restore previous lmf */
6254                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6255                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6256                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6257                 }
6258
6259                 /* Restore caller saved regs */
6260                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6261                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6262                 }
6263                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6264                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6265                 }
6266                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6267                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6268                 }
6269                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6270                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6271                 }
6272                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6273                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6274                 }
6275                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6276                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6277                 }
6278 #ifdef HOST_WIN32
6279                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6280                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6281                 }
6282                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6283                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6284                 }
6285 #endif
6286         } else {
6287
6288                 if (cfg->arch.omit_fp) {
6289                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6290
6291                         for (i = 0; i < AMD64_NREG; ++i)
6292                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6293                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6294                                         save_area_offset += 8;
6295                                 }
6296                 }
6297                 else {
6298                         for (i = 0; i < AMD64_NREG; ++i)
6299                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6300                                         pos -= sizeof (gpointer);
6301
6302                         if (pos) {
6303                                 if (pos == - sizeof (gpointer)) {
6304                                         /* Only one register, so avoid lea */
6305                                         for (i = AMD64_NREG - 1; i > 0; --i)
6306                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6307                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6308                                                 }
6309                                 }
6310                                 else {
6311                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6312
6313                                         /* Pop registers in reverse order */
6314                                         for (i = AMD64_NREG - 1; i > 0; --i)
6315                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6316                                                         amd64_pop_reg (code, i);
6317                                                 }
6318                                 }
6319                         }
6320                 }
6321         }
6322
6323         /* Load returned vtypes into registers if needed */
6324         cinfo = cfg->arch.cinfo;
6325         if (cinfo->ret.storage == ArgValuetypeInReg) {
6326                 ArgInfo *ainfo = &cinfo->ret;
6327                 MonoInst *inst = cfg->ret;
6328
6329                 for (quad = 0; quad < 2; quad ++) {
6330                         switch (ainfo->pair_storage [quad]) {
6331                         case ArgInIReg:
6332                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6333                                 break;
6334                         case ArgInFloatSSEReg:
6335                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6336                                 break;
6337                         case ArgInDoubleSSEReg:
6338                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6339                                 break;
6340                         case ArgNone:
6341                                 break;
6342                         default:
6343                                 g_assert_not_reached ();
6344                         }
6345                 }
6346         }
6347
6348         if (cfg->arch.omit_fp) {
6349                 if (cfg->arch.stack_alloc_size)
6350                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6351         } else {
6352                 amd64_leave (code);
6353         }
6354         async_exc_point (code);
6355         amd64_ret (code);
6356
6357         cfg->code_len = code - cfg->native_code;
6358
6359         g_assert (cfg->code_len < cfg->code_size);
6360 }
6361
6362 void
6363 mono_arch_emit_exceptions (MonoCompile *cfg)
6364 {
6365         MonoJumpInfo *patch_info;
6366         int nthrows, i;
6367         guint8 *code;
6368         MonoClass *exc_classes [16];
6369         guint8 *exc_throw_start [16], *exc_throw_end [16];
6370         guint32 code_size = 0;
6371
6372         /* Compute needed space */
6373         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6374                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6375                         code_size += 40;
6376                 if (patch_info->type == MONO_PATCH_INFO_R8)
6377                         code_size += 8 + 15; /* sizeof (double) + alignment */
6378                 if (patch_info->type == MONO_PATCH_INFO_R4)
6379                         code_size += 4 + 15; /* sizeof (float) + alignment */
6380         }
6381
6382         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6383                 cfg->code_size *= 2;
6384                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6385                 mono_jit_stats.code_reallocs++;
6386         }
6387
6388         code = cfg->native_code + cfg->code_len;
6389
6390         /* add code to raise exceptions */
6391         nthrows = 0;
6392         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6393                 switch (patch_info->type) {
6394                 case MONO_PATCH_INFO_EXC: {
6395                         MonoClass *exc_class;
6396                         guint8 *buf, *buf2;
6397                         guint32 throw_ip;
6398
6399                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6400
6401                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6402                         g_assert (exc_class);
6403                         throw_ip = patch_info->ip.i;
6404
6405                         //x86_breakpoint (code);
6406                         /* Find a throw sequence for the same exception class */
6407                         for (i = 0; i < nthrows; ++i)
6408                                 if (exc_classes [i] == exc_class)
6409                                         break;
6410                         if (i < nthrows) {
6411                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6412                                 x86_jump_code (code, exc_throw_start [i]);
6413                                 patch_info->type = MONO_PATCH_INFO_NONE;
6414                         }
6415                         else {
6416                                 buf = code;
6417                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6418                                 buf2 = code;
6419
6420                                 if (nthrows < 16) {
6421                                         exc_classes [nthrows] = exc_class;
6422                                         exc_throw_start [nthrows] = code;
6423                                 }
6424                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
6425
6426                                 patch_info->type = MONO_PATCH_INFO_NONE;
6427
6428                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6429
6430                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6431                                 while (buf < buf2)
6432                                         x86_nop (buf);
6433
6434                                 if (nthrows < 16) {
6435                                         exc_throw_end [nthrows] = code;
6436                                         nthrows ++;
6437                                 }
6438                         }
6439                         break;
6440                 }
6441                 default:
6442                         /* do nothing */
6443                         break;
6444                 }
6445         }
6446
6447         /* Handle relocations with RIP relative addressing */
6448         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6449                 gboolean remove = FALSE;
6450
6451                 switch (patch_info->type) {
6452                 case MONO_PATCH_INFO_R8:
6453                 case MONO_PATCH_INFO_R4: {
6454                         guint8 *pos;
6455
6456                         /* The SSE opcodes require a 16 byte alignment */
6457                         code = (guint8*)ALIGN_TO (code, 16);
6458
6459                         pos = cfg->native_code + patch_info->ip.i;
6460
6461                         if (IS_REX (pos [1]))
6462                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6463                         else
6464                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6465
6466                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6467                                 *(double*)code = *(double*)patch_info->data.target;
6468                                 code += sizeof (double);
6469                         } else {
6470                                 *(float*)code = *(float*)patch_info->data.target;
6471                                 code += sizeof (float);
6472                         }
6473
6474                         remove = TRUE;
6475                         break;
6476                 }
6477                 default:
6478                         break;
6479                 }
6480
6481                 if (remove) {
6482                         if (patch_info == cfg->patch_info)
6483                                 cfg->patch_info = patch_info->next;
6484                         else {
6485                                 MonoJumpInfo *tmp;
6486
6487                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6488                                         ;
6489                                 tmp->next = patch_info->next;
6490                         }
6491                 }
6492         }
6493
6494         cfg->code_len = code - cfg->native_code;
6495
6496         g_assert (cfg->code_len < cfg->code_size);
6497
6498 }
6499
6500 void*
6501 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6502 {
6503         guchar *code = p;
6504         CallInfo *cinfo = NULL;
6505         MonoMethodSignature *sig;
6506         MonoInst *inst;
6507         int i, n, stack_area = 0;
6508
6509         /* Keep this in sync with mono_arch_get_argument_info */
6510
6511         if (enable_arguments) {
6512                 /* Allocate a new area on the stack and save arguments there */
6513                 sig = mono_method_signature (cfg->method);
6514
6515                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6516
6517                 n = sig->param_count + sig->hasthis;
6518
6519                 stack_area = ALIGN_TO (n * 8, 16);
6520
6521                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6522
6523                 for (i = 0; i < n; ++i) {
6524                         inst = cfg->args [i];
6525
6526                         if (inst->opcode == OP_REGVAR)
6527                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6528                         else {
6529                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6530                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6531                         }
6532                 }
6533         }
6534
6535         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6536         amd64_set_reg_template (code, AMD64_ARG_REG1);
6537         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6538         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6539
6540         if (enable_arguments)
6541                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6542
6543         return code;
6544 }
6545
6546 enum {
6547         SAVE_NONE,
6548         SAVE_STRUCT,
6549         SAVE_EAX,
6550         SAVE_EAX_EDX,
6551         SAVE_XMM
6552 };
6553
6554 void*
6555 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6556 {
6557         guchar *code = p;
6558         int save_mode = SAVE_NONE;
6559         MonoMethod *method = cfg->method;
6560         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
6561
6562         switch (rtype) {
6563         case MONO_TYPE_VOID:
6564                 /* special case string .ctor icall */
6565                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6566                         save_mode = SAVE_EAX;
6567                 else
6568                         save_mode = SAVE_NONE;
6569                 break;
6570         case MONO_TYPE_I8:
6571         case MONO_TYPE_U8:
6572                 save_mode = SAVE_EAX;
6573                 break;
6574         case MONO_TYPE_R4:
6575         case MONO_TYPE_R8:
6576                 save_mode = SAVE_XMM;
6577                 break;
6578         case MONO_TYPE_GENERICINST:
6579                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
6580                         save_mode = SAVE_EAX;
6581                         break;
6582                 }
6583                 /* Fall through */
6584         case MONO_TYPE_VALUETYPE:
6585                 save_mode = SAVE_STRUCT;
6586                 break;
6587         default:
6588                 save_mode = SAVE_EAX;
6589                 break;
6590         }
6591
6592         /* Save the result and copy it into the proper argument register */
6593         switch (save_mode) {
6594         case SAVE_EAX:
6595                 amd64_push_reg (code, AMD64_RAX);
6596                 /* Align stack */
6597                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6598                 if (enable_arguments)
6599                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6600                 break;
6601         case SAVE_STRUCT:
6602                 /* FIXME: */
6603                 if (enable_arguments)
6604                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6605                 break;
6606         case SAVE_XMM:
6607                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6608                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6609                 /* Align stack */
6610                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6611                 /*
6612                  * The result is already in the proper argument register so no copying
6613                  * needed.
6614                  */
6615                 break;
6616         case SAVE_NONE:
6617                 break;
6618         default:
6619                 g_assert_not_reached ();
6620         }
6621
6622         /* Set %al since this is a varargs call */
6623         if (save_mode == SAVE_XMM)
6624                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6625         else
6626                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6627
6628         if (preserve_argument_registers) {
6629                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6630                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6631         }
6632
6633         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6634         amd64_set_reg_template (code, AMD64_ARG_REG1);
6635         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6636
6637         if (preserve_argument_registers) {
6638                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6639                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6640         }
6641
6642         /* Restore result */
6643         switch (save_mode) {
6644         case SAVE_EAX:
6645                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6646                 amd64_pop_reg (code, AMD64_RAX);
6647                 break;
6648         case SAVE_STRUCT:
6649                 /* FIXME: */
6650                 break;
6651         case SAVE_XMM:
6652                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6653                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6654                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6655                 break;
6656         case SAVE_NONE:
6657                 break;
6658         default:
6659                 g_assert_not_reached ();
6660         }
6661
6662         return code;
6663 }
6664
6665 void
6666 mono_arch_flush_icache (guint8 *code, gint size)
6667 {
6668         /* Not needed */
6669 }
6670
6671 void
6672 mono_arch_flush_register_windows (void)
6673 {
6674 }
6675
6676 gboolean
6677 mono_arch_is_inst_imm (gint64 imm)
6678 {
6679         return amd64_is_imm32 (imm);
6680 }
6681
6682 /*
6683  * Determine whenever the trap whose info is in SIGINFO is caused by
6684  * integer overflow.
6685  */
6686 gboolean
6687 mono_arch_is_int_overflow (void *sigctx, void *info)
6688 {
6689         MonoContext ctx;
6690         guint8* rip;
6691         int reg;
6692         gint64 value;
6693
6694         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6695
6696         rip = (guint8*)ctx.rip;
6697
6698         if (IS_REX (rip [0])) {
6699                 reg = amd64_rex_b (rip [0]);
6700                 rip ++;
6701         }
6702         else
6703                 reg = 0;
6704
6705         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6706                 /* idiv REG */
6707                 reg += x86_modrm_rm (rip [1]);
6708
6709                 switch (reg) {
6710                 case AMD64_RAX:
6711                         value = ctx.rax;
6712                         break;
6713                 case AMD64_RBX:
6714                         value = ctx.rbx;
6715                         break;
6716                 case AMD64_RCX:
6717                         value = ctx.rcx;
6718                         break;
6719                 case AMD64_RDX:
6720                         value = ctx.rdx;
6721                         break;
6722                 case AMD64_RBP:
6723                         value = ctx.rbp;
6724                         break;
6725                 case AMD64_RSP:
6726                         value = ctx.rsp;
6727                         break;
6728                 case AMD64_RSI:
6729                         value = ctx.rsi;
6730                         break;
6731                 case AMD64_RDI:
6732                         value = ctx.rdi;
6733                         break;
6734                 case AMD64_R12:
6735                         value = ctx.r12;
6736                         break;
6737                 case AMD64_R13:
6738                         value = ctx.r13;
6739                         break;
6740                 case AMD64_R14:
6741                         value = ctx.r14;
6742                         break;
6743                 case AMD64_R15:
6744                         value = ctx.r15;
6745                         break;
6746                 default:
6747                         g_assert_not_reached ();
6748                         reg = -1;
6749                 }
6750
6751                 if (value == -1)
6752                         return TRUE;
6753         }
6754
6755         return FALSE;
6756 }
6757
6758 guint32
6759 mono_arch_get_patch_offset (guint8 *code)
6760 {
6761         return 3;
6762 }
6763
6764 /**
6765  * mono_breakpoint_clean_code:
6766  *
6767  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6768  * breakpoints in the original code, they are removed in the copy.
6769  *
6770  * Returns TRUE if no sw breakpoint was present.
6771  */
6772 gboolean
6773 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6774 {
6775         int i;
6776         gboolean can_write = TRUE;
6777         /*
6778          * If method_start is non-NULL we need to perform bound checks, since we access memory
6779          * at code - offset we could go before the start of the method and end up in a different
6780          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6781          * instead.
6782          */
6783         if (!method_start || code - offset >= method_start) {
6784                 memcpy (buf, code - offset, size);
6785         } else {
6786                 int diff = code - method_start;
6787                 memset (buf, 0, size);
6788                 memcpy (buf + offset - diff, method_start, diff + size - offset);
6789         }
6790         code -= offset;
6791         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6792                 int idx = mono_breakpoint_info_index [i];
6793                 guint8 *ptr;
6794                 if (idx < 1)
6795                         continue;
6796                 ptr = mono_breakpoint_info [idx].address;
6797                 if (ptr >= code && ptr < code + size) {
6798                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6799                         can_write = FALSE;
6800                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6801                         buf [ptr - code] = saved_byte;
6802                 }
6803         }
6804         return can_write;
6805 }
6806
6807 gpointer
6808 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6809 {
6810         guint8 buf [10];
6811         guint32 reg;
6812         gint32 disp;
6813         guint8 rex = 0;
6814         MonoJitInfo *ji = NULL;
6815
6816 #ifdef ENABLE_LLVM
6817         /* code - 9 might be before the start of the method */
6818         /* FIXME: Avoid this expensive call somehow */
6819         ji = mono_jit_info_table_find (mono_domain_get (), (char*)code);
6820 #endif
6821
6822         mono_breakpoint_clean_code (ji ? ji->code_start : NULL, code, 9, buf, sizeof (buf));
6823         code = buf + 9;
6824
6825         *displacement = 0;
6826
6827         code -= 7;
6828
6829         /*
6830          * A given byte sequence can match more than case here, so we have to be
6831          * really careful about the ordering of the cases. Longer sequences
6832          * come first.
6833          * There are two types of calls:
6834          * - direct calls: 0xff address_byte 8/32 bits displacement
6835          * - indirect calls: nop nop nop <call>
6836          * The nops make sure we don't confuse the instruction preceeding an indirect
6837          * call with a direct call.
6838          */
6839         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6840                 /* call OFFSET(%rip) */
6841                 disp = *(guint32*)(code + 3);
6842                 return (gpointer*)(code + disp + 7);
6843         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
6844                 /* call *[reg+disp32] using indexed addressing */
6845                 /* The LLVM JIT emits this, and we emit it too for %r12 */
6846                 if (IS_REX (code [-1])) {
6847                         rex = code [-1];
6848                         g_assert (amd64_rex_x (rex) == 0);
6849                 }
6850                 reg = amd64_sib_base (code [2]);
6851                 disp = *(gint32*)(code + 3);
6852         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6853                 /* call *[reg+disp32] */
6854                 if (IS_REX (code [0]))
6855                         rex = code [0];
6856                 reg = amd64_modrm_rm (code [2]);
6857                 disp = *(gint32*)(code + 3);
6858                 /* R10 is clobbered by the IMT thunk code */
6859                 g_assert (reg != AMD64_R10);
6860         } else if (code [2] == 0xe8) {
6861                 /* call <ADDR> */
6862                 return NULL;
6863         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
6864                 /* call *[r12+disp8] using indexed addressing */
6865                 if (IS_REX (code [2]))
6866                         rex = code [2];
6867                 reg = amd64_sib_base (code [5]);
6868                 disp = *(gint8*)(code + 6);
6869         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6870                 /* call *%reg */
6871                 return NULL;
6872         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6873                 /* call *[reg+disp8] */
6874                 if (IS_REX (code [3]))
6875                         rex = code [3];
6876                 reg = amd64_modrm_rm (code [5]);
6877                 disp = *(gint8*)(code + 6);
6878                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6879         }
6880         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6881                 /* call *%reg */
6882                 if (IS_REX (code [4]))
6883                         rex = code [4];
6884                 reg = amd64_modrm_rm (code [6]);
6885                 disp = 0;
6886         }
6887         else
6888                 g_assert_not_reached ();
6889
6890         reg += amd64_rex_b (rex);
6891
6892         /* R11 is clobbered by the trampoline code */
6893         g_assert (reg != AMD64_R11);
6894
6895         *displacement = disp;
6896         return (gpointer)regs [reg];
6897 }
6898
6899 int
6900 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6901 {
6902         int this_reg = AMD64_ARG_REG1;
6903
6904         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6905                 CallInfo *cinfo;
6906
6907                 if (!gsctx && code)
6908                         gsctx = mono_get_generic_context_from_code (code);
6909
6910                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6911
6912                 if (cinfo->ret.storage != ArgValuetypeInReg)
6913                         this_reg = AMD64_ARG_REG2;
6914                 g_free (cinfo);
6915         }
6916
6917         return this_reg;
6918 }
6919
6920 gpointer
6921 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
6922 {
6923         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6924 }
6925
6926 #define MAX_ARCH_DELEGATE_PARAMS 10
6927
6928 static gpointer
6929 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6930 {
6931         guint8 *code, *start;
6932         int i;
6933
6934         if (has_target) {
6935                 start = code = mono_global_codeman_reserve (64);
6936
6937                 /* Replace the this argument with the target */
6938                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6939                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6940                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6941
6942                 g_assert ((code - start) < 64);
6943         } else {
6944                 start = code = mono_global_codeman_reserve (64);
6945
6946                 if (param_count == 0) {
6947                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6948                 } else {
6949                         /* We have to shift the arguments left */
6950                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6951                         for (i = 0; i < param_count; ++i) {
6952 #ifdef HOST_WIN32
6953                                 if (i < 3)
6954                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6955                                 else
6956                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6957 #else
6958                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6959 #endif
6960                         }
6961
6962                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6963                 }
6964                 g_assert ((code - start) < 64);
6965         }
6966
6967         mono_debug_add_delegate_trampoline (start, code - start);
6968
6969         if (code_len)
6970                 *code_len = code - start;
6971
6972         return start;
6973 }
6974
6975 /*
6976  * mono_arch_get_delegate_invoke_impls:
6977  *
6978  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
6979  * trampolines.
6980  */
6981 GSList*
6982 mono_arch_get_delegate_invoke_impls (void)
6983 {
6984         GSList *res = NULL;
6985         guint8 *code;
6986         guint32 code_len;
6987         int i;
6988
6989         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6990         res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
6991
6992         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6993                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6994                 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
6995         }
6996
6997         return res;
6998 }
6999
7000 gpointer
7001 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7002 {
7003         guint8 *code, *start;
7004         int i;
7005
7006         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7007                 return NULL;
7008
7009         /* FIXME: Support more cases */
7010         if (MONO_TYPE_ISSTRUCT (sig->ret))
7011                 return NULL;
7012
7013         if (has_target) {
7014                 static guint8* cached = NULL;
7015
7016                 if (cached)
7017                         return cached;
7018
7019                 if (mono_aot_only)
7020                         start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
7021                 else
7022                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7023
7024                 mono_memory_barrier ();
7025
7026                 cached = start;
7027         } else {
7028                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7029                 for (i = 0; i < sig->param_count; ++i)
7030                         if (!mono_is_regsize_var (sig->params [i]))
7031                                 return NULL;
7032                 if (sig->param_count > 4)
7033                         return NULL;
7034
7035                 code = cache [sig->param_count];
7036                 if (code)
7037                         return code;
7038
7039                 if (mono_aot_only) {
7040                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7041                         start = mono_aot_get_named_code (name);
7042                         g_free (name);
7043                 } else {
7044                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7045                 }
7046
7047                 mono_memory_barrier ();
7048
7049                 cache [sig->param_count] = start;
7050         }
7051
7052         return start;
7053 }
7054
7055 /*
7056  * Support for fast access to the thread-local lmf structure using the GS
7057  * segment register on NPTL + kernel 2.6.x.
7058  */
7059
7060 static gboolean tls_offset_inited = FALSE;
7061
7062 void
7063 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7064 {
7065         if (!tls_offset_inited) {
7066 #ifdef HOST_WIN32
7067                 /*
7068                  * We need to init this multiple times, since when we are first called, the key might not
7069                  * be initialized yet.
7070                  */
7071                 appdomain_tls_offset = mono_domain_get_tls_key ();
7072                 lmf_tls_offset = mono_get_jit_tls_key ();
7073                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7074
7075                 /* Only 64 tls entries can be accessed using inline code */
7076                 if (appdomain_tls_offset >= 64)
7077                         appdomain_tls_offset = -1;
7078                 if (lmf_tls_offset >= 64)
7079                         lmf_tls_offset = -1;
7080 #else
7081                 tls_offset_inited = TRUE;
7082 #ifdef MONO_XEN_OPT
7083                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7084 #endif
7085                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7086                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7087                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7088 #endif
7089         }
7090 }
7091
7092 void
7093 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7094 {
7095 }
7096
7097 #ifdef MONO_ARCH_HAVE_IMT
7098
7099 #define CMP_SIZE (6 + 1)
7100 #define CMP_REG_REG_SIZE (4 + 1)
7101 #define BR_SMALL_SIZE 2
7102 #define BR_LARGE_SIZE 6
7103 #define MOV_REG_IMM_SIZE 10
7104 #define MOV_REG_IMM_32BIT_SIZE 6
7105 #define JUMP_REG_SIZE (2 + 1)
7106
7107 static int
7108 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7109 {
7110         int i, distance = 0;
7111         for (i = start; i < target; ++i)
7112                 distance += imt_entries [i]->chunk_size;
7113         return distance;
7114 }
7115
7116 /*
7117  * LOCKING: called with the domain lock held
7118  */
7119 gpointer
7120 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7121         gpointer fail_tramp)
7122 {
7123         int i;
7124         int size = 0;
7125         guint8 *code, *start;
7126         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7127
7128         for (i = 0; i < count; ++i) {
7129                 MonoIMTCheckItem *item = imt_entries [i];
7130                 if (item->is_equals) {
7131                         if (item->check_target_idx) {
7132                                 if (!item->compare_done) {
7133                                         if (amd64_is_imm32 (item->key))
7134                                                 item->chunk_size += CMP_SIZE;
7135                                         else
7136                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7137                                 }
7138                                 if (item->has_target_code) {
7139                                         item->chunk_size += MOV_REG_IMM_SIZE;
7140                                 } else {
7141                                         if (vtable_is_32bit)
7142                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7143                                         else
7144                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7145                                 }
7146                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7147                         } else {
7148                                 if (fail_tramp) {
7149                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7150                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7151                                 } else {
7152                                         if (vtable_is_32bit)
7153                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7154                                         else
7155                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7156                                         item->chunk_size += JUMP_REG_SIZE;
7157                                         /* with assert below:
7158                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7159                                          */
7160                                 }
7161                         }
7162                 } else {
7163                         if (amd64_is_imm32 (item->key))
7164                                 item->chunk_size += CMP_SIZE;
7165                         else
7166                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7167                         item->chunk_size += BR_LARGE_SIZE;
7168                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7169                 }
7170                 size += item->chunk_size;
7171         }
7172         if (fail_tramp)
7173                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7174         else
7175                 code = mono_domain_code_reserve (domain, size);
7176         start = code;
7177         for (i = 0; i < count; ++i) {
7178                 MonoIMTCheckItem *item = imt_entries [i];
7179                 item->code_target = code;
7180                 if (item->is_equals) {
7181                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7182
7183                         if (item->check_target_idx || fail_case) {
7184                                 if (!item->compare_done || fail_case) {
7185                                         if (amd64_is_imm32 (item->key))
7186                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7187                                         else {
7188                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7189                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7190                                         }
7191                                 }
7192                                 item->jmp_code = code;
7193                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7194                                 /* See the comment below about R10 */
7195                                 if (item->has_target_code) {
7196                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
7197                                         amd64_jump_reg (code, AMD64_R10);
7198                                 } else {
7199                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7200                                         amd64_jump_membase (code, AMD64_R10, 0);
7201                                 }
7202
7203                                 if (fail_case) {
7204                                         amd64_patch (item->jmp_code, code);
7205                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
7206                                         amd64_jump_reg (code, AMD64_R10);
7207                                         item->jmp_code = NULL;
7208                                 }
7209                         } else {
7210                                 /* enable the commented code to assert on wrong method */
7211 #if 0
7212                                 if (amd64_is_imm32 (item->key))
7213                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7214                                 else {
7215                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
7216                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7217                                 }
7218                                 item->jmp_code = code;
7219                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7220                                 /* See the comment below about R10 */
7221                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7222                                 amd64_jump_membase (code, AMD64_R10, 0);
7223                                 amd64_patch (item->jmp_code, code);
7224                                 amd64_breakpoint (code);
7225                                 item->jmp_code = NULL;
7226 #else
7227                                 /* We're using R10 here because R11
7228                                    needs to be preserved.  R10 needs
7229                                    to be preserved for calls which
7230                                    require a runtime generic context,
7231                                    but interface calls don't. */
7232                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7233                                 amd64_jump_membase (code, AMD64_R10, 0);
7234 #endif
7235                         }
7236                 } else {
7237                         if (amd64_is_imm32 (item->key))
7238                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7239                         else {
7240                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7241                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7242                         }
7243                         item->jmp_code = code;
7244                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7245                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7246                         else
7247                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7248                 }
7249                 g_assert (code - item->code_target <= item->chunk_size);
7250         }
7251         /* patch the branches to get to the target items */
7252         for (i = 0; i < count; ++i) {
7253                 MonoIMTCheckItem *item = imt_entries [i];
7254                 if (item->jmp_code) {
7255                         if (item->check_target_idx) {
7256                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7257                         }
7258                 }
7259         }
7260
7261         if (!fail_tramp)
7262                 mono_stats.imt_thunks_size += code - start;
7263         g_assert (code - start <= size);
7264
7265         return start;
7266 }
7267
7268 MonoMethod*
7269 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7270 {
7271         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7272 }
7273
7274 MonoObject*
7275 mono_arch_find_this_argument (mgreg_t *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
7276 {
7277         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), regs, NULL);
7278 }
7279 #endif
7280
7281 MonoVTable*
7282 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7283 {
7284         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7285 }
7286
7287 MonoInst*
7288 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7289 {
7290         MonoInst *ins = NULL;
7291         int opcode = 0;
7292
7293         if (cmethod->klass == mono_defaults.math_class) {
7294                 if (strcmp (cmethod->name, "Sin") == 0) {
7295                         opcode = OP_SIN;
7296                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7297                         opcode = OP_COS;
7298                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7299                         opcode = OP_SQRT;
7300                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7301                         opcode = OP_ABS;
7302                 }
7303
7304                 if (opcode) {
7305                         MONO_INST_NEW (cfg, ins, opcode);
7306                         ins->type = STACK_R8;
7307                         ins->dreg = mono_alloc_freg (cfg);
7308                         ins->sreg1 = args [0]->dreg;
7309                         MONO_ADD_INS (cfg->cbb, ins);
7310                 }
7311
7312                 opcode = 0;
7313                 if (cfg->opt & MONO_OPT_CMOV) {
7314                         if (strcmp (cmethod->name, "Min") == 0) {
7315                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7316                                         opcode = OP_IMIN;
7317                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7318                                         opcode = OP_IMIN_UN;
7319                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7320                                         opcode = OP_LMIN;
7321                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7322                                         opcode = OP_LMIN_UN;
7323                         } else if (strcmp (cmethod->name, "Max") == 0) {
7324                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7325                                         opcode = OP_IMAX;
7326                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7327                                         opcode = OP_IMAX_UN;
7328                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7329                                         opcode = OP_LMAX;
7330                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7331                                         opcode = OP_LMAX_UN;
7332                         }
7333                 }
7334
7335                 if (opcode) {
7336                         MONO_INST_NEW (cfg, ins, opcode);
7337                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7338                         ins->dreg = mono_alloc_ireg (cfg);
7339                         ins->sreg1 = args [0]->dreg;
7340                         ins->sreg2 = args [1]->dreg;
7341                         MONO_ADD_INS (cfg->cbb, ins);
7342                 }
7343
7344 #if 0
7345                 /* OP_FREM is not IEEE compatible */
7346                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7347                         MONO_INST_NEW (cfg, ins, OP_FREM);
7348                         ins->inst_i0 = args [0];
7349                         ins->inst_i1 = args [1];
7350                 }
7351 #endif
7352         }
7353
7354         /*
7355          * Can't implement CompareExchange methods this way since they have
7356          * three arguments.
7357          */
7358
7359         return ins;
7360 }
7361
7362 gboolean
7363 mono_arch_print_tree (MonoInst *tree, int arity)
7364 {
7365         return 0;
7366 }
7367
7368 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7369 {
7370         MonoInst* ins;
7371
7372         if (appdomain_tls_offset == -1)
7373                 return NULL;
7374
7375         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7376         ins->inst_offset = appdomain_tls_offset;
7377         return ins;
7378 }
7379
7380 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7381
7382 gpointer
7383 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7384 {
7385         switch (reg) {
7386         case AMD64_RCX: return (gpointer)ctx->rcx;
7387         case AMD64_RDX: return (gpointer)ctx->rdx;
7388         case AMD64_RBX: return (gpointer)ctx->rbx;
7389         case AMD64_RBP: return (gpointer)ctx->rbp;
7390         case AMD64_RSP: return (gpointer)ctx->rsp;
7391         default:
7392                 if (reg < 8)
7393                         return _CTX_REG (ctx, rax, reg);
7394                 else if (reg >= 12)
7395                         return _CTX_REG (ctx, r12, reg - 12);
7396                 else
7397                         g_assert_not_reached ();
7398         }
7399 }
7400
7401 /* Soft Debug support */
7402 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7403
7404 /*
7405  * mono_arch_set_breakpoint:
7406  *
7407  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7408  * The location should contain code emitted by OP_SEQ_POINT.
7409  */
7410 void
7411 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7412 {
7413         guint8 *code = ip;
7414         guint8 *orig_code = code;
7415
7416         /*
7417          * In production, we will use int3 (has to fix the size in the md
7418          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7419          * instead.
7420          */
7421         g_assert (code [0] == 0x90);
7422
7423         g_assert (((guint64)bp_trigger_page >> 32) == 0);
7424
7425         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7426         g_assert (code - orig_code == BREAKPOINT_SIZE);
7427 }
7428
7429 /*
7430  * mono_arch_clear_breakpoint:
7431  *
7432  *   Clear the breakpoint at IP.
7433  */
7434 void
7435 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7436 {
7437         guint8 *code = ip;
7438         int i;
7439
7440         for (i = 0; i < BREAKPOINT_SIZE; ++i)
7441                 x86_nop (code);
7442 }
7443
7444 /*
7445  * mono_arch_start_single_stepping:
7446  *
7447  *   Start single stepping.
7448  */
7449 void
7450 mono_arch_start_single_stepping (void)
7451 {
7452         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7453 }
7454
7455 /*
7456  * mono_arch_stop_single_stepping:
7457  *
7458  *   Stop single stepping.
7459  */
7460 void
7461 mono_arch_stop_single_stepping (void)
7462 {
7463         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7464 }
7465
7466 /*
7467  * mono_arch_is_single_step_event:
7468  *
7469  *   Return whenever the machine state in SIGCTX corresponds to a single
7470  * step event.
7471  */
7472 gboolean
7473 mono_arch_is_single_step_event (void *info, void *sigctx)
7474 {
7475 #ifdef HOST_WIN32
7476         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7477         return FALSE;
7478 #else
7479         siginfo_t* sinfo = (siginfo_t*) info;
7480         /* Sometimes the address is off by 4 */
7481         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7482                 return TRUE;
7483         else
7484                 return FALSE;
7485 #endif
7486 }
7487
7488 gboolean
7489 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7490 {
7491 #ifdef HOST_WIN32
7492         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7493         return FALSE;
7494 #else
7495         siginfo_t* sinfo = (siginfo_t*) info;
7496         /* Sometimes the address is off by 4 */
7497         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7498                 return TRUE;
7499         else
7500                 return FALSE;
7501 #endif
7502 }
7503
7504 /*
7505  * mono_arch_get_ip_for_breakpoint:
7506  *
7507  *   Convert the ip in CTX to the address where a breakpoint was placed.
7508  */
7509 guint8*
7510 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7511 {
7512         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7513
7514         /* size of xor r11, r11 */
7515         ip -= 0;
7516
7517         return ip;
7518 }
7519
7520 /*
7521  * mono_arch_get_ip_for_single_step:
7522  *
7523  *   Convert the ip in CTX to the address stored in seq_points.
7524  */
7525 guint8*
7526 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7527 {
7528         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7529
7530         /* Size of amd64_mov_reg_mem (r11) */
7531         ip += 8;
7532
7533         return ip;
7534 }
7535
7536 /*
7537  * mono_arch_skip_breakpoint:
7538  *
7539  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7540  * we resume, the instruction is not executed again.
7541  */
7542 void
7543 mono_arch_skip_breakpoint (MonoContext *ctx)
7544 {
7545         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
7546 }
7547
7548 /*
7549  * mono_arch_skip_single_step:
7550  *
7551  *   Modify CTX so the ip is placed after the single step trigger instruction,
7552  * we resume, the instruction is not executed again.
7553  */
7554 void
7555 mono_arch_skip_single_step (MonoContext *ctx)
7556 {
7557         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 8);
7558 }
7559
7560 /*
7561  * mono_arch_create_seq_point_info:
7562  *
7563  *   Return a pointer to a data structure which is used by the sequence
7564  * point implementation in AOTed code.
7565  */
7566 gpointer
7567 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7568 {
7569         NOT_IMPLEMENTED;
7570         return NULL;
7571 }
7572
7573 #endif