mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "ir-emit.h"
  30 #include "mini-amd64.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * xmmregs [] = {
 121         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 122         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 123 };
 124
 125 const char*
 126 mono_arch_fregname (int reg)
 127 {
 128         if (reg < AMD64_XMM_NREG)
 129                 return xmmregs [reg];
 130         else
 131                 return "unknown";
 132 }
 133
 134 G_GNUC_UNUSED static void
 135 break_count (void)
 136 {
 137 }
 138
 139 G_GNUC_UNUSED static gboolean
 140 debug_count (void)
 141 {
 142         static int count = 0;
 143         count ++;
 144
 145         if (!getenv ("COUNT"))
 146                 return TRUE;
 147
 148         if (count == atoi (getenv ("COUNT"))) {
 149                 break_count ();
 150         }
 151
 152         if (count > atoi (getenv ("COUNT"))) {
 153                 return FALSE;
 154         }
 155
 156         return TRUE;
 157 }
 158
 159 static gboolean
 160 debug_omit_fp (void)
 161 {
 162 #if 0
 163         return debug_count ();
 164 #else
 165         return TRUE;
 166 #endif
 167 }
 168
 169 static inline gboolean
 170 amd64_is_near_call (guint8 *code)
 171 {
 172         /* Skip REX */
 173         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 174                 code += 1;
 175
 176         return code [0] == 0xe8;
 177 }
 178
 179 static inline void
 180 amd64_patch (unsigned char* code, gpointer target)
 181 {
 182         guint8 rex = 0;
 183
 184         /* Skip REX */
 185         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 186                 rex = code [0];
 187                 code += 1;
 188         }
 189
 190         if ((code [0] & 0xf8) == 0xb8) {
 191                 /* amd64_set_reg_template */
 192                 *(guint64*)(code + 1) = (guint64)target;
 193         }
 194         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 195                 /* mov 0(%rip), %dreg */
 196                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 197         }
 198         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 199                 /* call *<OFFSET>(%rip) */
 200                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 201         }
 202         else if ((code [0] == 0xe8)) {
 203                 /* call <DISP> */
 204                 gint64 disp = (guint8*)target - (guint8*)code;
 205                 g_assert (amd64_is_imm32 (disp));
 206                 x86_patch (code, (unsigned char*)target);
 207         }
 208         else
 209                 x86_patch (code, (unsigned char*)target);
 210 }
 211
 212 void
 213 mono_amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         amd64_patch (code, target);
 216 }
 217
 218 typedef enum {
 219         ArgInIReg,
 220         ArgInFloatSSEReg,
 221         ArgInDoubleSSEReg,
 222         ArgOnStack,
 223         ArgValuetypeInReg,
 224         ArgValuetypeAddrInIReg,
 225         ArgNone /* only in pair_storage */
 226 } ArgStorage;
 227
 228 typedef struct {
 229         gint16 offset;
 230         gint8  reg;
 231         ArgStorage storage;
 232
 233         /* Only if storage == ArgValuetypeInReg */
 234         ArgStorage pair_storage [2];
 235         gint8 pair_regs [2];
 236 } ArgInfo;
 237
 238 typedef struct {
 239         int nargs;
 240         guint32 stack_usage;
 241         guint32 reg_usage;
 242         guint32 freg_usage;
 243         gboolean need_stack_align;
 244         ArgInfo ret;
 245         ArgInfo sig_cookie;
 246         ArgInfo args [1];
 247 } CallInfo;
 248
 249 #define DEBUG(a) if (cfg->verbose_level > 1) a
 250
 251 #ifdef PLATFORM_WIN32
 252 #define PARAM_REGS 4
 253
 254 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 255
 256 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 257 #else
 258 #define PARAM_REGS 6
 259
 260 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 261
 262  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 263 #endif
 264
 265 static void inline
 266 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 267 {
 268     ainfo->offset = *stack_size;
 269
 270     if (*gr >= PARAM_REGS) {
 271                 ainfo->storage = ArgOnStack;
 272                 (*stack_size) += sizeof (gpointer);
 273     }
 274     else {
 275                 ainfo->storage = ArgInIReg;
 276                 ainfo->reg = param_regs [*gr];
 277                 (*gr) ++;
 278     }
 279 }
 280
 281 #ifdef PLATFORM_WIN32
 282 #define FLOAT_PARAM_REGS 4
 283 #else
 284 #define FLOAT_PARAM_REGS 8
 285 #endif
 286
 287 static void inline
 288 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 289 {
 290     ainfo->offset = *stack_size;
 291
 292     if (*gr >= FLOAT_PARAM_REGS) {
 293                 ainfo->storage = ArgOnStack;
 294                 (*stack_size) += sizeof (gpointer);
 295     }
 296     else {
 297                 /* A double register */
 298                 if (is_double)
 299                         ainfo->storage = ArgInDoubleSSEReg;
 300                 else
 301                         ainfo->storage = ArgInFloatSSEReg;
 302                 ainfo->reg = *gr;
 303                 (*gr) += 1;
 304     }
 305 }
 306
 307 typedef enum ArgumentClass {
 308         ARG_CLASS_NO_CLASS,
 309         ARG_CLASS_MEMORY,
 310         ARG_CLASS_INTEGER,
 311         ARG_CLASS_SSE
 312 } ArgumentClass;
 313
 314 static ArgumentClass
 315 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 316 {
 317         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 318         MonoType *ptype;
 319
 320         ptype = mini_type_get_underlying_type (NULL, type);
 321         switch (ptype->type) {
 322         case MONO_TYPE_BOOLEAN:
 323         case MONO_TYPE_CHAR:
 324         case MONO_TYPE_I1:
 325         case MONO_TYPE_U1:
 326         case MONO_TYPE_I2:
 327         case MONO_TYPE_U2:
 328         case MONO_TYPE_I4:
 329         case MONO_TYPE_U4:
 330         case MONO_TYPE_I:
 331         case MONO_TYPE_U:
 332         case MONO_TYPE_STRING:
 333         case MONO_TYPE_OBJECT:
 334         case MONO_TYPE_CLASS:
 335         case MONO_TYPE_SZARRAY:
 336         case MONO_TYPE_PTR:
 337         case MONO_TYPE_FNPTR:
 338         case MONO_TYPE_ARRAY:
 339         case MONO_TYPE_I8:
 340         case MONO_TYPE_U8:
 341                 class2 = ARG_CLASS_INTEGER;
 342                 break;
 343         case MONO_TYPE_R4:
 344         case MONO_TYPE_R8:
 345 #ifdef PLATFORM_WIN32
 346                 class2 = ARG_CLASS_INTEGER;
 347 #else
 348                 class2 = ARG_CLASS_SSE;
 349 #endif
 350                 break;
 351
 352         case MONO_TYPE_TYPEDBYREF:
 353                 g_assert_not_reached ();
 354
 355         case MONO_TYPE_GENERICINST:
 356                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 357                         class2 = ARG_CLASS_INTEGER;
 358                         break;
 359                 }
 360                 /* fall through */
 361         case MONO_TYPE_VALUETYPE: {
 362                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 363                 int i;
 364
 365                 for (i = 0; i < info->num_fields; ++i) {
 366                         class2 = class1;
 367                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 368                 }
 369                 break;
 370         }
 371         default:
 372                 g_assert_not_reached ();
 373         }
 374
 375         /* Merge */
 376         if (class1 == class2)
 377                 ;
 378         else if (class1 == ARG_CLASS_NO_CLASS)
 379                 class1 = class2;
 380         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 381                 class1 = ARG_CLASS_MEMORY;
 382         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 383                 class1 = ARG_CLASS_INTEGER;
 384         else
 385                 class1 = ARG_CLASS_SSE;
 386
 387         return class1;
 388 }
 389
 390 static void
 391 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 392                gboolean is_return,
 393                guint32 *gr, guint32 *fr, guint32 *stack_size)
 394 {
 395         guint32 size, quad, nquads, i;
 396         ArgumentClass args [2];
 397         MonoMarshalType *info = NULL;
 398         MonoClass *klass;
 399         MonoGenericSharingContext tmp_gsctx;
 400
 401         /*
 402          * The gsctx currently contains no data, it is only used for checking whenever
 403          * open types are allowed, some callers like mono_arch_get_argument_info ()
 404          * don't pass it to us, so work around that.
 405          */
 406         if (!gsctx)
 407                 gsctx = &tmp_gsctx;
 408
 409         klass = mono_class_from_mono_type (type);
 410         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 411 #ifndef PLATFORM_WIN32
 412         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 413                 /* We pass and return vtypes of size 8 in a register */
 414         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 415 #else
 416         if (!sig->pinvoke) {
 417 #endif
 418                 /* Allways pass in memory */
 419                 ainfo->offset = *stack_size;
 420                 *stack_size += ALIGN_TO (size, 8);
 421                 ainfo->storage = ArgOnStack;
 422
 423                 return;
 424         }
 425
 426         /* FIXME: Handle structs smaller than 8 bytes */
 427         //if ((size % 8) != 0)
 428         //      NOT_IMPLEMENTED;
 429
 430         if (size > 8)
 431                 nquads = 2;
 432         else
 433                 nquads = 1;
 434
 435         if (!sig->pinvoke) {
 436                 /* Always pass in 1 or 2 integer registers */
 437                 args [0] = ARG_CLASS_INTEGER;
 438                 args [1] = ARG_CLASS_INTEGER;
 439                 /* Only the simplest cases are supported */
 440                 if (is_return && nquads != 1) {
 441                         args [0] = ARG_CLASS_MEMORY;
 442                         args [1] = ARG_CLASS_MEMORY;
 443                 }
 444         } else {
 445                 /*
 446                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 447                  * The X87 and SSEUP stuff is left out since there are no such types in
 448                  * the CLR.
 449                  */
 450                 info = mono_marshal_load_type_info (klass);
 451                 g_assert (info);
 452
 453 #ifndef PLATFORM_WIN32
 454                 if (info->native_size > 16) {
 455                         ainfo->offset = *stack_size;
 456                         *stack_size += ALIGN_TO (info->native_size, 8);
 457                         ainfo->storage = ArgOnStack;
 458
 459                         return;
 460                 }
 461 #else
 462                 switch (info->native_size) {
 463                 case 1: case 2: case 4: case 8:
 464                         break;
 465                 default:
 466                         if (is_return) {
 467                                 ainfo->storage = ArgOnStack;
 468                                 ainfo->offset = *stack_size;
 469                                 *stack_size += ALIGN_TO (info->native_size, 8);
 470                         }
 471                         else {
 472                                 ainfo->storage = ArgValuetypeAddrInIReg;
 473
 474                                 if (*gr < PARAM_REGS) {
 475                                         ainfo->pair_storage [0] = ArgInIReg;
 476                                         ainfo->pair_regs [0] = param_regs [*gr];
 477                                         (*gr) ++;
 478                                 }
 479                                 else {
 480                                         ainfo->pair_storage [0] = ArgOnStack;
 481                                         ainfo->offset = *stack_size;
 482                                         *stack_size += 8;
 483                                 }
 484                         }
 485
 486                         return;
 487                 }
 488 #endif
 489
 490                 args [0] = ARG_CLASS_NO_CLASS;
 491                 args [1] = ARG_CLASS_NO_CLASS;
 492                 for (quad = 0; quad < nquads; ++quad) {
 493                         int size;
 494                         guint32 align;
 495                         ArgumentClass class1;
 496
 497                         if (info->num_fields == 0)
 498                                 class1 = ARG_CLASS_MEMORY;
 499                         else
 500                                 class1 = ARG_CLASS_NO_CLASS;
 501                         for (i = 0; i < info->num_fields; ++i) {
 502                                 size = mono_marshal_type_size (info->fields [i].field->type,
 503                                                                                            info->fields [i].mspec,
 504                                                                                            &align, TRUE, klass->unicode);
 505                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 506                                         /* Unaligned field */
 507                                         NOT_IMPLEMENTED;
 508                                 }
 509
 510                                 /* Skip fields in other quad */
 511                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 512                                         continue;
 513                                 if ((quad == 1) && (info->fields [i].offset < 8))
 514                                         continue;
 515
 516                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 517                         }
 518                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 519                         args [quad] = class1;
 520                 }
 521         }
 522
 523         /* Post merger cleanup */
 524         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 525                 args [0] = args [1] = ARG_CLASS_MEMORY;
 526
 527         /* Allocate registers */
 528         {
 529                 int orig_gr = *gr;
 530                 int orig_fr = *fr;
 531
 532                 ainfo->storage = ArgValuetypeInReg;
 533                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 534                 for (quad = 0; quad < nquads; ++quad) {
 535                         switch (args [quad]) {
 536                         case ARG_CLASS_INTEGER:
 537                                 if (*gr >= PARAM_REGS)
 538                                         args [quad] = ARG_CLASS_MEMORY;
 539                                 else {
 540                                         ainfo->pair_storage [quad] = ArgInIReg;
 541                                         if (is_return)
 542                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 543                                         else
 544                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 545                                         (*gr) ++;
 546                                 }
 547                                 break;
 548                         case ARG_CLASS_SSE:
 549                                 if (*fr >= FLOAT_PARAM_REGS)
 550                                         args [quad] = ARG_CLASS_MEMORY;
 551                                 else {
 552                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 553                                         ainfo->pair_regs [quad] = *fr;
 554                                         (*fr) ++;
 555                                 }
 556                                 break;
 557                         case ARG_CLASS_MEMORY:
 558                                 break;
 559                         default:
 560                                 g_assert_not_reached ();
 561                         }
 562                 }
 563
 564                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 565                         /* Revert possible register assignments */
 566                         *gr = orig_gr;
 567                         *fr = orig_fr;
 568
 569                         ainfo->offset = *stack_size;
 570                         if (sig->pinvoke)
 571                                 *stack_size += ALIGN_TO (info->native_size, 8);
 572                         else
 573                                 *stack_size += nquads * sizeof (gpointer);
 574                         ainfo->storage = ArgOnStack;
 575                 }
 576         }
 577 }
 578
 579 /*
 580  * get_call_info:
 581  *
 582  *  Obtain information about a call according to the calling convention.
 583  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 584  * Draft Version 0.23" document for more information.
 585  */
 586 static CallInfo*
 587 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 588 {
 589         guint32 i, gr, fr;
 590         MonoType *ret_type;
 591         int n = sig->hasthis + sig->param_count;
 592         guint32 stack_size = 0;
 593         CallInfo *cinfo;
 594
 595         if (mp)
 596                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 597         else
 598                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 599
 600         gr = 0;
 601         fr = 0;
 602
 603         /* return value */
 604         {
 605                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 606                 switch (ret_type->type) {
 607                 case MONO_TYPE_BOOLEAN:
 608                 case MONO_TYPE_I1:
 609                 case MONO_TYPE_U1:
 610                 case MONO_TYPE_I2:
 611                 case MONO_TYPE_U2:
 612                 case MONO_TYPE_CHAR:
 613                 case MONO_TYPE_I4:
 614                 case MONO_TYPE_U4:
 615                 case MONO_TYPE_I:
 616                 case MONO_TYPE_U:
 617                 case MONO_TYPE_PTR:
 618                 case MONO_TYPE_FNPTR:
 619                 case MONO_TYPE_CLASS:
 620                 case MONO_TYPE_OBJECT:
 621                 case MONO_TYPE_SZARRAY:
 622                 case MONO_TYPE_ARRAY:
 623                 case MONO_TYPE_STRING:
 624                         cinfo->ret.storage = ArgInIReg;
 625                         cinfo->ret.reg = AMD64_RAX;
 626                         break;
 627                 case MONO_TYPE_U8:
 628                 case MONO_TYPE_I8:
 629                         cinfo->ret.storage = ArgInIReg;
 630                         cinfo->ret.reg = AMD64_RAX;
 631                         break;
 632                 case MONO_TYPE_R4:
 633                         cinfo->ret.storage = ArgInFloatSSEReg;
 634                         cinfo->ret.reg = AMD64_XMM0;
 635                         break;
 636                 case MONO_TYPE_R8:
 637                         cinfo->ret.storage = ArgInDoubleSSEReg;
 638                         cinfo->ret.reg = AMD64_XMM0;
 639                         break;
 640                 case MONO_TYPE_GENERICINST:
 641                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 642                                 cinfo->ret.storage = ArgInIReg;
 643                                 cinfo->ret.reg = AMD64_RAX;
 644                                 break;
 645                         }
 646                         /* fall through */
 647                 case MONO_TYPE_VALUETYPE: {
 648                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 649
 650                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 651                         if (cinfo->ret.storage == ArgOnStack)
 652                                 /* The caller passes the address where the value is stored */
 653                                 add_general (&gr, &stack_size, &cinfo->ret);
 654                         break;
 655                 }
 656                 case MONO_TYPE_TYPEDBYREF:
 657                         /* Same as a valuetype with size 24 */
 658                         add_general (&gr, &stack_size, &cinfo->ret);
 659                         ;
 660                         break;
 661                 case MONO_TYPE_VOID:
 662                         break;
 663                 default:
 664                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 665                 }
 666         }
 667
 668         /* this */
 669         if (sig->hasthis)
 670                 add_general (&gr, &stack_size, cinfo->args + 0);
 671
 672         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 673                 gr = PARAM_REGS;
 674                 fr = FLOAT_PARAM_REGS;
 675
 676                 /* Emit the signature cookie just before the implicit arguments */
 677                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 678         }
 679
 680         for (i = 0; i < sig->param_count; ++i) {
 681                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 682                 MonoType *ptype;
 683
 684 #ifdef PLATFORM_WIN32
 685                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 686                 if (gr > fr)
 687                         fr = gr;
 688                 else if (fr > gr)
 689                         gr = fr;
 690 #endif
 691
 692                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 693                         /* We allways pass the sig cookie on the stack for simplicity */
 694                         /*
 695                          * Prevent implicit arguments + the sig cookie from being passed
 696                          * in registers.
 697                          */
 698                         gr = PARAM_REGS;
 699                         fr = FLOAT_PARAM_REGS;
 700
 701                         /* Emit the signature cookie just before the implicit arguments */
 702                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 703                 }
 704
 705                 if (sig->params [i]->byref) {
 706                         add_general (&gr, &stack_size, ainfo);
 707                         continue;
 708                 }
 709                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 710                 switch (ptype->type) {
 711                 case MONO_TYPE_BOOLEAN:
 712                 case MONO_TYPE_I1:
 713                 case MONO_TYPE_U1:
 714                         add_general (&gr, &stack_size, ainfo);
 715                         break;
 716                 case MONO_TYPE_I2:
 717                 case MONO_TYPE_U2:
 718                 case MONO_TYPE_CHAR:
 719                         add_general (&gr, &stack_size, ainfo);
 720                         break;
 721                 case MONO_TYPE_I4:
 722                 case MONO_TYPE_U4:
 723                         add_general (&gr, &stack_size, ainfo);
 724                         break;
 725                 case MONO_TYPE_I:
 726                 case MONO_TYPE_U:
 727                 case MONO_TYPE_PTR:
 728                 case MONO_TYPE_FNPTR:
 729                 case MONO_TYPE_CLASS:
 730                 case MONO_TYPE_OBJECT:
 731                 case MONO_TYPE_STRING:
 732                 case MONO_TYPE_SZARRAY:
 733                 case MONO_TYPE_ARRAY:
 734                         add_general (&gr, &stack_size, ainfo);
 735                         break;
 736                 case MONO_TYPE_GENERICINST:
 737                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 738                                 add_general (&gr, &stack_size, ainfo);
 739                                 break;
 740                         }
 741                         /* fall through */
 742                 case MONO_TYPE_VALUETYPE:
 743                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 744                         break;
 745                 case MONO_TYPE_TYPEDBYREF:
 746 #ifdef PLATFORM_WIN32
 747                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 748 #else
 749                         stack_size += sizeof (MonoTypedRef);
 750                         ainfo->storage = ArgOnStack;
 751 #endif
 752                         break;
 753                 case MONO_TYPE_U8:
 754                 case MONO_TYPE_I8:
 755                         add_general (&gr, &stack_size, ainfo);
 756                         break;
 757                 case MONO_TYPE_R4:
 758                         add_float (&fr, &stack_size, ainfo, FALSE);
 759                         break;
 760                 case MONO_TYPE_R8:
 761                         add_float (&fr, &stack_size, ainfo, TRUE);
 762                         break;
 763                 default:
 764                         g_assert_not_reached ();
 765                 }
 766         }
 767
 768         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 769                 gr = PARAM_REGS;
 770                 fr = FLOAT_PARAM_REGS;
 771
 772                 /* Emit the signature cookie just before the implicit arguments */
 773                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 774         }
 775
 776 #ifdef PLATFORM_WIN32
 777         // There always is 32 bytes reserved on the stack when calling on Winx64
 778         stack_size += 0x20;
 779 #endif
 780
 781         if (stack_size & 0x8) {
 782                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 783                 cinfo->need_stack_align = TRUE;
 784                 stack_size += 8;
 785         }
 786
 787         cinfo->stack_usage = stack_size;
 788         cinfo->reg_usage = gr;
 789         cinfo->freg_usage = fr;
 790         return cinfo;
 791 }
 792
 793 /*
 794  * mono_arch_get_argument_info:
 795  * @csig:  a method signature
 796  * @param_count: the number of parameters to consider
 797  * @arg_info: an array to store the result infos
 798  *
 799  * Gathers information on parameters such as size, alignment and
 800  * padding. arg_info should be large enought to hold param_count + 1 entries.
 801  *
 802  * Returns the size of the argument area on the stack.
 803  */
 804 int
 805 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 806 {
 807         int k;
 808         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 809         guint32 args_size = cinfo->stack_usage;
 810
 811         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 812         if (csig->hasthis) {
 813                 arg_info [0].offset = 0;
 814         }
 815
 816         for (k = 0; k < param_count; k++) {
 817                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 818                 /* FIXME: */
 819                 arg_info [k + 1].size = 0;
 820         }
 821
 822         g_free (cinfo);
 823
 824         return args_size;
 825 }
 826
 827 static int
 828 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 829 {
 830 #ifndef _MSC_VER
 831         __asm__ __volatile__ ("cpuid"
 832                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 833                 : "a" (id));
 834 #else
 835         int info[4];
 836         __cpuid(info, id);
 837         *p_eax = info[0];
 838         *p_ebx = info[1];
 839         *p_ecx = info[2];
 840         *p_edx = info[3];
 841 #endif
 842         return 1;
 843 }
 844
 845 /*
 846  * Initialize the cpu to execute managed code.
 847  */
 848 void
 849 mono_arch_cpu_init (void)
 850 {
 851 #ifndef _MSC_VER
 852         guint16 fpcw;
 853
 854         /* spec compliance requires running with double precision */
 855         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 856         fpcw &= ~X86_FPCW_PRECC_MASK;
 857         fpcw |= X86_FPCW_PREC_DOUBLE;
 858         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 859         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 860 #else
 861         /* TODO: This is crashing on Win64 right now.
 862         * _control87 (_PC_53, MCW_PC);
 863         */
 864 #endif
 865 }
 866
 867 /*
 868  * Initialize architecture specific code.
 869  */
 870 void
 871 mono_arch_init (void)
 872 {
 873         InitializeCriticalSection (&mini_arch_mutex);
 874 }
 875
 876 /*
 877  * Cleanup architecture specific code.
 878  */
 879 void
 880 mono_arch_cleanup (void)
 881 {
 882         DeleteCriticalSection (&mini_arch_mutex);
 883 }
 884
 885 /*
 886  * This function returns the optimizations supported on this cpu.
 887  */
 888 guint32
 889 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 890 {
 891         int eax, ebx, ecx, edx;
 892         guint32 opts = 0;
 893
 894         /* FIXME: AMD64 */
 895
 896         *exclude_mask = 0;
 897         /* Feature Flags function, flags returned in EDX. */
 898         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 899                 if (edx & (1 << 15)) {
 900                         opts |= MONO_OPT_CMOV;
 901                         if (edx & 1)
 902                                 opts |= MONO_OPT_FCMOV;
 903                         else
 904                                 *exclude_mask |= MONO_OPT_FCMOV;
 905                 } else
 906                         *exclude_mask |= MONO_OPT_CMOV;
 907         }
 908
 909         return opts;
 910 }
 911
 912 GList *
 913 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 914 {
 915         GList *vars = NULL;
 916         int i;
 917
 918         for (i = 0; i < cfg->num_varinfo; i++) {
 919                 MonoInst *ins = cfg->varinfo [i];
 920                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 921
 922                 /* unused vars */
 923                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 924                         continue;
 925
 926                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 927                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 928                         continue;
 929
 930                 if (mono_is_regsize_var (ins->inst_vtype)) {
 931                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 932                         g_assert (i == vmv->idx);
 933                         vars = g_list_prepend (vars, vmv);
 934                 }
 935         }
 936
 937         vars = mono_varlist_sort (cfg, vars, 0);
 938
 939         return vars;
 940 }
 941
 942 /**
 943  * mono_arch_compute_omit_fp:
 944  *
 945  *   Determine whenever the frame pointer can be eliminated.
 946  */
 947 static void
 948 mono_arch_compute_omit_fp (MonoCompile *cfg)
 949 {
 950         MonoMethodSignature *sig;
 951         MonoMethodHeader *header;
 952         int i, locals_size;
 953         CallInfo *cinfo;
 954
 955         if (cfg->arch.omit_fp_computed)
 956                 return;
 957
 958         header = mono_method_get_header (cfg->method);
 959
 960         sig = mono_method_signature (cfg->method);
 961
 962         if (!cfg->arch.cinfo)
 963                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 964         cinfo = cfg->arch.cinfo;
 965
 966         /*
 967          * FIXME: Remove some of the restrictions.
 968          */
 969         cfg->arch.omit_fp = TRUE;
 970         cfg->arch.omit_fp_computed = TRUE;
 971
 972         if (cfg->disable_omit_fp)
 973                 cfg->arch.omit_fp = FALSE;
 974
 975         if (!debug_omit_fp ())
 976                 cfg->arch.omit_fp = FALSE;
 977         /*
 978         if (cfg->method->save_lmf)
 979                 cfg->arch.omit_fp = FALSE;
 980         */
 981         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 982                 cfg->arch.omit_fp = FALSE;
 983         if (header->num_clauses)
 984                 cfg->arch.omit_fp = FALSE;
 985         if (cfg->param_area)
 986                 cfg->arch.omit_fp = FALSE;
 987         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 988                 cfg->arch.omit_fp = FALSE;
 989         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 990                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 991                 cfg->arch.omit_fp = FALSE;
 992         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 993                 ArgInfo *ainfo = &cinfo->args [i];
 994
 995                 if (ainfo->storage == ArgOnStack) {
 996                         /*
 997                          * The stack offset can only be determined when the frame
 998                          * size is known.
 999                          */
1000                         cfg->arch.omit_fp = FALSE;
1001                 }
1002         }
1003
1004         locals_size = 0;
1005         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1006                 MonoInst *ins = cfg->varinfo [i];
1007                 int ialign;
1008
1009                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1010         }
1011
1012         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1013                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1014                 cfg->arch.omit_fp = FALSE;
1015         }
1016 }
1017
1018 GList *
1019 mono_arch_get_global_int_regs (MonoCompile *cfg)
1020 {
1021         GList *regs = NULL;
1022
1023         mono_arch_compute_omit_fp (cfg);
1024
1025         if (cfg->globalra) {
1026                 if (cfg->arch.omit_fp)
1027                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1028
1029                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1030                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1031                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1032                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1033                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1034
1035                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1036                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1037                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1041                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1042                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1043         } else {
1044                 if (cfg->arch.omit_fp)
1045                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1046
1047                 /* We use the callee saved registers for global allocation */
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1051                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1052                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1053         }
1054
1055         return regs;
1056 }
1057
1058 GList*
1059 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1060 {
1061         GList *regs = NULL;
1062         int i;
1063
1064         /* All XMM registers */
1065         for (i = 0; i < 16; ++i)
1066                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1067
1068         return regs;
1069 }
1070
1071 GList*
1072 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1073 {
1074         static GList *r = NULL;
1075
1076         if (r == NULL) {
1077                 GList *regs = NULL;
1078
1079                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1080                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1081                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1082                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1083                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1084                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1085
1086                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1093                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1094
1095                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1096         }
1097
1098         return r;
1099 }
1100
1101 GList*
1102 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1103 {
1104         int i;
1105         static GList *r = NULL;
1106
1107         if (r == NULL) {
1108                 GList *regs = NULL;
1109
1110                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1111                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1112
1113                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1114         }
1115
1116         return r;
1117 }
1118
1119 /*
1120  * mono_arch_regalloc_cost:
1121  *
1122  *  Return the cost, in number of memory references, of the action of
1123  * allocating the variable VMV into a register during global register
1124  * allocation.
1125  */
1126 guint32
1127 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1128 {
1129         MonoInst *ins = cfg->varinfo [vmv->idx];
1130
1131         if (cfg->method->save_lmf)
1132                 /* The register is already saved */
1133                 /* substract 1 for the invisible store in the prolog */
1134                 return (ins->opcode == OP_ARG) ? 0 : 1;
1135         else
1136                 /* push+pop */
1137                 return (ins->opcode == OP_ARG) ? 1 : 2;
1138 }
1139
1140 /*
1141  * mono_arch_fill_argument_info:
1142  *
1143  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1144  * of the method.
1145  */
1146 void
1147 mono_arch_fill_argument_info (MonoCompile *cfg)
1148 {
1149         MonoMethodSignature *sig;
1150         MonoMethodHeader *header;
1151         MonoInst *ins;
1152         int i;
1153         CallInfo *cinfo;
1154
1155         header = mono_method_get_header (cfg->method);
1156
1157         sig = mono_method_signature (cfg->method);
1158
1159         cinfo = cfg->arch.cinfo;
1160
1161         /*
1162          * Contrary to mono_arch_allocate_vars (), the information should describe
1163          * where the arguments are at the beginning of the method, not where they can be
1164          * accessed during the execution of the method. The later makes no sense for the
1165          * global register allocator, since a variable can be in more than one location.
1166          */
1167         if (sig->ret->type != MONO_TYPE_VOID) {
1168                 switch (cinfo->ret.storage) {
1169                 case ArgInIReg:
1170                 case ArgInFloatSSEReg:
1171                 case ArgInDoubleSSEReg:
1172                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1173                                 cfg->vret_addr->opcode = OP_REGVAR;
1174                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1175                         }
1176                         else {
1177                                 cfg->ret->opcode = OP_REGVAR;
1178                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1179                         }
1180                         break;
1181                 case ArgValuetypeInReg:
1182                         cfg->ret->opcode = OP_REGOFFSET;
1183                         cfg->ret->inst_basereg = -1;
1184                         cfg->ret->inst_offset = -1;
1185                         break;
1186                 default:
1187                         g_assert_not_reached ();
1188                 }
1189         }
1190
1191         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1192                 ArgInfo *ainfo = &cinfo->args [i];
1193                 MonoType *arg_type;
1194
1195                 ins = cfg->args [i];
1196
1197                 if (sig->hasthis && (i == 0))
1198                         arg_type = &mono_defaults.object_class->byval_arg;
1199                 else
1200                         arg_type = sig->params [i - sig->hasthis];
1201
1202                 switch (ainfo->storage) {
1203                 case ArgInIReg:
1204                 case ArgInFloatSSEReg:
1205                 case ArgInDoubleSSEReg:
1206                         ins->opcode = OP_REGVAR;
1207                         ins->inst_c0 = ainfo->reg;
1208                         break;
1209                 case ArgOnStack:
1210                         ins->opcode = OP_REGOFFSET;
1211                         ins->inst_basereg = -1;
1212                         ins->inst_offset = -1;
1213                         break;
1214                 case ArgValuetypeInReg:
1215                         /* Dummy */
1216                         ins->opcode = OP_NOP;
1217                         break;
1218                 default:
1219                         g_assert_not_reached ();
1220                 }
1221         }
1222 }
1223
1224 void
1225 mono_arch_allocate_vars (MonoCompile *cfg)
1226 {
1227         MonoMethodSignature *sig;
1228         MonoMethodHeader *header;
1229         MonoInst *ins;
1230         int i, offset;
1231         guint32 locals_stack_size, locals_stack_align;
1232         gint32 *offsets;
1233         CallInfo *cinfo;
1234
1235         header = mono_method_get_header (cfg->method);
1236
1237         sig = mono_method_signature (cfg->method);
1238
1239         cinfo = cfg->arch.cinfo;
1240
1241         mono_arch_compute_omit_fp (cfg);
1242
1243         /*
1244          * We use the ABI calling conventions for managed code as well.
1245          * Exception: valuetypes are never passed or returned in registers.
1246          */
1247
1248         if (cfg->arch.omit_fp) {
1249                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1250                 cfg->frame_reg = AMD64_RSP;
1251                 offset = 0;
1252         } else {
1253                 /* Locals are allocated backwards from %fp */
1254                 cfg->frame_reg = AMD64_RBP;
1255                 offset = 0;
1256         }
1257
1258         if (cfg->method->save_lmf) {
1259                 /* Reserve stack space for saving LMF */
1260                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1261                 g_assert (offset == 0);
1262                 if (cfg->arch.omit_fp) {
1263                         cfg->arch.lmf_offset = offset;
1264                         offset += sizeof (MonoLMF);
1265                 }
1266                 else {
1267                         offset += sizeof (MonoLMF);
1268                         cfg->arch.lmf_offset = -offset;
1269                 }
1270         } else {
1271                 if (cfg->arch.omit_fp)
1272                         cfg->arch.reg_save_area_offset = offset;
1273                 /* Reserve space for caller saved registers */
1274                 for (i = 0; i < AMD64_NREG; ++i)
1275                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1276                                 offset += sizeof (gpointer);
1277                         }
1278         }
1279
1280         if (sig->ret->type != MONO_TYPE_VOID) {
1281                 switch (cinfo->ret.storage) {
1282                 case ArgInIReg:
1283                 case ArgInFloatSSEReg:
1284                 case ArgInDoubleSSEReg:
1285                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1286                                 if (cfg->globalra) {
1287                                         cfg->vret_addr->opcode = OP_REGVAR;
1288                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1289                                 } else {
1290                                         /* The register is volatile */
1291                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1292                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1293                                         if (cfg->arch.omit_fp) {
1294                                                 cfg->vret_addr->inst_offset = offset;
1295                                                 offset += 8;
1296                                         } else {
1297                                                 offset += 8;
1298                                                 cfg->vret_addr->inst_offset = -offset;
1299                                         }
1300                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1301                                                 printf ("vret_addr =");
1302                                                 mono_print_ins (cfg->vret_addr);
1303                                         }
1304                                 }
1305                         }
1306                         else {
1307                                 cfg->ret->opcode = OP_REGVAR;
1308                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1309                         }
1310                         break;
1311                 case ArgValuetypeInReg:
1312                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1313                         cfg->ret->opcode = OP_REGOFFSET;
1314                         cfg->ret->inst_basereg = cfg->frame_reg;
1315                         if (cfg->arch.omit_fp) {
1316                                 cfg->ret->inst_offset = offset;
1317                                 offset += 16;
1318                         } else {
1319                                 offset += 16;
1320                                 cfg->ret->inst_offset = - offset;
1321                         }
1322                         break;
1323                 default:
1324                         g_assert_not_reached ();
1325                 }
1326                 if (!cfg->globalra)
1327                         cfg->ret->dreg = cfg->ret->inst_c0;
1328         }
1329
1330         /* Allocate locals */
1331         if (!cfg->globalra) {
1332                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1333                 if (locals_stack_align) {
1334                         offset += (locals_stack_align - 1);
1335                         offset &= ~(locals_stack_align - 1);
1336                 }
1337                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1338                         if (offsets [i] != -1) {
1339                                 MonoInst *ins = cfg->varinfo [i];
1340                                 ins->opcode = OP_REGOFFSET;
1341                                 ins->inst_basereg = cfg->frame_reg;
1342                                 if (cfg->arch.omit_fp)
1343                                         ins->inst_offset = (offset + offsets [i]);
1344                                 else
1345                                         ins->inst_offset = - (offset + offsets [i]);
1346                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1347                         }
1348                 }
1349                 offset += locals_stack_size;
1350         }
1351
1352         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1353                 g_assert (!cfg->arch.omit_fp);
1354                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1355                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1356         }
1357
1358         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1359                 ins = cfg->args [i];
1360                 if (ins->opcode != OP_REGVAR) {
1361                         ArgInfo *ainfo = &cinfo->args [i];
1362                         gboolean inreg = TRUE;
1363                         MonoType *arg_type;
1364
1365                         if (sig->hasthis && (i == 0))
1366                                 arg_type = &mono_defaults.object_class->byval_arg;
1367                         else
1368                                 arg_type = sig->params [i - sig->hasthis];
1369
1370                         if (cfg->globalra) {
1371                                 /* The new allocator needs info about the original locations of the arguments */
1372                                 switch (ainfo->storage) {
1373                                 case ArgInIReg:
1374                                 case ArgInFloatSSEReg:
1375                                 case ArgInDoubleSSEReg:
1376                                         ins->opcode = OP_REGVAR;
1377                                         ins->inst_c0 = ainfo->reg;
1378                                         break;
1379                                 case ArgOnStack:
1380                                         g_assert (!cfg->arch.omit_fp);
1381                                         ins->opcode = OP_REGOFFSET;
1382                                         ins->inst_basereg = cfg->frame_reg;
1383                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1384                                         break;
1385                                 case ArgValuetypeInReg:
1386                                         ins->opcode = OP_REGOFFSET;
1387                                         ins->inst_basereg = cfg->frame_reg;
1388                                         /* These arguments are saved to the stack in the prolog */
1389                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1390                                         if (cfg->arch.omit_fp) {
1391                                                 ins->inst_offset = offset;
1392                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1393                                         } else {
1394                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1395                                                 ins->inst_offset = - offset;
1396                                         }
1397                                         break;
1398                                 default:
1399                                         g_assert_not_reached ();
1400                                 }
1401
1402                                 continue;
1403                         }
1404
1405                         /* FIXME: Allocate volatile arguments to registers */
1406                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1407                                 inreg = FALSE;
1408
1409                         /*
1410                          * Under AMD64, all registers used to pass arguments to functions
1411                          * are volatile across calls.
1412                          * FIXME: Optimize this.
1413                          */
1414                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1415                                 inreg = FALSE;
1416
1417                         ins->opcode = OP_REGOFFSET;
1418
1419                         switch (ainfo->storage) {
1420                         case ArgInIReg:
1421                         case ArgInFloatSSEReg:
1422                         case ArgInDoubleSSEReg:
1423                                 if (inreg) {
1424                                         ins->opcode = OP_REGVAR;
1425                                         ins->dreg = ainfo->reg;
1426                                 }
1427                                 break;
1428                         case ArgOnStack:
1429                                 g_assert (!cfg->arch.omit_fp);
1430                                 ins->opcode = OP_REGOFFSET;
1431                                 ins->inst_basereg = cfg->frame_reg;
1432                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1433                                 break;
1434                         case ArgValuetypeInReg:
1435                                 break;
1436                         case ArgValuetypeAddrInIReg: {
1437                                 MonoInst *indir;
1438                                 g_assert (!cfg->arch.omit_fp);
1439
1440                                 MONO_INST_NEW (cfg, indir, 0);
1441                                 indir->opcode = OP_REGOFFSET;
1442                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1443                                         indir->inst_basereg = cfg->frame_reg;
1444                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1445                                         offset += (sizeof (gpointer));
1446                                         indir->inst_offset = - offset;
1447                                 }
1448                                 else {
1449                                         indir->inst_basereg = cfg->frame_reg;
1450                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1451                                 }
1452
1453                                 ins->opcode = OP_VTARG_ADDR;
1454                                 ins->inst_left = indir;
1455
1456                                 break;
1457                         }
1458                         default:
1459                                 NOT_IMPLEMENTED;
1460                         }
1461
1462                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1463                                 ins->opcode = OP_REGOFFSET;
1464                                 ins->inst_basereg = cfg->frame_reg;
1465                                 /* These arguments are saved to the stack in the prolog */
1466                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1467                                 if (cfg->arch.omit_fp) {
1468                                         ins->inst_offset = offset;
1469                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1470                                 } else {
1471                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1472                                         ins->inst_offset = - offset;
1473                                 }
1474                         }
1475                 }
1476         }
1477
1478         cfg->stack_offset = offset;
1479 }
1480
1481 void
1482 mono_arch_create_vars (MonoCompile *cfg)
1483 {
1484         MonoMethodSignature *sig;
1485         CallInfo *cinfo;
1486
1487         sig = mono_method_signature (cfg->method);
1488
1489         if (!cfg->arch.cinfo)
1490                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1491         cinfo = cfg->arch.cinfo;
1492
1493         if (cinfo->ret.storage == ArgValuetypeInReg)
1494                 cfg->ret_var_is_local = TRUE;
1495
1496         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1497                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1498                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1499                         printf ("vret_addr = ");
1500                         mono_print_ins (cfg->vret_addr);
1501                 }
1502         }
1503 }
1504
1505 static void
1506 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1507 {
1508         MonoInst *ins;
1509
1510         switch (storage) {
1511         case ArgInIReg:
1512                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1513                 ins->dreg = mono_alloc_ireg (cfg);
1514                 ins->sreg1 = tree->dreg;
1515                 MONO_ADD_INS (cfg->cbb, ins);
1516                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1517                 break;
1518         case ArgInFloatSSEReg:
1519                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1520                 ins->dreg = mono_alloc_freg (cfg);
1521                 ins->sreg1 = tree->dreg;
1522                 MONO_ADD_INS (cfg->cbb, ins);
1523
1524                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1525                 break;
1526         case ArgInDoubleSSEReg:
1527                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1528                 ins->dreg = mono_alloc_freg (cfg);
1529                 ins->sreg1 = tree->dreg;
1530                 MONO_ADD_INS (cfg->cbb, ins);
1531
1532                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1533
1534                 break;
1535         default:
1536                 g_assert_not_reached ();
1537         }
1538 }
1539
1540 static int
1541 arg_storage_to_load_membase (ArgStorage storage)
1542 {
1543         switch (storage) {
1544         case ArgInIReg:
1545                 return OP_LOAD_MEMBASE;
1546         case ArgInDoubleSSEReg:
1547                 return OP_LOADR8_MEMBASE;
1548         case ArgInFloatSSEReg:
1549                 return OP_LOADR4_MEMBASE;
1550         default:
1551                 g_assert_not_reached ();
1552         }
1553
1554         return -1;
1555 }
1556
1557 static void
1558 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1559 {
1560         MonoInst *arg;
1561         MonoMethodSignature *tmp_sig;
1562         MonoInst *sig_arg;
1563
1564         if (call->tail_call)
1565                 NOT_IMPLEMENTED;
1566
1567         /* FIXME: Add support for signature tokens to AOT */
1568         cfg->disable_aot = TRUE;
1569
1570         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1571
1572         /*
1573          * mono_ArgIterator_Setup assumes the signature cookie is
1574          * passed first and all the arguments which were before it are
1575          * passed on the stack after the signature. So compensate by
1576          * passing a different signature.
1577          */
1578         tmp_sig = mono_metadata_signature_dup (call->signature);
1579         tmp_sig->param_count -= call->signature->sentinelpos;
1580         tmp_sig->sentinelpos = 0;
1581         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1582
1583         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1584         sig_arg->dreg = mono_alloc_ireg (cfg);
1585         sig_arg->inst_p0 = tmp_sig;
1586         MONO_ADD_INS (cfg->cbb, sig_arg);
1587
1588         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1589         arg->sreg1 = sig_arg->dreg;
1590         MONO_ADD_INS (cfg->cbb, arg);
1591 }
1592
1593 void
1594 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1595 {
1596         MonoInst *arg, *in;
1597         MonoMethodSignature *sig;
1598         int i, n, stack_size;
1599         CallInfo *cinfo;
1600         ArgInfo *ainfo;
1601
1602         stack_size = 0;
1603
1604         sig = call->signature;
1605         n = sig->param_count + sig->hasthis;
1606
1607         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1608
1609         if (cinfo->need_stack_align) {
1610                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1611         }
1612
1613         /*
1614          * Emit all parameters passed in registers in non-reverse order for better readability
1615          * and to help the optimization in emit_prolog ().
1616          */
1617         for (i = 0; i < n; ++i) {
1618                 ainfo = cinfo->args + i;
1619
1620                 in = call->args [i];
1621
1622                 if (ainfo->storage == ArgInIReg)
1623                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1624         }
1625
1626         for (i = n - 1; i >= 0; --i) {
1627                 ainfo = cinfo->args + i;
1628
1629                 in = call->args [i];
1630
1631                 switch (ainfo->storage) {
1632                 case ArgInIReg:
1633                         /* Already done */
1634                         break;
1635                 case ArgInFloatSSEReg:
1636                 case ArgInDoubleSSEReg:
1637                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1638                         break;
1639                 case ArgOnStack:
1640                 case ArgValuetypeInReg:
1641                 case ArgValuetypeAddrInIReg:
1642                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1643                                 MonoInst *call_inst = (MonoInst*)call;
1644                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1645                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1646                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1647                                 guint32 align;
1648                                 guint32 size;
1649
1650                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1651                                         size = sizeof (MonoTypedRef);
1652                                         align = sizeof (gpointer);
1653                                 }
1654                                 else {
1655                                         if (sig->pinvoke)
1656                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1657                                         else {
1658                                                 /*
1659                                                  * Other backends use mono_type_stack_size (), but that
1660                                                  * aligns the size to 8, which is larger than the size of
1661                                                  * the source, leading to reads of invalid memory if the
1662                                                  * source is at the end of address space.
1663                                                  */
1664                                                 size = mono_class_value_size (in->klass, &align);
1665                                         }
1666                                 }
1667                                 g_assert (in->klass);
1668
1669                                 if (size > 0) {
1670                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1671                                         arg->sreg1 = in->dreg;
1672                                         arg->klass = in->klass;
1673                                         arg->backend.size = size;
1674                                         arg->inst_p0 = call;
1675                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1676                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1677
1678                                         MONO_ADD_INS (cfg->cbb, arg);
1679                                 }
1680                         } else {
1681                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1682                                 arg->sreg1 = in->dreg;
1683                                 if (!sig->params [i - sig->hasthis]->byref) {
1684                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1685                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1686                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
1687                                                 arg->inst_destbasereg = X86_ESP;
1688                                                 arg->inst_offset = 0;
1689                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1690                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1691                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
1692                                                 arg->inst_destbasereg = X86_ESP;
1693                                                 arg->inst_offset = 0;
1694                                         }
1695                                 }
1696                                 MONO_ADD_INS (cfg->cbb, arg);
1697                         }
1698                         break;
1699                 default:
1700                         g_assert_not_reached ();
1701                 }
1702
1703                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1704                         /* Emit the signature cookie just before the implicit arguments */
1705                         emit_sig_cookie (cfg, call, cinfo);
1706         }
1707
1708         /* Handle the case where there are no implicit arguments */
1709         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1710                 emit_sig_cookie (cfg, call, cinfo);
1711
1712         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1713                 MonoInst *vtarg;
1714
1715                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1716                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1717                                 /*
1718                                  * Tell the JIT to use a more efficient calling convention: call using
1719                                  * OP_CALL, compute the result location after the call, and save the
1720                                  * result there.
1721                                  */
1722                                 call->vret_in_reg = TRUE;
1723                                 /*
1724                                  * Nullify the instruction computing the vret addr to enable
1725                                  * future optimizations.
1726                                  */
1727                                 if (call->vret_var)
1728                                         NULLIFY_INS (call->vret_var);
1729                         } else {
1730                                 if (call->tail_call)
1731                                         NOT_IMPLEMENTED;
1732                                 /*
1733                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1734                                  * the stack. Push the address here, so the call instruction can
1735                                  * access it.
1736                                  */
1737                                 if (!cfg->arch.vret_addr_loc) {
1738                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1739                                         /* Prevent it from being register allocated or optimized away */
1740                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1741                                 }
1742
1743                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1744                         }
1745                 }
1746                 else {
1747                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1748                         vtarg->sreg1 = call->vret_var->dreg;
1749                         vtarg->dreg = mono_alloc_preg (cfg);
1750                         MONO_ADD_INS (cfg->cbb, vtarg);
1751
1752                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1753                 }
1754         }
1755
1756 #ifdef PLATFORM_WIN32
1757         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1758                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1759         }
1760 #endif
1761
1762         if (cfg->method->save_lmf) {
1763                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1764                 MONO_ADD_INS (cfg->cbb, arg);
1765         }
1766
1767         call->stack_usage = cinfo->stack_usage;
1768 }
1769
1770 void
1771 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1772 {
1773         MonoInst *arg;
1774         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1775         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1776         int size = ins->backend.size;
1777
1778         if (ainfo->storage == ArgValuetypeInReg) {
1779                 MonoInst *load;
1780                 int part;
1781
1782                 for (part = 0; part < 2; ++part) {
1783                         if (ainfo->pair_storage [part] == ArgNone)
1784                                 continue;
1785
1786                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
1787                         load->inst_basereg = src->dreg;
1788                         load->inst_offset = part * sizeof (gpointer);
1789
1790                         switch (ainfo->pair_storage [part]) {
1791                         case ArgInIReg:
1792                                 load->dreg = mono_alloc_ireg (cfg);
1793                                 break;
1794                         case ArgInDoubleSSEReg:
1795                         case ArgInFloatSSEReg:
1796                                 load->dreg = mono_alloc_freg (cfg);
1797                                 break;
1798                         default:
1799                                 g_assert_not_reached ();
1800                         }
1801                         MONO_ADD_INS (cfg->cbb, load);
1802
1803                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
1804                 }
1805         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
1806                 MonoInst *vtaddr, *load;
1807                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
1808
1809                 MONO_INST_NEW (cfg, load, OP_LDADDR);
1810                 load->inst_p0 = vtaddr;
1811                 vtaddr->flags |= MONO_INST_INDIRECT;
1812                 load->type = STACK_MP;
1813                 load->klass = vtaddr->klass;
1814                 load->dreg = mono_alloc_ireg (cfg);
1815                 MONO_ADD_INS (cfg->cbb, load);
1816                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
1817
1818                 if (ainfo->pair_storage [0] == ArgInIReg) {
1819                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
1820                         arg->dreg = mono_alloc_ireg (cfg);
1821                         arg->sreg1 = load->dreg;
1822                         arg->inst_imm = 0;
1823                         MONO_ADD_INS (cfg->cbb, arg);
1824                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
1825                 } else {
1826                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1827                         arg->sreg1 = load->dreg;
1828                         MONO_ADD_INS (cfg->cbb, arg);
1829                 }
1830         } else {
1831                 if (size == 8) {
1832                         /* Can't use this for < 8 since it does an 8 byte memory load */
1833                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1834                         arg->inst_basereg = src->dreg;
1835                         arg->inst_offset = 0;
1836                         MONO_ADD_INS (cfg->cbb, arg);
1837                 } else if (size <= 40) {
1838                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
1839                         mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1840                 } else {
1841                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1842                         arg->inst_basereg = src->dreg;
1843                         arg->inst_offset = 0;
1844                         arg->inst_imm = size;
1845                         MONO_ADD_INS (cfg->cbb, arg);
1846                 }
1847         }
1848 }
1849
1850 void
1851 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1852 {
1853         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
1854
1855         if (!ret->byref) {
1856                 if (ret->type == MONO_TYPE_R4) {
1857                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
1858                         return;
1859                 } else if (ret->type == MONO_TYPE_R8) {
1860                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1861                         return;
1862                 }
1863         }
1864
1865         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1866 }
1867
1868 #define EMIT_COND_BRANCH(ins,cond,sign) \
1869 if (ins->flags & MONO_INST_BRLABEL) { \
1870         if (ins->inst_i0->inst_c0) { \
1871                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1872         } else { \
1873                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1874                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1875                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1876                         x86_branch8 (code, cond, 0, sign); \
1877                 else \
1878                         x86_branch32 (code, cond, 0, sign); \
1879         } \
1880 } else { \
1881         if (ins->inst_true_bb->native_offset) { \
1882                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1883         } else { \
1884                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1885                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1886                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1887                         x86_branch8 (code, cond, 0, sign); \
1888                 else \
1889                         x86_branch32 (code, cond, 0, sign); \
1890         } \
1891 }
1892
1893 /* emit an exception if condition is fail */
1894 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1895         do {                                                        \
1896                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1897                 if (tins == NULL) {                                                                             \
1898                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1899                                         MONO_PATCH_INFO_EXC, exc_name);  \
1900                         x86_branch32 (code, cond, 0, signed);               \
1901                 } else {        \
1902                         EMIT_COND_BRANCH (tins, cond, signed);  \
1903                 }                       \
1904         } while (0);
1905
1906 #define EMIT_FPCOMPARE(code) do { \
1907         amd64_fcompp (code); \
1908         amd64_fnstsw (code); \
1909 } while (0);
1910
1911 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1912     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1913         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1914         amd64_ ##op (code); \
1915         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1916         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1917 } while (0);
1918
1919 static guint8*
1920 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1921 {
1922         gboolean no_patch = FALSE;
1923
1924         /*
1925          * FIXME: Add support for thunks
1926          */
1927         {
1928                 gboolean near_call = FALSE;
1929
1930                 /*
1931                  * Indirect calls are expensive so try to make a near call if possible.
1932                  * The caller memory is allocated by the code manager so it is
1933                  * guaranteed to be at a 32 bit offset.
1934                  */
1935
1936                 if (patch_type != MONO_PATCH_INFO_ABS) {
1937                         /* The target is in memory allocated using the code manager */
1938                         near_call = TRUE;
1939
1940                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1941                                 if (((MonoMethod*)data)->klass->image->aot_module)
1942                                         /* The callee might be an AOT method */
1943                                         near_call = FALSE;
1944                                 if (((MonoMethod*)data)->dynamic)
1945                                         /* The target is in malloc-ed memory */
1946                                         near_call = FALSE;
1947                         }
1948
1949                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1950                                 /*
1951                                  * The call might go directly to a native function without
1952                                  * the wrapper.
1953                                  */
1954                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1955                                 if (mi) {
1956                                         gconstpointer target = mono_icall_get_wrapper (mi);
1957                                         if ((((guint64)target) >> 32) != 0)
1958                                                 near_call = FALSE;
1959                                 }
1960                         }
1961                 }
1962                 else {
1963                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
1964                                 /*
1965                                  * This is not really an optimization, but required because the
1966                                  * generic class init trampolines use R11 to pass the vtable.
1967                                  */
1968                                 near_call = TRUE;
1969                         } else {
1970                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1971                                 if (info) {
1972                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1973                                                 strstr (cfg->method->name, info->name)) {
1974                                                 /* A call to the wrapped function */
1975                                                 if ((((guint64)data) >> 32) == 0)
1976                                                         near_call = TRUE;
1977                                                 no_patch = TRUE;
1978                                         }
1979                                         else if (info->func == info->wrapper) {
1980                                                 /* No wrapper */
1981                                                 if ((((guint64)info->func) >> 32) == 0)
1982                                                         near_call = TRUE;
1983                                         }
1984                                         else {
1985                                                 /* See the comment in mono_codegen () */
1986                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1987                                                         near_call = TRUE;
1988                                         }
1989                                 }
1990                                 else if ((((guint64)data) >> 32) == 0) {
1991                                         near_call = TRUE;
1992                                         no_patch = TRUE;
1993                                 }
1994                         }
1995                 }
1996
1997                 if (cfg->method->dynamic)
1998                         /* These methods are allocated using malloc */
1999                         near_call = FALSE;
2000
2001                 if (cfg->compile_aot) {
2002                         near_call = TRUE;
2003                         no_patch = TRUE;
2004                 }
2005
2006 #ifdef MONO_ARCH_NOMAP32BIT
2007                 near_call = FALSE;
2008 #endif
2009
2010                 if (near_call) {
2011                         /*
2012                          * Align the call displacement to an address divisible by 4 so it does
2013                          * not span cache lines. This is required for code patching to work on SMP
2014                          * systems.
2015                          */
2016                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2017                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2018                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2019                         amd64_call_code (code, 0);
2020                 }
2021                 else {
2022                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2023                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2024                         amd64_call_reg (code, GP_SCRATCH_REG);
2025                 }
2026         }
2027
2028         return code;
2029 }
2030
2031 static inline guint8*
2032 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2033 {
2034 #ifdef PLATFORM_WIN32
2035         if (win64_adjust_stack)
2036                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2037 #endif
2038         code = emit_call_body (cfg, code, patch_type, data);
2039 #ifdef PLATFORM_WIN32
2040         if (win64_adjust_stack)
2041                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2042 #endif
2043
2044         return code;
2045 }
2046
2047 static inline int
2048 store_membase_imm_to_store_membase_reg (int opcode)
2049 {
2050         switch (opcode) {
2051         case OP_STORE_MEMBASE_IMM:
2052                 return OP_STORE_MEMBASE_REG;
2053         case OP_STOREI4_MEMBASE_IMM:
2054                 return OP_STOREI4_MEMBASE_REG;
2055         case OP_STOREI8_MEMBASE_IMM:
2056                 return OP_STOREI8_MEMBASE_REG;
2057         }
2058
2059         return -1;
2060 }
2061
2062 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2063
2064 /*
2065  * mono_arch_peephole_pass_1:
2066  *
2067  *   Perform peephole opts which should/can be performed before local regalloc
2068  */
2069 void
2070 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2071 {
2072         MonoInst *ins, *n;
2073
2074         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2075                 MonoInst *last_ins = ins->prev;
2076
2077                 switch (ins->opcode) {
2078                 case OP_ADD_IMM:
2079                 case OP_IADD_IMM:
2080                 case OP_LADD_IMM:
2081                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2082                                 /*
2083                                  * X86_LEA is like ADD, but doesn't have the
2084                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2085                                  * its operand to 64 bit.
2086                                  */
2087                                 ins->opcode = OP_X86_LEA_MEMBASE;
2088                                 ins->inst_basereg = ins->sreg1;
2089                         }
2090                         break;
2091                 case OP_LXOR:
2092                 case OP_IXOR:
2093                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2094                                 MonoInst *ins2;
2095
2096                                 /*
2097                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2098                                  * the latter has length 2-3 instead of 6 (reverse constant
2099                                  * propagation). These instruction sequences are very common
2100                                  * in the initlocals bblock.
2101                                  */
2102                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2103                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2104                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2105                                                 ins2->sreg1 = ins->dreg;
2106                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2107                                                 /* Continue */
2108                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2109                                                 NULLIFY_INS (ins2);
2110                                                 /* Continue */
2111                                         } else {
2112                                                 break;
2113                                         }
2114                                 }
2115                         }
2116                         break;
2117                 case OP_COMPARE_IMM:
2118                 case OP_LCOMPARE_IMM:
2119                         /* OP_COMPARE_IMM (reg, 0)
2120                          * -->
2121                          * OP_AMD64_TEST_NULL (reg)
2122                          */
2123                         if (!ins->inst_imm)
2124                                 ins->opcode = OP_AMD64_TEST_NULL;
2125                         break;
2126                 case OP_ICOMPARE_IMM:
2127                         if (!ins->inst_imm)
2128                                 ins->opcode = OP_X86_TEST_NULL;
2129                         break;
2130                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2131                         /*
2132                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2133                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2134                          * -->
2135                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2136                          * OP_COMPARE_IMM reg, imm
2137                          *
2138                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2139                          */
2140                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2141                             ins->inst_basereg == last_ins->inst_destbasereg &&
2142                             ins->inst_offset == last_ins->inst_offset) {
2143                                         ins->opcode = OP_ICOMPARE_IMM;
2144                                         ins->sreg1 = last_ins->sreg1;
2145
2146                                         /* check if we can remove cmp reg,0 with test null */
2147                                         if (!ins->inst_imm)
2148                                                 ins->opcode = OP_X86_TEST_NULL;
2149                                 }
2150
2151                         break;
2152                 }
2153
2154                 mono_peephole_ins (bb, ins);
2155         }
2156 }
2157
2158 void
2159 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2160 {
2161         MonoInst *ins, *n;
2162
2163         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2164                 switch (ins->opcode) {
2165                 case OP_ICONST:
2166                 case OP_I8CONST: {
2167                         /* reg = 0 -> XOR (reg, reg) */
2168                         /* XOR sets cflags on x86, so we cant do it always */
2169                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2170                                 ins->opcode = OP_LXOR;
2171                                 ins->sreg1 = ins->dreg;
2172                                 ins->sreg2 = ins->dreg;
2173                                 /* Fall through */
2174                         } else {
2175                                 break;
2176                         }
2177                 }
2178                 case OP_LXOR:
2179                         /*
2180                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2181                          * 0 result into 64 bits.
2182                          */
2183                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2184                                 ins->opcode = OP_IXOR;
2185                         }
2186                         /* Fall through */
2187                 case OP_IXOR:
2188                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2189                                 MonoInst *ins2;
2190
2191                                 /*
2192                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2193                                  * the latter has length 2-3 instead of 6 (reverse constant
2194                                  * propagation). These instruction sequences are very common
2195                                  * in the initlocals bblock.
2196                                  */
2197                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2198                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2199                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2200                                                 ins2->sreg1 = ins->dreg;
2201                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2202                                                 /* Continue */
2203                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2204                                                 NULLIFY_INS (ins2);
2205                                                 /* Continue */
2206                                         } else {
2207                                                 break;
2208                                         }
2209                                 }
2210                         }
2211                         break;
2212                 case OP_IADD_IMM:
2213                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2214                                 ins->opcode = OP_X86_INC_REG;
2215                         break;
2216                 case OP_ISUB_IMM:
2217                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2218                                 ins->opcode = OP_X86_DEC_REG;
2219                         break;
2220                 }
2221
2222                 mono_peephole_ins (bb, ins);
2223         }
2224 }
2225
2226 #define NEW_INS(cfg,ins,dest,op) do {   \
2227                 MONO_INST_NEW ((cfg), (dest), (op)); \
2228         (dest)->cil_code = (ins)->cil_code; \
2229         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2230         } while (0)
2231
2232 /*
2233  * mono_arch_lowering_pass:
2234  *
2235  *  Converts complex opcodes into simpler ones so that each IR instruction
2236  * corresponds to one machine instruction.
2237  */
2238 void
2239 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2240 {
2241         MonoInst *ins, *n, *temp;
2242
2243         /*
2244          * FIXME: Need to add more instructions, but the current machine
2245          * description can't model some parts of the composite instructions like
2246          * cdq.
2247          */
2248         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2249                 switch (ins->opcode) {
2250                 case OP_DIV_IMM:
2251                 case OP_REM_IMM:
2252                 case OP_IDIV_IMM:
2253                 case OP_IDIV_UN_IMM:
2254                 case OP_IREM_UN_IMM:
2255                         mono_decompose_op_imm (cfg, bb, ins);
2256                         break;
2257                 case OP_IREM_IMM:
2258                         /* Keep the opcode if we can implement it efficiently */
2259                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2260                                 mono_decompose_op_imm (cfg, bb, ins);
2261                         break;
2262                 case OP_COMPARE_IMM:
2263                 case OP_LCOMPARE_IMM:
2264                         if (!amd64_is_imm32 (ins->inst_imm)) {
2265                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2266                                 temp->inst_c0 = ins->inst_imm;
2267                                 temp->dreg = mono_alloc_ireg (cfg);
2268                                 ins->opcode = OP_COMPARE;
2269                                 ins->sreg2 = temp->dreg;
2270                         }
2271                         break;
2272                 case OP_LOAD_MEMBASE:
2273                 case OP_LOADI8_MEMBASE:
2274                         if (!amd64_is_imm32 (ins->inst_offset)) {
2275                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2276                                 temp->inst_c0 = ins->inst_offset;
2277                                 temp->dreg = mono_alloc_ireg (cfg);
2278                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2279                                 ins->inst_indexreg = temp->dreg;
2280                         }
2281                         break;
2282                 case OP_STORE_MEMBASE_IMM:
2283                 case OP_STOREI8_MEMBASE_IMM:
2284                         if (!amd64_is_imm32 (ins->inst_imm)) {
2285                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2286                                 temp->inst_c0 = ins->inst_imm;
2287                                 temp->dreg = mono_alloc_ireg (cfg);
2288                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2289                                 ins->sreg1 = temp->dreg;
2290                         }
2291                         break;
2292                 default:
2293                         break;
2294                 }
2295         }
2296
2297         bb->max_vreg = cfg->next_vreg;
2298 }
2299
2300 static const int
2301 branch_cc_table [] = {
2302         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2303         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2304         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2305 };
2306
2307 /* Maps CMP_... constants to X86_CC_... constants */
2308 static const int
2309 cc_table [] = {
2310         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2311         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2312 };
2313
2314 static const int
2315 cc_signed_table [] = {
2316         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2317         FALSE, FALSE, FALSE, FALSE
2318 };
2319
2320 /*#include "cprop.c"*/
2321
2322 static unsigned char*
2323 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2324 {
2325         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2326
2327         if (size == 1)
2328                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2329         else if (size == 2)
2330                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2331         return code;
2332 }
2333
2334 static unsigned char*
2335 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2336 {
2337         int sreg = tree->sreg1;
2338         int need_touch = FALSE;
2339
2340 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2341         if (!tree->flags & MONO_INST_INIT)
2342                 need_touch = TRUE;
2343 #endif
2344
2345         if (need_touch) {
2346                 guint8* br[5];
2347
2348                 /*
2349                  * Under Windows:
2350                  * If requested stack size is larger than one page,
2351                  * perform stack-touch operation
2352                  */
2353                 /*
2354                  * Generate stack probe code.
2355                  * Under Windows, it is necessary to allocate one page at a time,
2356                  * "touching" stack after each successful sub-allocation. This is
2357                  * because of the way stack growth is implemented - there is a
2358                  * guard page before the lowest stack page that is currently commited.
2359                  * Stack normally grows sequentially so OS traps access to the
2360                  * guard page and commits more pages when needed.
2361                  */
2362                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2363                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2364
2365                 br[2] = code; /* loop */
2366                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2367                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2368                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2369                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2370                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2371                 amd64_patch (br[3], br[2]);
2372                 amd64_test_reg_reg (code, sreg, sreg);
2373                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2374                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2375
2376                 br[1] = code; x86_jump8 (code, 0);
2377
2378                 amd64_patch (br[0], code);
2379                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2380                 amd64_patch (br[1], code);
2381                 amd64_patch (br[4], code);
2382         }
2383         else
2384                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2385
2386         if (tree->flags & MONO_INST_INIT) {
2387                 int offset = 0;
2388                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2389                         amd64_push_reg (code, AMD64_RAX);
2390                         offset += 8;
2391                 }
2392                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2393                         amd64_push_reg (code, AMD64_RCX);
2394                         offset += 8;
2395                 }
2396                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2397                         amd64_push_reg (code, AMD64_RDI);
2398                         offset += 8;
2399                 }
2400
2401                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2402                 if (sreg != AMD64_RCX)
2403                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2404                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2405
2406                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2407                 amd64_cld (code);
2408                 amd64_prefix (code, X86_REP_PREFIX);
2409                 amd64_stosl (code);
2410
2411                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2412                         amd64_pop_reg (code, AMD64_RDI);
2413                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2414                         amd64_pop_reg (code, AMD64_RCX);
2415                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2416                         amd64_pop_reg (code, AMD64_RAX);
2417         }
2418         return code;
2419 }
2420
2421 static guint8*
2422 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2423 {
2424         CallInfo *cinfo;
2425         guint32 quad;
2426
2427         /* Move return value to the target register */
2428         /* FIXME: do this in the local reg allocator */
2429         switch (ins->opcode) {
2430         case OP_CALL:
2431         case OP_CALL_REG:
2432         case OP_CALL_MEMBASE:
2433         case OP_LCALL:
2434         case OP_LCALL_REG:
2435         case OP_LCALL_MEMBASE:
2436                 g_assert (ins->dreg == AMD64_RAX);
2437                 break;
2438         case OP_FCALL:
2439         case OP_FCALL_REG:
2440         case OP_FCALL_MEMBASE:
2441                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2442                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2443                 }
2444                 else {
2445                         if (ins->dreg != AMD64_XMM0)
2446                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2447                 }
2448                 break;
2449         case OP_VCALL:
2450         case OP_VCALL_REG:
2451         case OP_VCALL_MEMBASE:
2452         case OP_VCALL2:
2453         case OP_VCALL2_REG:
2454         case OP_VCALL2_MEMBASE:
2455                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2456                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2457                         MonoInst *loc = cfg->arch.vret_addr_loc;
2458
2459                         /* Load the destination address */
2460                         g_assert (loc->opcode == OP_REGOFFSET);
2461                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2462
2463                         for (quad = 0; quad < 2; quad ++) {
2464                                 switch (cinfo->ret.pair_storage [quad]) {
2465                                 case ArgInIReg:
2466                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2467                                         break;
2468                                 case ArgInFloatSSEReg:
2469                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2470                                         break;
2471                                 case ArgInDoubleSSEReg:
2472                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2473                                         break;
2474                                 case ArgNone:
2475                                         break;
2476                                 default:
2477                                         NOT_IMPLEMENTED;
2478                                 }
2479                         }
2480                 }
2481                 break;
2482         }
2483
2484         return code;
2485 }
2486
2487 /*
2488  * mono_amd64_emit_tls_get:
2489  * @code: buffer to store code to
2490  * @dreg: hard register where to place the result
2491  * @tls_offset: offset info
2492  *
2493  * mono_amd64_emit_tls_get emits in @code the native code that puts in
2494  * the dreg register the item in the thread local storage identified
2495  * by tls_offset.
2496  *
2497  * Returns: a pointer to the end of the stored code
2498  */
2499 guint8*
2500 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2501 {
2502 #ifdef PLATFORM_WIN32
2503         g_assert (tls_offset < 64);
2504         x86_prefix (code, X86_GS_PREFIX);
2505         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2506 #else
2507         if (optimize_for_xen) {
2508                 x86_prefix (code, X86_FS_PREFIX);
2509                 amd64_mov_reg_mem (code, dreg, 0, 8);
2510                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2511         } else {
2512                 x86_prefix (code, X86_FS_PREFIX);
2513                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2514         }
2515 #endif
2516         return code;
2517 }
2518
2519 #define REAL_PRINT_REG(text,reg) \
2520 mono_assert (reg >= 0); \
2521 amd64_push_reg (code, AMD64_RAX); \
2522 amd64_push_reg (code, AMD64_RDX); \
2523 amd64_push_reg (code, AMD64_RCX); \
2524 amd64_push_reg (code, reg); \
2525 amd64_push_imm (code, reg); \
2526 amd64_push_imm (code, text " %d %p\n"); \
2527 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2528 amd64_call_reg (code, AMD64_RAX); \
2529 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2530 amd64_pop_reg (code, AMD64_RCX); \
2531 amd64_pop_reg (code, AMD64_RDX); \
2532 amd64_pop_reg (code, AMD64_RAX);
2533
2534 /* benchmark and set based on cpu */
2535 #define LOOP_ALIGNMENT 8
2536 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2537
2538 #ifndef DISABLE_JIT
2539
2540 void
2541 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2542 {
2543         MonoInst *ins;
2544         MonoCallInst *call;
2545         guint offset;
2546         guint8 *code = cfg->native_code + cfg->code_len;
2547         MonoInst *last_ins = NULL;
2548         guint last_offset = 0;
2549         int max_len, cpos;
2550
2551         if (cfg->opt & MONO_OPT_LOOP) {
2552                 int pad, align = LOOP_ALIGNMENT;
2553                 /* set alignment depending on cpu */
2554                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2555                         pad = align - pad;
2556                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2557                         amd64_padding (code, pad);
2558                         cfg->code_len += pad;
2559                         bb->native_offset = cfg->code_len;
2560                 }
2561         }
2562
2563         if (cfg->verbose_level > 2)
2564                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2565
2566         cpos = bb->max_offset;
2567
2568         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2569                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2570                 g_assert (!cfg->compile_aot);
2571                 cpos += 6;
2572
2573                 cov->data [bb->dfn].cil_code = bb->cil_code;
2574                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2575                 /* this is not thread save, but good enough */
2576                 amd64_inc_membase (code, AMD64_R11, 0);
2577         }
2578
2579         offset = code - cfg->native_code;
2580
2581         mono_debug_open_block (cfg, bb, offset);
2582
2583     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2584                 x86_breakpoint (code);
2585
2586         MONO_BB_FOR_EACH_INS (bb, ins) {
2587                 offset = code - cfg->native_code;
2588
2589                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2590
2591                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2592                         cfg->code_size *= 2;
2593                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2594                         code = cfg->native_code + offset;
2595                         mono_jit_stats.code_reallocs++;
2596                 }
2597
2598                 if (cfg->debug_info)
2599                         mono_debug_record_line_number (cfg, ins, offset);
2600
2601                 switch (ins->opcode) {
2602                 case OP_BIGMUL:
2603                         amd64_mul_reg (code, ins->sreg2, TRUE);
2604                         break;
2605                 case OP_BIGMUL_UN:
2606                         amd64_mul_reg (code, ins->sreg2, FALSE);
2607                         break;
2608                 case OP_X86_SETEQ_MEMBASE:
2609                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2610                         break;
2611                 case OP_STOREI1_MEMBASE_IMM:
2612                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2613                         break;
2614                 case OP_STOREI2_MEMBASE_IMM:
2615                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2616                         break;
2617                 case OP_STOREI4_MEMBASE_IMM:
2618                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2619                         break;
2620                 case OP_STOREI1_MEMBASE_REG:
2621                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2622                         break;
2623                 case OP_STOREI2_MEMBASE_REG:
2624                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2625                         break;
2626                 case OP_STORE_MEMBASE_REG:
2627                 case OP_STOREI8_MEMBASE_REG:
2628                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2629                         break;
2630                 case OP_STOREI4_MEMBASE_REG:
2631                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2632                         break;
2633                 case OP_STORE_MEMBASE_IMM:
2634                 case OP_STOREI8_MEMBASE_IMM:
2635                         g_assert (amd64_is_imm32 (ins->inst_imm));
2636                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2637                         break;
2638                 case OP_LOAD_MEM:
2639                 case OP_LOADI8_MEM:
2640                         // FIXME: Decompose this earlier
2641                         if (amd64_is_imm32 (ins->inst_imm))
2642                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2643                         else {
2644                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2645                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2646                         }
2647                         break;
2648                 case OP_LOADI4_MEM:
2649                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2650                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2651                         break;
2652                 case OP_LOADU4_MEM:
2653                         // FIXME: Decompose this earlier
2654                         if (amd64_is_imm32 (ins->inst_imm))
2655                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2656                         else {
2657                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2658                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2659                         }
2660                         break;
2661                 case OP_LOADU1_MEM:
2662                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2663                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2664                         break;
2665                 case OP_LOADU2_MEM:
2666                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2667                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2668                         break;
2669                 case OP_LOAD_MEMBASE:
2670                 case OP_LOADI8_MEMBASE:
2671                         g_assert (amd64_is_imm32 (ins->inst_offset));
2672                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2673                         break;
2674                 case OP_LOADI4_MEMBASE:
2675                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2676                         break;
2677                 case OP_LOADU4_MEMBASE:
2678                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2679                         break;
2680                 case OP_LOADU1_MEMBASE:
2681                         /* The cpu zero extends the result into 64 bits */
2682                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2683                         break;
2684                 case OP_LOADI1_MEMBASE:
2685                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2686                         break;
2687                 case OP_LOADU2_MEMBASE:
2688                         /* The cpu zero extends the result into 64 bits */
2689                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2690                         break;
2691                 case OP_LOADI2_MEMBASE:
2692                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2693                         break;
2694                 case OP_AMD64_LOADI8_MEMINDEX:
2695                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2696                         break;
2697                 case OP_LCONV_TO_I1:
2698                 case OP_ICONV_TO_I1:
2699                 case OP_SEXT_I1:
2700                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2701                         break;
2702                 case OP_LCONV_TO_I2:
2703                 case OP_ICONV_TO_I2:
2704                 case OP_SEXT_I2:
2705                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2706                         break;
2707                 case OP_LCONV_TO_U1:
2708                 case OP_ICONV_TO_U1:
2709                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2710                         break;
2711                 case OP_LCONV_TO_U2:
2712                 case OP_ICONV_TO_U2:
2713                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2714                         break;
2715                 case OP_ZEXT_I4:
2716                         /* Clean out the upper word */
2717                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2718                         break;
2719                 case OP_SEXT_I4:
2720                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2721                         break;
2722                 case OP_COMPARE:
2723                 case OP_LCOMPARE:
2724                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2725                         break;
2726                 case OP_COMPARE_IMM:
2727                 case OP_LCOMPARE_IMM:
2728                         g_assert (amd64_is_imm32 (ins->inst_imm));
2729                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2730                         break;
2731                 case OP_X86_COMPARE_REG_MEMBASE:
2732                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2733                         break;
2734                 case OP_X86_TEST_NULL:
2735                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2736                         break;
2737                 case OP_AMD64_TEST_NULL:
2738                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2739                         break;
2740
2741                 case OP_X86_ADD_REG_MEMBASE:
2742                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2743                         break;
2744                 case OP_X86_SUB_REG_MEMBASE:
2745                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2746                         break;
2747                 case OP_X86_AND_REG_MEMBASE:
2748                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2749                         break;
2750                 case OP_X86_OR_REG_MEMBASE:
2751                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2752                         break;
2753                 case OP_X86_XOR_REG_MEMBASE:
2754                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2755                         break;
2756
2757                 case OP_X86_ADD_MEMBASE_IMM:
2758                         /* FIXME: Make a 64 version too */
2759                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2760                         break;
2761                 case OP_X86_SUB_MEMBASE_IMM:
2762                         g_assert (amd64_is_imm32 (ins->inst_imm));
2763                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2764                         break;
2765                 case OP_X86_AND_MEMBASE_IMM:
2766                         g_assert (amd64_is_imm32 (ins->inst_imm));
2767                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2768                         break;
2769                 case OP_X86_OR_MEMBASE_IMM:
2770                         g_assert (amd64_is_imm32 (ins->inst_imm));
2771                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2772                         break;
2773                 case OP_X86_XOR_MEMBASE_IMM:
2774                         g_assert (amd64_is_imm32 (ins->inst_imm));
2775                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2776                         break;
2777                 case OP_X86_ADD_MEMBASE_REG:
2778                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2779                         break;
2780                 case OP_X86_SUB_MEMBASE_REG:
2781                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2782                         break;
2783                 case OP_X86_AND_MEMBASE_REG:
2784                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2785                         break;
2786                 case OP_X86_OR_MEMBASE_REG:
2787                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2788                         break;
2789                 case OP_X86_XOR_MEMBASE_REG:
2790                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2791                         break;
2792                 case OP_X86_INC_MEMBASE:
2793                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2794                         break;
2795                 case OP_X86_INC_REG:
2796                         amd64_inc_reg_size (code, ins->dreg, 4);
2797                         break;
2798                 case OP_X86_DEC_MEMBASE:
2799                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2800                         break;
2801                 case OP_X86_DEC_REG:
2802                         amd64_dec_reg_size (code, ins->dreg, 4);
2803                         break;
2804                 case OP_X86_MUL_REG_MEMBASE:
2805                 case OP_X86_MUL_MEMBASE_REG:
2806                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2807                         break;
2808                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2809                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2810                         break;
2811                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2812                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2813                         break;
2814                 case OP_AMD64_COMPARE_MEMBASE_REG:
2815                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2816                         break;
2817                 case OP_AMD64_COMPARE_MEMBASE_IMM:
2818                         g_assert (amd64_is_imm32 (ins->inst_imm));
2819                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2820                         break;
2821                 case OP_X86_COMPARE_MEMBASE8_IMM:
2822                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2823                         break;
2824                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2825                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2826                         break;
2827                 case OP_AMD64_COMPARE_REG_MEMBASE:
2828                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2829                         break;
2830
2831                 case OP_AMD64_ADD_REG_MEMBASE:
2832                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2833                         break;
2834                 case OP_AMD64_SUB_REG_MEMBASE:
2835                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2836                         break;
2837                 case OP_AMD64_AND_REG_MEMBASE:
2838                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2839                         break;
2840                 case OP_AMD64_OR_REG_MEMBASE:
2841                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2842                         break;
2843                 case OP_AMD64_XOR_REG_MEMBASE:
2844                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2845                         break;
2846
2847                 case OP_AMD64_ADD_MEMBASE_REG:
2848                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2849                         break;
2850                 case OP_AMD64_SUB_MEMBASE_REG:
2851                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2852                         break;
2853                 case OP_AMD64_AND_MEMBASE_REG:
2854                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2855                         break;
2856                 case OP_AMD64_OR_MEMBASE_REG:
2857                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2858                         break;
2859                 case OP_AMD64_XOR_MEMBASE_REG:
2860                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2861                         break;
2862
2863                 case OP_AMD64_ADD_MEMBASE_IMM:
2864                         g_assert (amd64_is_imm32 (ins->inst_imm));
2865                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2866                         break;
2867                 case OP_AMD64_SUB_MEMBASE_IMM:
2868                         g_assert (amd64_is_imm32 (ins->inst_imm));
2869                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2870                         break;
2871                 case OP_AMD64_AND_MEMBASE_IMM:
2872                         g_assert (amd64_is_imm32 (ins->inst_imm));
2873                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2874                         break;
2875                 case OP_AMD64_OR_MEMBASE_IMM:
2876                         g_assert (amd64_is_imm32 (ins->inst_imm));
2877                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2878                         break;
2879                 case OP_AMD64_XOR_MEMBASE_IMM:
2880                         g_assert (amd64_is_imm32 (ins->inst_imm));
2881                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2882                         break;
2883
2884                 case OP_BREAK:
2885                         amd64_breakpoint (code);
2886                         break;
2887                 case OP_RELAXED_NOP:
2888                         x86_prefix (code, X86_REP_PREFIX);
2889                         x86_nop (code);
2890                         break;
2891                 case OP_HARD_NOP:
2892                         x86_nop (code);
2893                         break;
2894                 case OP_NOP:
2895                 case OP_DUMMY_USE:
2896                 case OP_DUMMY_STORE:
2897                 case OP_NOT_REACHED:
2898                 case OP_NOT_NULL:
2899                         break;
2900                 case OP_ADDCC:
2901                 case OP_LADD:
2902                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2903                         break;
2904                 case OP_ADC:
2905                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2906                         break;
2907                 case OP_ADD_IMM:
2908                 case OP_LADD_IMM:
2909                         g_assert (amd64_is_imm32 (ins->inst_imm));
2910                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2911                         break;
2912                 case OP_ADC_IMM:
2913                         g_assert (amd64_is_imm32 (ins->inst_imm));
2914                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2915                         break;
2916                 case OP_SUBCC:
2917                 case OP_LSUB:
2918                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2919                         break;
2920                 case OP_SBB:
2921                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2922                         break;
2923                 case OP_SUB_IMM:
2924                 case OP_LSUB_IMM:
2925                         g_assert (amd64_is_imm32 (ins->inst_imm));
2926                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2927                         break;
2928                 case OP_SBB_IMM:
2929                         g_assert (amd64_is_imm32 (ins->inst_imm));
2930                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2931                         break;
2932                 case OP_LAND:
2933                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2934                         break;
2935                 case OP_AND_IMM:
2936                 case OP_LAND_IMM:
2937                         g_assert (amd64_is_imm32 (ins->inst_imm));
2938                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2939                         break;
2940                 case OP_LMUL:
2941                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2942                         break;
2943                 case OP_MUL_IMM:
2944                 case OP_LMUL_IMM:
2945                 case OP_IMUL_IMM: {
2946                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2947
2948                         switch (ins->inst_imm) {
2949                         case 2:
2950                                 /* MOV r1, r2 */
2951                                 /* ADD r1, r1 */
2952                                 if (ins->dreg != ins->sreg1)
2953                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2954                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2955                                 break;
2956                         case 3:
2957                                 /* LEA r1, [r2 + r2*2] */
2958                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2959                                 break;
2960                         case 5:
2961                                 /* LEA r1, [r2 + r2*4] */
2962                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2963                                 break;
2964                         case 6:
2965                                 /* LEA r1, [r2 + r2*2] */
2966                                 /* ADD r1, r1          */
2967                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2968                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2969                                 break;
2970                         case 9:
2971                                 /* LEA r1, [r2 + r2*8] */
2972                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2973                                 break;
2974                         case 10:
2975                                 /* LEA r1, [r2 + r2*4] */
2976                                 /* ADD r1, r1          */
2977                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2978                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2979                                 break;
2980                         case 12:
2981                                 /* LEA r1, [r2 + r2*2] */
2982                                 /* SHL r1, 2           */
2983                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2984                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2985                                 break;
2986                         case 25:
2987                                 /* LEA r1, [r2 + r2*4] */
2988                                 /* LEA r1, [r1 + r1*4] */
2989                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2990                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2991                                 break;
2992                         case 100:
2993                                 /* LEA r1, [r2 + r2*4] */
2994                                 /* SHL r1, 2           */
2995                                 /* LEA r1, [r1 + r1*4] */
2996                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2997                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2998                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2999                                 break;
3000                         default:
3001                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3002                                 break;
3003                         }
3004                         break;
3005                 }
3006                 case OP_LDIV:
3007                 case OP_LREM:
3008                         /* Regalloc magic makes the div/rem cases the same */
3009                         if (ins->sreg2 == AMD64_RDX) {
3010                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3011                                 amd64_cdq (code);
3012                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3013                         } else {
3014                                 amd64_cdq (code);
3015                                 amd64_div_reg (code, ins->sreg2, TRUE);
3016                         }
3017                         break;
3018                 case OP_LDIV_UN:
3019                 case OP_LREM_UN:
3020                         if (ins->sreg2 == AMD64_RDX) {
3021                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3022                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3023                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3024                         } else {
3025                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3026                                 amd64_div_reg (code, ins->sreg2, FALSE);
3027                         }
3028                         break;
3029                 case OP_IDIV:
3030                 case OP_IREM:
3031                         if (ins->sreg2 == AMD64_RDX) {
3032                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3033                                 amd64_cdq_size (code, 4);
3034                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3035                         } else {
3036                                 amd64_cdq_size (code, 4);
3037                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3038                         }
3039                         break;
3040                 case OP_IDIV_UN:
3041                 case OP_IREM_UN:
3042                         if (ins->sreg2 == AMD64_RDX) {
3043                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3044                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3045                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3046                         } else {
3047                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3048                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3049                         }
3050                         break;
3051                 case OP_IREM_IMM: {
3052                         int power = mono_is_power_of_two (ins->inst_imm);
3053
3054                         g_assert (ins->sreg1 == X86_EAX);
3055                         g_assert (ins->dreg == X86_EAX);
3056                         g_assert (power >= 0);
3057
3058                         /* Based on gcc code */
3059
3060                         /* Add compensation for negative dividents */
3061                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3062                         if (power > 1)
3063                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3064                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3065                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3066                         /* Compute remainder */
3067                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3068                         /* Remove compensation */
3069                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3070                         break;
3071                 }
3072                 case OP_LMUL_OVF:
3073                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3074                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3075                         break;
3076                 case OP_LOR:
3077                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3078                         break;
3079                 case OP_OR_IMM:
3080                 case OP_LOR_IMM:
3081                         g_assert (amd64_is_imm32 (ins->inst_imm));
3082                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3083                         break;
3084                 case OP_LXOR:
3085                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3086                         break;
3087                 case OP_XOR_IMM:
3088                 case OP_LXOR_IMM:
3089                         g_assert (amd64_is_imm32 (ins->inst_imm));
3090                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3091                         break;
3092                 case OP_LSHL:
3093                         g_assert (ins->sreg2 == AMD64_RCX);
3094                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3095                         break;
3096                 case OP_LSHR:
3097                         g_assert (ins->sreg2 == AMD64_RCX);
3098                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3099                         break;
3100                 case OP_SHR_IMM:
3101                         g_assert (amd64_is_imm32 (ins->inst_imm));
3102                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3103                         break;
3104                 case OP_LSHR_IMM:
3105                         g_assert (amd64_is_imm32 (ins->inst_imm));
3106                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3107                         break;
3108                 case OP_SHR_UN_IMM:
3109                         g_assert (amd64_is_imm32 (ins->inst_imm));
3110                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3111                         break;
3112                 case OP_LSHR_UN_IMM:
3113                         g_assert (amd64_is_imm32 (ins->inst_imm));
3114                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3115                         break;
3116                 case OP_LSHR_UN:
3117                         g_assert (ins->sreg2 == AMD64_RCX);
3118                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3119                         break;
3120                 case OP_SHL_IMM:
3121                         g_assert (amd64_is_imm32 (ins->inst_imm));
3122                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3123                         break;
3124                 case OP_LSHL_IMM:
3125                         g_assert (amd64_is_imm32 (ins->inst_imm));
3126                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3127                         break;
3128
3129                 case OP_IADDCC:
3130                 case OP_IADD:
3131                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3132                         break;
3133                 case OP_IADC:
3134                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3135                         break;
3136                 case OP_IADD_IMM:
3137                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3138                         break;
3139                 case OP_IADC_IMM:
3140                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3141                         break;
3142                 case OP_ISUBCC:
3143                 case OP_ISUB:
3144                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3145                         break;
3146                 case OP_ISBB:
3147                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3148                         break;
3149                 case OP_ISUB_IMM:
3150                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3151                         break;
3152                 case OP_ISBB_IMM:
3153                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3154                         break;
3155                 case OP_IAND:
3156                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3157                         break;
3158                 case OP_IAND_IMM:
3159                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3160                         break;
3161                 case OP_IOR:
3162                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3163                         break;
3164                 case OP_IOR_IMM:
3165                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3166                         break;
3167                 case OP_IXOR:
3168                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3169                         break;
3170                 case OP_IXOR_IMM:
3171                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3172                         break;
3173                 case OP_INEG:
3174                         amd64_neg_reg_size (code, ins->sreg1, 4);
3175                         break;
3176                 case OP_INOT:
3177                         amd64_not_reg_size (code, ins->sreg1, 4);
3178                         break;
3179                 case OP_ISHL:
3180                         g_assert (ins->sreg2 == AMD64_RCX);
3181                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3182                         break;
3183                 case OP_ISHR:
3184                         g_assert (ins->sreg2 == AMD64_RCX);
3185                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3186                         break;
3187                 case OP_ISHR_IMM:
3188                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3189                         break;
3190                 case OP_ISHR_UN_IMM:
3191                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3192                         break;
3193                 case OP_ISHR_UN:
3194                         g_assert (ins->sreg2 == AMD64_RCX);
3195                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3196                         break;
3197                 case OP_ISHL_IMM:
3198                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3199                         break;
3200                 case OP_IMUL:
3201                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3202                         break;
3203                 case OP_IMUL_OVF:
3204                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3205                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3206                         break;
3207                 case OP_IMUL_OVF_UN:
3208                 case OP_LMUL_OVF_UN: {
3209                         /* the mul operation and the exception check should most likely be split */
3210                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3211                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3212                         /*g_assert (ins->sreg2 == X86_EAX);
3213                         g_assert (ins->dreg == X86_EAX);*/
3214                         if (ins->sreg2 == X86_EAX) {
3215                                 non_eax_reg = ins->sreg1;
3216                         } else if (ins->sreg1 == X86_EAX) {
3217                                 non_eax_reg = ins->sreg2;
3218                         } else {
3219                                 /* no need to save since we're going to store to it anyway */
3220                                 if (ins->dreg != X86_EAX) {
3221                                         saved_eax = TRUE;
3222                                         amd64_push_reg (code, X86_EAX);
3223                                 }
3224                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3225                                 non_eax_reg = ins->sreg2;
3226                         }
3227                         if (ins->dreg == X86_EDX) {
3228                                 if (!saved_eax) {
3229                                         saved_eax = TRUE;
3230                                         amd64_push_reg (code, X86_EAX);
3231                                 }
3232                         } else {
3233                                 saved_edx = TRUE;
3234                                 amd64_push_reg (code, X86_EDX);
3235                         }
3236                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3237                         /* save before the check since pop and mov don't change the flags */
3238                         if (ins->dreg != X86_EAX)
3239                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3240                         if (saved_edx)
3241                                 amd64_pop_reg (code, X86_EDX);
3242                         if (saved_eax)
3243                                 amd64_pop_reg (code, X86_EAX);
3244                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3245                         break;
3246                 }
3247                 case OP_ICOMPARE:
3248                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3249                         break;
3250                 case OP_ICOMPARE_IMM:
3251                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3252                         break;
3253                 case OP_IBEQ:
3254                 case OP_IBLT:
3255                 case OP_IBGT:
3256                 case OP_IBGE:
3257                 case OP_IBLE:
3258                 case OP_LBEQ:
3259                 case OP_LBLT:
3260                 case OP_LBGT:
3261                 case OP_LBGE:
3262                 case OP_LBLE:
3263                 case OP_IBNE_UN:
3264                 case OP_IBLT_UN:
3265                 case OP_IBGT_UN:
3266                 case OP_IBGE_UN:
3267                 case OP_IBLE_UN:
3268                 case OP_LBNE_UN:
3269                 case OP_LBLT_UN:
3270                 case OP_LBGT_UN:
3271                 case OP_LBGE_UN:
3272                 case OP_LBLE_UN:
3273                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3274                         break;
3275
3276                 case OP_CMOV_IEQ:
3277                 case OP_CMOV_IGE:
3278                 case OP_CMOV_IGT:
3279                 case OP_CMOV_ILE:
3280                 case OP_CMOV_ILT:
3281                 case OP_CMOV_INE_UN:
3282                 case OP_CMOV_IGE_UN:
3283                 case OP_CMOV_IGT_UN:
3284                 case OP_CMOV_ILE_UN:
3285                 case OP_CMOV_ILT_UN:
3286                 case OP_CMOV_LEQ:
3287                 case OP_CMOV_LGE:
3288                 case OP_CMOV_LGT:
3289                 case OP_CMOV_LLE:
3290                 case OP_CMOV_LLT:
3291                 case OP_CMOV_LNE_UN:
3292                 case OP_CMOV_LGE_UN:
3293                 case OP_CMOV_LGT_UN:
3294                 case OP_CMOV_LLE_UN:
3295                 case OP_CMOV_LLT_UN:
3296                         g_assert (ins->dreg == ins->sreg1);
3297                         /* This needs to operate on 64 bit values */
3298                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3299                         break;
3300
3301                 case OP_LNOT:
3302                         amd64_not_reg (code, ins->sreg1);
3303                         break;
3304                 case OP_LNEG:
3305                         amd64_neg_reg (code, ins->sreg1);
3306                         break;
3307
3308                 case OP_ICONST:
3309                 case OP_I8CONST:
3310                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3311                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3312                         else
3313                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3314                         break;
3315                 case OP_AOTCONST:
3316                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3317                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3318                         break;
3319                 case OP_JUMP_TABLE:
3320                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3321                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3322                         break;
3323                 case OP_MOVE:
3324                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3325                         break;
3326                 case OP_AMD64_SET_XMMREG_R4: {
3327                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3328                         break;
3329                 }
3330                 case OP_AMD64_SET_XMMREG_R8: {
3331                         if (ins->dreg != ins->sreg1)
3332                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3333                         break;
3334                 }
3335                 case OP_TAILCALL: {
3336                         /*
3337                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3338                          * Keep in sync with the code in emit_epilog.
3339                          */
3340                         int pos = 0, i;
3341
3342                         /* FIXME: no tracing support... */
3343                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3344                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3345
3346                         g_assert (!cfg->method->save_lmf);
3347
3348                         if (cfg->arch.omit_fp) {
3349                                 guint32 save_offset = 0;
3350                                 /* Pop callee-saved registers */
3351                                 for (i = 0; i < AMD64_NREG; ++i)
3352                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3353                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3354                                                 save_offset += 8;
3355                                         }
3356                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3357                         }
3358                         else {
3359                                 for (i = 0; i < AMD64_NREG; ++i)
3360                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3361                                                 pos -= sizeof (gpointer);
3362
3363                                 if (pos)
3364                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3365
3366                                 /* Pop registers in reverse order */
3367                                 for (i = AMD64_NREG - 1; i > 0; --i)
3368                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3369                                                 amd64_pop_reg (code, i);
3370                                         }
3371
3372                                 amd64_leave (code);
3373                         }
3374
3375                         offset = code - cfg->native_code;
3376                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3377                         if (cfg->compile_aot)
3378                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3379                         else
3380                                 amd64_set_reg_template (code, AMD64_R11);
3381                         amd64_jump_reg (code, AMD64_R11);
3382                         break;
3383                 }
3384                 case OP_CHECK_THIS:
3385                         /* ensure ins->sreg1 is not NULL */
3386                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3387                         break;
3388                 case OP_ARGLIST: {
3389                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3390                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3391                         break;
3392                 }
3393                 case OP_CALL:
3394                 case OP_FCALL:
3395                 case OP_LCALL:
3396                 case OP_VCALL:
3397                 case OP_VCALL2:
3398                 case OP_VOIDCALL:
3399                         call = (MonoCallInst*)ins;
3400                         /*
3401                          * The AMD64 ABI forces callers to know about varargs.
3402                          */
3403                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3404                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3405                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3406                                 /*
3407                                  * Since the unmanaged calling convention doesn't contain a
3408                                  * 'vararg' entry, we have to treat every pinvoke call as a
3409                                  * potential vararg call.
3410                                  */
3411                                 guint32 nregs, i;
3412                                 nregs = 0;
3413                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3414                                         if (call->used_fregs & (1 << i))
3415                                                 nregs ++;
3416                                 if (!nregs)
3417                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3418                                 else
3419                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3420                         }
3421
3422                         if (ins->flags & MONO_INST_HAS_METHOD)
3423                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3424                         else
3425                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3426                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3427                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3428                         code = emit_move_return_value (cfg, ins, code);
3429                         break;
3430                 case OP_FCALL_REG:
3431                 case OP_LCALL_REG:
3432                 case OP_VCALL_REG:
3433                 case OP_VCALL2_REG:
3434                 case OP_VOIDCALL_REG:
3435                 case OP_CALL_REG:
3436                         call = (MonoCallInst*)ins;
3437
3438                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3439                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3440                                 ins->sreg1 = AMD64_R11;
3441                         }
3442
3443                         /*
3444                          * The AMD64 ABI forces callers to know about varargs.
3445                          */
3446                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3447                                 if (ins->sreg1 == AMD64_RAX) {
3448                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3449                                         ins->sreg1 = AMD64_R11;
3450                                 }
3451                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3452                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3453                                 /*
3454                                  * Since the unmanaged calling convention doesn't contain a
3455                                  * 'vararg' entry, we have to treat every pinvoke call as a
3456                                  * potential vararg call.
3457                                  */
3458                                 guint32 nregs, i;
3459                                 nregs = 0;
3460                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3461                                         if (call->used_fregs & (1 << i))
3462                                                 nregs ++;
3463                                 if (ins->sreg1 == AMD64_RAX) {
3464                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3465                                         ins->sreg1 = AMD64_R11;
3466                                 }
3467                                 if (!nregs)
3468                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3469                                 else
3470                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3471                         }
3472
3473                         amd64_call_reg (code, ins->sreg1);
3474                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3475                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3476                         code = emit_move_return_value (cfg, ins, code);
3477                         break;
3478                 case OP_FCALL_MEMBASE:
3479                 case OP_LCALL_MEMBASE:
3480                 case OP_VCALL_MEMBASE:
3481                 case OP_VCALL2_MEMBASE:
3482                 case OP_VOIDCALL_MEMBASE:
3483                 case OP_CALL_MEMBASE:
3484                         call = (MonoCallInst*)ins;
3485
3486                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3487                                 /*
3488                                  * Can't use R11 because it is clobbered by the trampoline
3489                                  * code, and the reg value is needed by get_vcall_slot_addr.
3490                                  */
3491                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3492                                 ins->sreg1 = AMD64_RAX;
3493                         }
3494
3495                         if (call->method && ins->inst_offset < 0) {
3496                                 gssize val;
3497
3498                                 /*
3499                                  * This is a possible IMT call so save the IMT method in the proper
3500                                  * register. We don't use the generic code in method-to-ir.c, because
3501                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3502                                  * maintain control over the layout of the code.
3503                                  * Also put the base reg in %rax to simplify find_imt_method ().
3504                                  */
3505                                 if (ins->sreg1 != AMD64_RAX) {
3506                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3507                                         ins->sreg1 = AMD64_RAX;
3508                                 }
3509                                 val = (gssize)(gpointer)call->method;
3510
3511                                 // FIXME: Generics sharing
3512 #if 0
3513                                 if ((((guint64)val) >> 32) == 0)
3514                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3515                                 else
3516                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3517 #endif
3518                         }
3519
3520                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3521                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3522                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3523                         code = emit_move_return_value (cfg, ins, code);
3524                         break;
3525                 case OP_AMD64_SAVE_SP_TO_LMF:
3526                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3527                         break;
3528                 case OP_X86_PUSH:
3529                         amd64_push_reg (code, ins->sreg1);
3530                         break;
3531                 case OP_X86_PUSH_IMM:
3532                         g_assert (amd64_is_imm32 (ins->inst_imm));
3533                         amd64_push_imm (code, ins->inst_imm);
3534                         break;
3535                 case OP_X86_PUSH_MEMBASE:
3536                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3537                         break;
3538                 case OP_X86_PUSH_OBJ: {
3539                         int size = ALIGN_TO (ins->inst_imm, 8);
3540                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3541                         amd64_push_reg (code, AMD64_RDI);
3542                         amd64_push_reg (code, AMD64_RSI);
3543                         amd64_push_reg (code, AMD64_RCX);
3544                         if (ins->inst_offset)
3545                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3546                         else
3547                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3548                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3549                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3550                         amd64_cld (code);
3551                         amd64_prefix (code, X86_REP_PREFIX);
3552                         amd64_movsd (code);
3553                         amd64_pop_reg (code, AMD64_RCX);
3554                         amd64_pop_reg (code, AMD64_RSI);
3555                         amd64_pop_reg (code, AMD64_RDI);
3556                         break;
3557                 }
3558                 case OP_X86_LEA:
3559                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3560                         break;
3561                 case OP_X86_LEA_MEMBASE:
3562                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3563                         break;
3564                 case OP_X86_XCHG:
3565                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3566                         break;
3567                 case OP_LOCALLOC:
3568                         /* keep alignment */
3569                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3570                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3571                         code = mono_emit_stack_alloc (code, ins);
3572                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3573                         break;
3574                 case OP_LOCALLOC_IMM: {
3575                         guint32 size = ins->inst_imm;
3576                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3577
3578                         if (ins->flags & MONO_INST_INIT) {
3579                                 if (size < 64) {
3580                                         int i;
3581
3582                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3583                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3584
3585                                         for (i = 0; i < size; i += 8)
3586                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3587                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3588                                 } else {
3589                                         amd64_mov_reg_imm (code, ins->dreg, size);
3590                                         ins->sreg1 = ins->dreg;
3591
3592                                         code = mono_emit_stack_alloc (code, ins);
3593                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3594                                 }
3595                         } else {
3596                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3597                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3598                         }
3599                         break;
3600                 }
3601                 case OP_THROW: {
3602                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3603                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3604                                              (gpointer)"mono_arch_throw_exception", FALSE);
3605                         break;
3606                 }
3607                 case OP_RETHROW: {
3608                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3609                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3610                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
3611                         break;
3612                 }
3613                 case OP_CALL_HANDLER:
3614                         /* Align stack */
3615                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3616                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3617                         amd64_call_imm (code, 0);
3618                         /* Restore stack alignment */
3619                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3620                         break;
3621                 case OP_START_HANDLER: {
3622                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3623                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3624                         break;
3625                 }
3626                 case OP_ENDFINALLY: {
3627                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3628                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3629                         amd64_ret (code);
3630                         break;
3631                 }
3632                 case OP_ENDFILTER: {
3633                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3634                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3635                         /* The local allocator will put the result into RAX */
3636                         amd64_ret (code);
3637                         break;
3638                 }
3639
3640                 case OP_LABEL:
3641                         ins->inst_c0 = code - cfg->native_code;
3642                         break;
3643                 case OP_BR:
3644                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3645                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3646                         //break;
3647                         if (ins->flags & MONO_INST_BRLABEL) {
3648                                 if (ins->inst_i0->inst_c0) {
3649                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3650                                 } else {
3651                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3652                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3653                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3654                                                 x86_jump8 (code, 0);
3655                                         else
3656                                                 x86_jump32 (code, 0);
3657                                 }
3658                         } else {
3659                                 if (ins->inst_target_bb->native_offset) {
3660                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3661                                 } else {
3662                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3663                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3664                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3665                                                 x86_jump8 (code, 0);
3666                                         else
3667                                                 x86_jump32 (code, 0);
3668                                 }
3669                         }
3670                         break;
3671                 case OP_BR_REG:
3672                         amd64_jump_reg (code, ins->sreg1);
3673                         break;
3674                 case OP_CEQ:
3675                 case OP_LCEQ:
3676                 case OP_ICEQ:
3677                 case OP_CLT:
3678                 case OP_LCLT:
3679                 case OP_ICLT:
3680                 case OP_CGT:
3681                 case OP_ICGT:
3682                 case OP_LCGT:
3683                 case OP_CLT_UN:
3684                 case OP_LCLT_UN:
3685                 case OP_ICLT_UN:
3686                 case OP_CGT_UN:
3687                 case OP_LCGT_UN:
3688                 case OP_ICGT_UN:
3689                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3690                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3691                         break;
3692                 case OP_COND_EXC_EQ:
3693                 case OP_COND_EXC_NE_UN:
3694                 case OP_COND_EXC_LT:
3695                 case OP_COND_EXC_LT_UN:
3696                 case OP_COND_EXC_GT:
3697                 case OP_COND_EXC_GT_UN:
3698                 case OP_COND_EXC_GE:
3699                 case OP_COND_EXC_GE_UN:
3700                 case OP_COND_EXC_LE:
3701                 case OP_COND_EXC_LE_UN:
3702                 case OP_COND_EXC_IEQ:
3703                 case OP_COND_EXC_INE_UN:
3704                 case OP_COND_EXC_ILT:
3705                 case OP_COND_EXC_ILT_UN:
3706                 case OP_COND_EXC_IGT:
3707                 case OP_COND_EXC_IGT_UN:
3708                 case OP_COND_EXC_IGE:
3709                 case OP_COND_EXC_IGE_UN:
3710                 case OP_COND_EXC_ILE:
3711                 case OP_COND_EXC_ILE_UN:
3712                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3713                         break;
3714                 case OP_COND_EXC_OV:
3715                 case OP_COND_EXC_NO:
3716                 case OP_COND_EXC_C:
3717                 case OP_COND_EXC_NC:
3718                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3719                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3720                         break;
3721                 case OP_COND_EXC_IOV:
3722                 case OP_COND_EXC_INO:
3723                 case OP_COND_EXC_IC:
3724                 case OP_COND_EXC_INC:
3725                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3726                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3727                         break;
3728
3729                 /* floating point opcodes */
3730                 case OP_R8CONST: {
3731                         double d = *(double *)ins->inst_p0;
3732
3733                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
3734                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3735                         }
3736                         else {
3737                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3738                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3739                         }
3740                         break;
3741                 }
3742                 case OP_R4CONST: {
3743                         float f = *(float *)ins->inst_p0;
3744
3745                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
3746                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3747                         }
3748                         else {
3749                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3750                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3751                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3752                         }
3753                         break;
3754                 }
3755                 case OP_STORER8_MEMBASE_REG:
3756                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3757                         break;
3758                 case OP_LOADR8_SPILL_MEMBASE:
3759                         g_assert_not_reached ();
3760                         break;
3761                 case OP_LOADR8_MEMBASE:
3762                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3763                         break;
3764                 case OP_STORER4_MEMBASE_REG:
3765                         /* This requires a double->single conversion */
3766                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3767                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3768                         break;
3769                 case OP_LOADR4_MEMBASE:
3770                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3771                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3772                         break;
3773                 case OP_ICONV_TO_R4: /* FIXME: change precision */
3774                 case OP_ICONV_TO_R8:
3775                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3776                         break;
3777                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3778                 case OP_LCONV_TO_R8:
3779                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3780                         break;
3781                 case OP_FCONV_TO_R4:
3782                         /* FIXME: nothing to do ?? */
3783                         break;
3784                 case OP_FCONV_TO_I1:
3785                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3786                         break;
3787                 case OP_FCONV_TO_U1:
3788                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3789                         break;
3790                 case OP_FCONV_TO_I2:
3791                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3792                         break;
3793                 case OP_FCONV_TO_U2:
3794                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3795                         break;
3796                 case OP_FCONV_TO_U4:
3797                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3798                         break;
3799                 case OP_FCONV_TO_I4:
3800                 case OP_FCONV_TO_I:
3801                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3802                         break;
3803                 case OP_FCONV_TO_I8:
3804                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3805                         break;
3806                 case OP_LCONV_TO_R_UN: {
3807                         guint8 *br [2];
3808
3809                         /* Based on gcc code */
3810                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3811                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3812
3813                         /* Positive case */
3814                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3815                         br [1] = code; x86_jump8 (code, 0);
3816                         amd64_patch (br [0], code);
3817
3818                         /* Negative case */
3819                         /* Save to the red zone */
3820                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3821                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3822                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3823                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3824                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3825                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3826                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3827                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3828                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3829                         /* Restore */
3830                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3831                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3832                         amd64_patch (br [1], code);
3833                         break;
3834                 }
3835                 case OP_LCONV_TO_OVF_U4:
3836                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3837                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3838                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3839                         break;
3840                 case OP_LCONV_TO_OVF_I4_UN:
3841                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3842                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3843                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3844                         break;
3845                 case OP_FMOVE:
3846                         if (ins->dreg != ins->sreg1)
3847                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3848                         break;
3849                 case OP_FADD:
3850                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3851                         break;
3852                 case OP_FSUB:
3853                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3854                         break;
3855                 case OP_FMUL:
3856                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3857                         break;
3858                 case OP_FDIV:
3859                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3860                         break;
3861                 case OP_FNEG: {
3862                         static double r8_0 = -0.0;
3863
3864                         g_assert (ins->sreg1 == ins->dreg);
3865
3866                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3867                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3868                         break;
3869                 }
3870                 case OP_SIN:
3871                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3872                         break;
3873                 case OP_COS:
3874                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3875                         break;
3876                 case OP_ABS: {
3877                         static guint64 d = 0x7fffffffffffffffUL;
3878
3879                         g_assert (ins->sreg1 == ins->dreg);
3880
3881                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
3882                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3883                         break;
3884                 }
3885                 case OP_SQRT:
3886                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3887                         break;
3888                 case OP_IMIN:
3889                         g_assert (cfg->opt & MONO_OPT_CMOV);
3890                         g_assert (ins->dreg == ins->sreg1);
3891                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3892                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3893                         break;
3894                 case OP_IMIN_UN:
3895                         g_assert (cfg->opt & MONO_OPT_CMOV);
3896                         g_assert (ins->dreg == ins->sreg1);
3897                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3898                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
3899                         break;
3900                 case OP_IMAX:
3901                         g_assert (cfg->opt & MONO_OPT_CMOV);
3902                         g_assert (ins->dreg == ins->sreg1);
3903                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3904                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3905                         break;
3906                 case OP_IMAX_UN:
3907                         g_assert (cfg->opt & MONO_OPT_CMOV);
3908                         g_assert (ins->dreg == ins->sreg1);
3909                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3910                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
3911                         break;
3912                 case OP_LMIN:
3913                         g_assert (cfg->opt & MONO_OPT_CMOV);
3914                         g_assert (ins->dreg == ins->sreg1);
3915                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3916                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3917                         break;
3918                 case OP_LMIN_UN:
3919                         g_assert (cfg->opt & MONO_OPT_CMOV);
3920                         g_assert (ins->dreg == ins->sreg1);
3921                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3922                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3923                         break;
3924                 case OP_LMAX:
3925                         g_assert (cfg->opt & MONO_OPT_CMOV);
3926                         g_assert (ins->dreg == ins->sreg1);
3927                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3928                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3929                         break;
3930                 case OP_LMAX_UN:
3931                         g_assert (cfg->opt & MONO_OPT_CMOV);
3932                         g_assert (ins->dreg == ins->sreg1);
3933                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3934                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3935                         break;
3936                 case OP_X86_FPOP:
3937                         break;
3938                 case OP_FCOMPARE:
3939                         /*
3940                          * The two arguments are swapped because the fbranch instructions
3941                          * depend on this for the non-sse case to work.
3942                          */
3943                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3944                         break;
3945                 case OP_FCEQ: {
3946                         /* zeroing the register at the start results in
3947                          * shorter and faster code (we can also remove the widening op)
3948                          */
3949                         guchar *unordered_check;
3950                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3951                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3952                         unordered_check = code;
3953                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3954                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3955                         amd64_patch (unordered_check, code);
3956                         break;
3957                 }
3958                 case OP_FCLT:
3959                 case OP_FCLT_UN:
3960                         /* zeroing the register at the start results in
3961                          * shorter and faster code (we can also remove the widening op)
3962                          */
3963                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3964                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3965                         if (ins->opcode == OP_FCLT_UN) {
3966                                 guchar *unordered_check = code;
3967                                 guchar *jump_to_end;
3968                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3969                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3970                                 jump_to_end = code;
3971                                 x86_jump8 (code, 0);
3972                                 amd64_patch (unordered_check, code);
3973                                 amd64_inc_reg (code, ins->dreg);
3974                                 amd64_patch (jump_to_end, code);
3975                         } else {
3976                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3977                         }
3978                         break;
3979                 case OP_FCGT:
3980                 case OP_FCGT_UN: {
3981                         /* zeroing the register at the start results in
3982                          * shorter and faster code (we can also remove the widening op)
3983                          */
3984                         guchar *unordered_check;
3985                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3986                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3987                         if (ins->opcode == OP_FCGT) {
3988                                 unordered_check = code;
3989                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3990                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3991                                 amd64_patch (unordered_check, code);
3992                         } else {
3993                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3994                         }
3995                         break;
3996                 }
3997                 case OP_FCLT_MEMBASE:
3998                 case OP_FCGT_MEMBASE:
3999                 case OP_FCLT_UN_MEMBASE:
4000                 case OP_FCGT_UN_MEMBASE:
4001                 case OP_FCEQ_MEMBASE: {
4002                         guchar *unordered_check, *jump_to_end;
4003                         int x86_cond;
4004
4005                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4006                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4007
4008                         switch (ins->opcode) {
4009                         case OP_FCEQ_MEMBASE:
4010                                 x86_cond = X86_CC_EQ;
4011                                 break;
4012                         case OP_FCLT_MEMBASE:
4013                         case OP_FCLT_UN_MEMBASE:
4014                                 x86_cond = X86_CC_LT;
4015                                 break;
4016                         case OP_FCGT_MEMBASE:
4017                         case OP_FCGT_UN_MEMBASE:
4018                                 x86_cond = X86_CC_GT;
4019                                 break;
4020                         default:
4021                                 g_assert_not_reached ();
4022                         }
4023
4024                         unordered_check = code;
4025                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4026                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4027
4028                         switch (ins->opcode) {
4029                         case OP_FCEQ_MEMBASE:
4030                         case OP_FCLT_MEMBASE:
4031                         case OP_FCGT_MEMBASE:
4032                                 amd64_patch (unordered_check, code);
4033                                 break;
4034                         case OP_FCLT_UN_MEMBASE:
4035                         case OP_FCGT_UN_MEMBASE:
4036                                 jump_to_end = code;
4037                                 x86_jump8 (code, 0);
4038                                 amd64_patch (unordered_check, code);
4039                                 amd64_inc_reg (code, ins->dreg);
4040                                 amd64_patch (jump_to_end, code);
4041                                 break;
4042                         default:
4043                                 break;
4044                         }
4045                         break;
4046                 }
4047                 case OP_FBEQ: {
4048                         guchar *jump = code;
4049                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4050                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4051                         amd64_patch (jump, code);
4052                         break;
4053                 }
4054                 case OP_FBNE_UN:
4055                         /* Branch if C013 != 100 */
4056                         /* branch if !ZF or (PF|CF) */
4057                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4058                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4059                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4060                         break;
4061                 case OP_FBLT:
4062                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4063                         break;
4064                 case OP_FBLT_UN:
4065                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4066                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4067                         break;
4068                 case OP_FBGT:
4069                 case OP_FBGT_UN:
4070                         if (ins->opcode == OP_FBGT) {
4071                                 guchar *br1;
4072
4073                                 /* skip branch if C1=1 */
4074                                 br1 = code;
4075                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4076                                 /* branch if (C0 | C3) = 1 */
4077                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4078                                 amd64_patch (br1, code);
4079                                 break;
4080                         } else {
4081                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4082                         }
4083                         break;
4084                 case OP_FBGE: {
4085                         /* Branch if C013 == 100 or 001 */
4086                         guchar *br1;
4087
4088                         /* skip branch if C1=1 */
4089                         br1 = code;
4090                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4091                         /* branch if (C0 | C3) = 1 */
4092                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4093                         amd64_patch (br1, code);
4094                         break;
4095                 }
4096                 case OP_FBGE_UN:
4097                         /* Branch if C013 == 000 */
4098                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4099                         break;
4100                 case OP_FBLE: {
4101                         /* Branch if C013=000 or 100 */
4102                         guchar *br1;
4103
4104                         /* skip branch if C1=1 */
4105                         br1 = code;
4106                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4107                         /* branch if C0=0 */
4108                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4109                         amd64_patch (br1, code);
4110                         break;
4111                 }
4112                 case OP_FBLE_UN:
4113                         /* Branch if C013 != 001 */
4114                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4115                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4116                         break;
4117                 case OP_CKFINITE:
4118                         /* Transfer value to the fp stack */
4119                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4120                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4121                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4122
4123                         amd64_push_reg (code, AMD64_RAX);
4124                         amd64_fxam (code);
4125                         amd64_fnstsw (code);
4126                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4127                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4128                         amd64_pop_reg (code, AMD64_RAX);
4129                         amd64_fstp (code, 0);
4130                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4131                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4132                         break;
4133                 case OP_TLS_GET: {
4134                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4135                         break;
4136                 }
4137                 case OP_MEMORY_BARRIER: {
4138                         /* Not needed on amd64 */
4139                         break;
4140                 }
4141                 case OP_ATOMIC_ADD_I4:
4142                 case OP_ATOMIC_ADD_I8: {
4143                         int dreg = ins->dreg;
4144                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4145
4146                         if (dreg == ins->inst_basereg)
4147                                 dreg = AMD64_R11;
4148
4149                         if (dreg != ins->sreg2)
4150                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4151
4152                         x86_prefix (code, X86_LOCK_PREFIX);
4153                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4154
4155                         if (dreg != ins->dreg)
4156                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4157
4158                         break;
4159                 }
4160                 case OP_ATOMIC_ADD_NEW_I4:
4161                 case OP_ATOMIC_ADD_NEW_I8: {
4162                         int dreg = ins->dreg;
4163                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4164
4165                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4166                                 dreg = AMD64_R11;
4167
4168                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4169                         amd64_prefix (code, X86_LOCK_PREFIX);
4170                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4171                         /* dreg contains the old value, add with sreg2 value */
4172                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4173
4174                         if (ins->dreg != dreg)
4175                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4176
4177                         break;
4178                 }
4179                 case OP_ATOMIC_EXCHANGE_I4:
4180                 case OP_ATOMIC_EXCHANGE_I8:
4181                 case OP_ATOMIC_CAS_IMM_I4: {
4182                         guchar *br[2];
4183                         int sreg2 = ins->sreg2;
4184                         int breg = ins->inst_basereg;
4185                         guint32 size;
4186                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4187
4188                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4189                                 size = 8;
4190                         else
4191                                 size = 4;
4192
4193                         /*
4194                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4195                          * an explanation of how this works.
4196                          */
4197
4198                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4199                          * hack to overcome limits in x86 reg allocator
4200                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4201                          */
4202                         g_assert (ins->dreg == AMD64_RAX);
4203
4204                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4205                                 /* Highly unlikely, but possible */
4206                                 need_push = TRUE;
4207
4208                         /* The pushes invalidate rsp */
4209                         if ((breg == AMD64_RAX) || need_push) {
4210                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4211                                 breg = AMD64_R11;
4212                         }
4213
4214                         /* We need the EAX reg for the comparand */
4215                         if (ins->sreg2 == AMD64_RAX) {
4216                                 if (breg != AMD64_R11) {
4217                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4218                                         sreg2 = AMD64_R11;
4219                                 } else {
4220                                         g_assert (need_push);
4221                                         amd64_push_reg (code, AMD64_RDX);
4222                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4223                                         sreg2 = AMD64_RDX;
4224                                         rdx_pushed = TRUE;
4225                                 }
4226                         }
4227
4228                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4229                                 if (ins->backend.data == NULL)
4230                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4231                                 else
4232                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4233
4234                                 amd64_prefix (code, X86_LOCK_PREFIX);
4235                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4236                         } else {
4237                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4238
4239                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4240                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4241                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4242                                 amd64_patch (br [1], br [0]);
4243                         }
4244
4245                         if (rdx_pushed)
4246                                 amd64_pop_reg (code, AMD64_RDX);
4247
4248                         break;
4249                 }
4250                 default:
4251                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4252                         g_assert_not_reached ();
4253                 }
4254
4255                 if ((code - cfg->native_code - offset) > max_len) {
4256                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4257                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4258                         g_assert_not_reached ();
4259                 }
4260
4261                 cpos += max_len;
4262
4263                 last_ins = ins;
4264                 last_offset = offset;
4265         }
4266
4267         cfg->code_len = code - cfg->native_code;
4268 }
4269
4270 #endif /* DISABLE_JIT */
4271
4272 void
4273 mono_arch_register_lowlevel_calls (void)
4274 {
4275         /* The signature doesn't matter */
4276         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4277 }
4278
4279 void
4280 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4281 {
4282         MonoJumpInfo *patch_info;
4283         gboolean compile_aot = !run_cctors;
4284
4285         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4286                 unsigned char *ip = patch_info->ip.i + code;
4287                 unsigned char *target;
4288
4289                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4290
4291                 if (compile_aot) {
4292                         switch (patch_info->type) {
4293                         case MONO_PATCH_INFO_BB:
4294                         case MONO_PATCH_INFO_LABEL:
4295                                 break;
4296                         default:
4297                                 /* No need to patch these */
4298                                 continue;
4299                         }
4300                 }
4301
4302                 switch (patch_info->type) {
4303                 case MONO_PATCH_INFO_NONE:
4304                         continue;
4305                 case MONO_PATCH_INFO_METHOD_REL:
4306                 case MONO_PATCH_INFO_R8:
4307                 case MONO_PATCH_INFO_R4:
4308                         g_assert_not_reached ();
4309                         continue;
4310                 case MONO_PATCH_INFO_BB:
4311                         break;
4312                 default:
4313                         break;
4314                 }
4315
4316                 /*
4317                  * Debug code to help track down problems where the target of a near call is
4318                  * is not valid.
4319                  */
4320                 if (amd64_is_near_call (ip)) {
4321                         gint64 disp = (guint8*)target - (guint8*)ip;
4322
4323                         if (!amd64_is_imm32 (disp)) {
4324                                 printf ("TYPE: %d\n", patch_info->type);
4325                                 switch (patch_info->type) {
4326                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4327                                         printf ("V: %s\n", patch_info->data.name);
4328                                         break;
4329                                 case MONO_PATCH_INFO_METHOD_JUMP:
4330                                 case MONO_PATCH_INFO_METHOD:
4331                                         printf ("V: %s\n", patch_info->data.method->name);
4332                                         break;
4333                                 default:
4334                                         break;
4335                                 }
4336                         }
4337                 }
4338
4339                 amd64_patch (ip, (gpointer)target);
4340         }
4341 }
4342
4343 static int
4344 get_max_epilog_size (MonoCompile *cfg)
4345 {
4346         int max_epilog_size = 16;
4347
4348         if (cfg->method->save_lmf)
4349                 max_epilog_size += 256;
4350
4351         if (mono_jit_trace_calls != NULL)
4352                 max_epilog_size += 50;
4353
4354         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4355                 max_epilog_size += 50;
4356
4357         max_epilog_size += (AMD64_NREG * 2);
4358
4359         return max_epilog_size;
4360 }
4361
4362 /*
4363  * This macro is used for testing whenever the unwinder works correctly at every point
4364  * where an async exception can happen.
4365  */
4366 /* This will generate a SIGSEGV at the given point in the code */
4367 #define async_exc_point(code) do { \
4368     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4369          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4370              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4371          cfg->arch.async_point_count ++; \
4372     } \
4373 } while (0)
4374
4375 guint8 *
4376 mono_arch_emit_prolog (MonoCompile *cfg)
4377 {
4378         MonoMethod *method = cfg->method;
4379         MonoBasicBlock *bb;
4380         MonoMethodSignature *sig;
4381         MonoInst *ins;
4382         int alloc_size, pos, max_offset, i, cfa_offset, quad, max_epilog_size;
4383         guint8 *code;
4384         CallInfo *cinfo;
4385         gint32 lmf_offset = cfg->arch.lmf_offset;
4386         gboolean args_clobbered = FALSE;
4387         gboolean trace = FALSE;
4388
4389         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4390
4391         code = cfg->native_code = g_malloc (cfg->code_size);
4392
4393         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4394                 trace = TRUE;
4395
4396         /* Amount of stack space allocated by register saving code */
4397         pos = 0;
4398
4399         /* Offset between RSP and the CFA */
4400         cfa_offset = 0;
4401
4402         /*
4403          * The prolog consists of the following parts:
4404          * FP present:
4405          * - push rbp, mov rbp, rsp
4406          * - save callee saved regs using pushes
4407          * - allocate frame
4408          * - save rgctx if needed
4409          * - save lmf if needed
4410          * FP not present:
4411          * - allocate frame
4412          * - save rgctx if needed
4413          * - save lmf if needed
4414          * - save callee saved regs using moves
4415          */
4416
4417         // CFA = sp + 8
4418         cfa_offset = 8;
4419         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4420         // IP saved at CFA - 8
4421         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4422         async_exc_point (code);
4423
4424         if (!cfg->arch.omit_fp) {
4425                 amd64_push_reg (code, AMD64_RBP);
4426                 cfa_offset += 8;
4427                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4428                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4429                 async_exc_point (code);
4430 #ifdef PLATFORM_WIN32
4431                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4432 #endif
4433
4434                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4435                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4436                 async_exc_point (code);
4437 #ifdef PLATFORM_WIN32
4438                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4439 #endif
4440         }
4441
4442         /* Save callee saved registers */
4443         if (!cfg->arch.omit_fp && !method->save_lmf) {
4444                 int offset = cfa_offset;
4445
4446                 for (i = 0; i < AMD64_NREG; ++i)
4447                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4448                                 amd64_push_reg (code, i);
4449                                 pos += sizeof (gpointer);
4450                                 offset += 8;
4451                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4452                                 async_exc_point (code);
4453                         }
4454         }
4455
4456         if (cfg->arch.omit_fp) {
4457                 /*
4458                  * On enter, the stack is misaligned by the the pushing of the return
4459                  * address. It is either made aligned by the pushing of %rbp, or by
4460                  * this.
4461                  */
4462                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4463                 if ((alloc_size % 16) == 0)
4464                         alloc_size += 8;
4465         } else {
4466                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4467
4468                 alloc_size -= pos;
4469         }
4470
4471         cfg->arch.stack_alloc_size = alloc_size;
4472
4473         /* Allocate stack frame */
4474         if (alloc_size) {
4475                 /* See mono_emit_stack_alloc */
4476 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4477                 guint32 remaining_size = alloc_size;
4478                 while (remaining_size >= 0x1000) {
4479                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4480                         if (cfg->arch.omit_fp) {
4481                                 cfa_offset += 0x1000;
4482                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4483                         }
4484                         async_exc_point (code);
4485 #ifdef PLATFORM_WIN32
4486                         if (cfg->arch.omit_fp)
4487                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4488 #endif
4489
4490                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4491                         remaining_size -= 0x1000;
4492                 }
4493                 if (remaining_size) {
4494                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4495                         if (cfg->arch.omit_fp) {
4496                                 cfa_offset += remaining_size;
4497                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4498                                 async_exc_point (code);
4499                         }
4500 #ifdef PLATFORM_WIN32
4501                         if (cfg->arch.omit_fp)
4502                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4503 #endif
4504                 }
4505 #else
4506                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4507                 if (cfg->arch.omit_fp) {
4508                         cfa_offset += alloc_size;
4509                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4510                         async_exc_point (code);
4511                 }
4512 #endif
4513         }
4514
4515         /* Stack alignment check */
4516 #if 0
4517         {
4518                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4519                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4520                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4521                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4522                 amd64_breakpoint (code);
4523         }
4524 #endif
4525
4526         /* Save LMF */
4527         if (method->save_lmf) {
4528                 /*
4529                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4530                  */
4531                 /* sp is saved right before calls */
4532                 /* Skip method (only needed for trampoline LMF frames) */
4533                 /* Save callee saved regs */
4534                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4535                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4536                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4537                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4538                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4539                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4540         }
4541
4542         /* Save callee saved registers */
4543         if (cfg->arch.omit_fp && !method->save_lmf) {
4544                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4545
4546                 /* Save caller saved registers after sp is adjusted */
4547                 /* The registers are saved at the bottom of the frame */
4548                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4549                 for (i = 0; i < AMD64_NREG; ++i)
4550                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4551                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4552                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
4553                                 save_area_offset += 8;
4554                                 async_exc_point (code);
4555                         }
4556         }
4557
4558         /* store runtime generic context */
4559         if (cfg->rgctx_var) {
4560                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4561                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4562
4563                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4564         }
4565
4566         /* compute max_offset in order to use short forward jumps */
4567         max_offset = 0;
4568         max_epilog_size = get_max_epilog_size (cfg);
4569         if (cfg->opt & MONO_OPT_BRANCH) {
4570                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4571                         MonoInst *ins;
4572                         bb->max_offset = max_offset;
4573
4574                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4575                                 max_offset += 6;
4576                         /* max alignment for loops */
4577                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4578                                 max_offset += LOOP_ALIGNMENT;
4579
4580                         MONO_BB_FOR_EACH_INS (bb, ins) {
4581                                 if (ins->opcode == OP_LABEL)
4582                                         ins->inst_c1 = max_offset;
4583
4584                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4585                         }
4586
4587                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4588                                 /* The tracing code can be quite large */
4589                                 max_offset += max_epilog_size;
4590                 }
4591         }
4592
4593         sig = mono_method_signature (method);
4594         pos = 0;
4595
4596         cinfo = cfg->arch.cinfo;
4597
4598         if (sig->ret->type != MONO_TYPE_VOID) {
4599                 /* Save volatile arguments to the stack */
4600                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4601                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4602         }
4603
4604         /* Keep this in sync with emit_load_volatile_arguments */
4605         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4606                 ArgInfo *ainfo = cinfo->args + i;
4607                 gint32 stack_offset;
4608                 MonoType *arg_type;
4609
4610                 ins = cfg->args [i];
4611
4612                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4613                         /* Unused arguments */
4614                         continue;
4615
4616                 if (sig->hasthis && (i == 0))
4617                         arg_type = &mono_defaults.object_class->byval_arg;
4618                 else
4619                         arg_type = sig->params [i - sig->hasthis];
4620
4621                 stack_offset = ainfo->offset + ARGS_OFFSET;
4622
4623                 if (cfg->globalra) {
4624                         /* All the other moves are done by the register allocator */
4625                         switch (ainfo->storage) {
4626                         case ArgInFloatSSEReg:
4627                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
4628                                 break;
4629                         case ArgValuetypeInReg:
4630                                 for (quad = 0; quad < 2; quad ++) {
4631                                         switch (ainfo->pair_storage [quad]) {
4632                                         case ArgInIReg:
4633                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4634                                                 break;
4635                                         case ArgInFloatSSEReg:
4636                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4637                                                 break;
4638                                         case ArgInDoubleSSEReg:
4639                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4640                                                 break;
4641                                         case ArgNone:
4642                                                 break;
4643                                         default:
4644                                                 g_assert_not_reached ();
4645                                         }
4646                                 }
4647                                 break;
4648                         default:
4649                                 break;
4650                         }
4651
4652                         continue;
4653                 }
4654
4655                 /* Save volatile arguments to the stack */
4656                 if (ins->opcode != OP_REGVAR) {
4657                         switch (ainfo->storage) {
4658                         case ArgInIReg: {
4659                                 guint32 size = 8;
4660
4661                                 /* FIXME: I1 etc */
4662                                 /*
4663                                 if (stack_offset & 0x1)
4664                                         size = 1;
4665                                 else if (stack_offset & 0x2)
4666                                         size = 2;
4667                                 else if (stack_offset & 0x4)
4668                                         size = 4;
4669                                 else
4670                                         size = 8;
4671                                 */
4672                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4673                                 break;
4674                         }
4675                         case ArgInFloatSSEReg:
4676                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4677                                 break;
4678                         case ArgInDoubleSSEReg:
4679                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4680                                 break;
4681                         case ArgValuetypeInReg:
4682                                 for (quad = 0; quad < 2; quad ++) {
4683                                         switch (ainfo->pair_storage [quad]) {
4684                                         case ArgInIReg:
4685                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4686                                                 break;
4687                                         case ArgInFloatSSEReg:
4688                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4689                                                 break;
4690                                         case ArgInDoubleSSEReg:
4691                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4692                                                 break;
4693                                         case ArgNone:
4694                                                 break;
4695                                         default:
4696                                                 g_assert_not_reached ();
4697                                         }
4698                                 }
4699                                 break;
4700                         case ArgValuetypeAddrInIReg:
4701                                 if (ainfo->pair_storage [0] == ArgInIReg)
4702                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
4703                                 break;
4704                         default:
4705                                 break;
4706                         }
4707                 } else {
4708                         /* Argument allocated to (non-volatile) register */
4709                         switch (ainfo->storage) {
4710                         case ArgInIReg:
4711                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4712                                 break;
4713                         case ArgOnStack:
4714                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4715                                 break;
4716                         default:
4717                                 g_assert_not_reached ();
4718                         }
4719                 }
4720         }
4721
4722         /* Might need to attach the thread to the JIT  or change the domain for the callback */
4723         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4724                 guint64 domain = (guint64)cfg->domain;
4725
4726                 args_clobbered = TRUE;
4727
4728                 /*
4729                  * The call might clobber argument registers, but they are already
4730                  * saved to the stack/global regs.
4731                  */
4732                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4733                         guint8 *buf, *no_domain_branch;
4734
4735                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4736                         if ((domain >> 32) == 0)
4737                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4738                         else
4739                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4740                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4741                         no_domain_branch = code;
4742                         x86_branch8 (code, X86_CC_NE, 0, 0);
4743                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4744                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4745                         buf = code;
4746                         x86_branch8 (code, X86_CC_NE, 0, 0);
4747                         amd64_patch (no_domain_branch, code);
4748                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4749                                           (gpointer)"mono_jit_thread_attach", TRUE);
4750                         amd64_patch (buf, code);
4751 #ifdef PLATFORM_WIN32
4752                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4753                         /* FIXME: Add a separate key for LMF to avoid this */
4754                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4755 #endif
4756                 } else {
4757                         g_assert (!cfg->compile_aot);
4758                         if ((domain >> 32) == 0)
4759                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4760                         else
4761                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4762                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4763                                           (gpointer)"mono_jit_thread_attach", TRUE);
4764                 }
4765         }
4766
4767         if (method->save_lmf) {
4768                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4769                         /*
4770                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4771                          * through the mono_lmf_addr TLS variable.
4772                          */
4773                         /* %rax = previous_lmf */
4774                         x86_prefix (code, X86_FS_PREFIX);
4775                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4776
4777                         /* Save previous_lmf */
4778                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4779                         /* Set new lmf */
4780                         if (lmf_offset == 0) {
4781                                 x86_prefix (code, X86_FS_PREFIX);
4782                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4783                         } else {
4784                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4785                                 x86_prefix (code, X86_FS_PREFIX);
4786                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4787                         }
4788                 } else {
4789                         if (lmf_addr_tls_offset != -1) {
4790                                 /* Load lmf quicky using the FS register */
4791                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4792 #ifdef PLATFORM_WIN32
4793                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4794                                 /* FIXME: Add a separate key for LMF to avoid this */
4795                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4796 #endif
4797                         }
4798                         else {
4799                                 /*
4800                                  * The call might clobber argument registers, but they are already
4801                                  * saved to the stack/global regs.
4802                                  */
4803                                 args_clobbered = TRUE;
4804                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4805                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
4806                         }
4807
4808                         /* Save lmf_addr */
4809                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4810                         /* Save previous_lmf */
4811                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4812                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4813                         /* Set new lmf */
4814                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4815                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4816                 }
4817         }
4818
4819         if (trace) {
4820                 args_clobbered = TRUE;
4821                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4822         }
4823
4824         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4825                 args_clobbered = TRUE;
4826
4827         /*
4828          * Optimize the common case of the first bblock making a call with the same
4829          * arguments as the method. This works because the arguments are still in their
4830          * original argument registers.
4831          * FIXME: Generalize this
4832          */
4833         if (!args_clobbered) {
4834                 MonoBasicBlock *first_bb = cfg->bb_entry;
4835                 MonoInst *next;
4836
4837                 next = mono_bb_first_ins (first_bb);
4838                 if (!next && first_bb->next_bb) {
4839                         first_bb = first_bb->next_bb;
4840                         next = mono_bb_first_ins (first_bb);
4841                 }
4842
4843                 if (first_bb->in_count > 1)
4844                         next = NULL;
4845
4846                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4847                         ArgInfo *ainfo = cinfo->args + i;
4848                         gboolean match = FALSE;
4849
4850                         ins = cfg->args [i];
4851                         if (ins->opcode != OP_REGVAR) {
4852                                 switch (ainfo->storage) {
4853                                 case ArgInIReg: {
4854                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4855                                                 if (next->dreg == ainfo->reg) {
4856                                                         NULLIFY_INS (next);
4857                                                         match = TRUE;
4858                                                 } else {
4859                                                         next->opcode = OP_MOVE;
4860                                                         next->sreg1 = ainfo->reg;
4861                                                         /* Only continue if the instruction doesn't change argument regs */
4862                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4863                                                                 match = TRUE;
4864                                                 }
4865                                         }
4866                                         break;
4867                                 }
4868                                 default:
4869                                         break;
4870                                 }
4871                         } else {
4872                                 /* Argument allocated to (non-volatile) register */
4873                                 switch (ainfo->storage) {
4874                                 case ArgInIReg:
4875                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4876                                                 NULLIFY_INS (next);
4877                                                 match = TRUE;
4878                                         }
4879                                         break;
4880                                 default:
4881                                         break;
4882                                 }
4883                         }
4884
4885                         if (match) {
4886                                 next = next->next;
4887                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4888                                 if (!next)
4889                                         break;
4890                         }
4891                 }
4892         }
4893
4894         cfg->code_len = code - cfg->native_code;
4895
4896         g_assert (cfg->code_len < cfg->code_size);
4897
4898         return code;
4899 }
4900
4901 void
4902 mono_arch_emit_epilog (MonoCompile *cfg)
4903 {
4904         MonoMethod *method = cfg->method;
4905         int quad, pos, i;
4906         guint8 *code;
4907         int max_epilog_size;
4908         CallInfo *cinfo;
4909         gint32 lmf_offset = cfg->arch.lmf_offset;
4910
4911         max_epilog_size = get_max_epilog_size (cfg);
4912
4913         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4914                 cfg->code_size *= 2;
4915                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4916                 mono_jit_stats.code_reallocs++;
4917         }
4918
4919         code = cfg->native_code + cfg->code_len;
4920
4921         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4922                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4923
4924         /* the code restoring the registers must be kept in sync with OP_JMP */
4925         pos = 0;
4926
4927         if (method->save_lmf) {
4928                 /* check if we need to restore protection of the stack after a stack overflow */
4929                 if (mono_get_jit_tls_offset () != -1) {
4930                         guint8 *patch;
4931                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4932                         /* we load the value in a separate instruction: this mechanism may be
4933                          * used later as a safer way to do thread interruption
4934                          */
4935                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
4936                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4937                         patch = code;
4938                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
4939                         /* note that the call trampoline will preserve eax/edx */
4940                         x86_call_reg (code, X86_ECX);
4941                         x86_patch (patch, code);
4942                 } else {
4943                         /* FIXME: maybe save the jit tls in the prolog */
4944                 }
4945                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4946                         /*
4947                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4948                          * through the mono_lmf_addr TLS variable.
4949                          */
4950                         /* reg = previous_lmf */
4951                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4952                         x86_prefix (code, X86_FS_PREFIX);
4953                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4954                 } else {
4955                         /* Restore previous lmf */
4956                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4957                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4958                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4959                 }
4960
4961                 /* Restore caller saved regs */
4962                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4963                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
4964                 }
4965                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4966                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4967                 }
4968                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4969                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4970                 }
4971                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4972                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4973                 }
4974                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4975                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4976                 }
4977                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4978                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4979                 }
4980         } else {
4981
4982                 if (cfg->arch.omit_fp) {
4983                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4984
4985                         for (i = 0; i < AMD64_NREG; ++i)
4986                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4987                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4988                                         save_area_offset += 8;
4989                                 }
4990                 }
4991                 else {
4992                         for (i = 0; i < AMD64_NREG; ++i)
4993                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4994                                         pos -= sizeof (gpointer);
4995
4996                         if (pos) {
4997                                 if (pos == - sizeof (gpointer)) {
4998                                         /* Only one register, so avoid lea */
4999                                         for (i = AMD64_NREG - 1; i > 0; --i)
5000                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5001                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5002                                                 }
5003                                 }
5004                                 else {
5005                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5006
5007                                         /* Pop registers in reverse order */
5008                                         for (i = AMD64_NREG - 1; i > 0; --i)
5009                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5010                                                         amd64_pop_reg (code, i);
5011                                                 }
5012                                 }
5013                         }
5014                 }
5015         }
5016
5017         /* Load returned vtypes into registers if needed */
5018         cinfo = cfg->arch.cinfo;
5019         if (cinfo->ret.storage == ArgValuetypeInReg) {
5020                 ArgInfo *ainfo = &cinfo->ret;
5021                 MonoInst *inst = cfg->ret;
5022
5023                 for (quad = 0; quad < 2; quad ++) {
5024                         switch (ainfo->pair_storage [quad]) {
5025                         case ArgInIReg:
5026                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5027                                 break;
5028                         case ArgInFloatSSEReg:
5029                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5030                                 break;
5031                         case ArgInDoubleSSEReg:
5032                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5033                                 break;
5034                         case ArgNone:
5035                                 break;
5036                         default:
5037                                 g_assert_not_reached ();
5038                         }
5039                 }
5040         }
5041
5042         if (cfg->arch.omit_fp) {
5043                 if (cfg->arch.stack_alloc_size)
5044                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5045         } else {
5046                 amd64_leave (code);
5047         }
5048         async_exc_point (code);
5049         amd64_ret (code);
5050
5051         cfg->code_len = code - cfg->native_code;
5052
5053         g_assert (cfg->code_len < cfg->code_size);
5054
5055         if (cfg->arch.omit_fp) {
5056                 /*
5057                  * Encode the stack size into used_int_regs so the exception handler
5058                  * can access it.
5059                  */
5060                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5061                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5062         }
5063 }
5064
5065 void
5066 mono_arch_emit_exceptions (MonoCompile *cfg)
5067 {
5068         MonoJumpInfo *patch_info;
5069         int nthrows, i;
5070         guint8 *code;
5071         MonoClass *exc_classes [16];
5072         guint8 *exc_throw_start [16], *exc_throw_end [16];
5073         guint32 code_size = 0;
5074
5075         /* Compute needed space */
5076         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5077                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5078                         code_size += 40;
5079                 if (patch_info->type == MONO_PATCH_INFO_R8)
5080                         code_size += 8 + 15; /* sizeof (double) + alignment */
5081                 if (patch_info->type == MONO_PATCH_INFO_R4)
5082                         code_size += 4 + 15; /* sizeof (float) + alignment */
5083         }
5084
5085         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5086                 cfg->code_size *= 2;
5087                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5088                 mono_jit_stats.code_reallocs++;
5089         }
5090
5091         code = cfg->native_code + cfg->code_len;
5092
5093         /* add code to raise exceptions */
5094         nthrows = 0;
5095         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5096                 switch (patch_info->type) {
5097                 case MONO_PATCH_INFO_EXC: {
5098                         MonoClass *exc_class;
5099                         guint8 *buf, *buf2;
5100                         guint32 throw_ip;
5101
5102                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5103
5104                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5105                         g_assert (exc_class);
5106                         throw_ip = patch_info->ip.i;
5107
5108                         //x86_breakpoint (code);
5109                         /* Find a throw sequence for the same exception class */
5110                         for (i = 0; i < nthrows; ++i)
5111                                 if (exc_classes [i] == exc_class)
5112                                         break;
5113                         if (i < nthrows) {
5114                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5115                                 x86_jump_code (code, exc_throw_start [i]);
5116                                 patch_info->type = MONO_PATCH_INFO_NONE;
5117                         }
5118                         else {
5119                                 buf = code;
5120                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5121                                 buf2 = code;
5122
5123                                 if (nthrows < 16) {
5124                                         exc_classes [nthrows] = exc_class;
5125                                         exc_throw_start [nthrows] = code;
5126                                 }
5127                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5128
5129                                 patch_info->type = MONO_PATCH_INFO_NONE;
5130
5131                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5132
5133                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5134                                 while (buf < buf2)
5135                                         x86_nop (buf);
5136
5137                                 if (nthrows < 16) {
5138                                         exc_throw_end [nthrows] = code;
5139                                         nthrows ++;
5140                                 }
5141                         }
5142                         break;
5143                 }
5144                 default:
5145                         /* do nothing */
5146                         break;
5147                 }
5148         }
5149
5150         /* Handle relocations with RIP relative addressing */
5151         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5152                 gboolean remove = FALSE;
5153
5154                 switch (patch_info->type) {
5155                 case MONO_PATCH_INFO_R8:
5156                 case MONO_PATCH_INFO_R4: {
5157                         guint8 *pos;
5158
5159                         /* The SSE opcodes require a 16 byte alignment */
5160                         code = (guint8*)ALIGN_TO (code, 16);
5161
5162                         pos = cfg->native_code + patch_info->ip.i;
5163
5164                         if (IS_REX (pos [1]))
5165                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5166                         else
5167                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5168
5169                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5170                                 *(double*)code = *(double*)patch_info->data.target;
5171                                 code += sizeof (double);
5172                         } else {
5173                                 *(float*)code = *(float*)patch_info->data.target;
5174                                 code += sizeof (float);
5175                         }
5176
5177                         remove = TRUE;
5178                         break;
5179                 }
5180                 default:
5181                         break;
5182                 }
5183
5184                 if (remove) {
5185                         if (patch_info == cfg->patch_info)
5186                                 cfg->patch_info = patch_info->next;
5187                         else {
5188                                 MonoJumpInfo *tmp;
5189
5190                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5191                                         ;
5192                                 tmp->next = patch_info->next;
5193                         }
5194                 }
5195         }
5196
5197         cfg->code_len = code - cfg->native_code;
5198
5199         g_assert (cfg->code_len < cfg->code_size);
5200
5201 }
5202
5203 void*
5204 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5205 {
5206         guchar *code = p;
5207         CallInfo *cinfo = NULL;
5208         MonoMethodSignature *sig;
5209         MonoInst *inst;
5210         int i, n, stack_area = 0;
5211
5212         /* Keep this in sync with mono_arch_get_argument_info */
5213
5214         if (enable_arguments) {
5215                 /* Allocate a new area on the stack and save arguments there */
5216                 sig = mono_method_signature (cfg->method);
5217
5218                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5219
5220                 n = sig->param_count + sig->hasthis;
5221
5222                 stack_area = ALIGN_TO (n * 8, 16);
5223
5224                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5225
5226                 for (i = 0; i < n; ++i) {
5227                         inst = cfg->args [i];
5228
5229                         if (inst->opcode == OP_REGVAR)
5230                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5231                         else {
5232                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5233                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5234                         }
5235                 }
5236         }
5237
5238         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5239         amd64_set_reg_template (code, AMD64_ARG_REG1);
5240         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5241         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5242
5243         if (enable_arguments)
5244                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5245
5246         return code;
5247 }
5248
5249 enum {
5250         SAVE_NONE,
5251         SAVE_STRUCT,
5252         SAVE_EAX,
5253         SAVE_EAX_EDX,
5254         SAVE_XMM
5255 };
5256
5257 void*
5258 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5259 {
5260         guchar *code = p;
5261         int save_mode = SAVE_NONE;
5262         MonoMethod *method = cfg->method;
5263         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5264
5265         switch (rtype) {
5266         case MONO_TYPE_VOID:
5267                 /* special case string .ctor icall */
5268                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5269                         save_mode = SAVE_EAX;
5270                 else
5271                         save_mode = SAVE_NONE;
5272                 break;
5273         case MONO_TYPE_I8:
5274         case MONO_TYPE_U8:
5275                 save_mode = SAVE_EAX;
5276                 break;
5277         case MONO_TYPE_R4:
5278         case MONO_TYPE_R8:
5279                 save_mode = SAVE_XMM;
5280                 break;
5281         case MONO_TYPE_GENERICINST:
5282                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5283                         save_mode = SAVE_EAX;
5284                         break;
5285                 }
5286                 /* Fall through */
5287         case MONO_TYPE_VALUETYPE:
5288                 save_mode = SAVE_STRUCT;
5289                 break;
5290         default:
5291                 save_mode = SAVE_EAX;
5292                 break;
5293         }
5294
5295         /* Save the result and copy it into the proper argument register */
5296         switch (save_mode) {
5297         case SAVE_EAX:
5298                 amd64_push_reg (code, AMD64_RAX);
5299                 /* Align stack */
5300                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5301                 if (enable_arguments)
5302                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5303                 break;
5304         case SAVE_STRUCT:
5305                 /* FIXME: */
5306                 if (enable_arguments)
5307                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5308                 break;
5309         case SAVE_XMM:
5310                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5311                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5312                 /* Align stack */
5313                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5314                 /*
5315                  * The result is already in the proper argument register so no copying
5316                  * needed.
5317                  */
5318                 break;
5319         case SAVE_NONE:
5320                 break;
5321         default:
5322                 g_assert_not_reached ();
5323         }
5324
5325         /* Set %al since this is a varargs call */
5326         if (save_mode == SAVE_XMM)
5327                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5328         else
5329                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5330
5331         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5332         amd64_set_reg_template (code, AMD64_ARG_REG1);
5333         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5334
5335         /* Restore result */
5336         switch (save_mode) {
5337         case SAVE_EAX:
5338                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5339                 amd64_pop_reg (code, AMD64_RAX);
5340                 break;
5341         case SAVE_STRUCT:
5342                 /* FIXME: */
5343                 break;
5344         case SAVE_XMM:
5345                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5346                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5347                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5348                 break;
5349         case SAVE_NONE:
5350                 break;
5351         default:
5352                 g_assert_not_reached ();
5353         }
5354
5355         return code;
5356 }
5357
5358 void
5359 mono_arch_flush_icache (guint8 *code, gint size)
5360 {
5361         /* Not needed */
5362 }
5363
5364 void
5365 mono_arch_flush_register_windows (void)
5366 {
5367 }
5368
5369 gboolean
5370 mono_arch_is_inst_imm (gint64 imm)
5371 {
5372         return amd64_is_imm32 (imm);
5373 }
5374
5375 /*
5376  * Determine whenever the trap whose info is in SIGINFO is caused by
5377  * integer overflow.
5378  */
5379 gboolean
5380 mono_arch_is_int_overflow (void *sigctx, void *info)
5381 {
5382         MonoContext ctx;
5383         guint8* rip;
5384         int reg;
5385         gint64 value;
5386
5387         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5388
5389         rip = (guint8*)ctx.rip;
5390
5391         if (IS_REX (rip [0])) {
5392                 reg = amd64_rex_b (rip [0]);
5393                 rip ++;
5394         }
5395         else
5396                 reg = 0;
5397
5398         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5399                 /* idiv REG */
5400                 reg += x86_modrm_rm (rip [1]);
5401
5402                 switch (reg) {
5403                 case AMD64_RAX:
5404                         value = ctx.rax;
5405                         break;
5406                 case AMD64_RBX:
5407                         value = ctx.rbx;
5408                         break;
5409                 case AMD64_RCX:
5410                         value = ctx.rcx;
5411                         break;
5412                 case AMD64_RDX:
5413                         value = ctx.rdx;
5414                         break;
5415                 case AMD64_RBP:
5416                         value = ctx.rbp;
5417                         break;
5418                 case AMD64_RSP:
5419                         value = ctx.rsp;
5420                         break;
5421                 case AMD64_RSI:
5422                         value = ctx.rsi;
5423                         break;
5424                 case AMD64_RDI:
5425                         value = ctx.rdi;
5426                         break;
5427                 case AMD64_R12:
5428                         value = ctx.r12;
5429                         break;
5430                 case AMD64_R13:
5431                         value = ctx.r13;
5432                         break;
5433                 case AMD64_R14:
5434                         value = ctx.r14;
5435                         break;
5436                 case AMD64_R15:
5437                         value = ctx.r15;
5438                         break;
5439                 default:
5440                         g_assert_not_reached ();
5441                         reg = -1;
5442                 }
5443
5444                 if (value == -1)
5445                         return TRUE;
5446         }
5447
5448         return FALSE;
5449 }
5450
5451 guint32
5452 mono_arch_get_patch_offset (guint8 *code)
5453 {
5454         return 3;
5455 }
5456
5457 /**
5458  * mono_breakpoint_clean_code:
5459  *
5460  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5461  * breakpoints in the original code, they are removed in the copy.
5462  *
5463  * Returns TRUE if no sw breakpoint was present.
5464  */
5465 gboolean
5466 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5467 {
5468         int i;
5469         gboolean can_write = TRUE;
5470         /*
5471          * If method_start is non-NULL we need to perform bound checks, since we access memory
5472          * at code - offset we could go before the start of the method and end up in a different
5473          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5474          * instead.
5475          */
5476         if (!method_start || code - offset >= method_start) {
5477                 memcpy (buf, code - offset, size);
5478         } else {
5479                 int diff = code - method_start;
5480                 memset (buf, 0, size);
5481                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5482         }
5483         code -= offset;
5484         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5485                 int idx = mono_breakpoint_info_index [i];
5486                 guint8 *ptr;
5487                 if (idx < 1)
5488                         continue;
5489                 ptr = mono_breakpoint_info [idx].address;
5490                 if (ptr >= code && ptr < code + size) {
5491                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5492                         can_write = FALSE;
5493                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5494                         buf [ptr - code] = saved_byte;
5495                 }
5496         }
5497         return can_write;
5498 }
5499
5500 gpointer
5501 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5502 {
5503         guint8 buf [10];
5504         guint32 reg;
5505         gint32 disp;
5506         guint8 rex = 0;
5507
5508         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5509         code = buf + 9;
5510
5511         *displacement = 0;
5512
5513         /* go to the start of the call instruction
5514          *
5515          * address_byte = (m << 6) | (o << 3) | reg
5516          * call opcode: 0xff address_byte displacement
5517          * 0xff m=1,o=2 imm8
5518          * 0xff m=2,o=2 imm32
5519          */
5520         code -= 7;
5521
5522         /*
5523          * A given byte sequence can match more than case here, so we have to be
5524          * really careful about the ordering of the cases. Longer sequences
5525          * come first.
5526          */
5527 #ifdef MONO_ARCH_HAVE_IMT
5528         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5529                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5530                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5531                  * ff 50 fc                call   *0xfffffffc(%rax)
5532                  */
5533                 reg = amd64_modrm_rm (code [5]);
5534                 disp = (signed char)code [6];
5535                 /* R10 is clobbered by the IMT thunk code */
5536                 g_assert (reg != AMD64_R10);
5537         }
5538 #else
5539         if (0) {
5540         }
5541 #endif
5542         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5543                         /*
5544                          * This is a interface call
5545                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5546                          * ff 10                  callq  *(%rax)
5547                          */
5548                 if (IS_REX (code [4]))
5549                         rex = code [4];
5550                 reg = amd64_modrm_rm (code [6]);
5551                 disp = 0;
5552                 /* R10 is clobbered by the IMT thunk code */
5553                 g_assert (reg != AMD64_R10);
5554         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5555                 /* call OFFSET(%rip) */
5556                 disp = *(guint32*)(code + 3);
5557                 return (gpointer*)(code + disp + 7);
5558         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5559                 /* call *[r12+disp32] */
5560                 if (IS_REX (code [-1]))
5561                         rex = code [-1];
5562                 reg = AMD64_RSP;
5563                 disp = *(gint32*)(code + 3);
5564         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5565                 /* call *[reg+disp32] */
5566                 if (IS_REX (code [0]))
5567                         rex = code [0];
5568                 reg = amd64_modrm_rm (code [2]);
5569                 disp = *(gint32*)(code + 3);
5570                 /* R10 is clobbered by the IMT thunk code */
5571                 g_assert (reg != AMD64_R10);
5572         } else if (code [2] == 0xe8) {
5573                 /* call <ADDR> */
5574                 return NULL;
5575         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5576                 /* call *[r12+disp32] */
5577                 if (IS_REX (code [2]))
5578                         rex = code [2];
5579                 reg = AMD64_RSP;
5580                 disp = *(gint8*)(code + 6);
5581         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5582                 /* call *%reg */
5583                 return NULL;
5584         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5585                 /* call *[reg+disp8] */
5586                 if (IS_REX (code [3]))
5587                         rex = code [3];
5588                 reg = amd64_modrm_rm (code [5]);
5589                 disp = *(gint8*)(code + 6);
5590                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5591         }
5592         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5593                         /*
5594                          * This is a interface call: should check the above code can't catch it earlier
5595                          * 8b 40 30   mov    0x30(%eax),%eax
5596                          * ff 10      call   *(%eax)
5597                          */
5598                 if (IS_REX (code [4]))
5599                         rex = code [4];
5600                 reg = amd64_modrm_rm (code [6]);
5601                 disp = 0;
5602         }
5603         else
5604                 g_assert_not_reached ();
5605
5606         reg += amd64_rex_b (rex);
5607
5608         /* R11 is clobbered by the trampoline code */
5609         g_assert (reg != AMD64_R11);
5610
5611         *displacement = disp;
5612         return regs [reg];
5613 }
5614
5615 gpointer*
5616 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5617 {
5618         gpointer vt;
5619         int displacement;
5620         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5621         if (!vt)
5622                 return NULL;
5623         return (gpointer*)((char*)vt + displacement);
5624 }
5625
5626 int
5627 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5628 {
5629         int this_reg = AMD64_ARG_REG1;
5630
5631         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5632                 CallInfo *cinfo;
5633
5634                 if (!gsctx && code)
5635                         gsctx = mono_get_generic_context_from_code (code);
5636
5637                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5638
5639                 if (cinfo->ret.storage != ArgValuetypeInReg)
5640                         this_reg = AMD64_ARG_REG2;
5641                 g_free (cinfo);
5642         }
5643
5644         return this_reg;
5645 }
5646
5647 gpointer
5648 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5649 {
5650         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
5651 }
5652
5653 #define MAX_ARCH_DELEGATE_PARAMS 10
5654
5655 gpointer
5656 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5657 {
5658         guint8 *code, *start;
5659         int i;
5660
5661         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5662                 return NULL;
5663
5664         /* FIXME: Support more cases */
5665         if (MONO_TYPE_ISSTRUCT (sig->ret))
5666                 return NULL;
5667
5668         if (has_target) {
5669                 static guint8* cached = NULL;
5670
5671                 if (cached)
5672                         return cached;
5673
5674                 start = code = mono_global_codeman_reserve (64);
5675
5676                 /* Replace the this argument with the target */
5677                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5678                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5679                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5680
5681                 g_assert ((code - start) < 64);
5682
5683                 mono_debug_add_delegate_trampoline (start, code - start);
5684
5685                 mono_memory_barrier ();
5686
5687                 cached = start;
5688         } else {
5689                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5690                 for (i = 0; i < sig->param_count; ++i)
5691                         if (!mono_is_regsize_var (sig->params [i]))
5692                                 return NULL;
5693                 if (sig->param_count > 4)
5694                         return NULL;
5695
5696                 code = cache [sig->param_count];
5697                 if (code)
5698                         return code;
5699
5700                 start = code = mono_global_codeman_reserve (64);
5701
5702                 if (sig->param_count == 0) {
5703                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5704                 } else {
5705                         /* We have to shift the arguments left */
5706                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5707                         for (i = 0; i < sig->param_count; ++i) {
5708 #ifdef PLATFORM_WIN32
5709                                 if (i < 3)
5710                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5711                                 else
5712                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
5713 #else
5714                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5715 #endif
5716                         }
5717
5718                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5719                 }
5720                 g_assert ((code - start) < 64);
5721
5722                 mono_debug_add_delegate_trampoline (start, code - start);
5723
5724                 mono_memory_barrier ();
5725
5726                 cache [sig->param_count] = start;
5727         }
5728
5729         return start;
5730 }
5731
5732 /*
5733  * Support for fast access to the thread-local lmf structure using the GS
5734  * segment register on NPTL + kernel 2.6.x.
5735  */
5736
5737 static gboolean tls_offset_inited = FALSE;
5738
5739 void
5740 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5741 {
5742         if (!tls_offset_inited) {
5743 #ifdef PLATFORM_WIN32
5744                 /*
5745                  * We need to init this multiple times, since when we are first called, the key might not
5746                  * be initialized yet.
5747                  */
5748                 appdomain_tls_offset = mono_domain_get_tls_key ();
5749                 lmf_tls_offset = mono_get_jit_tls_key ();
5750                 thread_tls_offset = mono_thread_get_tls_key ();
5751                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
5752
5753                 /* Only 64 tls entries can be accessed using inline code */
5754                 if (appdomain_tls_offset >= 64)
5755                         appdomain_tls_offset = -1;
5756                 if (lmf_tls_offset >= 64)
5757                         lmf_tls_offset = -1;
5758                 if (thread_tls_offset >= 64)
5759                         thread_tls_offset = -1;
5760 #else
5761                 tls_offset_inited = TRUE;
5762 #ifdef MONO_XEN_OPT
5763                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5764 #endif
5765                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5766                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5767                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5768                 thread_tls_offset = mono_thread_get_tls_offset ();
5769 #endif
5770         }
5771 }
5772
5773 void
5774 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5775 {
5776 }
5777
5778 #ifdef MONO_ARCH_HAVE_IMT
5779
5780 #define CMP_SIZE (6 + 1)
5781 #define CMP_REG_REG_SIZE (4 + 1)
5782 #define BR_SMALL_SIZE 2
5783 #define BR_LARGE_SIZE 6
5784 #define MOV_REG_IMM_SIZE 10
5785 #define MOV_REG_IMM_32BIT_SIZE 6
5786 #define JUMP_REG_SIZE (2 + 1)
5787
5788 static int
5789 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5790 {
5791         int i, distance = 0;
5792         for (i = start; i < target; ++i)
5793                 distance += imt_entries [i]->chunk_size;
5794         return distance;
5795 }
5796
5797 /*
5798  * LOCKING: called with the domain lock held
5799  */
5800 gpointer
5801 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5802         gpointer fail_tramp)
5803 {
5804         int i;
5805         int size = 0;
5806         guint8 *code, *start;
5807         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5808
5809         for (i = 0; i < count; ++i) {
5810                 MonoIMTCheckItem *item = imt_entries [i];
5811                 if (item->is_equals) {
5812                         if (item->check_target_idx) {
5813                                 if (!item->compare_done) {
5814                                         if (amd64_is_imm32 (item->key))
5815                                                 item->chunk_size += CMP_SIZE;
5816                                         else
5817                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5818                                 }
5819                                 if (vtable_is_32bit)
5820                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5821                                 else
5822                                         item->chunk_size += MOV_REG_IMM_SIZE;
5823                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5824                         } else {
5825                                 if (fail_tramp) {
5826                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
5827                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
5828                                 } else {
5829                                         if (vtable_is_32bit)
5830                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5831                                         else
5832                                                 item->chunk_size += MOV_REG_IMM_SIZE;
5833                                         item->chunk_size += JUMP_REG_SIZE;
5834                                         /* with assert below:
5835                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5836                                          */
5837                                 }
5838                         }
5839                 } else {
5840                         if (amd64_is_imm32 (item->key))
5841                                 item->chunk_size += CMP_SIZE;
5842                         else
5843                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5844                         item->chunk_size += BR_LARGE_SIZE;
5845                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5846                 }
5847                 size += item->chunk_size;
5848         }
5849         if (fail_tramp)
5850                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5851         else
5852                 code = mono_code_manager_reserve (domain->code_mp, size);
5853         start = code;
5854         for (i = 0; i < count; ++i) {
5855                 MonoIMTCheckItem *item = imt_entries [i];
5856                 item->code_target = code;
5857                 if (item->is_equals) {
5858                         if (item->check_target_idx) {
5859                                 if (!item->compare_done) {
5860                                         if (amd64_is_imm32 (item->key))
5861                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5862                                         else {
5863                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5864                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5865                                         }
5866                                 }
5867                                 item->jmp_code = code;
5868                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5869                                 /* See the comment below about R10 */
5870                                 if (fail_tramp) {
5871                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5872                                         amd64_jump_reg (code, AMD64_R10);
5873                                 } else {
5874                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5875                                         amd64_jump_membase (code, AMD64_R10, 0);
5876                                 }
5877                         } else {
5878                                 if (fail_tramp) {
5879                                         if (amd64_is_imm32 (item->key))
5880                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5881                                         else {
5882                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5883                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5884                                         }
5885                                         item->jmp_code = code;
5886                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5887                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5888                                         amd64_jump_reg (code, AMD64_R10);
5889                                         amd64_patch (item->jmp_code, code);
5890                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
5891                                         amd64_jump_reg (code, AMD64_R10);
5892                                         item->jmp_code = NULL;
5893
5894                                 } else {
5895                                         /* enable the commented code to assert on wrong method */
5896 #if 0
5897                                         if (amd64_is_imm32 (item->key))
5898                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5899                                         else {
5900                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5901                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5902                                         }
5903                                         item->jmp_code = code;
5904                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5905                                         /* See the comment below about R10 */
5906                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5907                                         amd64_jump_membase (code, AMD64_R10, 0);
5908                                         amd64_patch (item->jmp_code, code);
5909                                         amd64_breakpoint (code);
5910                                         item->jmp_code = NULL;
5911 #else
5912                                         /* We're using R10 here because R11
5913                                            needs to be preserved.  R10 needs
5914                                            to be preserved for calls which
5915                                            require a runtime generic context,
5916                                            but interface calls don't. */
5917                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5918                                         amd64_jump_membase (code, AMD64_R10, 0);
5919 #endif
5920                                 }
5921                         }
5922                 } else {
5923                         if (amd64_is_imm32 (item->key))
5924                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5925                         else {
5926                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5927                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5928                         }
5929                         item->jmp_code = code;
5930                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5931                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5932                         else
5933                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5934                 }
5935                 g_assert (code - item->code_target <= item->chunk_size);
5936         }
5937         /* patch the branches to get to the target items */
5938         for (i = 0; i < count; ++i) {
5939                 MonoIMTCheckItem *item = imt_entries [i];
5940                 if (item->jmp_code) {
5941                         if (item->check_target_idx) {
5942                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5943                         }
5944                 }
5945         }
5946
5947         if (!fail_tramp)
5948                 mono_stats.imt_thunks_size += code - start;
5949         g_assert (code - start <= size);
5950
5951         return start;
5952 }
5953
5954 MonoMethod*
5955 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
5956 {
5957         return regs [MONO_ARCH_IMT_REG];
5958 }
5959
5960 MonoObject*
5961 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
5962 {
5963         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
5964 }
5965
5966 void
5967 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
5968 {
5969         /* Done by the implementation of the CALL_MEMBASE opcodes */
5970 }
5971 #endif
5972
5973 MonoVTable*
5974 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
5975 {
5976         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5977 }
5978
5979 MonoInst*
5980 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5981 {
5982         MonoInst *ins = NULL;
5983         int opcode = 0;
5984
5985         if (cmethod->klass == mono_defaults.math_class) {
5986                 if (strcmp (cmethod->name, "Sin") == 0) {
5987                         opcode = OP_SIN;
5988                 } else if (strcmp (cmethod->name, "Cos") == 0) {
5989                         opcode = OP_COS;
5990                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5991                         opcode = OP_SQRT;
5992                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5993                         opcode = OP_ABS;
5994                 }
5995
5996                 if (opcode) {
5997                         MONO_INST_NEW (cfg, ins, opcode);
5998                         ins->type = STACK_R8;
5999                         ins->dreg = mono_alloc_freg (cfg);
6000                         ins->sreg1 = args [0]->dreg;
6001                         MONO_ADD_INS (cfg->cbb, ins);
6002                 }
6003
6004                 opcode = 0;
6005                 if (cfg->opt & MONO_OPT_CMOV) {
6006                         if (strcmp (cmethod->name, "Min") == 0) {
6007                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6008                                         opcode = OP_IMIN;
6009                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6010                                         opcode = OP_IMIN_UN;
6011                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6012                                         opcode = OP_LMIN;
6013                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6014                                         opcode = OP_LMIN_UN;
6015                         } else if (strcmp (cmethod->name, "Max") == 0) {
6016                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6017                                         opcode = OP_IMAX;
6018                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6019                                         opcode = OP_IMAX_UN;
6020                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6021                                         opcode = OP_LMAX;
6022                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6023                                         opcode = OP_LMAX_UN;
6024                         }
6025                 }
6026
6027                 if (opcode) {
6028                         MONO_INST_NEW (cfg, ins, opcode);
6029                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6030                         ins->dreg = mono_alloc_ireg (cfg);
6031                         ins->sreg1 = args [0]->dreg;
6032                         ins->sreg2 = args [1]->dreg;
6033                         MONO_ADD_INS (cfg->cbb, ins);
6034                 }
6035
6036 #if 0
6037                 /* OP_FREM is not IEEE compatible */
6038                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6039                         MONO_INST_NEW (cfg, ins, OP_FREM);
6040                         ins->inst_i0 = args [0];
6041                         ins->inst_i1 = args [1];
6042                 }
6043 #endif
6044         }
6045
6046         /*
6047          * Can't implement CompareExchange methods this way since they have
6048          * three arguments.
6049          */
6050
6051         return ins;
6052 }
6053
6054 gboolean
6055 mono_arch_print_tree (MonoInst *tree, int arity)
6056 {
6057         return 0;
6058 }
6059
6060 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6061 {
6062         MonoInst* ins;
6063
6064         if (appdomain_tls_offset == -1)
6065                 return NULL;
6066
6067         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6068         ins->inst_offset = appdomain_tls_offset;
6069         return ins;
6070 }
6071
6072 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6073 {
6074         MonoInst* ins;
6075
6076         if (thread_tls_offset == -1)
6077                 return NULL;
6078
6079         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6080         ins->inst_offset = thread_tls_offset;
6081         return ins;
6082 }
6083
6084 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6085
6086 gpointer
6087 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6088 {
6089         switch (reg) {
6090         case AMD64_RCX: return (gpointer)ctx->rcx;
6091         case AMD64_RDX: return (gpointer)ctx->rdx;
6092         case AMD64_RBX: return (gpointer)ctx->rbx;
6093         case AMD64_RBP: return (gpointer)ctx->rbp;
6094         case AMD64_RSP: return (gpointer)ctx->rsp;
6095         default:
6096                 if (reg < 8)
6097                         return _CTX_REG (ctx, rax, reg);
6098                 else if (reg >= 12)
6099                         return _CTX_REG (ctx, r12, reg - 12);
6100                 else
6101                         g_assert_not_reached ();
6102         }
6103 }