mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *
  11  * (C) 2003 Ximian, Inc.
  12  */
  13 #include "mini.h"
  14 #include <string.h>
  15 #include <math.h>
  16 #include <unistd.h>
  17
  18 #include <mono/metadata/appdomain.h>
  19 #include <mono/metadata/debug-helpers.h>
  20 #include <mono/metadata/threads.h>
  21 #include <mono/metadata/profiler-private.h>
  22 #include <mono/metadata/mono-debug.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-amd64.h"
  27 #include "inssel.h"
  28 #include "cpu-amd64.h"
  29
  30 static gint lmf_tls_offset = -1;
  31 static gint appdomain_tls_offset = -1;
  32 static gint thread_tls_offset = -1;
  33
  34 #ifdef MONO_XEN_OPT
  35 /* TRUE by default until we add runtime detection of Xen */
  36 static gboolean optimize_for_xen = TRUE;
  37 #else
  38 #define optimize_for_xen 0
  39 #endif
  40
  41 static gboolean use_sse2 = !MONO_ARCH_USE_FPSTACK;
  42
  43 const char * const amd64_desc [OP_LAST];
  44 static const char*const * ins_spec = amd64_desc;
  45
  46 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  47
  48 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  49
  50 #ifdef PLATFORM_WIN32
  51 /* Under windows, the default pinvoke calling convention is stdcall */
  52 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  53 #else
  54 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  55 #endif
  56
  57 #define ARGS_OFFSET 16
  58 #define GP_SCRATCH_REG AMD64_R11
  59
  60 /*
  61  * AMD64 register usage:
  62  * - callee saved registers are used for global register allocation
  63  * - %r11 is used for materializing 64 bit constants in opcodes
  64  * - the rest is used for local allocation
  65  */
  66
  67 /*
  68  * Floating point comparison results:
  69  *                  ZF PF CF
  70  * A > B            0  0  0
  71  * A < B            0  0  1
  72  * A = B            1  0  0
  73  * A > B            0  0  0
  74  * UNORDERED        1  1  1
  75  */
  76
  77 #define NOT_IMPLEMENTED g_assert_not_reached ()
  78
  79 const char*
  80 mono_arch_regname (int reg) {
  81         switch (reg) {
  82         case AMD64_RAX: return "%rax";
  83         case AMD64_RBX: return "%rbx";
  84         case AMD64_RCX: return "%rcx";
  85         case AMD64_RDX: return "%rdx";
  86         case AMD64_RSP: return "%rsp";
  87         case AMD64_RBP: return "%rbp";
  88         case AMD64_RDI: return "%rdi";
  89         case AMD64_RSI: return "%rsi";
  90         case AMD64_R8: return "%r8";
  91         case AMD64_R9: return "%r9";
  92         case AMD64_R10: return "%r10";
  93         case AMD64_R11: return "%r11";
  94         case AMD64_R12: return "%r12";
  95         case AMD64_R13: return "%r13";
  96         case AMD64_R14: return "%r14";
  97         case AMD64_R15: return "%r15";
  98         }
  99         return "unknown";
 100 }
 101
 102 static const char * xmmregs [] = {
 103         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 104         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 105 };
 106
 107 const char*
 108 mono_arch_fregname (int reg)
 109 {
 110         if (reg < AMD64_XMM_NREG)
 111                 return xmmregs [reg];
 112         else
 113                 return "unknown";
 114 }
 115
 116 G_GNUC_UNUSED static void
 117 break_count (void)
 118 {
 119 }
 120
 121 G_GNUC_UNUSED static gboolean
 122 debug_count (void)
 123 {
 124         static int count = 0;
 125         count ++;
 126
 127         if (!getenv ("COUNT"))
 128                 return TRUE;
 129
 130         if (count == atoi (getenv ("COUNT"))) {
 131                 break_count ();
 132         }
 133
 134         if (count > atoi (getenv ("COUNT"))) {
 135                 return FALSE;
 136         }
 137
 138         return TRUE;
 139 }
 140
 141 static gboolean
 142 debug_omit_fp (void)
 143 {
 144 #if 0
 145         return debug_count ();
 146 #else
 147         return TRUE;
 148 #endif
 149 }
 150
 151 static inline void
 152 amd64_patch (unsigned char* code, gpointer target)
 153 {
 154         /* Skip REX */
 155         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 156                 code += 1;
 157
 158         if ((code [0] & 0xf8) == 0xb8) {
 159                 /* amd64_set_reg_template */
 160                 *(guint64*)(code + 1) = (guint64)target;
 161         }
 162         else if (code [0] == 0x8b) {
 163                 /* mov 0(%rip), %dreg */
 164                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 165         }
 166         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 167                 /* call *<OFFSET>(%rip) */
 168                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 169         }
 170         else if ((code [0] == 0xe8)) {
 171                 /* call <DISP> */
 172                 gint64 disp = (guint8*)target - (guint8*)code;
 173                 g_assert (amd64_is_imm32 (disp));
 174                 x86_patch (code, (unsigned char*)target);
 175         }
 176         else
 177                 x86_patch (code, (unsigned char*)target);
 178 }
 179
 180 typedef enum {
 181         ArgInIReg,
 182         ArgInFloatSSEReg,
 183         ArgInDoubleSSEReg,
 184         ArgOnStack,
 185         ArgValuetypeInReg,
 186         ArgNone /* only in pair_storage */
 187 } ArgStorage;
 188
 189 typedef struct {
 190         gint16 offset;
 191         gint8  reg;
 192         ArgStorage storage;
 193
 194         /* Only if storage == ArgValuetypeInReg */
 195         ArgStorage pair_storage [2];
 196         gint8 pair_regs [2];
 197 } ArgInfo;
 198
 199 typedef struct {
 200         int nargs;
 201         guint32 stack_usage;
 202         guint32 reg_usage;
 203         guint32 freg_usage;
 204         gboolean need_stack_align;
 205         ArgInfo ret;
 206         ArgInfo sig_cookie;
 207         ArgInfo args [1];
 208 } CallInfo;
 209
 210 #define DEBUG(a) if (cfg->verbose_level > 1) a
 211
 212 #define NEW_ICONST(cfg,dest,val) do {   \
 213                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 214                 (dest)->opcode = OP_ICONST;     \
 215                 (dest)->inst_c0 = (val);        \
 216                 (dest)->type = STACK_I4;        \
 217         } while (0)
 218
 219 #define PARAM_REGS 6
 220
 221 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 222
 223 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 224
 225 static void inline
 226 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 227 {
 228     ainfo->offset = *stack_size;
 229
 230     if (*gr >= PARAM_REGS) {
 231                 ainfo->storage = ArgOnStack;
 232                 (*stack_size) += sizeof (gpointer);
 233     }
 234     else {
 235                 ainfo->storage = ArgInIReg;
 236                 ainfo->reg = param_regs [*gr];
 237                 (*gr) ++;
 238     }
 239 }
 240
 241 #define FLOAT_PARAM_REGS 8
 242
 243 static void inline
 244 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 245 {
 246     ainfo->offset = *stack_size;
 247
 248     if (*gr >= FLOAT_PARAM_REGS) {
 249                 ainfo->storage = ArgOnStack;
 250                 (*stack_size) += sizeof (gpointer);
 251     }
 252     else {
 253                 /* A double register */
 254                 if (is_double)
 255                         ainfo->storage = ArgInDoubleSSEReg;
 256                 else
 257                         ainfo->storage = ArgInFloatSSEReg;
 258                 ainfo->reg = *gr;
 259                 (*gr) += 1;
 260     }
 261 }
 262
 263 typedef enum ArgumentClass {
 264         ARG_CLASS_NO_CLASS,
 265         ARG_CLASS_MEMORY,
 266         ARG_CLASS_INTEGER,
 267         ARG_CLASS_SSE
 268 } ArgumentClass;
 269
 270 static ArgumentClass
 271 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 272 {
 273         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 274         MonoType *ptype;
 275
 276         ptype = mono_type_get_underlying_type (type);
 277         switch (ptype->type) {
 278         case MONO_TYPE_BOOLEAN:
 279         case MONO_TYPE_CHAR:
 280         case MONO_TYPE_I1:
 281         case MONO_TYPE_U1:
 282         case MONO_TYPE_I2:
 283         case MONO_TYPE_U2:
 284         case MONO_TYPE_I4:
 285         case MONO_TYPE_U4:
 286         case MONO_TYPE_I:
 287         case MONO_TYPE_U:
 288         case MONO_TYPE_STRING:
 289         case MONO_TYPE_OBJECT:
 290         case MONO_TYPE_CLASS:
 291         case MONO_TYPE_SZARRAY:
 292         case MONO_TYPE_PTR:
 293         case MONO_TYPE_FNPTR:
 294         case MONO_TYPE_ARRAY:
 295         case MONO_TYPE_I8:
 296         case MONO_TYPE_U8:
 297                 class2 = ARG_CLASS_INTEGER;
 298                 break;
 299         case MONO_TYPE_R4:
 300         case MONO_TYPE_R8:
 301                 class2 = ARG_CLASS_SSE;
 302                 break;
 303
 304         case MONO_TYPE_TYPEDBYREF:
 305                 g_assert_not_reached ();
 306
 307         case MONO_TYPE_GENERICINST:
 308                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 309                         class2 = ARG_CLASS_INTEGER;
 310                         break;
 311                 }
 312                 /* fall through */
 313         case MONO_TYPE_VALUETYPE: {
 314                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 315                 int i;
 316
 317                 for (i = 0; i < info->num_fields; ++i) {
 318                         class2 = class1;
 319                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 320                 }
 321                 break;
 322         }
 323         default:
 324                 g_assert_not_reached ();
 325         }
 326
 327         /* Merge */
 328         if (class1 == class2)
 329                 ;
 330         else if (class1 == ARG_CLASS_NO_CLASS)
 331                 class1 = class2;
 332         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 333                 class1 = ARG_CLASS_MEMORY;
 334         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 335                 class1 = ARG_CLASS_INTEGER;
 336         else
 337                 class1 = ARG_CLASS_SSE;
 338
 339         return class1;
 340 }
 341
 342 static void
 343 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 344                gboolean is_return,
 345                guint32 *gr, guint32 *fr, guint32 *stack_size)
 346 {
 347         guint32 size, quad, nquads, i;
 348         ArgumentClass args [2];
 349         MonoMarshalType *info;
 350         MonoClass *klass;
 351
 352         klass = mono_class_from_mono_type (type);
 353         if (sig->pinvoke)
 354                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 355         else
 356                 size = mono_type_stack_size (&klass->byval_arg, NULL);
 357
 358         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 359                 /* Allways pass in memory */
 360                 ainfo->offset = *stack_size;
 361                 *stack_size += ALIGN_TO (size, 8);
 362                 ainfo->storage = ArgOnStack;
 363
 364                 return;
 365         }
 366
 367         /* FIXME: Handle structs smaller than 8 bytes */
 368         //if ((size % 8) != 0)
 369         //      NOT_IMPLEMENTED;
 370
 371         if (size > 8)
 372                 nquads = 2;
 373         else
 374                 nquads = 1;
 375
 376         /*
 377          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 378          * The X87 and SSEUP stuff is left out since there are no such types in
 379          * the CLR.
 380          */
 381         info = mono_marshal_load_type_info (klass);
 382         g_assert (info);
 383         if (info->native_size > 16) {
 384                 ainfo->offset = *stack_size;
 385                 *stack_size += ALIGN_TO (info->native_size, 8);
 386                 ainfo->storage = ArgOnStack;
 387
 388                 return;
 389         }
 390
 391         for (quad = 0; quad < nquads; ++quad) {
 392                 int size;
 393                 guint32 align;
 394                 ArgumentClass class1;
 395
 396                 class1 = ARG_CLASS_NO_CLASS;
 397                 for (i = 0; i < info->num_fields; ++i) {
 398                         size = mono_marshal_type_size (info->fields [i].field->type,
 399                                                                                    info->fields [i].mspec,
 400                                                                                    &align, TRUE, klass->unicode);
 401                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 402                                 /* Unaligned field */
 403                                 NOT_IMPLEMENTED;
 404                         }
 405
 406                         /* Skip fields in other quad */
 407                         if ((quad == 0) && (info->fields [i].offset >= 8))
 408                                 continue;
 409                         if ((quad == 1) && (info->fields [i].offset < 8))
 410                                 continue;
 411
 412                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 413                 }
 414                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 415                 args [quad] = class1;
 416         }
 417
 418         /* Post merger cleanup */
 419         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 420                 args [0] = args [1] = ARG_CLASS_MEMORY;
 421
 422         /* Allocate registers */
 423         {
 424                 int orig_gr = *gr;
 425                 int orig_fr = *fr;
 426
 427                 ainfo->storage = ArgValuetypeInReg;
 428                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 429                 for (quad = 0; quad < nquads; ++quad) {
 430                         switch (args [quad]) {
 431                         case ARG_CLASS_INTEGER:
 432                                 if (*gr >= PARAM_REGS)
 433                                         args [quad] = ARG_CLASS_MEMORY;
 434                                 else {
 435                                         ainfo->pair_storage [quad] = ArgInIReg;
 436                                         if (is_return)
 437                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 438                                         else
 439                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 440                                         (*gr) ++;
 441                                 }
 442                                 break;
 443                         case ARG_CLASS_SSE:
 444                                 if (*fr >= FLOAT_PARAM_REGS)
 445                                         args [quad] = ARG_CLASS_MEMORY;
 446                                 else {
 447                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 448                                         ainfo->pair_regs [quad] = *fr;
 449                                         (*fr) ++;
 450                                 }
 451                                 break;
 452                         case ARG_CLASS_MEMORY:
 453                                 break;
 454                         default:
 455                                 g_assert_not_reached ();
 456                         }
 457                 }
 458
 459                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 460                         /* Revert possible register assignments */
 461                         *gr = orig_gr;
 462                         *fr = orig_fr;
 463
 464                         ainfo->offset = *stack_size;
 465                         *stack_size += ALIGN_TO (info->native_size, 8);
 466                         ainfo->storage = ArgOnStack;
 467                 }
 468         }
 469 }
 470
 471 /*
 472  * get_call_info:
 473  *
 474  *  Obtain information about a call according to the calling convention.
 475  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 476  * Draft Version 0.23" document for more information.
 477  */
 478 static CallInfo*
 479 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 480 {
 481         guint32 i, gr, fr;
 482         MonoType *ret_type;
 483         int n = sig->hasthis + sig->param_count;
 484         guint32 stack_size = 0;
 485         CallInfo *cinfo;
 486
 487         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 488
 489         gr = 0;
 490         fr = 0;
 491
 492         /* return value */
 493         {
 494                 ret_type = mono_type_get_underlying_type (sig->ret);
 495                 switch (ret_type->type) {
 496                 case MONO_TYPE_BOOLEAN:
 497                 case MONO_TYPE_I1:
 498                 case MONO_TYPE_U1:
 499                 case MONO_TYPE_I2:
 500                 case MONO_TYPE_U2:
 501                 case MONO_TYPE_CHAR:
 502                 case MONO_TYPE_I4:
 503                 case MONO_TYPE_U4:
 504                 case MONO_TYPE_I:
 505                 case MONO_TYPE_U:
 506                 case MONO_TYPE_PTR:
 507                 case MONO_TYPE_FNPTR:
 508                 case MONO_TYPE_CLASS:
 509                 case MONO_TYPE_OBJECT:
 510                 case MONO_TYPE_SZARRAY:
 511                 case MONO_TYPE_ARRAY:
 512                 case MONO_TYPE_STRING:
 513                         cinfo->ret.storage = ArgInIReg;
 514                         cinfo->ret.reg = AMD64_RAX;
 515                         break;
 516                 case MONO_TYPE_U8:
 517                 case MONO_TYPE_I8:
 518                         cinfo->ret.storage = ArgInIReg;
 519                         cinfo->ret.reg = AMD64_RAX;
 520                         break;
 521                 case MONO_TYPE_R4:
 522                         cinfo->ret.storage = ArgInFloatSSEReg;
 523                         cinfo->ret.reg = AMD64_XMM0;
 524                         break;
 525                 case MONO_TYPE_R8:
 526                         cinfo->ret.storage = ArgInDoubleSSEReg;
 527                         cinfo->ret.reg = AMD64_XMM0;
 528                         break;
 529                 case MONO_TYPE_GENERICINST:
 530                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 531                                 cinfo->ret.storage = ArgInIReg;
 532                                 cinfo->ret.reg = AMD64_RAX;
 533                                 break;
 534                         }
 535                         /* fall through */
 536                 case MONO_TYPE_VALUETYPE: {
 537                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 538
 539                         add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 540                         if (cinfo->ret.storage == ArgOnStack)
 541                                 /* The caller passes the address where the value is stored */
 542                                 add_general (&gr, &stack_size, &cinfo->ret);
 543                         break;
 544                 }
 545                 case MONO_TYPE_TYPEDBYREF:
 546                         /* Same as a valuetype with size 24 */
 547                         add_general (&gr, &stack_size, &cinfo->ret);
 548                         ;
 549                         break;
 550                 case MONO_TYPE_VOID:
 551                         break;
 552                 default:
 553                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 554                 }
 555         }
 556
 557         /* this */
 558         if (sig->hasthis)
 559                 add_general (&gr, &stack_size, cinfo->args + 0);
 560
 561         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 562                 gr = PARAM_REGS;
 563                 fr = FLOAT_PARAM_REGS;
 564
 565                 /* Emit the signature cookie just before the implicit arguments */
 566                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 567         }
 568
 569         for (i = 0; i < sig->param_count; ++i) {
 570                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 571                 MonoType *ptype;
 572
 573                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 574                         /* We allways pass the sig cookie on the stack for simplicity */
 575                         /*
 576                          * Prevent implicit arguments + the sig cookie from being passed
 577                          * in registers.
 578                          */
 579                         gr = PARAM_REGS;
 580                         fr = FLOAT_PARAM_REGS;
 581
 582                         /* Emit the signature cookie just before the implicit arguments */
 583                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 584                 }
 585
 586                 if (sig->params [i]->byref) {
 587                         add_general (&gr, &stack_size, ainfo);
 588                         continue;
 589                 }
 590                 ptype = mono_type_get_underlying_type (sig->params [i]);
 591                 switch (ptype->type) {
 592                 case MONO_TYPE_BOOLEAN:
 593                 case MONO_TYPE_I1:
 594                 case MONO_TYPE_U1:
 595                         add_general (&gr, &stack_size, ainfo);
 596                         break;
 597                 case MONO_TYPE_I2:
 598                 case MONO_TYPE_U2:
 599                 case MONO_TYPE_CHAR:
 600                         add_general (&gr, &stack_size, ainfo);
 601                         break;
 602                 case MONO_TYPE_I4:
 603                 case MONO_TYPE_U4:
 604                         add_general (&gr, &stack_size, ainfo);
 605                         break;
 606                 case MONO_TYPE_I:
 607                 case MONO_TYPE_U:
 608                 case MONO_TYPE_PTR:
 609                 case MONO_TYPE_FNPTR:
 610                 case MONO_TYPE_CLASS:
 611                 case MONO_TYPE_OBJECT:
 612                 case MONO_TYPE_STRING:
 613                 case MONO_TYPE_SZARRAY:
 614                 case MONO_TYPE_ARRAY:
 615                         add_general (&gr, &stack_size, ainfo);
 616                         break;
 617                 case MONO_TYPE_GENERICINST:
 618                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 619                                 add_general (&gr, &stack_size, ainfo);
 620                                 break;
 621                         }
 622                         /* fall through */
 623                 case MONO_TYPE_VALUETYPE:
 624                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 625                         break;
 626                 case MONO_TYPE_TYPEDBYREF:
 627                         stack_size += sizeof (MonoTypedRef);
 628                         ainfo->storage = ArgOnStack;
 629                         break;
 630                 case MONO_TYPE_U8:
 631                 case MONO_TYPE_I8:
 632                         add_general (&gr, &stack_size, ainfo);
 633                         break;
 634                 case MONO_TYPE_R4:
 635                         add_float (&fr, &stack_size, ainfo, FALSE);
 636                         break;
 637                 case MONO_TYPE_R8:
 638                         add_float (&fr, &stack_size, ainfo, TRUE);
 639                         break;
 640                 default:
 641                         g_assert_not_reached ();
 642                 }
 643         }
 644
 645         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 646                 gr = PARAM_REGS;
 647                 fr = FLOAT_PARAM_REGS;
 648
 649                 /* Emit the signature cookie just before the implicit arguments */
 650                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 651         }
 652
 653         if (stack_size & 0x8) {
 654                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 655                 cinfo->need_stack_align = TRUE;
 656                 stack_size += 8;
 657         }
 658
 659         cinfo->stack_usage = stack_size;
 660         cinfo->reg_usage = gr;
 661         cinfo->freg_usage = fr;
 662         return cinfo;
 663 }
 664
 665 /*
 666  * mono_arch_get_argument_info:
 667  * @csig:  a method signature
 668  * @param_count: the number of parameters to consider
 669  * @arg_info: an array to store the result infos
 670  *
 671  * Gathers information on parameters such as size, alignment and
 672  * padding. arg_info should be large enought to hold param_count + 1 entries.
 673  *
 674  * Returns the size of the argument area on the stack.
 675  */
 676 int
 677 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 678 {
 679         int k;
 680         CallInfo *cinfo = get_call_info (csig, FALSE);
 681         guint32 args_size = cinfo->stack_usage;
 682
 683         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 684         if (csig->hasthis) {
 685                 arg_info [0].offset = 0;
 686         }
 687
 688         for (k = 0; k < param_count; k++) {
 689                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 690                 /* FIXME: */
 691                 arg_info [k + 1].size = 0;
 692         }
 693
 694         g_free (cinfo);
 695
 696         return args_size;
 697 }
 698
 699 static int
 700 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 701 {
 702         return 0;
 703 }
 704
 705 /*
 706  * Initialize the cpu to execute managed code.
 707  */
 708 void
 709 mono_arch_cpu_init (void)
 710 {
 711         guint16 fpcw;
 712
 713         /* spec compliance requires running with double precision */
 714         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 715         fpcw &= ~X86_FPCW_PRECC_MASK;
 716         fpcw |= X86_FPCW_PREC_DOUBLE;
 717         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 718         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 719 }
 720
 721 /*
 722  * This function returns the optimizations supported on this cpu.
 723  */
 724 guint32
 725 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 726 {
 727         int eax, ebx, ecx, edx;
 728         guint32 opts = 0;
 729
 730         /* FIXME: AMD64 */
 731
 732         *exclude_mask = 0;
 733         /* Feature Flags function, flags returned in EDX. */
 734         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 735                 if (edx & (1 << 15)) {
 736                         opts |= MONO_OPT_CMOV;
 737                         if (edx & 1)
 738                                 opts |= MONO_OPT_FCMOV;
 739                         else
 740                                 *exclude_mask |= MONO_OPT_FCMOV;
 741                 } else
 742                         *exclude_mask |= MONO_OPT_CMOV;
 743         }
 744         return opts;
 745 }
 746
 747 gboolean
 748 mono_amd64_is_sse2 (void)
 749 {
 750         return use_sse2;
 751 }
 752
 753 static gboolean
 754 is_regsize_var (MonoType *t) {
 755         if (t->byref)
 756                 return TRUE;
 757         t = mono_type_get_underlying_type (t);
 758         switch (t->type) {
 759         case MONO_TYPE_I4:
 760         case MONO_TYPE_U4:
 761         case MONO_TYPE_I:
 762         case MONO_TYPE_U:
 763         case MONO_TYPE_PTR:
 764         case MONO_TYPE_FNPTR:
 765                 return TRUE;
 766         case MONO_TYPE_OBJECT:
 767         case MONO_TYPE_STRING:
 768         case MONO_TYPE_CLASS:
 769         case MONO_TYPE_SZARRAY:
 770         case MONO_TYPE_ARRAY:
 771                 return TRUE;
 772         case MONO_TYPE_GENERICINST:
 773                 if (!mono_type_generic_inst_is_valuetype (t))
 774                         return TRUE;
 775                 return FALSE;
 776         case MONO_TYPE_VALUETYPE:
 777                 return FALSE;
 778         }
 779         return FALSE;
 780 }
 781
 782 GList *
 783 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 784 {
 785         GList *vars = NULL;
 786         int i;
 787
 788         for (i = 0; i < cfg->num_varinfo; i++) {
 789                 MonoInst *ins = cfg->varinfo [i];
 790                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 791
 792                 /* unused vars */
 793                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 794                         continue;
 795
 796                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 797                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 798                         continue;
 799
 800                 /* we dont allocate I1 to registers because there is no simply way to sign extend
 801                  * 8bit quantities in caller saved registers on x86 */
 802                 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
 803                     (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
 804                     (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
 805                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 806                         g_assert (i == vmv->idx);
 807                         vars = g_list_prepend (vars, vmv);
 808                 }
 809         }
 810
 811         vars = mono_varlist_sort (cfg, vars, 0);
 812
 813         return vars;
 814 }
 815
 816 /**
 817  * mono_arch_compute_omit_fp:
 818  *
 819  *   Determine whenever the frame pointer can be eliminated.
 820  */
 821 static void
 822 mono_arch_compute_omit_fp (MonoCompile *cfg)
 823 {
 824         MonoMethodSignature *sig;
 825         MonoMethodHeader *header;
 826         int i;
 827         CallInfo *cinfo;
 828
 829         if (cfg->arch.omit_fp_computed)
 830                 return;
 831
 832         header = mono_method_get_header (cfg->method);
 833
 834         sig = mono_method_signature (cfg->method);
 835
 836         cinfo = get_call_info (sig, FALSE);
 837
 838         /*
 839          * FIXME: Remove some of the restrictions.
 840          */
 841         cfg->arch.omit_fp = TRUE;
 842         cfg->arch.omit_fp_computed = TRUE;
 843
 844         /* Temporarily disable this when running in the debugger until we have support
 845          * for this in the debugger. */
 846         if (mono_debug_using_mono_debugger ())
 847                 cfg->arch.omit_fp = FALSE;
 848
 849         if (!debug_omit_fp ())
 850                 cfg->arch.omit_fp = FALSE;
 851         /*
 852         if (cfg->method->save_lmf)
 853                 cfg->arch.omit_fp = FALSE;
 854         */
 855         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 856                 cfg->arch.omit_fp = FALSE;
 857         if (header->num_clauses)
 858                 cfg->arch.omit_fp = FALSE;
 859         if (cfg->param_area)
 860                 cfg->arch.omit_fp = FALSE;
 861         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 862                 cfg->arch.omit_fp = FALSE;
 863         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 864                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 865                 cfg->arch.omit_fp = FALSE;
 866         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 867                 ArgInfo *ainfo = &cinfo->args [i];
 868
 869                 if (ainfo->storage == ArgOnStack) {
 870                         /*
 871                          * The stack offset can only be determined when the frame
 872                          * size is known.
 873                          */
 874                         cfg->arch.omit_fp = FALSE;
 875                 }
 876         }
 877
 878         if (cfg->num_varinfo > 10000) {
 879                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
 880                 cfg->arch.omit_fp = FALSE;
 881         }
 882
 883         g_free (cinfo);
 884 }
 885
 886 GList *
 887 mono_arch_get_global_int_regs (MonoCompile *cfg)
 888 {
 889         GList *regs = NULL;
 890
 891         mono_arch_compute_omit_fp (cfg);
 892
 893         if (cfg->arch.omit_fp)
 894                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
 895
 896         /* We use the callee saved registers for global allocation */
 897         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 898         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 899         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 900         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 901         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 902
 903         return regs;
 904 }
 905
 906 /*
 907  * mono_arch_regalloc_cost:
 908  *
 909  *  Return the cost, in number of memory references, of the action of
 910  * allocating the variable VMV into a register during global register
 911  * allocation.
 912  */
 913 guint32
 914 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 915 {
 916         MonoInst *ins = cfg->varinfo [vmv->idx];
 917
 918         if (cfg->method->save_lmf)
 919                 /* The register is already saved */
 920                 /* substract 1 for the invisible store in the prolog */
 921                 return (ins->opcode == OP_ARG) ? 0 : 1;
 922         else
 923                 /* push+pop */
 924                 return (ins->opcode == OP_ARG) ? 1 : 2;
 925 }
 926
 927 void
 928 mono_arch_allocate_vars (MonoCompile *cfg)
 929 {
 930         MonoMethodSignature *sig;
 931         MonoMethodHeader *header;
 932         MonoInst *inst;
 933         int i, offset;
 934         guint32 locals_stack_size, locals_stack_align;
 935         gint32 *offsets;
 936         CallInfo *cinfo;
 937
 938         header = mono_method_get_header (cfg->method);
 939
 940         sig = mono_method_signature (cfg->method);
 941
 942         cinfo = get_call_info (sig, FALSE);
 943
 944         mono_arch_compute_omit_fp (cfg);
 945
 946         /*
 947          * We use the ABI calling conventions for managed code as well.
 948          * Exception: valuetypes are never passed or returned in registers.
 949          */
 950
 951         if (cfg->arch.omit_fp) {
 952                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 953                 cfg->frame_reg = AMD64_RSP;
 954                 offset = 0;
 955         } else {
 956                 /* Locals are allocated backwards from %fp */
 957                 cfg->frame_reg = AMD64_RBP;
 958                 offset = 0;
 959         }
 960
 961         cfg->arch.reg_save_area_offset = offset;
 962
 963         /* Reserve space for caller saved registers */
 964         for (i = 0; i < AMD64_NREG; ++i)
 965                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
 966                         offset += sizeof (gpointer);
 967                 }
 968
 969         if (cfg->method->save_lmf) {
 970                 /* Reserve stack space for saving LMF + argument regs */
 971                 guint32 size = sizeof (MonoLMF);
 972
 973                 if (lmf_tls_offset == -1)
 974                         /* Need to save argument regs too */
 975                         size += (AMD64_NREG * 8) + (8 * 8);
 976
 977                 if (cfg->arch.omit_fp) {
 978                         cfg->arch.lmf_offset = offset;
 979                         offset += size;
 980                 }
 981                 else {
 982                         offset += size;
 983                         cfg->arch.lmf_offset = -offset;
 984                 }
 985         }
 986
 987         if (sig->ret->type != MONO_TYPE_VOID) {
 988                 switch (cinfo->ret.storage) {
 989                 case ArgInIReg:
 990                 case ArgInFloatSSEReg:
 991                 case ArgInDoubleSSEReg:
 992                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
 993                                 /* The register is volatile */
 994                                 cfg->ret->opcode = OP_REGOFFSET;
 995                                 cfg->ret->inst_basereg = cfg->frame_reg;
 996                                 if (cfg->arch.omit_fp) {
 997                                         cfg->ret->inst_offset = offset;
 998                                         offset += 8;
 999                                 } else {
1000                                         offset += 8;
1001                                         cfg->ret->inst_offset = -offset;
1002                                 }
1003                         }
1004                         else {
1005                                 cfg->ret->opcode = OP_REGVAR;
1006                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1007                         }
1008                         break;
1009                 case ArgValuetypeInReg:
1010                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1011                         g_assert (!cfg->arch.omit_fp);
1012                         offset += 16;
1013                         cfg->ret->opcode = OP_REGOFFSET;
1014                         cfg->ret->inst_basereg = cfg->frame_reg;
1015                         cfg->ret->inst_offset = - offset;
1016                         break;
1017                 default:
1018                         g_assert_not_reached ();
1019                 }
1020                 cfg->ret->dreg = cfg->ret->inst_c0;
1021         }
1022
1023         /* Allocate locals */
1024         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1025         if (locals_stack_align) {
1026                 offset += (locals_stack_align - 1);
1027                 offset &= ~(locals_stack_align - 1);
1028         }
1029         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1030                 if (offsets [i] != -1) {
1031                         MonoInst *inst = cfg->varinfo [i];
1032                         inst->opcode = OP_REGOFFSET;
1033                         inst->inst_basereg = cfg->frame_reg;
1034                         if (cfg->arch.omit_fp)
1035                                 inst->inst_offset = (offset + offsets [i]);
1036                         else
1037                                 inst->inst_offset = - (offset + offsets [i]);
1038                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1039                 }
1040         }
1041         g_free (offsets);
1042         offset += locals_stack_size;
1043
1044         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1045                 g_assert (!cfg->arch.omit_fp);
1046                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1047                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1048         }
1049
1050         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1051                 inst = cfg->varinfo [i];
1052                 if (inst->opcode != OP_REGVAR) {
1053                         ArgInfo *ainfo = &cinfo->args [i];
1054                         gboolean inreg = TRUE;
1055                         MonoType *arg_type;
1056
1057                         if (sig->hasthis && (i == 0))
1058                                 arg_type = &mono_defaults.object_class->byval_arg;
1059                         else
1060                                 arg_type = sig->params [i - sig->hasthis];
1061
1062                         /* FIXME: Allocate volatile arguments to registers */
1063                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1064                                 inreg = FALSE;
1065
1066                         /*
1067                          * Under AMD64, all registers used to pass arguments to functions
1068                          * are volatile across calls.
1069                          * FIXME: Optimize this.
1070                          */
1071                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1072                                 inreg = FALSE;
1073
1074                         inst->opcode = OP_REGOFFSET;
1075
1076                         switch (ainfo->storage) {
1077                         case ArgInIReg:
1078                         case ArgInFloatSSEReg:
1079                         case ArgInDoubleSSEReg:
1080                                 inst->opcode = OP_REGVAR;
1081                                 inst->dreg = ainfo->reg;
1082                                 break;
1083                         case ArgOnStack:
1084                                 g_assert (!cfg->arch.omit_fp);
1085                                 inst->opcode = OP_REGOFFSET;
1086                                 inst->inst_basereg = cfg->frame_reg;
1087                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1088                                 break;
1089                         case ArgValuetypeInReg:
1090                                 break;
1091                         default:
1092                                 NOT_IMPLEMENTED;
1093                         }
1094
1095                         if (!inreg && (ainfo->storage != ArgOnStack)) {
1096                                 inst->opcode = OP_REGOFFSET;
1097                                 inst->inst_basereg = cfg->frame_reg;
1098                                 /* These arguments are saved to the stack in the prolog */
1099                                 if (cfg->arch.omit_fp) {
1100                                         inst->inst_offset = offset;
1101                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1102                                 } else {
1103                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1104                                         inst->inst_offset = - offset;
1105                                 }
1106                         }
1107                 }
1108         }
1109
1110         cfg->stack_offset = offset;
1111
1112         g_free (cinfo);
1113 }
1114
1115 void
1116 mono_arch_create_vars (MonoCompile *cfg)
1117 {
1118         MonoMethodSignature *sig;
1119         CallInfo *cinfo;
1120
1121         sig = mono_method_signature (cfg->method);
1122
1123         cinfo = get_call_info (sig, FALSE);
1124
1125         if (cinfo->ret.storage == ArgValuetypeInReg)
1126                 cfg->ret_var_is_local = TRUE;
1127
1128         g_free (cinfo);
1129 }
1130
1131 static void
1132 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1133 {
1134         switch (storage) {
1135         case ArgInIReg:
1136                 arg->opcode = OP_OUTARG_REG;
1137                 arg->inst_left = tree;
1138                 arg->inst_right = (MonoInst*)call;
1139                 arg->unused = reg;
1140                 break;
1141         case ArgInFloatSSEReg:
1142                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1143                 arg->inst_left = tree;
1144                 arg->inst_right = (MonoInst*)call;
1145                 arg->unused = reg;
1146                 break;
1147         case ArgInDoubleSSEReg:
1148                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1149                 arg->inst_left = tree;
1150                 arg->inst_right = (MonoInst*)call;
1151                 arg->unused = reg;
1152                 break;
1153         default:
1154                 g_assert_not_reached ();
1155         }
1156 }
1157
1158 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1159  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1160  */
1161
1162 static int
1163 arg_storage_to_ldind (ArgStorage storage)
1164 {
1165         switch (storage) {
1166         case ArgInIReg:
1167                 return CEE_LDIND_I;
1168         case ArgInDoubleSSEReg:
1169                 return CEE_LDIND_R8;
1170         case ArgInFloatSSEReg:
1171                 return CEE_LDIND_R4;
1172         default:
1173                 g_assert_not_reached ();
1174         }
1175
1176         return -1;
1177 }
1178
1179 /*
1180  * take the arguments and generate the arch-specific
1181  * instructions to properly call the function in call.
1182  * This includes pushing, moving arguments to the right register
1183  * etc.
1184  * Issue: who does the spilling if needed, and when?
1185  */
1186 MonoCallInst*
1187 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1188         MonoInst *arg, *in;
1189         MonoMethodSignature *sig;
1190         int i, n, stack_size;
1191         CallInfo *cinfo;
1192         ArgInfo *ainfo;
1193
1194         stack_size = 0;
1195
1196         sig = call->signature;
1197         n = sig->param_count + sig->hasthis;
1198
1199         cinfo = get_call_info (sig, sig->pinvoke);
1200
1201         for (i = 0; i < n; ++i) {
1202                 ainfo = cinfo->args + i;
1203
1204                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1205                         MonoMethodSignature *tmp_sig;
1206
1207                         /* Emit the signature cookie just before the implicit arguments */
1208                         MonoInst *sig_arg;
1209                         /* FIXME: Add support for signature tokens to AOT */
1210                         cfg->disable_aot = TRUE;
1211
1212                         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1213
1214                         /*
1215                          * mono_ArgIterator_Setup assumes the signature cookie is
1216                          * passed first and all the arguments which were before it are
1217                          * passed on the stack after the signature. So compensate by
1218                          * passing a different signature.
1219                          */
1220                         tmp_sig = mono_metadata_signature_dup (call->signature);
1221                         tmp_sig->param_count -= call->signature->sentinelpos;
1222                         tmp_sig->sentinelpos = 0;
1223                         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1224
1225                         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1226                         sig_arg->inst_p0 = tmp_sig;
1227
1228                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1229                         arg->inst_left = sig_arg;
1230                         arg->type = STACK_PTR;
1231
1232                         /* prepend, so they get reversed */
1233                         arg->next = call->out_args;
1234                         call->out_args = arg;
1235                 }
1236
1237                 if (is_virtual && i == 0) {
1238                         /* the argument will be attached to the call instruction */
1239                         in = call->args [i];
1240                 } else {
1241                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1242                         in = call->args [i];
1243                         arg->cil_code = in->cil_code;
1244                         arg->inst_left = in;
1245                         arg->type = in->type;
1246                         /* prepend, so they get reversed */
1247                         arg->next = call->out_args;
1248                         call->out_args = arg;
1249
1250                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1251                                 guint32 align;
1252                                 guint32 size;
1253
1254                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1255                                         size = sizeof (MonoTypedRef);
1256                                         align = sizeof (gpointer);
1257                                 }
1258                                 else
1259                                 if (sig->pinvoke)
1260                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1261                                 else {
1262                                         /*
1263                                          * Other backends use mono_type_stack_size (), but that
1264                                          * aligns the size to 8, which is larger than the size of
1265                                          * the source, leading to reads of invalid memory if the
1266                                          * source is at the end of address space.
1267                                          */
1268                                         size = mono_class_value_size (in->klass, &align);
1269                                 }
1270                                 if (ainfo->storage == ArgValuetypeInReg) {
1271                                         if (ainfo->pair_storage [1] == ArgNone) {
1272                                                 MonoInst *load;
1273
1274                                                 /* Simpler case */
1275
1276                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1277                                                 load->inst_left = in;
1278
1279                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1280                                         }
1281                                         else {
1282                                                 /* Trees can't be shared so make a copy */
1283                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1284                                                 MonoInst *load, *load2, *offset_ins;
1285
1286                                                 /* Reg1 */
1287                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1288                                                 load->ssa_op = MONO_SSA_LOAD;
1289                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1290
1291                                                 NEW_ICONST (cfg, offset_ins, 0);
1292                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1293                                                 load2->inst_left = load;
1294                                                 load2->inst_right = offset_ins;
1295
1296                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1297                                                 load->inst_left = load2;
1298
1299                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1300
1301                                                 /* Reg2 */
1302                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1303                                                 load->ssa_op = MONO_SSA_LOAD;
1304                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1305
1306                                                 NEW_ICONST (cfg, offset_ins, 8);
1307                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1308                                                 load2->inst_left = load;
1309                                                 load2->inst_right = offset_ins;
1310
1311                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1312                                                 load->inst_left = load2;
1313
1314                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1315                                                 arg->cil_code = in->cil_code;
1316                                                 arg->type = in->type;
1317                                                 /* prepend, so they get reversed */
1318                                                 arg->next = call->out_args;
1319                                                 call->out_args = arg;
1320
1321                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1322
1323                                                 /* Prepend a copy inst */
1324                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1325                                                 arg->cil_code = in->cil_code;
1326                                                 arg->ssa_op = MONO_SSA_STORE;
1327                                                 arg->inst_left = vtaddr;
1328                                                 arg->inst_right = in;
1329                                                 arg->type = in->type;
1330
1331                                                 /* prepend, so they get reversed */
1332                                                 arg->next = call->out_args;
1333                                                 call->out_args = arg;
1334                                         }
1335                                 }
1336                                 else {
1337                                         arg->opcode = OP_OUTARG_VT;
1338                                         arg->klass = in->klass;
1339                                         arg->unused = sig->pinvoke;
1340                                         arg->inst_imm = size;
1341                                 }
1342                         }
1343                         else {
1344                                 switch (ainfo->storage) {
1345                                 case ArgInIReg:
1346                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1347                                         break;
1348                                 case ArgInFloatSSEReg:
1349                                 case ArgInDoubleSSEReg:
1350                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1351                                         break;
1352                                 case ArgOnStack:
1353                                         arg->opcode = OP_OUTARG;
1354                                         if (!sig->params [i - sig->hasthis]->byref) {
1355                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1356                                                         arg->opcode = OP_OUTARG_R4;
1357                                                 else
1358                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1359                                                                 arg->opcode = OP_OUTARG_R8;
1360                                         }
1361                                         break;
1362                                 default:
1363                                         g_assert_not_reached ();
1364                                 }
1365                         }
1366                 }
1367         }
1368
1369         if (cinfo->need_stack_align) {
1370                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1371                 /* prepend, so they get reversed */
1372                 arg->next = call->out_args;
1373                 call->out_args = arg;
1374         }
1375
1376         call->stack_usage = cinfo->stack_usage;
1377         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1378         cfg->flags |= MONO_CFG_HAS_CALLS;
1379
1380         g_free (cinfo);
1381
1382         return call;
1383 }
1384
1385 #define EMIT_COND_BRANCH(ins,cond,sign) \
1386 if (ins->flags & MONO_INST_BRLABEL) { \
1387         if (ins->inst_i0->inst_c0) { \
1388                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1389         } else { \
1390                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1391                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1392                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1393                         x86_branch8 (code, cond, 0, sign); \
1394                 else \
1395                         x86_branch32 (code, cond, 0, sign); \
1396         } \
1397 } else { \
1398         if (ins->inst_true_bb->native_offset) { \
1399                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1400         } else { \
1401                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1402                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1403                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1404                         x86_branch8 (code, cond, 0, sign); \
1405                 else \
1406                         x86_branch32 (code, cond, 0, sign); \
1407         } \
1408 }
1409
1410 /* emit an exception if condition is fail */
1411 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1412         do {                                                        \
1413                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1414                 if (tins == NULL) {                                                                             \
1415                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1416                                         MONO_PATCH_INFO_EXC, exc_name);  \
1417                         x86_branch32 (code, cond, 0, signed);               \
1418                 } else {        \
1419                         EMIT_COND_BRANCH (tins, cond, signed);  \
1420                 }                       \
1421         } while (0);
1422
1423 #define EMIT_FPCOMPARE(code) do { \
1424         amd64_fcompp (code); \
1425         amd64_fnstsw (code); \
1426 } while (0);
1427
1428 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1429     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1430         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1431         amd64_ ##op (code); \
1432         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1433         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1434 } while (0);
1435
1436 static guint8*
1437 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1438 {
1439         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1440
1441         if (cfg->compile_aot) {
1442                 amd64_call_membase (code, AMD64_RIP, 0);
1443         }
1444         else {
1445                 gboolean near_call = FALSE;
1446
1447                 /*
1448                  * Indirect calls are expensive so try to make a near call if possible.
1449                  * The caller memory is allocated by the code manager so it is
1450                  * guaranteed to be at a 32 bit offset.
1451                  */
1452
1453                 if (patch_type != MONO_PATCH_INFO_ABS) {
1454                         /* The target is in memory allocated using the code manager */
1455                         near_call = TRUE;
1456
1457                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1458                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1459                                         /* The callee might be an AOT method */
1460                                         near_call = FALSE;
1461                         }
1462
1463                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1464                                 /*
1465                                  * The call might go directly to a native function without
1466                                  * the wrapper.
1467                                  */
1468                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1469                                 if (mi) {
1470                                         gconstpointer target = mono_icall_get_wrapper (mi);
1471                                         if ((((guint64)target) >> 32) != 0)
1472                                                 near_call = FALSE;
1473                                 }
1474                         }
1475                 }
1476                 else {
1477                         if (mono_find_class_init_trampoline_by_addr (data))
1478                                 near_call = TRUE;
1479                         else {
1480                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1481                                 if (info) {
1482                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1483                                                 strstr (cfg->method->name, info->name)) {
1484                                                 /* A call to the wrapped function */
1485                                                 if ((((guint64)data) >> 32) == 0)
1486                                                         near_call = TRUE;
1487                                         }
1488                                         else if (info->func == info->wrapper) {
1489                                                 /* No wrapper */
1490                                                 if ((((guint64)info->func) >> 32) == 0)
1491                                                         near_call = TRUE;
1492                                         }
1493                                         else
1494                                                 near_call = TRUE;
1495                                 }
1496                                 else if ((((guint64)data) >> 32) == 0)
1497                                         near_call = TRUE;
1498                         }
1499                 }
1500
1501                 if (cfg->method->dynamic)
1502                         /* These methods are allocated using malloc */
1503                         near_call = FALSE;
1504
1505                 if (near_call) {
1506                         amd64_call_code (code, 0);
1507                 }
1508                 else {
1509                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1510                         amd64_call_reg (code, GP_SCRATCH_REG);
1511                 }
1512         }
1513
1514         return code;
1515 }
1516
1517 /* FIXME: Add more instructions */
1518 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM) || ((ins)->opcode == OP_STOREI8_MEMBASE_REG) || ((ins)->opcode == OP_MOVE) || ((ins)->opcode == OP_ICONST) || ((ins)->opcode == OP_I8CONST) || ((ins)->opcode == OP_LOAD_MEMBASE))
1519
1520 static void
1521 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1522 {
1523         MonoInst *ins, *last_ins = NULL;
1524         ins = bb->code;
1525
1526         while (ins) {
1527
1528                 switch (ins->opcode) {
1529                 case OP_ICONST:
1530                 case OP_I8CONST:
1531                         /* reg = 0 -> XOR (reg, reg) */
1532                         /* XOR sets cflags on x86, so we cant do it always */
1533                         if (ins->inst_c0 == 0 && (ins->next && INST_IGNORES_CFLAGS (ins->next))) {
1534                                 ins->opcode = CEE_XOR;
1535                                 ins->sreg1 = ins->dreg;
1536                                 ins->sreg2 = ins->dreg;
1537                         }
1538                         break;
1539                 case OP_MUL_IMM:
1540                         /* remove unnecessary multiplication with 1 */
1541                         if (ins->inst_imm == 1) {
1542                                 if (ins->dreg != ins->sreg1) {
1543                                         ins->opcode = OP_MOVE;
1544                                 } else {
1545                                         last_ins->next = ins->next;
1546                                         ins = ins->next;
1547                                         continue;
1548                                 }
1549                         }
1550                         break;
1551                 case OP_COMPARE_IMM:
1552                         /* OP_COMPARE_IMM (reg, 0)
1553                          * -->
1554                          * OP_AMD64_TEST_NULL (reg)
1555                          */
1556                         if (!ins->inst_imm)
1557                                 ins->opcode = OP_AMD64_TEST_NULL;
1558                         break;
1559                 case OP_ICOMPARE_IMM:
1560                         if (!ins->inst_imm)
1561                                 ins->opcode = OP_X86_TEST_NULL;
1562                         break;
1563                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1564                         /*
1565                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1566                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1567                          * -->
1568                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1569                          * OP_COMPARE_IMM reg, imm
1570                          *
1571                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1572                          */
1573                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1574                             ins->inst_basereg == last_ins->inst_destbasereg &&
1575                             ins->inst_offset == last_ins->inst_offset) {
1576                                         ins->opcode = OP_ICOMPARE_IMM;
1577                                         ins->sreg1 = last_ins->sreg1;
1578
1579                                         /* check if we can remove cmp reg,0 with test null */
1580                                         if (!ins->inst_imm)
1581                                                 ins->opcode = OP_X86_TEST_NULL;
1582                                 }
1583
1584                         break;
1585                 case OP_LOAD_MEMBASE:
1586                 case OP_LOADI4_MEMBASE:
1587                         /*
1588                          * Note: if reg1 = reg2 the load op is removed
1589                          *
1590                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1591                          * OP_LOAD_MEMBASE offset(basereg), reg2
1592                          * -->
1593                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1594                          * OP_MOVE reg1, reg2
1595                          */
1596                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1597                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1598                             ins->inst_basereg == last_ins->inst_destbasereg &&
1599                             ins->inst_offset == last_ins->inst_offset) {
1600                                 if (ins->dreg == last_ins->sreg1) {
1601                                         last_ins->next = ins->next;
1602                                         ins = ins->next;
1603                                         continue;
1604                                 } else {
1605                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1606                                         ins->opcode = OP_MOVE;
1607                                         ins->sreg1 = last_ins->sreg1;
1608                                 }
1609
1610                         /*
1611                          * Note: reg1 must be different from the basereg in the second load
1612                          * Note: if reg1 = reg2 is equal then second load is removed
1613                          *
1614                          * OP_LOAD_MEMBASE offset(basereg), reg1
1615                          * OP_LOAD_MEMBASE offset(basereg), reg2
1616                          * -->
1617                          * OP_LOAD_MEMBASE offset(basereg), reg1
1618                          * OP_MOVE reg1, reg2
1619                          */
1620                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1621                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1622                               ins->inst_basereg != last_ins->dreg &&
1623                               ins->inst_basereg == last_ins->inst_basereg &&
1624                               ins->inst_offset == last_ins->inst_offset) {
1625
1626                                 if (ins->dreg == last_ins->dreg) {
1627                                         last_ins->next = ins->next;
1628                                         ins = ins->next;
1629                                         continue;
1630                                 } else {
1631                                         ins->opcode = OP_MOVE;
1632                                         ins->sreg1 = last_ins->dreg;
1633                                 }
1634
1635                                 //g_assert_not_reached ();
1636
1637 #if 0
1638                         /*
1639                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1640                          * OP_LOAD_MEMBASE offset(basereg), reg
1641                          * -->
1642                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1643                          * OP_ICONST reg, imm
1644                          */
1645                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1646                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1647                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1648                                    ins->inst_offset == last_ins->inst_offset) {
1649                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1650                                 ins->opcode = OP_ICONST;
1651                                 ins->inst_c0 = last_ins->inst_imm;
1652                                 g_assert_not_reached (); // check this rule
1653 #endif
1654                         }
1655                         break;
1656                 case OP_LOADU1_MEMBASE:
1657                 case OP_LOADI1_MEMBASE:
1658                         /*
1659                          * Note: if reg1 = reg2 the load op is removed
1660                          *
1661                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1662                          * OP_LOAD_MEMBASE offset(basereg), reg2
1663                          * -->
1664                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1665                          * OP_MOVE reg1, reg2
1666                          */
1667                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1668                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1669                                         ins->inst_offset == last_ins->inst_offset) {
1670                                 if (ins->dreg == last_ins->sreg1) {
1671                                         last_ins->next = ins->next;
1672                                         ins = ins->next;
1673                                         continue;
1674                                 } else {
1675                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1676                                         ins->opcode = OP_MOVE;
1677                                         ins->sreg1 = last_ins->sreg1;
1678                                 }
1679                         }
1680                         break;
1681                 case OP_LOADU2_MEMBASE:
1682                 case OP_LOADI2_MEMBASE:
1683                         /*
1684                          * Note: if reg1 = reg2 the load op is removed
1685                          *
1686                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1687                          * OP_LOAD_MEMBASE offset(basereg), reg2
1688                          * -->
1689                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1690                          * OP_MOVE reg1, reg2
1691                          */
1692                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1693                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1694                                         ins->inst_offset == last_ins->inst_offset) {
1695                                 if (ins->dreg == last_ins->sreg1) {
1696                                         last_ins->next = ins->next;
1697                                         ins = ins->next;
1698                                         continue;
1699                                 } else {
1700                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1701                                         ins->opcode = OP_MOVE;
1702                                         ins->sreg1 = last_ins->sreg1;
1703                                 }
1704                         }
1705                         break;
1706                 case CEE_CONV_I4:
1707                 case CEE_CONV_U4:
1708                 case OP_MOVE:
1709                         /*
1710                          * Removes:
1711                          *
1712                          * OP_MOVE reg, reg
1713                          */
1714                         if (ins->dreg == ins->sreg1) {
1715                                 if (last_ins)
1716                                         last_ins->next = ins->next;
1717                                 ins = ins->next;
1718                                 continue;
1719                         }
1720                         /*
1721                          * Removes:
1722                          *
1723                          * OP_MOVE sreg, dreg
1724                          * OP_MOVE dreg, sreg
1725                          */
1726                         if (last_ins && last_ins->opcode == OP_MOVE &&
1727                             ins->sreg1 == last_ins->dreg &&
1728                             ins->dreg == last_ins->sreg1) {
1729                                 last_ins->next = ins->next;
1730                                 ins = ins->next;
1731                                 continue;
1732                         }
1733                         break;
1734                 }
1735                 last_ins = ins;
1736                 ins = ins->next;
1737         }
1738         bb->last_ins = last_ins;
1739 }
1740
1741 static void
1742 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1743 {
1744         if (ins == NULL) {
1745                 ins = bb->code;
1746                 bb->code = to_insert;
1747                 to_insert->next = ins;
1748         }
1749         else {
1750                 to_insert->next = ins->next;
1751                 ins->next = to_insert;
1752         }
1753 }
1754
1755 #define NEW_INS(cfg,dest,op) do {       \
1756                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1757                 (dest)->opcode = (op);  \
1758         insert_after_ins (bb, last_ins, (dest)); \
1759         } while (0)
1760
1761 /*
1762  * mono_arch_lowering_pass:
1763  *
1764  *  Converts complex opcodes into simpler ones so that each IR instruction
1765  * corresponds to one machine instruction.
1766  */
1767 static void
1768 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1769 {
1770         MonoInst *ins, *temp, *last_ins = NULL;
1771         ins = bb->code;
1772
1773         if (bb->max_ireg > cfg->rs->next_vireg)
1774                 cfg->rs->next_vireg = bb->max_ireg;
1775         if (bb->max_freg > cfg->rs->next_vfreg)
1776                 cfg->rs->next_vfreg = bb->max_freg;
1777
1778         /*
1779          * FIXME: Need to add more instructions, but the current machine
1780          * description can't model some parts of the composite instructions like
1781          * cdq.
1782          */
1783         while (ins) {
1784                 switch (ins->opcode) {
1785                 case OP_DIV_IMM:
1786                 case OP_REM_IMM:
1787                 case OP_IDIV_IMM:
1788                 case OP_IREM_IMM:
1789                         NEW_INS (cfg, temp, OP_ICONST);
1790                         temp->inst_c0 = ins->inst_imm;
1791                         temp->dreg = mono_regstate_next_int (cfg->rs);
1792                         switch (ins->opcode) {
1793                         case OP_DIV_IMM:
1794                                 ins->opcode = OP_LDIV;
1795                                 break;
1796                         case OP_REM_IMM:
1797                                 ins->opcode = OP_LREM;
1798                                 break;
1799                         case OP_IDIV_IMM:
1800                                 ins->opcode = OP_IDIV;
1801                                 break;
1802                         case OP_IREM_IMM:
1803                                 ins->opcode = OP_IREM;
1804                                 break;
1805                         }
1806                         ins->sreg2 = temp->dreg;
1807                         break;
1808                 case OP_COMPARE_IMM:
1809                         if (!amd64_is_imm32 (ins->inst_imm)) {
1810                                 NEW_INS (cfg, temp, OP_I8CONST);
1811                                 temp->inst_c0 = ins->inst_imm;
1812                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1813                                 ins->opcode = OP_COMPARE;
1814                                 ins->sreg2 = temp->dreg;
1815                         }
1816                         break;
1817                 case OP_LOAD_MEMBASE:
1818                 case OP_LOADI8_MEMBASE:
1819                         if (!amd64_is_imm32 (ins->inst_offset)) {
1820                                 NEW_INS (cfg, temp, OP_I8CONST);
1821                                 temp->inst_c0 = ins->inst_offset;
1822                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1823                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
1824                                 ins->inst_indexreg = temp->dreg;
1825                         }
1826                         break;
1827                 case OP_STORE_MEMBASE_IMM:
1828                 case OP_STOREI8_MEMBASE_IMM:
1829                         if (!amd64_is_imm32 (ins->inst_imm)) {
1830                                 NEW_INS (cfg, temp, OP_I8CONST);
1831                                 temp->inst_c0 = ins->inst_imm;
1832                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1833                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1834                                 ins->sreg1 = temp->dreg;
1835                         }
1836                         break;
1837                 default:
1838                         break;
1839                 }
1840                 last_ins = ins;
1841                 ins = ins->next;
1842         }
1843         bb->last_ins = last_ins;
1844
1845         bb->max_ireg = cfg->rs->next_vireg;
1846         bb->max_freg = cfg->rs->next_vfreg;
1847 }
1848
1849 static const int
1850 branch_cc_table [] = {
1851         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1852         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1853         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1854 };
1855
1856 static int
1857 opcode_to_x86_cond (int opcode)
1858 {
1859         switch (opcode) {
1860         case OP_IBEQ:
1861                 return X86_CC_EQ;
1862         case OP_IBNE_UN:
1863                 return X86_CC_NE;
1864         case OP_IBLT:
1865                 return X86_CC_LT;
1866         case OP_IBLT_UN:
1867                 return X86_CC_LT;
1868         case OP_IBGT:
1869                 return X86_CC_GT;
1870         case OP_IBGT_UN:
1871                 return X86_CC_GT;
1872         case OP_IBGE:
1873                 return X86_CC_GE;
1874         case OP_IBGE_UN:
1875                 return X86_CC_GE;
1876         case OP_IBLE:
1877                 return X86_CC_LE;
1878         case OP_IBLE_UN:
1879                 return X86_CC_LE;
1880         case OP_COND_EXC_IOV:
1881                 return X86_CC_O;
1882         case OP_COND_EXC_IC:
1883                 return X86_CC_C;
1884         default:
1885                 g_assert_not_reached ();
1886         }
1887
1888         return -1;
1889 }
1890
1891 /*#include "cprop.c"*/
1892
1893 /*
1894  * Local register allocation.
1895  * We first scan the list of instructions and we save the liveness info of
1896  * each register (when the register is first used, when it's value is set etc.).
1897  * We also reverse the list of instructions (in the InstList list) because assigning
1898  * registers backwards allows for more tricks to be used.
1899  */
1900 void
1901 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1902 {
1903         if (!bb->code)
1904                 return;
1905
1906         mono_arch_lowering_pass (cfg, bb);
1907
1908         mono_local_regalloc (cfg, bb);
1909 }
1910
1911 static unsigned char*
1912 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1913 {
1914         if (use_sse2) {
1915                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
1916         }
1917         else {
1918                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
1919                 x86_fnstcw_membase(code, AMD64_RSP, 0);
1920                 amd64_mov_reg_membase (code, dreg, AMD64_RSP, 0, 2);
1921                 amd64_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1922                 amd64_mov_membase_reg (code, AMD64_RSP, 2, dreg, 2);
1923                 amd64_fldcw_membase (code, AMD64_RSP, 2);
1924                 amd64_push_reg (code, AMD64_RAX); // SP = SP - 8
1925                 amd64_fist_pop_membase (code, AMD64_RSP, 0, size == 8);
1926                 amd64_pop_reg (code, dreg);
1927                 amd64_fldcw_membase (code, AMD64_RSP, 0);
1928                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
1929         }
1930
1931         if (size == 1)
1932                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
1933         else if (size == 2)
1934                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
1935         return code;
1936 }
1937
1938 static unsigned char*
1939 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1940 {
1941         int sreg = tree->sreg1;
1942         int need_touch = FALSE;
1943
1944 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1945         if (!tree->flags & MONO_INST_INIT)
1946                 need_touch = TRUE;
1947 #endif
1948
1949         if (need_touch) {
1950                 guint8* br[5];
1951
1952                 /*
1953                  * Under Windows:
1954                  * If requested stack size is larger than one page,
1955                  * perform stack-touch operation
1956                  */
1957                 /*
1958                  * Generate stack probe code.
1959                  * Under Windows, it is necessary to allocate one page at a time,
1960                  * "touching" stack after each successful sub-allocation. This is
1961                  * because of the way stack growth is implemented - there is a
1962                  * guard page before the lowest stack page that is currently commited.
1963                  * Stack normally grows sequentially so OS traps access to the
1964                  * guard page and commits more pages when needed.
1965                  */
1966                 amd64_test_reg_imm (code, sreg, ~0xFFF);
1967                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1968
1969                 br[2] = code; /* loop */
1970                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
1971                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
1972                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1973                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1974                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1975                 amd64_patch (br[3], br[2]);
1976                 amd64_test_reg_reg (code, sreg, sreg);
1977                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1978                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
1979
1980                 br[1] = code; x86_jump8 (code, 0);
1981
1982                 amd64_patch (br[0], code);
1983                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
1984                 amd64_patch (br[1], code);
1985                 amd64_patch (br[4], code);
1986         }
1987         else
1988                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
1989
1990         if (tree->flags & MONO_INST_INIT) {
1991                 int offset = 0;
1992                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
1993                         amd64_push_reg (code, AMD64_RAX);
1994                         offset += 8;
1995                 }
1996                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
1997                         amd64_push_reg (code, AMD64_RCX);
1998                         offset += 8;
1999                 }
2000                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2001                         amd64_push_reg (code, AMD64_RDI);
2002                         offset += 8;
2003                 }
2004
2005                 amd64_shift_reg_imm (code, X86_SHR, sreg, 4);
2006                 if (sreg != AMD64_RCX)
2007                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2008                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2009
2010                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2011                 amd64_cld (code);
2012                 amd64_prefix (code, X86_REP_PREFIX);
2013                 amd64_stosl (code);
2014
2015                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2016                         amd64_pop_reg (code, AMD64_RDI);
2017                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2018                         amd64_pop_reg (code, AMD64_RCX);
2019                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2020                         amd64_pop_reg (code, AMD64_RAX);
2021         }
2022         return code;
2023 }
2024
2025 static guint8*
2026 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2027 {
2028         CallInfo *cinfo;
2029         guint32 quad;
2030
2031         /* Move return value to the target register */
2032         /* FIXME: do this in the local reg allocator */
2033         switch (ins->opcode) {
2034         case CEE_CALL:
2035         case OP_CALL_REG:
2036         case OP_CALL_MEMBASE:
2037         case OP_LCALL:
2038         case OP_LCALL_REG:
2039         case OP_LCALL_MEMBASE:
2040                 g_assert (ins->dreg == AMD64_RAX);
2041                 break;
2042         case OP_FCALL:
2043         case OP_FCALL_REG:
2044         case OP_FCALL_MEMBASE:
2045                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2046                         if (use_sse2)
2047                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2048                         else {
2049                                 /* FIXME: optimize this */
2050                                 amd64_movss_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2051                                 amd64_fld_membase (code, AMD64_RSP, -8, FALSE);
2052                         }
2053                 }
2054                 else {
2055                         if (use_sse2) {
2056                                 if (ins->dreg != AMD64_XMM0)
2057                                         amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2058                         }
2059                         else {
2060                                 /* FIXME: optimize this */
2061                                 amd64_movsd_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2062                                 amd64_fld_membase (code, AMD64_RSP, -8, TRUE);
2063                         }
2064                 }
2065                 break;
2066         case OP_VCALL:
2067         case OP_VCALL_REG:
2068         case OP_VCALL_MEMBASE:
2069                 cinfo = get_call_info (((MonoCallInst*)ins)->signature, FALSE);
2070                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2071                         /* Pop the destination address from the stack */
2072                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2073                         amd64_pop_reg (code, AMD64_RCX);
2074
2075                         for (quad = 0; quad < 2; quad ++) {
2076                                 switch (cinfo->ret.pair_storage [quad]) {
2077                                 case ArgInIReg:
2078                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2079                                         break;
2080                                 case ArgInFloatSSEReg:
2081                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2082                                         break;
2083                                 case ArgInDoubleSSEReg:
2084                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2085                                         break;
2086                                 case ArgNone:
2087                                         break;
2088                                 default:
2089                                         NOT_IMPLEMENTED;
2090                                 }
2091                         }
2092                 }
2093                 g_free (cinfo);
2094                 break;
2095         }
2096
2097         return code;
2098 }
2099
2100 /*
2101  * emit_tls_get:
2102  * @code: buffer to store code to
2103  * @dreg: hard register where to place the result
2104  * @tls_offset: offset info
2105  *
2106  * emit_tls_get emits in @code the native code that puts in the dreg register
2107  * the item in the thread local storage identified by tls_offset.
2108  *
2109  * Returns: a pointer to the end of the stored code
2110  */
2111 static guint8*
2112 emit_tls_get (guint8* code, int dreg, int tls_offset)
2113 {
2114         if (optimize_for_xen) {
2115                 x86_prefix (code, X86_FS_PREFIX);
2116                 amd64_mov_reg_mem (code, dreg, 0, 8);
2117                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2118         } else {
2119                 x86_prefix (code, X86_FS_PREFIX);
2120                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2121         }
2122         return code;
2123 }
2124
2125 /*
2126  * emit_load_volatile_arguments:
2127  *
2128  *  Load volatile arguments from the stack to the original input registers.
2129  * Required before a tail call.
2130  */
2131 static guint8*
2132 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2133 {
2134         MonoMethod *method = cfg->method;
2135         MonoMethodSignature *sig;
2136         MonoInst *inst;
2137         CallInfo *cinfo;
2138         guint32 i;
2139
2140         /* FIXME: Generate intermediate code instead */
2141
2142         sig = mono_method_signature (method);
2143
2144         cinfo = get_call_info (sig, FALSE);
2145
2146         /* This is the opposite of the code in emit_prolog */
2147
2148         if (sig->ret->type != MONO_TYPE_VOID) {
2149                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
2150                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->ret->inst_basereg, cfg->ret->inst_offset, 8);
2151                 }
2152         }
2153
2154         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2155                 ArgInfo *ainfo = cinfo->args + i;
2156                 MonoType *arg_type;
2157                 inst = cfg->varinfo [i];
2158
2159                 if (sig->hasthis && (i == 0))
2160                         arg_type = &mono_defaults.object_class->byval_arg;
2161                 else
2162                         arg_type = sig->params [i - sig->hasthis];
2163
2164                 if (inst->opcode != OP_REGVAR) {
2165                         switch (ainfo->storage) {
2166                         case ArgInIReg: {
2167                                 guint32 size = 8;
2168
2169                                 /* FIXME: I1 etc */
2170                                 amd64_mov_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset, size);
2171                                 break;
2172                         }
2173                         case ArgInFloatSSEReg:
2174                                 amd64_movss_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2175                                 break;
2176                         case ArgInDoubleSSEReg:
2177                                 amd64_movsd_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2178                                 break;
2179                         default:
2180                                 break;
2181                         }
2182                 }
2183                 else {
2184                         g_assert (ainfo->storage == ArgInIReg);
2185
2186                         amd64_mov_reg_reg (code, ainfo->reg, inst->dreg, 8);
2187                 }
2188         }
2189
2190         g_free (cinfo);
2191
2192         return code;
2193 }
2194
2195 #define REAL_PRINT_REG(text,reg) \
2196 mono_assert (reg >= 0); \
2197 amd64_push_reg (code, AMD64_RAX); \
2198 amd64_push_reg (code, AMD64_RDX); \
2199 amd64_push_reg (code, AMD64_RCX); \
2200 amd64_push_reg (code, reg); \
2201 amd64_push_imm (code, reg); \
2202 amd64_push_imm (code, text " %d %p\n"); \
2203 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2204 amd64_call_reg (code, AMD64_RAX); \
2205 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2206 amd64_pop_reg (code, AMD64_RCX); \
2207 amd64_pop_reg (code, AMD64_RDX); \
2208 amd64_pop_reg (code, AMD64_RAX);
2209
2210 /* benchmark and set based on cpu */
2211 #define LOOP_ALIGNMENT 8
2212 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2213
2214 void
2215 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2216 {
2217         MonoInst *ins;
2218         MonoCallInst *call;
2219         guint offset;
2220         guint8 *code = cfg->native_code + cfg->code_len;
2221         MonoInst *last_ins = NULL;
2222         guint last_offset = 0;
2223         int max_len, cpos;
2224
2225         if (cfg->opt & MONO_OPT_PEEPHOLE)
2226                 peephole_pass (cfg, bb);
2227
2228         if (cfg->opt & MONO_OPT_LOOP) {
2229                 int pad, align = LOOP_ALIGNMENT;
2230                 /* set alignment depending on cpu */
2231                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2232                         pad = align - pad;
2233                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2234                         amd64_padding (code, pad);
2235                         cfg->code_len += pad;
2236                         bb->native_offset = cfg->code_len;
2237                 }
2238         }
2239
2240         if (cfg->verbose_level > 2)
2241                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2242
2243         cpos = bb->max_offset;
2244
2245         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2246                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2247                 g_assert (!cfg->compile_aot);
2248                 cpos += 6;
2249
2250                 cov->data [bb->dfn].cil_code = bb->cil_code;
2251                 /* this is not thread save, but good enough */
2252                 amd64_inc_mem (code, (guint64)&cov->data [bb->dfn].count);
2253         }
2254
2255         offset = code - cfg->native_code;
2256
2257         ins = bb->code;
2258         while (ins) {
2259                 offset = code - cfg->native_code;
2260
2261                 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
2262
2263                 if (offset > (cfg->code_size - max_len - 16)) {
2264                         cfg->code_size *= 2;
2265                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2266                         code = cfg->native_code + offset;
2267                         mono_jit_stats.code_reallocs++;
2268                 }
2269
2270                 mono_debug_record_line_number (cfg, ins, offset);
2271
2272                 switch (ins->opcode) {
2273                 case OP_BIGMUL:
2274                         amd64_mul_reg (code, ins->sreg2, TRUE);
2275                         break;
2276                 case OP_BIGMUL_UN:
2277                         amd64_mul_reg (code, ins->sreg2, FALSE);
2278                         break;
2279                 case OP_X86_SETEQ_MEMBASE:
2280                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2281                         break;
2282                 case OP_STOREI1_MEMBASE_IMM:
2283                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2284                         break;
2285                 case OP_STOREI2_MEMBASE_IMM:
2286                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2287                         break;
2288                 case OP_STOREI4_MEMBASE_IMM:
2289                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2290                         break;
2291                 case OP_STOREI1_MEMBASE_REG:
2292                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2293                         break;
2294                 case OP_STOREI2_MEMBASE_REG:
2295                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2296                         break;
2297                 case OP_STORE_MEMBASE_REG:
2298                 case OP_STOREI8_MEMBASE_REG:
2299                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2300                         break;
2301                 case OP_STOREI4_MEMBASE_REG:
2302                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2303                         break;
2304                 case OP_STORE_MEMBASE_IMM:
2305                 case OP_STOREI8_MEMBASE_IMM:
2306                         g_assert (amd64_is_imm32 (ins->inst_imm));
2307                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2308                         break;
2309                 case CEE_LDIND_I:
2310                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, sizeof (gpointer));
2311                         break;
2312                 case CEE_LDIND_I4:
2313                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2314                         break;
2315                 case CEE_LDIND_U4:
2316                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2317                         break;
2318                 case OP_LOADU4_MEM:
2319                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2320                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2321                         break;
2322                 case OP_LOAD_MEMBASE:
2323                 case OP_LOADI8_MEMBASE:
2324                         g_assert (amd64_is_imm32 (ins->inst_offset));
2325                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2326                         break;
2327                 case OP_LOADI4_MEMBASE:
2328                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2329                         break;
2330                 case OP_LOADU4_MEMBASE:
2331                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2332                         break;
2333                 case OP_LOADU1_MEMBASE:
2334                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2335                         break;
2336                 case OP_LOADI1_MEMBASE:
2337                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2338                         break;
2339                 case OP_LOADU2_MEMBASE:
2340                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2341                         break;
2342                 case OP_LOADI2_MEMBASE:
2343                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2344                         break;
2345                 case OP_AMD64_LOADI8_MEMINDEX:
2346                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2347                         break;
2348                 case CEE_CONV_I1:
2349                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2350                         break;
2351                 case CEE_CONV_I2:
2352                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2353                         break;
2354                 case CEE_CONV_U1:
2355                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2356                         break;
2357                 case CEE_CONV_U2:
2358                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2359                         break;
2360                 case CEE_CONV_U8:
2361                 case CEE_CONV_U:
2362                         /* Clean out the upper word */
2363                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2364                         break;
2365                 case CEE_CONV_I8:
2366                 case CEE_CONV_I:
2367                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2368                         break;
2369                 case OP_COMPARE:
2370                 case OP_LCOMPARE:
2371                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2372                         break;
2373                 case OP_COMPARE_IMM:
2374                         g_assert (amd64_is_imm32 (ins->inst_imm));
2375                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2376                         break;
2377                 case OP_X86_COMPARE_REG_MEMBASE:
2378                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2379                         break;
2380                 case OP_X86_TEST_NULL:
2381                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2382                         break;
2383                 case OP_AMD64_TEST_NULL:
2384                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2385                         break;
2386                 case OP_X86_ADD_MEMBASE_IMM:
2387                         /* FIXME: Make a 64 version too */
2388                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2389                         break;
2390                 case OP_X86_ADD_MEMBASE:
2391                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2392                         break;
2393                 case OP_X86_SUB_MEMBASE_IMM:
2394                         g_assert (amd64_is_imm32 (ins->inst_imm));
2395                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2396                         break;
2397                 case OP_X86_SUB_MEMBASE:
2398                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2399                         break;
2400                 case OP_X86_INC_MEMBASE:
2401                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2402                         break;
2403                 case OP_X86_INC_REG:
2404                         amd64_inc_reg_size (code, ins->dreg, 4);
2405                         break;
2406                 case OP_X86_DEC_MEMBASE:
2407                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2408                         break;
2409                 case OP_X86_DEC_REG:
2410                         amd64_dec_reg_size (code, ins->dreg, 4);
2411                         break;
2412                 case OP_X86_MUL_MEMBASE:
2413                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2414                         break;
2415                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2416                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2417                         break;
2418                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2419                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2420                         break;
2421                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2422                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2423                         break;
2424                 case CEE_BREAK:
2425                         amd64_breakpoint (code);
2426                         break;
2427                 case OP_ADDCC:
2428                 case CEE_ADD:
2429                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2430                         break;
2431                 case OP_ADC:
2432                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2433                         break;
2434                 case OP_ADD_IMM:
2435                         g_assert (amd64_is_imm32 (ins->inst_imm));
2436                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2437                         break;
2438                 case OP_ADC_IMM:
2439                         g_assert (amd64_is_imm32 (ins->inst_imm));
2440                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2441                         break;
2442                 case OP_SUBCC:
2443                 case CEE_SUB:
2444                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2445                         break;
2446                 case OP_SBB:
2447                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2448                         break;
2449                 case OP_SUB_IMM:
2450                         g_assert (amd64_is_imm32 (ins->inst_imm));
2451                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2452                         break;
2453                 case OP_SBB_IMM:
2454                         g_assert (amd64_is_imm32 (ins->inst_imm));
2455                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2456                         break;
2457                 case CEE_AND:
2458                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2459                         break;
2460                 case OP_AND_IMM:
2461                         g_assert (amd64_is_imm32 (ins->inst_imm));
2462                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2463                         break;
2464                 case CEE_MUL:
2465                 case OP_LMUL:
2466                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2467                         break;
2468                 case OP_MUL_IMM:
2469                 case OP_LMUL_IMM:
2470                 case OP_IMUL_IMM: {
2471                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2472
2473                         switch (ins->inst_imm) {
2474                         case 2:
2475                                 /* MOV r1, r2 */
2476                                 /* ADD r1, r1 */
2477                                 if (ins->dreg != ins->sreg1)
2478                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2479                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2480                                 break;
2481                         case 3:
2482                                 /* LEA r1, [r2 + r2*2] */
2483                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2484                                 break;
2485                         case 5:
2486                                 /* LEA r1, [r2 + r2*4] */
2487                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2488                                 break;
2489                         case 6:
2490                                 /* LEA r1, [r2 + r2*2] */
2491                                 /* ADD r1, r1          */
2492                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2493                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2494                                 break;
2495                         case 9:
2496                                 /* LEA r1, [r2 + r2*8] */
2497                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2498                                 break;
2499                         case 10:
2500                                 /* LEA r1, [r2 + r2*4] */
2501                                 /* ADD r1, r1          */
2502                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2503                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2504                                 break;
2505                         case 12:
2506                                 /* LEA r1, [r2 + r2*2] */
2507                                 /* SHL r1, 2           */
2508                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2509                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2510                                 break;
2511                         case 25:
2512                                 /* LEA r1, [r2 + r2*4] */
2513                                 /* LEA r1, [r1 + r1*4] */
2514                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2515                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2516                                 break;
2517                         case 100:
2518                                 /* LEA r1, [r2 + r2*4] */
2519                                 /* SHL r1, 2           */
2520                                 /* LEA r1, [r1 + r1*4] */
2521                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2522                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2523                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2524                                 break;
2525                         default:
2526                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2527                                 break;
2528                         }
2529                         break;
2530                 }
2531                 case CEE_DIV:
2532                 case OP_LDIV:
2533                         amd64_cdq (code);
2534                         amd64_div_reg (code, ins->sreg2, TRUE);
2535                         break;
2536                 case CEE_DIV_UN:
2537                 case OP_LDIV_UN:
2538                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2539                         amd64_div_reg (code, ins->sreg2, FALSE);
2540                         break;
2541                 case CEE_REM:
2542                 case OP_LREM:
2543                         amd64_cdq (code);
2544                         amd64_div_reg (code, ins->sreg2, TRUE);
2545                         break;
2546                 case CEE_REM_UN:
2547                 case OP_LREM_UN:
2548                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2549                         amd64_div_reg (code, ins->sreg2, FALSE);
2550                         break;
2551                 case OP_LMUL_OVF:
2552                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2553                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2554                         break;
2555                 case CEE_OR:
2556                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2557                         break;
2558                 case OP_OR_IMM
2559 :                       g_assert (amd64_is_imm32 (ins->inst_imm));
2560                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2561                         break;
2562                 case CEE_XOR:
2563                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2564                         break;
2565                 case OP_XOR_IMM:
2566                         g_assert (amd64_is_imm32 (ins->inst_imm));
2567                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2568                         break;
2569                 case CEE_SHL:
2570                 case OP_LSHL:
2571                         g_assert (ins->sreg2 == AMD64_RCX);
2572                         amd64_shift_reg (code, X86_SHL, ins->dreg);
2573                         break;
2574                 case CEE_SHR:
2575                 case OP_LSHR:
2576                         g_assert (ins->sreg2 == AMD64_RCX);
2577                         amd64_shift_reg (code, X86_SAR, ins->dreg);
2578                         break;
2579                 case OP_SHR_IMM:
2580                         g_assert (amd64_is_imm32 (ins->inst_imm));
2581                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2582                         break;
2583                 case OP_LSHR_IMM:
2584                         g_assert (amd64_is_imm32 (ins->inst_imm));
2585                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2586                         break;
2587                 case OP_SHR_UN_IMM:
2588                         g_assert (amd64_is_imm32 (ins->inst_imm));
2589                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2590                         break;
2591                 case OP_LSHR_UN_IMM:
2592                         g_assert (amd64_is_imm32 (ins->inst_imm));
2593                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2594                         break;
2595                 case CEE_SHR_UN:
2596                         g_assert (ins->sreg2 == AMD64_RCX);
2597                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2598                         break;
2599                 case OP_LSHR_UN:
2600                         g_assert (ins->sreg2 == AMD64_RCX);
2601                         amd64_shift_reg (code, X86_SHR, ins->dreg);
2602                         break;
2603                 case OP_SHL_IMM:
2604                         g_assert (amd64_is_imm32 (ins->inst_imm));
2605                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2606                         break;
2607                 case OP_LSHL_IMM:
2608                         g_assert (amd64_is_imm32 (ins->inst_imm));
2609                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2610                         break;
2611
2612                 case OP_IADDCC:
2613                 case OP_IADD:
2614                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
2615                         break;
2616                 case OP_IADC:
2617                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
2618                         break;
2619                 case OP_IADD_IMM:
2620                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
2621                         break;
2622                 case OP_IADC_IMM:
2623                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
2624                         break;
2625                 case OP_ISUBCC:
2626                 case OP_ISUB:
2627                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
2628                         break;
2629                 case OP_ISBB:
2630                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
2631                         break;
2632                 case OP_ISUB_IMM:
2633                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
2634                         break;
2635                 case OP_ISBB_IMM:
2636                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
2637                         break;
2638                 case OP_IAND:
2639                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
2640                         break;
2641                 case OP_IAND_IMM:
2642                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
2643                         break;
2644                 case OP_IOR:
2645                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
2646                         break;
2647                 case OP_IOR_IMM:
2648                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
2649                         break;
2650                 case OP_IXOR:
2651                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
2652                         break;
2653                 case OP_IXOR_IMM:
2654                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
2655                         break;
2656                 case OP_INEG:
2657                         amd64_neg_reg_size (code, ins->sreg1, 4);
2658                         break;
2659                 case OP_INOT:
2660                         amd64_not_reg_size (code, ins->sreg1, 4);
2661                         break;
2662                 case OP_ISHL:
2663                         g_assert (ins->sreg2 == AMD64_RCX);
2664                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
2665                         break;
2666                 case OP_ISHR:
2667                         g_assert (ins->sreg2 == AMD64_RCX);
2668                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
2669                         break;
2670                 case OP_ISHR_IMM:
2671                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2672                         break;
2673                 case OP_ISHR_UN_IMM:
2674                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2675                         break;
2676                 case OP_ISHR_UN:
2677                         g_assert (ins->sreg2 == AMD64_RCX);
2678                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2679                         break;
2680                 case OP_ISHL_IMM:
2681                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2682                         break;
2683                 case OP_IMUL:
2684                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2685                         break;
2686                 case OP_IMUL_OVF:
2687                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2688                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2689                         break;
2690                 case OP_IMUL_OVF_UN:
2691                 case OP_LMUL_OVF_UN: {
2692                         /* the mul operation and the exception check should most likely be split */
2693                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2694                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
2695                         /*g_assert (ins->sreg2 == X86_EAX);
2696                         g_assert (ins->dreg == X86_EAX);*/
2697                         if (ins->sreg2 == X86_EAX) {
2698                                 non_eax_reg = ins->sreg1;
2699                         } else if (ins->sreg1 == X86_EAX) {
2700                                 non_eax_reg = ins->sreg2;
2701                         } else {
2702                                 /* no need to save since we're going to store to it anyway */
2703                                 if (ins->dreg != X86_EAX) {
2704                                         saved_eax = TRUE;
2705                                         amd64_push_reg (code, X86_EAX);
2706                                 }
2707                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
2708                                 non_eax_reg = ins->sreg2;
2709                         }
2710                         if (ins->dreg == X86_EDX) {
2711                                 if (!saved_eax) {
2712                                         saved_eax = TRUE;
2713                                         amd64_push_reg (code, X86_EAX);
2714                                 }
2715                         } else {
2716                                 saved_edx = TRUE;
2717                                 amd64_push_reg (code, X86_EDX);
2718                         }
2719                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
2720                         /* save before the check since pop and mov don't change the flags */
2721                         if (ins->dreg != X86_EAX)
2722                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
2723                         if (saved_edx)
2724                                 amd64_pop_reg (code, X86_EDX);
2725                         if (saved_eax)
2726                                 amd64_pop_reg (code, X86_EAX);
2727                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2728                         break;
2729                 }
2730                 case OP_IDIV:
2731                         amd64_cdq_size (code, 4);
2732                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2733                         break;
2734                 case OP_IDIV_UN:
2735                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2736                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2737                         break;
2738                 case OP_IREM:
2739                         amd64_cdq_size (code, 4);
2740                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2741                         break;
2742                 case OP_IREM_UN:
2743                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2744                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2745                         break;
2746                 case OP_ICOMPARE:
2747                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
2748                         break;
2749                 case OP_ICOMPARE_IMM:
2750                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
2751                         break;
2752                 case OP_IBEQ:
2753                 case OP_IBLT:
2754                 case OP_IBGT:
2755                 case OP_IBGE:
2756                 case OP_IBLE:
2757                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), TRUE);
2758                         break;
2759                 case OP_IBNE_UN:
2760                 case OP_IBLT_UN:
2761                 case OP_IBGT_UN:
2762                 case OP_IBGE_UN:
2763                 case OP_IBLE_UN:
2764                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), FALSE);
2765                         break;
2766                 case OP_COND_EXC_IOV:
2767                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2768                                                                                 TRUE, ins->inst_p1);
2769                         break;
2770                 case OP_COND_EXC_IC:
2771                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2772                                                                                 FALSE, ins->inst_p1);
2773                         break;
2774                 case CEE_NOT:
2775                         amd64_not_reg (code, ins->sreg1);
2776                         break;
2777                 case CEE_NEG:
2778                         amd64_neg_reg (code, ins->sreg1);
2779                         break;
2780                 case OP_SEXT_I1:
2781                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2782                         break;
2783                 case OP_SEXT_I2:
2784                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2785                         break;
2786                 case OP_SEXT_I4:
2787                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2788                         break;
2789                 case OP_ICONST:
2790                 case OP_I8CONST:
2791                         if ((((guint64)ins->inst_c0) >> 32) == 0)
2792                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
2793                         else
2794                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
2795                         break;
2796                 case OP_AOTCONST:
2797                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2798                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
2799                         break;
2800                 case CEE_CONV_I4:
2801                 case CEE_CONV_U4:
2802                 case OP_MOVE:
2803                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
2804                         break;
2805                 case OP_AMD64_SET_XMMREG_R4: {
2806                         if (use_sse2) {
2807                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
2808                         }
2809                         else {
2810                                 amd64_fst_membase (code, AMD64_RSP, -8, FALSE, TRUE);
2811                                 /* ins->dreg is set to -1 by the reg allocator */
2812                                 amd64_movss_reg_membase (code, ins->unused, AMD64_RSP, -8);
2813                         }
2814                         break;
2815                 }
2816                 case OP_AMD64_SET_XMMREG_R8: {
2817                         if (use_sse2) {
2818                                 if (ins->dreg != ins->sreg1)
2819                                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
2820                         }
2821                         else {
2822                                 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE);
2823                                 /* ins->dreg is set to -1 by the reg allocator */
2824                                 amd64_movsd_reg_membase (code, ins->unused, AMD64_RSP, -8);
2825                         }
2826                         break;
2827                 }
2828                 case CEE_JMP: {
2829                         /*
2830                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2831                          * Keep in sync with the code in emit_epilog.
2832                          */
2833                         int pos = 0, i;
2834
2835                         /* FIXME: no tracing support... */
2836                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2837                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2838
2839                         g_assert (!cfg->method->save_lmf);
2840
2841                         code = emit_load_volatile_arguments (cfg, code);
2842
2843                         if (cfg->arch.omit_fp) {
2844                                 guint32 save_offset = 0;
2845                                 /* Pop callee-saved registers */
2846                                 for (i = 0; i < AMD64_NREG; ++i)
2847                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2848                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
2849                                                 save_offset += 8;
2850                                         }
2851                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
2852                         }
2853                         else {
2854                                 for (i = 0; i < AMD64_NREG; ++i)
2855                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
2856                                                 pos -= sizeof (gpointer);
2857
2858                                 if (pos)
2859                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
2860
2861                                 /* Pop registers in reverse order */
2862                                 for (i = AMD64_NREG - 1; i > 0; --i)
2863                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2864                                                 amd64_pop_reg (code, i);
2865                                         }
2866
2867                                 amd64_leave (code);
2868                         }
2869
2870                         offset = code - cfg->native_code;
2871                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2872                         if (cfg->compile_aot)
2873                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
2874                         else
2875                                 amd64_set_reg_template (code, AMD64_R11);
2876                         amd64_jump_reg (code, AMD64_R11);
2877                         break;
2878                 }
2879                 case OP_CHECK_THIS:
2880                         /* ensure ins->sreg1 is not NULL */
2881                         amd64_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2882                         break;
2883                 case OP_ARGLIST: {
2884                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
2885                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
2886                         break;
2887                 }
2888                 case OP_FCALL:
2889                 case OP_LCALL:
2890                 case OP_VCALL:
2891                 case OP_VOIDCALL:
2892                 case CEE_CALL:
2893                         call = (MonoCallInst*)ins;
2894                         /*
2895                          * The AMD64 ABI forces callers to know about varargs.
2896                          */
2897                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
2898                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2899                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
2900                                 /*
2901                                  * Since the unmanaged calling convention doesn't contain a
2902                                  * 'vararg' entry, we have to treat every pinvoke call as a
2903                                  * potential vararg call.
2904                                  */
2905                                 guint32 nregs, i;
2906                                 nregs = 0;
2907                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
2908                                         if (call->used_fregs & (1 << i))
2909                                                 nregs ++;
2910                                 if (!nregs)
2911                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2912                                 else
2913                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
2914                         }
2915
2916                         if (ins->flags & MONO_INST_HAS_METHOD)
2917                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2918                         else
2919                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2920                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2921                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2922                         code = emit_move_return_value (cfg, ins, code);
2923                         break;
2924                 case OP_FCALL_REG:
2925                 case OP_LCALL_REG:
2926                 case OP_VCALL_REG:
2927                 case OP_VOIDCALL_REG:
2928                 case OP_CALL_REG:
2929                         call = (MonoCallInst*)ins;
2930
2931                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2932                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
2933                                 ins->sreg1 = AMD64_R11;
2934                         }
2935
2936                         /*
2937                          * The AMD64 ABI forces callers to know about varargs.
2938                          */
2939                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
2940                                 if (ins->sreg1 == AMD64_RAX) {
2941                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
2942                                         ins->sreg1 = AMD64_R11;
2943                                 }
2944                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2945                         }
2946                         amd64_call_reg (code, ins->sreg1);
2947                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2948                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2949                         code = emit_move_return_value (cfg, ins, code);
2950                         break;
2951                 case OP_FCALL_MEMBASE:
2952                 case OP_LCALL_MEMBASE:
2953                 case OP_VCALL_MEMBASE:
2954                 case OP_VOIDCALL_MEMBASE:
2955                 case OP_CALL_MEMBASE:
2956                         call = (MonoCallInst*)ins;
2957
2958                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2959                                 /*
2960                                  * Can't use R11 because it is clobbered by the trampoline
2961                                  * code, and the reg value is needed by get_vcall_slot_addr.
2962                                  */
2963                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
2964                                 ins->sreg1 = AMD64_RAX;
2965                         }
2966
2967                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
2968                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2969                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2970                         code = emit_move_return_value (cfg, ins, code);
2971                         break;
2972                 case OP_OUTARG:
2973                 case OP_X86_PUSH:
2974                         amd64_push_reg (code, ins->sreg1);
2975                         break;
2976                 case OP_X86_PUSH_IMM:
2977                         g_assert (amd64_is_imm32 (ins->inst_imm));
2978                         amd64_push_imm (code, ins->inst_imm);
2979                         break;
2980                 case OP_X86_PUSH_MEMBASE:
2981                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
2982                         break;
2983                 case OP_X86_PUSH_OBJ:
2984                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
2985                         amd64_push_reg (code, AMD64_RDI);
2986                         amd64_push_reg (code, AMD64_RSI);
2987                         amd64_push_reg (code, AMD64_RCX);
2988                         if (ins->inst_offset)
2989                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
2990                         else
2991                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
2992                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
2993                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
2994                         amd64_cld (code);
2995                         amd64_prefix (code, X86_REP_PREFIX);
2996                         amd64_movsd (code);
2997                         amd64_pop_reg (code, AMD64_RCX);
2998                         amd64_pop_reg (code, AMD64_RSI);
2999                         amd64_pop_reg (code, AMD64_RDI);
3000                         break;
3001                 case OP_X86_LEA:
3002                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->unused);
3003                         break;
3004                 case OP_X86_LEA_MEMBASE:
3005                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3006                         break;
3007                 case OP_X86_XCHG:
3008                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3009                         break;
3010                 case OP_LOCALLOC:
3011                         /* keep alignment */
3012                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3013                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3014                         code = mono_emit_stack_alloc (code, ins);
3015                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3016                         break;
3017                 case CEE_RET:
3018                         amd64_ret (code);
3019                         break;
3020                 case CEE_THROW: {
3021                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3022                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3023                                              (gpointer)"mono_arch_throw_exception");
3024                         break;
3025                 }
3026                 case OP_RETHROW: {
3027                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3028                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3029                                              (gpointer)"mono_arch_rethrow_exception");
3030                         break;
3031                 }
3032                 case OP_CALL_HANDLER:
3033                         /* Align stack */
3034                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3035                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3036                         amd64_call_imm (code, 0);
3037                         /* Restore stack alignment */
3038                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3039                         break;
3040                 case OP_LABEL:
3041                         ins->inst_c0 = code - cfg->native_code;
3042                         break;
3043                 case CEE_BR:
3044                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3045                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3046                         //break;
3047                         if (ins->flags & MONO_INST_BRLABEL) {
3048                                 if (ins->inst_i0->inst_c0) {
3049                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3050                                 } else {
3051                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3052                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3053                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3054                                                 x86_jump8 (code, 0);
3055                                         else
3056                                                 x86_jump32 (code, 0);
3057                                 }
3058                         } else {
3059                                 if (ins->inst_target_bb->native_offset) {
3060                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3061                                 } else {
3062                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3063                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3064                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3065                                                 x86_jump8 (code, 0);
3066                                         else
3067                                                 x86_jump32 (code, 0);
3068                                 }
3069                         }
3070                         break;
3071                 case OP_BR_REG:
3072                         amd64_jump_reg (code, ins->sreg1);
3073                         break;
3074                 case OP_CEQ:
3075                 case OP_ICEQ:
3076                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3077                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3078                         break;
3079                 case OP_CLT:
3080                 case OP_ICLT:
3081                         amd64_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
3082                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3083                         break;
3084                 case OP_CLT_UN:
3085                 case OP_ICLT_UN:
3086                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3087                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3088                         break;
3089                 case OP_CGT:
3090                 case OP_ICGT:
3091                         amd64_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
3092                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3093                         break;
3094                 case OP_CGT_UN:
3095                 case OP_ICGT_UN:
3096                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3097                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3098                         break;
3099                 case OP_COND_EXC_EQ:
3100                 case OP_COND_EXC_NE_UN:
3101                 case OP_COND_EXC_LT:
3102                 case OP_COND_EXC_LT_UN:
3103                 case OP_COND_EXC_GT:
3104                 case OP_COND_EXC_GT_UN:
3105                 case OP_COND_EXC_GE:
3106                 case OP_COND_EXC_GE_UN:
3107                 case OP_COND_EXC_LE:
3108                 case OP_COND_EXC_LE_UN:
3109                 case OP_COND_EXC_OV:
3110                 case OP_COND_EXC_NO:
3111                 case OP_COND_EXC_C:
3112                 case OP_COND_EXC_NC:
3113                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3114                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3115                         break;
3116                 case CEE_BEQ:
3117                 case CEE_BNE_UN:
3118                 case CEE_BLT:
3119                 case CEE_BLT_UN:
3120                 case CEE_BGT:
3121                 case CEE_BGT_UN:
3122                 case CEE_BGE:
3123                 case CEE_BGE_UN:
3124                 case CEE_BLE:
3125                 case CEE_BLE_UN:
3126                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
3127                         break;
3128
3129                 /* floating point opcodes */
3130                 case OP_R8CONST: {
3131                         double d = *(double *)ins->inst_p0;
3132
3133                         if (use_sse2) {
3134                                 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3135                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3136                                 }
3137                                 else {
3138                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3139                                         amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3140                                 }
3141                         }
3142                         else if ((d == 0.0) && (mono_signbit (d) == 0)) {
3143                                 amd64_fldz (code);
3144                         } else if (d == 1.0) {
3145                                 x86_fld1 (code);
3146                         } else {
3147                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3148                                 amd64_fld_membase (code, AMD64_RIP, 0, TRUE);
3149                         }
3150                         break;
3151                 }
3152                 case OP_R4CONST: {
3153                         float f = *(float *)ins->inst_p0;
3154
3155                         if (use_sse2) {
3156                                 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3157                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3158                                 }
3159                                 else {
3160                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3161                                         amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3162                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3163                                 }
3164                         }
3165                         else if ((f == 0.0) && (mono_signbit (f) == 0)) {
3166                                 amd64_fldz (code);
3167                         } else if (f == 1.0) {
3168                                 x86_fld1 (code);
3169                         } else {
3170                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3171                                 amd64_fld_membase (code, AMD64_RIP, 0, FALSE);
3172                         }
3173                         break;
3174                 }
3175                 case OP_STORER8_MEMBASE_REG:
3176                         if (use_sse2)
3177                                 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3178                         else
3179                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3180                         break;
3181                 case OP_LOADR8_SPILL_MEMBASE:
3182                         if (use_sse2)
3183                                 g_assert_not_reached ();
3184                         amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3185                         amd64_fxch (code, 1);
3186                         break;
3187                 case OP_LOADR8_MEMBASE:
3188                         if (use_sse2)
3189                                 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3190                         else
3191                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3192                         break;
3193                 case OP_STORER4_MEMBASE_REG:
3194                         if (use_sse2) {
3195                                 /* This requires a double->single conversion */
3196                                 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3197                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3198                         }
3199                         else
3200                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3201                         break;
3202                 case OP_LOADR4_MEMBASE:
3203                         if (use_sse2) {
3204                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3205                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3206                         }
3207                         else
3208                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3209                         break;
3210                 case CEE_CONV_R4: /* FIXME: change precision */
3211                 case CEE_CONV_R8:
3212                         if (use_sse2)
3213                                 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3214                         else {
3215                                 amd64_push_reg (code, ins->sreg1);
3216                                 amd64_fild_membase (code, AMD64_RSP, 0, FALSE);
3217                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3218                         }
3219                         break;
3220                 case CEE_CONV_R_UN:
3221                         /* Emulated */
3222                         g_assert_not_reached ();
3223                         break;
3224                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3225                 case OP_LCONV_TO_R8:
3226                         if (use_sse2)
3227                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3228                         else {
3229                                 amd64_push_reg (code, ins->sreg1);
3230                                 amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3231                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3232                         }
3233                         break;
3234                 case OP_X86_FP_LOAD_I8:
3235                         if (use_sse2)
3236                                 g_assert_not_reached ();
3237                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3238                         break;
3239                 case OP_X86_FP_LOAD_I4:
3240                         if (use_sse2)
3241                                 g_assert_not_reached ();
3242                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3243                         break;
3244                 case OP_FCONV_TO_I1:
3245                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3246                         break;
3247                 case OP_FCONV_TO_U1:
3248                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3249                         break;
3250                 case OP_FCONV_TO_I2:
3251                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3252                         break;
3253                 case OP_FCONV_TO_U2:
3254                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3255                         break;
3256                 case OP_FCONV_TO_I4:
3257                 case OP_FCONV_TO_I:
3258                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3259                         break;
3260                 case OP_FCONV_TO_I8:
3261                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3262                         break;
3263                 case OP_LCONV_TO_R_UN: {
3264                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3265                         guint8 *br;
3266
3267                         if (use_sse2)
3268                                 g_assert_not_reached ();
3269
3270                         /* load 64bit integer to FP stack */
3271                         amd64_push_imm (code, 0);
3272                         amd64_push_reg (code, ins->sreg2);
3273                         amd64_push_reg (code, ins->sreg1);
3274                         amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3275                         /* store as 80bit FP value */
3276                         x86_fst80_membase (code, AMD64_RSP, 0);
3277
3278                         /* test if lreg is negative */
3279                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
3280                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3281
3282                         /* add correction constant mn */
3283                         x86_fld80_mem (code, mn);
3284                         x86_fld80_membase (code, AMD64_RSP, 0);
3285                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3286                         x86_fst80_membase (code, AMD64_RSP, 0);
3287
3288                         amd64_patch (br, code);
3289
3290                         x86_fld80_membase (code, AMD64_RSP, 0);
3291                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 12);
3292
3293                         break;
3294                 }
3295                 case CEE_CONV_OVF_U4:
3296                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3297                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3298                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3299                         break;
3300                 case CEE_CONV_OVF_I4_UN:
3301                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3302                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3303                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3304                         break;
3305                 case OP_FMOVE:
3306                         if (use_sse2 && (ins->dreg != ins->sreg1))
3307                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3308                         break;
3309                 case OP_FADD:
3310                         if (use_sse2)
3311                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3312                         else
3313                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3314                         break;
3315                 case OP_FSUB:
3316                         if (use_sse2)
3317                                 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3318                         else
3319                                 amd64_fp_op_reg (code, X86_FSUB, 1, TRUE);
3320                         break;
3321                 case OP_FMUL:
3322                         if (use_sse2)
3323                                 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3324                         else
3325                                 amd64_fp_op_reg (code, X86_FMUL, 1, TRUE);
3326                         break;
3327                 case OP_FDIV:
3328                         if (use_sse2)
3329                                 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3330                         else
3331                                 amd64_fp_op_reg (code, X86_FDIV, 1, TRUE);
3332                         break;
3333                 case OP_FNEG:
3334                         if (use_sse2) {
3335                                 amd64_mov_reg_imm_size (code, AMD64_R11, 0x8000000000000000, 8);
3336                                 amd64_push_reg (code, AMD64_R11);
3337                                 amd64_push_reg (code, AMD64_R11);
3338                                 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RSP, 0);
3339                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3340                         }
3341                         else
3342                                 amd64_fchs (code);
3343                         break;
3344                 case OP_SIN:
3345                         if (use_sse2) {
3346                                 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3347                         }
3348                         else {
3349                                 amd64_fsin (code);
3350                                 amd64_fldz (code);
3351                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3352                         }
3353                         break;
3354                 case OP_COS:
3355                         if (use_sse2) {
3356                                 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3357                         }
3358                         else {
3359                                 amd64_fcos (code);
3360                                 amd64_fldz (code);
3361                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3362                         }
3363                         break;
3364                 case OP_ABS:
3365                         if (use_sse2) {
3366                                 EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
3367                         }
3368                         else
3369                                 amd64_fabs (code);
3370                         break;
3371                 case OP_TAN: {
3372                         /*
3373                          * it really doesn't make sense to inline all this code,
3374                          * it's here just to show that things may not be as simple
3375                          * as they appear.
3376                          */
3377                         guchar *check_pos, *end_tan, *pop_jump;
3378                         if (use_sse2)
3379                                 g_assert_not_reached ();
3380                         amd64_push_reg (code, AMD64_RAX);
3381                         amd64_fptan (code);
3382                         amd64_fnstsw (code);
3383                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3384                         check_pos = code;
3385                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3386                         amd64_fstp (code, 0); /* pop the 1.0 */
3387                         end_tan = code;
3388                         x86_jump8 (code, 0);
3389                         amd64_fldpi (code);
3390                         amd64_fp_op (code, X86_FADD, 0);
3391                         amd64_fxch (code, 1);
3392                         x86_fprem1 (code);
3393                         amd64_fstsw (code);
3394                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3395                         pop_jump = code;
3396                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3397                         amd64_fstp (code, 1);
3398                         amd64_fptan (code);
3399                         amd64_patch (pop_jump, code);
3400                         amd64_fstp (code, 0); /* pop the 1.0 */
3401                         amd64_patch (check_pos, code);
3402                         amd64_patch (end_tan, code);
3403                         amd64_fldz (code);
3404                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3405                         amd64_pop_reg (code, AMD64_RAX);
3406                         break;
3407                 }
3408                 case OP_ATAN:
3409                         if (use_sse2)
3410                                 g_assert_not_reached ();
3411                         x86_fld1 (code);
3412                         amd64_fpatan (code);
3413                         amd64_fldz (code);
3414                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3415                         break;
3416                 case OP_SQRT:
3417                         if (use_sse2) {
3418                                 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3419                         }
3420                         else
3421                                 amd64_fsqrt (code);
3422                         break;
3423                 case OP_X86_FPOP:
3424                         if (!use_sse2)
3425                                 amd64_fstp (code, 0);
3426                         break;
3427                 case OP_FREM: {
3428                         guint8 *l1, *l2;
3429
3430                         if (use_sse2)
3431                                 g_assert_not_reached ();
3432                         amd64_push_reg (code, AMD64_RAX);
3433                         /* we need to exchange ST(0) with ST(1) */
3434                         amd64_fxch (code, 1);
3435
3436                         /* this requires a loop, because fprem somtimes
3437                          * returns a partial remainder */
3438                         l1 = code;
3439                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3440                         /* x86_fprem1 (code); */
3441                         amd64_fprem (code);
3442                         amd64_fnstsw (code);
3443                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_C2);
3444                         l2 = code + 2;
3445                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3446
3447                         /* pop result */
3448                         amd64_fstp (code, 1);
3449
3450                         amd64_pop_reg (code, AMD64_RAX);
3451                         break;
3452                 }
3453                 case OP_FCOMPARE:
3454                         if (use_sse2) {
3455                                 /*
3456                                  * The two arguments are swapped because the fbranch instructions
3457                                  * depend on this for the non-sse case to work.
3458                                  */
3459                                 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3460                                 break;
3461                         }
3462                         if (cfg->opt & MONO_OPT_FCMOV) {
3463                                 amd64_fcomip (code, 1);
3464                                 amd64_fstp (code, 0);
3465                                 break;
3466                         }
3467                         /* this overwrites EAX */
3468                         EMIT_FPCOMPARE(code);
3469                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3470                         break;
3471                 case OP_FCEQ:
3472                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3473                                 /* zeroing the register at the start results in
3474                                  * shorter and faster code (we can also remove the widening op)
3475                                  */
3476                                 guchar *unordered_check;
3477                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3478
3479                                 if (use_sse2)
3480                                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3481                                 else {
3482                                         amd64_fcomip (code, 1);
3483                                         amd64_fstp (code, 0);
3484                                 }
3485                                 unordered_check = code;
3486                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3487                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3488                                 amd64_patch (unordered_check, code);
3489                                 break;
3490                         }
3491                         if (ins->dreg != AMD64_RAX)
3492                                 amd64_push_reg (code, AMD64_RAX);
3493
3494                         EMIT_FPCOMPARE(code);
3495                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3496                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3497                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3498                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3499
3500                         if (ins->dreg != AMD64_RAX)
3501                                 amd64_pop_reg (code, AMD64_RAX);
3502                         break;
3503                 case OP_FCLT:
3504                 case OP_FCLT_UN:
3505                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3506                                 /* zeroing the register at the start results in
3507                                  * shorter and faster code (we can also remove the widening op)
3508                                  */
3509                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3510                                 if (use_sse2)
3511                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3512                                 else {
3513                                         amd64_fcomip (code, 1);
3514                                         amd64_fstp (code, 0);
3515                                 }
3516                                 if (ins->opcode == OP_FCLT_UN) {
3517                                         guchar *unordered_check = code;
3518                                         guchar *jump_to_end;
3519                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3520                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3521                                         jump_to_end = code;
3522                                         x86_jump8 (code, 0);
3523                                         amd64_patch (unordered_check, code);
3524                                         amd64_inc_reg (code, ins->dreg);
3525                                         amd64_patch (jump_to_end, code);
3526                                 } else {
3527                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3528                                 }
3529                                 break;
3530                         }
3531                         if (ins->dreg != AMD64_RAX)
3532                                 amd64_push_reg (code, AMD64_RAX);
3533
3534                         EMIT_FPCOMPARE(code);
3535                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3536                         if (ins->opcode == OP_FCLT_UN) {
3537                                 guchar *is_not_zero_check, *end_jump;
3538                                 is_not_zero_check = code;
3539                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3540                                 end_jump = code;
3541                                 x86_jump8 (code, 0);
3542                                 amd64_patch (is_not_zero_check, code);
3543                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3544
3545                                 amd64_patch (end_jump, code);
3546                         }
3547                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3548                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3549
3550                         if (ins->dreg != AMD64_RAX)
3551                                 amd64_pop_reg (code, AMD64_RAX);
3552                         break;
3553                 case OP_FCGT:
3554                 case OP_FCGT_UN:
3555                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3556                                 /* zeroing the register at the start results in
3557                                  * shorter and faster code (we can also remove the widening op)
3558                                  */
3559                                 guchar *unordered_check;
3560                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3561                                 if (use_sse2)
3562                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3563                                 else {
3564                                         amd64_fcomip (code, 1);
3565                                         amd64_fstp (code, 0);
3566                                 }
3567                                 if (ins->opcode == OP_FCGT) {
3568                                         unordered_check = code;
3569                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3570                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3571                                         amd64_patch (unordered_check, code);
3572                                 } else {
3573                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3574                                 }
3575                                 break;
3576                         }
3577                         if (ins->dreg != AMD64_RAX)
3578                                 amd64_push_reg (code, AMD64_RAX);
3579
3580                         EMIT_FPCOMPARE(code);
3581                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3582                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3583                         if (ins->opcode == OP_FCGT_UN) {
3584                                 guchar *is_not_zero_check, *end_jump;
3585                                 is_not_zero_check = code;
3586                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3587                                 end_jump = code;
3588                                 x86_jump8 (code, 0);
3589                                 amd64_patch (is_not_zero_check, code);
3590                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3591
3592                                 amd64_patch (end_jump, code);
3593                         }
3594                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3595                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3596
3597                         if (ins->dreg != AMD64_RAX)
3598                                 amd64_pop_reg (code, AMD64_RAX);
3599                         break;
3600                 case OP_FCLT_MEMBASE:
3601                 case OP_FCGT_MEMBASE:
3602                 case OP_FCLT_UN_MEMBASE:
3603                 case OP_FCGT_UN_MEMBASE:
3604                 case OP_FCEQ_MEMBASE: {
3605                         guchar *unordered_check, *jump_to_end;
3606                         int x86_cond;
3607                         g_assert (use_sse2);
3608
3609                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3610                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
3611
3612                         switch (ins->opcode) {
3613                         case OP_FCEQ_MEMBASE:
3614                                 x86_cond = X86_CC_EQ;
3615                                 break;
3616                         case OP_FCLT_MEMBASE:
3617                         case OP_FCLT_UN_MEMBASE:
3618                                 x86_cond = X86_CC_LT;
3619                                 break;
3620                         case OP_FCGT_MEMBASE:
3621                         case OP_FCGT_UN_MEMBASE:
3622                                 x86_cond = X86_CC_GT;
3623                                 break;
3624                         default:
3625                                 g_assert_not_reached ();
3626                         }
3627
3628                         unordered_check = code;
3629                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3630                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
3631
3632                         switch (ins->opcode) {
3633                         case OP_FCEQ_MEMBASE:
3634                         case OP_FCLT_MEMBASE:
3635                         case OP_FCGT_MEMBASE:
3636                                 amd64_patch (unordered_check, code);
3637                                 break;
3638                         case OP_FCLT_UN_MEMBASE:
3639                         case OP_FCGT_UN_MEMBASE:
3640                                 jump_to_end = code;
3641                                 x86_jump8 (code, 0);
3642                                 amd64_patch (unordered_check, code);
3643                                 amd64_inc_reg (code, ins->dreg);
3644                                 amd64_patch (jump_to_end, code);
3645                                 break;
3646                         default:
3647                                 break;
3648                         }
3649                         break;
3650                 }
3651                 case OP_FBEQ:
3652                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3653                                 guchar *jump = code;
3654                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
3655                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3656                                 amd64_patch (jump, code);
3657                                 break;
3658                         }
3659                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3660                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3661                         break;
3662                 case OP_FBNE_UN:
3663                         /* Branch if C013 != 100 */
3664                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3665                                 /* branch if !ZF or (PF|CF) */
3666                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3667                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3668                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3669                                 break;
3670                         }
3671                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3672                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3673                         break;
3674                 case OP_FBLT:
3675                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3676                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3677                                 break;
3678                         }
3679                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3680                         break;
3681                 case OP_FBLT_UN:
3682                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3683                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3684                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3685                                 break;
3686                         }
3687                         if (ins->opcode == OP_FBLT_UN) {
3688                                 guchar *is_not_zero_check, *end_jump;
3689                                 is_not_zero_check = code;
3690                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3691                                 end_jump = code;
3692                                 x86_jump8 (code, 0);
3693                                 amd64_patch (is_not_zero_check, code);
3694                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3695
3696                                 amd64_patch (end_jump, code);
3697                         }
3698                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3699                         break;
3700                 case OP_FBGT:
3701                 case OP_FBGT_UN:
3702                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3703                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3704                                 break;
3705                         }
3706                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3707                         if (ins->opcode == OP_FBGT_UN) {
3708                                 guchar *is_not_zero_check, *end_jump;
3709                                 is_not_zero_check = code;
3710                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3711                                 end_jump = code;
3712                                 x86_jump8 (code, 0);
3713                                 amd64_patch (is_not_zero_check, code);
3714                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3715
3716                                 amd64_patch (end_jump, code);
3717                         }
3718                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3719                         break;
3720                 case OP_FBGE:
3721                         /* Branch if C013 == 100 or 001 */
3722                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3723                                 guchar *br1;
3724
3725                                 /* skip branch if C1=1 */
3726                                 br1 = code;
3727                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3728                                 /* branch if (C0 | C3) = 1 */
3729                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3730                                 amd64_patch (br1, code);
3731                                 break;
3732                         }
3733                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3734                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3735                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3736                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3737                         break;
3738                 case OP_FBGE_UN:
3739                         /* Branch if C013 == 000 */
3740                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3741                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3742                                 break;
3743                         }
3744                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3745                         break;
3746                 case OP_FBLE:
3747                         /* Branch if C013=000 or 100 */
3748                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3749                                 guchar *br1;
3750
3751                                 /* skip branch if C1=1 */
3752                                 br1 = code;
3753                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3754                                 /* branch if C0=0 */
3755                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3756                                 amd64_patch (br1, code);
3757                                 break;
3758                         }
3759                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, (X86_FP_C0|X86_FP_C1));
3760                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
3761                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3762                         break;
3763                 case OP_FBLE_UN:
3764                         /* Branch if C013 != 001 */
3765                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3766                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3767                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3768                                 break;
3769                         }
3770                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3771                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3772                         break;
3773                 case CEE_CKFINITE: {
3774                         if (use_sse2) {
3775                                 /* Transfer value to the fp stack */
3776                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
3777                                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
3778                                 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
3779                         }
3780                         amd64_push_reg (code, AMD64_RAX);
3781                         amd64_fxam (code);
3782                         amd64_fnstsw (code);
3783                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
3784                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3785                         amd64_pop_reg (code, AMD64_RAX);
3786                         if (use_sse2) {
3787                                 amd64_fstp (code, 0);
3788                         }
3789                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3790                         if (use_sse2)
3791                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3792                         break;
3793                 }
3794                 case OP_TLS_GET: {
3795                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
3796                         break;
3797                 }
3798                 case OP_MEMORY_BARRIER: {
3799                         /* Not needed on amd64 */
3800                         break;
3801                 }
3802                 case OP_ATOMIC_ADD_I4:
3803                 case OP_ATOMIC_ADD_I8: {
3804                         int dreg = ins->dreg;
3805                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
3806
3807                         if (dreg == ins->inst_basereg)
3808                                 dreg = AMD64_R11;
3809
3810                         if (dreg != ins->sreg2)
3811                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
3812
3813                         x86_prefix (code, X86_LOCK_PREFIX);
3814                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3815
3816                         if (dreg != ins->dreg)
3817                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3818
3819                         break;
3820                 }
3821                 case OP_ATOMIC_ADD_NEW_I4:
3822                 case OP_ATOMIC_ADD_NEW_I8: {
3823                         int dreg = ins->dreg;
3824                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
3825
3826                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
3827                                 dreg = AMD64_R11;
3828
3829                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
3830                         amd64_prefix (code, X86_LOCK_PREFIX);
3831                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3832                         /* dreg contains the old value, add with sreg2 value */
3833                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
3834
3835                         if (ins->dreg != dreg)
3836                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3837
3838                         break;
3839                 }
3840                 case OP_ATOMIC_EXCHANGE_I4:
3841                 case OP_ATOMIC_EXCHANGE_I8: {
3842                         guchar *br[2];
3843                         int sreg2 = ins->sreg2;
3844                         int breg = ins->inst_basereg;
3845                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
3846
3847                         /*
3848                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
3849                          * an explanation of how this works.
3850                          */
3851
3852                         /* cmpxchg uses eax as comperand, need to make sure we can use it
3853                          * hack to overcome limits in x86 reg allocator
3854                          * (req: dreg == eax and sreg2 != eax and breg != eax)
3855                          */
3856                         if (ins->dreg != AMD64_RAX)
3857                                 amd64_push_reg (code, AMD64_RAX);
3858
3859                         /* We need the EAX reg for the cmpxchg */
3860                         if (ins->sreg2 == AMD64_RAX) {
3861                                 amd64_push_reg (code, AMD64_RDX);
3862                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
3863                                 sreg2 = AMD64_RDX;
3864                         }
3865
3866                         if (breg == AMD64_RAX) {
3867                                 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, size);
3868                                 breg = AMD64_R11;
3869                         }
3870
3871                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
3872
3873                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
3874                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
3875                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
3876                         amd64_patch (br [1], br [0]);
3877
3878                         if (ins->dreg != AMD64_RAX) {
3879                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
3880                                 amd64_pop_reg (code, AMD64_RAX);
3881                         }
3882
3883                         if (ins->sreg2 != sreg2)
3884                                 amd64_pop_reg (code, AMD64_RDX);
3885
3886                         break;
3887                 }
3888                 default:
3889                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3890                         g_assert_not_reached ();
3891                 }
3892
3893                 if ((code - cfg->native_code - offset) > max_len) {
3894                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3895                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3896                         g_assert_not_reached ();
3897                 }
3898
3899                 cpos += max_len;
3900
3901                 last_ins = ins;
3902                 last_offset = offset;
3903
3904                 ins = ins->next;
3905         }
3906
3907         cfg->code_len = code - cfg->native_code;
3908 }
3909
3910 void
3911 mono_arch_register_lowlevel_calls (void)
3912 {
3913 }
3914
3915 void
3916 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3917 {
3918         MonoJumpInfo *patch_info;
3919         gboolean compile_aot = !run_cctors;
3920
3921         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3922                 unsigned char *ip = patch_info->ip.i + code;
3923                 const unsigned char *target;
3924
3925                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3926
3927                 if (compile_aot) {
3928                         switch (patch_info->type) {
3929                         case MONO_PATCH_INFO_BB:
3930                         case MONO_PATCH_INFO_LABEL:
3931                                 break;
3932                         default:
3933                                 /* No need to patch these */
3934                                 continue;
3935                         }
3936                 }
3937
3938                 switch (patch_info->type) {
3939                 case MONO_PATCH_INFO_NONE:
3940                         continue;
3941                 case MONO_PATCH_INFO_CLASS_INIT: {
3942                         /* Might already been changed to a nop */
3943                         guint8* ip2 = ip;
3944                         amd64_call_code (ip2, 0);
3945                         break;
3946                 }
3947                 case MONO_PATCH_INFO_METHOD_REL:
3948                 case MONO_PATCH_INFO_R8:
3949                 case MONO_PATCH_INFO_R4:
3950                         g_assert_not_reached ();
3951                         continue;
3952                 case MONO_PATCH_INFO_BB:
3953                         break;
3954                 default:
3955                         break;
3956                 }
3957                 amd64_patch (ip, (gpointer)target);
3958         }
3959 }
3960
3961 guint8 *
3962 mono_arch_emit_prolog (MonoCompile *cfg)
3963 {
3964         MonoMethod *method = cfg->method;
3965         MonoBasicBlock *bb;
3966         MonoMethodSignature *sig;
3967         MonoInst *inst;
3968         int alloc_size, pos, max_offset, i, quad;
3969         guint8 *code;
3970         CallInfo *cinfo;
3971         gint32 lmf_offset = cfg->arch.lmf_offset;
3972
3973         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
3974         code = cfg->native_code = g_malloc (cfg->code_size);
3975
3976         /* Amount of stack space allocated by register saving code */
3977         pos = 0;
3978
3979         /*
3980          * The prolog consists of the following parts:
3981          * FP present:
3982          * - push rbp, mov rbp, rsp
3983          * - save callee saved regs using pushes
3984          * - allocate frame
3985          * - save lmf if needed
3986          * FP not present:
3987          * - allocate frame
3988          * - save lmf if needed
3989          * - save callee saved regs using moves
3990          */
3991
3992         if (!cfg->arch.omit_fp) {
3993                 amd64_push_reg (code, AMD64_RBP);
3994                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
3995         }
3996
3997         /* Save callee saved registers */
3998         if (!cfg->arch.omit_fp && !method->save_lmf) {
3999                 for (i = 0; i < AMD64_NREG; ++i)
4000                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4001                                 amd64_push_reg (code, i);
4002                                 pos += sizeof (gpointer);
4003                         }
4004         }
4005
4006         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4007
4008         alloc_size -= pos;
4009
4010         if (cfg->arch.omit_fp)
4011                 /*
4012                  * On enter, the stack is misaligned by the the pushing of the return
4013                  * address. It is either made aligned by the pushing of %rbp, or by
4014                  * this.
4015                  */
4016                 alloc_size += 8;
4017
4018         cfg->arch.stack_alloc_size = alloc_size;
4019
4020         /* Allocate stack frame */
4021         if (alloc_size) {
4022                 /* See mono_emit_stack_alloc */
4023 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4024                 guint32 remaining_size = alloc_size;
4025                 while (remaining_size >= 0x1000) {
4026                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4027                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4028                         remaining_size -= 0x1000;
4029                 }
4030                 if (remaining_size)
4031                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4032 #else
4033                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4034 #endif
4035         }
4036
4037         /* Stack alignment check */
4038 #if 0
4039         {
4040                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4041                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4042                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4043                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4044                 amd64_breakpoint (code);
4045         }
4046 #endif
4047
4048         /* Save LMF */
4049         if (method->save_lmf) {
4050                 /* Save ip */
4051                 amd64_lea_membase (code, AMD64_R11, AMD64_RIP, 0);
4052                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, 8);
4053                 /* Save fp */
4054                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), AMD64_RBP, 8);
4055                 /* Save sp */
4056                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4057                 /* Save method */
4058                 /* FIXME: add a relocation for this */
4059                 if (IS_IMM32 (cfg->method))
4060                         amd64_mov_membase_imm (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), (guint64)cfg->method, 8);
4061                 else {
4062                         amd64_mov_reg_imm (code, AMD64_R11, cfg->method);
4063                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), AMD64_R11, 8);
4064                 }
4065                 /* Save callee saved regs */
4066                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4067                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4068                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4069                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4070                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4071         }
4072
4073         /* Save callee saved registers */
4074         if (cfg->arch.omit_fp && !method->save_lmf) {
4075                 gint32 save_area_offset = 0;
4076
4077                 /* Save caller saved registers after sp is adjusted */
4078                 /* The registers are saved at the bottom of the frame */
4079                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4080                 for (i = 0; i < AMD64_NREG; ++i)
4081                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4082                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4083                                 save_area_offset += 8;
4084                         }
4085         }
4086
4087         /* compute max_offset in order to use short forward jumps */
4088         max_offset = 0;
4089         if (cfg->opt & MONO_OPT_BRANCH) {
4090                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4091                         MonoInst *ins = bb->code;
4092                         bb->max_offset = max_offset;
4093
4094                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4095                                 max_offset += 6;
4096                         /* max alignment for loops */
4097                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4098                                 max_offset += LOOP_ALIGNMENT;
4099
4100                         while (ins) {
4101                                 if (ins->opcode == OP_LABEL)
4102                                         ins->inst_c1 = max_offset;
4103
4104                                 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
4105                                 ins = ins->next;
4106                         }
4107                 }
4108         }
4109
4110         sig = mono_method_signature (method);
4111         pos = 0;
4112
4113         cinfo = get_call_info (sig, FALSE);
4114
4115         if (sig->ret->type != MONO_TYPE_VOID) {
4116                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
4117                         /* Save volatile arguments to the stack */
4118                         amd64_mov_membase_reg (code, cfg->ret->inst_basereg, cfg->ret->inst_offset, cinfo->ret.reg, 8);
4119                 }
4120         }
4121
4122         /* Keep this in sync with emit_load_volatile_arguments */
4123         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4124                 ArgInfo *ainfo = cinfo->args + i;
4125                 gint32 stack_offset;
4126                 MonoType *arg_type;
4127                 inst = cfg->varinfo [i];
4128
4129                 if (sig->hasthis && (i == 0))
4130                         arg_type = &mono_defaults.object_class->byval_arg;
4131                 else
4132                         arg_type = sig->params [i - sig->hasthis];
4133
4134                 stack_offset = ainfo->offset + ARGS_OFFSET;
4135
4136                 /* Save volatile arguments to the stack */
4137                 if (inst->opcode != OP_REGVAR) {
4138                         switch (ainfo->storage) {
4139                         case ArgInIReg: {
4140                                 guint32 size = 8;
4141
4142                                 /* FIXME: I1 etc */
4143                                 /*
4144                                 if (stack_offset & 0x1)
4145                                         size = 1;
4146                                 else if (stack_offset & 0x2)
4147                                         size = 2;
4148                                 else if (stack_offset & 0x4)
4149                                         size = 4;
4150                                 else
4151                                         size = 8;
4152                                 */
4153                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, size);
4154                                 break;
4155                         }
4156                         case ArgInFloatSSEReg:
4157                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4158                                 break;
4159                         case ArgInDoubleSSEReg:
4160                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4161                                 break;
4162                         case ArgValuetypeInReg:
4163                                 for (quad = 0; quad < 2; quad ++) {
4164                                         switch (ainfo->pair_storage [quad]) {
4165                                         case ArgInIReg:
4166                                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4167                                                 break;
4168                                         case ArgInFloatSSEReg:
4169                                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4170                                                 break;
4171                                         case ArgInDoubleSSEReg:
4172                                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4173                                                 break;
4174                                         case ArgNone:
4175                                                 break;
4176                                         default:
4177                                                 g_assert_not_reached ();
4178                                         }
4179                                 }
4180                                 break;
4181                         default:
4182                                 break;
4183                         }
4184                 }
4185
4186                 if (inst->opcode == OP_REGVAR) {
4187                         /* Argument allocated to (non-volatile) register */
4188                         switch (ainfo->storage) {
4189                         case ArgInIReg:
4190                                 amd64_mov_reg_reg (code, inst->dreg, ainfo->reg, 8);
4191                                 break;
4192                         case ArgOnStack:
4193                                 amd64_mov_reg_membase (code, inst->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4194                                 break;
4195                         default:
4196                                 g_assert_not_reached ();
4197                         }
4198                 }
4199         }
4200
4201         if (method->save_lmf) {
4202                 if (lmf_tls_offset != -1) {
4203                         /* Load lmf quicky using the FS register */
4204                         code = emit_tls_get (code, AMD64_RAX, lmf_tls_offset);
4205                 }
4206                 else {
4207                         /*
4208                          * The call might clobber argument registers, but they are already
4209                          * saved to the stack/global regs.
4210                          */
4211
4212                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4213                                                                  (gpointer)"mono_get_lmf_addr");
4214                 }
4215
4216                 /* Save lmf_addr */
4217                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4218                 /* Save previous_lmf */
4219                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4220                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4221                 /* Set new lmf */
4222                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4223                 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4224         }
4225
4226
4227         g_free (cinfo);
4228
4229         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4230                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4231
4232         cfg->code_len = code - cfg->native_code;
4233
4234         g_assert (cfg->code_len < cfg->code_size);
4235
4236         return code;
4237 }
4238
4239 void
4240 mono_arch_emit_epilog (MonoCompile *cfg)
4241 {
4242         MonoMethod *method = cfg->method;
4243         int quad, pos, i;
4244         guint8 *code;
4245         int max_epilog_size = 16;
4246         CallInfo *cinfo;
4247         gint32 lmf_offset = cfg->arch.lmf_offset;
4248
4249         if (cfg->method->save_lmf)
4250                 max_epilog_size += 256;
4251
4252         if (mono_jit_trace_calls != NULL)
4253                 max_epilog_size += 50;
4254
4255         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4256                 max_epilog_size += 50;
4257
4258         max_epilog_size += (AMD64_NREG * 2);
4259
4260         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4261                 cfg->code_size *= 2;
4262                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4263                 mono_jit_stats.code_reallocs++;
4264         }
4265
4266         code = cfg->native_code + cfg->code_len;
4267
4268         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4269                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4270
4271         /* the code restoring the registers must be kept in sync with CEE_JMP */
4272         pos = 0;
4273
4274         if (method->save_lmf) {
4275                 /* Restore previous lmf */
4276                 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4277                 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4278                 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4279
4280                 /* Restore caller saved regs */
4281                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4282                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), 8);
4283                 }
4284                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4285                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4286                 }
4287                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4288                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4289                 }
4290                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4291                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4292                 }
4293                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4294                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4295                 }
4296                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4297                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4298                 }
4299         } else {
4300
4301                 if (cfg->arch.omit_fp) {
4302                         gint32 save_area_offset = 0;
4303
4304                         for (i = 0; i < AMD64_NREG; ++i)
4305                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4306                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4307                                         save_area_offset += 8;
4308                                 }
4309                 }
4310                 else {
4311                         for (i = 0; i < AMD64_NREG; ++i)
4312                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4313                                         pos -= sizeof (gpointer);
4314
4315                         if (pos) {
4316                                 if (pos == - sizeof (gpointer)) {
4317                                         /* Only one register, so avoid lea */
4318                                         for (i = AMD64_NREG - 1; i > 0; --i)
4319                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4320                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4321                                                 }
4322                                 }
4323                                 else {
4324                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4325
4326                                         /* Pop registers in reverse order */
4327                                         for (i = AMD64_NREG - 1; i > 0; --i)
4328                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4329                                                         amd64_pop_reg (code, i);
4330                                                 }
4331                                 }
4332                         }
4333                 }
4334         }
4335
4336         /* Load returned vtypes into registers if needed */
4337         cinfo = get_call_info (mono_method_signature (method), FALSE);
4338         if (cinfo->ret.storage == ArgValuetypeInReg) {
4339                 ArgInfo *ainfo = &cinfo->ret;
4340                 MonoInst *inst = cfg->ret;
4341
4342                 for (quad = 0; quad < 2; quad ++) {
4343                         switch (ainfo->pair_storage [quad]) {
4344                         case ArgInIReg:
4345                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
4346                                 break;
4347                         case ArgInFloatSSEReg:
4348                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4349                                 break;
4350                         case ArgInDoubleSSEReg:
4351                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4352                                 break;
4353                         case ArgNone:
4354                                 break;
4355                         default:
4356                                 g_assert_not_reached ();
4357                         }
4358                 }
4359         }
4360         g_free (cinfo);
4361
4362         if (cfg->arch.omit_fp) {
4363                 if (cfg->arch.stack_alloc_size)
4364                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4365         } else {
4366                 amd64_leave (code);
4367         }
4368         amd64_ret (code);
4369
4370         cfg->code_len = code - cfg->native_code;
4371
4372         g_assert (cfg->code_len < cfg->code_size);
4373
4374         if (cfg->arch.omit_fp) {
4375                 /*
4376                  * Encode the stack size into used_int_regs so the exception handler
4377                  * can access it.
4378                  */
4379                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
4380                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
4381         }
4382 }
4383
4384 void
4385 mono_arch_emit_exceptions (MonoCompile *cfg)
4386 {
4387         MonoJumpInfo *patch_info;
4388         int nthrows, i;
4389         guint8 *code;
4390         MonoClass *exc_classes [16];
4391         guint8 *exc_throw_start [16], *exc_throw_end [16];
4392         guint32 code_size = 0;
4393
4394         /* Compute needed space */
4395         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4396                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4397                         code_size += 40;
4398                 if (patch_info->type == MONO_PATCH_INFO_R8)
4399                         code_size += 8 + 7; /* sizeof (double) + alignment */
4400                 if (patch_info->type == MONO_PATCH_INFO_R4)
4401                         code_size += 4 + 7; /* sizeof (float) + alignment */
4402         }
4403
4404         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4405                 cfg->code_size *= 2;
4406                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4407                 mono_jit_stats.code_reallocs++;
4408         }
4409
4410         code = cfg->native_code + cfg->code_len;
4411
4412         /* add code to raise exceptions */
4413         nthrows = 0;
4414         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4415                 switch (patch_info->type) {
4416                 case MONO_PATCH_INFO_EXC: {
4417                         MonoClass *exc_class;
4418                         guint8 *buf, *buf2;
4419                         guint32 throw_ip;
4420
4421                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
4422
4423                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4424                         g_assert (exc_class);
4425                         throw_ip = patch_info->ip.i;
4426
4427                         //x86_breakpoint (code);
4428                         /* Find a throw sequence for the same exception class */
4429                         for (i = 0; i < nthrows; ++i)
4430                                 if (exc_classes [i] == exc_class)
4431                                         break;
4432                         if (i < nthrows) {
4433                                 amd64_mov_reg_imm (code, AMD64_RSI, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4434                                 x86_jump_code (code, exc_throw_start [i]);
4435                                 patch_info->type = MONO_PATCH_INFO_NONE;
4436                         }
4437                         else {
4438                                 buf = code;
4439                                 amd64_mov_reg_imm_size (code, AMD64_RSI, 0xf0f0f0f0, 4);
4440                                 buf2 = code;
4441
4442                                 if (nthrows < 16) {
4443                                         exc_classes [nthrows] = exc_class;
4444                                         exc_throw_start [nthrows] = code;
4445                                 }
4446
4447                                 amd64_mov_reg_imm (code, AMD64_RDI, exc_class->type_token);
4448                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4449                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4450                                 patch_info->ip.i = code - cfg->native_code;
4451
4452                                 if (cfg->compile_aot) {
4453                                         amd64_mov_reg_membase (code, GP_SCRATCH_REG, AMD64_RIP, 0, 8);
4454                                         amd64_call_reg (code, GP_SCRATCH_REG);
4455                                 } else {
4456                                         /* The callee is in memory allocated using the code manager */
4457                                         amd64_call_code (code, 0);
4458                                 }
4459
4460                                 amd64_mov_reg_imm (buf, AMD64_RSI, (code - cfg->native_code) - throw_ip);
4461                                 while (buf < buf2)
4462                                         x86_nop (buf);
4463
4464                                 if (nthrows < 16) {
4465                                         exc_throw_end [nthrows] = code;
4466                                         nthrows ++;
4467                                 }
4468                         }
4469                         break;
4470                 }
4471                 default:
4472                         /* do nothing */
4473                         break;
4474                 }
4475         }
4476
4477         /* Handle relocations with RIP relative addressing */
4478         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4479                 gboolean remove = FALSE;
4480
4481                 switch (patch_info->type) {
4482                 case MONO_PATCH_INFO_R8: {
4483                         guint8 *pos;
4484
4485                         code = (guint8*)ALIGN_TO (code, 8);
4486
4487                         pos = cfg->native_code + patch_info->ip.i;
4488
4489                         *(double*)code = *(double*)patch_info->data.target;
4490
4491                         if (use_sse2)
4492                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4493                         else
4494                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4495                         code += 8;
4496
4497                         remove = TRUE;
4498                         break;
4499                 }
4500                 case MONO_PATCH_INFO_R4: {
4501                         guint8 *pos;
4502
4503                         code = (guint8*)ALIGN_TO (code, 8);
4504
4505                         pos = cfg->native_code + patch_info->ip.i;
4506
4507                         *(float*)code = *(float*)patch_info->data.target;
4508
4509                         if (use_sse2)
4510                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4511                         else
4512                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4513                         code += 4;
4514
4515                         remove = TRUE;
4516                         break;
4517                 }
4518                 default:
4519                         break;
4520                 }
4521
4522                 if (remove) {
4523                         if (patch_info == cfg->patch_info)
4524                                 cfg->patch_info = patch_info->next;
4525                         else {
4526                                 MonoJumpInfo *tmp;
4527
4528                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
4529                                         ;
4530                                 tmp->next = patch_info->next;
4531                         }
4532                 }
4533         }
4534
4535         cfg->code_len = code - cfg->native_code;
4536
4537         g_assert (cfg->code_len < cfg->code_size);
4538
4539 }
4540
4541 void*
4542 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4543 {
4544         guchar *code = p;
4545         CallInfo *cinfo = NULL;
4546         MonoMethodSignature *sig;
4547         MonoInst *inst;
4548         int i, n, stack_area = 0;
4549
4550         /* Keep this in sync with mono_arch_get_argument_info */
4551
4552         if (enable_arguments) {
4553                 /* Allocate a new area on the stack and save arguments there */
4554                 sig = mono_method_signature (cfg->method);
4555
4556                 cinfo = get_call_info (sig, FALSE);
4557
4558                 n = sig->param_count + sig->hasthis;
4559
4560                 stack_area = ALIGN_TO (n * 8, 16);
4561
4562                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
4563
4564                 for (i = 0; i < n; ++i) {
4565                         inst = cfg->varinfo [i];
4566
4567                         if (inst->opcode == OP_REGVAR)
4568                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
4569                         else {
4570                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
4571                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
4572                         }
4573                 }
4574         }
4575
4576         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4577         amd64_set_reg_template (code, AMD64_RDI);
4578         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RSP, 8);
4579         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4580
4581         if (enable_arguments) {
4582                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
4583
4584                 g_free (cinfo);
4585         }
4586
4587         return code;
4588 }
4589
4590 enum {
4591         SAVE_NONE,
4592         SAVE_STRUCT,
4593         SAVE_EAX,
4594         SAVE_EAX_EDX,
4595         SAVE_XMM
4596 };
4597
4598 void*
4599 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4600 {
4601         guchar *code = p;
4602         int save_mode = SAVE_NONE;
4603         MonoMethod *method = cfg->method;
4604         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
4605
4606         switch (rtype) {
4607         case MONO_TYPE_VOID:
4608                 /* special case string .ctor icall */
4609                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4610                         save_mode = SAVE_EAX;
4611                 else
4612                         save_mode = SAVE_NONE;
4613                 break;
4614         case MONO_TYPE_I8:
4615         case MONO_TYPE_U8:
4616                 save_mode = SAVE_EAX;
4617                 break;
4618         case MONO_TYPE_R4:
4619         case MONO_TYPE_R8:
4620                 save_mode = SAVE_XMM;
4621                 break;
4622         case MONO_TYPE_GENERICINST:
4623                 if (mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
4624                         save_mode = SAVE_EAX;
4625                         break;
4626                 }
4627                 /* Fall through */
4628         case MONO_TYPE_VALUETYPE:
4629                 save_mode = SAVE_STRUCT;
4630                 break;
4631         default:
4632                 save_mode = SAVE_EAX;
4633                 break;
4634         }
4635
4636         /* Save the result and copy it into the proper argument register */
4637         switch (save_mode) {
4638         case SAVE_EAX:
4639                 amd64_push_reg (code, AMD64_RAX);
4640                 /* Align stack */
4641                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4642                 if (enable_arguments)
4643                         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RAX, 8);
4644                 break;
4645         case SAVE_STRUCT:
4646                 /* FIXME: */
4647                 if (enable_arguments)
4648                         amd64_mov_reg_imm (code, AMD64_RSI, 0);
4649                 break;
4650         case SAVE_XMM:
4651                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4652                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
4653                 /* Align stack */
4654                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4655                 /*
4656                  * The result is already in the proper argument register so no copying
4657                  * needed.
4658                  */
4659                 break;
4660         case SAVE_NONE:
4661                 break;
4662         default:
4663                 g_assert_not_reached ();
4664         }
4665
4666         /* Set %al since this is a varargs call */
4667         if (save_mode == SAVE_XMM)
4668                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
4669         else
4670                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
4671
4672         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
4673         amd64_set_reg_template (code, AMD64_RDI);
4674         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4675
4676         /* Restore result */
4677         switch (save_mode) {
4678         case SAVE_EAX:
4679                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4680                 amd64_pop_reg (code, AMD64_RAX);
4681                 break;
4682         case SAVE_STRUCT:
4683                 /* FIXME: */
4684                 break;
4685         case SAVE_XMM:
4686                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4687                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
4688                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4689                 break;
4690         case SAVE_NONE:
4691                 break;
4692         default:
4693                 g_assert_not_reached ();
4694         }
4695
4696         return code;
4697 }
4698
4699 void
4700 mono_arch_flush_icache (guint8 *code, gint size)
4701 {
4702         /* Not needed */
4703 }
4704
4705 void
4706 mono_arch_flush_register_windows (void)
4707 {
4708 }
4709
4710 gboolean
4711 mono_arch_is_inst_imm (gint64 imm)
4712 {
4713         return amd64_is_imm32 (imm);
4714 }
4715
4716 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
4717
4718 static int reg_to_ucontext_reg [] = {
4719         REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI,
4720         REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15,
4721         REG_RIP
4722 };
4723
4724 /*
4725  * Determine whenever the trap whose info is in SIGINFO is caused by
4726  * integer overflow.
4727  */
4728 gboolean
4729 mono_arch_is_int_overflow (void *sigctx, void *info)
4730 {
4731         ucontext_t *ctx = (ucontext_t*)sigctx;
4732         guint8* rip;
4733         int reg;
4734
4735         rip = (guint8*)ctx->uc_mcontext.gregs [REG_RIP];
4736
4737         if (IS_REX (rip [0])) {
4738                 reg = amd64_rex_b (rip [0]);
4739                 rip ++;
4740         }
4741         else
4742                 reg = 0;
4743
4744         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
4745                 /* idiv REG */
4746                 reg += x86_modrm_rm (rip [1]);
4747
4748                 if (ctx->uc_mcontext.gregs [reg_to_ucontext_reg [reg]] == -1)
4749                         return TRUE;
4750         }
4751
4752         return FALSE;
4753 }
4754
4755 guint32
4756 mono_arch_get_patch_offset (guint8 *code)
4757 {
4758         return 3;
4759 }
4760
4761 gpointer*
4762 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
4763 {
4764         guint32 reg;
4765         guint32 disp;
4766         guint8 rex = 0;
4767
4768         /* go to the start of the call instruction
4769          *
4770          * address_byte = (m << 6) | (o << 3) | reg
4771          * call opcode: 0xff address_byte displacement
4772          * 0xff m=1,o=2 imm8
4773          * 0xff m=2,o=2 imm32
4774          */
4775         code -= 7;
4776
4777         /*
4778          * A given byte sequence can match more than case here, so we have to be
4779          * really careful about the ordering of the cases. Longer sequences
4780          * come first.
4781          */
4782         if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4783                         /*
4784                          * This is a interface call
4785                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
4786                          * ff 10                  callq  *(%rax)
4787                          */
4788                 if (IS_REX (code [4]))
4789                         rex = code [4];
4790                 reg = amd64_modrm_rm (code [6]);
4791                 disp = 0;
4792         }
4793         else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
4794                 /* call OFFSET(%rip) */
4795                 disp = *(guint32*)(code + 3);
4796                 return (gpointer*)(code + disp + 7);
4797         }
4798         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
4799                 /* call *[reg+disp32] */
4800                 if (IS_REX (code [0]))
4801                         rex = code [0];
4802                 reg = amd64_modrm_rm (code [2]);
4803                 disp = *(guint32*)(code + 3);
4804                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4805         }
4806         else if (code [2] == 0xe8) {
4807                 /* call <ADDR> */
4808                 return NULL;
4809         }
4810         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
4811                 /* call *%reg */
4812                 return NULL;
4813         }
4814         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
4815                 /* call *[reg+disp8] */
4816                 if (IS_REX (code [3]))
4817                         rex = code [3];
4818                 reg = amd64_modrm_rm (code [5]);
4819                 disp = *(guint8*)(code + 6);
4820                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4821         }
4822         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4823                         /*
4824                          * This is a interface call: should check the above code can't catch it earlier
4825                          * 8b 40 30   mov    0x30(%eax),%eax
4826                          * ff 10      call   *(%eax)
4827                          */
4828                 if (IS_REX (code [4]))
4829                         rex = code [4];
4830                 reg = amd64_modrm_rm (code [6]);
4831                 disp = 0;
4832         }
4833         else
4834                 g_assert_not_reached ();
4835
4836         reg += amd64_rex_b (rex);
4837
4838         /* R11 is clobbered by the trampoline code */
4839         g_assert (reg != AMD64_R11);
4840
4841         return (gpointer)(((guint64)(regs [reg])) + disp);
4842 }
4843
4844 gpointer*
4845 mono_arch_get_delegate_method_ptr_addr (guint8* code, gpointer *regs)
4846 {
4847         guint32 reg;
4848         guint32 disp;
4849
4850         code -= 10;
4851
4852         if (IS_REX (code [0]) && (code [1] == 0x8b) && (code [3] == 0x48) && (code [4] == 0x8b) && (code [5] == 0x40) && (code [7] == 0x48) && (code [8] == 0xff) && (code [9] == 0xd0)) {
4853                 /* mov REG, %rax; mov <OFFSET>(%rax), %rax; call *%rax */
4854                 reg = amd64_rex_b (code [0]) + amd64_modrm_rm (code [2]);
4855                 disp = code [6];
4856
4857                 if (reg == AMD64_RAX)
4858                         return NULL;
4859                 else
4860                         return (gpointer*)(((guint64)(regs [reg])) + disp);
4861         }
4862
4863         return NULL;
4864 }
4865
4866 /*
4867  * Support for fast access to the thread-local lmf structure using the GS
4868  * segment register on NPTL + kernel 2.6.x.
4869  */
4870
4871 static gboolean tls_offset_inited = FALSE;
4872
4873 void
4874 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4875 {
4876         if (!tls_offset_inited) {
4877                 tls_offset_inited = TRUE;
4878 #ifdef MONO_XEN_OPT
4879                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
4880 #endif
4881                 appdomain_tls_offset = mono_domain_get_tls_offset ();
4882                 lmf_tls_offset = mono_get_lmf_tls_offset ();
4883                 thread_tls_offset = mono_thread_get_tls_offset ();
4884         }
4885 }
4886
4887 void
4888 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4889 {
4890 }
4891
4892 void
4893 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
4894 {
4895         MonoCallInst *call = (MonoCallInst*)inst;
4896         CallInfo * cinfo = get_call_info (inst->signature, FALSE);
4897
4898         if (vt_reg != -1) {
4899                 MonoInst *vtarg;
4900
4901                 if (cinfo->ret.storage == ArgValuetypeInReg) {
4902                         /*
4903                          * The valuetype is in RAX:RDX after the call, need to be copied to
4904                          * the stack. Push the address here, so the call instruction can
4905                          * access it.
4906                          */
4907                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
4908                         vtarg->sreg1 = vt_reg;
4909                         mono_bblock_add_inst (cfg->cbb, vtarg);
4910
4911                         /* Align stack */
4912                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
4913                 }
4914                 else {
4915                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
4916                         vtarg->sreg1 = vt_reg;
4917                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
4918                         mono_bblock_add_inst (cfg->cbb, vtarg);
4919
4920                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
4921                 }
4922         }
4923
4924         /* add the this argument */
4925         if (this_reg != -1) {
4926                 MonoInst *this;
4927                 MONO_INST_NEW (cfg, this, OP_MOVE);
4928                 this->type = this_type;
4929                 this->sreg1 = this_reg;
4930                 this->dreg = mono_regstate_next_int (cfg->rs);
4931                 mono_bblock_add_inst (cfg->cbb, this);
4932
4933                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
4934         }
4935
4936         g_free (cinfo);
4937 }
4938
4939 MonoInst*
4940 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4941 {
4942         MonoInst *ins = NULL;
4943
4944         if (cmethod->klass == mono_defaults.math_class) {
4945                 if (strcmp (cmethod->name, "Sin") == 0) {
4946                         MONO_INST_NEW (cfg, ins, OP_SIN);
4947                         ins->inst_i0 = args [0];
4948                 } else if (strcmp (cmethod->name, "Cos") == 0) {
4949                         MONO_INST_NEW (cfg, ins, OP_COS);
4950                         ins->inst_i0 = args [0];
4951                 } else if (strcmp (cmethod->name, "Tan") == 0) {
4952                         if (use_sse2)
4953                                 return ins;
4954                         MONO_INST_NEW (cfg, ins, OP_TAN);
4955                         ins->inst_i0 = args [0];
4956                 } else if (strcmp (cmethod->name, "Atan") == 0) {
4957                         if (use_sse2)
4958                                 return ins;
4959                         MONO_INST_NEW (cfg, ins, OP_ATAN);
4960                         ins->inst_i0 = args [0];
4961                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
4962                         MONO_INST_NEW (cfg, ins, OP_SQRT);
4963                         ins->inst_i0 = args [0];
4964                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
4965                         MONO_INST_NEW (cfg, ins, OP_ABS);
4966                         ins->inst_i0 = args [0];
4967                 }
4968 #if 0
4969                 /* OP_FREM is not IEEE compatible */
4970                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
4971                         MONO_INST_NEW (cfg, ins, OP_FREM);
4972                         ins->inst_i0 = args [0];
4973                         ins->inst_i1 = args [1];
4974                 }
4975 #endif
4976         } else if (cmethod->klass == mono_defaults.thread_class &&
4977                            strcmp (cmethod->name, "MemoryBarrier") == 0) {
4978                 MONO_INST_NEW (cfg, ins, OP_MEMORY_BARRIER);
4979         } else if(cmethod->klass->image == mono_defaults.corlib &&
4980                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4981                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4982
4983                 if (strcmp (cmethod->name, "Increment") == 0) {
4984                         MonoInst *ins_iconst;
4985                         guint32 opcode;
4986
4987                         if (fsig->params [0]->type == MONO_TYPE_I4)
4988                                 opcode = OP_ATOMIC_ADD_NEW_I4;
4989                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4990                                 opcode = OP_ATOMIC_ADD_NEW_I8;
4991                         else
4992                                 g_assert_not_reached ();
4993                         MONO_INST_NEW (cfg, ins, opcode);
4994                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
4995                         ins_iconst->inst_c0 = 1;
4996
4997                         ins->inst_i0 = args [0];
4998                         ins->inst_i1 = ins_iconst;
4999                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
5000                         MonoInst *ins_iconst;
5001                         guint32 opcode;
5002
5003                         if (fsig->params [0]->type == MONO_TYPE_I4)
5004                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5005                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5006                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5007                         else
5008                                 g_assert_not_reached ();
5009                         MONO_INST_NEW (cfg, ins, opcode);
5010                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5011                         ins_iconst->inst_c0 = -1;
5012
5013                         ins->inst_i0 = args [0];
5014                         ins->inst_i1 = ins_iconst;
5015                 } else if (strcmp (cmethod->name, "Add") == 0) {
5016                         guint32 opcode;
5017
5018                         if (fsig->params [0]->type == MONO_TYPE_I4)
5019                                 opcode = OP_ATOMIC_ADD_I4;
5020                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5021                                 opcode = OP_ATOMIC_ADD_I8;
5022                         else
5023                                 g_assert_not_reached ();
5024
5025                         MONO_INST_NEW (cfg, ins, opcode);
5026
5027                         ins->inst_i0 = args [0];
5028                         ins->inst_i1 = args [1];
5029                 } else if (strcmp (cmethod->name, "Exchange") == 0) {
5030                         guint32 opcode;
5031
5032                         if (fsig->params [0]->type == MONO_TYPE_I4)
5033                                 opcode = OP_ATOMIC_EXCHANGE_I4;
5034                         else if ((fsig->params [0]->type == MONO_TYPE_I8) ||
5035                                          (fsig->params [0]->type == MONO_TYPE_I) ||
5036                                          (fsig->params [0]->type == MONO_TYPE_OBJECT))
5037                                 opcode = OP_ATOMIC_EXCHANGE_I8;
5038                         else
5039                                 return NULL;
5040
5041                         MONO_INST_NEW (cfg, ins, opcode);
5042
5043                         ins->inst_i0 = args [0];
5044                         ins->inst_i1 = args [1];
5045                 } else if (strcmp (cmethod->name, "Read") == 0 && (fsig->params [0]->type == MONO_TYPE_I8)) {
5046                         /* 64 bit reads are already atomic */
5047                         MONO_INST_NEW (cfg, ins, CEE_LDIND_I8);
5048                         ins->inst_i0 = args [0];
5049                 }
5050
5051                 /*
5052                  * Can't implement CompareExchange methods this way since they have
5053                  * three arguments.
5054                  */
5055         }
5056
5057         return ins;
5058 }
5059
5060 gboolean
5061 mono_arch_print_tree (MonoInst *tree, int arity)
5062 {
5063         return 0;
5064 }
5065
5066 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5067 {
5068         MonoInst* ins;
5069
5070         if (appdomain_tls_offset == -1)
5071                 return NULL;
5072
5073         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5074         ins->inst_offset = appdomain_tls_offset;
5075         return ins;
5076 }
5077
5078 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5079 {
5080         MonoInst* ins;
5081
5082         if (thread_tls_offset == -1)
5083                 return NULL;
5084
5085         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5086         ins->inst_offset = thread_tls_offset;
5087         return ins;
5088 }