mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *
  11  * (C) 2003 Ximian, Inc.
  12  */
  13 #include "mini.h"
  14 #include <string.h>
  15 #include <math.h>
  16 #include <unistd.h>
  17
  18 #include <mono/metadata/appdomain.h>
  19 #include <mono/metadata/debug-helpers.h>
  20 #include <mono/metadata/threads.h>
  21 #include <mono/metadata/profiler-private.h>
  22 #include <mono/metadata/mono-debug.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-amd64.h"
  27 #include "inssel.h"
  28 #include "cpu-amd64.h"
  29
  30 static gint lmf_tls_offset = -1;
  31 static gint lmf_addr_tls_offset = -1;
  32 static gint appdomain_tls_offset = -1;
  33 static gint thread_tls_offset = -1;
  34
  35 #ifdef MONO_XEN_OPT
  36 static gboolean optimize_for_xen = TRUE;
  37 #else
  38 #define optimize_for_xen 0
  39 #endif
  40
  41 static gboolean use_sse2 = !MONO_ARCH_USE_FPSTACK;
  42
  43 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  44
  45 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  46
  47 #ifdef PLATFORM_WIN32
  48 /* Under windows, the default pinvoke calling convention is stdcall */
  49 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  50 #else
  51 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  52 #endif
  53
  54 #define ARGS_OFFSET 16
  55 #define GP_SCRATCH_REG AMD64_R11
  56
  57 /*
  58  * AMD64 register usage:
  59  * - callee saved registers are used for global register allocation
  60  * - %r11 is used for materializing 64 bit constants in opcodes
  61  * - the rest is used for local allocation
  62  */
  63
  64 /*
  65  * Floating point comparison results:
  66  *                  ZF PF CF
  67  * A > B            0  0  0
  68  * A < B            0  0  1
  69  * A = B            1  0  0
  70  * A > B            0  0  0
  71  * UNORDERED        1  1  1
  72  */
  73
  74 #define NOT_IMPLEMENTED g_assert_not_reached ()
  75
  76 const char*
  77 mono_arch_regname (int reg) {
  78         switch (reg) {
  79         case AMD64_RAX: return "%rax";
  80         case AMD64_RBX: return "%rbx";
  81         case AMD64_RCX: return "%rcx";
  82         case AMD64_RDX: return "%rdx";
  83         case AMD64_RSP: return "%rsp";
  84         case AMD64_RBP: return "%rbp";
  85         case AMD64_RDI: return "%rdi";
  86         case AMD64_RSI: return "%rsi";
  87         case AMD64_R8: return "%r8";
  88         case AMD64_R9: return "%r9";
  89         case AMD64_R10: return "%r10";
  90         case AMD64_R11: return "%r11";
  91         case AMD64_R12: return "%r12";
  92         case AMD64_R13: return "%r13";
  93         case AMD64_R14: return "%r14";
  94         case AMD64_R15: return "%r15";
  95         }
  96         return "unknown";
  97 }
  98
  99 static const char * xmmregs [] = {
 100         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 101         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 102 };
 103
 104 const char*
 105 mono_arch_fregname (int reg)
 106 {
 107         if (reg < AMD64_XMM_NREG)
 108                 return xmmregs [reg];
 109         else
 110                 return "unknown";
 111 }
 112
 113 G_GNUC_UNUSED static void
 114 break_count (void)
 115 {
 116 }
 117
 118 G_GNUC_UNUSED static gboolean
 119 debug_count (void)
 120 {
 121         static int count = 0;
 122         count ++;
 123
 124         if (!getenv ("COUNT"))
 125                 return TRUE;
 126
 127         if (count == atoi (getenv ("COUNT"))) {
 128                 break_count ();
 129         }
 130
 131         if (count > atoi (getenv ("COUNT"))) {
 132                 return FALSE;
 133         }
 134
 135         return TRUE;
 136 }
 137
 138 static gboolean
 139 debug_omit_fp (void)
 140 {
 141 #if 0
 142         return debug_count ();
 143 #else
 144         return TRUE;
 145 #endif
 146 }
 147
 148 static inline gboolean
 149 amd64_is_near_call (guint8 *code)
 150 {
 151         /* Skip REX */
 152         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 153                 code += 1;
 154
 155         return code [0] == 0xe8;
 156 }
 157
 158 static inline void
 159 amd64_patch (unsigned char* code, gpointer target)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         if ((code [0] & 0xf8) == 0xb8) {
 166                 /* amd64_set_reg_template */
 167                 *(guint64*)(code + 1) = (guint64)target;
 168         }
 169         else if (code [0] == 0x8b) {
 170                 /* mov 0(%rip), %dreg */
 171                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 172         }
 173         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 174                 /* call *<OFFSET>(%rip) */
 175                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 176         }
 177         else if ((code [0] == 0xe8)) {
 178                 /* call <DISP> */
 179                 gint64 disp = (guint8*)target - (guint8*)code;
 180                 g_assert (amd64_is_imm32 (disp));
 181                 x86_patch (code, (unsigned char*)target);
 182         }
 183         else
 184                 x86_patch (code, (unsigned char*)target);
 185 }
 186
 187 typedef enum {
 188         ArgInIReg,
 189         ArgInFloatSSEReg,
 190         ArgInDoubleSSEReg,
 191         ArgOnStack,
 192         ArgValuetypeInReg,
 193         ArgNone /* only in pair_storage */
 194 } ArgStorage;
 195
 196 typedef struct {
 197         gint16 offset;
 198         gint8  reg;
 199         ArgStorage storage;
 200
 201         /* Only if storage == ArgValuetypeInReg */
 202         ArgStorage pair_storage [2];
 203         gint8 pair_regs [2];
 204 } ArgInfo;
 205
 206 typedef struct {
 207         int nargs;
 208         guint32 stack_usage;
 209         guint32 reg_usage;
 210         guint32 freg_usage;
 211         gboolean need_stack_align;
 212         ArgInfo ret;
 213         ArgInfo sig_cookie;
 214         ArgInfo args [1];
 215 } CallInfo;
 216
 217 #define DEBUG(a) if (cfg->verbose_level > 1) a
 218
 219 #define NEW_ICONST(cfg,dest,val) do {   \
 220                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 221                 (dest)->opcode = OP_ICONST;     \
 222                 (dest)->inst_c0 = (val);        \
 223                 (dest)->type = STACK_I4;        \
 224         } while (0)
 225
 226 #define PARAM_REGS 6
 227
 228 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 229
 230 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 231
 232 static void inline
 233 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 234 {
 235     ainfo->offset = *stack_size;
 236
 237     if (*gr >= PARAM_REGS) {
 238                 ainfo->storage = ArgOnStack;
 239                 (*stack_size) += sizeof (gpointer);
 240     }
 241     else {
 242                 ainfo->storage = ArgInIReg;
 243                 ainfo->reg = param_regs [*gr];
 244                 (*gr) ++;
 245     }
 246 }
 247
 248 #define FLOAT_PARAM_REGS 8
 249
 250 static void inline
 251 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 252 {
 253     ainfo->offset = *stack_size;
 254
 255     if (*gr >= FLOAT_PARAM_REGS) {
 256                 ainfo->storage = ArgOnStack;
 257                 (*stack_size) += sizeof (gpointer);
 258     }
 259     else {
 260                 /* A double register */
 261                 if (is_double)
 262                         ainfo->storage = ArgInDoubleSSEReg;
 263                 else
 264                         ainfo->storage = ArgInFloatSSEReg;
 265                 ainfo->reg = *gr;
 266                 (*gr) += 1;
 267     }
 268 }
 269
 270 typedef enum ArgumentClass {
 271         ARG_CLASS_NO_CLASS,
 272         ARG_CLASS_MEMORY,
 273         ARG_CLASS_INTEGER,
 274         ARG_CLASS_SSE
 275 } ArgumentClass;
 276
 277 static ArgumentClass
 278 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 279 {
 280         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 281         MonoType *ptype;
 282
 283         ptype = mono_type_get_underlying_type (type);
 284         switch (ptype->type) {
 285         case MONO_TYPE_BOOLEAN:
 286         case MONO_TYPE_CHAR:
 287         case MONO_TYPE_I1:
 288         case MONO_TYPE_U1:
 289         case MONO_TYPE_I2:
 290         case MONO_TYPE_U2:
 291         case MONO_TYPE_I4:
 292         case MONO_TYPE_U4:
 293         case MONO_TYPE_I:
 294         case MONO_TYPE_U:
 295         case MONO_TYPE_STRING:
 296         case MONO_TYPE_OBJECT:
 297         case MONO_TYPE_CLASS:
 298         case MONO_TYPE_SZARRAY:
 299         case MONO_TYPE_PTR:
 300         case MONO_TYPE_FNPTR:
 301         case MONO_TYPE_ARRAY:
 302         case MONO_TYPE_I8:
 303         case MONO_TYPE_U8:
 304                 class2 = ARG_CLASS_INTEGER;
 305                 break;
 306         case MONO_TYPE_R4:
 307         case MONO_TYPE_R8:
 308                 class2 = ARG_CLASS_SSE;
 309                 break;
 310
 311         case MONO_TYPE_TYPEDBYREF:
 312                 g_assert_not_reached ();
 313
 314         case MONO_TYPE_GENERICINST:
 315                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 316                         class2 = ARG_CLASS_INTEGER;
 317                         break;
 318                 }
 319                 /* fall through */
 320         case MONO_TYPE_VALUETYPE: {
 321                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 322                 int i;
 323
 324                 for (i = 0; i < info->num_fields; ++i) {
 325                         class2 = class1;
 326                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 327                 }
 328                 break;
 329         }
 330         default:
 331                 g_assert_not_reached ();
 332         }
 333
 334         /* Merge */
 335         if (class1 == class2)
 336                 ;
 337         else if (class1 == ARG_CLASS_NO_CLASS)
 338                 class1 = class2;
 339         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 340                 class1 = ARG_CLASS_MEMORY;
 341         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 342                 class1 = ARG_CLASS_INTEGER;
 343         else
 344                 class1 = ARG_CLASS_SSE;
 345
 346         return class1;
 347 }
 348
 349 static void
 350 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 351                gboolean is_return,
 352                guint32 *gr, guint32 *fr, guint32 *stack_size)
 353 {
 354         guint32 size, quad, nquads, i;
 355         ArgumentClass args [2];
 356         MonoMarshalType *info;
 357         MonoClass *klass;
 358
 359         klass = mono_class_from_mono_type (type);
 360         if (sig->pinvoke)
 361                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 362         else
 363                 size = mono_type_stack_size (&klass->byval_arg, NULL);
 364
 365         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 366                 /* Allways pass in memory */
 367                 ainfo->offset = *stack_size;
 368                 *stack_size += ALIGN_TO (size, 8);
 369                 ainfo->storage = ArgOnStack;
 370
 371                 return;
 372         }
 373
 374         /* FIXME: Handle structs smaller than 8 bytes */
 375         //if ((size % 8) != 0)
 376         //      NOT_IMPLEMENTED;
 377
 378         if (size > 8)
 379                 nquads = 2;
 380         else
 381                 nquads = 1;
 382
 383         /*
 384          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 385          * The X87 and SSEUP stuff is left out since there are no such types in
 386          * the CLR.
 387          */
 388         info = mono_marshal_load_type_info (klass);
 389         g_assert (info);
 390         if (info->native_size > 16) {
 391                 ainfo->offset = *stack_size;
 392                 *stack_size += ALIGN_TO (info->native_size, 8);
 393                 ainfo->storage = ArgOnStack;
 394
 395                 return;
 396         }
 397
 398         args [0] = ARG_CLASS_NO_CLASS;
 399         args [1] = ARG_CLASS_NO_CLASS;
 400         for (quad = 0; quad < nquads; ++quad) {
 401                 int size;
 402                 guint32 align;
 403                 ArgumentClass class1;
 404
 405                 class1 = ARG_CLASS_NO_CLASS;
 406                 for (i = 0; i < info->num_fields; ++i) {
 407                         size = mono_marshal_type_size (info->fields [i].field->type,
 408                                                                                    info->fields [i].mspec,
 409                                                                                    &align, TRUE, klass->unicode);
 410                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 411                                 /* Unaligned field */
 412                                 NOT_IMPLEMENTED;
 413                         }
 414
 415                         /* Skip fields in other quad */
 416                         if ((quad == 0) && (info->fields [i].offset >= 8))
 417                                 continue;
 418                         if ((quad == 1) && (info->fields [i].offset < 8))
 419                                 continue;
 420
 421                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 422                 }
 423                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 424                 args [quad] = class1;
 425         }
 426
 427         /* Post merger cleanup */
 428         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 429                 args [0] = args [1] = ARG_CLASS_MEMORY;
 430
 431         /* Allocate registers */
 432         {
 433                 int orig_gr = *gr;
 434                 int orig_fr = *fr;
 435
 436                 ainfo->storage = ArgValuetypeInReg;
 437                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 438                 for (quad = 0; quad < nquads; ++quad) {
 439                         switch (args [quad]) {
 440                         case ARG_CLASS_INTEGER:
 441                                 if (*gr >= PARAM_REGS)
 442                                         args [quad] = ARG_CLASS_MEMORY;
 443                                 else {
 444                                         ainfo->pair_storage [quad] = ArgInIReg;
 445                                         if (is_return)
 446                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 447                                         else
 448                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 449                                         (*gr) ++;
 450                                 }
 451                                 break;
 452                         case ARG_CLASS_SSE:
 453                                 if (*fr >= FLOAT_PARAM_REGS)
 454                                         args [quad] = ARG_CLASS_MEMORY;
 455                                 else {
 456                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 457                                         ainfo->pair_regs [quad] = *fr;
 458                                         (*fr) ++;
 459                                 }
 460                                 break;
 461                         case ARG_CLASS_MEMORY:
 462                                 break;
 463                         default:
 464                                 g_assert_not_reached ();
 465                         }
 466                 }
 467
 468                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 469                         /* Revert possible register assignments */
 470                         *gr = orig_gr;
 471                         *fr = orig_fr;
 472
 473                         ainfo->offset = *stack_size;
 474                         *stack_size += ALIGN_TO (info->native_size, 8);
 475                         ainfo->storage = ArgOnStack;
 476                 }
 477         }
 478 }
 479
 480 /*
 481  * get_call_info:
 482  *
 483  *  Obtain information about a call according to the calling convention.
 484  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 485  * Draft Version 0.23" document for more information.
 486  */
 487 static CallInfo*
 488 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 489 {
 490         guint32 i, gr, fr;
 491         MonoType *ret_type;
 492         int n = sig->hasthis + sig->param_count;
 493         guint32 stack_size = 0;
 494         CallInfo *cinfo;
 495
 496         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 497
 498         gr = 0;
 499         fr = 0;
 500
 501         /* return value */
 502         {
 503                 ret_type = mono_type_get_underlying_type (sig->ret);
 504                 switch (ret_type->type) {
 505                 case MONO_TYPE_BOOLEAN:
 506                 case MONO_TYPE_I1:
 507                 case MONO_TYPE_U1:
 508                 case MONO_TYPE_I2:
 509                 case MONO_TYPE_U2:
 510                 case MONO_TYPE_CHAR:
 511                 case MONO_TYPE_I4:
 512                 case MONO_TYPE_U4:
 513                 case MONO_TYPE_I:
 514                 case MONO_TYPE_U:
 515                 case MONO_TYPE_PTR:
 516                 case MONO_TYPE_FNPTR:
 517                 case MONO_TYPE_CLASS:
 518                 case MONO_TYPE_OBJECT:
 519                 case MONO_TYPE_SZARRAY:
 520                 case MONO_TYPE_ARRAY:
 521                 case MONO_TYPE_STRING:
 522                         cinfo->ret.storage = ArgInIReg;
 523                         cinfo->ret.reg = AMD64_RAX;
 524                         break;
 525                 case MONO_TYPE_U8:
 526                 case MONO_TYPE_I8:
 527                         cinfo->ret.storage = ArgInIReg;
 528                         cinfo->ret.reg = AMD64_RAX;
 529                         break;
 530                 case MONO_TYPE_R4:
 531                         cinfo->ret.storage = ArgInFloatSSEReg;
 532                         cinfo->ret.reg = AMD64_XMM0;
 533                         break;
 534                 case MONO_TYPE_R8:
 535                         cinfo->ret.storage = ArgInDoubleSSEReg;
 536                         cinfo->ret.reg = AMD64_XMM0;
 537                         break;
 538                 case MONO_TYPE_GENERICINST:
 539                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 540                                 cinfo->ret.storage = ArgInIReg;
 541                                 cinfo->ret.reg = AMD64_RAX;
 542                                 break;
 543                         }
 544                         /* fall through */
 545                 case MONO_TYPE_VALUETYPE: {
 546                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 547
 548                         add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 549                         if (cinfo->ret.storage == ArgOnStack)
 550                                 /* The caller passes the address where the value is stored */
 551                                 add_general (&gr, &stack_size, &cinfo->ret);
 552                         break;
 553                 }
 554                 case MONO_TYPE_TYPEDBYREF:
 555                         /* Same as a valuetype with size 24 */
 556                         add_general (&gr, &stack_size, &cinfo->ret);
 557                         ;
 558                         break;
 559                 case MONO_TYPE_VOID:
 560                         break;
 561                 default:
 562                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 563                 }
 564         }
 565
 566         /* this */
 567         if (sig->hasthis)
 568                 add_general (&gr, &stack_size, cinfo->args + 0);
 569
 570         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 571                 gr = PARAM_REGS;
 572                 fr = FLOAT_PARAM_REGS;
 573
 574                 /* Emit the signature cookie just before the implicit arguments */
 575                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 576         }
 577
 578         for (i = 0; i < sig->param_count; ++i) {
 579                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 580                 MonoType *ptype;
 581
 582                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 583                         /* We allways pass the sig cookie on the stack for simplicity */
 584                         /*
 585                          * Prevent implicit arguments + the sig cookie from being passed
 586                          * in registers.
 587                          */
 588                         gr = PARAM_REGS;
 589                         fr = FLOAT_PARAM_REGS;
 590
 591                         /* Emit the signature cookie just before the implicit arguments */
 592                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 593                 }
 594
 595                 if (sig->params [i]->byref) {
 596                         add_general (&gr, &stack_size, ainfo);
 597                         continue;
 598                 }
 599                 ptype = mono_type_get_underlying_type (sig->params [i]);
 600                 switch (ptype->type) {
 601                 case MONO_TYPE_BOOLEAN:
 602                 case MONO_TYPE_I1:
 603                 case MONO_TYPE_U1:
 604                         add_general (&gr, &stack_size, ainfo);
 605                         break;
 606                 case MONO_TYPE_I2:
 607                 case MONO_TYPE_U2:
 608                 case MONO_TYPE_CHAR:
 609                         add_general (&gr, &stack_size, ainfo);
 610                         break;
 611                 case MONO_TYPE_I4:
 612                 case MONO_TYPE_U4:
 613                         add_general (&gr, &stack_size, ainfo);
 614                         break;
 615                 case MONO_TYPE_I:
 616                 case MONO_TYPE_U:
 617                 case MONO_TYPE_PTR:
 618                 case MONO_TYPE_FNPTR:
 619                 case MONO_TYPE_CLASS:
 620                 case MONO_TYPE_OBJECT:
 621                 case MONO_TYPE_STRING:
 622                 case MONO_TYPE_SZARRAY:
 623                 case MONO_TYPE_ARRAY:
 624                         add_general (&gr, &stack_size, ainfo);
 625                         break;
 626                 case MONO_TYPE_GENERICINST:
 627                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 628                                 add_general (&gr, &stack_size, ainfo);
 629                                 break;
 630                         }
 631                         /* fall through */
 632                 case MONO_TYPE_VALUETYPE:
 633                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 634                         break;
 635                 case MONO_TYPE_TYPEDBYREF:
 636                         stack_size += sizeof (MonoTypedRef);
 637                         ainfo->storage = ArgOnStack;
 638                         break;
 639                 case MONO_TYPE_U8:
 640                 case MONO_TYPE_I8:
 641                         add_general (&gr, &stack_size, ainfo);
 642                         break;
 643                 case MONO_TYPE_R4:
 644                         add_float (&fr, &stack_size, ainfo, FALSE);
 645                         break;
 646                 case MONO_TYPE_R8:
 647                         add_float (&fr, &stack_size, ainfo, TRUE);
 648                         break;
 649                 default:
 650                         g_assert_not_reached ();
 651                 }
 652         }
 653
 654         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 655                 gr = PARAM_REGS;
 656                 fr = FLOAT_PARAM_REGS;
 657
 658                 /* Emit the signature cookie just before the implicit arguments */
 659                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 660         }
 661
 662         if (stack_size & 0x8) {
 663                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 664                 cinfo->need_stack_align = TRUE;
 665                 stack_size += 8;
 666         }
 667
 668         cinfo->stack_usage = stack_size;
 669         cinfo->reg_usage = gr;
 670         cinfo->freg_usage = fr;
 671         return cinfo;
 672 }
 673
 674 /*
 675  * mono_arch_get_argument_info:
 676  * @csig:  a method signature
 677  * @param_count: the number of parameters to consider
 678  * @arg_info: an array to store the result infos
 679  *
 680  * Gathers information on parameters such as size, alignment and
 681  * padding. arg_info should be large enought to hold param_count + 1 entries.
 682  *
 683  * Returns the size of the argument area on the stack.
 684  */
 685 int
 686 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 687 {
 688         int k;
 689         CallInfo *cinfo = get_call_info (csig, FALSE);
 690         guint32 args_size = cinfo->stack_usage;
 691
 692         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 693         if (csig->hasthis) {
 694                 arg_info [0].offset = 0;
 695         }
 696
 697         for (k = 0; k < param_count; k++) {
 698                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 699                 /* FIXME: */
 700                 arg_info [k + 1].size = 0;
 701         }
 702
 703         g_free (cinfo);
 704
 705         return args_size;
 706 }
 707
 708 static int
 709 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 710 {
 711         return 0;
 712 }
 713
 714 /*
 715  * Initialize the cpu to execute managed code.
 716  */
 717 void
 718 mono_arch_cpu_init (void)
 719 {
 720         guint16 fpcw;
 721
 722         /* spec compliance requires running with double precision */
 723         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 724         fpcw &= ~X86_FPCW_PRECC_MASK;
 725         fpcw |= X86_FPCW_PREC_DOUBLE;
 726         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 727         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 728 }
 729
 730 /*
 731  * This function returns the optimizations supported on this cpu.
 732  */
 733 guint32
 734 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 735 {
 736         int eax, ebx, ecx, edx;
 737         guint32 opts = 0;
 738
 739         /* FIXME: AMD64 */
 740
 741         *exclude_mask = 0;
 742         /* Feature Flags function, flags returned in EDX. */
 743         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 744                 if (edx & (1 << 15)) {
 745                         opts |= MONO_OPT_CMOV;
 746                         if (edx & 1)
 747                                 opts |= MONO_OPT_FCMOV;
 748                         else
 749                                 *exclude_mask |= MONO_OPT_FCMOV;
 750                 } else
 751                         *exclude_mask |= MONO_OPT_CMOV;
 752         }
 753         return opts;
 754 }
 755
 756 gboolean
 757 mono_amd64_is_sse2 (void)
 758 {
 759         return use_sse2;
 760 }
 761
 762 static gboolean
 763 is_regsize_var (MonoType *t) {
 764         if (t->byref)
 765                 return TRUE;
 766         t = mono_type_get_underlying_type (t);
 767         switch (t->type) {
 768         case MONO_TYPE_I4:
 769         case MONO_TYPE_U4:
 770         case MONO_TYPE_I:
 771         case MONO_TYPE_U:
 772         case MONO_TYPE_PTR:
 773         case MONO_TYPE_FNPTR:
 774                 return TRUE;
 775         case MONO_TYPE_OBJECT:
 776         case MONO_TYPE_STRING:
 777         case MONO_TYPE_CLASS:
 778         case MONO_TYPE_SZARRAY:
 779         case MONO_TYPE_ARRAY:
 780                 return TRUE;
 781         case MONO_TYPE_GENERICINST:
 782                 if (!mono_type_generic_inst_is_valuetype (t))
 783                         return TRUE;
 784                 return FALSE;
 785         case MONO_TYPE_VALUETYPE:
 786                 return FALSE;
 787         }
 788         return FALSE;
 789 }
 790
 791 GList *
 792 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 793 {
 794         GList *vars = NULL;
 795         int i;
 796
 797         for (i = 0; i < cfg->num_varinfo; i++) {
 798                 MonoInst *ins = cfg->varinfo [i];
 799                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 800
 801                 /* unused vars */
 802                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 803                         continue;
 804
 805                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 806                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 807                         continue;
 808
 809                 /* we dont allocate I1 to registers because there is no simply way to sign extend
 810                  * 8bit quantities in caller saved registers on x86 */
 811                 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
 812                     (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
 813                     (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
 814                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 815                         g_assert (i == vmv->idx);
 816                         vars = g_list_prepend (vars, vmv);
 817                 }
 818         }
 819
 820         vars = mono_varlist_sort (cfg, vars, 0);
 821
 822         return vars;
 823 }
 824
 825 /**
 826  * mono_arch_compute_omit_fp:
 827  *
 828  *   Determine whenever the frame pointer can be eliminated.
 829  */
 830 static void
 831 mono_arch_compute_omit_fp (MonoCompile *cfg)
 832 {
 833         MonoMethodSignature *sig;
 834         MonoMethodHeader *header;
 835         int i;
 836         CallInfo *cinfo;
 837
 838         if (cfg->arch.omit_fp_computed)
 839                 return;
 840
 841         header = mono_method_get_header (cfg->method);
 842
 843         sig = mono_method_signature (cfg->method);
 844
 845         cinfo = get_call_info (sig, FALSE);
 846
 847         /*
 848          * FIXME: Remove some of the restrictions.
 849          */
 850         cfg->arch.omit_fp = TRUE;
 851         cfg->arch.omit_fp_computed = TRUE;
 852
 853         /* Temporarily disable this when running in the debugger until we have support
 854          * for this in the debugger. */
 855         if (mono_debug_using_mono_debugger ())
 856                 cfg->arch.omit_fp = FALSE;
 857
 858         if (!debug_omit_fp ())
 859                 cfg->arch.omit_fp = FALSE;
 860         /*
 861         if (cfg->method->save_lmf)
 862                 cfg->arch.omit_fp = FALSE;
 863         */
 864         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 865                 cfg->arch.omit_fp = FALSE;
 866         if (header->num_clauses)
 867                 cfg->arch.omit_fp = FALSE;
 868         if (cfg->param_area)
 869                 cfg->arch.omit_fp = FALSE;
 870         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 871                 cfg->arch.omit_fp = FALSE;
 872         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 873                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 874                 cfg->arch.omit_fp = FALSE;
 875         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 876                 ArgInfo *ainfo = &cinfo->args [i];
 877
 878                 if (ainfo->storage == ArgOnStack) {
 879                         /*
 880                          * The stack offset can only be determined when the frame
 881                          * size is known.
 882                          */
 883                         cfg->arch.omit_fp = FALSE;
 884                 }
 885         }
 886
 887         if (cfg->num_varinfo > 10000) {
 888                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
 889                 cfg->arch.omit_fp = FALSE;
 890         }
 891
 892         g_free (cinfo);
 893 }
 894
 895 GList *
 896 mono_arch_get_global_int_regs (MonoCompile *cfg)
 897 {
 898         GList *regs = NULL;
 899
 900         mono_arch_compute_omit_fp (cfg);
 901
 902         if (cfg->arch.omit_fp)
 903                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
 904
 905         /* We use the callee saved registers for global allocation */
 906         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 907         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 908         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 909         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 910         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 911
 912         return regs;
 913 }
 914
 915 /*
 916  * mono_arch_regalloc_cost:
 917  *
 918  *  Return the cost, in number of memory references, of the action of
 919  * allocating the variable VMV into a register during global register
 920  * allocation.
 921  */
 922 guint32
 923 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 924 {
 925         MonoInst *ins = cfg->varinfo [vmv->idx];
 926
 927         if (cfg->method->save_lmf)
 928                 /* The register is already saved */
 929                 /* substract 1 for the invisible store in the prolog */
 930                 return (ins->opcode == OP_ARG) ? 0 : 1;
 931         else
 932                 /* push+pop */
 933                 return (ins->opcode == OP_ARG) ? 1 : 2;
 934 }
 935
 936 void
 937 mono_arch_allocate_vars (MonoCompile *cfg)
 938 {
 939         MonoMethodSignature *sig;
 940         MonoMethodHeader *header;
 941         MonoInst *inst;
 942         int i, offset;
 943         guint32 locals_stack_size, locals_stack_align;
 944         gint32 *offsets;
 945         CallInfo *cinfo;
 946
 947         header = mono_method_get_header (cfg->method);
 948
 949         sig = mono_method_signature (cfg->method);
 950
 951         cinfo = get_call_info (sig, FALSE);
 952
 953         mono_arch_compute_omit_fp (cfg);
 954
 955         /*
 956          * We use the ABI calling conventions for managed code as well.
 957          * Exception: valuetypes are never passed or returned in registers.
 958          */
 959
 960         if (cfg->arch.omit_fp) {
 961                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 962                 cfg->frame_reg = AMD64_RSP;
 963                 offset = 0;
 964         } else {
 965                 /* Locals are allocated backwards from %fp */
 966                 cfg->frame_reg = AMD64_RBP;
 967                 offset = 0;
 968         }
 969
 970         cfg->arch.reg_save_area_offset = offset;
 971
 972         /* Reserve space for caller saved registers */
 973         for (i = 0; i < AMD64_NREG; ++i)
 974                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
 975                         offset += sizeof (gpointer);
 976                 }
 977
 978         if (cfg->method->save_lmf) {
 979                 /* Reserve stack space for saving LMF + argument regs */
 980                 guint32 size = sizeof (MonoLMF);
 981
 982                 if (lmf_addr_tls_offset == -1)
 983                         /* Need to save argument regs too */
 984                         size += (AMD64_NREG * 8) + (8 * 8);
 985
 986                 if (cfg->arch.omit_fp) {
 987                         cfg->arch.lmf_offset = offset;
 988                         offset += size;
 989                 }
 990                 else {
 991                         offset += size;
 992                         cfg->arch.lmf_offset = -offset;
 993                 }
 994         }
 995
 996         if (sig->ret->type != MONO_TYPE_VOID) {
 997                 switch (cinfo->ret.storage) {
 998                 case ArgInIReg:
 999                 case ArgInFloatSSEReg:
1000                 case ArgInDoubleSSEReg:
1001                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1002                                 /* The register is volatile */
1003                                 cfg->ret->opcode = OP_REGOFFSET;
1004                                 cfg->ret->inst_basereg = cfg->frame_reg;
1005                                 if (cfg->arch.omit_fp) {
1006                                         cfg->ret->inst_offset = offset;
1007                                         offset += 8;
1008                                 } else {
1009                                         offset += 8;
1010                                         cfg->ret->inst_offset = -offset;
1011                                 }
1012                         }
1013                         else {
1014                                 cfg->ret->opcode = OP_REGVAR;
1015                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1016                         }
1017                         break;
1018                 case ArgValuetypeInReg:
1019                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1020                         g_assert (!cfg->arch.omit_fp);
1021                         offset += 16;
1022                         cfg->ret->opcode = OP_REGOFFSET;
1023                         cfg->ret->inst_basereg = cfg->frame_reg;
1024                         cfg->ret->inst_offset = - offset;
1025                         break;
1026                 default:
1027                         g_assert_not_reached ();
1028                 }
1029                 cfg->ret->dreg = cfg->ret->inst_c0;
1030         }
1031
1032         /* Allocate locals */
1033         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1034         if (locals_stack_align) {
1035                 offset += (locals_stack_align - 1);
1036                 offset &= ~(locals_stack_align - 1);
1037         }
1038         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1039                 if (offsets [i] != -1) {
1040                         MonoInst *inst = cfg->varinfo [i];
1041                         inst->opcode = OP_REGOFFSET;
1042                         inst->inst_basereg = cfg->frame_reg;
1043                         if (cfg->arch.omit_fp)
1044                                 inst->inst_offset = (offset + offsets [i]);
1045                         else
1046                                 inst->inst_offset = - (offset + offsets [i]);
1047                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1048                 }
1049         }
1050         offset += locals_stack_size;
1051
1052         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1053                 g_assert (!cfg->arch.omit_fp);
1054                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1055                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1056         }
1057
1058         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1059                 inst = cfg->varinfo [i];
1060                 if (inst->opcode != OP_REGVAR) {
1061                         ArgInfo *ainfo = &cinfo->args [i];
1062                         gboolean inreg = TRUE;
1063                         MonoType *arg_type;
1064
1065                         if (sig->hasthis && (i == 0))
1066                                 arg_type = &mono_defaults.object_class->byval_arg;
1067                         else
1068                                 arg_type = sig->params [i - sig->hasthis];
1069
1070                         /* FIXME: Allocate volatile arguments to registers */
1071                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1072                                 inreg = FALSE;
1073
1074                         /*
1075                          * Under AMD64, all registers used to pass arguments to functions
1076                          * are volatile across calls.
1077                          * FIXME: Optimize this.
1078                          */
1079                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1080                                 inreg = FALSE;
1081
1082                         inst->opcode = OP_REGOFFSET;
1083
1084                         switch (ainfo->storage) {
1085                         case ArgInIReg:
1086                         case ArgInFloatSSEReg:
1087                         case ArgInDoubleSSEReg:
1088                                 inst->opcode = OP_REGVAR;
1089                                 inst->dreg = ainfo->reg;
1090                                 break;
1091                         case ArgOnStack:
1092                                 g_assert (!cfg->arch.omit_fp);
1093                                 inst->opcode = OP_REGOFFSET;
1094                                 inst->inst_basereg = cfg->frame_reg;
1095                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1096                                 break;
1097                         case ArgValuetypeInReg:
1098                                 break;
1099                         default:
1100                                 NOT_IMPLEMENTED;
1101                         }
1102
1103                         if (!inreg && (ainfo->storage != ArgOnStack)) {
1104                                 inst->opcode = OP_REGOFFSET;
1105                                 inst->inst_basereg = cfg->frame_reg;
1106                                 /* These arguments are saved to the stack in the prolog */
1107                                 if (cfg->arch.omit_fp) {
1108                                         inst->inst_offset = offset;
1109                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1110                                 } else {
1111                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1112                                         inst->inst_offset = - offset;
1113                                 }
1114                         }
1115                 }
1116         }
1117
1118         cfg->stack_offset = offset;
1119
1120         g_free (cinfo);
1121 }
1122
1123 void
1124 mono_arch_create_vars (MonoCompile *cfg)
1125 {
1126         MonoMethodSignature *sig;
1127         CallInfo *cinfo;
1128
1129         sig = mono_method_signature (cfg->method);
1130
1131         cinfo = get_call_info (sig, FALSE);
1132
1133         if (cinfo->ret.storage == ArgValuetypeInReg)
1134                 cfg->ret_var_is_local = TRUE;
1135
1136         g_free (cinfo);
1137 }
1138
1139 static void
1140 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1141 {
1142         switch (storage) {
1143         case ArgInIReg:
1144                 arg->opcode = OP_OUTARG_REG;
1145                 arg->inst_left = tree;
1146                 arg->inst_call = call;
1147                 arg->backend.reg3 = reg;
1148                 break;
1149         case ArgInFloatSSEReg:
1150                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1151                 arg->inst_left = tree;
1152                 arg->inst_call = call;
1153                 arg->backend.reg3 = reg;
1154                 break;
1155         case ArgInDoubleSSEReg:
1156                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1157                 arg->inst_left = tree;
1158                 arg->inst_call = call;
1159                 arg->backend.reg3 = reg;
1160                 break;
1161         default:
1162                 g_assert_not_reached ();
1163         }
1164 }
1165
1166 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1167  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1168  */
1169
1170 static int
1171 arg_storage_to_ldind (ArgStorage storage)
1172 {
1173         switch (storage) {
1174         case ArgInIReg:
1175                 return CEE_LDIND_I;
1176         case ArgInDoubleSSEReg:
1177                 return CEE_LDIND_R8;
1178         case ArgInFloatSSEReg:
1179                 return CEE_LDIND_R4;
1180         default:
1181                 g_assert_not_reached ();
1182         }
1183
1184         return -1;
1185 }
1186
1187 static void
1188 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1189 {
1190         MonoInst *arg;
1191         MonoMethodSignature *tmp_sig;
1192         MonoInst *sig_arg;
1193
1194         /* FIXME: Add support for signature tokens to AOT */
1195         cfg->disable_aot = TRUE;
1196
1197         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1198
1199         /*
1200          * mono_ArgIterator_Setup assumes the signature cookie is
1201          * passed first and all the arguments which were before it are
1202          * passed on the stack after the signature. So compensate by
1203          * passing a different signature.
1204          */
1205         tmp_sig = mono_metadata_signature_dup (call->signature);
1206         tmp_sig->param_count -= call->signature->sentinelpos;
1207         tmp_sig->sentinelpos = 0;
1208         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1209
1210         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1211         sig_arg->inst_p0 = tmp_sig;
1212
1213         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1214         arg->inst_left = sig_arg;
1215         arg->type = STACK_PTR;
1216
1217         /* prepend, so they get reversed */
1218         arg->next = call->out_args;
1219         call->out_args = arg;
1220 }
1221
1222 /*
1223  * take the arguments and generate the arch-specific
1224  * instructions to properly call the function in call.
1225  * This includes pushing, moving arguments to the right register
1226  * etc.
1227  * Issue: who does the spilling if needed, and when?
1228  */
1229 MonoCallInst*
1230 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1231         MonoInst *arg, *in;
1232         MonoMethodSignature *sig;
1233         int i, n, stack_size;
1234         CallInfo *cinfo;
1235         ArgInfo *ainfo;
1236
1237         stack_size = 0;
1238
1239         sig = call->signature;
1240         n = sig->param_count + sig->hasthis;
1241
1242         cinfo = get_call_info (sig, sig->pinvoke);
1243
1244         for (i = 0; i < n; ++i) {
1245                 ainfo = cinfo->args + i;
1246
1247                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1248                         /* Emit the signature cookie just before the implicit arguments */
1249                         emit_sig_cookie (cfg, call, cinfo);
1250                 }
1251
1252                 if (is_virtual && i == 0) {
1253                         /* the argument will be attached to the call instruction */
1254                         in = call->args [i];
1255                 } else {
1256                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1257                         in = call->args [i];
1258                         arg->cil_code = in->cil_code;
1259                         arg->inst_left = in;
1260                         arg->type = in->type;
1261                         /* prepend, so they get reversed */
1262                         arg->next = call->out_args;
1263                         call->out_args = arg;
1264
1265                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1266                                 guint32 align;
1267                                 guint32 size;
1268
1269                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1270                                         size = sizeof (MonoTypedRef);
1271                                         align = sizeof (gpointer);
1272                                 }
1273                                 else
1274                                 if (sig->pinvoke)
1275                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1276                                 else {
1277                                         /*
1278                                          * Other backends use mono_type_stack_size (), but that
1279                                          * aligns the size to 8, which is larger than the size of
1280                                          * the source, leading to reads of invalid memory if the
1281                                          * source is at the end of address space.
1282                                          */
1283                                         size = mono_class_value_size (in->klass, &align);
1284                                 }
1285                                 if (ainfo->storage == ArgValuetypeInReg) {
1286                                         if (ainfo->pair_storage [1] == ArgNone) {
1287                                                 MonoInst *load;
1288
1289                                                 /* Simpler case */
1290
1291                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1292                                                 load->inst_left = in;
1293
1294                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1295                                         }
1296                                         else {
1297                                                 /* Trees can't be shared so make a copy */
1298                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1299                                                 MonoInst *load, *load2, *offset_ins;
1300
1301                                                 /* Reg1 */
1302                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1303                                                 load->ssa_op = MONO_SSA_LOAD;
1304                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1305
1306                                                 NEW_ICONST (cfg, offset_ins, 0);
1307                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1308                                                 load2->inst_left = load;
1309                                                 load2->inst_right = offset_ins;
1310
1311                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1312                                                 load->inst_left = load2;
1313
1314                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1315
1316                                                 /* Reg2 */
1317                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1318                                                 load->ssa_op = MONO_SSA_LOAD;
1319                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1320
1321                                                 NEW_ICONST (cfg, offset_ins, 8);
1322                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1323                                                 load2->inst_left = load;
1324                                                 load2->inst_right = offset_ins;
1325
1326                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1327                                                 load->inst_left = load2;
1328
1329                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1330                                                 arg->cil_code = in->cil_code;
1331                                                 arg->type = in->type;
1332                                                 /* prepend, so they get reversed */
1333                                                 arg->next = call->out_args;
1334                                                 call->out_args = arg;
1335
1336                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1337
1338                                                 /* Prepend a copy inst */
1339                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1340                                                 arg->cil_code = in->cil_code;
1341                                                 arg->ssa_op = MONO_SSA_STORE;
1342                                                 arg->inst_left = vtaddr;
1343                                                 arg->inst_right = in;
1344                                                 arg->type = in->type;
1345
1346                                                 /* prepend, so they get reversed */
1347                                                 arg->next = call->out_args;
1348                                                 call->out_args = arg;
1349                                         }
1350                                 }
1351                                 else {
1352                                         arg->opcode = OP_OUTARG_VT;
1353                                         arg->klass = in->klass;
1354                                         arg->backend.is_pinvoke = sig->pinvoke;
1355                                         arg->inst_imm = size;
1356                                 }
1357                         }
1358                         else {
1359                                 switch (ainfo->storage) {
1360                                 case ArgInIReg:
1361                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1362                                         break;
1363                                 case ArgInFloatSSEReg:
1364                                 case ArgInDoubleSSEReg:
1365                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1366                                         break;
1367                                 case ArgOnStack:
1368                                         arg->opcode = OP_OUTARG;
1369                                         if (!sig->params [i - sig->hasthis]->byref) {
1370                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1371                                                         arg->opcode = OP_OUTARG_R4;
1372                                                 else
1373                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1374                                                                 arg->opcode = OP_OUTARG_R8;
1375                                         }
1376                                         break;
1377                                 default:
1378                                         g_assert_not_reached ();
1379                                 }
1380                         }
1381                 }
1382         }
1383
1384         /* Handle the case where there are no implicit arguments */
1385         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1386                 emit_sig_cookie (cfg, call, cinfo);
1387         }
1388
1389         if (cinfo->need_stack_align) {
1390                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1391                 /* prepend, so they get reversed */
1392                 arg->next = call->out_args;
1393                 call->out_args = arg;
1394         }
1395
1396         call->stack_usage = cinfo->stack_usage;
1397         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1398         cfg->flags |= MONO_CFG_HAS_CALLS;
1399
1400         g_free (cinfo);
1401
1402         return call;
1403 }
1404
1405 #define EMIT_COND_BRANCH(ins,cond,sign) \
1406 if (ins->flags & MONO_INST_BRLABEL) { \
1407         if (ins->inst_i0->inst_c0) { \
1408                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1409         } else { \
1410                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1411                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1412                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1413                         x86_branch8 (code, cond, 0, sign); \
1414                 else \
1415                         x86_branch32 (code, cond, 0, sign); \
1416         } \
1417 } else { \
1418         if (ins->inst_true_bb->native_offset) { \
1419                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1420         } else { \
1421                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1422                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1423                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1424                         x86_branch8 (code, cond, 0, sign); \
1425                 else \
1426                         x86_branch32 (code, cond, 0, sign); \
1427         } \
1428 }
1429
1430 /* emit an exception if condition is fail */
1431 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1432         do {                                                        \
1433                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1434                 if (tins == NULL) {                                                                             \
1435                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1436                                         MONO_PATCH_INFO_EXC, exc_name);  \
1437                         x86_branch32 (code, cond, 0, signed);               \
1438                 } else {        \
1439                         EMIT_COND_BRANCH (tins, cond, signed);  \
1440                 }                       \
1441         } while (0);
1442
1443 #define EMIT_FPCOMPARE(code) do { \
1444         amd64_fcompp (code); \
1445         amd64_fnstsw (code); \
1446 } while (0);
1447
1448 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1449     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1450         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1451         amd64_ ##op (code); \
1452         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1453         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1454 } while (0);
1455
1456 static guint8*
1457 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1458 {
1459         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1460
1461         /*
1462          * FIXME: Add support for thunks
1463          */
1464         {
1465                 gboolean near_call = FALSE;
1466
1467                 /*
1468                  * Indirect calls are expensive so try to make a near call if possible.
1469                  * The caller memory is allocated by the code manager so it is
1470                  * guaranteed to be at a 32 bit offset.
1471                  */
1472
1473                 if (patch_type != MONO_PATCH_INFO_ABS) {
1474                         /* The target is in memory allocated using the code manager */
1475                         near_call = TRUE;
1476
1477                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1478                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1479                                         /* The callee might be an AOT method */
1480                                         near_call = FALSE;
1481                         }
1482
1483                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1484                                 /*
1485                                  * The call might go directly to a native function without
1486                                  * the wrapper.
1487                                  */
1488                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1489                                 if (mi) {
1490                                         gconstpointer target = mono_icall_get_wrapper (mi);
1491                                         if ((((guint64)target) >> 32) != 0)
1492                                                 near_call = FALSE;
1493                                 }
1494                         }
1495                 }
1496                 else {
1497                         if (mono_find_class_init_trampoline_by_addr (data))
1498                                 near_call = TRUE;
1499                         else {
1500                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1501                                 if (info) {
1502                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1503                                                 strstr (cfg->method->name, info->name)) {
1504                                                 /* A call to the wrapped function */
1505                                                 if ((((guint64)data) >> 32) == 0)
1506                                                         near_call = TRUE;
1507                                         }
1508                                         else if (info->func == info->wrapper) {
1509                                                 /* No wrapper */
1510                                                 if ((((guint64)info->func) >> 32) == 0)
1511                                                         near_call = TRUE;
1512                                         }
1513                                         else {
1514                                                 /* See the comment in mono_codegen () */
1515                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1516                                                         near_call = TRUE;
1517                                         }
1518                                 }
1519                                 else if ((((guint64)data) >> 32) == 0)
1520                                         near_call = TRUE;
1521                         }
1522                 }
1523
1524                 if (cfg->method->dynamic)
1525                         /* These methods are allocated using malloc */
1526                         near_call = FALSE;
1527
1528                 if (cfg->compile_aot)
1529                         near_call = TRUE;
1530
1531 #ifdef MONO_ARCH_NOMAP32BIT
1532                 near_call = FALSE;
1533 #endif
1534
1535                 if (near_call) {
1536                         amd64_call_code (code, 0);
1537                 }
1538                 else {
1539                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1540                         amd64_call_reg (code, GP_SCRATCH_REG);
1541                 }
1542         }
1543
1544         return code;
1545 }
1546
1547 static inline guint8*
1548 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1549 {
1550         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1551
1552         return emit_call_body (cfg, code, patch_type, data);
1553 }
1554
1555 /* FIXME: Add more instructions */
1556 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM) || ((ins)->opcode == OP_STOREI8_MEMBASE_REG) || ((ins)->opcode == OP_MOVE) || ((ins)->opcode == OP_ICONST) || ((ins)->opcode == OP_I8CONST) || ((ins)->opcode == OP_LOAD_MEMBASE))
1557
1558 static void
1559 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1560 {
1561         MonoInst *ins, *last_ins = NULL;
1562         ins = bb->code;
1563
1564         while (ins) {
1565
1566                 switch (ins->opcode) {
1567                 case OP_ICONST:
1568                 case OP_I8CONST:
1569                         /* reg = 0 -> XOR (reg, reg) */
1570                         /* XOR sets cflags on x86, so we cant do it always */
1571                         if (ins->inst_c0 == 0 && (ins->next && INST_IGNORES_CFLAGS (ins->next))) {
1572                                 ins->opcode = CEE_XOR;
1573                                 ins->sreg1 = ins->dreg;
1574                                 ins->sreg2 = ins->dreg;
1575                         }
1576                         break;
1577                 case OP_MUL_IMM:
1578                         /* remove unnecessary multiplication with 1 */
1579                         if (ins->inst_imm == 1) {
1580                                 if (ins->dreg != ins->sreg1) {
1581                                         ins->opcode = OP_MOVE;
1582                                 } else {
1583                                         last_ins->next = ins->next;
1584                                         ins = ins->next;
1585                                         continue;
1586                                 }
1587                         }
1588                         break;
1589                 case OP_COMPARE_IMM:
1590                         /* OP_COMPARE_IMM (reg, 0)
1591                          * -->
1592                          * OP_AMD64_TEST_NULL (reg)
1593                          */
1594                         if (!ins->inst_imm)
1595                                 ins->opcode = OP_AMD64_TEST_NULL;
1596                         break;
1597                 case OP_ICOMPARE_IMM:
1598                         if (!ins->inst_imm)
1599                                 ins->opcode = OP_X86_TEST_NULL;
1600                         break;
1601                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1602                         /*
1603                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1604                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1605                          * -->
1606                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1607                          * OP_COMPARE_IMM reg, imm
1608                          *
1609                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1610                          */
1611                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1612                             ins->inst_basereg == last_ins->inst_destbasereg &&
1613                             ins->inst_offset == last_ins->inst_offset) {
1614                                         ins->opcode = OP_ICOMPARE_IMM;
1615                                         ins->sreg1 = last_ins->sreg1;
1616
1617                                         /* check if we can remove cmp reg,0 with test null */
1618                                         if (!ins->inst_imm)
1619                                                 ins->opcode = OP_X86_TEST_NULL;
1620                                 }
1621
1622                         break;
1623                 case OP_LOAD_MEMBASE:
1624                 case OP_LOADI4_MEMBASE:
1625                         /*
1626                          * Note: if reg1 = reg2 the load op is removed
1627                          *
1628                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1629                          * OP_LOAD_MEMBASE offset(basereg), reg2
1630                          * -->
1631                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1632                          * OP_MOVE reg1, reg2
1633                          */
1634                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1635                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1636                             ins->inst_basereg == last_ins->inst_destbasereg &&
1637                             ins->inst_offset == last_ins->inst_offset) {
1638                                 if (ins->dreg == last_ins->sreg1) {
1639                                         last_ins->next = ins->next;
1640                                         ins = ins->next;
1641                                         continue;
1642                                 } else {
1643                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1644                                         ins->opcode = OP_MOVE;
1645                                         ins->sreg1 = last_ins->sreg1;
1646                                 }
1647
1648                         /*
1649                          * Note: reg1 must be different from the basereg in the second load
1650                          * Note: if reg1 = reg2 is equal then second load is removed
1651                          *
1652                          * OP_LOAD_MEMBASE offset(basereg), reg1
1653                          * OP_LOAD_MEMBASE offset(basereg), reg2
1654                          * -->
1655                          * OP_LOAD_MEMBASE offset(basereg), reg1
1656                          * OP_MOVE reg1, reg2
1657                          */
1658                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1659                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1660                               ins->inst_basereg != last_ins->dreg &&
1661                               ins->inst_basereg == last_ins->inst_basereg &&
1662                               ins->inst_offset == last_ins->inst_offset) {
1663
1664                                 if (ins->dreg == last_ins->dreg) {
1665                                         last_ins->next = ins->next;
1666                                         ins = ins->next;
1667                                         continue;
1668                                 } else {
1669                                         ins->opcode = OP_MOVE;
1670                                         ins->sreg1 = last_ins->dreg;
1671                                 }
1672
1673                                 //g_assert_not_reached ();
1674
1675 #if 0
1676                         /*
1677                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1678                          * OP_LOAD_MEMBASE offset(basereg), reg
1679                          * -->
1680                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1681                          * OP_ICONST reg, imm
1682                          */
1683                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1684                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1685                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1686                                    ins->inst_offset == last_ins->inst_offset) {
1687                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1688                                 ins->opcode = OP_ICONST;
1689                                 ins->inst_c0 = last_ins->inst_imm;
1690                                 g_assert_not_reached (); // check this rule
1691 #endif
1692                         }
1693                         break;
1694                 case OP_LOADI1_MEMBASE:
1695                         /*
1696                          * Note: if reg1 = reg2 the load op is removed
1697                          *
1698                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1699                          * OP_LOAD_MEMBASE offset(basereg), reg2
1700                          * -->
1701                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1702                          * OP_MOVE reg1, reg2
1703                          */
1704                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1705                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1706                                         ins->inst_offset == last_ins->inst_offset) {
1707                                 if (ins->dreg == last_ins->sreg1) {
1708                                         last_ins->next = ins->next;
1709                                         ins = ins->next;
1710                                         continue;
1711                                 } else {
1712                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1713                                         ins->opcode = OP_MOVE;
1714                                         ins->sreg1 = last_ins->sreg1;
1715                                 }
1716                         }
1717                         break;
1718                 case OP_LOADI2_MEMBASE:
1719                         /*
1720                          * Note: if reg1 = reg2 the load op is removed
1721                          *
1722                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1723                          * OP_LOAD_MEMBASE offset(basereg), reg2
1724                          * -->
1725                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1726                          * OP_MOVE reg1, reg2
1727                          */
1728                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1729                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1730                                         ins->inst_offset == last_ins->inst_offset) {
1731                                 if (ins->dreg == last_ins->sreg1) {
1732                                         last_ins->next = ins->next;
1733                                         ins = ins->next;
1734                                         continue;
1735                                 } else {
1736                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1737                                         ins->opcode = OP_MOVE;
1738                                         ins->sreg1 = last_ins->sreg1;
1739                                 }
1740                         }
1741                         break;
1742                 case CEE_CONV_I4:
1743                 case CEE_CONV_U4:
1744                 case OP_MOVE:
1745                         /*
1746                          * Removes:
1747                          *
1748                          * OP_MOVE reg, reg
1749                          */
1750                         if (ins->dreg == ins->sreg1) {
1751                                 if (last_ins)
1752                                         last_ins->next = ins->next;
1753                                 ins = ins->next;
1754                                 continue;
1755                         }
1756                         /*
1757                          * Removes:
1758                          *
1759                          * OP_MOVE sreg, dreg
1760                          * OP_MOVE dreg, sreg
1761                          */
1762                         if (last_ins && last_ins->opcode == OP_MOVE &&
1763                             ins->sreg1 == last_ins->dreg &&
1764                             ins->dreg == last_ins->sreg1) {
1765                                 last_ins->next = ins->next;
1766                                 ins = ins->next;
1767                                 continue;
1768                         }
1769                         break;
1770                 }
1771                 last_ins = ins;
1772                 ins = ins->next;
1773         }
1774         bb->last_ins = last_ins;
1775 }
1776
1777 static void
1778 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1779 {
1780         if (ins == NULL) {
1781                 ins = bb->code;
1782                 bb->code = to_insert;
1783                 to_insert->next = ins;
1784         }
1785         else {
1786                 to_insert->next = ins->next;
1787                 ins->next = to_insert;
1788         }
1789 }
1790
1791 #define NEW_INS(cfg,dest,op) do {       \
1792                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1793                 (dest)->opcode = (op);  \
1794         insert_after_ins (bb, last_ins, (dest)); \
1795         } while (0)
1796
1797 /*
1798  * mono_arch_lowering_pass:
1799  *
1800  *  Converts complex opcodes into simpler ones so that each IR instruction
1801  * corresponds to one machine instruction.
1802  */
1803 static void
1804 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1805 {
1806         MonoInst *ins, *temp, *last_ins = NULL;
1807         ins = bb->code;
1808
1809         if (bb->max_vreg > cfg->rs->next_vreg)
1810                 cfg->rs->next_vreg = bb->max_vreg;
1811
1812         /*
1813          * FIXME: Need to add more instructions, but the current machine
1814          * description can't model some parts of the composite instructions like
1815          * cdq.
1816          */
1817         while (ins) {
1818                 switch (ins->opcode) {
1819                 case OP_DIV_IMM:
1820                 case OP_REM_IMM:
1821                 case OP_IDIV_IMM:
1822                 case OP_IREM_IMM:
1823                         NEW_INS (cfg, temp, OP_ICONST);
1824                         temp->inst_c0 = ins->inst_imm;
1825                         temp->dreg = mono_regstate_next_int (cfg->rs);
1826                         switch (ins->opcode) {
1827                         case OP_DIV_IMM:
1828                                 ins->opcode = OP_LDIV;
1829                                 break;
1830                         case OP_REM_IMM:
1831                                 ins->opcode = OP_LREM;
1832                                 break;
1833                         case OP_IDIV_IMM:
1834                                 ins->opcode = OP_IDIV;
1835                                 break;
1836                         case OP_IREM_IMM:
1837                                 ins->opcode = OP_IREM;
1838                                 break;
1839                         }
1840                         ins->sreg2 = temp->dreg;
1841                         break;
1842                 case OP_COMPARE_IMM:
1843                         if (!amd64_is_imm32 (ins->inst_imm)) {
1844                                 NEW_INS (cfg, temp, OP_I8CONST);
1845                                 temp->inst_c0 = ins->inst_imm;
1846                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1847                                 ins->opcode = OP_COMPARE;
1848                                 ins->sreg2 = temp->dreg;
1849                         }
1850                         break;
1851                 case OP_LOAD_MEMBASE:
1852                 case OP_LOADI8_MEMBASE:
1853                         if (!amd64_is_imm32 (ins->inst_offset)) {
1854                                 NEW_INS (cfg, temp, OP_I8CONST);
1855                                 temp->inst_c0 = ins->inst_offset;
1856                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1857                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
1858                                 ins->inst_indexreg = temp->dreg;
1859                         }
1860                         break;
1861                 case OP_STORE_MEMBASE_IMM:
1862                 case OP_STOREI8_MEMBASE_IMM:
1863                         if (!amd64_is_imm32 (ins->inst_imm)) {
1864                                 NEW_INS (cfg, temp, OP_I8CONST);
1865                                 temp->inst_c0 = ins->inst_imm;
1866                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1867                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1868                                 ins->sreg1 = temp->dreg;
1869                         }
1870                         break;
1871                 default:
1872                         break;
1873                 }
1874                 last_ins = ins;
1875                 ins = ins->next;
1876         }
1877         bb->last_ins = last_ins;
1878
1879         bb->max_vreg = cfg->rs->next_vreg;
1880 }
1881
1882 static const int
1883 branch_cc_table [] = {
1884         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1885         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1886         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1887 };
1888
1889 static int
1890 opcode_to_x86_cond (int opcode)
1891 {
1892         switch (opcode) {
1893         case OP_IBEQ:
1894                 return X86_CC_EQ;
1895         case OP_IBNE_UN:
1896                 return X86_CC_NE;
1897         case OP_IBLT:
1898                 return X86_CC_LT;
1899         case OP_IBLT_UN:
1900                 return X86_CC_LT;
1901         case OP_IBGT:
1902                 return X86_CC_GT;
1903         case OP_IBGT_UN:
1904                 return X86_CC_GT;
1905         case OP_IBGE:
1906                 return X86_CC_GE;
1907         case OP_IBGE_UN:
1908                 return X86_CC_GE;
1909         case OP_IBLE:
1910                 return X86_CC_LE;
1911         case OP_IBLE_UN:
1912                 return X86_CC_LE;
1913         case OP_COND_EXC_IOV:
1914                 return X86_CC_O;
1915         case OP_COND_EXC_IC:
1916                 return X86_CC_C;
1917         default:
1918                 g_assert_not_reached ();
1919         }
1920
1921         return -1;
1922 }
1923
1924 /*#include "cprop.c"*/
1925
1926 /*
1927  * Local register allocation.
1928  * We first scan the list of instructions and we save the liveness info of
1929  * each register (when the register is first used, when it's value is set etc.).
1930  * We also reverse the list of instructions (in the InstList list) because assigning
1931  * registers backwards allows for more tricks to be used.
1932  */
1933 void
1934 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1935 {
1936         if (!bb->code)
1937                 return;
1938
1939         mono_arch_lowering_pass (cfg, bb);
1940
1941         mono_local_regalloc (cfg, bb);
1942 }
1943
1944 static unsigned char*
1945 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1946 {
1947         if (use_sse2) {
1948                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
1949         }
1950         else {
1951                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
1952                 x86_fnstcw_membase(code, AMD64_RSP, 0);
1953                 amd64_mov_reg_membase (code, dreg, AMD64_RSP, 0, 2);
1954                 amd64_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1955                 amd64_mov_membase_reg (code, AMD64_RSP, 2, dreg, 2);
1956                 amd64_fldcw_membase (code, AMD64_RSP, 2);
1957                 amd64_push_reg (code, AMD64_RAX); // SP = SP - 8
1958                 amd64_fist_pop_membase (code, AMD64_RSP, 0, size == 8);
1959                 amd64_pop_reg (code, dreg);
1960                 amd64_fldcw_membase (code, AMD64_RSP, 0);
1961                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
1962         }
1963
1964         if (size == 1)
1965                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
1966         else if (size == 2)
1967                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
1968         return code;
1969 }
1970
1971 static unsigned char*
1972 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1973 {
1974         int sreg = tree->sreg1;
1975         int need_touch = FALSE;
1976
1977 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1978         if (!tree->flags & MONO_INST_INIT)
1979                 need_touch = TRUE;
1980 #endif
1981
1982         if (need_touch) {
1983                 guint8* br[5];
1984
1985                 /*
1986                  * Under Windows:
1987                  * If requested stack size is larger than one page,
1988                  * perform stack-touch operation
1989                  */
1990                 /*
1991                  * Generate stack probe code.
1992                  * Under Windows, it is necessary to allocate one page at a time,
1993                  * "touching" stack after each successful sub-allocation. This is
1994                  * because of the way stack growth is implemented - there is a
1995                  * guard page before the lowest stack page that is currently commited.
1996                  * Stack normally grows sequentially so OS traps access to the
1997                  * guard page and commits more pages when needed.
1998                  */
1999                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2000                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2001
2002                 br[2] = code; /* loop */
2003                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2004                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2005                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2006                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2007                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2008                 amd64_patch (br[3], br[2]);
2009                 amd64_test_reg_reg (code, sreg, sreg);
2010                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2011                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2012
2013                 br[1] = code; x86_jump8 (code, 0);
2014
2015                 amd64_patch (br[0], code);
2016                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2017                 amd64_patch (br[1], code);
2018                 amd64_patch (br[4], code);
2019         }
2020         else
2021                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2022
2023         if (tree->flags & MONO_INST_INIT) {
2024                 int offset = 0;
2025                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2026                         amd64_push_reg (code, AMD64_RAX);
2027                         offset += 8;
2028                 }
2029                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2030                         amd64_push_reg (code, AMD64_RCX);
2031                         offset += 8;
2032                 }
2033                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2034                         amd64_push_reg (code, AMD64_RDI);
2035                         offset += 8;
2036                 }
2037
2038                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2039                 if (sreg != AMD64_RCX)
2040                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2041                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2042
2043                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2044                 amd64_cld (code);
2045                 amd64_prefix (code, X86_REP_PREFIX);
2046                 amd64_stosl (code);
2047
2048                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2049                         amd64_pop_reg (code, AMD64_RDI);
2050                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2051                         amd64_pop_reg (code, AMD64_RCX);
2052                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2053                         amd64_pop_reg (code, AMD64_RAX);
2054         }
2055         return code;
2056 }
2057
2058 static guint8*
2059 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2060 {
2061         CallInfo *cinfo;
2062         guint32 quad;
2063
2064         /* Move return value to the target register */
2065         /* FIXME: do this in the local reg allocator */
2066         switch (ins->opcode) {
2067         case CEE_CALL:
2068         case OP_CALL_REG:
2069         case OP_CALL_MEMBASE:
2070         case OP_LCALL:
2071         case OP_LCALL_REG:
2072         case OP_LCALL_MEMBASE:
2073                 g_assert (ins->dreg == AMD64_RAX);
2074                 break;
2075         case OP_FCALL:
2076         case OP_FCALL_REG:
2077         case OP_FCALL_MEMBASE:
2078                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2079                         if (use_sse2)
2080                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2081                         else {
2082                                 /* FIXME: optimize this */
2083                                 amd64_movss_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2084                                 amd64_fld_membase (code, AMD64_RSP, -8, FALSE);
2085                         }
2086                 }
2087                 else {
2088                         if (use_sse2) {
2089                                 if (ins->dreg != AMD64_XMM0)
2090                                         amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2091                         }
2092                         else {
2093                                 /* FIXME: optimize this */
2094                                 amd64_movsd_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2095                                 amd64_fld_membase (code, AMD64_RSP, -8, TRUE);
2096                         }
2097                 }
2098                 break;
2099         case OP_VCALL:
2100         case OP_VCALL_REG:
2101         case OP_VCALL_MEMBASE:
2102                 cinfo = get_call_info (((MonoCallInst*)ins)->signature, FALSE);
2103                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2104                         /* Pop the destination address from the stack */
2105                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2106                         amd64_pop_reg (code, AMD64_RCX);
2107
2108                         for (quad = 0; quad < 2; quad ++) {
2109                                 switch (cinfo->ret.pair_storage [quad]) {
2110                                 case ArgInIReg:
2111                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2112                                         break;
2113                                 case ArgInFloatSSEReg:
2114                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2115                                         break;
2116                                 case ArgInDoubleSSEReg:
2117                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2118                                         break;
2119                                 case ArgNone:
2120                                         break;
2121                                 default:
2122                                         NOT_IMPLEMENTED;
2123                                 }
2124                         }
2125                 }
2126                 g_free (cinfo);
2127                 break;
2128         }
2129
2130         return code;
2131 }
2132
2133 /*
2134  * emit_tls_get:
2135  * @code: buffer to store code to
2136  * @dreg: hard register where to place the result
2137  * @tls_offset: offset info
2138  *
2139  * emit_tls_get emits in @code the native code that puts in the dreg register
2140  * the item in the thread local storage identified by tls_offset.
2141  *
2142  * Returns: a pointer to the end of the stored code
2143  */
2144 static guint8*
2145 emit_tls_get (guint8* code, int dreg, int tls_offset)
2146 {
2147         if (optimize_for_xen) {
2148                 x86_prefix (code, X86_FS_PREFIX);
2149                 amd64_mov_reg_mem (code, dreg, 0, 8);
2150                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2151         } else {
2152                 x86_prefix (code, X86_FS_PREFIX);
2153                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2154         }
2155         return code;
2156 }
2157
2158 /*
2159  * emit_load_volatile_arguments:
2160  *
2161  *  Load volatile arguments from the stack to the original input registers.
2162  * Required before a tail call.
2163  */
2164 static guint8*
2165 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2166 {
2167         MonoMethod *method = cfg->method;
2168         MonoMethodSignature *sig;
2169         MonoInst *inst;
2170         CallInfo *cinfo;
2171         guint32 i;
2172
2173         /* FIXME: Generate intermediate code instead */
2174
2175         sig = mono_method_signature (method);
2176
2177         cinfo = get_call_info (sig, FALSE);
2178
2179         /* This is the opposite of the code in emit_prolog */
2180
2181         if (sig->ret->type != MONO_TYPE_VOID) {
2182                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
2183                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->ret->inst_basereg, cfg->ret->inst_offset, 8);
2184                 }
2185         }
2186
2187         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2188                 ArgInfo *ainfo = cinfo->args + i;
2189                 MonoType *arg_type;
2190                 inst = cfg->varinfo [i];
2191
2192                 if (sig->hasthis && (i == 0))
2193                         arg_type = &mono_defaults.object_class->byval_arg;
2194                 else
2195                         arg_type = sig->params [i - sig->hasthis];
2196
2197                 if (inst->opcode != OP_REGVAR) {
2198                         switch (ainfo->storage) {
2199                         case ArgInIReg: {
2200                                 guint32 size = 8;
2201
2202                                 /* FIXME: I1 etc */
2203                                 amd64_mov_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset, size);
2204                                 break;
2205                         }
2206                         case ArgInFloatSSEReg:
2207                                 amd64_movss_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2208                                 break;
2209                         case ArgInDoubleSSEReg:
2210                                 amd64_movsd_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2211                                 break;
2212                         default:
2213                                 break;
2214                         }
2215                 }
2216                 else {
2217                         g_assert (ainfo->storage == ArgInIReg);
2218
2219                         amd64_mov_reg_reg (code, ainfo->reg, inst->dreg, 8);
2220                 }
2221         }
2222
2223         g_free (cinfo);
2224
2225         return code;
2226 }
2227
2228 #define REAL_PRINT_REG(text,reg) \
2229 mono_assert (reg >= 0); \
2230 amd64_push_reg (code, AMD64_RAX); \
2231 amd64_push_reg (code, AMD64_RDX); \
2232 amd64_push_reg (code, AMD64_RCX); \
2233 amd64_push_reg (code, reg); \
2234 amd64_push_imm (code, reg); \
2235 amd64_push_imm (code, text " %d %p\n"); \
2236 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2237 amd64_call_reg (code, AMD64_RAX); \
2238 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2239 amd64_pop_reg (code, AMD64_RCX); \
2240 amd64_pop_reg (code, AMD64_RDX); \
2241 amd64_pop_reg (code, AMD64_RAX);
2242
2243 /* benchmark and set based on cpu */
2244 #define LOOP_ALIGNMENT 8
2245 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2246
2247 void
2248 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2249 {
2250         MonoInst *ins;
2251         MonoCallInst *call;
2252         guint offset;
2253         guint8 *code = cfg->native_code + cfg->code_len;
2254         MonoInst *last_ins = NULL;
2255         guint last_offset = 0;
2256         int max_len, cpos;
2257
2258         if (cfg->opt & MONO_OPT_PEEPHOLE)
2259                 peephole_pass (cfg, bb);
2260
2261         if (cfg->opt & MONO_OPT_LOOP) {
2262                 int pad, align = LOOP_ALIGNMENT;
2263                 /* set alignment depending on cpu */
2264                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2265                         pad = align - pad;
2266                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2267                         amd64_padding (code, pad);
2268                         cfg->code_len += pad;
2269                         bb->native_offset = cfg->code_len;
2270                 }
2271         }
2272
2273         if (cfg->verbose_level > 2)
2274                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2275
2276         cpos = bb->max_offset;
2277
2278         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2279                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2280                 g_assert (!cfg->compile_aot);
2281                 cpos += 6;
2282
2283                 cov->data [bb->dfn].cil_code = bb->cil_code;
2284                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2285                 /* this is not thread save, but good enough */
2286                 amd64_inc_membase (code, AMD64_R11, 0);
2287         }
2288
2289         offset = code - cfg->native_code;
2290
2291         mono_debug_open_block (cfg, bb, offset);
2292
2293         ins = bb->code;
2294         while (ins) {
2295                 offset = code - cfg->native_code;
2296
2297                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2298
2299                 if (offset > (cfg->code_size - max_len - 16)) {
2300                         cfg->code_size *= 2;
2301                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2302                         code = cfg->native_code + offset;
2303                         mono_jit_stats.code_reallocs++;
2304                 }
2305
2306                 mono_debug_record_line_number (cfg, ins, offset);
2307
2308                 switch (ins->opcode) {
2309                 case OP_BIGMUL:
2310                         amd64_mul_reg (code, ins->sreg2, TRUE);
2311                         break;
2312                 case OP_BIGMUL_UN:
2313                         amd64_mul_reg (code, ins->sreg2, FALSE);
2314                         break;
2315                 case OP_X86_SETEQ_MEMBASE:
2316                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2317                         break;
2318                 case OP_STOREI1_MEMBASE_IMM:
2319                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2320                         break;
2321                 case OP_STOREI2_MEMBASE_IMM:
2322                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2323                         break;
2324                 case OP_STOREI4_MEMBASE_IMM:
2325                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2326                         break;
2327                 case OP_STOREI1_MEMBASE_REG:
2328                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2329                         break;
2330                 case OP_STOREI2_MEMBASE_REG:
2331                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2332                         break;
2333                 case OP_STORE_MEMBASE_REG:
2334                 case OP_STOREI8_MEMBASE_REG:
2335                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2336                         break;
2337                 case OP_STOREI4_MEMBASE_REG:
2338                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2339                         break;
2340                 case OP_STORE_MEMBASE_IMM:
2341                 case OP_STOREI8_MEMBASE_IMM:
2342                         g_assert (amd64_is_imm32 (ins->inst_imm));
2343                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2344                         break;
2345                 case CEE_LDIND_I:
2346                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, sizeof (gpointer));
2347                         break;
2348                 case CEE_LDIND_I4:
2349                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2350                         break;
2351                 case CEE_LDIND_U4:
2352                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2353                         break;
2354                 case OP_LOADU4_MEM:
2355                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2356                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2357                         break;
2358                 case OP_LOAD_MEMBASE:
2359                 case OP_LOADI8_MEMBASE:
2360                         g_assert (amd64_is_imm32 (ins->inst_offset));
2361                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2362                         break;
2363                 case OP_LOADI4_MEMBASE:
2364                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2365                         break;
2366                 case OP_LOADU4_MEMBASE:
2367                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2368                         break;
2369                 case OP_LOADU1_MEMBASE:
2370                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2371                         break;
2372                 case OP_LOADI1_MEMBASE:
2373                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2374                         break;
2375                 case OP_LOADU2_MEMBASE:
2376                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2377                         break;
2378                 case OP_LOADI2_MEMBASE:
2379                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2380                         break;
2381                 case OP_AMD64_LOADI8_MEMINDEX:
2382                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2383                         break;
2384                 case CEE_CONV_I1:
2385                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2386                         break;
2387                 case CEE_CONV_I2:
2388                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2389                         break;
2390                 case CEE_CONV_U1:
2391                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2392                         break;
2393                 case CEE_CONV_U2:
2394                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2395                         break;
2396                 case CEE_CONV_U8:
2397                 case CEE_CONV_U:
2398                         /* Clean out the upper word */
2399                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2400                         break;
2401                 case CEE_CONV_I8:
2402                 case CEE_CONV_I:
2403                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2404                         break;
2405                 case OP_COMPARE:
2406                 case OP_LCOMPARE:
2407                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2408                         break;
2409                 case OP_COMPARE_IMM:
2410                         g_assert (amd64_is_imm32 (ins->inst_imm));
2411                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2412                         break;
2413                 case OP_X86_COMPARE_REG_MEMBASE:
2414                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2415                         break;
2416                 case OP_X86_TEST_NULL:
2417                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2418                         break;
2419                 case OP_AMD64_TEST_NULL:
2420                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2421                         break;
2422                 case OP_X86_ADD_MEMBASE_IMM:
2423                         /* FIXME: Make a 64 version too */
2424                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2425                         break;
2426                 case OP_X86_ADD_MEMBASE:
2427                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2428                         break;
2429                 case OP_X86_SUB_MEMBASE_IMM:
2430                         g_assert (amd64_is_imm32 (ins->inst_imm));
2431                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2432                         break;
2433                 case OP_X86_SUB_MEMBASE:
2434                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2435                         break;
2436                 case OP_X86_INC_MEMBASE:
2437                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2438                         break;
2439                 case OP_X86_INC_REG:
2440                         amd64_inc_reg_size (code, ins->dreg, 4);
2441                         break;
2442                 case OP_X86_DEC_MEMBASE:
2443                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2444                         break;
2445                 case OP_X86_DEC_REG:
2446                         amd64_dec_reg_size (code, ins->dreg, 4);
2447                         break;
2448                 case OP_X86_MUL_MEMBASE:
2449                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2450                         break;
2451                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2452                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2453                         break;
2454                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2455                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2456                         break;
2457                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2458                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2459                         break;
2460                 case CEE_BREAK:
2461                         amd64_breakpoint (code);
2462                         break;
2463                 case OP_ADDCC:
2464                 case CEE_ADD:
2465                 case OP_LADD:
2466                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2467                         break;
2468                 case OP_ADC:
2469                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2470                         break;
2471                 case OP_ADD_IMM:
2472                         g_assert (amd64_is_imm32 (ins->inst_imm));
2473                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2474                         break;
2475                 case OP_ADC_IMM:
2476                         g_assert (amd64_is_imm32 (ins->inst_imm));
2477                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2478                         break;
2479                 case OP_SUBCC:
2480                 case CEE_SUB:
2481                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2482                         break;
2483                 case OP_SBB:
2484                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2485                         break;
2486                 case OP_SUB_IMM:
2487                         g_assert (amd64_is_imm32 (ins->inst_imm));
2488                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2489                         break;
2490                 case OP_SBB_IMM:
2491                         g_assert (amd64_is_imm32 (ins->inst_imm));
2492                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2493                         break;
2494                 case CEE_AND:
2495                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2496                         break;
2497                 case OP_AND_IMM:
2498                         g_assert (amd64_is_imm32 (ins->inst_imm));
2499                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2500                         break;
2501                 case CEE_MUL:
2502                 case OP_LMUL:
2503                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2504                         break;
2505                 case OP_MUL_IMM:
2506                 case OP_LMUL_IMM:
2507                 case OP_IMUL_IMM: {
2508                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2509
2510                         switch (ins->inst_imm) {
2511                         case 2:
2512                                 /* MOV r1, r2 */
2513                                 /* ADD r1, r1 */
2514                                 if (ins->dreg != ins->sreg1)
2515                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2516                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2517                                 break;
2518                         case 3:
2519                                 /* LEA r1, [r2 + r2*2] */
2520                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2521                                 break;
2522                         case 5:
2523                                 /* LEA r1, [r2 + r2*4] */
2524                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2525                                 break;
2526                         case 6:
2527                                 /* LEA r1, [r2 + r2*2] */
2528                                 /* ADD r1, r1          */
2529                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2530                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2531                                 break;
2532                         case 9:
2533                                 /* LEA r1, [r2 + r2*8] */
2534                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2535                                 break;
2536                         case 10:
2537                                 /* LEA r1, [r2 + r2*4] */
2538                                 /* ADD r1, r1          */
2539                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2540                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2541                                 break;
2542                         case 12:
2543                                 /* LEA r1, [r2 + r2*2] */
2544                                 /* SHL r1, 2           */
2545                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2546                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2547                                 break;
2548                         case 25:
2549                                 /* LEA r1, [r2 + r2*4] */
2550                                 /* LEA r1, [r1 + r1*4] */
2551                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2552                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2553                                 break;
2554                         case 100:
2555                                 /* LEA r1, [r2 + r2*4] */
2556                                 /* SHL r1, 2           */
2557                                 /* LEA r1, [r1 + r1*4] */
2558                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2559                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2560                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2561                                 break;
2562                         default:
2563                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2564                                 break;
2565                         }
2566                         break;
2567                 }
2568                 case CEE_DIV:
2569                 case OP_LDIV:
2570                         amd64_cdq (code);
2571                         amd64_div_reg (code, ins->sreg2, TRUE);
2572                         break;
2573                 case CEE_DIV_UN:
2574                 case OP_LDIV_UN:
2575                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2576                         amd64_div_reg (code, ins->sreg2, FALSE);
2577                         break;
2578                 case CEE_REM:
2579                 case OP_LREM:
2580                         amd64_cdq (code);
2581                         amd64_div_reg (code, ins->sreg2, TRUE);
2582                         break;
2583                 case CEE_REM_UN:
2584                 case OP_LREM_UN:
2585                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2586                         amd64_div_reg (code, ins->sreg2, FALSE);
2587                         break;
2588                 case OP_LMUL_OVF:
2589                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2590                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2591                         break;
2592                 case CEE_OR:
2593                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2594                         break;
2595                 case OP_OR_IMM
2596 :                       g_assert (amd64_is_imm32 (ins->inst_imm));
2597                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2598                         break;
2599                 case CEE_XOR:
2600                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2601                         break;
2602                 case OP_XOR_IMM:
2603                         g_assert (amd64_is_imm32 (ins->inst_imm));
2604                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2605                         break;
2606                 case CEE_SHL:
2607                 case OP_LSHL:
2608                         g_assert (ins->sreg2 == AMD64_RCX);
2609                         amd64_shift_reg (code, X86_SHL, ins->dreg);
2610                         break;
2611                 case CEE_SHR:
2612                 case OP_LSHR:
2613                         g_assert (ins->sreg2 == AMD64_RCX);
2614                         amd64_shift_reg (code, X86_SAR, ins->dreg);
2615                         break;
2616                 case OP_SHR_IMM:
2617                         g_assert (amd64_is_imm32 (ins->inst_imm));
2618                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2619                         break;
2620                 case OP_LSHR_IMM:
2621                         g_assert (amd64_is_imm32 (ins->inst_imm));
2622                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2623                         break;
2624                 case OP_SHR_UN_IMM:
2625                         g_assert (amd64_is_imm32 (ins->inst_imm));
2626                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2627                         break;
2628                 case OP_LSHR_UN_IMM:
2629                         g_assert (amd64_is_imm32 (ins->inst_imm));
2630                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2631                         break;
2632                 case CEE_SHR_UN:
2633                         g_assert (ins->sreg2 == AMD64_RCX);
2634                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2635                         break;
2636                 case OP_LSHR_UN:
2637                         g_assert (ins->sreg2 == AMD64_RCX);
2638                         amd64_shift_reg (code, X86_SHR, ins->dreg);
2639                         break;
2640                 case OP_SHL_IMM:
2641                         g_assert (amd64_is_imm32 (ins->inst_imm));
2642                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2643                         break;
2644                 case OP_LSHL_IMM:
2645                         g_assert (amd64_is_imm32 (ins->inst_imm));
2646                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2647                         break;
2648
2649                 case OP_IADDCC:
2650                 case OP_IADD:
2651                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
2652                         break;
2653                 case OP_IADC:
2654                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
2655                         break;
2656                 case OP_IADD_IMM:
2657                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
2658                         break;
2659                 case OP_IADC_IMM:
2660                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
2661                         break;
2662                 case OP_ISUBCC:
2663                 case OP_ISUB:
2664                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
2665                         break;
2666                 case OP_ISBB:
2667                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
2668                         break;
2669                 case OP_ISUB_IMM:
2670                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
2671                         break;
2672                 case OP_ISBB_IMM:
2673                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
2674                         break;
2675                 case OP_IAND:
2676                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
2677                         break;
2678                 case OP_IAND_IMM:
2679                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
2680                         break;
2681                 case OP_IOR:
2682                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
2683                         break;
2684                 case OP_IOR_IMM:
2685                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
2686                         break;
2687                 case OP_IXOR:
2688                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
2689                         break;
2690                 case OP_IXOR_IMM:
2691                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
2692                         break;
2693                 case OP_INEG:
2694                         amd64_neg_reg_size (code, ins->sreg1, 4);
2695                         break;
2696                 case OP_INOT:
2697                         amd64_not_reg_size (code, ins->sreg1, 4);
2698                         break;
2699                 case OP_ISHL:
2700                         g_assert (ins->sreg2 == AMD64_RCX);
2701                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
2702                         break;
2703                 case OP_ISHR:
2704                         g_assert (ins->sreg2 == AMD64_RCX);
2705                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
2706                         break;
2707                 case OP_ISHR_IMM:
2708                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2709                         break;
2710                 case OP_ISHR_UN_IMM:
2711                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2712                         break;
2713                 case OP_ISHR_UN:
2714                         g_assert (ins->sreg2 == AMD64_RCX);
2715                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2716                         break;
2717                 case OP_ISHL_IMM:
2718                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2719                         break;
2720                 case OP_IMUL:
2721                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2722                         break;
2723                 case OP_IMUL_OVF:
2724                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2725                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2726                         break;
2727                 case OP_IMUL_OVF_UN:
2728                 case OP_LMUL_OVF_UN: {
2729                         /* the mul operation and the exception check should most likely be split */
2730                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2731                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
2732                         /*g_assert (ins->sreg2 == X86_EAX);
2733                         g_assert (ins->dreg == X86_EAX);*/
2734                         if (ins->sreg2 == X86_EAX) {
2735                                 non_eax_reg = ins->sreg1;
2736                         } else if (ins->sreg1 == X86_EAX) {
2737                                 non_eax_reg = ins->sreg2;
2738                         } else {
2739                                 /* no need to save since we're going to store to it anyway */
2740                                 if (ins->dreg != X86_EAX) {
2741                                         saved_eax = TRUE;
2742                                         amd64_push_reg (code, X86_EAX);
2743                                 }
2744                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
2745                                 non_eax_reg = ins->sreg2;
2746                         }
2747                         if (ins->dreg == X86_EDX) {
2748                                 if (!saved_eax) {
2749                                         saved_eax = TRUE;
2750                                         amd64_push_reg (code, X86_EAX);
2751                                 }
2752                         } else {
2753                                 saved_edx = TRUE;
2754                                 amd64_push_reg (code, X86_EDX);
2755                         }
2756                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
2757                         /* save before the check since pop and mov don't change the flags */
2758                         if (ins->dreg != X86_EAX)
2759                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
2760                         if (saved_edx)
2761                                 amd64_pop_reg (code, X86_EDX);
2762                         if (saved_eax)
2763                                 amd64_pop_reg (code, X86_EAX);
2764                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2765                         break;
2766                 }
2767                 case OP_IDIV:
2768                         amd64_cdq_size (code, 4);
2769                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2770                         break;
2771                 case OP_IDIV_UN:
2772                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2773                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2774                         break;
2775                 case OP_IREM:
2776                         amd64_cdq_size (code, 4);
2777                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2778                         break;
2779                 case OP_IREM_UN:
2780                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2781                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2782                         break;
2783                 case OP_ICOMPARE:
2784                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
2785                         break;
2786                 case OP_ICOMPARE_IMM:
2787                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
2788                         break;
2789                 case OP_IBEQ:
2790                 case OP_IBLT:
2791                 case OP_IBGT:
2792                 case OP_IBGE:
2793                 case OP_IBLE:
2794                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), TRUE);
2795                         break;
2796                 case OP_IBNE_UN:
2797                 case OP_IBLT_UN:
2798                 case OP_IBGT_UN:
2799                 case OP_IBGE_UN:
2800                 case OP_IBLE_UN:
2801                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), FALSE);
2802                         break;
2803                 case OP_COND_EXC_IOV:
2804                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2805                                                                                 TRUE, ins->inst_p1);
2806                         break;
2807                 case OP_COND_EXC_IC:
2808                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2809                                                                                 FALSE, ins->inst_p1);
2810                         break;
2811                 case CEE_NOT:
2812                         amd64_not_reg (code, ins->sreg1);
2813                         break;
2814                 case CEE_NEG:
2815                         amd64_neg_reg (code, ins->sreg1);
2816                         break;
2817                 case OP_SEXT_I1:
2818                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2819                         break;
2820                 case OP_SEXT_I2:
2821                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2822                         break;
2823                 case OP_SEXT_I4:
2824                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2825                         break;
2826                 case OP_ICONST:
2827                 case OP_I8CONST:
2828                         if ((((guint64)ins->inst_c0) >> 32) == 0)
2829                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
2830                         else
2831                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
2832                         break;
2833                 case OP_AOTCONST:
2834                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2835                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
2836                         break;
2837                 case CEE_CONV_I4:
2838                 case CEE_CONV_U4:
2839                 case OP_MOVE:
2840                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
2841                         break;
2842                 case OP_AMD64_SET_XMMREG_R4: {
2843                         if (use_sse2) {
2844                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
2845                         }
2846                         else {
2847                                 amd64_fst_membase (code, AMD64_RSP, -8, FALSE, TRUE);
2848                                 /* ins->dreg is set to -1 by the reg allocator */
2849                                 amd64_movss_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
2850                         }
2851                         break;
2852                 }
2853                 case OP_AMD64_SET_XMMREG_R8: {
2854                         if (use_sse2) {
2855                                 if (ins->dreg != ins->sreg1)
2856                                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
2857                         }
2858                         else {
2859                                 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE);
2860                                 /* ins->dreg is set to -1 by the reg allocator */
2861                                 amd64_movsd_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
2862                         }
2863                         break;
2864                 }
2865                 case CEE_JMP: {
2866                         /*
2867                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2868                          * Keep in sync with the code in emit_epilog.
2869                          */
2870                         int pos = 0, i;
2871
2872                         /* FIXME: no tracing support... */
2873                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2874                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2875
2876                         g_assert (!cfg->method->save_lmf);
2877
2878                         code = emit_load_volatile_arguments (cfg, code);
2879
2880                         if (cfg->arch.omit_fp) {
2881                                 guint32 save_offset = 0;
2882                                 /* Pop callee-saved registers */
2883                                 for (i = 0; i < AMD64_NREG; ++i)
2884                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2885                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
2886                                                 save_offset += 8;
2887                                         }
2888                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
2889                         }
2890                         else {
2891                                 for (i = 0; i < AMD64_NREG; ++i)
2892                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
2893                                                 pos -= sizeof (gpointer);
2894
2895                                 if (pos)
2896                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
2897
2898                                 /* Pop registers in reverse order */
2899                                 for (i = AMD64_NREG - 1; i > 0; --i)
2900                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2901                                                 amd64_pop_reg (code, i);
2902                                         }
2903
2904                                 amd64_leave (code);
2905                         }
2906
2907                         offset = code - cfg->native_code;
2908                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2909                         if (cfg->compile_aot)
2910                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
2911                         else
2912                                 amd64_set_reg_template (code, AMD64_R11);
2913                         amd64_jump_reg (code, AMD64_R11);
2914                         break;
2915                 }
2916                 case OP_CHECK_THIS:
2917                         /* ensure ins->sreg1 is not NULL */
2918                         amd64_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2919                         break;
2920                 case OP_ARGLIST: {
2921                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
2922                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
2923                         break;
2924                 }
2925                 case OP_FCALL:
2926                 case OP_LCALL:
2927                 case OP_VCALL:
2928                 case OP_VOIDCALL:
2929                 case CEE_CALL:
2930                         call = (MonoCallInst*)ins;
2931                         /*
2932                          * The AMD64 ABI forces callers to know about varargs.
2933                          */
2934                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
2935                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2936                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
2937                                 /*
2938                                  * Since the unmanaged calling convention doesn't contain a
2939                                  * 'vararg' entry, we have to treat every pinvoke call as a
2940                                  * potential vararg call.
2941                                  */
2942                                 guint32 nregs, i;
2943                                 nregs = 0;
2944                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
2945                                         if (call->used_fregs & (1 << i))
2946                                                 nregs ++;
2947                                 if (!nregs)
2948                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2949                                 else
2950                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
2951                         }
2952
2953                         if (ins->flags & MONO_INST_HAS_METHOD)
2954                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2955                         else
2956                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2957                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2958                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2959                         code = emit_move_return_value (cfg, ins, code);
2960                         break;
2961                 case OP_FCALL_REG:
2962                 case OP_LCALL_REG:
2963                 case OP_VCALL_REG:
2964                 case OP_VOIDCALL_REG:
2965                 case OP_CALL_REG:
2966                         call = (MonoCallInst*)ins;
2967
2968                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2969                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
2970                                 ins->sreg1 = AMD64_R11;
2971                         }
2972
2973                         /*
2974                          * The AMD64 ABI forces callers to know about varargs.
2975                          */
2976                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
2977                                 if (ins->sreg1 == AMD64_RAX) {
2978                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
2979                                         ins->sreg1 = AMD64_R11;
2980                                 }
2981                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2982                         }
2983                         amd64_call_reg (code, ins->sreg1);
2984                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2985                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2986                         code = emit_move_return_value (cfg, ins, code);
2987                         break;
2988                 case OP_FCALL_MEMBASE:
2989                 case OP_LCALL_MEMBASE:
2990                 case OP_VCALL_MEMBASE:
2991                 case OP_VOIDCALL_MEMBASE:
2992                 case OP_CALL_MEMBASE:
2993                         call = (MonoCallInst*)ins;
2994
2995                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2996                                 /*
2997                                  * Can't use R11 because it is clobbered by the trampoline
2998                                  * code, and the reg value is needed by get_vcall_slot_addr.
2999                                  */
3000                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3001                                 ins->sreg1 = AMD64_RAX;
3002                         }
3003
3004                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3005                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3006                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3007                         code = emit_move_return_value (cfg, ins, code);
3008                         break;
3009                 case OP_OUTARG:
3010                 case OP_X86_PUSH:
3011                         amd64_push_reg (code, ins->sreg1);
3012                         break;
3013                 case OP_X86_PUSH_IMM:
3014                         g_assert (amd64_is_imm32 (ins->inst_imm));
3015                         amd64_push_imm (code, ins->inst_imm);
3016                         break;
3017                 case OP_X86_PUSH_MEMBASE:
3018                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3019                         break;
3020                 case OP_X86_PUSH_OBJ:
3021                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3022                         amd64_push_reg (code, AMD64_RDI);
3023                         amd64_push_reg (code, AMD64_RSI);
3024                         amd64_push_reg (code, AMD64_RCX);
3025                         if (ins->inst_offset)
3026                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3027                         else
3028                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3029                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3030                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3031                         amd64_cld (code);
3032                         amd64_prefix (code, X86_REP_PREFIX);
3033                         amd64_movsd (code);
3034                         amd64_pop_reg (code, AMD64_RCX);
3035                         amd64_pop_reg (code, AMD64_RSI);
3036                         amd64_pop_reg (code, AMD64_RDI);
3037                         break;
3038                 case OP_X86_LEA:
3039                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3040                         break;
3041                 case OP_X86_LEA_MEMBASE:
3042                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3043                         break;
3044                 case OP_X86_XCHG:
3045                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3046                         break;
3047                 case OP_LOCALLOC:
3048                         /* keep alignment */
3049                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3050                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3051                         code = mono_emit_stack_alloc (code, ins);
3052                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3053                         break;
3054                 case CEE_RET:
3055                         amd64_ret (code);
3056                         break;
3057                 case CEE_THROW: {
3058                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3059                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3060                                              (gpointer)"mono_arch_throw_exception");
3061                         break;
3062                 }
3063                 case OP_RETHROW: {
3064                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3065                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3066                                              (gpointer)"mono_arch_rethrow_exception");
3067                         break;
3068                 }
3069                 case OP_CALL_HANDLER:
3070                         /* Align stack */
3071                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3072                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3073                         amd64_call_imm (code, 0);
3074                         /* Restore stack alignment */
3075                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3076                         break;
3077                 case OP_LABEL:
3078                         ins->inst_c0 = code - cfg->native_code;
3079                         break;
3080                 case CEE_BR:
3081                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3082                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3083                         //break;
3084                         if (ins->flags & MONO_INST_BRLABEL) {
3085                                 if (ins->inst_i0->inst_c0) {
3086                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3087                                 } else {
3088                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3089                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3090                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3091                                                 x86_jump8 (code, 0);
3092                                         else
3093                                                 x86_jump32 (code, 0);
3094                                 }
3095                         } else {
3096                                 if (ins->inst_target_bb->native_offset) {
3097                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3098                                 } else {
3099                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3100                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3101                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3102                                                 x86_jump8 (code, 0);
3103                                         else
3104                                                 x86_jump32 (code, 0);
3105                                 }
3106                         }
3107                         break;
3108                 case OP_BR_REG:
3109                         amd64_jump_reg (code, ins->sreg1);
3110                         break;
3111                 case OP_CEQ:
3112                 case OP_ICEQ:
3113                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3114                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3115                         break;
3116                 case OP_CLT:
3117                 case OP_ICLT:
3118                         amd64_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
3119                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3120                         break;
3121                 case OP_CLT_UN:
3122                 case OP_ICLT_UN:
3123                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3124                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3125                         break;
3126                 case OP_CGT:
3127                 case OP_ICGT:
3128                         amd64_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
3129                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3130                         break;
3131                 case OP_CGT_UN:
3132                 case OP_ICGT_UN:
3133                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3134                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3135                         break;
3136                 case OP_COND_EXC_EQ:
3137                 case OP_COND_EXC_NE_UN:
3138                 case OP_COND_EXC_LT:
3139                 case OP_COND_EXC_LT_UN:
3140                 case OP_COND_EXC_GT:
3141                 case OP_COND_EXC_GT_UN:
3142                 case OP_COND_EXC_GE:
3143                 case OP_COND_EXC_GE_UN:
3144                 case OP_COND_EXC_LE:
3145                 case OP_COND_EXC_LE_UN:
3146                 case OP_COND_EXC_OV:
3147                 case OP_COND_EXC_NO:
3148                 case OP_COND_EXC_C:
3149                 case OP_COND_EXC_NC:
3150                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3151                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3152                         break;
3153                 case CEE_BEQ:
3154                 case CEE_BNE_UN:
3155                 case CEE_BLT:
3156                 case CEE_BLT_UN:
3157                 case CEE_BGT:
3158                 case CEE_BGT_UN:
3159                 case CEE_BGE:
3160                 case CEE_BGE_UN:
3161                 case CEE_BLE:
3162                 case CEE_BLE_UN:
3163                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
3164                         break;
3165
3166                 /* floating point opcodes */
3167                 case OP_R8CONST: {
3168                         double d = *(double *)ins->inst_p0;
3169
3170                         if (use_sse2) {
3171                                 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3172                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3173                                 }
3174                                 else {
3175                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3176                                         amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3177                                 }
3178                         }
3179                         else if ((d == 0.0) && (mono_signbit (d) == 0)) {
3180                                 amd64_fldz (code);
3181                         } else if (d == 1.0) {
3182                                 x86_fld1 (code);
3183                         } else {
3184                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3185                                 amd64_fld_membase (code, AMD64_RIP, 0, TRUE);
3186                         }
3187                         break;
3188                 }
3189                 case OP_R4CONST: {
3190                         float f = *(float *)ins->inst_p0;
3191
3192                         if (use_sse2) {
3193                                 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3194                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3195                                 }
3196                                 else {
3197                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3198                                         amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3199                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3200                                 }
3201                         }
3202                         else if ((f == 0.0) && (mono_signbit (f) == 0)) {
3203                                 amd64_fldz (code);
3204                         } else if (f == 1.0) {
3205                                 x86_fld1 (code);
3206                         } else {
3207                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3208                                 amd64_fld_membase (code, AMD64_RIP, 0, FALSE);
3209                         }
3210                         break;
3211                 }
3212                 case OP_STORER8_MEMBASE_REG:
3213                         if (use_sse2)
3214                                 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3215                         else
3216                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3217                         break;
3218                 case OP_LOADR8_SPILL_MEMBASE:
3219                         if (use_sse2)
3220                                 g_assert_not_reached ();
3221                         amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3222                         amd64_fxch (code, 1);
3223                         break;
3224                 case OP_LOADR8_MEMBASE:
3225                         if (use_sse2)
3226                                 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3227                         else
3228                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3229                         break;
3230                 case OP_STORER4_MEMBASE_REG:
3231                         if (use_sse2) {
3232                                 /* This requires a double->single conversion */
3233                                 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3234                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3235                         }
3236                         else
3237                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3238                         break;
3239                 case OP_LOADR4_MEMBASE:
3240                         if (use_sse2) {
3241                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3242                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3243                         }
3244                         else
3245                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3246                         break;
3247                 case CEE_CONV_R4: /* FIXME: change precision */
3248                 case CEE_CONV_R8:
3249                         if (use_sse2)
3250                                 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3251                         else {
3252                                 amd64_push_reg (code, ins->sreg1);
3253                                 amd64_fild_membase (code, AMD64_RSP, 0, FALSE);
3254                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3255                         }
3256                         break;
3257                 case CEE_CONV_R_UN:
3258                         /* Emulated */
3259                         g_assert_not_reached ();
3260                         break;
3261                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3262                 case OP_LCONV_TO_R8:
3263                         if (use_sse2)
3264                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3265                         else {
3266                                 amd64_push_reg (code, ins->sreg1);
3267                                 amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3268                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3269                         }
3270                         break;
3271                 case OP_X86_FP_LOAD_I8:
3272                         if (use_sse2)
3273                                 g_assert_not_reached ();
3274                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3275                         break;
3276                 case OP_X86_FP_LOAD_I4:
3277                         if (use_sse2)
3278                                 g_assert_not_reached ();
3279                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3280                         break;
3281                 case OP_FCONV_TO_I1:
3282                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3283                         break;
3284                 case OP_FCONV_TO_U1:
3285                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3286                         break;
3287                 case OP_FCONV_TO_I2:
3288                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3289                         break;
3290                 case OP_FCONV_TO_U2:
3291                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3292                         break;
3293                 case OP_FCONV_TO_I4:
3294                 case OP_FCONV_TO_I:
3295                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3296                         break;
3297                 case OP_FCONV_TO_I8:
3298                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3299                         break;
3300                 case OP_LCONV_TO_R_UN: {
3301                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3302                         guint8 *br;
3303
3304                         if (use_sse2)
3305                                 g_assert_not_reached ();
3306
3307                         /* load 64bit integer to FP stack */
3308                         amd64_push_imm (code, 0);
3309                         amd64_push_reg (code, ins->sreg2);
3310                         amd64_push_reg (code, ins->sreg1);
3311                         amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3312                         /* store as 80bit FP value */
3313                         x86_fst80_membase (code, AMD64_RSP, 0);
3314
3315                         /* test if lreg is negative */
3316                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
3317                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3318
3319                         /* add correction constant mn */
3320                         x86_fld80_mem (code, mn);
3321                         x86_fld80_membase (code, AMD64_RSP, 0);
3322                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3323                         x86_fst80_membase (code, AMD64_RSP, 0);
3324
3325                         amd64_patch (br, code);
3326
3327                         x86_fld80_membase (code, AMD64_RSP, 0);
3328                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 12);
3329
3330                         break;
3331                 }
3332                 case CEE_CONV_OVF_U4:
3333                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3334                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3335                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3336                         break;
3337                 case CEE_CONV_OVF_I4_UN:
3338                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3339                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3340                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3341                         break;
3342                 case OP_FMOVE:
3343                         if (use_sse2 && (ins->dreg != ins->sreg1))
3344                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3345                         break;
3346                 case OP_FADD:
3347                         if (use_sse2)
3348                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3349                         else
3350                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3351                         break;
3352                 case OP_FSUB:
3353                         if (use_sse2)
3354                                 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3355                         else
3356                                 amd64_fp_op_reg (code, X86_FSUB, 1, TRUE);
3357                         break;
3358                 case OP_FMUL:
3359                         if (use_sse2)
3360                                 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3361                         else
3362                                 amd64_fp_op_reg (code, X86_FMUL, 1, TRUE);
3363                         break;
3364                 case OP_FDIV:
3365                         if (use_sse2)
3366                                 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3367                         else
3368                                 amd64_fp_op_reg (code, X86_FDIV, 1, TRUE);
3369                         break;
3370                 case OP_FNEG:
3371                         if (use_sse2) {
3372                                 static double r8_0 = -0.0;
3373
3374                                 g_assert (ins->sreg1 == ins->dreg);
3375
3376                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3377                                 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3378                         }
3379                         else
3380                                 amd64_fchs (code);
3381                         break;
3382                 case OP_SIN:
3383                         if (use_sse2) {
3384                                 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3385                         }
3386                         else {
3387                                 amd64_fsin (code);
3388                                 amd64_fldz (code);
3389                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3390                         }
3391                         break;
3392                 case OP_COS:
3393                         if (use_sse2) {
3394                                 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3395                         }
3396                         else {
3397                                 amd64_fcos (code);
3398                                 amd64_fldz (code);
3399                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3400                         }
3401                         break;
3402                 case OP_ABS:
3403                         if (use_sse2) {
3404                                 EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
3405                         }
3406                         else
3407                                 amd64_fabs (code);
3408                         break;
3409                 case OP_TAN: {
3410                         /*
3411                          * it really doesn't make sense to inline all this code,
3412                          * it's here just to show that things may not be as simple
3413                          * as they appear.
3414                          */
3415                         guchar *check_pos, *end_tan, *pop_jump;
3416                         if (use_sse2)
3417                                 g_assert_not_reached ();
3418                         amd64_push_reg (code, AMD64_RAX);
3419                         amd64_fptan (code);
3420                         amd64_fnstsw (code);
3421                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3422                         check_pos = code;
3423                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3424                         amd64_fstp (code, 0); /* pop the 1.0 */
3425                         end_tan = code;
3426                         x86_jump8 (code, 0);
3427                         amd64_fldpi (code);
3428                         amd64_fp_op (code, X86_FADD, 0);
3429                         amd64_fxch (code, 1);
3430                         x86_fprem1 (code);
3431                         amd64_fstsw (code);
3432                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3433                         pop_jump = code;
3434                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3435                         amd64_fstp (code, 1);
3436                         amd64_fptan (code);
3437                         amd64_patch (pop_jump, code);
3438                         amd64_fstp (code, 0); /* pop the 1.0 */
3439                         amd64_patch (check_pos, code);
3440                         amd64_patch (end_tan, code);
3441                         amd64_fldz (code);
3442                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3443                         amd64_pop_reg (code, AMD64_RAX);
3444                         break;
3445                 }
3446                 case OP_ATAN:
3447                         if (use_sse2)
3448                                 g_assert_not_reached ();
3449                         x86_fld1 (code);
3450                         amd64_fpatan (code);
3451                         amd64_fldz (code);
3452                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3453                         break;
3454                 case OP_SQRT:
3455                         if (use_sse2) {
3456                                 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3457                         }
3458                         else
3459                                 amd64_fsqrt (code);
3460                         break;
3461                 case OP_X86_FPOP:
3462                         if (!use_sse2)
3463                                 amd64_fstp (code, 0);
3464                         break;
3465                 case OP_FREM: {
3466                         guint8 *l1, *l2;
3467
3468                         if (use_sse2)
3469                                 g_assert_not_reached ();
3470                         amd64_push_reg (code, AMD64_RAX);
3471                         /* we need to exchange ST(0) with ST(1) */
3472                         amd64_fxch (code, 1);
3473
3474                         /* this requires a loop, because fprem somtimes
3475                          * returns a partial remainder */
3476                         l1 = code;
3477                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3478                         /* x86_fprem1 (code); */
3479                         amd64_fprem (code);
3480                         amd64_fnstsw (code);
3481                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_C2);
3482                         l2 = code + 2;
3483                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3484
3485                         /* pop result */
3486                         amd64_fstp (code, 1);
3487
3488                         amd64_pop_reg (code, AMD64_RAX);
3489                         break;
3490                 }
3491                 case OP_FCOMPARE:
3492                         if (use_sse2) {
3493                                 /*
3494                                  * The two arguments are swapped because the fbranch instructions
3495                                  * depend on this for the non-sse case to work.
3496                                  */
3497                                 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3498                                 break;
3499                         }
3500                         if (cfg->opt & MONO_OPT_FCMOV) {
3501                                 amd64_fcomip (code, 1);
3502                                 amd64_fstp (code, 0);
3503                                 break;
3504                         }
3505                         /* this overwrites EAX */
3506                         EMIT_FPCOMPARE(code);
3507                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3508                         break;
3509                 case OP_FCEQ:
3510                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3511                                 /* zeroing the register at the start results in
3512                                  * shorter and faster code (we can also remove the widening op)
3513                                  */
3514                                 guchar *unordered_check;
3515                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3516
3517                                 if (use_sse2)
3518                                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3519                                 else {
3520                                         amd64_fcomip (code, 1);
3521                                         amd64_fstp (code, 0);
3522                                 }
3523                                 unordered_check = code;
3524                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3525                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3526                                 amd64_patch (unordered_check, code);
3527                                 break;
3528                         }
3529                         if (ins->dreg != AMD64_RAX)
3530                                 amd64_push_reg (code, AMD64_RAX);
3531
3532                         EMIT_FPCOMPARE(code);
3533                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3534                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3535                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3536                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3537
3538                         if (ins->dreg != AMD64_RAX)
3539                                 amd64_pop_reg (code, AMD64_RAX);
3540                         break;
3541                 case OP_FCLT:
3542                 case OP_FCLT_UN:
3543                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3544                                 /* zeroing the register at the start results in
3545                                  * shorter and faster code (we can also remove the widening op)
3546                                  */
3547                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3548                                 if (use_sse2)
3549                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3550                                 else {
3551                                         amd64_fcomip (code, 1);
3552                                         amd64_fstp (code, 0);
3553                                 }
3554                                 if (ins->opcode == OP_FCLT_UN) {
3555                                         guchar *unordered_check = code;
3556                                         guchar *jump_to_end;
3557                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3558                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3559                                         jump_to_end = code;
3560                                         x86_jump8 (code, 0);
3561                                         amd64_patch (unordered_check, code);
3562                                         amd64_inc_reg (code, ins->dreg);
3563                                         amd64_patch (jump_to_end, code);
3564                                 } else {
3565                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3566                                 }
3567                                 break;
3568                         }
3569                         if (ins->dreg != AMD64_RAX)
3570                                 amd64_push_reg (code, AMD64_RAX);
3571
3572                         EMIT_FPCOMPARE(code);
3573                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3574                         if (ins->opcode == OP_FCLT_UN) {
3575                                 guchar *is_not_zero_check, *end_jump;
3576                                 is_not_zero_check = code;
3577                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3578                                 end_jump = code;
3579                                 x86_jump8 (code, 0);
3580                                 amd64_patch (is_not_zero_check, code);
3581                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3582
3583                                 amd64_patch (end_jump, code);
3584                         }
3585                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3586                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3587
3588                         if (ins->dreg != AMD64_RAX)
3589                                 amd64_pop_reg (code, AMD64_RAX);
3590                         break;
3591                 case OP_FCGT:
3592                 case OP_FCGT_UN:
3593                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3594                                 /* zeroing the register at the start results in
3595                                  * shorter and faster code (we can also remove the widening op)
3596                                  */
3597                                 guchar *unordered_check;
3598                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3599                                 if (use_sse2)
3600                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3601                                 else {
3602                                         amd64_fcomip (code, 1);
3603                                         amd64_fstp (code, 0);
3604                                 }
3605                                 if (ins->opcode == OP_FCGT) {
3606                                         unordered_check = code;
3607                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3608                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3609                                         amd64_patch (unordered_check, code);
3610                                 } else {
3611                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3612                                 }
3613                                 break;
3614                         }
3615                         if (ins->dreg != AMD64_RAX)
3616                                 amd64_push_reg (code, AMD64_RAX);
3617
3618                         EMIT_FPCOMPARE(code);
3619                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3620                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3621                         if (ins->opcode == OP_FCGT_UN) {
3622                                 guchar *is_not_zero_check, *end_jump;
3623                                 is_not_zero_check = code;
3624                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3625                                 end_jump = code;
3626                                 x86_jump8 (code, 0);
3627                                 amd64_patch (is_not_zero_check, code);
3628                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3629
3630                                 amd64_patch (end_jump, code);
3631                         }
3632                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3633                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3634
3635                         if (ins->dreg != AMD64_RAX)
3636                                 amd64_pop_reg (code, AMD64_RAX);
3637                         break;
3638                 case OP_FCLT_MEMBASE:
3639                 case OP_FCGT_MEMBASE:
3640                 case OP_FCLT_UN_MEMBASE:
3641                 case OP_FCGT_UN_MEMBASE:
3642                 case OP_FCEQ_MEMBASE: {
3643                         guchar *unordered_check, *jump_to_end;
3644                         int x86_cond;
3645                         g_assert (use_sse2);
3646
3647                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3648                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
3649
3650                         switch (ins->opcode) {
3651                         case OP_FCEQ_MEMBASE:
3652                                 x86_cond = X86_CC_EQ;
3653                                 break;
3654                         case OP_FCLT_MEMBASE:
3655                         case OP_FCLT_UN_MEMBASE:
3656                                 x86_cond = X86_CC_LT;
3657                                 break;
3658                         case OP_FCGT_MEMBASE:
3659                         case OP_FCGT_UN_MEMBASE:
3660                                 x86_cond = X86_CC_GT;
3661                                 break;
3662                         default:
3663                                 g_assert_not_reached ();
3664                         }
3665
3666                         unordered_check = code;
3667                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3668                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
3669
3670                         switch (ins->opcode) {
3671                         case OP_FCEQ_MEMBASE:
3672                         case OP_FCLT_MEMBASE:
3673                         case OP_FCGT_MEMBASE:
3674                                 amd64_patch (unordered_check, code);
3675                                 break;
3676                         case OP_FCLT_UN_MEMBASE:
3677                         case OP_FCGT_UN_MEMBASE:
3678                                 jump_to_end = code;
3679                                 x86_jump8 (code, 0);
3680                                 amd64_patch (unordered_check, code);
3681                                 amd64_inc_reg (code, ins->dreg);
3682                                 amd64_patch (jump_to_end, code);
3683                                 break;
3684                         default:
3685                                 break;
3686                         }
3687                         break;
3688                 }
3689                 case OP_FBEQ:
3690                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3691                                 guchar *jump = code;
3692                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
3693                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3694                                 amd64_patch (jump, code);
3695                                 break;
3696                         }
3697                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3698                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3699                         break;
3700                 case OP_FBNE_UN:
3701                         /* Branch if C013 != 100 */
3702                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3703                                 /* branch if !ZF or (PF|CF) */
3704                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3705                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3706                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3707                                 break;
3708                         }
3709                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3710                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3711                         break;
3712                 case OP_FBLT:
3713                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3714                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3715                                 break;
3716                         }
3717                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3718                         break;
3719                 case OP_FBLT_UN:
3720                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3721                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3722                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3723                                 break;
3724                         }
3725                         if (ins->opcode == OP_FBLT_UN) {
3726                                 guchar *is_not_zero_check, *end_jump;
3727                                 is_not_zero_check = code;
3728                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3729                                 end_jump = code;
3730                                 x86_jump8 (code, 0);
3731                                 amd64_patch (is_not_zero_check, code);
3732                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3733
3734                                 amd64_patch (end_jump, code);
3735                         }
3736                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3737                         break;
3738                 case OP_FBGT:
3739                 case OP_FBGT_UN:
3740                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3741                                 if (ins->opcode == OP_FBGT) {
3742                                         guchar *br1;
3743
3744                                         /* skip branch if C1=1 */
3745                                         br1 = code;
3746                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3747                                         /* branch if (C0 | C3) = 1 */
3748                                         EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3749                                         amd64_patch (br1, code);
3750                                         break;
3751                                 } else {
3752                                         EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3753                                 }
3754                                 break;
3755                         }
3756                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3757                         if (ins->opcode == OP_FBGT_UN) {
3758                                 guchar *is_not_zero_check, *end_jump;
3759                                 is_not_zero_check = code;
3760                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3761                                 end_jump = code;
3762                                 x86_jump8 (code, 0);
3763                                 amd64_patch (is_not_zero_check, code);
3764                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3765
3766                                 amd64_patch (end_jump, code);
3767                         }
3768                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3769                         break;
3770                 case OP_FBGE:
3771                         /* Branch if C013 == 100 or 001 */
3772                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3773                                 guchar *br1;
3774
3775                                 /* skip branch if C1=1 */
3776                                 br1 = code;
3777                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3778                                 /* branch if (C0 | C3) = 1 */
3779                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3780                                 amd64_patch (br1, code);
3781                                 break;
3782                         }
3783                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3784                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3785                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3786                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3787                         break;
3788                 case OP_FBGE_UN:
3789                         /* Branch if C013 == 000 */
3790                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3791                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3792                                 break;
3793                         }
3794                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3795                         break;
3796                 case OP_FBLE:
3797                         /* Branch if C013=000 or 100 */
3798                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3799                                 guchar *br1;
3800
3801                                 /* skip branch if C1=1 */
3802                                 br1 = code;
3803                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3804                                 /* branch if C0=0 */
3805                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3806                                 amd64_patch (br1, code);
3807                                 break;
3808                         }
3809                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, (X86_FP_C0|X86_FP_C1));
3810                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
3811                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3812                         break;
3813                 case OP_FBLE_UN:
3814                         /* Branch if C013 != 001 */
3815                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3816                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3817                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3818                                 break;
3819                         }
3820                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3821                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3822                         break;
3823                 case CEE_CKFINITE: {
3824                         if (use_sse2) {
3825                                 /* Transfer value to the fp stack */
3826                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
3827                                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
3828                                 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
3829                         }
3830                         amd64_push_reg (code, AMD64_RAX);
3831                         amd64_fxam (code);
3832                         amd64_fnstsw (code);
3833                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
3834                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3835                         amd64_pop_reg (code, AMD64_RAX);
3836                         if (use_sse2) {
3837                                 amd64_fstp (code, 0);
3838                         }
3839                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3840                         if (use_sse2)
3841                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3842                         break;
3843                 }
3844                 case OP_TLS_GET: {
3845                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
3846                         break;
3847                 }
3848                 case OP_MEMORY_BARRIER: {
3849                         /* Not needed on amd64 */
3850                         break;
3851                 }
3852                 case OP_ATOMIC_ADD_I4:
3853                 case OP_ATOMIC_ADD_I8: {
3854                         int dreg = ins->dreg;
3855                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
3856
3857                         if (dreg == ins->inst_basereg)
3858                                 dreg = AMD64_R11;
3859
3860                         if (dreg != ins->sreg2)
3861                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
3862
3863                         x86_prefix (code, X86_LOCK_PREFIX);
3864                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3865
3866                         if (dreg != ins->dreg)
3867                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3868
3869                         break;
3870                 }
3871                 case OP_ATOMIC_ADD_NEW_I4:
3872                 case OP_ATOMIC_ADD_NEW_I8: {
3873                         int dreg = ins->dreg;
3874                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
3875
3876                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
3877                                 dreg = AMD64_R11;
3878
3879                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
3880                         amd64_prefix (code, X86_LOCK_PREFIX);
3881                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3882                         /* dreg contains the old value, add with sreg2 value */
3883                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
3884
3885                         if (ins->dreg != dreg)
3886                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3887
3888                         break;
3889                 }
3890                 case OP_ATOMIC_EXCHANGE_I4:
3891                 case OP_ATOMIC_EXCHANGE_I8: {
3892                         guchar *br[2];
3893                         int sreg2 = ins->sreg2;
3894                         int breg = ins->inst_basereg;
3895                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
3896
3897                         /*
3898                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
3899                          * an explanation of how this works.
3900                          */
3901
3902                         /* cmpxchg uses eax as comperand, need to make sure we can use it
3903                          * hack to overcome limits in x86 reg allocator
3904                          * (req: dreg == eax and sreg2 != eax and breg != eax)
3905                          */
3906                         if (ins->dreg != AMD64_RAX)
3907                                 amd64_push_reg (code, AMD64_RAX);
3908
3909                         /* We need the EAX reg for the cmpxchg */
3910                         if (ins->sreg2 == AMD64_RAX) {
3911                                 amd64_push_reg (code, AMD64_RDX);
3912                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
3913                                 sreg2 = AMD64_RDX;
3914                         }
3915
3916                         if (breg == AMD64_RAX) {
3917                                 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3918                                 breg = AMD64_R11;
3919                         }
3920
3921                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
3922
3923                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
3924                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
3925                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
3926                         amd64_patch (br [1], br [0]);
3927
3928                         if (ins->dreg != AMD64_RAX) {
3929                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
3930                                 amd64_pop_reg (code, AMD64_RAX);
3931                         }
3932
3933                         if (ins->sreg2 != sreg2)
3934                                 amd64_pop_reg (code, AMD64_RDX);
3935
3936                         break;
3937                 }
3938                 default:
3939                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3940                         g_assert_not_reached ();
3941                 }
3942
3943                 if ((code - cfg->native_code - offset) > max_len) {
3944                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3945                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3946                         g_assert_not_reached ();
3947                 }
3948
3949                 cpos += max_len;
3950
3951                 last_ins = ins;
3952                 last_offset = offset;
3953
3954                 ins = ins->next;
3955         }
3956
3957         cfg->code_len = code - cfg->native_code;
3958 }
3959
3960 void
3961 mono_arch_register_lowlevel_calls (void)
3962 {
3963 }
3964
3965 void
3966 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3967 {
3968         MonoJumpInfo *patch_info;
3969         gboolean compile_aot = !run_cctors;
3970
3971         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3972                 unsigned char *ip = patch_info->ip.i + code;
3973                 const unsigned char *target;
3974
3975                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3976
3977                 if (compile_aot) {
3978                         switch (patch_info->type) {
3979                         case MONO_PATCH_INFO_BB:
3980                         case MONO_PATCH_INFO_LABEL:
3981                                 break;
3982                         default:
3983                                 /* No need to patch these */
3984                                 continue;
3985                         }
3986                 }
3987
3988                 switch (patch_info->type) {
3989                 case MONO_PATCH_INFO_NONE:
3990                         continue;
3991                 case MONO_PATCH_INFO_METHOD_REL:
3992                 case MONO_PATCH_INFO_R8:
3993                 case MONO_PATCH_INFO_R4:
3994                         g_assert_not_reached ();
3995                         continue;
3996                 case MONO_PATCH_INFO_BB:
3997                         break;
3998                 default:
3999                         break;
4000                 }
4001
4002                 /*
4003                  * Debug code to help track down problems where the target of a near call is
4004                  * is not valid.
4005                  */
4006                 if (amd64_is_near_call (ip)) {
4007                         gint64 disp = (guint8*)target - (guint8*)ip;
4008
4009                         if (!amd64_is_imm32 (disp)) {
4010                                 printf ("TYPE: %d\n", patch_info->type);
4011                                 switch (patch_info->type) {
4012                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4013                                         printf ("V: %s\n", patch_info->data.name);
4014                                         break;
4015                                 case MONO_PATCH_INFO_METHOD_JUMP:
4016                                 case MONO_PATCH_INFO_METHOD:
4017                                         printf ("V: %s\n", patch_info->data.method->name);
4018                                         break;
4019                                 default:
4020                                         break;
4021                                 }
4022                         }
4023                 }
4024
4025                 amd64_patch (ip, (gpointer)target);
4026         }
4027 }
4028
4029 guint8 *
4030 mono_arch_emit_prolog (MonoCompile *cfg)
4031 {
4032         MonoMethod *method = cfg->method;
4033         MonoBasicBlock *bb;
4034         MonoMethodSignature *sig;
4035         MonoInst *inst;
4036         int alloc_size, pos, max_offset, i, quad;
4037         guint8 *code;
4038         CallInfo *cinfo;
4039         gint32 lmf_offset = cfg->arch.lmf_offset;
4040
4041         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
4042         code = cfg->native_code = g_malloc (cfg->code_size);
4043
4044         /* Amount of stack space allocated by register saving code */
4045         pos = 0;
4046
4047         /*
4048          * The prolog consists of the following parts:
4049          * FP present:
4050          * - push rbp, mov rbp, rsp
4051          * - save callee saved regs using pushes
4052          * - allocate frame
4053          * - save lmf if needed
4054          * FP not present:
4055          * - allocate frame
4056          * - save lmf if needed
4057          * - save callee saved regs using moves
4058          */
4059
4060         if (!cfg->arch.omit_fp) {
4061                 amd64_push_reg (code, AMD64_RBP);
4062                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4063         }
4064
4065         /* Save callee saved registers */
4066         if (!cfg->arch.omit_fp && !method->save_lmf) {
4067                 for (i = 0; i < AMD64_NREG; ++i)
4068                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4069                                 amd64_push_reg (code, i);
4070                                 pos += sizeof (gpointer);
4071                         }
4072         }
4073
4074         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4075
4076         alloc_size -= pos;
4077
4078         if (cfg->arch.omit_fp)
4079                 /*
4080                  * On enter, the stack is misaligned by the the pushing of the return
4081                  * address. It is either made aligned by the pushing of %rbp, or by
4082                  * this.
4083                  */
4084                 alloc_size += 8;
4085
4086         cfg->arch.stack_alloc_size = alloc_size;
4087
4088         /* Allocate stack frame */
4089         if (alloc_size) {
4090                 /* See mono_emit_stack_alloc */
4091 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4092                 guint32 remaining_size = alloc_size;
4093                 while (remaining_size >= 0x1000) {
4094                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4095                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4096                         remaining_size -= 0x1000;
4097                 }
4098                 if (remaining_size)
4099                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4100 #else
4101                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4102 #endif
4103         }
4104
4105         /* Stack alignment check */
4106 #if 0
4107         {
4108                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4109                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4110                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4111                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4112                 amd64_breakpoint (code);
4113         }
4114 #endif
4115
4116         /* Save LMF */
4117         if (method->save_lmf) {
4118                 /* Save ip */
4119                 amd64_lea_membase (code, AMD64_R11, AMD64_RIP, 0);
4120                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, 8);
4121                 /* Save fp */
4122                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), AMD64_RBP, 8);
4123                 /* Save sp */
4124                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4125                 /* Skip method (only needed for trampoline LMF frames) */
4126                 /* Save callee saved regs */
4127                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4128                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4129                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4130                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4131                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4132         }
4133
4134         /* Save callee saved registers */
4135         if (cfg->arch.omit_fp && !method->save_lmf) {
4136                 gint32 save_area_offset = 0;
4137
4138                 /* Save caller saved registers after sp is adjusted */
4139                 /* The registers are saved at the bottom of the frame */
4140                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4141                 for (i = 0; i < AMD64_NREG; ++i)
4142                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4143                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4144                                 save_area_offset += 8;
4145                         }
4146         }
4147
4148         /* compute max_offset in order to use short forward jumps */
4149         max_offset = 0;
4150         if (cfg->opt & MONO_OPT_BRANCH) {
4151                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4152                         MonoInst *ins = bb->code;
4153                         bb->max_offset = max_offset;
4154
4155                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4156                                 max_offset += 6;
4157                         /* max alignment for loops */
4158                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4159                                 max_offset += LOOP_ALIGNMENT;
4160
4161                         while (ins) {
4162                                 if (ins->opcode == OP_LABEL)
4163                                         ins->inst_c1 = max_offset;
4164
4165                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4166                                 ins = ins->next;
4167                         }
4168                 }
4169         }
4170
4171         sig = mono_method_signature (method);
4172         pos = 0;
4173
4174         cinfo = get_call_info (sig, FALSE);
4175
4176         if (sig->ret->type != MONO_TYPE_VOID) {
4177                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
4178                         /* Save volatile arguments to the stack */
4179                         amd64_mov_membase_reg (code, cfg->ret->inst_basereg, cfg->ret->inst_offset, cinfo->ret.reg, 8);
4180                 }
4181         }
4182
4183         /* Keep this in sync with emit_load_volatile_arguments */
4184         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4185                 ArgInfo *ainfo = cinfo->args + i;
4186                 gint32 stack_offset;
4187                 MonoType *arg_type;
4188                 inst = cfg->varinfo [i];
4189
4190                 if (sig->hasthis && (i == 0))
4191                         arg_type = &mono_defaults.object_class->byval_arg;
4192                 else
4193                         arg_type = sig->params [i - sig->hasthis];
4194
4195                 stack_offset = ainfo->offset + ARGS_OFFSET;
4196
4197                 /* Save volatile arguments to the stack */
4198                 if (inst->opcode != OP_REGVAR) {
4199                         switch (ainfo->storage) {
4200                         case ArgInIReg: {
4201                                 guint32 size = 8;
4202
4203                                 /* FIXME: I1 etc */
4204                                 /*
4205                                 if (stack_offset & 0x1)
4206                                         size = 1;
4207                                 else if (stack_offset & 0x2)
4208                                         size = 2;
4209                                 else if (stack_offset & 0x4)
4210                                         size = 4;
4211                                 else
4212                                         size = 8;
4213                                 */
4214                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, size);
4215                                 break;
4216                         }
4217                         case ArgInFloatSSEReg:
4218                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4219                                 break;
4220                         case ArgInDoubleSSEReg:
4221                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4222                                 break;
4223                         case ArgValuetypeInReg:
4224                                 for (quad = 0; quad < 2; quad ++) {
4225                                         switch (ainfo->pair_storage [quad]) {
4226                                         case ArgInIReg:
4227                                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4228                                                 break;
4229                                         case ArgInFloatSSEReg:
4230                                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4231                                                 break;
4232                                         case ArgInDoubleSSEReg:
4233                                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4234                                                 break;
4235                                         case ArgNone:
4236                                                 break;
4237                                         default:
4238                                                 g_assert_not_reached ();
4239                                         }
4240                                 }
4241                                 break;
4242                         default:
4243                                 break;
4244                         }
4245                 }
4246
4247                 if (inst->opcode == OP_REGVAR) {
4248                         /* Argument allocated to (non-volatile) register */
4249                         switch (ainfo->storage) {
4250                         case ArgInIReg:
4251                                 amd64_mov_reg_reg (code, inst->dreg, ainfo->reg, 8);
4252                                 break;
4253                         case ArgOnStack:
4254                                 amd64_mov_reg_membase (code, inst->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4255                                 break;
4256                         default:
4257                                 g_assert_not_reached ();
4258                         }
4259                 }
4260         }
4261
4262         /* Might need to attach the thread to the JIT */
4263         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4264                 guint64 domain = (guint64)cfg->domain;
4265
4266                 /*
4267                  * The call might clobber argument registers, but they are already
4268                  * saved to the stack/global regs.
4269                  */
4270                 if (lmf_addr_tls_offset != -1) {
4271                         guint8 *buf;
4272
4273                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4274                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4275                         buf = code;
4276                         x86_branch8 (code, X86_CC_NE, 0, 0);
4277                         if ((domain >> 32) == 0)
4278                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 4);
4279                         else
4280                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 8);
4281                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4282                         amd64_patch (buf, code);
4283                 } else {
4284                         g_assert (!cfg->compile_aot);
4285                         if ((domain >> 32) == 0)
4286                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 4);
4287                         else
4288                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 8);
4289                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4290                 }
4291         }
4292
4293         if (method->save_lmf) {
4294                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4295                         /*
4296                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4297                          * through the mono_lmf_addr TLS variable.
4298                          */
4299                         /* %rax = previous_lmf */
4300                         x86_prefix (code, X86_FS_PREFIX);
4301                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4302
4303                         /* Save previous_lmf */
4304                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4305                         /* Set new lmf */
4306                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4307                         x86_prefix (code, X86_FS_PREFIX);
4308                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4309                 } else {
4310                         if (lmf_addr_tls_offset != -1) {
4311                                 /* Load lmf quicky using the FS register */
4312                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4313                         }
4314                         else {
4315                                 /*
4316                                  * The call might clobber argument registers, but they are already
4317                                  * saved to the stack/global regs.
4318                                  */
4319                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4320                                                                   (gpointer)"mono_get_lmf_addr");
4321                         }
4322
4323                         /* Save lmf_addr */
4324                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4325                         /* Save previous_lmf */
4326                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4327                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4328                         /* Set new lmf */
4329                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4330                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4331                 }
4332         }
4333
4334
4335         g_free (cinfo);
4336
4337         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4338                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4339
4340         cfg->code_len = code - cfg->native_code;
4341
4342         g_assert (cfg->code_len < cfg->code_size);
4343
4344         return code;
4345 }
4346
4347 void
4348 mono_arch_emit_epilog (MonoCompile *cfg)
4349 {
4350         MonoMethod *method = cfg->method;
4351         int quad, pos, i;
4352         guint8 *code;
4353         int max_epilog_size = 16;
4354         CallInfo *cinfo;
4355         gint32 lmf_offset = cfg->arch.lmf_offset;
4356
4357         if (cfg->method->save_lmf)
4358                 max_epilog_size += 256;
4359
4360         if (mono_jit_trace_calls != NULL)
4361                 max_epilog_size += 50;
4362
4363         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4364                 max_epilog_size += 50;
4365
4366         max_epilog_size += (AMD64_NREG * 2);
4367
4368         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4369                 cfg->code_size *= 2;
4370                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4371                 mono_jit_stats.code_reallocs++;
4372         }
4373
4374         code = cfg->native_code + cfg->code_len;
4375
4376         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4377                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4378
4379         /* the code restoring the registers must be kept in sync with CEE_JMP */
4380         pos = 0;
4381
4382         if (method->save_lmf) {
4383                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4384                         /*
4385                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4386                          * through the mono_lmf_addr TLS variable.
4387                          */
4388                         /* reg = previous_lmf */
4389                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4390                         x86_prefix (code, X86_FS_PREFIX);
4391                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4392                 } else {
4393                         /* Restore previous lmf */
4394                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4395                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4396                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4397                 }
4398
4399                 /* Restore caller saved regs */
4400                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4401                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), 8);
4402                 }
4403                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4404                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4405                 }
4406                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4407                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4408                 }
4409                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4410                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4411                 }
4412                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4413                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4414                 }
4415                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4416                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4417                 }
4418         } else {
4419
4420                 if (cfg->arch.omit_fp) {
4421                         gint32 save_area_offset = 0;
4422
4423                         for (i = 0; i < AMD64_NREG; ++i)
4424                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4425                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4426                                         save_area_offset += 8;
4427                                 }
4428                 }
4429                 else {
4430                         for (i = 0; i < AMD64_NREG; ++i)
4431                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4432                                         pos -= sizeof (gpointer);
4433
4434                         if (pos) {
4435                                 if (pos == - sizeof (gpointer)) {
4436                                         /* Only one register, so avoid lea */
4437                                         for (i = AMD64_NREG - 1; i > 0; --i)
4438                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4439                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4440                                                 }
4441                                 }
4442                                 else {
4443                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4444
4445                                         /* Pop registers in reverse order */
4446                                         for (i = AMD64_NREG - 1; i > 0; --i)
4447                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4448                                                         amd64_pop_reg (code, i);
4449                                                 }
4450                                 }
4451                         }
4452                 }
4453         }
4454
4455         /* Load returned vtypes into registers if needed */
4456         cinfo = get_call_info (mono_method_signature (method), FALSE);
4457         if (cinfo->ret.storage == ArgValuetypeInReg) {
4458                 ArgInfo *ainfo = &cinfo->ret;
4459                 MonoInst *inst = cfg->ret;
4460
4461                 for (quad = 0; quad < 2; quad ++) {
4462                         switch (ainfo->pair_storage [quad]) {
4463                         case ArgInIReg:
4464                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
4465                                 break;
4466                         case ArgInFloatSSEReg:
4467                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4468                                 break;
4469                         case ArgInDoubleSSEReg:
4470                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4471                                 break;
4472                         case ArgNone:
4473                                 break;
4474                         default:
4475                                 g_assert_not_reached ();
4476                         }
4477                 }
4478         }
4479         g_free (cinfo);
4480
4481         if (cfg->arch.omit_fp) {
4482                 if (cfg->arch.stack_alloc_size)
4483                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4484         } else {
4485                 amd64_leave (code);
4486         }
4487         amd64_ret (code);
4488
4489         cfg->code_len = code - cfg->native_code;
4490
4491         g_assert (cfg->code_len < cfg->code_size);
4492
4493         if (cfg->arch.omit_fp) {
4494                 /*
4495                  * Encode the stack size into used_int_regs so the exception handler
4496                  * can access it.
4497                  */
4498                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
4499                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
4500         }
4501 }
4502
4503 void
4504 mono_arch_emit_exceptions (MonoCompile *cfg)
4505 {
4506         MonoJumpInfo *patch_info;
4507         int nthrows, i;
4508         guint8 *code;
4509         MonoClass *exc_classes [16];
4510         guint8 *exc_throw_start [16], *exc_throw_end [16];
4511         guint32 code_size = 0;
4512
4513         /* Compute needed space */
4514         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4515                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4516                         code_size += 40;
4517                 if (patch_info->type == MONO_PATCH_INFO_R8)
4518                         code_size += 8 + 15; /* sizeof (double) + alignment */
4519                 if (patch_info->type == MONO_PATCH_INFO_R4)
4520                         code_size += 4 + 15; /* sizeof (float) + alignment */
4521         }
4522
4523         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4524                 cfg->code_size *= 2;
4525                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4526                 mono_jit_stats.code_reallocs++;
4527         }
4528
4529         code = cfg->native_code + cfg->code_len;
4530
4531         /* add code to raise exceptions */
4532         nthrows = 0;
4533         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4534                 switch (patch_info->type) {
4535                 case MONO_PATCH_INFO_EXC: {
4536                         MonoClass *exc_class;
4537                         guint8 *buf, *buf2;
4538                         guint32 throw_ip;
4539
4540                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
4541
4542                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4543                         g_assert (exc_class);
4544                         throw_ip = patch_info->ip.i;
4545
4546                         //x86_breakpoint (code);
4547                         /* Find a throw sequence for the same exception class */
4548                         for (i = 0; i < nthrows; ++i)
4549                                 if (exc_classes [i] == exc_class)
4550                                         break;
4551                         if (i < nthrows) {
4552                                 amd64_mov_reg_imm (code, AMD64_RSI, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4553                                 x86_jump_code (code, exc_throw_start [i]);
4554                                 patch_info->type = MONO_PATCH_INFO_NONE;
4555                         }
4556                         else {
4557                                 buf = code;
4558                                 amd64_mov_reg_imm_size (code, AMD64_RSI, 0xf0f0f0f0, 4);
4559                                 buf2 = code;
4560
4561                                 if (nthrows < 16) {
4562                                         exc_classes [nthrows] = exc_class;
4563                                         exc_throw_start [nthrows] = code;
4564                                 }
4565
4566                                 amd64_mov_reg_imm (code, AMD64_RDI, exc_class->type_token);
4567                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4568                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4569                                 patch_info->ip.i = code - cfg->native_code;
4570
4571                                 code = emit_call_body (cfg, code, patch_info->type, patch_info->data.name);
4572
4573                                 amd64_mov_reg_imm (buf, AMD64_RSI, (code - cfg->native_code) - throw_ip);
4574                                 while (buf < buf2)
4575                                         x86_nop (buf);
4576
4577                                 if (nthrows < 16) {
4578                                         exc_throw_end [nthrows] = code;
4579                                         nthrows ++;
4580                                 }
4581                         }
4582                         break;
4583                 }
4584                 default:
4585                         /* do nothing */
4586                         break;
4587                 }
4588         }
4589
4590         /* Handle relocations with RIP relative addressing */
4591         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4592                 gboolean remove = FALSE;
4593
4594                 switch (patch_info->type) {
4595                 case MONO_PATCH_INFO_R8:
4596                 case MONO_PATCH_INFO_R4: {
4597                         guint8 *pos;
4598
4599                         if (use_sse2) {
4600                                 /* The SSE opcodes require a 16 byte alignment */
4601                                 code = (guint8*)ALIGN_TO (code, 16);
4602                         } else {
4603                                 code = (guint8*)ALIGN_TO (code, 8);
4604                         }
4605
4606                         pos = cfg->native_code + patch_info->ip.i;
4607
4608                         if (use_sse2)
4609                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4610                         else
4611                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4612
4613                         if (patch_info->type == MONO_PATCH_INFO_R8) {
4614                                 *(double*)code = *(double*)patch_info->data.target;
4615                                 code += sizeof (double);
4616                         } else {
4617                                 *(float*)code = *(float*)patch_info->data.target;
4618                                 code += sizeof (float);
4619                         }
4620
4621                         remove = TRUE;
4622                         break;
4623                 }
4624                 default:
4625                         break;
4626                 }
4627
4628                 if (remove) {
4629                         if (patch_info == cfg->patch_info)
4630                                 cfg->patch_info = patch_info->next;
4631                         else {
4632                                 MonoJumpInfo *tmp;
4633
4634                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
4635                                         ;
4636                                 tmp->next = patch_info->next;
4637                         }
4638                 }
4639         }
4640
4641         cfg->code_len = code - cfg->native_code;
4642
4643         g_assert (cfg->code_len < cfg->code_size);
4644
4645 }
4646
4647 void*
4648 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4649 {
4650         guchar *code = p;
4651         CallInfo *cinfo = NULL;
4652         MonoMethodSignature *sig;
4653         MonoInst *inst;
4654         int i, n, stack_area = 0;
4655
4656         /* Keep this in sync with mono_arch_get_argument_info */
4657
4658         if (enable_arguments) {
4659                 /* Allocate a new area on the stack and save arguments there */
4660                 sig = mono_method_signature (cfg->method);
4661
4662                 cinfo = get_call_info (sig, FALSE);
4663
4664                 n = sig->param_count + sig->hasthis;
4665
4666                 stack_area = ALIGN_TO (n * 8, 16);
4667
4668                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
4669
4670                 for (i = 0; i < n; ++i) {
4671                         inst = cfg->varinfo [i];
4672
4673                         if (inst->opcode == OP_REGVAR)
4674                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
4675                         else {
4676                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
4677                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
4678                         }
4679                 }
4680         }
4681
4682         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4683         amd64_set_reg_template (code, AMD64_RDI);
4684         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RSP, 8);
4685         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4686
4687         if (enable_arguments) {
4688                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
4689
4690                 g_free (cinfo);
4691         }
4692
4693         return code;
4694 }
4695
4696 enum {
4697         SAVE_NONE,
4698         SAVE_STRUCT,
4699         SAVE_EAX,
4700         SAVE_EAX_EDX,
4701         SAVE_XMM
4702 };
4703
4704 void*
4705 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4706 {
4707         guchar *code = p;
4708         int save_mode = SAVE_NONE;
4709         MonoMethod *method = cfg->method;
4710         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
4711
4712         switch (rtype) {
4713         case MONO_TYPE_VOID:
4714                 /* special case string .ctor icall */
4715                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4716                         save_mode = SAVE_EAX;
4717                 else
4718                         save_mode = SAVE_NONE;
4719                 break;
4720         case MONO_TYPE_I8:
4721         case MONO_TYPE_U8:
4722                 save_mode = SAVE_EAX;
4723                 break;
4724         case MONO_TYPE_R4:
4725         case MONO_TYPE_R8:
4726                 save_mode = SAVE_XMM;
4727                 break;
4728         case MONO_TYPE_GENERICINST:
4729                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
4730                         save_mode = SAVE_EAX;
4731                         break;
4732                 }
4733                 /* Fall through */
4734         case MONO_TYPE_VALUETYPE:
4735                 save_mode = SAVE_STRUCT;
4736                 break;
4737         default:
4738                 save_mode = SAVE_EAX;
4739                 break;
4740         }
4741
4742         /* Save the result and copy it into the proper argument register */
4743         switch (save_mode) {
4744         case SAVE_EAX:
4745                 amd64_push_reg (code, AMD64_RAX);
4746                 /* Align stack */
4747                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4748                 if (enable_arguments)
4749                         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RAX, 8);
4750                 break;
4751         case SAVE_STRUCT:
4752                 /* FIXME: */
4753                 if (enable_arguments)
4754                         amd64_mov_reg_imm (code, AMD64_RSI, 0);
4755                 break;
4756         case SAVE_XMM:
4757                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4758                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
4759                 /* Align stack */
4760                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4761                 /*
4762                  * The result is already in the proper argument register so no copying
4763                  * needed.
4764                  */
4765                 break;
4766         case SAVE_NONE:
4767                 break;
4768         default:
4769                 g_assert_not_reached ();
4770         }
4771
4772         /* Set %al since this is a varargs call */
4773         if (save_mode == SAVE_XMM)
4774                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
4775         else
4776                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
4777
4778         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
4779         amd64_set_reg_template (code, AMD64_RDI);
4780         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4781
4782         /* Restore result */
4783         switch (save_mode) {
4784         case SAVE_EAX:
4785                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4786                 amd64_pop_reg (code, AMD64_RAX);
4787                 break;
4788         case SAVE_STRUCT:
4789                 /* FIXME: */
4790                 break;
4791         case SAVE_XMM:
4792                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4793                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
4794                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4795                 break;
4796         case SAVE_NONE:
4797                 break;
4798         default:
4799                 g_assert_not_reached ();
4800         }
4801
4802         return code;
4803 }
4804
4805 void
4806 mono_arch_flush_icache (guint8 *code, gint size)
4807 {
4808         /* Not needed */
4809 }
4810
4811 void
4812 mono_arch_flush_register_windows (void)
4813 {
4814 }
4815
4816 gboolean
4817 mono_arch_is_inst_imm (gint64 imm)
4818 {
4819         return amd64_is_imm32 (imm);
4820 }
4821
4822 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
4823
4824 /*
4825  * Determine whenever the trap whose info is in SIGINFO is caused by
4826  * integer overflow.
4827  */
4828 gboolean
4829 mono_arch_is_int_overflow (void *sigctx, void *info)
4830 {
4831         MonoContext ctx;
4832         guint8* rip;
4833         int reg;
4834         gint64 value;
4835
4836         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
4837
4838         rip = (guint8*)ctx.rip;
4839
4840         if (IS_REX (rip [0])) {
4841                 reg = amd64_rex_b (rip [0]);
4842                 rip ++;
4843         }
4844         else
4845                 reg = 0;
4846
4847         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
4848                 /* idiv REG */
4849                 reg += x86_modrm_rm (rip [1]);
4850
4851                 switch (reg) {
4852                 case AMD64_RAX:
4853                         value = ctx.rax;
4854                         break;
4855                 case AMD64_RBX:
4856                         value = ctx.rbx;
4857                         break;
4858                 case AMD64_RCX:
4859                         value = ctx.rcx;
4860                         break;
4861                 case AMD64_RDX:
4862                         value = ctx.rdx;
4863                         break;
4864                 case AMD64_RBP:
4865                         value = ctx.rbp;
4866                         break;
4867                 case AMD64_RSP:
4868                         value = ctx.rsp;
4869                         break;
4870                 case AMD64_RSI:
4871                         value = ctx.rsi;
4872                         break;
4873                 case AMD64_RDI:
4874                         value = ctx.rdi;
4875                         break;
4876                 case AMD64_R12:
4877                         value = ctx.r12;
4878                         break;
4879                 case AMD64_R13:
4880                         value = ctx.r13;
4881                         break;
4882                 case AMD64_R14:
4883                         value = ctx.r14;
4884                         break;
4885                 case AMD64_R15:
4886                         value = ctx.r15;
4887                         break;
4888                 default:
4889                         g_assert_not_reached ();
4890                         reg = -1;
4891                 }
4892
4893                 if (value == -1)
4894                         return TRUE;
4895         }
4896
4897         return FALSE;
4898 }
4899
4900 guint32
4901 mono_arch_get_patch_offset (guint8 *code)
4902 {
4903         return 3;
4904 }
4905
4906 gpointer*
4907 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
4908 {
4909         guint32 reg;
4910         guint32 disp;
4911         guint8 rex = 0;
4912
4913         /* go to the start of the call instruction
4914          *
4915          * address_byte = (m << 6) | (o << 3) | reg
4916          * call opcode: 0xff address_byte displacement
4917          * 0xff m=1,o=2 imm8
4918          * 0xff m=2,o=2 imm32
4919          */
4920         code -= 7;
4921
4922         /*
4923          * A given byte sequence can match more than case here, so we have to be
4924          * really careful about the ordering of the cases. Longer sequences
4925          * come first.
4926          */
4927         if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4928                         /*
4929                          * This is a interface call
4930                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
4931                          * ff 10                  callq  *(%rax)
4932                          */
4933                 if (IS_REX (code [4]))
4934                         rex = code [4];
4935                 reg = amd64_modrm_rm (code [6]);
4936                 disp = 0;
4937         }
4938         else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
4939                 /* call OFFSET(%rip) */
4940                 disp = *(guint32*)(code + 3);
4941                 return (gpointer*)(code + disp + 7);
4942         }
4943         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
4944                 /* call *[reg+disp32] */
4945                 if (IS_REX (code [0]))
4946                         rex = code [0];
4947                 reg = amd64_modrm_rm (code [2]);
4948                 disp = *(guint32*)(code + 3);
4949                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4950         }
4951         else if (code [2] == 0xe8) {
4952                 /* call <ADDR> */
4953                 return NULL;
4954         }
4955         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
4956                 /* call *%reg */
4957                 return NULL;
4958         }
4959         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
4960                 /* call *[reg+disp8] */
4961                 if (IS_REX (code [3]))
4962                         rex = code [3];
4963                 reg = amd64_modrm_rm (code [5]);
4964                 disp = *(guint8*)(code + 6);
4965                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4966         }
4967         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4968                         /*
4969                          * This is a interface call: should check the above code can't catch it earlier
4970                          * 8b 40 30   mov    0x30(%eax),%eax
4971                          * ff 10      call   *(%eax)
4972                          */
4973                 if (IS_REX (code [4]))
4974                         rex = code [4];
4975                 reg = amd64_modrm_rm (code [6]);
4976                 disp = 0;
4977         }
4978         else
4979                 g_assert_not_reached ();
4980
4981         reg += amd64_rex_b (rex);
4982
4983         /* R11 is clobbered by the trampoline code */
4984         g_assert (reg != AMD64_R11);
4985
4986         return (gpointer)(((guint64)(regs [reg])) + disp);
4987 }
4988
4989 gpointer*
4990 mono_arch_get_delegate_method_ptr_addr (guint8* code, gpointer *regs)
4991 {
4992         guint32 reg;
4993         guint32 disp;
4994
4995         code -= 10;
4996
4997         if (IS_REX (code [0]) && (code [1] == 0x8b) && (code [3] == 0x48) && (code [4] == 0x8b) && (code [5] == 0x40) && (code [7] == 0x48) && (code [8] == 0xff) && (code [9] == 0xd0)) {
4998                 /* mov REG, %rax; mov <OFFSET>(%rax), %rax; call *%rax */
4999                 reg = amd64_rex_b (code [0]) + amd64_modrm_rm (code [2]);
5000                 disp = code [6];
5001
5002                 if (reg == AMD64_RAX)
5003                         return NULL;
5004                 else
5005                         return (gpointer*)(((guint64)(regs [reg])) + disp);
5006         }
5007
5008         return NULL;
5009 }
5010
5011 /*
5012  * Support for fast access to the thread-local lmf structure using the GS
5013  * segment register on NPTL + kernel 2.6.x.
5014  */
5015
5016 static gboolean tls_offset_inited = FALSE;
5017
5018 void
5019 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5020 {
5021         if (!tls_offset_inited) {
5022                 tls_offset_inited = TRUE;
5023 #ifdef MONO_XEN_OPT
5024                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5025 #endif
5026                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5027                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5028                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5029                 thread_tls_offset = mono_thread_get_tls_offset ();
5030         }
5031 }
5032
5033 void
5034 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5035 {
5036 }
5037
5038 void
5039 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
5040 {
5041         MonoCallInst *call = (MonoCallInst*)inst;
5042         CallInfo * cinfo = get_call_info (inst->signature, FALSE);
5043
5044         if (vt_reg != -1) {
5045                 MonoInst *vtarg;
5046
5047                 if (cinfo->ret.storage == ArgValuetypeInReg) {
5048                         /*
5049                          * The valuetype is in RAX:RDX after the call, need to be copied to
5050                          * the stack. Push the address here, so the call instruction can
5051                          * access it.
5052                          */
5053                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
5054                         vtarg->sreg1 = vt_reg;
5055                         mono_bblock_add_inst (cfg->cbb, vtarg);
5056
5057                         /* Align stack */
5058                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
5059                 }
5060                 else {
5061                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
5062                         vtarg->sreg1 = vt_reg;
5063                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
5064                         mono_bblock_add_inst (cfg->cbb, vtarg);
5065
5066                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
5067                 }
5068         }
5069
5070         /* add the this argument */
5071         if (this_reg != -1) {
5072                 MonoInst *this;
5073                 MONO_INST_NEW (cfg, this, OP_MOVE);
5074                 this->type = this_type;
5075                 this->sreg1 = this_reg;
5076                 this->dreg = mono_regstate_next_int (cfg->rs);
5077                 mono_bblock_add_inst (cfg->cbb, this);
5078
5079                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
5080         }
5081
5082         g_free (cinfo);
5083 }
5084
5085 MonoInst*
5086 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5087 {
5088         MonoInst *ins = NULL;
5089
5090         if (cmethod->klass == mono_defaults.math_class) {
5091                 if (strcmp (cmethod->name, "Sin") == 0) {
5092                         MONO_INST_NEW (cfg, ins, OP_SIN);
5093                         ins->inst_i0 = args [0];
5094                 } else if (strcmp (cmethod->name, "Cos") == 0) {
5095                         MONO_INST_NEW (cfg, ins, OP_COS);
5096                         ins->inst_i0 = args [0];
5097                 } else if (strcmp (cmethod->name, "Tan") == 0) {
5098                         if (use_sse2)
5099                                 return ins;
5100                         MONO_INST_NEW (cfg, ins, OP_TAN);
5101                         ins->inst_i0 = args [0];
5102                 } else if (strcmp (cmethod->name, "Atan") == 0) {
5103                         if (use_sse2)
5104                                 return ins;
5105                         MONO_INST_NEW (cfg, ins, OP_ATAN);
5106                         ins->inst_i0 = args [0];
5107                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5108                         MONO_INST_NEW (cfg, ins, OP_SQRT);
5109                         ins->inst_i0 = args [0];
5110                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5111                         MONO_INST_NEW (cfg, ins, OP_ABS);
5112                         ins->inst_i0 = args [0];
5113                 }
5114 #if 0
5115                 /* OP_FREM is not IEEE compatible */
5116                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5117                         MONO_INST_NEW (cfg, ins, OP_FREM);
5118                         ins->inst_i0 = args [0];
5119                         ins->inst_i1 = args [1];
5120                 }
5121 #endif
5122         } else if (cmethod->klass == mono_defaults.thread_class &&
5123                            strcmp (cmethod->name, "MemoryBarrier") == 0) {
5124                 MONO_INST_NEW (cfg, ins, OP_MEMORY_BARRIER);
5125         } else if(cmethod->klass->image == mono_defaults.corlib &&
5126                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
5127                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
5128
5129                 if (strcmp (cmethod->name, "Increment") == 0) {
5130                         MonoInst *ins_iconst;
5131                         guint32 opcode;
5132
5133                         if (fsig->params [0]->type == MONO_TYPE_I4)
5134                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5135                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5136                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5137                         else
5138                                 g_assert_not_reached ();
5139                         MONO_INST_NEW (cfg, ins, opcode);
5140                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5141                         ins_iconst->inst_c0 = 1;
5142
5143                         ins->inst_i0 = args [0];
5144                         ins->inst_i1 = ins_iconst;
5145                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
5146                         MonoInst *ins_iconst;
5147                         guint32 opcode;
5148
5149                         if (fsig->params [0]->type == MONO_TYPE_I4)
5150                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5151                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5152                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5153                         else
5154                                 g_assert_not_reached ();
5155                         MONO_INST_NEW (cfg, ins, opcode);
5156                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5157                         ins_iconst->inst_c0 = -1;
5158
5159                         ins->inst_i0 = args [0];
5160                         ins->inst_i1 = ins_iconst;
5161                 } else if (strcmp (cmethod->name, "Add") == 0) {
5162                         guint32 opcode;
5163
5164                         if (fsig->params [0]->type == MONO_TYPE_I4)
5165                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5166                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5167                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5168                         else
5169                                 g_assert_not_reached ();
5170
5171                         MONO_INST_NEW (cfg, ins, opcode);
5172
5173                         ins->inst_i0 = args [0];
5174                         ins->inst_i1 = args [1];
5175                 } else if (strcmp (cmethod->name, "Exchange") == 0) {
5176                         guint32 opcode;
5177
5178                         if (fsig->params [0]->type == MONO_TYPE_I4)
5179                                 opcode = OP_ATOMIC_EXCHANGE_I4;
5180                         else if ((fsig->params [0]->type == MONO_TYPE_I8) ||
5181                                          (fsig->params [0]->type == MONO_TYPE_I) ||
5182                                          (fsig->params [0]->type == MONO_TYPE_OBJECT))
5183                                 opcode = OP_ATOMIC_EXCHANGE_I8;
5184                         else
5185                                 return NULL;
5186
5187                         MONO_INST_NEW (cfg, ins, opcode);
5188
5189                         ins->inst_i0 = args [0];
5190                         ins->inst_i1 = args [1];
5191                 } else if (strcmp (cmethod->name, "Read") == 0 && (fsig->params [0]->type == MONO_TYPE_I8)) {
5192                         /* 64 bit reads are already atomic */
5193                         MONO_INST_NEW (cfg, ins, CEE_LDIND_I8);
5194                         ins->inst_i0 = args [0];
5195                 }
5196
5197                 /*
5198                  * Can't implement CompareExchange methods this way since they have
5199                  * three arguments.
5200                  */
5201         }
5202
5203         return ins;
5204 }
5205
5206 gboolean
5207 mono_arch_print_tree (MonoInst *tree, int arity)
5208 {
5209         return 0;
5210 }
5211
5212 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5213 {
5214         MonoInst* ins;
5215
5216         if (appdomain_tls_offset == -1)
5217                 return NULL;
5218
5219         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5220         ins->inst_offset = appdomain_tls_offset;
5221         return ins;
5222 }
5223
5224 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5225 {
5226         MonoInst* ins;
5227
5228         if (thread_tls_offset == -1)
5229                 return NULL;
5230
5231         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5232         ins->inst_offset = thread_tls_offset;
5233         return ins;
5234 }