mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "ir-emit.h"
  30 #include "mini-amd64.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * xmmregs [] = {
 121         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 122         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 123 };
 124
 125 const char*
 126 mono_arch_fregname (int reg)
 127 {
 128         if (reg < AMD64_XMM_NREG)
 129                 return xmmregs [reg];
 130         else
 131                 return "unknown";
 132 }
 133
 134 G_GNUC_UNUSED static void
 135 break_count (void)
 136 {
 137 }
 138
 139 G_GNUC_UNUSED static gboolean
 140 debug_count (void)
 141 {
 142         static int count = 0;
 143         count ++;
 144
 145         if (!getenv ("COUNT"))
 146                 return TRUE;
 147
 148         if (count == atoi (getenv ("COUNT"))) {
 149                 break_count ();
 150         }
 151
 152         if (count > atoi (getenv ("COUNT"))) {
 153                 return FALSE;
 154         }
 155
 156         return TRUE;
 157 }
 158
 159 static gboolean
 160 debug_omit_fp (void)
 161 {
 162 #if 0
 163         return debug_count ();
 164 #else
 165         return TRUE;
 166 #endif
 167 }
 168
 169 static inline gboolean
 170 amd64_is_near_call (guint8 *code)
 171 {
 172         /* Skip REX */
 173         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 174                 code += 1;
 175
 176         return code [0] == 0xe8;
 177 }
 178
 179 static inline void
 180 amd64_patch (unsigned char* code, gpointer target)
 181 {
 182         guint8 rex = 0;
 183
 184         /* Skip REX */
 185         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 186                 rex = code [0];
 187                 code += 1;
 188         }
 189
 190         if ((code [0] & 0xf8) == 0xb8) {
 191                 /* amd64_set_reg_template */
 192                 *(guint64*)(code + 1) = (guint64)target;
 193         }
 194         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 195                 /* mov 0(%rip), %dreg */
 196                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 197         }
 198         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 199                 /* call *<OFFSET>(%rip) */
 200                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 201         }
 202         else if ((code [0] == 0xe8)) {
 203                 /* call <DISP> */
 204                 gint64 disp = (guint8*)target - (guint8*)code;
 205                 g_assert (amd64_is_imm32 (disp));
 206                 x86_patch (code, (unsigned char*)target);
 207         }
 208         else
 209                 x86_patch (code, (unsigned char*)target);
 210 }
 211
 212 void
 213 mono_amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         amd64_patch (code, target);
 216 }
 217
 218 typedef enum {
 219         ArgInIReg,
 220         ArgInFloatSSEReg,
 221         ArgInDoubleSSEReg,
 222         ArgOnStack,
 223         ArgValuetypeInReg,
 224         ArgValuetypeAddrInIReg,
 225         ArgNone /* only in pair_storage */
 226 } ArgStorage;
 227
 228 typedef struct {
 229         gint16 offset;
 230         gint8  reg;
 231         ArgStorage storage;
 232
 233         /* Only if storage == ArgValuetypeInReg */
 234         ArgStorage pair_storage [2];
 235         gint8 pair_regs [2];
 236 } ArgInfo;
 237
 238 typedef struct {
 239         int nargs;
 240         guint32 stack_usage;
 241         guint32 reg_usage;
 242         guint32 freg_usage;
 243         gboolean need_stack_align;
 244         ArgInfo ret;
 245         ArgInfo sig_cookie;
 246         ArgInfo args [1];
 247 } CallInfo;
 248
 249 #define DEBUG(a) if (cfg->verbose_level > 1) a
 250
 251 #ifdef PLATFORM_WIN32
 252 #define PARAM_REGS 4
 253
 254 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 255
 256 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 257 #else
 258 #define PARAM_REGS 6
 259
 260 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 261
 262  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 263 #endif
 264
 265 static void inline
 266 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 267 {
 268     ainfo->offset = *stack_size;
 269
 270     if (*gr >= PARAM_REGS) {
 271                 ainfo->storage = ArgOnStack;
 272                 (*stack_size) += sizeof (gpointer);
 273     }
 274     else {
 275                 ainfo->storage = ArgInIReg;
 276                 ainfo->reg = param_regs [*gr];
 277                 (*gr) ++;
 278     }
 279 }
 280
 281 #ifdef PLATFORM_WIN32
 282 #define FLOAT_PARAM_REGS 4
 283 #else
 284 #define FLOAT_PARAM_REGS 8
 285 #endif
 286
 287 static void inline
 288 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 289 {
 290     ainfo->offset = *stack_size;
 291
 292     if (*gr >= FLOAT_PARAM_REGS) {
 293                 ainfo->storage = ArgOnStack;
 294                 (*stack_size) += sizeof (gpointer);
 295     }
 296     else {
 297                 /* A double register */
 298                 if (is_double)
 299                         ainfo->storage = ArgInDoubleSSEReg;
 300                 else
 301                         ainfo->storage = ArgInFloatSSEReg;
 302                 ainfo->reg = *gr;
 303                 (*gr) += 1;
 304     }
 305 }
 306
 307 typedef enum ArgumentClass {
 308         ARG_CLASS_NO_CLASS,
 309         ARG_CLASS_MEMORY,
 310         ARG_CLASS_INTEGER,
 311         ARG_CLASS_SSE
 312 } ArgumentClass;
 313
 314 static ArgumentClass
 315 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 316 {
 317         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 318         MonoType *ptype;
 319
 320         ptype = mini_type_get_underlying_type (NULL, type);
 321         switch (ptype->type) {
 322         case MONO_TYPE_BOOLEAN:
 323         case MONO_TYPE_CHAR:
 324         case MONO_TYPE_I1:
 325         case MONO_TYPE_U1:
 326         case MONO_TYPE_I2:
 327         case MONO_TYPE_U2:
 328         case MONO_TYPE_I4:
 329         case MONO_TYPE_U4:
 330         case MONO_TYPE_I:
 331         case MONO_TYPE_U:
 332         case MONO_TYPE_STRING:
 333         case MONO_TYPE_OBJECT:
 334         case MONO_TYPE_CLASS:
 335         case MONO_TYPE_SZARRAY:
 336         case MONO_TYPE_PTR:
 337         case MONO_TYPE_FNPTR:
 338         case MONO_TYPE_ARRAY:
 339         case MONO_TYPE_I8:
 340         case MONO_TYPE_U8:
 341                 class2 = ARG_CLASS_INTEGER;
 342                 break;
 343         case MONO_TYPE_R4:
 344         case MONO_TYPE_R8:
 345 #ifdef PLATFORM_WIN32
 346                 class2 = ARG_CLASS_INTEGER;
 347 #else
 348                 class2 = ARG_CLASS_SSE;
 349 #endif
 350                 break;
 351
 352         case MONO_TYPE_TYPEDBYREF:
 353                 g_assert_not_reached ();
 354
 355         case MONO_TYPE_GENERICINST:
 356                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 357                         class2 = ARG_CLASS_INTEGER;
 358                         break;
 359                 }
 360                 /* fall through */
 361         case MONO_TYPE_VALUETYPE: {
 362                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 363                 int i;
 364
 365                 for (i = 0; i < info->num_fields; ++i) {
 366                         class2 = class1;
 367                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 368                 }
 369                 break;
 370         }
 371         default:
 372                 g_assert_not_reached ();
 373         }
 374
 375         /* Merge */
 376         if (class1 == class2)
 377                 ;
 378         else if (class1 == ARG_CLASS_NO_CLASS)
 379                 class1 = class2;
 380         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 381                 class1 = ARG_CLASS_MEMORY;
 382         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 383                 class1 = ARG_CLASS_INTEGER;
 384         else
 385                 class1 = ARG_CLASS_SSE;
 386
 387         return class1;
 388 }
 389
 390 static void
 391 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 392                gboolean is_return,
 393                guint32 *gr, guint32 *fr, guint32 *stack_size)
 394 {
 395         guint32 size, quad, nquads, i;
 396         ArgumentClass args [2];
 397         MonoMarshalType *info = NULL;
 398         MonoClass *klass;
 399         MonoGenericSharingContext tmp_gsctx;
 400
 401         /*
 402          * The gsctx currently contains no data, it is only used for checking whenever
 403          * open types are allowed, some callers like mono_arch_get_argument_info ()
 404          * don't pass it to us, so work around that.
 405          */
 406         if (!gsctx)
 407                 gsctx = &tmp_gsctx;
 408
 409         klass = mono_class_from_mono_type (type);
 410         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 411 #ifndef PLATFORM_WIN32
 412         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 413                 /* We pass and return vtypes of size 8 in a register */
 414         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 415 #else
 416         if (!sig->pinvoke) {
 417 #endif
 418                 /* Allways pass in memory */
 419                 ainfo->offset = *stack_size;
 420                 *stack_size += ALIGN_TO (size, 8);
 421                 ainfo->storage = ArgOnStack;
 422
 423                 return;
 424         }
 425
 426         /* FIXME: Handle structs smaller than 8 bytes */
 427         //if ((size % 8) != 0)
 428         //      NOT_IMPLEMENTED;
 429
 430         if (size > 8)
 431                 nquads = 2;
 432         else
 433                 nquads = 1;
 434
 435         if (!sig->pinvoke) {
 436                 /* Always pass in 1 or 2 integer registers */
 437                 args [0] = ARG_CLASS_INTEGER;
 438                 args [1] = ARG_CLASS_INTEGER;
 439                 /* Only the simplest cases are supported */
 440                 if (is_return && nquads != 1) {
 441                         args [0] = ARG_CLASS_MEMORY;
 442                         args [1] = ARG_CLASS_MEMORY;
 443                 }
 444         } else {
 445                 /*
 446                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 447                  * The X87 and SSEUP stuff is left out since there are no such types in
 448                  * the CLR.
 449                  */
 450                 info = mono_marshal_load_type_info (klass);
 451                 g_assert (info);
 452
 453 #ifndef PLATFORM_WIN32
 454                 if (info->native_size > 16) {
 455                         ainfo->offset = *stack_size;
 456                         *stack_size += ALIGN_TO (info->native_size, 8);
 457                         ainfo->storage = ArgOnStack;
 458
 459                         return;
 460                 }
 461 #else
 462                 switch (info->native_size) {
 463                 case 1: case 2: case 4: case 8:
 464                         break;
 465                 default:
 466                         if (is_return) {
 467                                 ainfo->storage = ArgOnStack;
 468                                 ainfo->offset = *stack_size;
 469                                 *stack_size += ALIGN_TO (info->native_size, 8);
 470                         }
 471                         else {
 472                                 ainfo->storage = ArgValuetypeAddrInIReg;
 473
 474                                 if (*gr < PARAM_REGS) {
 475                                         ainfo->pair_storage [0] = ArgInIReg;
 476                                         ainfo->pair_regs [0] = param_regs [*gr];
 477                                         (*gr) ++;
 478                                 }
 479                                 else {
 480                                         ainfo->pair_storage [0] = ArgOnStack;
 481                                         ainfo->offset = *stack_size;
 482                                         *stack_size += 8;
 483                                 }
 484                         }
 485
 486                         return;
 487                 }
 488 #endif
 489
 490                 args [0] = ARG_CLASS_NO_CLASS;
 491                 args [1] = ARG_CLASS_NO_CLASS;
 492                 for (quad = 0; quad < nquads; ++quad) {
 493                         int size;
 494                         guint32 align;
 495                         ArgumentClass class1;
 496
 497                         if (info->num_fields == 0)
 498                                 class1 = ARG_CLASS_MEMORY;
 499                         else
 500                                 class1 = ARG_CLASS_NO_CLASS;
 501                         for (i = 0; i < info->num_fields; ++i) {
 502                                 size = mono_marshal_type_size (info->fields [i].field->type,
 503                                                                                            info->fields [i].mspec,
 504                                                                                            &align, TRUE, klass->unicode);
 505                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 506                                         /* Unaligned field */
 507                                         NOT_IMPLEMENTED;
 508                                 }
 509
 510                                 /* Skip fields in other quad */
 511                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 512                                         continue;
 513                                 if ((quad == 1) && (info->fields [i].offset < 8))
 514                                         continue;
 515
 516                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 517                         }
 518                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 519                         args [quad] = class1;
 520                 }
 521         }
 522
 523         /* Post merger cleanup */
 524         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 525                 args [0] = args [1] = ARG_CLASS_MEMORY;
 526
 527         /* Allocate registers */
 528         {
 529                 int orig_gr = *gr;
 530                 int orig_fr = *fr;
 531
 532                 ainfo->storage = ArgValuetypeInReg;
 533                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 534                 for (quad = 0; quad < nquads; ++quad) {
 535                         switch (args [quad]) {
 536                         case ARG_CLASS_INTEGER:
 537                                 if (*gr >= PARAM_REGS)
 538                                         args [quad] = ARG_CLASS_MEMORY;
 539                                 else {
 540                                         ainfo->pair_storage [quad] = ArgInIReg;
 541                                         if (is_return)
 542                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 543                                         else
 544                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 545                                         (*gr) ++;
 546                                 }
 547                                 break;
 548                         case ARG_CLASS_SSE:
 549                                 if (*fr >= FLOAT_PARAM_REGS)
 550                                         args [quad] = ARG_CLASS_MEMORY;
 551                                 else {
 552                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 553                                         ainfo->pair_regs [quad] = *fr;
 554                                         (*fr) ++;
 555                                 }
 556                                 break;
 557                         case ARG_CLASS_MEMORY:
 558                                 break;
 559                         default:
 560                                 g_assert_not_reached ();
 561                         }
 562                 }
 563
 564                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 565                         /* Revert possible register assignments */
 566                         *gr = orig_gr;
 567                         *fr = orig_fr;
 568
 569                         ainfo->offset = *stack_size;
 570                         if (sig->pinvoke)
 571                                 *stack_size += ALIGN_TO (info->native_size, 8);
 572                         else
 573                                 *stack_size += nquads * sizeof (gpointer);
 574                         ainfo->storage = ArgOnStack;
 575                 }
 576         }
 577 }
 578
 579 /*
 580  * get_call_info:
 581  *
 582  *  Obtain information about a call according to the calling convention.
 583  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 584  * Draft Version 0.23" document for more information.
 585  */
 586 static CallInfo*
 587 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 588 {
 589         guint32 i, gr, fr;
 590         MonoType *ret_type;
 591         int n = sig->hasthis + sig->param_count;
 592         guint32 stack_size = 0;
 593         CallInfo *cinfo;
 594
 595         if (mp)
 596                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 597         else
 598                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 599
 600         gr = 0;
 601         fr = 0;
 602
 603         /* return value */
 604         {
 605                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 606                 switch (ret_type->type) {
 607                 case MONO_TYPE_BOOLEAN:
 608                 case MONO_TYPE_I1:
 609                 case MONO_TYPE_U1:
 610                 case MONO_TYPE_I2:
 611                 case MONO_TYPE_U2:
 612                 case MONO_TYPE_CHAR:
 613                 case MONO_TYPE_I4:
 614                 case MONO_TYPE_U4:
 615                 case MONO_TYPE_I:
 616                 case MONO_TYPE_U:
 617                 case MONO_TYPE_PTR:
 618                 case MONO_TYPE_FNPTR:
 619                 case MONO_TYPE_CLASS:
 620                 case MONO_TYPE_OBJECT:
 621                 case MONO_TYPE_SZARRAY:
 622                 case MONO_TYPE_ARRAY:
 623                 case MONO_TYPE_STRING:
 624                         cinfo->ret.storage = ArgInIReg;
 625                         cinfo->ret.reg = AMD64_RAX;
 626                         break;
 627                 case MONO_TYPE_U8:
 628                 case MONO_TYPE_I8:
 629                         cinfo->ret.storage = ArgInIReg;
 630                         cinfo->ret.reg = AMD64_RAX;
 631                         break;
 632                 case MONO_TYPE_R4:
 633                         cinfo->ret.storage = ArgInFloatSSEReg;
 634                         cinfo->ret.reg = AMD64_XMM0;
 635                         break;
 636                 case MONO_TYPE_R8:
 637                         cinfo->ret.storage = ArgInDoubleSSEReg;
 638                         cinfo->ret.reg = AMD64_XMM0;
 639                         break;
 640                 case MONO_TYPE_GENERICINST:
 641                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 642                                 cinfo->ret.storage = ArgInIReg;
 643                                 cinfo->ret.reg = AMD64_RAX;
 644                                 break;
 645                         }
 646                         /* fall through */
 647                 case MONO_TYPE_VALUETYPE: {
 648                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 649
 650                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 651                         if (cinfo->ret.storage == ArgOnStack)
 652                                 /* The caller passes the address where the value is stored */
 653                                 add_general (&gr, &stack_size, &cinfo->ret);
 654                         break;
 655                 }
 656                 case MONO_TYPE_TYPEDBYREF:
 657                         /* Same as a valuetype with size 24 */
 658                         add_general (&gr, &stack_size, &cinfo->ret);
 659                         ;
 660                         break;
 661                 case MONO_TYPE_VOID:
 662                         break;
 663                 default:
 664                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 665                 }
 666         }
 667
 668         /* this */
 669         if (sig->hasthis)
 670                 add_general (&gr, &stack_size, cinfo->args + 0);
 671
 672         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 673                 gr = PARAM_REGS;
 674                 fr = FLOAT_PARAM_REGS;
 675
 676                 /* Emit the signature cookie just before the implicit arguments */
 677                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 678         }
 679
 680         for (i = 0; i < sig->param_count; ++i) {
 681                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 682                 MonoType *ptype;
 683
 684 #ifdef PLATFORM_WIN32
 685                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 686                 if (gr > fr)
 687                         fr = gr;
 688                 else if (fr > gr)
 689                         gr = fr;
 690 #endif
 691
 692                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 693                         /* We allways pass the sig cookie on the stack for simplicity */
 694                         /*
 695                          * Prevent implicit arguments + the sig cookie from being passed
 696                          * in registers.
 697                          */
 698                         gr = PARAM_REGS;
 699                         fr = FLOAT_PARAM_REGS;
 700
 701                         /* Emit the signature cookie just before the implicit arguments */
 702                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 703                 }
 704
 705                 if (sig->params [i]->byref) {
 706                         add_general (&gr, &stack_size, ainfo);
 707                         continue;
 708                 }
 709                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 710                 switch (ptype->type) {
 711                 case MONO_TYPE_BOOLEAN:
 712                 case MONO_TYPE_I1:
 713                 case MONO_TYPE_U1:
 714                         add_general (&gr, &stack_size, ainfo);
 715                         break;
 716                 case MONO_TYPE_I2:
 717                 case MONO_TYPE_U2:
 718                 case MONO_TYPE_CHAR:
 719                         add_general (&gr, &stack_size, ainfo);
 720                         break;
 721                 case MONO_TYPE_I4:
 722                 case MONO_TYPE_U4:
 723                         add_general (&gr, &stack_size, ainfo);
 724                         break;
 725                 case MONO_TYPE_I:
 726                 case MONO_TYPE_U:
 727                 case MONO_TYPE_PTR:
 728                 case MONO_TYPE_FNPTR:
 729                 case MONO_TYPE_CLASS:
 730                 case MONO_TYPE_OBJECT:
 731                 case MONO_TYPE_STRING:
 732                 case MONO_TYPE_SZARRAY:
 733                 case MONO_TYPE_ARRAY:
 734                         add_general (&gr, &stack_size, ainfo);
 735                         break;
 736                 case MONO_TYPE_GENERICINST:
 737                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 738                                 add_general (&gr, &stack_size, ainfo);
 739                                 break;
 740                         }
 741                         /* fall through */
 742                 case MONO_TYPE_VALUETYPE:
 743                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 744                         break;
 745                 case MONO_TYPE_TYPEDBYREF:
 746 #ifdef PLATFORM_WIN32
 747                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 748 #else
 749                         stack_size += sizeof (MonoTypedRef);
 750                         ainfo->storage = ArgOnStack;
 751 #endif
 752                         break;
 753                 case MONO_TYPE_U8:
 754                 case MONO_TYPE_I8:
 755                         add_general (&gr, &stack_size, ainfo);
 756                         break;
 757                 case MONO_TYPE_R4:
 758                         add_float (&fr, &stack_size, ainfo, FALSE);
 759                         break;
 760                 case MONO_TYPE_R8:
 761                         add_float (&fr, &stack_size, ainfo, TRUE);
 762                         break;
 763                 default:
 764                         g_assert_not_reached ();
 765                 }
 766         }
 767
 768         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 769                 gr = PARAM_REGS;
 770                 fr = FLOAT_PARAM_REGS;
 771
 772                 /* Emit the signature cookie just before the implicit arguments */
 773                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 774         }
 775
 776 #ifdef PLATFORM_WIN32
 777         // There always is 32 bytes reserved on the stack when calling on Winx64
 778         stack_size += 0x20;
 779 #endif
 780
 781         if (stack_size & 0x8) {
 782                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 783                 cinfo->need_stack_align = TRUE;
 784                 stack_size += 8;
 785         }
 786
 787         cinfo->stack_usage = stack_size;
 788         cinfo->reg_usage = gr;
 789         cinfo->freg_usage = fr;
 790         return cinfo;
 791 }
 792
 793 /*
 794  * mono_arch_get_argument_info:
 795  * @csig:  a method signature
 796  * @param_count: the number of parameters to consider
 797  * @arg_info: an array to store the result infos
 798  *
 799  * Gathers information on parameters such as size, alignment and
 800  * padding. arg_info should be large enought to hold param_count + 1 entries.
 801  *
 802  * Returns the size of the argument area on the stack.
 803  */
 804 int
 805 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 806 {
 807         int k;
 808         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 809         guint32 args_size = cinfo->stack_usage;
 810
 811         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 812         if (csig->hasthis) {
 813                 arg_info [0].offset = 0;
 814         }
 815
 816         for (k = 0; k < param_count; k++) {
 817                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 818                 /* FIXME: */
 819                 arg_info [k + 1].size = 0;
 820         }
 821
 822         g_free (cinfo);
 823
 824         return args_size;
 825 }
 826
 827 static int
 828 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 829 {
 830 #ifndef _MSC_VER
 831         __asm__ __volatile__ ("cpuid"
 832                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 833                 : "a" (id));
 834 #else
 835         int info[4];
 836         __cpuid(info, id);
 837         *p_eax = info[0];
 838         *p_ebx = info[1];
 839         *p_ecx = info[2];
 840         *p_edx = info[3];
 841 #endif
 842         return 1;
 843 }
 844
 845 /*
 846  * Initialize the cpu to execute managed code.
 847  */
 848 void
 849 mono_arch_cpu_init (void)
 850 {
 851 #ifndef _MSC_VER
 852         guint16 fpcw;
 853
 854         /* spec compliance requires running with double precision */
 855         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 856         fpcw &= ~X86_FPCW_PRECC_MASK;
 857         fpcw |= X86_FPCW_PREC_DOUBLE;
 858         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 859         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 860 #else
 861         /* TODO: This is crashing on Win64 right now.
 862         * _control87 (_PC_53, MCW_PC);
 863         */
 864 #endif
 865 }
 866
 867 /*
 868  * Initialize architecture specific code.
 869  */
 870 void
 871 mono_arch_init (void)
 872 {
 873         InitializeCriticalSection (&mini_arch_mutex);
 874 }
 875
 876 /*
 877  * Cleanup architecture specific code.
 878  */
 879 void
 880 mono_arch_cleanup (void)
 881 {
 882         DeleteCriticalSection (&mini_arch_mutex);
 883 }
 884
 885 /*
 886  * This function returns the optimizations supported on this cpu.
 887  */
 888 guint32
 889 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 890 {
 891         int eax, ebx, ecx, edx;
 892         guint32 opts = 0;
 893
 894         /* FIXME: AMD64 */
 895
 896         *exclude_mask = 0;
 897         /* Feature Flags function, flags returned in EDX. */
 898         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 899                 if (edx & (1 << 15)) {
 900                         opts |= MONO_OPT_CMOV;
 901                         if (edx & 1)
 902                                 opts |= MONO_OPT_FCMOV;
 903                         else
 904                                 *exclude_mask |= MONO_OPT_FCMOV;
 905                 } else
 906                         *exclude_mask |= MONO_OPT_CMOV;
 907         }
 908
 909         return opts;
 910 }
 911
 912 GList *
 913 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 914 {
 915         GList *vars = NULL;
 916         int i;
 917
 918         for (i = 0; i < cfg->num_varinfo; i++) {
 919                 MonoInst *ins = cfg->varinfo [i];
 920                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 921
 922                 /* unused vars */
 923                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 924                         continue;
 925
 926                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 927                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 928                         continue;
 929
 930                 if (mono_is_regsize_var (ins->inst_vtype)) {
 931                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 932                         g_assert (i == vmv->idx);
 933                         vars = g_list_prepend (vars, vmv);
 934                 }
 935         }
 936
 937         vars = mono_varlist_sort (cfg, vars, 0);
 938
 939         return vars;
 940 }
 941
 942 /**
 943  * mono_arch_compute_omit_fp:
 944  *
 945  *   Determine whenever the frame pointer can be eliminated.
 946  */
 947 static void
 948 mono_arch_compute_omit_fp (MonoCompile *cfg)
 949 {
 950         MonoMethodSignature *sig;
 951         MonoMethodHeader *header;
 952         int i, locals_size;
 953         CallInfo *cinfo;
 954
 955         if (cfg->arch.omit_fp_computed)
 956                 return;
 957
 958         header = mono_method_get_header (cfg->method);
 959
 960         sig = mono_method_signature (cfg->method);
 961
 962         if (!cfg->arch.cinfo)
 963                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 964         cinfo = cfg->arch.cinfo;
 965
 966         /*
 967          * FIXME: Remove some of the restrictions.
 968          */
 969         cfg->arch.omit_fp = TRUE;
 970         cfg->arch.omit_fp_computed = TRUE;
 971
 972         if (cfg->disable_omit_fp)
 973                 cfg->arch.omit_fp = FALSE;
 974
 975         if (!debug_omit_fp ())
 976                 cfg->arch.omit_fp = FALSE;
 977         /*
 978         if (cfg->method->save_lmf)
 979                 cfg->arch.omit_fp = FALSE;
 980         */
 981         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 982                 cfg->arch.omit_fp = FALSE;
 983         if (header->num_clauses)
 984                 cfg->arch.omit_fp = FALSE;
 985         if (cfg->param_area)
 986                 cfg->arch.omit_fp = FALSE;
 987         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 988                 cfg->arch.omit_fp = FALSE;
 989         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 990                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 991                 cfg->arch.omit_fp = FALSE;
 992         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 993                 ArgInfo *ainfo = &cinfo->args [i];
 994
 995                 if (ainfo->storage == ArgOnStack) {
 996                         /*
 997                          * The stack offset can only be determined when the frame
 998                          * size is known.
 999                          */
1000                         cfg->arch.omit_fp = FALSE;
1001                 }
1002         }
1003
1004         locals_size = 0;
1005         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1006                 MonoInst *ins = cfg->varinfo [i];
1007                 int ialign;
1008
1009                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1010         }
1011
1012         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1013                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1014                 cfg->arch.omit_fp = FALSE;
1015         }
1016 }
1017
1018 GList *
1019 mono_arch_get_global_int_regs (MonoCompile *cfg)
1020 {
1021         GList *regs = NULL;
1022
1023         mono_arch_compute_omit_fp (cfg);
1024
1025         if (cfg->globalra) {
1026                 if (cfg->arch.omit_fp)
1027                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1028
1029                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1030                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1031                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1032                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1033                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1034
1035                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1036                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1037                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1041                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1042                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1043         } else {
1044                 if (cfg->arch.omit_fp)
1045                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1046
1047                 /* We use the callee saved registers for global allocation */
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1051                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1052                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1053 #ifdef PLATFORM_WIN32
1054                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1055                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1056 #endif
1057         }
1058
1059         return regs;
1060 }
1061
1062 GList*
1063 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1064 {
1065         GList *regs = NULL;
1066         int i;
1067
1068         /* All XMM registers */
1069         for (i = 0; i < 16; ++i)
1070                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1071
1072         return regs;
1073 }
1074
1075 GList*
1076 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1077 {
1078         static GList *r = NULL;
1079
1080         if (r == NULL) {
1081                 GList *regs = NULL;
1082
1083                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1084                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1085                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1086                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1089
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1093                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1094                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1095                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1096                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1097                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1098
1099                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1100         }
1101
1102         return r;
1103 }
1104
1105 GList*
1106 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1107 {
1108         int i;
1109         static GList *r = NULL;
1110
1111         if (r == NULL) {
1112                 GList *regs = NULL;
1113
1114                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1115                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1116
1117                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1118         }
1119
1120         return r;
1121 }
1122
1123 /*
1124  * mono_arch_regalloc_cost:
1125  *
1126  *  Return the cost, in number of memory references, of the action of
1127  * allocating the variable VMV into a register during global register
1128  * allocation.
1129  */
1130 guint32
1131 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1132 {
1133         MonoInst *ins = cfg->varinfo [vmv->idx];
1134
1135         if (cfg->method->save_lmf)
1136                 /* The register is already saved */
1137                 /* substract 1 for the invisible store in the prolog */
1138                 return (ins->opcode == OP_ARG) ? 0 : 1;
1139         else
1140                 /* push+pop */
1141                 return (ins->opcode == OP_ARG) ? 1 : 2;
1142 }
1143
1144 /*
1145  * mono_arch_fill_argument_info:
1146  *
1147  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1148  * of the method.
1149  */
1150 void
1151 mono_arch_fill_argument_info (MonoCompile *cfg)
1152 {
1153         MonoMethodSignature *sig;
1154         MonoMethodHeader *header;
1155         MonoInst *ins;
1156         int i;
1157         CallInfo *cinfo;
1158
1159         header = mono_method_get_header (cfg->method);
1160
1161         sig = mono_method_signature (cfg->method);
1162
1163         cinfo = cfg->arch.cinfo;
1164
1165         /*
1166          * Contrary to mono_arch_allocate_vars (), the information should describe
1167          * where the arguments are at the beginning of the method, not where they can be
1168          * accessed during the execution of the method. The later makes no sense for the
1169          * global register allocator, since a variable can be in more than one location.
1170          */
1171         if (sig->ret->type != MONO_TYPE_VOID) {
1172                 switch (cinfo->ret.storage) {
1173                 case ArgInIReg:
1174                 case ArgInFloatSSEReg:
1175                 case ArgInDoubleSSEReg:
1176                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1177                                 cfg->vret_addr->opcode = OP_REGVAR;
1178                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1179                         }
1180                         else {
1181                                 cfg->ret->opcode = OP_REGVAR;
1182                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1183                         }
1184                         break;
1185                 case ArgValuetypeInReg:
1186                         cfg->ret->opcode = OP_REGOFFSET;
1187                         cfg->ret->inst_basereg = -1;
1188                         cfg->ret->inst_offset = -1;
1189                         break;
1190                 default:
1191                         g_assert_not_reached ();
1192                 }
1193         }
1194
1195         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1196                 ArgInfo *ainfo = &cinfo->args [i];
1197                 MonoType *arg_type;
1198
1199                 ins = cfg->args [i];
1200
1201                 if (sig->hasthis && (i == 0))
1202                         arg_type = &mono_defaults.object_class->byval_arg;
1203                 else
1204                         arg_type = sig->params [i - sig->hasthis];
1205
1206                 switch (ainfo->storage) {
1207                 case ArgInIReg:
1208                 case ArgInFloatSSEReg:
1209                 case ArgInDoubleSSEReg:
1210                         ins->opcode = OP_REGVAR;
1211                         ins->inst_c0 = ainfo->reg;
1212                         break;
1213                 case ArgOnStack:
1214                         ins->opcode = OP_REGOFFSET;
1215                         ins->inst_basereg = -1;
1216                         ins->inst_offset = -1;
1217                         break;
1218                 case ArgValuetypeInReg:
1219                         /* Dummy */
1220                         ins->opcode = OP_NOP;
1221                         break;
1222                 default:
1223                         g_assert_not_reached ();
1224                 }
1225         }
1226 }
1227
1228 void
1229 mono_arch_allocate_vars (MonoCompile *cfg)
1230 {
1231         MonoMethodSignature *sig;
1232         MonoMethodHeader *header;
1233         MonoInst *ins;
1234         int i, offset;
1235         guint32 locals_stack_size, locals_stack_align;
1236         gint32 *offsets;
1237         CallInfo *cinfo;
1238
1239         header = mono_method_get_header (cfg->method);
1240
1241         sig = mono_method_signature (cfg->method);
1242
1243         cinfo = cfg->arch.cinfo;
1244
1245         mono_arch_compute_omit_fp (cfg);
1246
1247         /*
1248          * We use the ABI calling conventions for managed code as well.
1249          * Exception: valuetypes are never passed or returned in registers.
1250          */
1251
1252         if (cfg->arch.omit_fp) {
1253                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1254                 cfg->frame_reg = AMD64_RSP;
1255                 offset = 0;
1256         } else {
1257                 /* Locals are allocated backwards from %fp */
1258                 cfg->frame_reg = AMD64_RBP;
1259                 offset = 0;
1260         }
1261
1262         if (cfg->method->save_lmf) {
1263                 /* Reserve stack space for saving LMF */
1264                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1265                 g_assert (offset == 0);
1266                 if (cfg->arch.omit_fp) {
1267                         cfg->arch.lmf_offset = offset;
1268                         offset += sizeof (MonoLMF);
1269                 }
1270                 else {
1271                         offset += sizeof (MonoLMF);
1272                         cfg->arch.lmf_offset = -offset;
1273                 }
1274         } else {
1275                 if (cfg->arch.omit_fp)
1276                         cfg->arch.reg_save_area_offset = offset;
1277                 /* Reserve space for caller saved registers */
1278                 for (i = 0; i < AMD64_NREG; ++i)
1279                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1280                                 offset += sizeof (gpointer);
1281                         }
1282         }
1283
1284         if (sig->ret->type != MONO_TYPE_VOID) {
1285                 switch (cinfo->ret.storage) {
1286                 case ArgInIReg:
1287                 case ArgInFloatSSEReg:
1288                 case ArgInDoubleSSEReg:
1289                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1290                                 if (cfg->globalra) {
1291                                         cfg->vret_addr->opcode = OP_REGVAR;
1292                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1293                                 } else {
1294                                         /* The register is volatile */
1295                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1296                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1297                                         if (cfg->arch.omit_fp) {
1298                                                 cfg->vret_addr->inst_offset = offset;
1299                                                 offset += 8;
1300                                         } else {
1301                                                 offset += 8;
1302                                                 cfg->vret_addr->inst_offset = -offset;
1303                                         }
1304                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1305                                                 printf ("vret_addr =");
1306                                                 mono_print_ins (cfg->vret_addr);
1307                                         }
1308                                 }
1309                         }
1310                         else {
1311                                 cfg->ret->opcode = OP_REGVAR;
1312                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1313                         }
1314                         break;
1315                 case ArgValuetypeInReg:
1316                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1317                         cfg->ret->opcode = OP_REGOFFSET;
1318                         cfg->ret->inst_basereg = cfg->frame_reg;
1319                         if (cfg->arch.omit_fp) {
1320                                 cfg->ret->inst_offset = offset;
1321                                 offset += 16;
1322                         } else {
1323                                 offset += 16;
1324                                 cfg->ret->inst_offset = - offset;
1325                         }
1326                         break;
1327                 default:
1328                         g_assert_not_reached ();
1329                 }
1330         }
1331
1332         /* Allocate locals */
1333         if (!cfg->globalra) {
1334                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1335                 if (locals_stack_align) {
1336                         offset += (locals_stack_align - 1);
1337                         offset &= ~(locals_stack_align - 1);
1338                 }
1339                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1340                         if (offsets [i] != -1) {
1341                                 MonoInst *ins = cfg->varinfo [i];
1342                                 ins->opcode = OP_REGOFFSET;
1343                                 ins->inst_basereg = cfg->frame_reg;
1344                                 if (cfg->arch.omit_fp)
1345                                         ins->inst_offset = (offset + offsets [i]);
1346                                 else
1347                                         ins->inst_offset = - (offset + offsets [i]);
1348                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1349                         }
1350                 }
1351                 offset += locals_stack_size;
1352         }
1353
1354         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1355                 g_assert (!cfg->arch.omit_fp);
1356                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1357                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1358         }
1359
1360         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1361                 ins = cfg->args [i];
1362                 if (ins->opcode != OP_REGVAR) {
1363                         ArgInfo *ainfo = &cinfo->args [i];
1364                         gboolean inreg = TRUE;
1365                         MonoType *arg_type;
1366
1367                         if (sig->hasthis && (i == 0))
1368                                 arg_type = &mono_defaults.object_class->byval_arg;
1369                         else
1370                                 arg_type = sig->params [i - sig->hasthis];
1371
1372                         if (cfg->globalra) {
1373                                 /* The new allocator needs info about the original locations of the arguments */
1374                                 switch (ainfo->storage) {
1375                                 case ArgInIReg:
1376                                 case ArgInFloatSSEReg:
1377                                 case ArgInDoubleSSEReg:
1378                                         ins->opcode = OP_REGVAR;
1379                                         ins->inst_c0 = ainfo->reg;
1380                                         break;
1381                                 case ArgOnStack:
1382                                         g_assert (!cfg->arch.omit_fp);
1383                                         ins->opcode = OP_REGOFFSET;
1384                                         ins->inst_basereg = cfg->frame_reg;
1385                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1386                                         break;
1387                                 case ArgValuetypeInReg:
1388                                         ins->opcode = OP_REGOFFSET;
1389                                         ins->inst_basereg = cfg->frame_reg;
1390                                         /* These arguments are saved to the stack in the prolog */
1391                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1392                                         if (cfg->arch.omit_fp) {
1393                                                 ins->inst_offset = offset;
1394                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1395                                         } else {
1396                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1397                                                 ins->inst_offset = - offset;
1398                                         }
1399                                         break;
1400                                 default:
1401                                         g_assert_not_reached ();
1402                                 }
1403
1404                                 continue;
1405                         }
1406
1407                         /* FIXME: Allocate volatile arguments to registers */
1408                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1409                                 inreg = FALSE;
1410
1411                         /*
1412                          * Under AMD64, all registers used to pass arguments to functions
1413                          * are volatile across calls.
1414                          * FIXME: Optimize this.
1415                          */
1416                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1417                                 inreg = FALSE;
1418
1419                         ins->opcode = OP_REGOFFSET;
1420
1421                         switch (ainfo->storage) {
1422                         case ArgInIReg:
1423                         case ArgInFloatSSEReg:
1424                         case ArgInDoubleSSEReg:
1425                                 if (inreg) {
1426                                         ins->opcode = OP_REGVAR;
1427                                         ins->dreg = ainfo->reg;
1428                                 }
1429                                 break;
1430                         case ArgOnStack:
1431                                 g_assert (!cfg->arch.omit_fp);
1432                                 ins->opcode = OP_REGOFFSET;
1433                                 ins->inst_basereg = cfg->frame_reg;
1434                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1435                                 break;
1436                         case ArgValuetypeInReg:
1437                                 break;
1438                         case ArgValuetypeAddrInIReg: {
1439                                 MonoInst *indir;
1440                                 g_assert (!cfg->arch.omit_fp);
1441
1442                                 MONO_INST_NEW (cfg, indir, 0);
1443                                 indir->opcode = OP_REGOFFSET;
1444                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1445                                         indir->inst_basereg = cfg->frame_reg;
1446                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1447                                         offset += (sizeof (gpointer));
1448                                         indir->inst_offset = - offset;
1449                                 }
1450                                 else {
1451                                         indir->inst_basereg = cfg->frame_reg;
1452                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1453                                 }
1454
1455                                 ins->opcode = OP_VTARG_ADDR;
1456                                 ins->inst_left = indir;
1457
1458                                 break;
1459                         }
1460                         default:
1461                                 NOT_IMPLEMENTED;
1462                         }
1463
1464                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1465                                 ins->opcode = OP_REGOFFSET;
1466                                 ins->inst_basereg = cfg->frame_reg;
1467                                 /* These arguments are saved to the stack in the prolog */
1468                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1469                                 if (cfg->arch.omit_fp) {
1470                                         ins->inst_offset = offset;
1471                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1472                                 } else {
1473                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1474                                         ins->inst_offset = - offset;
1475                                 }
1476                         }
1477                 }
1478         }
1479
1480         cfg->stack_offset = offset;
1481 }
1482
1483 void
1484 mono_arch_create_vars (MonoCompile *cfg)
1485 {
1486         MonoMethodSignature *sig;
1487         CallInfo *cinfo;
1488
1489         sig = mono_method_signature (cfg->method);
1490
1491         if (!cfg->arch.cinfo)
1492                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1493         cinfo = cfg->arch.cinfo;
1494
1495         if (cinfo->ret.storage == ArgValuetypeInReg)
1496                 cfg->ret_var_is_local = TRUE;
1497
1498         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1499                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1500                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1501                         printf ("vret_addr = ");
1502                         mono_print_ins (cfg->vret_addr);
1503                 }
1504         }
1505 }
1506
1507 static void
1508 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1509 {
1510         MonoInst *ins;
1511
1512         switch (storage) {
1513         case ArgInIReg:
1514                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1515                 ins->dreg = mono_alloc_ireg (cfg);
1516                 ins->sreg1 = tree->dreg;
1517                 MONO_ADD_INS (cfg->cbb, ins);
1518                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1519                 break;
1520         case ArgInFloatSSEReg:
1521                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1522                 ins->dreg = mono_alloc_freg (cfg);
1523                 ins->sreg1 = tree->dreg;
1524                 MONO_ADD_INS (cfg->cbb, ins);
1525
1526                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1527                 break;
1528         case ArgInDoubleSSEReg:
1529                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1530                 ins->dreg = mono_alloc_freg (cfg);
1531                 ins->sreg1 = tree->dreg;
1532                 MONO_ADD_INS (cfg->cbb, ins);
1533
1534                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1535
1536                 break;
1537         default:
1538                 g_assert_not_reached ();
1539         }
1540 }
1541
1542 static int
1543 arg_storage_to_load_membase (ArgStorage storage)
1544 {
1545         switch (storage) {
1546         case ArgInIReg:
1547                 return OP_LOAD_MEMBASE;
1548         case ArgInDoubleSSEReg:
1549                 return OP_LOADR8_MEMBASE;
1550         case ArgInFloatSSEReg:
1551                 return OP_LOADR4_MEMBASE;
1552         default:
1553                 g_assert_not_reached ();
1554         }
1555
1556         return -1;
1557 }
1558
1559 static void
1560 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1561 {
1562         MonoInst *arg;
1563         MonoMethodSignature *tmp_sig;
1564         MonoInst *sig_arg;
1565
1566         if (call->tail_call)
1567                 NOT_IMPLEMENTED;
1568
1569         /* FIXME: Add support for signature tokens to AOT */
1570         cfg->disable_aot = TRUE;
1571
1572         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1573
1574         /*
1575          * mono_ArgIterator_Setup assumes the signature cookie is
1576          * passed first and all the arguments which were before it are
1577          * passed on the stack after the signature. So compensate by
1578          * passing a different signature.
1579          */
1580         tmp_sig = mono_metadata_signature_dup (call->signature);
1581         tmp_sig->param_count -= call->signature->sentinelpos;
1582         tmp_sig->sentinelpos = 0;
1583         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1584
1585         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1586         sig_arg->dreg = mono_alloc_ireg (cfg);
1587         sig_arg->inst_p0 = tmp_sig;
1588         MONO_ADD_INS (cfg->cbb, sig_arg);
1589
1590         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1591         arg->sreg1 = sig_arg->dreg;
1592         MONO_ADD_INS (cfg->cbb, arg);
1593 }
1594
1595 void
1596 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1597 {
1598         MonoInst *arg, *in;
1599         MonoMethodSignature *sig;
1600         int i, n, stack_size;
1601         CallInfo *cinfo;
1602         ArgInfo *ainfo;
1603
1604         stack_size = 0;
1605
1606         sig = call->signature;
1607         n = sig->param_count + sig->hasthis;
1608
1609         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1610
1611         if (cinfo->need_stack_align) {
1612                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1613         }
1614
1615         /*
1616          * Emit all parameters passed in registers in non-reverse order for better readability
1617          * and to help the optimization in emit_prolog ().
1618          */
1619         for (i = 0; i < n; ++i) {
1620                 ainfo = cinfo->args + i;
1621
1622                 in = call->args [i];
1623
1624                 if (ainfo->storage == ArgInIReg)
1625                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1626         }
1627
1628         for (i = n - 1; i >= 0; --i) {
1629                 ainfo = cinfo->args + i;
1630
1631                 in = call->args [i];
1632
1633                 switch (ainfo->storage) {
1634                 case ArgInIReg:
1635                         /* Already done */
1636                         break;
1637                 case ArgInFloatSSEReg:
1638                 case ArgInDoubleSSEReg:
1639                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1640                         break;
1641                 case ArgOnStack:
1642                 case ArgValuetypeInReg:
1643                 case ArgValuetypeAddrInIReg:
1644                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1645                                 MonoInst *call_inst = (MonoInst*)call;
1646                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1647                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1648                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1649                                 guint32 align;
1650                                 guint32 size;
1651
1652                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1653                                         size = sizeof (MonoTypedRef);
1654                                         align = sizeof (gpointer);
1655                                 }
1656                                 else {
1657                                         if (sig->pinvoke)
1658                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1659                                         else {
1660                                                 /*
1661                                                  * Other backends use mono_type_stack_size (), but that
1662                                                  * aligns the size to 8, which is larger than the size of
1663                                                  * the source, leading to reads of invalid memory if the
1664                                                  * source is at the end of address space.
1665                                                  */
1666                                                 size = mono_class_value_size (in->klass, &align);
1667                                         }
1668                                 }
1669                                 g_assert (in->klass);
1670
1671                                 if (size > 0) {
1672                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1673                                         arg->sreg1 = in->dreg;
1674                                         arg->klass = in->klass;
1675                                         arg->backend.size = size;
1676                                         arg->inst_p0 = call;
1677                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1678                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1679
1680                                         MONO_ADD_INS (cfg->cbb, arg);
1681                                 }
1682                         } else {
1683                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1684                                 arg->sreg1 = in->dreg;
1685                                 if (!sig->params [i - sig->hasthis]->byref) {
1686                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1687                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1688                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
1689                                                 arg->inst_destbasereg = X86_ESP;
1690                                                 arg->inst_offset = 0;
1691                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1692                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1693                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
1694                                                 arg->inst_destbasereg = X86_ESP;
1695                                                 arg->inst_offset = 0;
1696                                         }
1697                                 }
1698                                 MONO_ADD_INS (cfg->cbb, arg);
1699                         }
1700                         break;
1701                 default:
1702                         g_assert_not_reached ();
1703                 }
1704
1705                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1706                         /* Emit the signature cookie just before the implicit arguments */
1707                         emit_sig_cookie (cfg, call, cinfo);
1708         }
1709
1710         /* Handle the case where there are no implicit arguments */
1711         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1712                 emit_sig_cookie (cfg, call, cinfo);
1713
1714         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1715                 MonoInst *vtarg;
1716
1717                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1718                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1719                                 /*
1720                                  * Tell the JIT to use a more efficient calling convention: call using
1721                                  * OP_CALL, compute the result location after the call, and save the
1722                                  * result there.
1723                                  */
1724                                 call->vret_in_reg = TRUE;
1725                                 /*
1726                                  * Nullify the instruction computing the vret addr to enable
1727                                  * future optimizations.
1728                                  */
1729                                 if (call->vret_var)
1730                                         NULLIFY_INS (call->vret_var);
1731                         } else {
1732                                 if (call->tail_call)
1733                                         NOT_IMPLEMENTED;
1734                                 /*
1735                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1736                                  * the stack. Push the address here, so the call instruction can
1737                                  * access it.
1738                                  */
1739                                 if (!cfg->arch.vret_addr_loc) {
1740                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1741                                         /* Prevent it from being register allocated or optimized away */
1742                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1743                                 }
1744
1745                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1746                         }
1747                 }
1748                 else {
1749                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1750                         vtarg->sreg1 = call->vret_var->dreg;
1751                         vtarg->dreg = mono_alloc_preg (cfg);
1752                         MONO_ADD_INS (cfg->cbb, vtarg);
1753
1754                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1755                 }
1756         }
1757
1758 #ifdef PLATFORM_WIN32
1759         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1760                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1761         }
1762 #endif
1763
1764         if (cfg->method->save_lmf) {
1765                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1766                 MONO_ADD_INS (cfg->cbb, arg);
1767         }
1768
1769         call->stack_usage = cinfo->stack_usage;
1770 }
1771
1772 void
1773 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1774 {
1775         MonoInst *arg;
1776         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1777         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1778         int size = ins->backend.size;
1779
1780         if (ainfo->storage == ArgValuetypeInReg) {
1781                 MonoInst *load;
1782                 int part;
1783
1784                 for (part = 0; part < 2; ++part) {
1785                         if (ainfo->pair_storage [part] == ArgNone)
1786                                 continue;
1787
1788                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
1789                         load->inst_basereg = src->dreg;
1790                         load->inst_offset = part * sizeof (gpointer);
1791
1792                         switch (ainfo->pair_storage [part]) {
1793                         case ArgInIReg:
1794                                 load->dreg = mono_alloc_ireg (cfg);
1795                                 break;
1796                         case ArgInDoubleSSEReg:
1797                         case ArgInFloatSSEReg:
1798                                 load->dreg = mono_alloc_freg (cfg);
1799                                 break;
1800                         default:
1801                                 g_assert_not_reached ();
1802                         }
1803                         MONO_ADD_INS (cfg->cbb, load);
1804
1805                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
1806                 }
1807         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
1808                 MonoInst *vtaddr, *load;
1809                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
1810
1811                 MONO_INST_NEW (cfg, load, OP_LDADDR);
1812                 load->inst_p0 = vtaddr;
1813                 vtaddr->flags |= MONO_INST_INDIRECT;
1814                 load->type = STACK_MP;
1815                 load->klass = vtaddr->klass;
1816                 load->dreg = mono_alloc_ireg (cfg);
1817                 MONO_ADD_INS (cfg->cbb, load);
1818                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
1819
1820                 if (ainfo->pair_storage [0] == ArgInIReg) {
1821                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
1822                         arg->dreg = mono_alloc_ireg (cfg);
1823                         arg->sreg1 = load->dreg;
1824                         arg->inst_imm = 0;
1825                         MONO_ADD_INS (cfg->cbb, arg);
1826                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
1827                 } else {
1828                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1829                         arg->sreg1 = load->dreg;
1830                         MONO_ADD_INS (cfg->cbb, arg);
1831                 }
1832         } else {
1833                 if (size == 8) {
1834                         /* Can't use this for < 8 since it does an 8 byte memory load */
1835                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1836                         arg->inst_basereg = src->dreg;
1837                         arg->inst_offset = 0;
1838                         MONO_ADD_INS (cfg->cbb, arg);
1839                 } else if (size <= 40) {
1840                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
1841                         mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1842                 } else {
1843                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1844                         arg->inst_basereg = src->dreg;
1845                         arg->inst_offset = 0;
1846                         arg->inst_imm = size;
1847                         MONO_ADD_INS (cfg->cbb, arg);
1848                 }
1849         }
1850 }
1851
1852 void
1853 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1854 {
1855         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
1856
1857         if (!ret->byref) {
1858                 if (ret->type == MONO_TYPE_R4) {
1859                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
1860                         return;
1861                 } else if (ret->type == MONO_TYPE_R8) {
1862                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1863                         return;
1864                 }
1865         }
1866
1867         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1868 }
1869
1870 #define EMIT_COND_BRANCH(ins,cond,sign) \
1871 if (ins->flags & MONO_INST_BRLABEL) { \
1872         if (ins->inst_i0->inst_c0) { \
1873                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1874         } else { \
1875                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1876                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1877                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1878                         x86_branch8 (code, cond, 0, sign); \
1879                 else \
1880                         x86_branch32 (code, cond, 0, sign); \
1881         } \
1882 } else { \
1883         if (ins->inst_true_bb->native_offset) { \
1884                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1885         } else { \
1886                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1887                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1888                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1889                         x86_branch8 (code, cond, 0, sign); \
1890                 else \
1891                         x86_branch32 (code, cond, 0, sign); \
1892         } \
1893 }
1894
1895 /* emit an exception if condition is fail */
1896 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1897         do {                                                        \
1898                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1899                 if (tins == NULL) {                                                                             \
1900                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1901                                         MONO_PATCH_INFO_EXC, exc_name);  \
1902                         x86_branch32 (code, cond, 0, signed);               \
1903                 } else {        \
1904                         EMIT_COND_BRANCH (tins, cond, signed);  \
1905                 }                       \
1906         } while (0);
1907
1908 #define EMIT_FPCOMPARE(code) do { \
1909         amd64_fcompp (code); \
1910         amd64_fnstsw (code); \
1911 } while (0);
1912
1913 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1914     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1915         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1916         amd64_ ##op (code); \
1917         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1918         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1919 } while (0);
1920
1921 static guint8*
1922 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1923 {
1924         gboolean no_patch = FALSE;
1925
1926         /*
1927          * FIXME: Add support for thunks
1928          */
1929         {
1930                 gboolean near_call = FALSE;
1931
1932                 /*
1933                  * Indirect calls are expensive so try to make a near call if possible.
1934                  * The caller memory is allocated by the code manager so it is
1935                  * guaranteed to be at a 32 bit offset.
1936                  */
1937
1938                 if (patch_type != MONO_PATCH_INFO_ABS) {
1939                         /* The target is in memory allocated using the code manager */
1940                         near_call = TRUE;
1941
1942                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1943                                 if (((MonoMethod*)data)->klass->image->aot_module)
1944                                         /* The callee might be an AOT method */
1945                                         near_call = FALSE;
1946                                 if (((MonoMethod*)data)->dynamic)
1947                                         /* The target is in malloc-ed memory */
1948                                         near_call = FALSE;
1949                         }
1950
1951                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1952                                 /*
1953                                  * The call might go directly to a native function without
1954                                  * the wrapper.
1955                                  */
1956                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1957                                 if (mi) {
1958                                         gconstpointer target = mono_icall_get_wrapper (mi);
1959                                         if ((((guint64)target) >> 32) != 0)
1960                                                 near_call = FALSE;
1961                                 }
1962                         }
1963                 }
1964                 else {
1965                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
1966                                 /*
1967                                  * This is not really an optimization, but required because the
1968                                  * generic class init trampolines use R11 to pass the vtable.
1969                                  */
1970                                 near_call = TRUE;
1971                         } else {
1972                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1973                                 if (info) {
1974                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1975                                                 strstr (cfg->method->name, info->name)) {
1976                                                 /* A call to the wrapped function */
1977                                                 if ((((guint64)data) >> 32) == 0)
1978                                                         near_call = TRUE;
1979                                                 no_patch = TRUE;
1980                                         }
1981                                         else if (info->func == info->wrapper) {
1982                                                 /* No wrapper */
1983                                                 if ((((guint64)info->func) >> 32) == 0)
1984                                                         near_call = TRUE;
1985                                         }
1986                                         else {
1987                                                 /* See the comment in mono_codegen () */
1988                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1989                                                         near_call = TRUE;
1990                                         }
1991                                 }
1992                                 else if ((((guint64)data) >> 32) == 0) {
1993                                         near_call = TRUE;
1994                                         no_patch = TRUE;
1995                                 }
1996                         }
1997                 }
1998
1999                 if (cfg->method->dynamic)
2000                         /* These methods are allocated using malloc */
2001                         near_call = FALSE;
2002
2003                 if (cfg->compile_aot) {
2004                         near_call = TRUE;
2005                         no_patch = TRUE;
2006                 }
2007
2008 #ifdef MONO_ARCH_NOMAP32BIT
2009                 near_call = FALSE;
2010 #endif
2011
2012                 if (near_call) {
2013                         /*
2014                          * Align the call displacement to an address divisible by 4 so it does
2015                          * not span cache lines. This is required for code patching to work on SMP
2016                          * systems.
2017                          */
2018                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2019                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2020                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2021                         amd64_call_code (code, 0);
2022                 }
2023                 else {
2024                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2025                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2026                         amd64_call_reg (code, GP_SCRATCH_REG);
2027                 }
2028         }
2029
2030         return code;
2031 }
2032
2033 static inline guint8*
2034 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2035 {
2036 #ifdef PLATFORM_WIN32
2037         if (win64_adjust_stack)
2038                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2039 #endif
2040         code = emit_call_body (cfg, code, patch_type, data);
2041 #ifdef PLATFORM_WIN32
2042         if (win64_adjust_stack)
2043                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2044 #endif
2045
2046         return code;
2047 }
2048
2049 static inline int
2050 store_membase_imm_to_store_membase_reg (int opcode)
2051 {
2052         switch (opcode) {
2053         case OP_STORE_MEMBASE_IMM:
2054                 return OP_STORE_MEMBASE_REG;
2055         case OP_STOREI4_MEMBASE_IMM:
2056                 return OP_STOREI4_MEMBASE_REG;
2057         case OP_STOREI8_MEMBASE_IMM:
2058                 return OP_STOREI8_MEMBASE_REG;
2059         }
2060
2061         return -1;
2062 }
2063
2064 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2065
2066 /*
2067  * mono_arch_peephole_pass_1:
2068  *
2069  *   Perform peephole opts which should/can be performed before local regalloc
2070  */
2071 void
2072 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2073 {
2074         MonoInst *ins, *n;
2075
2076         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2077                 MonoInst *last_ins = ins->prev;
2078
2079                 switch (ins->opcode) {
2080                 case OP_ADD_IMM:
2081                 case OP_IADD_IMM:
2082                 case OP_LADD_IMM:
2083                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2084                                 /*
2085                                  * X86_LEA is like ADD, but doesn't have the
2086                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2087                                  * its operand to 64 bit.
2088                                  */
2089                                 ins->opcode = OP_X86_LEA_MEMBASE;
2090                                 ins->inst_basereg = ins->sreg1;
2091                         }
2092                         break;
2093                 case OP_LXOR:
2094                 case OP_IXOR:
2095                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2096                                 MonoInst *ins2;
2097
2098                                 /*
2099                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2100                                  * the latter has length 2-3 instead of 6 (reverse constant
2101                                  * propagation). These instruction sequences are very common
2102                                  * in the initlocals bblock.
2103                                  */
2104                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2105                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2106                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2107                                                 ins2->sreg1 = ins->dreg;
2108                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2109                                                 /* Continue */
2110                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2111                                                 NULLIFY_INS (ins2);
2112                                                 /* Continue */
2113                                         } else {
2114                                                 break;
2115                                         }
2116                                 }
2117                         }
2118                         break;
2119                 case OP_COMPARE_IMM:
2120                 case OP_LCOMPARE_IMM:
2121                         /* OP_COMPARE_IMM (reg, 0)
2122                          * -->
2123                          * OP_AMD64_TEST_NULL (reg)
2124                          */
2125                         if (!ins->inst_imm)
2126                                 ins->opcode = OP_AMD64_TEST_NULL;
2127                         break;
2128                 case OP_ICOMPARE_IMM:
2129                         if (!ins->inst_imm)
2130                                 ins->opcode = OP_X86_TEST_NULL;
2131                         break;
2132                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2133                         /*
2134                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2135                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2136                          * -->
2137                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2138                          * OP_COMPARE_IMM reg, imm
2139                          *
2140                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2141                          */
2142                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2143                             ins->inst_basereg == last_ins->inst_destbasereg &&
2144                             ins->inst_offset == last_ins->inst_offset) {
2145                                         ins->opcode = OP_ICOMPARE_IMM;
2146                                         ins->sreg1 = last_ins->sreg1;
2147
2148                                         /* check if we can remove cmp reg,0 with test null */
2149                                         if (!ins->inst_imm)
2150                                                 ins->opcode = OP_X86_TEST_NULL;
2151                                 }
2152
2153                         break;
2154                 }
2155
2156                 mono_peephole_ins (bb, ins);
2157         }
2158 }
2159
2160 void
2161 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2162 {
2163         MonoInst *ins, *n;
2164
2165         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2166                 switch (ins->opcode) {
2167                 case OP_ICONST:
2168                 case OP_I8CONST: {
2169                         /* reg = 0 -> XOR (reg, reg) */
2170                         /* XOR sets cflags on x86, so we cant do it always */
2171                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2172                                 ins->opcode = OP_LXOR;
2173                                 ins->sreg1 = ins->dreg;
2174                                 ins->sreg2 = ins->dreg;
2175                                 /* Fall through */
2176                         } else {
2177                                 break;
2178                         }
2179                 }
2180                 case OP_LXOR:
2181                         /*
2182                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2183                          * 0 result into 64 bits.
2184                          */
2185                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2186                                 ins->opcode = OP_IXOR;
2187                         }
2188                         /* Fall through */
2189                 case OP_IXOR:
2190                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2191                                 MonoInst *ins2;
2192
2193                                 /*
2194                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2195                                  * the latter has length 2-3 instead of 6 (reverse constant
2196                                  * propagation). These instruction sequences are very common
2197                                  * in the initlocals bblock.
2198                                  */
2199                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2200                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2201                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2202                                                 ins2->sreg1 = ins->dreg;
2203                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2204                                                 /* Continue */
2205                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2206                                                 NULLIFY_INS (ins2);
2207                                                 /* Continue */
2208                                         } else {
2209                                                 break;
2210                                         }
2211                                 }
2212                         }
2213                         break;
2214                 case OP_IADD_IMM:
2215                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2216                                 ins->opcode = OP_X86_INC_REG;
2217                         break;
2218                 case OP_ISUB_IMM:
2219                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2220                                 ins->opcode = OP_X86_DEC_REG;
2221                         break;
2222                 }
2223
2224                 mono_peephole_ins (bb, ins);
2225         }
2226 }
2227
2228 #define NEW_INS(cfg,ins,dest,op) do {   \
2229                 MONO_INST_NEW ((cfg), (dest), (op)); \
2230         (dest)->cil_code = (ins)->cil_code; \
2231         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2232         } while (0)
2233
2234 /*
2235  * mono_arch_lowering_pass:
2236  *
2237  *  Converts complex opcodes into simpler ones so that each IR instruction
2238  * corresponds to one machine instruction.
2239  */
2240 void
2241 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2242 {
2243         MonoInst *ins, *n, *temp;
2244
2245         /*
2246          * FIXME: Need to add more instructions, but the current machine
2247          * description can't model some parts of the composite instructions like
2248          * cdq.
2249          */
2250         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2251                 switch (ins->opcode) {
2252                 case OP_DIV_IMM:
2253                 case OP_REM_IMM:
2254                 case OP_IDIV_IMM:
2255                 case OP_IDIV_UN_IMM:
2256                 case OP_IREM_UN_IMM:
2257                         mono_decompose_op_imm (cfg, bb, ins);
2258                         break;
2259                 case OP_IREM_IMM:
2260                         /* Keep the opcode if we can implement it efficiently */
2261                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2262                                 mono_decompose_op_imm (cfg, bb, ins);
2263                         break;
2264                 case OP_COMPARE_IMM:
2265                 case OP_LCOMPARE_IMM:
2266                         if (!amd64_is_imm32 (ins->inst_imm)) {
2267                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2268                                 temp->inst_c0 = ins->inst_imm;
2269                                 temp->dreg = mono_alloc_ireg (cfg);
2270                                 ins->opcode = OP_COMPARE;
2271                                 ins->sreg2 = temp->dreg;
2272                         }
2273                         break;
2274                 case OP_LOAD_MEMBASE:
2275                 case OP_LOADI8_MEMBASE:
2276                         if (!amd64_is_imm32 (ins->inst_offset)) {
2277                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2278                                 temp->inst_c0 = ins->inst_offset;
2279                                 temp->dreg = mono_alloc_ireg (cfg);
2280                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2281                                 ins->inst_indexreg = temp->dreg;
2282                         }
2283                         break;
2284                 case OP_STORE_MEMBASE_IMM:
2285                 case OP_STOREI8_MEMBASE_IMM:
2286                         if (!amd64_is_imm32 (ins->inst_imm)) {
2287                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2288                                 temp->inst_c0 = ins->inst_imm;
2289                                 temp->dreg = mono_alloc_ireg (cfg);
2290                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2291                                 ins->sreg1 = temp->dreg;
2292                         }
2293                         break;
2294                 default:
2295                         break;
2296                 }
2297         }
2298
2299         bb->max_vreg = cfg->next_vreg;
2300 }
2301
2302 static const int
2303 branch_cc_table [] = {
2304         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2305         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2306         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2307 };
2308
2309 /* Maps CMP_... constants to X86_CC_... constants */
2310 static const int
2311 cc_table [] = {
2312         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2313         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2314 };
2315
2316 static const int
2317 cc_signed_table [] = {
2318         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2319         FALSE, FALSE, FALSE, FALSE
2320 };
2321
2322 /*#include "cprop.c"*/
2323
2324 static unsigned char*
2325 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2326 {
2327         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2328
2329         if (size == 1)
2330                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2331         else if (size == 2)
2332                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2333         return code;
2334 }
2335
2336 static unsigned char*
2337 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2338 {
2339         int sreg = tree->sreg1;
2340         int need_touch = FALSE;
2341
2342 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2343         if (!tree->flags & MONO_INST_INIT)
2344                 need_touch = TRUE;
2345 #endif
2346
2347         if (need_touch) {
2348                 guint8* br[5];
2349
2350                 /*
2351                  * Under Windows:
2352                  * If requested stack size is larger than one page,
2353                  * perform stack-touch operation
2354                  */
2355                 /*
2356                  * Generate stack probe code.
2357                  * Under Windows, it is necessary to allocate one page at a time,
2358                  * "touching" stack after each successful sub-allocation. This is
2359                  * because of the way stack growth is implemented - there is a
2360                  * guard page before the lowest stack page that is currently commited.
2361                  * Stack normally grows sequentially so OS traps access to the
2362                  * guard page and commits more pages when needed.
2363                  */
2364                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2365                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2366
2367                 br[2] = code; /* loop */
2368                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2369                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2370                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2371                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2372                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2373                 amd64_patch (br[3], br[2]);
2374                 amd64_test_reg_reg (code, sreg, sreg);
2375                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2376                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2377
2378                 br[1] = code; x86_jump8 (code, 0);
2379
2380                 amd64_patch (br[0], code);
2381                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2382                 amd64_patch (br[1], code);
2383                 amd64_patch (br[4], code);
2384         }
2385         else
2386                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2387
2388         if (tree->flags & MONO_INST_INIT) {
2389                 int offset = 0;
2390                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2391                         amd64_push_reg (code, AMD64_RAX);
2392                         offset += 8;
2393                 }
2394                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2395                         amd64_push_reg (code, AMD64_RCX);
2396                         offset += 8;
2397                 }
2398                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2399                         amd64_push_reg (code, AMD64_RDI);
2400                         offset += 8;
2401                 }
2402
2403                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2404                 if (sreg != AMD64_RCX)
2405                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2406                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2407
2408                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2409                 amd64_cld (code);
2410                 amd64_prefix (code, X86_REP_PREFIX);
2411                 amd64_stosl (code);
2412
2413                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2414                         amd64_pop_reg (code, AMD64_RDI);
2415                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2416                         amd64_pop_reg (code, AMD64_RCX);
2417                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2418                         amd64_pop_reg (code, AMD64_RAX);
2419         }
2420         return code;
2421 }
2422
2423 static guint8*
2424 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2425 {
2426         CallInfo *cinfo;
2427         guint32 quad;
2428
2429         /* Move return value to the target register */
2430         /* FIXME: do this in the local reg allocator */
2431         switch (ins->opcode) {
2432         case OP_CALL:
2433         case OP_CALL_REG:
2434         case OP_CALL_MEMBASE:
2435         case OP_LCALL:
2436         case OP_LCALL_REG:
2437         case OP_LCALL_MEMBASE:
2438                 g_assert (ins->dreg == AMD64_RAX);
2439                 break;
2440         case OP_FCALL:
2441         case OP_FCALL_REG:
2442         case OP_FCALL_MEMBASE:
2443                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2444                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2445                 }
2446                 else {
2447                         if (ins->dreg != AMD64_XMM0)
2448                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2449                 }
2450                 break;
2451         case OP_VCALL:
2452         case OP_VCALL_REG:
2453         case OP_VCALL_MEMBASE:
2454         case OP_VCALL2:
2455         case OP_VCALL2_REG:
2456         case OP_VCALL2_MEMBASE:
2457                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2458                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2459                         MonoInst *loc = cfg->arch.vret_addr_loc;
2460
2461                         /* Load the destination address */
2462                         g_assert (loc->opcode == OP_REGOFFSET);
2463                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2464
2465                         for (quad = 0; quad < 2; quad ++) {
2466                                 switch (cinfo->ret.pair_storage [quad]) {
2467                                 case ArgInIReg:
2468                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2469                                         break;
2470                                 case ArgInFloatSSEReg:
2471                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2472                                         break;
2473                                 case ArgInDoubleSSEReg:
2474                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2475                                         break;
2476                                 case ArgNone:
2477                                         break;
2478                                 default:
2479                                         NOT_IMPLEMENTED;
2480                                 }
2481                         }
2482                 }
2483                 break;
2484         }
2485
2486         return code;
2487 }
2488
2489 /*
2490  * mono_amd64_emit_tls_get:
2491  * @code: buffer to store code to
2492  * @dreg: hard register where to place the result
2493  * @tls_offset: offset info
2494  *
2495  * mono_amd64_emit_tls_get emits in @code the native code that puts in
2496  * the dreg register the item in the thread local storage identified
2497  * by tls_offset.
2498  *
2499  * Returns: a pointer to the end of the stored code
2500  */
2501 guint8*
2502 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2503 {
2504 #ifdef PLATFORM_WIN32
2505         g_assert (tls_offset < 64);
2506         x86_prefix (code, X86_GS_PREFIX);
2507         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2508 #else
2509         if (optimize_for_xen) {
2510                 x86_prefix (code, X86_FS_PREFIX);
2511                 amd64_mov_reg_mem (code, dreg, 0, 8);
2512                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2513         } else {
2514                 x86_prefix (code, X86_FS_PREFIX);
2515                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2516         }
2517 #endif
2518         return code;
2519 }
2520
2521 #define REAL_PRINT_REG(text,reg) \
2522 mono_assert (reg >= 0); \
2523 amd64_push_reg (code, AMD64_RAX); \
2524 amd64_push_reg (code, AMD64_RDX); \
2525 amd64_push_reg (code, AMD64_RCX); \
2526 amd64_push_reg (code, reg); \
2527 amd64_push_imm (code, reg); \
2528 amd64_push_imm (code, text " %d %p\n"); \
2529 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2530 amd64_call_reg (code, AMD64_RAX); \
2531 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2532 amd64_pop_reg (code, AMD64_RCX); \
2533 amd64_pop_reg (code, AMD64_RDX); \
2534 amd64_pop_reg (code, AMD64_RAX);
2535
2536 /* benchmark and set based on cpu */
2537 #define LOOP_ALIGNMENT 8
2538 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2539
2540 #ifndef DISABLE_JIT
2541
2542 void
2543 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2544 {
2545         MonoInst *ins;
2546         MonoCallInst *call;
2547         guint offset;
2548         guint8 *code = cfg->native_code + cfg->code_len;
2549         MonoInst *last_ins = NULL;
2550         guint last_offset = 0;
2551         int max_len, cpos;
2552
2553         if (cfg->opt & MONO_OPT_LOOP) {
2554                 int pad, align = LOOP_ALIGNMENT;
2555                 /* set alignment depending on cpu */
2556                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2557                         pad = align - pad;
2558                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2559                         amd64_padding (code, pad);
2560                         cfg->code_len += pad;
2561                         bb->native_offset = cfg->code_len;
2562                 }
2563         }
2564
2565         if (cfg->verbose_level > 2)
2566                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2567
2568         cpos = bb->max_offset;
2569
2570         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2571                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2572                 g_assert (!cfg->compile_aot);
2573                 cpos += 6;
2574
2575                 cov->data [bb->dfn].cil_code = bb->cil_code;
2576                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2577                 /* this is not thread save, but good enough */
2578                 amd64_inc_membase (code, AMD64_R11, 0);
2579         }
2580
2581         offset = code - cfg->native_code;
2582
2583         mono_debug_open_block (cfg, bb, offset);
2584
2585     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2586                 x86_breakpoint (code);
2587
2588         MONO_BB_FOR_EACH_INS (bb, ins) {
2589                 offset = code - cfg->native_code;
2590
2591                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2592
2593                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2594                         cfg->code_size *= 2;
2595                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2596                         code = cfg->native_code + offset;
2597                         mono_jit_stats.code_reallocs++;
2598                 }
2599
2600                 if (cfg->debug_info)
2601                         mono_debug_record_line_number (cfg, ins, offset);
2602
2603                 switch (ins->opcode) {
2604                 case OP_BIGMUL:
2605                         amd64_mul_reg (code, ins->sreg2, TRUE);
2606                         break;
2607                 case OP_BIGMUL_UN:
2608                         amd64_mul_reg (code, ins->sreg2, FALSE);
2609                         break;
2610                 case OP_X86_SETEQ_MEMBASE:
2611                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2612                         break;
2613                 case OP_STOREI1_MEMBASE_IMM:
2614                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2615                         break;
2616                 case OP_STOREI2_MEMBASE_IMM:
2617                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2618                         break;
2619                 case OP_STOREI4_MEMBASE_IMM:
2620                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2621                         break;
2622                 case OP_STOREI1_MEMBASE_REG:
2623                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2624                         break;
2625                 case OP_STOREI2_MEMBASE_REG:
2626                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2627                         break;
2628                 case OP_STORE_MEMBASE_REG:
2629                 case OP_STOREI8_MEMBASE_REG:
2630                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2631                         break;
2632                 case OP_STOREI4_MEMBASE_REG:
2633                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2634                         break;
2635                 case OP_STORE_MEMBASE_IMM:
2636                 case OP_STOREI8_MEMBASE_IMM:
2637                         g_assert (amd64_is_imm32 (ins->inst_imm));
2638                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2639                         break;
2640                 case OP_LOAD_MEM:
2641                 case OP_LOADI8_MEM:
2642                         // FIXME: Decompose this earlier
2643                         if (amd64_is_imm32 (ins->inst_imm))
2644                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2645                         else {
2646                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2647                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2648                         }
2649                         break;
2650                 case OP_LOADI4_MEM:
2651                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2652                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2653                         break;
2654                 case OP_LOADU4_MEM:
2655                         // FIXME: Decompose this earlier
2656                         if (amd64_is_imm32 (ins->inst_imm))
2657                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2658                         else {
2659                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2660                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2661                         }
2662                         break;
2663                 case OP_LOADU1_MEM:
2664                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2665                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2666                         break;
2667                 case OP_LOADU2_MEM:
2668                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2669                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2670                         break;
2671                 case OP_LOAD_MEMBASE:
2672                 case OP_LOADI8_MEMBASE:
2673                         g_assert (amd64_is_imm32 (ins->inst_offset));
2674                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2675                         break;
2676                 case OP_LOADI4_MEMBASE:
2677                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2678                         break;
2679                 case OP_LOADU4_MEMBASE:
2680                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2681                         break;
2682                 case OP_LOADU1_MEMBASE:
2683                         /* The cpu zero extends the result into 64 bits */
2684                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2685                         break;
2686                 case OP_LOADI1_MEMBASE:
2687                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2688                         break;
2689                 case OP_LOADU2_MEMBASE:
2690                         /* The cpu zero extends the result into 64 bits */
2691                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2692                         break;
2693                 case OP_LOADI2_MEMBASE:
2694                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2695                         break;
2696                 case OP_AMD64_LOADI8_MEMINDEX:
2697                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2698                         break;
2699                 case OP_LCONV_TO_I1:
2700                 case OP_ICONV_TO_I1:
2701                 case OP_SEXT_I1:
2702                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2703                         break;
2704                 case OP_LCONV_TO_I2:
2705                 case OP_ICONV_TO_I2:
2706                 case OP_SEXT_I2:
2707                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2708                         break;
2709                 case OP_LCONV_TO_U1:
2710                 case OP_ICONV_TO_U1:
2711                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2712                         break;
2713                 case OP_LCONV_TO_U2:
2714                 case OP_ICONV_TO_U2:
2715                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2716                         break;
2717                 case OP_ZEXT_I4:
2718                         /* Clean out the upper word */
2719                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2720                         break;
2721                 case OP_SEXT_I4:
2722                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2723                         break;
2724                 case OP_COMPARE:
2725                 case OP_LCOMPARE:
2726                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2727                         break;
2728                 case OP_COMPARE_IMM:
2729                 case OP_LCOMPARE_IMM:
2730                         g_assert (amd64_is_imm32 (ins->inst_imm));
2731                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2732                         break;
2733                 case OP_X86_COMPARE_REG_MEMBASE:
2734                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2735                         break;
2736                 case OP_X86_TEST_NULL:
2737                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2738                         break;
2739                 case OP_AMD64_TEST_NULL:
2740                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2741                         break;
2742
2743                 case OP_X86_ADD_REG_MEMBASE:
2744                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2745                         break;
2746                 case OP_X86_SUB_REG_MEMBASE:
2747                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2748                         break;
2749                 case OP_X86_AND_REG_MEMBASE:
2750                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2751                         break;
2752                 case OP_X86_OR_REG_MEMBASE:
2753                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2754                         break;
2755                 case OP_X86_XOR_REG_MEMBASE:
2756                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2757                         break;
2758
2759                 case OP_X86_ADD_MEMBASE_IMM:
2760                         /* FIXME: Make a 64 version too */
2761                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2762                         break;
2763                 case OP_X86_SUB_MEMBASE_IMM:
2764                         g_assert (amd64_is_imm32 (ins->inst_imm));
2765                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2766                         break;
2767                 case OP_X86_AND_MEMBASE_IMM:
2768                         g_assert (amd64_is_imm32 (ins->inst_imm));
2769                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2770                         break;
2771                 case OP_X86_OR_MEMBASE_IMM:
2772                         g_assert (amd64_is_imm32 (ins->inst_imm));
2773                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2774                         break;
2775                 case OP_X86_XOR_MEMBASE_IMM:
2776                         g_assert (amd64_is_imm32 (ins->inst_imm));
2777                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2778                         break;
2779                 case OP_X86_ADD_MEMBASE_REG:
2780                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2781                         break;
2782                 case OP_X86_SUB_MEMBASE_REG:
2783                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2784                         break;
2785                 case OP_X86_AND_MEMBASE_REG:
2786                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2787                         break;
2788                 case OP_X86_OR_MEMBASE_REG:
2789                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2790                         break;
2791                 case OP_X86_XOR_MEMBASE_REG:
2792                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2793                         break;
2794                 case OP_X86_INC_MEMBASE:
2795                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2796                         break;
2797                 case OP_X86_INC_REG:
2798                         amd64_inc_reg_size (code, ins->dreg, 4);
2799                         break;
2800                 case OP_X86_DEC_MEMBASE:
2801                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2802                         break;
2803                 case OP_X86_DEC_REG:
2804                         amd64_dec_reg_size (code, ins->dreg, 4);
2805                         break;
2806                 case OP_X86_MUL_REG_MEMBASE:
2807                 case OP_X86_MUL_MEMBASE_REG:
2808                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2809                         break;
2810                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2811                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2812                         break;
2813                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2814                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2815                         break;
2816                 case OP_AMD64_COMPARE_MEMBASE_REG:
2817                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2818                         break;
2819                 case OP_AMD64_COMPARE_MEMBASE_IMM:
2820                         g_assert (amd64_is_imm32 (ins->inst_imm));
2821                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2822                         break;
2823                 case OP_X86_COMPARE_MEMBASE8_IMM:
2824                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2825                         break;
2826                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2827                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2828                         break;
2829                 case OP_AMD64_COMPARE_REG_MEMBASE:
2830                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2831                         break;
2832
2833                 case OP_AMD64_ADD_REG_MEMBASE:
2834                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2835                         break;
2836                 case OP_AMD64_SUB_REG_MEMBASE:
2837                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2838                         break;
2839                 case OP_AMD64_AND_REG_MEMBASE:
2840                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2841                         break;
2842                 case OP_AMD64_OR_REG_MEMBASE:
2843                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2844                         break;
2845                 case OP_AMD64_XOR_REG_MEMBASE:
2846                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2847                         break;
2848
2849                 case OP_AMD64_ADD_MEMBASE_REG:
2850                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2851                         break;
2852                 case OP_AMD64_SUB_MEMBASE_REG:
2853                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2854                         break;
2855                 case OP_AMD64_AND_MEMBASE_REG:
2856                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2857                         break;
2858                 case OP_AMD64_OR_MEMBASE_REG:
2859                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2860                         break;
2861                 case OP_AMD64_XOR_MEMBASE_REG:
2862                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2863                         break;
2864
2865                 case OP_AMD64_ADD_MEMBASE_IMM:
2866                         g_assert (amd64_is_imm32 (ins->inst_imm));
2867                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2868                         break;
2869                 case OP_AMD64_SUB_MEMBASE_IMM:
2870                         g_assert (amd64_is_imm32 (ins->inst_imm));
2871                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2872                         break;
2873                 case OP_AMD64_AND_MEMBASE_IMM:
2874                         g_assert (amd64_is_imm32 (ins->inst_imm));
2875                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2876                         break;
2877                 case OP_AMD64_OR_MEMBASE_IMM:
2878                         g_assert (amd64_is_imm32 (ins->inst_imm));
2879                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2880                         break;
2881                 case OP_AMD64_XOR_MEMBASE_IMM:
2882                         g_assert (amd64_is_imm32 (ins->inst_imm));
2883                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2884                         break;
2885
2886                 case OP_BREAK:
2887                         amd64_breakpoint (code);
2888                         break;
2889                 case OP_RELAXED_NOP:
2890                         x86_prefix (code, X86_REP_PREFIX);
2891                         x86_nop (code);
2892                         break;
2893                 case OP_HARD_NOP:
2894                         x86_nop (code);
2895                         break;
2896                 case OP_NOP:
2897                 case OP_DUMMY_USE:
2898                 case OP_DUMMY_STORE:
2899                 case OP_NOT_REACHED:
2900                 case OP_NOT_NULL:
2901                         break;
2902                 case OP_ADDCC:
2903                 case OP_LADD:
2904                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2905                         break;
2906                 case OP_ADC:
2907                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2908                         break;
2909                 case OP_ADD_IMM:
2910                 case OP_LADD_IMM:
2911                         g_assert (amd64_is_imm32 (ins->inst_imm));
2912                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2913                         break;
2914                 case OP_ADC_IMM:
2915                         g_assert (amd64_is_imm32 (ins->inst_imm));
2916                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2917                         break;
2918                 case OP_SUBCC:
2919                 case OP_LSUB:
2920                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2921                         break;
2922                 case OP_SBB:
2923                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2924                         break;
2925                 case OP_SUB_IMM:
2926                 case OP_LSUB_IMM:
2927                         g_assert (amd64_is_imm32 (ins->inst_imm));
2928                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2929                         break;
2930                 case OP_SBB_IMM:
2931                         g_assert (amd64_is_imm32 (ins->inst_imm));
2932                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2933                         break;
2934                 case OP_LAND:
2935                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2936                         break;
2937                 case OP_AND_IMM:
2938                 case OP_LAND_IMM:
2939                         g_assert (amd64_is_imm32 (ins->inst_imm));
2940                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2941                         break;
2942                 case OP_LMUL:
2943                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2944                         break;
2945                 case OP_MUL_IMM:
2946                 case OP_LMUL_IMM:
2947                 case OP_IMUL_IMM: {
2948                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2949
2950                         switch (ins->inst_imm) {
2951                         case 2:
2952                                 /* MOV r1, r2 */
2953                                 /* ADD r1, r1 */
2954                                 if (ins->dreg != ins->sreg1)
2955                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2956                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2957                                 break;
2958                         case 3:
2959                                 /* LEA r1, [r2 + r2*2] */
2960                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2961                                 break;
2962                         case 5:
2963                                 /* LEA r1, [r2 + r2*4] */
2964                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2965                                 break;
2966                         case 6:
2967                                 /* LEA r1, [r2 + r2*2] */
2968                                 /* ADD r1, r1          */
2969                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2970                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2971                                 break;
2972                         case 9:
2973                                 /* LEA r1, [r2 + r2*8] */
2974                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2975                                 break;
2976                         case 10:
2977                                 /* LEA r1, [r2 + r2*4] */
2978                                 /* ADD r1, r1          */
2979                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2980                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2981                                 break;
2982                         case 12:
2983                                 /* LEA r1, [r2 + r2*2] */
2984                                 /* SHL r1, 2           */
2985                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2986                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2987                                 break;
2988                         case 25:
2989                                 /* LEA r1, [r2 + r2*4] */
2990                                 /* LEA r1, [r1 + r1*4] */
2991                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2992                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2993                                 break;
2994                         case 100:
2995                                 /* LEA r1, [r2 + r2*4] */
2996                                 /* SHL r1, 2           */
2997                                 /* LEA r1, [r1 + r1*4] */
2998                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2999                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3000                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3001                                 break;
3002                         default:
3003                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3004                                 break;
3005                         }
3006                         break;
3007                 }
3008                 case OP_LDIV:
3009                 case OP_LREM:
3010                         /* Regalloc magic makes the div/rem cases the same */
3011                         if (ins->sreg2 == AMD64_RDX) {
3012                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3013                                 amd64_cdq (code);
3014                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3015                         } else {
3016                                 amd64_cdq (code);
3017                                 amd64_div_reg (code, ins->sreg2, TRUE);
3018                         }
3019                         break;
3020                 case OP_LDIV_UN:
3021                 case OP_LREM_UN:
3022                         if (ins->sreg2 == AMD64_RDX) {
3023                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3024                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3025                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3026                         } else {
3027                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3028                                 amd64_div_reg (code, ins->sreg2, FALSE);
3029                         }
3030                         break;
3031                 case OP_IDIV:
3032                 case OP_IREM:
3033                         if (ins->sreg2 == AMD64_RDX) {
3034                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3035                                 amd64_cdq_size (code, 4);
3036                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3037                         } else {
3038                                 amd64_cdq_size (code, 4);
3039                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3040                         }
3041                         break;
3042                 case OP_IDIV_UN:
3043                 case OP_IREM_UN:
3044                         if (ins->sreg2 == AMD64_RDX) {
3045                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3046                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3047                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3048                         } else {
3049                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3050                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3051                         }
3052                         break;
3053                 case OP_IREM_IMM: {
3054                         int power = mono_is_power_of_two (ins->inst_imm);
3055
3056                         g_assert (ins->sreg1 == X86_EAX);
3057                         g_assert (ins->dreg == X86_EAX);
3058                         g_assert (power >= 0);
3059
3060                         /* Based on gcc code */
3061
3062                         /* Add compensation for negative dividents */
3063                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3064                         if (power > 1)
3065                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3066                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3067                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3068                         /* Compute remainder */
3069                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3070                         /* Remove compensation */
3071                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3072                         break;
3073                 }
3074                 case OP_LMUL_OVF:
3075                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3076                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3077                         break;
3078                 case OP_LOR:
3079                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3080                         break;
3081                 case OP_OR_IMM:
3082                 case OP_LOR_IMM:
3083                         g_assert (amd64_is_imm32 (ins->inst_imm));
3084                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3085                         break;
3086                 case OP_LXOR:
3087                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3088                         break;
3089                 case OP_XOR_IMM:
3090                 case OP_LXOR_IMM:
3091                         g_assert (amd64_is_imm32 (ins->inst_imm));
3092                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3093                         break;
3094                 case OP_LSHL:
3095                         g_assert (ins->sreg2 == AMD64_RCX);
3096                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3097                         break;
3098                 case OP_LSHR:
3099                         g_assert (ins->sreg2 == AMD64_RCX);
3100                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3101                         break;
3102                 case OP_SHR_IMM:
3103                         g_assert (amd64_is_imm32 (ins->inst_imm));
3104                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3105                         break;
3106                 case OP_LSHR_IMM:
3107                         g_assert (amd64_is_imm32 (ins->inst_imm));
3108                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3109                         break;
3110                 case OP_SHR_UN_IMM:
3111                         g_assert (amd64_is_imm32 (ins->inst_imm));
3112                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3113                         break;
3114                 case OP_LSHR_UN_IMM:
3115                         g_assert (amd64_is_imm32 (ins->inst_imm));
3116                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3117                         break;
3118                 case OP_LSHR_UN:
3119                         g_assert (ins->sreg2 == AMD64_RCX);
3120                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3121                         break;
3122                 case OP_SHL_IMM:
3123                         g_assert (amd64_is_imm32 (ins->inst_imm));
3124                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3125                         break;
3126                 case OP_LSHL_IMM:
3127                         g_assert (amd64_is_imm32 (ins->inst_imm));
3128                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3129                         break;
3130
3131                 case OP_IADDCC:
3132                 case OP_IADD:
3133                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3134                         break;
3135                 case OP_IADC:
3136                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3137                         break;
3138                 case OP_IADD_IMM:
3139                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3140                         break;
3141                 case OP_IADC_IMM:
3142                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3143                         break;
3144                 case OP_ISUBCC:
3145                 case OP_ISUB:
3146                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3147                         break;
3148                 case OP_ISBB:
3149                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3150                         break;
3151                 case OP_ISUB_IMM:
3152                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3153                         break;
3154                 case OP_ISBB_IMM:
3155                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3156                         break;
3157                 case OP_IAND:
3158                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3159                         break;
3160                 case OP_IAND_IMM:
3161                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3162                         break;
3163                 case OP_IOR:
3164                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3165                         break;
3166                 case OP_IOR_IMM:
3167                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3168                         break;
3169                 case OP_IXOR:
3170                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3171                         break;
3172                 case OP_IXOR_IMM:
3173                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3174                         break;
3175                 case OP_INEG:
3176                         amd64_neg_reg_size (code, ins->sreg1, 4);
3177                         break;
3178                 case OP_INOT:
3179                         amd64_not_reg_size (code, ins->sreg1, 4);
3180                         break;
3181                 case OP_ISHL:
3182                         g_assert (ins->sreg2 == AMD64_RCX);
3183                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3184                         break;
3185                 case OP_ISHR:
3186                         g_assert (ins->sreg2 == AMD64_RCX);
3187                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3188                         break;
3189                 case OP_ISHR_IMM:
3190                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3191                         break;
3192                 case OP_ISHR_UN_IMM:
3193                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3194                         break;
3195                 case OP_ISHR_UN:
3196                         g_assert (ins->sreg2 == AMD64_RCX);
3197                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3198                         break;
3199                 case OP_ISHL_IMM:
3200                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3201                         break;
3202                 case OP_IMUL:
3203                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3204                         break;
3205                 case OP_IMUL_OVF:
3206                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3207                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3208                         break;
3209                 case OP_IMUL_OVF_UN:
3210                 case OP_LMUL_OVF_UN: {
3211                         /* the mul operation and the exception check should most likely be split */
3212                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3213                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3214                         /*g_assert (ins->sreg2 == X86_EAX);
3215                         g_assert (ins->dreg == X86_EAX);*/
3216                         if (ins->sreg2 == X86_EAX) {
3217                                 non_eax_reg = ins->sreg1;
3218                         } else if (ins->sreg1 == X86_EAX) {
3219                                 non_eax_reg = ins->sreg2;
3220                         } else {
3221                                 /* no need to save since we're going to store to it anyway */
3222                                 if (ins->dreg != X86_EAX) {
3223                                         saved_eax = TRUE;
3224                                         amd64_push_reg (code, X86_EAX);
3225                                 }
3226                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3227                                 non_eax_reg = ins->sreg2;
3228                         }
3229                         if (ins->dreg == X86_EDX) {
3230                                 if (!saved_eax) {
3231                                         saved_eax = TRUE;
3232                                         amd64_push_reg (code, X86_EAX);
3233                                 }
3234                         } else {
3235                                 saved_edx = TRUE;
3236                                 amd64_push_reg (code, X86_EDX);
3237                         }
3238                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3239                         /* save before the check since pop and mov don't change the flags */
3240                         if (ins->dreg != X86_EAX)
3241                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3242                         if (saved_edx)
3243                                 amd64_pop_reg (code, X86_EDX);
3244                         if (saved_eax)
3245                                 amd64_pop_reg (code, X86_EAX);
3246                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3247                         break;
3248                 }
3249                 case OP_ICOMPARE:
3250                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3251                         break;
3252                 case OP_ICOMPARE_IMM:
3253                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3254                         break;
3255                 case OP_IBEQ:
3256                 case OP_IBLT:
3257                 case OP_IBGT:
3258                 case OP_IBGE:
3259                 case OP_IBLE:
3260                 case OP_LBEQ:
3261                 case OP_LBLT:
3262                 case OP_LBGT:
3263                 case OP_LBGE:
3264                 case OP_LBLE:
3265                 case OP_IBNE_UN:
3266                 case OP_IBLT_UN:
3267                 case OP_IBGT_UN:
3268                 case OP_IBGE_UN:
3269                 case OP_IBLE_UN:
3270                 case OP_LBNE_UN:
3271                 case OP_LBLT_UN:
3272                 case OP_LBGT_UN:
3273                 case OP_LBGE_UN:
3274                 case OP_LBLE_UN:
3275                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3276                         break;
3277
3278                 case OP_CMOV_IEQ:
3279                 case OP_CMOV_IGE:
3280                 case OP_CMOV_IGT:
3281                 case OP_CMOV_ILE:
3282                 case OP_CMOV_ILT:
3283                 case OP_CMOV_INE_UN:
3284                 case OP_CMOV_IGE_UN:
3285                 case OP_CMOV_IGT_UN:
3286                 case OP_CMOV_ILE_UN:
3287                 case OP_CMOV_ILT_UN:
3288                 case OP_CMOV_LEQ:
3289                 case OP_CMOV_LGE:
3290                 case OP_CMOV_LGT:
3291                 case OP_CMOV_LLE:
3292                 case OP_CMOV_LLT:
3293                 case OP_CMOV_LNE_UN:
3294                 case OP_CMOV_LGE_UN:
3295                 case OP_CMOV_LGT_UN:
3296                 case OP_CMOV_LLE_UN:
3297                 case OP_CMOV_LLT_UN:
3298                         g_assert (ins->dreg == ins->sreg1);
3299                         /* This needs to operate on 64 bit values */
3300                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3301                         break;
3302
3303                 case OP_LNOT:
3304                         amd64_not_reg (code, ins->sreg1);
3305                         break;
3306                 case OP_LNEG:
3307                         amd64_neg_reg (code, ins->sreg1);
3308                         break;
3309
3310                 case OP_ICONST:
3311                 case OP_I8CONST:
3312                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3313                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3314                         else
3315                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3316                         break;
3317                 case OP_AOTCONST:
3318                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3319                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3320                         break;
3321                 case OP_JUMP_TABLE:
3322                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3323                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3324                         break;
3325                 case OP_MOVE:
3326                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3327                         break;
3328                 case OP_AMD64_SET_XMMREG_R4: {
3329                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3330                         break;
3331                 }
3332                 case OP_AMD64_SET_XMMREG_R8: {
3333                         if (ins->dreg != ins->sreg1)
3334                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3335                         break;
3336                 }
3337                 case OP_TAILCALL: {
3338                         /*
3339                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3340                          * Keep in sync with the code in emit_epilog.
3341                          */
3342                         int pos = 0, i;
3343
3344                         /* FIXME: no tracing support... */
3345                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3346                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3347
3348                         g_assert (!cfg->method->save_lmf);
3349
3350                         if (cfg->arch.omit_fp) {
3351                                 guint32 save_offset = 0;
3352                                 /* Pop callee-saved registers */
3353                                 for (i = 0; i < AMD64_NREG; ++i)
3354                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3355                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3356                                                 save_offset += 8;
3357                                         }
3358                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3359                         }
3360                         else {
3361                                 for (i = 0; i < AMD64_NREG; ++i)
3362                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3363                                                 pos -= sizeof (gpointer);
3364
3365                                 if (pos)
3366                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3367
3368                                 /* Pop registers in reverse order */
3369                                 for (i = AMD64_NREG - 1; i > 0; --i)
3370                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3371                                                 amd64_pop_reg (code, i);
3372                                         }
3373
3374                                 amd64_leave (code);
3375                         }
3376
3377                         offset = code - cfg->native_code;
3378                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3379                         if (cfg->compile_aot)
3380                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3381                         else
3382                                 amd64_set_reg_template (code, AMD64_R11);
3383                         amd64_jump_reg (code, AMD64_R11);
3384                         break;
3385                 }
3386                 case OP_CHECK_THIS:
3387                         /* ensure ins->sreg1 is not NULL */
3388                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3389                         break;
3390                 case OP_ARGLIST: {
3391                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3392                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3393                         break;
3394                 }
3395                 case OP_CALL:
3396                 case OP_FCALL:
3397                 case OP_LCALL:
3398                 case OP_VCALL:
3399                 case OP_VCALL2:
3400                 case OP_VOIDCALL:
3401                         call = (MonoCallInst*)ins;
3402                         /*
3403                          * The AMD64 ABI forces callers to know about varargs.
3404                          */
3405                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3406                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3407                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3408                                 /*
3409                                  * Since the unmanaged calling convention doesn't contain a
3410                                  * 'vararg' entry, we have to treat every pinvoke call as a
3411                                  * potential vararg call.
3412                                  */
3413                                 guint32 nregs, i;
3414                                 nregs = 0;
3415                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3416                                         if (call->used_fregs & (1 << i))
3417                                                 nregs ++;
3418                                 if (!nregs)
3419                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3420                                 else
3421                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3422                         }
3423
3424                         if (ins->flags & MONO_INST_HAS_METHOD)
3425                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3426                         else
3427                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3428                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3429                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3430                         code = emit_move_return_value (cfg, ins, code);
3431                         break;
3432                 case OP_FCALL_REG:
3433                 case OP_LCALL_REG:
3434                 case OP_VCALL_REG:
3435                 case OP_VCALL2_REG:
3436                 case OP_VOIDCALL_REG:
3437                 case OP_CALL_REG:
3438                         call = (MonoCallInst*)ins;
3439
3440                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3441                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3442                                 ins->sreg1 = AMD64_R11;
3443                         }
3444
3445                         /*
3446                          * The AMD64 ABI forces callers to know about varargs.
3447                          */
3448                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3449                                 if (ins->sreg1 == AMD64_RAX) {
3450                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3451                                         ins->sreg1 = AMD64_R11;
3452                                 }
3453                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3454                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3455                                 /*
3456                                  * Since the unmanaged calling convention doesn't contain a
3457                                  * 'vararg' entry, we have to treat every pinvoke call as a
3458                                  * potential vararg call.
3459                                  */
3460                                 guint32 nregs, i;
3461                                 nregs = 0;
3462                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3463                                         if (call->used_fregs & (1 << i))
3464                                                 nregs ++;
3465                                 if (ins->sreg1 == AMD64_RAX) {
3466                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3467                                         ins->sreg1 = AMD64_R11;
3468                                 }
3469                                 if (!nregs)
3470                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3471                                 else
3472                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3473                         }
3474
3475                         amd64_call_reg (code, ins->sreg1);
3476                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3477                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3478                         code = emit_move_return_value (cfg, ins, code);
3479                         break;
3480                 case OP_FCALL_MEMBASE:
3481                 case OP_LCALL_MEMBASE:
3482                 case OP_VCALL_MEMBASE:
3483                 case OP_VCALL2_MEMBASE:
3484                 case OP_VOIDCALL_MEMBASE:
3485                 case OP_CALL_MEMBASE:
3486                         call = (MonoCallInst*)ins;
3487
3488                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3489                                 /*
3490                                  * Can't use R11 because it is clobbered by the trampoline
3491                                  * code, and the reg value is needed by get_vcall_slot_addr.
3492                                  */
3493                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3494                                 ins->sreg1 = AMD64_RAX;
3495                         }
3496
3497                         if (call->method && ins->inst_offset < 0) {
3498                                 gssize val;
3499
3500                                 /*
3501                                  * This is a possible IMT call so save the IMT method in the proper
3502                                  * register. We don't use the generic code in method-to-ir.c, because
3503                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3504                                  * maintain control over the layout of the code.
3505                                  * Also put the base reg in %rax to simplify find_imt_method ().
3506                                  */
3507                                 if (ins->sreg1 != AMD64_RAX) {
3508                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3509                                         ins->sreg1 = AMD64_RAX;
3510                                 }
3511                                 val = (gssize)(gpointer)call->method;
3512
3513                                 // FIXME: Generics sharing
3514 #if 0
3515                                 if ((((guint64)val) >> 32) == 0)
3516                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3517                                 else
3518                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3519 #endif
3520                         }
3521
3522                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3523                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3524                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3525                         code = emit_move_return_value (cfg, ins, code);
3526                         break;
3527                 case OP_AMD64_SAVE_SP_TO_LMF:
3528                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3529                         break;
3530                 case OP_X86_PUSH:
3531                         amd64_push_reg (code, ins->sreg1);
3532                         break;
3533                 case OP_X86_PUSH_IMM:
3534                         g_assert (amd64_is_imm32 (ins->inst_imm));
3535                         amd64_push_imm (code, ins->inst_imm);
3536                         break;
3537                 case OP_X86_PUSH_MEMBASE:
3538                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3539                         break;
3540                 case OP_X86_PUSH_OBJ: {
3541                         int size = ALIGN_TO (ins->inst_imm, 8);
3542                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3543                         amd64_push_reg (code, AMD64_RDI);
3544                         amd64_push_reg (code, AMD64_RSI);
3545                         amd64_push_reg (code, AMD64_RCX);
3546                         if (ins->inst_offset)
3547                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3548                         else
3549                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3550                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3551                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3552                         amd64_cld (code);
3553                         amd64_prefix (code, X86_REP_PREFIX);
3554                         amd64_movsd (code);
3555                         amd64_pop_reg (code, AMD64_RCX);
3556                         amd64_pop_reg (code, AMD64_RSI);
3557                         amd64_pop_reg (code, AMD64_RDI);
3558                         break;
3559                 }
3560                 case OP_X86_LEA:
3561                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3562                         break;
3563                 case OP_X86_LEA_MEMBASE:
3564                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3565                         break;
3566                 case OP_X86_XCHG:
3567                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3568                         break;
3569                 case OP_LOCALLOC:
3570                         /* keep alignment */
3571                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3572                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3573                         code = mono_emit_stack_alloc (code, ins);
3574                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3575                         break;
3576                 case OP_LOCALLOC_IMM: {
3577                         guint32 size = ins->inst_imm;
3578                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3579
3580                         if (ins->flags & MONO_INST_INIT) {
3581                                 if (size < 64) {
3582                                         int i;
3583
3584                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3585                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3586
3587                                         for (i = 0; i < size; i += 8)
3588                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3589                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3590                                 } else {
3591                                         amd64_mov_reg_imm (code, ins->dreg, size);
3592                                         ins->sreg1 = ins->dreg;
3593
3594                                         code = mono_emit_stack_alloc (code, ins);
3595                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3596                                 }
3597                         } else {
3598                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3599                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3600                         }
3601                         break;
3602                 }
3603                 case OP_THROW: {
3604                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3605                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3606                                              (gpointer)"mono_arch_throw_exception", FALSE);
3607                         break;
3608                 }
3609                 case OP_RETHROW: {
3610                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3611                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3612                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
3613                         break;
3614                 }
3615                 case OP_CALL_HANDLER:
3616                         /* Align stack */
3617                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3618                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3619                         amd64_call_imm (code, 0);
3620                         /* Restore stack alignment */
3621                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3622                         break;
3623                 case OP_START_HANDLER: {
3624                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3625                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3626                         break;
3627                 }
3628                 case OP_ENDFINALLY: {
3629                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3630                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3631                         amd64_ret (code);
3632                         break;
3633                 }
3634                 case OP_ENDFILTER: {
3635                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3636                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3637                         /* The local allocator will put the result into RAX */
3638                         amd64_ret (code);
3639                         break;
3640                 }
3641
3642                 case OP_LABEL:
3643                         ins->inst_c0 = code - cfg->native_code;
3644                         break;
3645                 case OP_BR:
3646                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3647                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3648                         //break;
3649                         if (ins->flags & MONO_INST_BRLABEL) {
3650                                 if (ins->inst_i0->inst_c0) {
3651                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3652                                 } else {
3653                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3654                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3655                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3656                                                 x86_jump8 (code, 0);
3657                                         else
3658                                                 x86_jump32 (code, 0);
3659                                 }
3660                         } else {
3661                                 if (ins->inst_target_bb->native_offset) {
3662                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3663                                 } else {
3664                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3665                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3666                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3667                                                 x86_jump8 (code, 0);
3668                                         else
3669                                                 x86_jump32 (code, 0);
3670                                 }
3671                         }
3672                         break;
3673                 case OP_BR_REG:
3674                         amd64_jump_reg (code, ins->sreg1);
3675                         break;
3676                 case OP_CEQ:
3677                 case OP_LCEQ:
3678                 case OP_ICEQ:
3679                 case OP_CLT:
3680                 case OP_LCLT:
3681                 case OP_ICLT:
3682                 case OP_CGT:
3683                 case OP_ICGT:
3684                 case OP_LCGT:
3685                 case OP_CLT_UN:
3686                 case OP_LCLT_UN:
3687                 case OP_ICLT_UN:
3688                 case OP_CGT_UN:
3689                 case OP_LCGT_UN:
3690                 case OP_ICGT_UN:
3691                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3692                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3693                         break;
3694                 case OP_COND_EXC_EQ:
3695                 case OP_COND_EXC_NE_UN:
3696                 case OP_COND_EXC_LT:
3697                 case OP_COND_EXC_LT_UN:
3698                 case OP_COND_EXC_GT:
3699                 case OP_COND_EXC_GT_UN:
3700                 case OP_COND_EXC_GE:
3701                 case OP_COND_EXC_GE_UN:
3702                 case OP_COND_EXC_LE:
3703                 case OP_COND_EXC_LE_UN:
3704                 case OP_COND_EXC_IEQ:
3705                 case OP_COND_EXC_INE_UN:
3706                 case OP_COND_EXC_ILT:
3707                 case OP_COND_EXC_ILT_UN:
3708                 case OP_COND_EXC_IGT:
3709                 case OP_COND_EXC_IGT_UN:
3710                 case OP_COND_EXC_IGE:
3711                 case OP_COND_EXC_IGE_UN:
3712                 case OP_COND_EXC_ILE:
3713                 case OP_COND_EXC_ILE_UN:
3714                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3715                         break;
3716                 case OP_COND_EXC_OV:
3717                 case OP_COND_EXC_NO:
3718                 case OP_COND_EXC_C:
3719                 case OP_COND_EXC_NC:
3720                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3721                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3722                         break;
3723                 case OP_COND_EXC_IOV:
3724                 case OP_COND_EXC_INO:
3725                 case OP_COND_EXC_IC:
3726                 case OP_COND_EXC_INC:
3727                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3728                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3729                         break;
3730
3731                 /* floating point opcodes */
3732                 case OP_R8CONST: {
3733                         double d = *(double *)ins->inst_p0;
3734
3735                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
3736                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3737                         }
3738                         else {
3739                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3740                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3741                         }
3742                         break;
3743                 }
3744                 case OP_R4CONST: {
3745                         float f = *(float *)ins->inst_p0;
3746
3747                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
3748                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3749                         }
3750                         else {
3751                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3752                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3753                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3754                         }
3755                         break;
3756                 }
3757                 case OP_STORER8_MEMBASE_REG:
3758                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3759                         break;
3760                 case OP_LOADR8_SPILL_MEMBASE:
3761                         g_assert_not_reached ();
3762                         break;
3763                 case OP_LOADR8_MEMBASE:
3764                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3765                         break;
3766                 case OP_STORER4_MEMBASE_REG:
3767                         /* This requires a double->single conversion */
3768                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3769                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3770                         break;
3771                 case OP_LOADR4_MEMBASE:
3772                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3773                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3774                         break;
3775                 case OP_ICONV_TO_R4: /* FIXME: change precision */
3776                 case OP_ICONV_TO_R8:
3777                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3778                         break;
3779                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3780                 case OP_LCONV_TO_R8:
3781                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3782                         break;
3783                 case OP_FCONV_TO_R4:
3784                         /* FIXME: nothing to do ?? */
3785                         break;
3786                 case OP_FCONV_TO_I1:
3787                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3788                         break;
3789                 case OP_FCONV_TO_U1:
3790                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3791                         break;
3792                 case OP_FCONV_TO_I2:
3793                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3794                         break;
3795                 case OP_FCONV_TO_U2:
3796                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3797                         break;
3798                 case OP_FCONV_TO_U4:
3799                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3800                         break;
3801                 case OP_FCONV_TO_I4:
3802                 case OP_FCONV_TO_I:
3803                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3804                         break;
3805                 case OP_FCONV_TO_I8:
3806                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3807                         break;
3808                 case OP_LCONV_TO_R_UN: {
3809                         guint8 *br [2];
3810
3811                         /* Based on gcc code */
3812                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3813                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3814
3815                         /* Positive case */
3816                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3817                         br [1] = code; x86_jump8 (code, 0);
3818                         amd64_patch (br [0], code);
3819
3820                         /* Negative case */
3821                         /* Save to the red zone */
3822                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3823                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3824                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3825                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3826                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3827                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3828                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3829                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3830                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3831                         /* Restore */
3832                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3833                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3834                         amd64_patch (br [1], code);
3835                         break;
3836                 }
3837                 case OP_LCONV_TO_OVF_U4:
3838                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3839                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3840                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3841                         break;
3842                 case OP_LCONV_TO_OVF_I4_UN:
3843                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3844                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3845                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3846                         break;
3847                 case OP_FMOVE:
3848                         if (ins->dreg != ins->sreg1)
3849                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3850                         break;
3851                 case OP_FADD:
3852                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3853                         break;
3854                 case OP_FSUB:
3855                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3856                         break;
3857                 case OP_FMUL:
3858                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3859                         break;
3860                 case OP_FDIV:
3861                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3862                         break;
3863                 case OP_FNEG: {
3864                         static double r8_0 = -0.0;
3865
3866                         g_assert (ins->sreg1 == ins->dreg);
3867
3868                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3869                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3870                         break;
3871                 }
3872                 case OP_SIN:
3873                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3874                         break;
3875                 case OP_COS:
3876                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3877                         break;
3878                 case OP_ABS: {
3879                         static guint64 d = 0x7fffffffffffffffUL;
3880
3881                         g_assert (ins->sreg1 == ins->dreg);
3882
3883                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
3884                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3885                         break;
3886                 }
3887                 case OP_SQRT:
3888                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3889                         break;
3890                 case OP_IMIN:
3891                         g_assert (cfg->opt & MONO_OPT_CMOV);
3892                         g_assert (ins->dreg == ins->sreg1);
3893                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3894                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3895                         break;
3896                 case OP_IMIN_UN:
3897                         g_assert (cfg->opt & MONO_OPT_CMOV);
3898                         g_assert (ins->dreg == ins->sreg1);
3899                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3900                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
3901                         break;
3902                 case OP_IMAX:
3903                         g_assert (cfg->opt & MONO_OPT_CMOV);
3904                         g_assert (ins->dreg == ins->sreg1);
3905                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3906                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3907                         break;
3908                 case OP_IMAX_UN:
3909                         g_assert (cfg->opt & MONO_OPT_CMOV);
3910                         g_assert (ins->dreg == ins->sreg1);
3911                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3912                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
3913                         break;
3914                 case OP_LMIN:
3915                         g_assert (cfg->opt & MONO_OPT_CMOV);
3916                         g_assert (ins->dreg == ins->sreg1);
3917                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3918                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3919                         break;
3920                 case OP_LMIN_UN:
3921                         g_assert (cfg->opt & MONO_OPT_CMOV);
3922                         g_assert (ins->dreg == ins->sreg1);
3923                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3924                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3925                         break;
3926                 case OP_LMAX:
3927                         g_assert (cfg->opt & MONO_OPT_CMOV);
3928                         g_assert (ins->dreg == ins->sreg1);
3929                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3930                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3931                         break;
3932                 case OP_LMAX_UN:
3933                         g_assert (cfg->opt & MONO_OPT_CMOV);
3934                         g_assert (ins->dreg == ins->sreg1);
3935                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3936                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3937                         break;
3938                 case OP_X86_FPOP:
3939                         break;
3940                 case OP_FCOMPARE:
3941                         /*
3942                          * The two arguments are swapped because the fbranch instructions
3943                          * depend on this for the non-sse case to work.
3944                          */
3945                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3946                         break;
3947                 case OP_FCEQ: {
3948                         /* zeroing the register at the start results in
3949                          * shorter and faster code (we can also remove the widening op)
3950                          */
3951                         guchar *unordered_check;
3952                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3953                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3954                         unordered_check = code;
3955                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3956                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3957                         amd64_patch (unordered_check, code);
3958                         break;
3959                 }
3960                 case OP_FCLT:
3961                 case OP_FCLT_UN:
3962                         /* zeroing the register at the start results in
3963                          * shorter and faster code (we can also remove the widening op)
3964                          */
3965                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3966                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3967                         if (ins->opcode == OP_FCLT_UN) {
3968                                 guchar *unordered_check = code;
3969                                 guchar *jump_to_end;
3970                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3971                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3972                                 jump_to_end = code;
3973                                 x86_jump8 (code, 0);
3974                                 amd64_patch (unordered_check, code);
3975                                 amd64_inc_reg (code, ins->dreg);
3976                                 amd64_patch (jump_to_end, code);
3977                         } else {
3978                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3979                         }
3980                         break;
3981                 case OP_FCGT:
3982                 case OP_FCGT_UN: {
3983                         /* zeroing the register at the start results in
3984                          * shorter and faster code (we can also remove the widening op)
3985                          */
3986                         guchar *unordered_check;
3987                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3988                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3989                         if (ins->opcode == OP_FCGT) {
3990                                 unordered_check = code;
3991                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3992                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3993                                 amd64_patch (unordered_check, code);
3994                         } else {
3995                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3996                         }
3997                         break;
3998                 }
3999                 case OP_FCLT_MEMBASE:
4000                 case OP_FCGT_MEMBASE:
4001                 case OP_FCLT_UN_MEMBASE:
4002                 case OP_FCGT_UN_MEMBASE:
4003                 case OP_FCEQ_MEMBASE: {
4004                         guchar *unordered_check, *jump_to_end;
4005                         int x86_cond;
4006
4007                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4008                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4009
4010                         switch (ins->opcode) {
4011                         case OP_FCEQ_MEMBASE:
4012                                 x86_cond = X86_CC_EQ;
4013                                 break;
4014                         case OP_FCLT_MEMBASE:
4015                         case OP_FCLT_UN_MEMBASE:
4016                                 x86_cond = X86_CC_LT;
4017                                 break;
4018                         case OP_FCGT_MEMBASE:
4019                         case OP_FCGT_UN_MEMBASE:
4020                                 x86_cond = X86_CC_GT;
4021                                 break;
4022                         default:
4023                                 g_assert_not_reached ();
4024                         }
4025
4026                         unordered_check = code;
4027                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4028                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4029
4030                         switch (ins->opcode) {
4031                         case OP_FCEQ_MEMBASE:
4032                         case OP_FCLT_MEMBASE:
4033                         case OP_FCGT_MEMBASE:
4034                                 amd64_patch (unordered_check, code);
4035                                 break;
4036                         case OP_FCLT_UN_MEMBASE:
4037                         case OP_FCGT_UN_MEMBASE:
4038                                 jump_to_end = code;
4039                                 x86_jump8 (code, 0);
4040                                 amd64_patch (unordered_check, code);
4041                                 amd64_inc_reg (code, ins->dreg);
4042                                 amd64_patch (jump_to_end, code);
4043                                 break;
4044                         default:
4045                                 break;
4046                         }
4047                         break;
4048                 }
4049                 case OP_FBEQ: {
4050                         guchar *jump = code;
4051                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4052                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4053                         amd64_patch (jump, code);
4054                         break;
4055                 }
4056                 case OP_FBNE_UN:
4057                         /* Branch if C013 != 100 */
4058                         /* branch if !ZF or (PF|CF) */
4059                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4060                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4061                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4062                         break;
4063                 case OP_FBLT:
4064                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4065                         break;
4066                 case OP_FBLT_UN:
4067                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4068                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4069                         break;
4070                 case OP_FBGT:
4071                 case OP_FBGT_UN:
4072                         if (ins->opcode == OP_FBGT) {
4073                                 guchar *br1;
4074
4075                                 /* skip branch if C1=1 */
4076                                 br1 = code;
4077                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4078                                 /* branch if (C0 | C3) = 1 */
4079                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4080                                 amd64_patch (br1, code);
4081                                 break;
4082                         } else {
4083                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4084                         }
4085                         break;
4086                 case OP_FBGE: {
4087                         /* Branch if C013 == 100 or 001 */
4088                         guchar *br1;
4089
4090                         /* skip branch if C1=1 */
4091                         br1 = code;
4092                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4093                         /* branch if (C0 | C3) = 1 */
4094                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4095                         amd64_patch (br1, code);
4096                         break;
4097                 }
4098                 case OP_FBGE_UN:
4099                         /* Branch if C013 == 000 */
4100                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4101                         break;
4102                 case OP_FBLE: {
4103                         /* Branch if C013=000 or 100 */
4104                         guchar *br1;
4105
4106                         /* skip branch if C1=1 */
4107                         br1 = code;
4108                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4109                         /* branch if C0=0 */
4110                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4111                         amd64_patch (br1, code);
4112                         break;
4113                 }
4114                 case OP_FBLE_UN:
4115                         /* Branch if C013 != 001 */
4116                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4117                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4118                         break;
4119                 case OP_CKFINITE:
4120                         /* Transfer value to the fp stack */
4121                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4122                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4123                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4124
4125                         amd64_push_reg (code, AMD64_RAX);
4126                         amd64_fxam (code);
4127                         amd64_fnstsw (code);
4128                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4129                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4130                         amd64_pop_reg (code, AMD64_RAX);
4131                         amd64_fstp (code, 0);
4132                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4133                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4134                         break;
4135                 case OP_TLS_GET: {
4136                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4137                         break;
4138                 }
4139                 case OP_MEMORY_BARRIER: {
4140                         /* Not needed on amd64 */
4141                         break;
4142                 }
4143                 case OP_ATOMIC_ADD_I4:
4144                 case OP_ATOMIC_ADD_I8: {
4145                         int dreg = ins->dreg;
4146                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4147
4148                         if (dreg == ins->inst_basereg)
4149                                 dreg = AMD64_R11;
4150
4151                         if (dreg != ins->sreg2)
4152                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4153
4154                         x86_prefix (code, X86_LOCK_PREFIX);
4155                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4156
4157                         if (dreg != ins->dreg)
4158                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4159
4160                         break;
4161                 }
4162                 case OP_ATOMIC_ADD_NEW_I4:
4163                 case OP_ATOMIC_ADD_NEW_I8: {
4164                         int dreg = ins->dreg;
4165                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4166
4167                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4168                                 dreg = AMD64_R11;
4169
4170                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4171                         amd64_prefix (code, X86_LOCK_PREFIX);
4172                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4173                         /* dreg contains the old value, add with sreg2 value */
4174                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4175
4176                         if (ins->dreg != dreg)
4177                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4178
4179                         break;
4180                 }
4181                 case OP_ATOMIC_EXCHANGE_I4:
4182                 case OP_ATOMIC_EXCHANGE_I8:
4183                 case OP_ATOMIC_CAS_IMM_I4: {
4184                         guchar *br[2];
4185                         int sreg2 = ins->sreg2;
4186                         int breg = ins->inst_basereg;
4187                         guint32 size;
4188                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4189
4190                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4191                                 size = 8;
4192                         else
4193                                 size = 4;
4194
4195                         /*
4196                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4197                          * an explanation of how this works.
4198                          */
4199
4200                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4201                          * hack to overcome limits in x86 reg allocator
4202                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4203                          */
4204                         g_assert (ins->dreg == AMD64_RAX);
4205
4206                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4207                                 /* Highly unlikely, but possible */
4208                                 need_push = TRUE;
4209
4210                         /* The pushes invalidate rsp */
4211                         if ((breg == AMD64_RAX) || need_push) {
4212                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4213                                 breg = AMD64_R11;
4214                         }
4215
4216                         /* We need the EAX reg for the comparand */
4217                         if (ins->sreg2 == AMD64_RAX) {
4218                                 if (breg != AMD64_R11) {
4219                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4220                                         sreg2 = AMD64_R11;
4221                                 } else {
4222                                         g_assert (need_push);
4223                                         amd64_push_reg (code, AMD64_RDX);
4224                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4225                                         sreg2 = AMD64_RDX;
4226                                         rdx_pushed = TRUE;
4227                                 }
4228                         }
4229
4230                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4231                                 if (ins->backend.data == NULL)
4232                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4233                                 else
4234                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4235
4236                                 amd64_prefix (code, X86_LOCK_PREFIX);
4237                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4238                         } else {
4239                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4240
4241                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4242                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4243                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4244                                 amd64_patch (br [1], br [0]);
4245                         }
4246
4247                         if (rdx_pushed)
4248                                 amd64_pop_reg (code, AMD64_RDX);
4249
4250                         break;
4251                 }
4252                 case OP_LIVERANGE_START: {
4253                         if (cfg->verbose_level > 1)
4254                                 printf ("R%d START=0x%x\n", cfg->varinfo [ins->inst_c0]->dreg, (int)(code - cfg->native_code));
4255                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4256                         break;
4257                 }
4258                 case OP_LIVERANGE_END: {
4259                         if (cfg->verbose_level > 1)
4260                                 printf ("R%d END=0x%x\n", cfg->varinfo [ins->inst_c0]->dreg, (int)(code - cfg->native_code));
4261                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4262                         break;
4263                 }
4264                 default:
4265                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4266                         g_assert_not_reached ();
4267                 }
4268
4269                 if ((code - cfg->native_code - offset) > max_len) {
4270                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4271                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4272                         g_assert_not_reached ();
4273                 }
4274
4275                 cpos += max_len;
4276
4277                 last_ins = ins;
4278                 last_offset = offset;
4279         }
4280
4281         cfg->code_len = code - cfg->native_code;
4282 }
4283
4284 #endif /* DISABLE_JIT */
4285
4286 void
4287 mono_arch_register_lowlevel_calls (void)
4288 {
4289         /* The signature doesn't matter */
4290         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4291 }
4292
4293 void
4294 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4295 {
4296         MonoJumpInfo *patch_info;
4297         gboolean compile_aot = !run_cctors;
4298
4299         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4300                 unsigned char *ip = patch_info->ip.i + code;
4301                 unsigned char *target;
4302
4303                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4304
4305                 if (compile_aot) {
4306                         switch (patch_info->type) {
4307                         case MONO_PATCH_INFO_BB:
4308                         case MONO_PATCH_INFO_LABEL:
4309                                 break;
4310                         default:
4311                                 /* No need to patch these */
4312                                 continue;
4313                         }
4314                 }
4315
4316                 switch (patch_info->type) {
4317                 case MONO_PATCH_INFO_NONE:
4318                         continue;
4319                 case MONO_PATCH_INFO_METHOD_REL:
4320                 case MONO_PATCH_INFO_R8:
4321                 case MONO_PATCH_INFO_R4:
4322                         g_assert_not_reached ();
4323                         continue;
4324                 case MONO_PATCH_INFO_BB:
4325                         break;
4326                 default:
4327                         break;
4328                 }
4329
4330                 /*
4331                  * Debug code to help track down problems where the target of a near call is
4332                  * is not valid.
4333                  */
4334                 if (amd64_is_near_call (ip)) {
4335                         gint64 disp = (guint8*)target - (guint8*)ip;
4336
4337                         if (!amd64_is_imm32 (disp)) {
4338                                 printf ("TYPE: %d\n", patch_info->type);
4339                                 switch (patch_info->type) {
4340                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4341                                         printf ("V: %s\n", patch_info->data.name);
4342                                         break;
4343                                 case MONO_PATCH_INFO_METHOD_JUMP:
4344                                 case MONO_PATCH_INFO_METHOD:
4345                                         printf ("V: %s\n", patch_info->data.method->name);
4346                                         break;
4347                                 default:
4348                                         break;
4349                                 }
4350                         }
4351                 }
4352
4353                 amd64_patch (ip, (gpointer)target);
4354         }
4355 }
4356
4357 static int
4358 get_max_epilog_size (MonoCompile *cfg)
4359 {
4360         int max_epilog_size = 16;
4361
4362         if (cfg->method->save_lmf)
4363                 max_epilog_size += 256;
4364
4365         if (mono_jit_trace_calls != NULL)
4366                 max_epilog_size += 50;
4367
4368         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4369                 max_epilog_size += 50;
4370
4371         max_epilog_size += (AMD64_NREG * 2);
4372
4373         return max_epilog_size;
4374 }
4375
4376 /*
4377  * This macro is used for testing whenever the unwinder works correctly at every point
4378  * where an async exception can happen.
4379  */
4380 /* This will generate a SIGSEGV at the given point in the code */
4381 #define async_exc_point(code) do { \
4382     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4383          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4384              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4385          cfg->arch.async_point_count ++; \
4386     } \
4387 } while (0)
4388
4389 guint8 *
4390 mono_arch_emit_prolog (MonoCompile *cfg)
4391 {
4392         MonoMethod *method = cfg->method;
4393         MonoBasicBlock *bb;
4394         MonoMethodSignature *sig;
4395         MonoInst *ins;
4396         int alloc_size, pos, max_offset, i, cfa_offset, quad, max_epilog_size;
4397         guint8 *code;
4398         CallInfo *cinfo;
4399         gint32 lmf_offset = cfg->arch.lmf_offset;
4400         gboolean args_clobbered = FALSE;
4401         gboolean trace = FALSE;
4402
4403         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4404
4405         code = cfg->native_code = g_malloc (cfg->code_size);
4406
4407         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4408                 trace = TRUE;
4409
4410         /* Amount of stack space allocated by register saving code */
4411         pos = 0;
4412
4413         /* Offset between RSP and the CFA */
4414         cfa_offset = 0;
4415
4416         /*
4417          * The prolog consists of the following parts:
4418          * FP present:
4419          * - push rbp, mov rbp, rsp
4420          * - save callee saved regs using pushes
4421          * - allocate frame
4422          * - save rgctx if needed
4423          * - save lmf if needed
4424          * FP not present:
4425          * - allocate frame
4426          * - save rgctx if needed
4427          * - save lmf if needed
4428          * - save callee saved regs using moves
4429          */
4430
4431         // CFA = sp + 8
4432         cfa_offset = 8;
4433         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4434         // IP saved at CFA - 8
4435         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4436         async_exc_point (code);
4437
4438         if (!cfg->arch.omit_fp) {
4439                 amd64_push_reg (code, AMD64_RBP);
4440                 cfa_offset += 8;
4441                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4442                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4443                 async_exc_point (code);
4444 #ifdef PLATFORM_WIN32
4445                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4446 #endif
4447
4448                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4449                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4450                 async_exc_point (code);
4451 #ifdef PLATFORM_WIN32
4452                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4453 #endif
4454         }
4455
4456         /* Save callee saved registers */
4457         if (!cfg->arch.omit_fp && !method->save_lmf) {
4458                 int offset = cfa_offset;
4459
4460                 for (i = 0; i < AMD64_NREG; ++i)
4461                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4462                                 amd64_push_reg (code, i);
4463                                 pos += sizeof (gpointer);
4464                                 offset += 8;
4465                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4466                                 async_exc_point (code);
4467                         }
4468         }
4469
4470         if (cfg->arch.omit_fp) {
4471                 /*
4472                  * On enter, the stack is misaligned by the the pushing of the return
4473                  * address. It is either made aligned by the pushing of %rbp, or by
4474                  * this.
4475                  */
4476                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4477                 if ((alloc_size % 16) == 0)
4478                         alloc_size += 8;
4479         } else {
4480                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4481
4482                 alloc_size -= pos;
4483         }
4484
4485         cfg->arch.stack_alloc_size = alloc_size;
4486
4487         /* Allocate stack frame */
4488         if (alloc_size) {
4489                 /* See mono_emit_stack_alloc */
4490 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4491                 guint32 remaining_size = alloc_size;
4492                 while (remaining_size >= 0x1000) {
4493                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4494                         if (cfg->arch.omit_fp) {
4495                                 cfa_offset += 0x1000;
4496                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4497                         }
4498                         async_exc_point (code);
4499 #ifdef PLATFORM_WIN32
4500                         if (cfg->arch.omit_fp)
4501                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4502 #endif
4503
4504                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4505                         remaining_size -= 0x1000;
4506                 }
4507                 if (remaining_size) {
4508                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4509                         if (cfg->arch.omit_fp) {
4510                                 cfa_offset += remaining_size;
4511                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4512                                 async_exc_point (code);
4513                         }
4514 #ifdef PLATFORM_WIN32
4515                         if (cfg->arch.omit_fp)
4516                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4517 #endif
4518                 }
4519 #else
4520                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4521                 if (cfg->arch.omit_fp) {
4522                         cfa_offset += alloc_size;
4523                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4524                         async_exc_point (code);
4525                 }
4526 #endif
4527         }
4528
4529         /* Stack alignment check */
4530 #if 0
4531         {
4532                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4533                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4534                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4535                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4536                 amd64_breakpoint (code);
4537         }
4538 #endif
4539
4540         /* Save LMF */
4541         if (method->save_lmf) {
4542                 /*
4543                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4544                  */
4545                 /* sp is saved right before calls */
4546                 /* Skip method (only needed for trampoline LMF frames) */
4547                 /* Save callee saved regs */
4548                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
4549                         int offset;
4550
4551                         switch (i) {
4552                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
4553                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
4554                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
4555                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
4556                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
4557                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
4558 #ifdef PLATFORM_WIN32
4559                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
4560                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
4561 #endif
4562                         default:
4563                                 offset = -1;
4564                                 break;
4565                         }
4566
4567                         if (offset != -1) {
4568                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
4569                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
4570                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
4571                         }
4572                 }
4573         }
4574
4575         /* Save callee saved registers */
4576         if (cfg->arch.omit_fp && !method->save_lmf) {
4577                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4578
4579                 /* Save caller saved registers after sp is adjusted */
4580                 /* The registers are saved at the bottom of the frame */
4581                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4582                 for (i = 0; i < AMD64_NREG; ++i)
4583                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4584                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4585                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
4586                                 save_area_offset += 8;
4587                                 async_exc_point (code);
4588                         }
4589         }
4590
4591         /* store runtime generic context */
4592         if (cfg->rgctx_var) {
4593                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4594                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4595
4596                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4597         }
4598
4599         /* compute max_offset in order to use short forward jumps */
4600         max_offset = 0;
4601         max_epilog_size = get_max_epilog_size (cfg);
4602         if (cfg->opt & MONO_OPT_BRANCH) {
4603                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4604                         MonoInst *ins;
4605                         bb->max_offset = max_offset;
4606
4607                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4608                                 max_offset += 6;
4609                         /* max alignment for loops */
4610                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4611                                 max_offset += LOOP_ALIGNMENT;
4612
4613                         MONO_BB_FOR_EACH_INS (bb, ins) {
4614                                 if (ins->opcode == OP_LABEL)
4615                                         ins->inst_c1 = max_offset;
4616
4617                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4618                         }
4619
4620                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4621                                 /* The tracing code can be quite large */
4622                                 max_offset += max_epilog_size;
4623                 }
4624         }
4625
4626         sig = mono_method_signature (method);
4627         pos = 0;
4628
4629         cinfo = cfg->arch.cinfo;
4630
4631         if (sig->ret->type != MONO_TYPE_VOID) {
4632                 /* Save volatile arguments to the stack */
4633                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4634                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4635         }
4636
4637         /* Keep this in sync with emit_load_volatile_arguments */
4638         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4639                 ArgInfo *ainfo = cinfo->args + i;
4640                 gint32 stack_offset;
4641                 MonoType *arg_type;
4642
4643                 ins = cfg->args [i];
4644
4645                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4646                         /* Unused arguments */
4647                         continue;
4648
4649                 if (sig->hasthis && (i == 0))
4650                         arg_type = &mono_defaults.object_class->byval_arg;
4651                 else
4652                         arg_type = sig->params [i - sig->hasthis];
4653
4654                 stack_offset = ainfo->offset + ARGS_OFFSET;
4655
4656                 if (cfg->globalra) {
4657                         /* All the other moves are done by the register allocator */
4658                         switch (ainfo->storage) {
4659                         case ArgInFloatSSEReg:
4660                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
4661                                 break;
4662                         case ArgValuetypeInReg:
4663                                 for (quad = 0; quad < 2; quad ++) {
4664                                         switch (ainfo->pair_storage [quad]) {
4665                                         case ArgInIReg:
4666                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4667                                                 break;
4668                                         case ArgInFloatSSEReg:
4669                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4670                                                 break;
4671                                         case ArgInDoubleSSEReg:
4672                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4673                                                 break;
4674                                         case ArgNone:
4675                                                 break;
4676                                         default:
4677                                                 g_assert_not_reached ();
4678                                         }
4679                                 }
4680                                 break;
4681                         default:
4682                                 break;
4683                         }
4684
4685                         continue;
4686                 }
4687
4688                 /* Save volatile arguments to the stack */
4689                 if (ins->opcode != OP_REGVAR) {
4690                         switch (ainfo->storage) {
4691                         case ArgInIReg: {
4692                                 guint32 size = 8;
4693
4694                                 /* FIXME: I1 etc */
4695                                 /*
4696                                 if (stack_offset & 0x1)
4697                                         size = 1;
4698                                 else if (stack_offset & 0x2)
4699                                         size = 2;
4700                                 else if (stack_offset & 0x4)
4701                                         size = 4;
4702                                 else
4703                                         size = 8;
4704                                 */
4705                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4706                                 break;
4707                         }
4708                         case ArgInFloatSSEReg:
4709                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4710                                 break;
4711                         case ArgInDoubleSSEReg:
4712                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4713                                 break;
4714                         case ArgValuetypeInReg:
4715                                 for (quad = 0; quad < 2; quad ++) {
4716                                         switch (ainfo->pair_storage [quad]) {
4717                                         case ArgInIReg:
4718                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4719                                                 break;
4720                                         case ArgInFloatSSEReg:
4721                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4722                                                 break;
4723                                         case ArgInDoubleSSEReg:
4724                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4725                                                 break;
4726                                         case ArgNone:
4727                                                 break;
4728                                         default:
4729                                                 g_assert_not_reached ();
4730                                         }
4731                                 }
4732                                 break;
4733                         case ArgValuetypeAddrInIReg:
4734                                 if (ainfo->pair_storage [0] == ArgInIReg)
4735                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
4736                                 break;
4737                         default:
4738                                 break;
4739                         }
4740                 } else {
4741                         /* Argument allocated to (non-volatile) register */
4742                         switch (ainfo->storage) {
4743                         case ArgInIReg:
4744                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4745                                 break;
4746                         case ArgOnStack:
4747                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4748                                 break;
4749                         default:
4750                                 g_assert_not_reached ();
4751                         }
4752                 }
4753         }
4754
4755         /* Might need to attach the thread to the JIT  or change the domain for the callback */
4756         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4757                 guint64 domain = (guint64)cfg->domain;
4758
4759                 args_clobbered = TRUE;
4760
4761                 /*
4762                  * The call might clobber argument registers, but they are already
4763                  * saved to the stack/global regs.
4764                  */
4765                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4766                         guint8 *buf, *no_domain_branch;
4767
4768                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4769                         if ((domain >> 32) == 0)
4770                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4771                         else
4772                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4773                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4774                         no_domain_branch = code;
4775                         x86_branch8 (code, X86_CC_NE, 0, 0);
4776                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4777                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4778                         buf = code;
4779                         x86_branch8 (code, X86_CC_NE, 0, 0);
4780                         amd64_patch (no_domain_branch, code);
4781                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4782                                           (gpointer)"mono_jit_thread_attach", TRUE);
4783                         amd64_patch (buf, code);
4784 #ifdef PLATFORM_WIN32
4785                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4786                         /* FIXME: Add a separate key for LMF to avoid this */
4787                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4788 #endif
4789                 } else {
4790                         g_assert (!cfg->compile_aot);
4791                         if ((domain >> 32) == 0)
4792                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4793                         else
4794                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4795                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4796                                           (gpointer)"mono_jit_thread_attach", TRUE);
4797                 }
4798         }
4799
4800         if (method->save_lmf) {
4801                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4802                         /*
4803                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4804                          * through the mono_lmf_addr TLS variable.
4805                          */
4806                         /* %rax = previous_lmf */
4807                         x86_prefix (code, X86_FS_PREFIX);
4808                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4809
4810                         /* Save previous_lmf */
4811                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4812                         /* Set new lmf */
4813                         if (lmf_offset == 0) {
4814                                 x86_prefix (code, X86_FS_PREFIX);
4815                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4816                         } else {
4817                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4818                                 x86_prefix (code, X86_FS_PREFIX);
4819                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4820                         }
4821                 } else {
4822                         if (lmf_addr_tls_offset != -1) {
4823                                 /* Load lmf quicky using the FS register */
4824                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4825 #ifdef PLATFORM_WIN32
4826                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4827                                 /* FIXME: Add a separate key for LMF to avoid this */
4828                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4829 #endif
4830                         }
4831                         else {
4832                                 /*
4833                                  * The call might clobber argument registers, but they are already
4834                                  * saved to the stack/global regs.
4835                                  */
4836                                 args_clobbered = TRUE;
4837                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4838                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
4839                         }
4840
4841                         /* Save lmf_addr */
4842                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4843                         /* Save previous_lmf */
4844                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4845                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4846                         /* Set new lmf */
4847                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4848                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4849                 }
4850         }
4851
4852         if (trace) {
4853                 args_clobbered = TRUE;
4854                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4855         }
4856
4857         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4858                 args_clobbered = TRUE;
4859
4860         /*
4861          * Optimize the common case of the first bblock making a call with the same
4862          * arguments as the method. This works because the arguments are still in their
4863          * original argument registers.
4864          * FIXME: Generalize this
4865          */
4866         if (!args_clobbered) {
4867                 MonoBasicBlock *first_bb = cfg->bb_entry;
4868                 MonoInst *next;
4869
4870                 next = mono_bb_first_ins (first_bb);
4871                 if (!next && first_bb->next_bb) {
4872                         first_bb = first_bb->next_bb;
4873                         next = mono_bb_first_ins (first_bb);
4874                 }
4875
4876                 if (first_bb->in_count > 1)
4877                         next = NULL;
4878
4879                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4880                         ArgInfo *ainfo = cinfo->args + i;
4881                         gboolean match = FALSE;
4882
4883                         ins = cfg->args [i];
4884                         if (ins->opcode != OP_REGVAR) {
4885                                 switch (ainfo->storage) {
4886                                 case ArgInIReg: {
4887                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4888                                                 if (next->dreg == ainfo->reg) {
4889                                                         NULLIFY_INS (next);
4890                                                         match = TRUE;
4891                                                 } else {
4892                                                         next->opcode = OP_MOVE;
4893                                                         next->sreg1 = ainfo->reg;
4894                                                         /* Only continue if the instruction doesn't change argument regs */
4895                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4896                                                                 match = TRUE;
4897                                                 }
4898                                         }
4899                                         break;
4900                                 }
4901                                 default:
4902                                         break;
4903                                 }
4904                         } else {
4905                                 /* Argument allocated to (non-volatile) register */
4906                                 switch (ainfo->storage) {
4907                                 case ArgInIReg:
4908                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4909                                                 NULLIFY_INS (next);
4910                                                 match = TRUE;
4911                                         }
4912                                         break;
4913                                 default:
4914                                         break;
4915                                 }
4916                         }
4917
4918                         if (match) {
4919                                 next = next->next;
4920                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4921                                 if (!next)
4922                                         break;
4923                         }
4924                 }
4925         }
4926
4927         cfg->code_len = code - cfg->native_code;
4928
4929         g_assert (cfg->code_len < cfg->code_size);
4930
4931         return code;
4932 }
4933
4934 void
4935 mono_arch_emit_epilog (MonoCompile *cfg)
4936 {
4937         MonoMethod *method = cfg->method;
4938         int quad, pos, i;
4939         guint8 *code;
4940         int max_epilog_size;
4941         CallInfo *cinfo;
4942         gint32 lmf_offset = cfg->arch.lmf_offset;
4943
4944         max_epilog_size = get_max_epilog_size (cfg);
4945
4946         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4947                 cfg->code_size *= 2;
4948                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4949                 mono_jit_stats.code_reallocs++;
4950         }
4951
4952         code = cfg->native_code + cfg->code_len;
4953
4954         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4955                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4956
4957         /* the code restoring the registers must be kept in sync with OP_JMP */
4958         pos = 0;
4959
4960         if (method->save_lmf) {
4961                 /* check if we need to restore protection of the stack after a stack overflow */
4962                 if (mono_get_jit_tls_offset () != -1) {
4963                         guint8 *patch;
4964                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4965                         /* we load the value in a separate instruction: this mechanism may be
4966                          * used later as a safer way to do thread interruption
4967                          */
4968                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
4969                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4970                         patch = code;
4971                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
4972                         /* note that the call trampoline will preserve eax/edx */
4973                         x86_call_reg (code, X86_ECX);
4974                         x86_patch (patch, code);
4975                 } else {
4976                         /* FIXME: maybe save the jit tls in the prolog */
4977                 }
4978                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4979                         /*
4980                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4981                          * through the mono_lmf_addr TLS variable.
4982                          */
4983                         /* reg = previous_lmf */
4984                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4985                         x86_prefix (code, X86_FS_PREFIX);
4986                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4987                 } else {
4988                         /* Restore previous lmf */
4989                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4990                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4991                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4992                 }
4993
4994                 /* Restore caller saved regs */
4995                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4996                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
4997                 }
4998                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4999                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5000                 }
5001                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5002                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5003                 }
5004                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5005                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5006                 }
5007                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5008                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5009                 }
5010                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5011                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5012                 }
5013 #ifdef PLATFORM_WIN32
5014                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
5015                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
5016                 }
5017                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
5018                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
5019                 }
5020 #endif
5021         } else {
5022
5023                 if (cfg->arch.omit_fp) {
5024                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5025
5026                         for (i = 0; i < AMD64_NREG; ++i)
5027                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5028                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5029                                         save_area_offset += 8;
5030                                 }
5031                 }
5032                 else {
5033                         for (i = 0; i < AMD64_NREG; ++i)
5034                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5035                                         pos -= sizeof (gpointer);
5036
5037                         if (pos) {
5038                                 if (pos == - sizeof (gpointer)) {
5039                                         /* Only one register, so avoid lea */
5040                                         for (i = AMD64_NREG - 1; i > 0; --i)
5041                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5042                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5043                                                 }
5044                                 }
5045                                 else {
5046                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5047
5048                                         /* Pop registers in reverse order */
5049                                         for (i = AMD64_NREG - 1; i > 0; --i)
5050                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5051                                                         amd64_pop_reg (code, i);
5052                                                 }
5053                                 }
5054                         }
5055                 }
5056         }
5057
5058         /* Load returned vtypes into registers if needed */
5059         cinfo = cfg->arch.cinfo;
5060         if (cinfo->ret.storage == ArgValuetypeInReg) {
5061                 ArgInfo *ainfo = &cinfo->ret;
5062                 MonoInst *inst = cfg->ret;
5063
5064                 for (quad = 0; quad < 2; quad ++) {
5065                         switch (ainfo->pair_storage [quad]) {
5066                         case ArgInIReg:
5067                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5068                                 break;
5069                         case ArgInFloatSSEReg:
5070                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5071                                 break;
5072                         case ArgInDoubleSSEReg:
5073                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5074                                 break;
5075                         case ArgNone:
5076                                 break;
5077                         default:
5078                                 g_assert_not_reached ();
5079                         }
5080                 }
5081         }
5082
5083         if (cfg->arch.omit_fp) {
5084                 if (cfg->arch.stack_alloc_size)
5085                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5086         } else {
5087                 amd64_leave (code);
5088         }
5089         async_exc_point (code);
5090         amd64_ret (code);
5091
5092         cfg->code_len = code - cfg->native_code;
5093
5094         g_assert (cfg->code_len < cfg->code_size);
5095
5096         if (cfg->arch.omit_fp) {
5097                 /*
5098                  * Encode the stack size into used_int_regs so the exception handler
5099                  * can access it.
5100                  */
5101                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5102                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5103         }
5104 }
5105
5106 void
5107 mono_arch_emit_exceptions (MonoCompile *cfg)
5108 {
5109         MonoJumpInfo *patch_info;
5110         int nthrows, i;
5111         guint8 *code;
5112         MonoClass *exc_classes [16];
5113         guint8 *exc_throw_start [16], *exc_throw_end [16];
5114         guint32 code_size = 0;
5115
5116         /* Compute needed space */
5117         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5118                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5119                         code_size += 40;
5120                 if (patch_info->type == MONO_PATCH_INFO_R8)
5121                         code_size += 8 + 15; /* sizeof (double) + alignment */
5122                 if (patch_info->type == MONO_PATCH_INFO_R4)
5123                         code_size += 4 + 15; /* sizeof (float) + alignment */
5124         }
5125
5126         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5127                 cfg->code_size *= 2;
5128                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5129                 mono_jit_stats.code_reallocs++;
5130         }
5131
5132         code = cfg->native_code + cfg->code_len;
5133
5134         /* add code to raise exceptions */
5135         nthrows = 0;
5136         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5137                 switch (patch_info->type) {
5138                 case MONO_PATCH_INFO_EXC: {
5139                         MonoClass *exc_class;
5140                         guint8 *buf, *buf2;
5141                         guint32 throw_ip;
5142
5143                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5144
5145                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5146                         g_assert (exc_class);
5147                         throw_ip = patch_info->ip.i;
5148
5149                         //x86_breakpoint (code);
5150                         /* Find a throw sequence for the same exception class */
5151                         for (i = 0; i < nthrows; ++i)
5152                                 if (exc_classes [i] == exc_class)
5153                                         break;
5154                         if (i < nthrows) {
5155                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5156                                 x86_jump_code (code, exc_throw_start [i]);
5157                                 patch_info->type = MONO_PATCH_INFO_NONE;
5158                         }
5159                         else {
5160                                 buf = code;
5161                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5162                                 buf2 = code;
5163
5164                                 if (nthrows < 16) {
5165                                         exc_classes [nthrows] = exc_class;
5166                                         exc_throw_start [nthrows] = code;
5167                                 }
5168                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5169
5170                                 patch_info->type = MONO_PATCH_INFO_NONE;
5171
5172                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5173
5174                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5175                                 while (buf < buf2)
5176                                         x86_nop (buf);
5177
5178                                 if (nthrows < 16) {
5179                                         exc_throw_end [nthrows] = code;
5180                                         nthrows ++;
5181                                 }
5182                         }
5183                         break;
5184                 }
5185                 default:
5186                         /* do nothing */
5187                         break;
5188                 }
5189         }
5190
5191         /* Handle relocations with RIP relative addressing */
5192         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5193                 gboolean remove = FALSE;
5194
5195                 switch (patch_info->type) {
5196                 case MONO_PATCH_INFO_R8:
5197                 case MONO_PATCH_INFO_R4: {
5198                         guint8 *pos;
5199
5200                         /* The SSE opcodes require a 16 byte alignment */
5201                         code = (guint8*)ALIGN_TO (code, 16);
5202
5203                         pos = cfg->native_code + patch_info->ip.i;
5204
5205                         if (IS_REX (pos [1]))
5206                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5207                         else
5208                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5209
5210                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5211                                 *(double*)code = *(double*)patch_info->data.target;
5212                                 code += sizeof (double);
5213                         } else {
5214                                 *(float*)code = *(float*)patch_info->data.target;
5215                                 code += sizeof (float);
5216                         }
5217
5218                         remove = TRUE;
5219                         break;
5220                 }
5221                 default:
5222                         break;
5223                 }
5224
5225                 if (remove) {
5226                         if (patch_info == cfg->patch_info)
5227                                 cfg->patch_info = patch_info->next;
5228                         else {
5229                                 MonoJumpInfo *tmp;
5230
5231                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5232                                         ;
5233                                 tmp->next = patch_info->next;
5234                         }
5235                 }
5236         }
5237
5238         cfg->code_len = code - cfg->native_code;
5239
5240         g_assert (cfg->code_len < cfg->code_size);
5241
5242 }
5243
5244 void*
5245 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5246 {
5247         guchar *code = p;
5248         CallInfo *cinfo = NULL;
5249         MonoMethodSignature *sig;
5250         MonoInst *inst;
5251         int i, n, stack_area = 0;
5252
5253         /* Keep this in sync with mono_arch_get_argument_info */
5254
5255         if (enable_arguments) {
5256                 /* Allocate a new area on the stack and save arguments there */
5257                 sig = mono_method_signature (cfg->method);
5258
5259                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5260
5261                 n = sig->param_count + sig->hasthis;
5262
5263                 stack_area = ALIGN_TO (n * 8, 16);
5264
5265                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5266
5267                 for (i = 0; i < n; ++i) {
5268                         inst = cfg->args [i];
5269
5270                         if (inst->opcode == OP_REGVAR)
5271                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5272                         else {
5273                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5274                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5275                         }
5276                 }
5277         }
5278
5279         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5280         amd64_set_reg_template (code, AMD64_ARG_REG1);
5281         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5282         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5283
5284         if (enable_arguments)
5285                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5286
5287         return code;
5288 }
5289
5290 enum {
5291         SAVE_NONE,
5292         SAVE_STRUCT,
5293         SAVE_EAX,
5294         SAVE_EAX_EDX,
5295         SAVE_XMM
5296 };
5297
5298 void*
5299 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5300 {
5301         guchar *code = p;
5302         int save_mode = SAVE_NONE;
5303         MonoMethod *method = cfg->method;
5304         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5305
5306         switch (rtype) {
5307         case MONO_TYPE_VOID:
5308                 /* special case string .ctor icall */
5309                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5310                         save_mode = SAVE_EAX;
5311                 else
5312                         save_mode = SAVE_NONE;
5313                 break;
5314         case MONO_TYPE_I8:
5315         case MONO_TYPE_U8:
5316                 save_mode = SAVE_EAX;
5317                 break;
5318         case MONO_TYPE_R4:
5319         case MONO_TYPE_R8:
5320                 save_mode = SAVE_XMM;
5321                 break;
5322         case MONO_TYPE_GENERICINST:
5323                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5324                         save_mode = SAVE_EAX;
5325                         break;
5326                 }
5327                 /* Fall through */
5328         case MONO_TYPE_VALUETYPE:
5329                 save_mode = SAVE_STRUCT;
5330                 break;
5331         default:
5332                 save_mode = SAVE_EAX;
5333                 break;
5334         }
5335
5336         /* Save the result and copy it into the proper argument register */
5337         switch (save_mode) {
5338         case SAVE_EAX:
5339                 amd64_push_reg (code, AMD64_RAX);
5340                 /* Align stack */
5341                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5342                 if (enable_arguments)
5343                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5344                 break;
5345         case SAVE_STRUCT:
5346                 /* FIXME: */
5347                 if (enable_arguments)
5348                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5349                 break;
5350         case SAVE_XMM:
5351                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5352                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5353                 /* Align stack */
5354                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5355                 /*
5356                  * The result is already in the proper argument register so no copying
5357                  * needed.
5358                  */
5359                 break;
5360         case SAVE_NONE:
5361                 break;
5362         default:
5363                 g_assert_not_reached ();
5364         }
5365
5366         /* Set %al since this is a varargs call */
5367         if (save_mode == SAVE_XMM)
5368                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5369         else
5370                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5371
5372         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5373         amd64_set_reg_template (code, AMD64_ARG_REG1);
5374         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5375
5376         /* Restore result */
5377         switch (save_mode) {
5378         case SAVE_EAX:
5379                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5380                 amd64_pop_reg (code, AMD64_RAX);
5381                 break;
5382         case SAVE_STRUCT:
5383                 /* FIXME: */
5384                 break;
5385         case SAVE_XMM:
5386                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5387                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5388                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5389                 break;
5390         case SAVE_NONE:
5391                 break;
5392         default:
5393                 g_assert_not_reached ();
5394         }
5395
5396         return code;
5397 }
5398
5399 void
5400 mono_arch_flush_icache (guint8 *code, gint size)
5401 {
5402         /* Not needed */
5403 }
5404
5405 void
5406 mono_arch_flush_register_windows (void)
5407 {
5408 }
5409
5410 gboolean
5411 mono_arch_is_inst_imm (gint64 imm)
5412 {
5413         return amd64_is_imm32 (imm);
5414 }
5415
5416 /*
5417  * Determine whenever the trap whose info is in SIGINFO is caused by
5418  * integer overflow.
5419  */
5420 gboolean
5421 mono_arch_is_int_overflow (void *sigctx, void *info)
5422 {
5423         MonoContext ctx;
5424         guint8* rip;
5425         int reg;
5426         gint64 value;
5427
5428         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5429
5430         rip = (guint8*)ctx.rip;
5431
5432         if (IS_REX (rip [0])) {
5433                 reg = amd64_rex_b (rip [0]);
5434                 rip ++;
5435         }
5436         else
5437                 reg = 0;
5438
5439         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5440                 /* idiv REG */
5441                 reg += x86_modrm_rm (rip [1]);
5442
5443                 switch (reg) {
5444                 case AMD64_RAX:
5445                         value = ctx.rax;
5446                         break;
5447                 case AMD64_RBX:
5448                         value = ctx.rbx;
5449                         break;
5450                 case AMD64_RCX:
5451                         value = ctx.rcx;
5452                         break;
5453                 case AMD64_RDX:
5454                         value = ctx.rdx;
5455                         break;
5456                 case AMD64_RBP:
5457                         value = ctx.rbp;
5458                         break;
5459                 case AMD64_RSP:
5460                         value = ctx.rsp;
5461                         break;
5462                 case AMD64_RSI:
5463                         value = ctx.rsi;
5464                         break;
5465                 case AMD64_RDI:
5466                         value = ctx.rdi;
5467                         break;
5468                 case AMD64_R12:
5469                         value = ctx.r12;
5470                         break;
5471                 case AMD64_R13:
5472                         value = ctx.r13;
5473                         break;
5474                 case AMD64_R14:
5475                         value = ctx.r14;
5476                         break;
5477                 case AMD64_R15:
5478                         value = ctx.r15;
5479                         break;
5480                 default:
5481                         g_assert_not_reached ();
5482                         reg = -1;
5483                 }
5484
5485                 if (value == -1)
5486                         return TRUE;
5487         }
5488
5489         return FALSE;
5490 }
5491
5492 guint32
5493 mono_arch_get_patch_offset (guint8 *code)
5494 {
5495         return 3;
5496 }
5497
5498 /**
5499  * mono_breakpoint_clean_code:
5500  *
5501  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5502  * breakpoints in the original code, they are removed in the copy.
5503  *
5504  * Returns TRUE if no sw breakpoint was present.
5505  */
5506 gboolean
5507 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5508 {
5509         int i;
5510         gboolean can_write = TRUE;
5511         /*
5512          * If method_start is non-NULL we need to perform bound checks, since we access memory
5513          * at code - offset we could go before the start of the method and end up in a different
5514          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5515          * instead.
5516          */
5517         if (!method_start || code - offset >= method_start) {
5518                 memcpy (buf, code - offset, size);
5519         } else {
5520                 int diff = code - method_start;
5521                 memset (buf, 0, size);
5522                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5523         }
5524         code -= offset;
5525         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5526                 int idx = mono_breakpoint_info_index [i];
5527                 guint8 *ptr;
5528                 if (idx < 1)
5529                         continue;
5530                 ptr = mono_breakpoint_info [idx].address;
5531                 if (ptr >= code && ptr < code + size) {
5532                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5533                         can_write = FALSE;
5534                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5535                         buf [ptr - code] = saved_byte;
5536                 }
5537         }
5538         return can_write;
5539 }
5540
5541 gpointer
5542 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5543 {
5544         guint8 buf [10];
5545         guint32 reg;
5546         gint32 disp;
5547         guint8 rex = 0;
5548
5549         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5550         code = buf + 9;
5551
5552         *displacement = 0;
5553
5554         /* go to the start of the call instruction
5555          *
5556          * address_byte = (m << 6) | (o << 3) | reg
5557          * call opcode: 0xff address_byte displacement
5558          * 0xff m=1,o=2 imm8
5559          * 0xff m=2,o=2 imm32
5560          */
5561         code -= 7;
5562
5563         /*
5564          * A given byte sequence can match more than case here, so we have to be
5565          * really careful about the ordering of the cases. Longer sequences
5566          * come first.
5567          * Some of the rules are only needed because the imm in the mov could
5568          * match the
5569          * code [2] == 0xe8 case below.
5570          */
5571 #ifdef MONO_ARCH_HAVE_IMT
5572         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5573                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5574                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5575                  * ff 50 fc                call   *0xfffffffc(%rax)
5576                  */
5577                 reg = amd64_modrm_rm (code [5]);
5578                 disp = (signed char)code [6];
5579                 /* R10 is clobbered by the IMT thunk code */
5580                 g_assert (reg != AMD64_R10);
5581         }
5582 #else
5583         if (0) {
5584         }
5585 #endif
5586         else if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5587                 /*
5588                  * 41 bb e8 e8 e8 e8     mov    $0xe8e8e8e8,%r11d
5589                  * ff 50 60              callq  *0x60(%rax)
5590                  */
5591                 if (IS_REX (code [3]))
5592                         rex = code [3];
5593                 reg = amd64_modrm_rm (code [5]);
5594                 disp = *(gint8*)(code + 6);
5595                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5596         } else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5597                 /*
5598                  * This is a interface call
5599                  * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5600                  * ff 10                  callq  *(%rax)
5601                  */
5602                 if (IS_REX (code [4]))
5603                         rex = code [4];
5604                 reg = amd64_modrm_rm (code [6]);
5605                 disp = 0;
5606                 /* R10 is clobbered by the IMT thunk code */
5607                 g_assert (reg != AMD64_R10);
5608         } else if ((code [-1] >= 0xb8) && (code [-1] < 0xb8 + 8) && (code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5609                 /*
5610                  * ba e8 e8 e8 e8     mov    $0xe8e8e8e8,%edx
5611                  * ff 50 60              callq  *0x60(%rax)
5612                  */
5613                 if (IS_REX (code [3]))
5614                         rex = code [3];
5615                 reg = amd64_modrm_rm (code [5]);
5616                 disp = *(gint8*)(code + 6);
5617         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5618                 /* call OFFSET(%rip) */
5619                 disp = *(guint32*)(code + 3);
5620                 return (gpointer*)(code + disp + 7);
5621         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5622                 /* call *[r12+disp32] */
5623                 if (IS_REX (code [-1]))
5624                         rex = code [-1];
5625                 reg = AMD64_RSP;
5626                 disp = *(gint32*)(code + 3);
5627         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5628                 /* call *[reg+disp32] */
5629                 if (IS_REX (code [0]))
5630                         rex = code [0];
5631                 reg = amd64_modrm_rm (code [2]);
5632                 disp = *(gint32*)(code + 3);
5633                 /* R10 is clobbered by the IMT thunk code */
5634                 g_assert (reg != AMD64_R10);
5635         } else if (code [2] == 0xe8) {
5636                 /* call <ADDR> */
5637                 return NULL;
5638         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5639                 /* call *[r12+disp32] */
5640                 if (IS_REX (code [2]))
5641                         rex = code [2];
5642                 reg = AMD64_RSP;
5643                 disp = *(gint8*)(code + 6);
5644         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5645                 /* call *%reg */
5646                 return NULL;
5647         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5648                 /* call *[reg+disp8] */
5649                 if (IS_REX (code [3]))
5650                         rex = code [3];
5651                 reg = amd64_modrm_rm (code [5]);
5652                 disp = *(gint8*)(code + 6);
5653                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5654         }
5655         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5656                         /*
5657                          * This is a interface call: should check the above code can't catch it earlier
5658                          * 8b 40 30   mov    0x30(%eax),%eax
5659                          * ff 10      call   *(%eax)
5660                          */
5661                 if (IS_REX (code [4]))
5662                         rex = code [4];
5663                 reg = amd64_modrm_rm (code [6]);
5664                 disp = 0;
5665         }
5666         else
5667                 g_assert_not_reached ();
5668
5669         reg += amd64_rex_b (rex);
5670
5671         /* R11 is clobbered by the trampoline code */
5672         g_assert (reg != AMD64_R11);
5673
5674         *displacement = disp;
5675         return regs [reg];
5676 }
5677
5678 gpointer*
5679 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5680 {
5681         gpointer vt;
5682         int displacement;
5683         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5684         if (!vt)
5685                 return NULL;
5686         return (gpointer*)((char*)vt + displacement);
5687 }
5688
5689 int
5690 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5691 {
5692         int this_reg = AMD64_ARG_REG1;
5693
5694         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5695                 CallInfo *cinfo;
5696
5697                 if (!gsctx && code)
5698                         gsctx = mono_get_generic_context_from_code (code);
5699
5700                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5701
5702                 if (cinfo->ret.storage != ArgValuetypeInReg)
5703                         this_reg = AMD64_ARG_REG2;
5704                 g_free (cinfo);
5705         }
5706
5707         return this_reg;
5708 }
5709
5710 gpointer
5711 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5712 {
5713         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
5714 }
5715
5716 #define MAX_ARCH_DELEGATE_PARAMS 10
5717
5718 gpointer
5719 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5720 {
5721         guint8 *code, *start;
5722         int i;
5723
5724         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5725                 return NULL;
5726
5727         /* FIXME: Support more cases */
5728         if (MONO_TYPE_ISSTRUCT (sig->ret))
5729                 return NULL;
5730
5731         if (has_target) {
5732                 static guint8* cached = NULL;
5733
5734                 if (cached)
5735                         return cached;
5736
5737                 start = code = mono_global_codeman_reserve (64);
5738
5739                 /* Replace the this argument with the target */
5740                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5741                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5742                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5743
5744                 g_assert ((code - start) < 64);
5745
5746                 mono_debug_add_delegate_trampoline (start, code - start);
5747
5748                 mono_memory_barrier ();
5749
5750                 cached = start;
5751         } else {
5752                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5753                 for (i = 0; i < sig->param_count; ++i)
5754                         if (!mono_is_regsize_var (sig->params [i]))
5755                                 return NULL;
5756                 if (sig->param_count > 4)
5757                         return NULL;
5758
5759                 code = cache [sig->param_count];
5760                 if (code)
5761                         return code;
5762
5763                 start = code = mono_global_codeman_reserve (64);
5764
5765                 if (sig->param_count == 0) {
5766                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5767                 } else {
5768                         /* We have to shift the arguments left */
5769                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5770                         for (i = 0; i < sig->param_count; ++i) {
5771 #ifdef PLATFORM_WIN32
5772                                 if (i < 3)
5773                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5774                                 else
5775                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
5776 #else
5777                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5778 #endif
5779                         }
5780
5781                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5782                 }
5783                 g_assert ((code - start) < 64);
5784
5785                 mono_debug_add_delegate_trampoline (start, code - start);
5786
5787                 mono_memory_barrier ();
5788
5789                 cache [sig->param_count] = start;
5790         }
5791
5792         return start;
5793 }
5794
5795 /*
5796  * Support for fast access to the thread-local lmf structure using the GS
5797  * segment register on NPTL + kernel 2.6.x.
5798  */
5799
5800 static gboolean tls_offset_inited = FALSE;
5801
5802 void
5803 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5804 {
5805         if (!tls_offset_inited) {
5806 #ifdef PLATFORM_WIN32
5807                 /*
5808                  * We need to init this multiple times, since when we are first called, the key might not
5809                  * be initialized yet.
5810                  */
5811                 appdomain_tls_offset = mono_domain_get_tls_key ();
5812                 lmf_tls_offset = mono_get_jit_tls_key ();
5813                 thread_tls_offset = mono_thread_get_tls_key ();
5814                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
5815
5816                 /* Only 64 tls entries can be accessed using inline code */
5817                 if (appdomain_tls_offset >= 64)
5818                         appdomain_tls_offset = -1;
5819                 if (lmf_tls_offset >= 64)
5820                         lmf_tls_offset = -1;
5821                 if (thread_tls_offset >= 64)
5822                         thread_tls_offset = -1;
5823 #else
5824                 tls_offset_inited = TRUE;
5825 #ifdef MONO_XEN_OPT
5826                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5827 #endif
5828                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5829                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5830                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5831                 thread_tls_offset = mono_thread_get_tls_offset ();
5832 #endif
5833         }
5834 }
5835
5836 void
5837 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5838 {
5839 }
5840
5841 #ifdef MONO_ARCH_HAVE_IMT
5842
5843 #define CMP_SIZE (6 + 1)
5844 #define CMP_REG_REG_SIZE (4 + 1)
5845 #define BR_SMALL_SIZE 2
5846 #define BR_LARGE_SIZE 6
5847 #define MOV_REG_IMM_SIZE 10
5848 #define MOV_REG_IMM_32BIT_SIZE 6
5849 #define JUMP_REG_SIZE (2 + 1)
5850
5851 static int
5852 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5853 {
5854         int i, distance = 0;
5855         for (i = start; i < target; ++i)
5856                 distance += imt_entries [i]->chunk_size;
5857         return distance;
5858 }
5859
5860 /*
5861  * LOCKING: called with the domain lock held
5862  */
5863 gpointer
5864 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5865         gpointer fail_tramp)
5866 {
5867         int i;
5868         int size = 0;
5869         guint8 *code, *start;
5870         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5871
5872         for (i = 0; i < count; ++i) {
5873                 MonoIMTCheckItem *item = imt_entries [i];
5874                 if (item->is_equals) {
5875                         if (item->check_target_idx) {
5876                                 if (!item->compare_done) {
5877                                         if (amd64_is_imm32 (item->key))
5878                                                 item->chunk_size += CMP_SIZE;
5879                                         else
5880                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5881                                 }
5882                                 if (vtable_is_32bit)
5883                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5884                                 else
5885                                         item->chunk_size += MOV_REG_IMM_SIZE;
5886                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5887                         } else {
5888                                 if (fail_tramp) {
5889                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
5890                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
5891                                 } else {
5892                                         if (vtable_is_32bit)
5893                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5894                                         else
5895                                                 item->chunk_size += MOV_REG_IMM_SIZE;
5896                                         item->chunk_size += JUMP_REG_SIZE;
5897                                         /* with assert below:
5898                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5899                                          */
5900                                 }
5901                         }
5902                 } else {
5903                         if (amd64_is_imm32 (item->key))
5904                                 item->chunk_size += CMP_SIZE;
5905                         else
5906                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5907                         item->chunk_size += BR_LARGE_SIZE;
5908                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5909                 }
5910                 size += item->chunk_size;
5911         }
5912         if (fail_tramp)
5913                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5914         else
5915                 code = mono_code_manager_reserve (domain->code_mp, size);
5916         start = code;
5917         for (i = 0; i < count; ++i) {
5918                 MonoIMTCheckItem *item = imt_entries [i];
5919                 item->code_target = code;
5920                 if (item->is_equals) {
5921                         if (item->check_target_idx) {
5922                                 if (!item->compare_done) {
5923                                         if (amd64_is_imm32 (item->key))
5924                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5925                                         else {
5926                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5927                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5928                                         }
5929                                 }
5930                                 item->jmp_code = code;
5931                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5932                                 /* See the comment below about R10 */
5933                                 if (fail_tramp) {
5934                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5935                                         amd64_jump_reg (code, AMD64_R10);
5936                                 } else {
5937                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5938                                         amd64_jump_membase (code, AMD64_R10, 0);
5939                                 }
5940                         } else {
5941                                 if (fail_tramp) {
5942                                         if (amd64_is_imm32 (item->key))
5943                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5944                                         else {
5945                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5946                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5947                                         }
5948                                         item->jmp_code = code;
5949                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5950                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5951                                         amd64_jump_reg (code, AMD64_R10);
5952                                         amd64_patch (item->jmp_code, code);
5953                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
5954                                         amd64_jump_reg (code, AMD64_R10);
5955                                         item->jmp_code = NULL;
5956
5957                                 } else {
5958                                         /* enable the commented code to assert on wrong method */
5959 #if 0
5960                                         if (amd64_is_imm32 (item->key))
5961                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5962                                         else {
5963                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5964                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5965                                         }
5966                                         item->jmp_code = code;
5967                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5968                                         /* See the comment below about R10 */
5969                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5970                                         amd64_jump_membase (code, AMD64_R10, 0);
5971                                         amd64_patch (item->jmp_code, code);
5972                                         amd64_breakpoint (code);
5973                                         item->jmp_code = NULL;
5974 #else
5975                                         /* We're using R10 here because R11
5976                                            needs to be preserved.  R10 needs
5977                                            to be preserved for calls which
5978                                            require a runtime generic context,
5979                                            but interface calls don't. */
5980                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5981                                         amd64_jump_membase (code, AMD64_R10, 0);
5982 #endif
5983                                 }
5984                         }
5985                 } else {
5986                         if (amd64_is_imm32 (item->key))
5987                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5988                         else {
5989                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5990                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5991                         }
5992                         item->jmp_code = code;
5993                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5994                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5995                         else
5996                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5997                 }
5998                 g_assert (code - item->code_target <= item->chunk_size);
5999         }
6000         /* patch the branches to get to the target items */
6001         for (i = 0; i < count; ++i) {
6002                 MonoIMTCheckItem *item = imt_entries [i];
6003                 if (item->jmp_code) {
6004                         if (item->check_target_idx) {
6005                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6006                         }
6007                 }
6008         }
6009
6010         if (!fail_tramp)
6011                 mono_stats.imt_thunks_size += code - start;
6012         g_assert (code - start <= size);
6013
6014         return start;
6015 }
6016
6017 MonoMethod*
6018 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6019 {
6020         return regs [MONO_ARCH_IMT_REG];
6021 }
6022
6023 MonoObject*
6024 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6025 {
6026         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6027 }
6028
6029 void
6030 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6031 {
6032         /* Done by the implementation of the CALL_MEMBASE opcodes */
6033 }
6034 #endif
6035
6036 MonoVTable*
6037 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6038 {
6039         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6040 }
6041
6042 MonoInst*
6043 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6044 {
6045         MonoInst *ins = NULL;
6046         int opcode = 0;
6047
6048         if (cmethod->klass == mono_defaults.math_class) {
6049                 if (strcmp (cmethod->name, "Sin") == 0) {
6050                         opcode = OP_SIN;
6051                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6052                         opcode = OP_COS;
6053                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6054                         opcode = OP_SQRT;
6055                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6056                         opcode = OP_ABS;
6057                 }
6058
6059                 if (opcode) {
6060                         MONO_INST_NEW (cfg, ins, opcode);
6061                         ins->type = STACK_R8;
6062                         ins->dreg = mono_alloc_freg (cfg);
6063                         ins->sreg1 = args [0]->dreg;
6064                         MONO_ADD_INS (cfg->cbb, ins);
6065                 }
6066
6067                 opcode = 0;
6068                 if (cfg->opt & MONO_OPT_CMOV) {
6069                         if (strcmp (cmethod->name, "Min") == 0) {
6070                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6071                                         opcode = OP_IMIN;
6072                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6073                                         opcode = OP_IMIN_UN;
6074                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6075                                         opcode = OP_LMIN;
6076                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6077                                         opcode = OP_LMIN_UN;
6078                         } else if (strcmp (cmethod->name, "Max") == 0) {
6079                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6080                                         opcode = OP_IMAX;
6081                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6082                                         opcode = OP_IMAX_UN;
6083                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6084                                         opcode = OP_LMAX;
6085                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6086                                         opcode = OP_LMAX_UN;
6087                         }
6088                 }
6089
6090                 if (opcode) {
6091                         MONO_INST_NEW (cfg, ins, opcode);
6092                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6093                         ins->dreg = mono_alloc_ireg (cfg);
6094                         ins->sreg1 = args [0]->dreg;
6095                         ins->sreg2 = args [1]->dreg;
6096                         MONO_ADD_INS (cfg->cbb, ins);
6097                 }
6098
6099 #if 0
6100                 /* OP_FREM is not IEEE compatible */
6101                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6102                         MONO_INST_NEW (cfg, ins, OP_FREM);
6103                         ins->inst_i0 = args [0];
6104                         ins->inst_i1 = args [1];
6105                 }
6106 #endif
6107         }
6108
6109         /*
6110          * Can't implement CompareExchange methods this way since they have
6111          * three arguments.
6112          */
6113
6114         return ins;
6115 }
6116
6117 gboolean
6118 mono_arch_print_tree (MonoInst *tree, int arity)
6119 {
6120         return 0;
6121 }
6122
6123 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6124 {
6125         MonoInst* ins;
6126
6127         if (appdomain_tls_offset == -1)
6128                 return NULL;
6129
6130         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6131         ins->inst_offset = appdomain_tls_offset;
6132         return ins;
6133 }
6134
6135 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6136 {
6137         MonoInst* ins;
6138
6139         if (thread_tls_offset == -1)
6140                 return NULL;
6141
6142         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6143         ins->inst_offset = thread_tls_offset;
6144         return ins;
6145 }
6146
6147 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6148
6149 gpointer
6150 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6151 {
6152         switch (reg) {
6153         case AMD64_RCX: return (gpointer)ctx->rcx;
6154         case AMD64_RDX: return (gpointer)ctx->rdx;
6155         case AMD64_RBX: return (gpointer)ctx->rbx;
6156         case AMD64_RBP: return (gpointer)ctx->rbp;
6157         case AMD64_RSP: return (gpointer)ctx->rsp;
6158         default:
6159                 if (reg < 8)
6160                         return _CTX_REG (ctx, rax, reg);
6161                 else if (reg >= 12)
6162                         return _CTX_REG (ctx, r12, reg - 12);
6163                 else
6164                         g_assert_not_reached ();
6165         }
6166 }