mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/appdomain.h>
  24 #include <mono/metadata/debug-helpers.h>
  25 #include <mono/metadata/threads.h>
  26 #include <mono/metadata/profiler-private.h>
  27 #include <mono/metadata/mono-debug.h>
  28 #include <mono/metadata/gc-internal.h>
  29 #include <mono/utils/mono-math.h>
  30 #include <mono/utils/mono-mmap.h>
  31 #include <mono/utils/mono-memory-model.h>
  32 #include <mono/utils/mono-tls.h>
  33
  34 #include "trace.h"
  35 #include "ir-emit.h"
  36 #include "mini-amd64.h"
  37 #include "cpu-amd64.h"
  38 #include "debugger-agent.h"
  39 #include "mini-gc.h"
  40
  41 static gint lmf_tls_offset = -1;
  42 static gint lmf_addr_tls_offset = -1;
  43 static gint appdomain_tls_offset = -1;
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef HOST_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  67 static CRITICAL_SECTION mini_arch_mutex;
  68
  69 MonoBreakpointInfo
  70 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  71
  72 /* Structure used by the sequence points in AOTed code */
  73 typedef struct {
  74         gpointer ss_trigger_page;
  75         gpointer bp_trigger_page;
  76         gpointer bp_addrs [MONO_ZERO_LEN_ARRAY];
  77 } SeqPointInfo;
  78
  79 /*
  80  * The code generated for sequence points reads from this location, which is
  81  * made read-only when single stepping is enabled.
  82  */
  83 static gpointer ss_trigger_page;
  84
  85 /* Enabled breakpoints read from this trigger page */
  86 static gpointer bp_trigger_page;
  87
  88 /* The size of the breakpoint sequence */
  89 static int breakpoint_size;
  90
  91 /* The size of the breakpoint instruction causing the actual fault */
  92 static int breakpoint_fault_size;
  93
  94 /* The size of the single step instruction causing the actual fault */
  95 static int single_step_fault_size;
  96
  97 #ifdef HOST_WIN32
  98 /* On Win64 always reserve first 32 bytes for first four arguments */
  99 #define ARGS_OFFSET 48
 100 #else
 101 #define ARGS_OFFSET 16
 102 #endif
 103 #define GP_SCRATCH_REG AMD64_R11
 104
 105 /*
 106  * AMD64 register usage:
 107  * - callee saved registers are used for global register allocation
 108  * - %r11 is used for materializing 64 bit constants in opcodes
 109  * - the rest is used for local allocation
 110  */
 111
 112 /*
 113  * Floating point comparison results:
 114  *                  ZF PF CF
 115  * A > B            0  0  0
 116  * A < B            0  0  1
 117  * A = B            1  0  0
 118  * A > B            0  0  0
 119  * UNORDERED        1  1  1
 120  */
 121
 122 const char*
 123 mono_arch_regname (int reg)
 124 {
 125         switch (reg) {
 126         case AMD64_RAX: return "%rax";
 127         case AMD64_RBX: return "%rbx";
 128         case AMD64_RCX: return "%rcx";
 129         case AMD64_RDX: return "%rdx";
 130         case AMD64_RSP: return "%rsp";
 131         case AMD64_RBP: return "%rbp";
 132         case AMD64_RDI: return "%rdi";
 133         case AMD64_RSI: return "%rsi";
 134         case AMD64_R8: return "%r8";
 135         case AMD64_R9: return "%r9";
 136         case AMD64_R10: return "%r10";
 137         case AMD64_R11: return "%r11";
 138         case AMD64_R12: return "%r12";
 139         case AMD64_R13: return "%r13";
 140         case AMD64_R14: return "%r14";
 141         case AMD64_R15: return "%r15";
 142         }
 143         return "unknown";
 144 }
 145
 146 static const char * packed_xmmregs [] = {
 147         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 148         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 149 };
 150
 151 static const char * single_xmmregs [] = {
 152         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 153         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 154 };
 155
 156 const char*
 157 mono_arch_fregname (int reg)
 158 {
 159         if (reg < AMD64_XMM_NREG)
 160                 return single_xmmregs [reg];
 161         else
 162                 return "unknown";
 163 }
 164
 165 const char *
 166 mono_arch_xregname (int reg)
 167 {
 168         if (reg < AMD64_XMM_NREG)
 169                 return packed_xmmregs [reg];
 170         else
 171                 return "unknown";
 172 }
 173
 174 static gboolean
 175 debug_omit_fp (void)
 176 {
 177 #if 0
 178         return mono_debug_count ();
 179 #else
 180         return TRUE;
 181 #endif
 182 }
 183
 184 static inline gboolean
 185 amd64_is_near_call (guint8 *code)
 186 {
 187         /* Skip REX */
 188         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 189                 code += 1;
 190
 191         return code [0] == 0xe8;
 192 }
 193
 194 #ifdef __native_client_codegen__
 195
 196 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 197 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 198 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 199 /* We only want to force bundle alignment for the top level instruction,    */
 200 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 201 static MonoNativeTlsKey nacl_instruction_depth;
 202
 203 static MonoNativeTlsKey nacl_rex_tag;
 204 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 205
 206 void
 207 amd64_nacl_clear_legacy_prefix_tag ()
 208 {
 209         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 210 }
 211
 212 void
 213 amd64_nacl_tag_legacy_prefix (guint8* code)
 214 {
 215         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 216                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 217 }
 218
 219 void
 220 amd64_nacl_tag_rex (guint8* code)
 221 {
 222         mono_native_tls_set_value (nacl_rex_tag, code);
 223 }
 224
 225 guint8*
 226 amd64_nacl_get_legacy_prefix_tag ()
 227 {
 228         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 229 }
 230
 231 guint8*
 232 amd64_nacl_get_rex_tag ()
 233 {
 234         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 235 }
 236
 237 /* Increment the instruction "depth" described above */
 238 void
 239 amd64_nacl_instruction_pre ()
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth++;
 243         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 244 }
 245
 246 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 247 /* alignment if depth == 0 (top level instruction)                          */
 248 /* IN: start, end    pointers to instruction beginning and end              */
 249 /* OUT: start, end   pointers to beginning and end after possible alignment */
 250 /* GLOBALS: nacl_instruction_depth     defined above                        */
 251 void
 252 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 253 {
 254         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 255         depth--;
 256         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 257
 258         g_assert ( depth >= 0 );
 259         if (depth == 0) {
 260                 uintptr_t space_in_block;
 261                 uintptr_t instlen;
 262                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 263                 /* if legacy prefix is present, and if it was emitted before */
 264                 /* the start of the instruction sequence, adjust the start   */
 265                 if (prefix != NULL && prefix < *start) {
 266                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 267                         *start = prefix;
 268                 }
 269                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 270                 instlen = (uintptr_t)(*end - *start);
 271                 /* Only check for instructions which are less than        */
 272                 /* kNaClAlignment. The only instructions that should ever */
 273                 /* be that long are call sequences, which are already     */
 274                 /* padded out to align the return to the next bundle.     */
 275                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 276                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 277                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 278                         const size_t length = (size_t)((*end)-(*start));
 279                         g_assert (length < MAX_NACL_INST_LENGTH);
 280
 281                         memcpy (copy_of_instruction, *start, length);
 282                         *start = mono_arch_nacl_pad (*start, space_in_block);
 283                         memcpy (*start, copy_of_instruction, length);
 284                         *end = *start + length;
 285                 }
 286                 amd64_nacl_clear_legacy_prefix_tag ();
 287                 amd64_nacl_tag_rex (NULL);
 288         }
 289 }
 290
 291 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 292 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 293 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 294 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 295 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 296 /* IN:      code                                                            */
 297 /*             pointer to current instruction stream (in the                */
 298 /*             middle of an instruction, after opcode is emitted)           */
 299 /*          basereg/offset/dreg                                             */
 300 /*             operands of normal membase address                           */
 301 /* OUT:     code                                                            */
 302 /*             pointer to the end of the membase/memindex emit              */
 303 /* GLOBALS: nacl_rex_tag                                                    */
 304 /*             position in instruction stream that rex prefix was emitted   */
 305 /*          nacl_legacy_prefix_tag                                          */
 306 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 307 void
 308 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 309 {
 310         gint8 true_basereg = basereg;
 311
 312         /* Cache these values, they might change  */
 313         /* as new instructions are emitted below. */
 314         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 315         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 316
 317         /* 'basereg' is given masked to 0x7 at this point, so check */
 318         /* the rex prefix to see if this is an extended register.   */
 319         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 320                 true_basereg |= 0x8;
 321         }
 322
 323 #define X86_LEA_OPCODE (0x8D)
 324
 325         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 326                 guint8* old_instruction_start;
 327
 328                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 329                 /* 32-bits of the old base register (new index register)     */
 330                 guint8 buf[32];
 331                 guint8* buf_ptr = buf;
 332                 size_t insert_len;
 333
 334                 g_assert (rex_tag != NULL);
 335
 336                 if (IS_REX(*rex_tag)) {
 337                         /* The old rex.B should be the new rex.X */
 338                         if (*rex_tag & AMD64_REX_B) {
 339                                 *rex_tag |= AMD64_REX_X;
 340                         }
 341                         /* Since our new base is %r15 set rex.B */
 342                         *rex_tag |= AMD64_REX_B;
 343                 } else {
 344                         /* Shift the instruction by one byte  */
 345                         /* so we can insert a rex prefix      */
 346                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 347                         *code += 1;
 348                         /* New rex prefix only needs rex.B for %r15 base */
 349                         *rex_tag = AMD64_REX(AMD64_REX_B);
 350                 }
 351
 352                 if (legacy_prefix_tag) {
 353                         old_instruction_start = legacy_prefix_tag;
 354                 } else {
 355                         old_instruction_start = rex_tag;
 356                 }
 357
 358                 /* Clears the upper 32-bits of the previous base register */
 359                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 360                 insert_len = buf_ptr - buf;
 361
 362                 /* Move the old instruction forward to make */
 363                 /* room for 'mov' stored in 'buf_ptr'       */
 364                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 365                 *code += insert_len;
 366                 memcpy (old_instruction_start, buf, insert_len);
 367
 368                 /* Sandboxed replacement for the normal membase_emit */
 369                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 370
 371         } else {
 372                 /* Normal default behavior, emit membase memory location */
 373                 x86_membase_emit_body (*code, dreg, basereg, offset);
 374         }
 375 }
 376
 377
 378 static inline unsigned char*
 379 amd64_skip_nops (unsigned char* code)
 380 {
 381         guint8 in_nop;
 382         do {
 383                 in_nop = 0;
 384                 if (   code[0] == 0x90) {
 385                         in_nop = 1;
 386                         code += 1;
 387                 }
 388                 if (   code[0] == 0x66 && code[1] == 0x90) {
 389                         in_nop = 1;
 390                         code += 2;
 391                 }
 392                 if (code[0] == 0x0f && code[1] == 0x1f
 393                  && code[2] == 0x00) {
 394                         in_nop = 1;
 395                         code += 3;
 396                 }
 397                 if (code[0] == 0x0f && code[1] == 0x1f
 398                  && code[2] == 0x40 && code[3] == 0x00) {
 399                         in_nop = 1;
 400                         code += 4;
 401                 }
 402                 if (code[0] == 0x0f && code[1] == 0x1f
 403                  && code[2] == 0x44 && code[3] == 0x00
 404                  && code[4] == 0x00) {
 405                         in_nop = 1;
 406                         code += 5;
 407                 }
 408                 if (code[0] == 0x66 && code[1] == 0x0f
 409                  && code[2] == 0x1f && code[3] == 0x44
 410                  && code[4] == 0x00 && code[5] == 0x00) {
 411                         in_nop = 1;
 412                         code += 6;
 413                 }
 414                 if (code[0] == 0x0f && code[1] == 0x1f
 415                  && code[2] == 0x80 && code[3] == 0x00
 416                  && code[4] == 0x00 && code[5] == 0x00
 417                  && code[6] == 0x00) {
 418                         in_nop = 1;
 419                         code += 7;
 420                 }
 421                 if (code[0] == 0x0f && code[1] == 0x1f
 422                  && code[2] == 0x84 && code[3] == 0x00
 423                  && code[4] == 0x00 && code[5] == 0x00
 424                  && code[6] == 0x00 && code[7] == 0x00) {
 425                         in_nop = 1;
 426                         code += 8;
 427                 }
 428         } while ( in_nop );
 429         return code;
 430 }
 431
 432 guint8*
 433 mono_arch_nacl_skip_nops (guint8* code)
 434 {
 435   return amd64_skip_nops(code);
 436 }
 437
 438 #endif /*__native_client_codegen__*/
 439
 440 static inline void
 441 amd64_patch (unsigned char* code, gpointer target)
 442 {
 443         guint8 rex = 0;
 444
 445 #ifdef __native_client_codegen__
 446         code = amd64_skip_nops (code);
 447 #endif
 448 #if defined(__native_client_codegen__) && defined(__native_client__)
 449         if (nacl_is_code_address (code)) {
 450                 /* For tail calls, code is patched after being installed */
 451                 /* but not through the normal "patch callsite" method.   */
 452                 unsigned char buf[kNaClAlignment];
 453                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 454                 int ret;
 455                 memcpy (buf, aligned_code, kNaClAlignment);
 456                 /* Patch a temp buffer of bundle size, */
 457                 /* then install to actual location.    */
 458                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 459                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 460                 g_assert (ret == 0);
 461                 return;
 462         }
 463         target = nacl_modify_patch_target (target);
 464 #endif
 465
 466         /* Skip REX */
 467         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 468                 rex = code [0];
 469                 code += 1;
 470         }
 471
 472         if ((code [0] & 0xf8) == 0xb8) {
 473                 /* amd64_set_reg_template */
 474                 *(guint64*)(code + 1) = (guint64)target;
 475         }
 476         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 477                 /* mov 0(%rip), %dreg */
 478                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 479         }
 480         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 481                 /* call *<OFFSET>(%rip) */
 482                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 483         }
 484         else if (code [0] == 0xe8) {
 485                 /* call <DISP> */
 486                 gint64 disp = (guint8*)target - (guint8*)code;
 487                 g_assert (amd64_is_imm32 (disp));
 488                 x86_patch (code, (unsigned char*)target);
 489         }
 490         else
 491                 x86_patch (code, (unsigned char*)target);
 492 }
 493
 494 void
 495 mono_amd64_patch (unsigned char* code, gpointer target)
 496 {
 497         amd64_patch (code, target);
 498 }
 499
 500 typedef enum {
 501         ArgInIReg,
 502         ArgInFloatSSEReg,
 503         ArgInDoubleSSEReg,
 504         ArgOnStack,
 505         ArgValuetypeInReg,
 506         ArgValuetypeAddrInIReg,
 507         ArgNone /* only in pair_storage */
 508 } ArgStorage;
 509
 510 typedef struct {
 511         gint16 offset;
 512         gint8  reg;
 513         ArgStorage storage;
 514
 515         /* Only if storage == ArgValuetypeInReg */
 516         ArgStorage pair_storage [2];
 517         gint8 pair_regs [2];
 518         int nregs;
 519 } ArgInfo;
 520
 521 typedef struct {
 522         int nargs;
 523         guint32 stack_usage;
 524         guint32 reg_usage;
 525         guint32 freg_usage;
 526         gboolean need_stack_align;
 527         gboolean vtype_retaddr;
 528         /* The index of the vret arg in the argument list */
 529         int vret_arg_index;
 530         ArgInfo ret;
 531         ArgInfo sig_cookie;
 532         ArgInfo args [1];
 533 } CallInfo;
 534
 535 #define DEBUG(a) if (cfg->verbose_level > 1) a
 536
 537 #ifdef HOST_WIN32
 538 #define PARAM_REGS 4
 539
 540 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 541
 542 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 543 #else
 544 #define PARAM_REGS 6
 545
 546 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 547
 548  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 549 #endif
 550
 551 static void inline
 552 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 553 {
 554     ainfo->offset = *stack_size;
 555
 556     if (*gr >= PARAM_REGS) {
 557                 ainfo->storage = ArgOnStack;
 558                 /* Since the same stack slot size is used for all arg */
 559                 /*  types, it needs to be big enough to hold them all */
 560                 (*stack_size) += sizeof(mgreg_t);
 561     }
 562     else {
 563                 ainfo->storage = ArgInIReg;
 564                 ainfo->reg = param_regs [*gr];
 565                 (*gr) ++;
 566     }
 567 }
 568
 569 #ifdef HOST_WIN32
 570 #define FLOAT_PARAM_REGS 4
 571 #else
 572 #define FLOAT_PARAM_REGS 8
 573 #endif
 574
 575 static void inline
 576 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 577 {
 578     ainfo->offset = *stack_size;
 579
 580     if (*gr >= FLOAT_PARAM_REGS) {
 581                 ainfo->storage = ArgOnStack;
 582                 /* Since the same stack slot size is used for both float */
 583                 /*  types, it needs to be big enough to hold them both */
 584                 (*stack_size) += sizeof(mgreg_t);
 585     }
 586     else {
 587                 /* A double register */
 588                 if (is_double)
 589                         ainfo->storage = ArgInDoubleSSEReg;
 590                 else
 591                         ainfo->storage = ArgInFloatSSEReg;
 592                 ainfo->reg = *gr;
 593                 (*gr) += 1;
 594     }
 595 }
 596
 597 typedef enum ArgumentClass {
 598         ARG_CLASS_NO_CLASS,
 599         ARG_CLASS_MEMORY,
 600         ARG_CLASS_INTEGER,
 601         ARG_CLASS_SSE
 602 } ArgumentClass;
 603
 604 static ArgumentClass
 605 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 606 {
 607         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 608         MonoType *ptype;
 609
 610         ptype = mini_type_get_underlying_type (NULL, type);
 611         switch (ptype->type) {
 612         case MONO_TYPE_BOOLEAN:
 613         case MONO_TYPE_CHAR:
 614         case MONO_TYPE_I1:
 615         case MONO_TYPE_U1:
 616         case MONO_TYPE_I2:
 617         case MONO_TYPE_U2:
 618         case MONO_TYPE_I4:
 619         case MONO_TYPE_U4:
 620         case MONO_TYPE_I:
 621         case MONO_TYPE_U:
 622         case MONO_TYPE_STRING:
 623         case MONO_TYPE_OBJECT:
 624         case MONO_TYPE_CLASS:
 625         case MONO_TYPE_SZARRAY:
 626         case MONO_TYPE_PTR:
 627         case MONO_TYPE_FNPTR:
 628         case MONO_TYPE_ARRAY:
 629         case MONO_TYPE_I8:
 630         case MONO_TYPE_U8:
 631                 class2 = ARG_CLASS_INTEGER;
 632                 break;
 633         case MONO_TYPE_R4:
 634         case MONO_TYPE_R8:
 635 #ifdef HOST_WIN32
 636                 class2 = ARG_CLASS_INTEGER;
 637 #else
 638                 class2 = ARG_CLASS_SSE;
 639 #endif
 640                 break;
 641
 642         case MONO_TYPE_TYPEDBYREF:
 643                 g_assert_not_reached ();
 644
 645         case MONO_TYPE_GENERICINST:
 646                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 647                         class2 = ARG_CLASS_INTEGER;
 648                         break;
 649                 }
 650                 /* fall through */
 651         case MONO_TYPE_VALUETYPE: {
 652                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 653                 int i;
 654
 655                 for (i = 0; i < info->num_fields; ++i) {
 656                         class2 = class1;
 657                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 658                 }
 659                 break;
 660         }
 661         default:
 662                 g_assert_not_reached ();
 663         }
 664
 665         /* Merge */
 666         if (class1 == class2)
 667                 ;
 668         else if (class1 == ARG_CLASS_NO_CLASS)
 669                 class1 = class2;
 670         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 671                 class1 = ARG_CLASS_MEMORY;
 672         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 673                 class1 = ARG_CLASS_INTEGER;
 674         else
 675                 class1 = ARG_CLASS_SSE;
 676
 677         return class1;
 678 }
 679 #ifdef __native_client_codegen__
 680 const guint kNaClAlignment = kNaClAlignmentAMD64;
 681 const guint kNaClAlignmentMask = kNaClAlignmentMaskAMD64;
 682
 683 /* Default alignment for Native Client is 32-byte. */
 684 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 685
 686 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 687 /* Check that alignment doesn't cross an alignment boundary.             */
 688 guint8*
 689 mono_arch_nacl_pad(guint8 *code, int pad)
 690 {
 691         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 692
 693         if (pad == 0) return code;
 694         /* assertion: alignment cannot cross a block boundary */
 695         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 696                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 697         while (pad >= kMaxPadding) {
 698                 amd64_padding (code, kMaxPadding);
 699                 pad -= kMaxPadding;
 700         }
 701         if (pad != 0) amd64_padding (code, pad);
 702         return code;
 703 }
 704 #endif
 705
 706 static void
 707 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 708                            gboolean is_return,
 709                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 710 {
 711         guint32 size, quad, nquads, i;
 712         /* Keep track of the size used in each quad so we can */
 713         /* use the right size when copying args/return vars.  */
 714         guint32 quadsize [2] = {8, 8};
 715         ArgumentClass args [2];
 716         MonoMarshalType *info = NULL;
 717         MonoClass *klass;
 718         MonoGenericSharingContext tmp_gsctx;
 719         gboolean pass_on_stack = FALSE;
 720
 721         /*
 722          * The gsctx currently contains no data, it is only used for checking whenever
 723          * open types are allowed, some callers like mono_arch_get_argument_info ()
 724          * don't pass it to us, so work around that.
 725          */
 726         if (!gsctx)
 727                 gsctx = &tmp_gsctx;
 728
 729         klass = mono_class_from_mono_type (type);
 730         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 731 #ifndef HOST_WIN32
 732         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 733                 /* We pass and return vtypes of size 8 in a register */
 734         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 735                 pass_on_stack = TRUE;
 736         }
 737 #else
 738         if (!sig->pinvoke) {
 739                 pass_on_stack = TRUE;
 740         }
 741 #endif
 742
 743         /* If this struct can't be split up naturally into 8-byte */
 744         /* chunks (registers), pass it on the stack.              */
 745         if (sig->pinvoke && !pass_on_stack) {
 746                 guint32 align;
 747                 guint32 field_size;
 748
 749                 info = mono_marshal_load_type_info (klass);
 750                 g_assert(info);
 751                 for (i = 0; i < info->num_fields; ++i) {
 752                         field_size = mono_marshal_type_size (info->fields [i].field->type,
 753                                                            info->fields [i].mspec,
 754                                                            &align, TRUE, klass->unicode);
 755                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
 756                                 pass_on_stack = TRUE;
 757                                 break;
 758                         }
 759                 }
 760         }
 761
 762         if (pass_on_stack) {
 763                 /* Allways pass in memory */
 764                 ainfo->offset = *stack_size;
 765                 *stack_size += ALIGN_TO (size, 8);
 766                 ainfo->storage = ArgOnStack;
 767
 768                 return;
 769         }
 770
 771         /* FIXME: Handle structs smaller than 8 bytes */
 772         //if ((size % 8) != 0)
 773         //      NOT_IMPLEMENTED;
 774
 775         if (size > 8)
 776                 nquads = 2;
 777         else
 778                 nquads = 1;
 779
 780         if (!sig->pinvoke) {
 781                 /* Always pass in 1 or 2 integer registers */
 782                 args [0] = ARG_CLASS_INTEGER;
 783                 args [1] = ARG_CLASS_INTEGER;
 784                 /* Only the simplest cases are supported */
 785                 if (is_return && nquads != 1) {
 786                         args [0] = ARG_CLASS_MEMORY;
 787                         args [1] = ARG_CLASS_MEMORY;
 788                 }
 789         } else {
 790                 /*
 791                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 792                  * The X87 and SSEUP stuff is left out since there are no such types in
 793                  * the CLR.
 794                  */
 795                 info = mono_marshal_load_type_info (klass);
 796                 g_assert (info);
 797
 798 #ifndef HOST_WIN32
 799                 if (info->native_size > 16) {
 800                         ainfo->offset = *stack_size;
 801                         *stack_size += ALIGN_TO (info->native_size, 8);
 802                         ainfo->storage = ArgOnStack;
 803
 804                         return;
 805                 }
 806 #else
 807                 switch (info->native_size) {
 808                 case 1: case 2: case 4: case 8:
 809                         break;
 810                 default:
 811                         if (is_return) {
 812                                 ainfo->storage = ArgOnStack;
 813                                 ainfo->offset = *stack_size;
 814                                 *stack_size += ALIGN_TO (info->native_size, 8);
 815                         }
 816                         else {
 817                                 ainfo->storage = ArgValuetypeAddrInIReg;
 818
 819                                 if (*gr < PARAM_REGS) {
 820                                         ainfo->pair_storage [0] = ArgInIReg;
 821                                         ainfo->pair_regs [0] = param_regs [*gr];
 822                                         (*gr) ++;
 823                                 }
 824                                 else {
 825                                         ainfo->pair_storage [0] = ArgOnStack;
 826                                         ainfo->offset = *stack_size;
 827                                         *stack_size += 8;
 828                                 }
 829                         }
 830
 831                         return;
 832                 }
 833 #endif
 834
 835                 args [0] = ARG_CLASS_NO_CLASS;
 836                 args [1] = ARG_CLASS_NO_CLASS;
 837                 for (quad = 0; quad < nquads; ++quad) {
 838                         int size;
 839                         guint32 align;
 840                         ArgumentClass class1;
 841
 842                         if (info->num_fields == 0)
 843                                 class1 = ARG_CLASS_MEMORY;
 844                         else
 845                                 class1 = ARG_CLASS_NO_CLASS;
 846                         for (i = 0; i < info->num_fields; ++i) {
 847                                 size = mono_marshal_type_size (info->fields [i].field->type,
 848                                                                                            info->fields [i].mspec,
 849                                                                                            &align, TRUE, klass->unicode);
 850                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 851                                         /* Unaligned field */
 852                                         NOT_IMPLEMENTED;
 853                                 }
 854
 855                                 /* Skip fields in other quad */
 856                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 857                                         continue;
 858                                 if ((quad == 1) && (info->fields [i].offset < 8))
 859                                         continue;
 860
 861                                 /* How far into this quad this data extends.*/
 862                                 /* (8 is size of quad) */
 863                                 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
 864
 865                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 866                         }
 867                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 868                         args [quad] = class1;
 869                 }
 870         }
 871
 872         /* Post merger cleanup */
 873         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 874                 args [0] = args [1] = ARG_CLASS_MEMORY;
 875
 876         /* Allocate registers */
 877         {
 878                 int orig_gr = *gr;
 879                 int orig_fr = *fr;
 880
 881                 ainfo->storage = ArgValuetypeInReg;
 882                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 883                 ainfo->nregs = nquads;
 884                 for (quad = 0; quad < nquads; ++quad) {
 885                         switch (args [quad]) {
 886                         case ARG_CLASS_INTEGER:
 887                                 if (*gr >= PARAM_REGS)
 888                                         args [quad] = ARG_CLASS_MEMORY;
 889                                 else {
 890                                         ainfo->pair_storage [quad] = ArgInIReg;
 891                                         if (is_return)
 892                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 893                                         else
 894                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 895                                         (*gr) ++;
 896                                 }
 897                                 break;
 898                         case ARG_CLASS_SSE:
 899                                 if (*fr >= FLOAT_PARAM_REGS)
 900                                         args [quad] = ARG_CLASS_MEMORY;
 901                                 else {
 902                                         if (quadsize[quad] <= 4)
 903                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 904                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 905                                         ainfo->pair_regs [quad] = *fr;
 906                                         (*fr) ++;
 907                                 }
 908                                 break;
 909                         case ARG_CLASS_MEMORY:
 910                                 break;
 911                         default:
 912                                 g_assert_not_reached ();
 913                         }
 914                 }
 915
 916                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 917                         /* Revert possible register assignments */
 918                         *gr = orig_gr;
 919                         *fr = orig_fr;
 920
 921                         ainfo->offset = *stack_size;
 922                         if (sig->pinvoke)
 923                                 *stack_size += ALIGN_TO (info->native_size, 8);
 924                         else
 925                                 *stack_size += nquads * sizeof(mgreg_t);
 926                         ainfo->storage = ArgOnStack;
 927                 }
 928         }
 929 }
 930
 931 /*
 932  * get_call_info:
 933  *
 934  *  Obtain information about a call according to the calling convention.
 935  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 936  * Draft Version 0.23" document for more information.
 937  */
 938 static CallInfo*
 939 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 940 {
 941         guint32 i, gr, fr, pstart;
 942         MonoType *ret_type;
 943         int n = sig->hasthis + sig->param_count;
 944         guint32 stack_size = 0;
 945         CallInfo *cinfo;
 946         gboolean is_pinvoke = sig->pinvoke;
 947
 948         if (mp)
 949                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 950         else
 951                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 952
 953         cinfo->nargs = n;
 954
 955         gr = 0;
 956         fr = 0;
 957
 958         /* return value */
 959         {
 960                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 961                 switch (ret_type->type) {
 962                 case MONO_TYPE_BOOLEAN:
 963                 case MONO_TYPE_I1:
 964                 case MONO_TYPE_U1:
 965                 case MONO_TYPE_I2:
 966                 case MONO_TYPE_U2:
 967                 case MONO_TYPE_CHAR:
 968                 case MONO_TYPE_I4:
 969                 case MONO_TYPE_U4:
 970                 case MONO_TYPE_I:
 971                 case MONO_TYPE_U:
 972                 case MONO_TYPE_PTR:
 973                 case MONO_TYPE_FNPTR:
 974                 case MONO_TYPE_CLASS:
 975                 case MONO_TYPE_OBJECT:
 976                 case MONO_TYPE_SZARRAY:
 977                 case MONO_TYPE_ARRAY:
 978                 case MONO_TYPE_STRING:
 979                         cinfo->ret.storage = ArgInIReg;
 980                         cinfo->ret.reg = AMD64_RAX;
 981                         break;
 982                 case MONO_TYPE_U8:
 983                 case MONO_TYPE_I8:
 984                         cinfo->ret.storage = ArgInIReg;
 985                         cinfo->ret.reg = AMD64_RAX;
 986                         break;
 987                 case MONO_TYPE_R4:
 988                         cinfo->ret.storage = ArgInFloatSSEReg;
 989                         cinfo->ret.reg = AMD64_XMM0;
 990                         break;
 991                 case MONO_TYPE_R8:
 992                         cinfo->ret.storage = ArgInDoubleSSEReg;
 993                         cinfo->ret.reg = AMD64_XMM0;
 994                         break;
 995                 case MONO_TYPE_GENERICINST:
 996                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 997                                 cinfo->ret.storage = ArgInIReg;
 998                                 cinfo->ret.reg = AMD64_RAX;
 999                                 break;
1000                         }
1001                         /* fall through */
1002                 case MONO_TYPE_VALUETYPE: {
1003                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1004
1005                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1006                         if (cinfo->ret.storage == ArgOnStack) {
1007                                 cinfo->vtype_retaddr = TRUE;
1008                                 /* The caller passes the address where the value is stored */
1009                         }
1010                         break;
1011                 }
1012                 case MONO_TYPE_TYPEDBYREF:
1013                         /* Same as a valuetype with size 24 */
1014                         cinfo->vtype_retaddr = TRUE;
1015                         break;
1016                 case MONO_TYPE_VOID:
1017                         break;
1018                 default:
1019                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
1020                 }
1021         }
1022
1023         pstart = 0;
1024         /*
1025          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1026          * the first argument, allowing 'this' to be always passed in the first arg reg.
1027          * Also do this if the first argument is a reference type, since virtual calls
1028          * are sometimes made using calli without sig->hasthis set, like in the delegate
1029          * invoke wrappers.
1030          */
1031         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1032                 if (sig->hasthis) {
1033                         add_general (&gr, &stack_size, cinfo->args + 0);
1034                 } else {
1035                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1036                         pstart = 1;
1037                 }
1038                 add_general (&gr, &stack_size, &cinfo->ret);
1039                 cinfo->vret_arg_index = 1;
1040         } else {
1041                 /* this */
1042                 if (sig->hasthis)
1043                         add_general (&gr, &stack_size, cinfo->args + 0);
1044
1045                 if (cinfo->vtype_retaddr)
1046                         add_general (&gr, &stack_size, &cinfo->ret);
1047         }
1048
1049         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1050                 gr = PARAM_REGS;
1051                 fr = FLOAT_PARAM_REGS;
1052
1053                 /* Emit the signature cookie just before the implicit arguments */
1054                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1055         }
1056
1057         for (i = pstart; i < sig->param_count; ++i) {
1058                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1059                 MonoType *ptype;
1060
1061 #ifdef HOST_WIN32
1062                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1063                 if (gr > fr)
1064                         fr = gr;
1065                 else if (fr > gr)
1066                         gr = fr;
1067 #endif
1068
1069                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1070                         /* We allways pass the sig cookie on the stack for simplicity */
1071                         /*
1072                          * Prevent implicit arguments + the sig cookie from being passed
1073                          * in registers.
1074                          */
1075                         gr = PARAM_REGS;
1076                         fr = FLOAT_PARAM_REGS;
1077
1078                         /* Emit the signature cookie just before the implicit arguments */
1079                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1080                 }
1081
1082                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1083                 switch (ptype->type) {
1084                 case MONO_TYPE_BOOLEAN:
1085                 case MONO_TYPE_I1:
1086                 case MONO_TYPE_U1:
1087                         add_general (&gr, &stack_size, ainfo);
1088                         break;
1089                 case MONO_TYPE_I2:
1090                 case MONO_TYPE_U2:
1091                 case MONO_TYPE_CHAR:
1092                         add_general (&gr, &stack_size, ainfo);
1093                         break;
1094                 case MONO_TYPE_I4:
1095                 case MONO_TYPE_U4:
1096                         add_general (&gr, &stack_size, ainfo);
1097                         break;
1098                 case MONO_TYPE_I:
1099                 case MONO_TYPE_U:
1100                 case MONO_TYPE_PTR:
1101                 case MONO_TYPE_FNPTR:
1102                 case MONO_TYPE_CLASS:
1103                 case MONO_TYPE_OBJECT:
1104                 case MONO_TYPE_STRING:
1105                 case MONO_TYPE_SZARRAY:
1106                 case MONO_TYPE_ARRAY:
1107                         add_general (&gr, &stack_size, ainfo);
1108                         break;
1109                 case MONO_TYPE_GENERICINST:
1110                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1111                                 add_general (&gr, &stack_size, ainfo);
1112                                 break;
1113                         }
1114                         /* fall through */
1115                 case MONO_TYPE_VALUETYPE:
1116                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1117                         break;
1118                 case MONO_TYPE_TYPEDBYREF:
1119 #ifdef HOST_WIN32
1120                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1121 #else
1122                         stack_size += sizeof (MonoTypedRef);
1123                         ainfo->storage = ArgOnStack;
1124 #endif
1125                         break;
1126                 case MONO_TYPE_U8:
1127                 case MONO_TYPE_I8:
1128                         add_general (&gr, &stack_size, ainfo);
1129                         break;
1130                 case MONO_TYPE_R4:
1131                         add_float (&fr, &stack_size, ainfo, FALSE);
1132                         break;
1133                 case MONO_TYPE_R8:
1134                         add_float (&fr, &stack_size, ainfo, TRUE);
1135                         break;
1136                 default:
1137                         g_assert_not_reached ();
1138                 }
1139         }
1140
1141         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1142                 gr = PARAM_REGS;
1143                 fr = FLOAT_PARAM_REGS;
1144
1145                 /* Emit the signature cookie just before the implicit arguments */
1146                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1147         }
1148
1149 #ifdef HOST_WIN32
1150         // There always is 32 bytes reserved on the stack when calling on Winx64
1151         stack_size += 0x20;
1152 #endif
1153
1154 #ifndef MONO_AMD64_NO_PUSHES
1155         if (stack_size & 0x8) {
1156                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1157                 cinfo->need_stack_align = TRUE;
1158                 stack_size += 8;
1159         }
1160 #endif
1161
1162         cinfo->stack_usage = stack_size;
1163         cinfo->reg_usage = gr;
1164         cinfo->freg_usage = fr;
1165         return cinfo;
1166 }
1167
1168 /*
1169  * mono_arch_get_argument_info:
1170  * @csig:  a method signature
1171  * @param_count: the number of parameters to consider
1172  * @arg_info: an array to store the result infos
1173  *
1174  * Gathers information on parameters such as size, alignment and
1175  * padding. arg_info should be large enought to hold param_count + 1 entries.
1176  *
1177  * Returns the size of the argument area on the stack.
1178  */
1179 int
1180 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1181 {
1182         int k;
1183         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1184         guint32 args_size = cinfo->stack_usage;
1185
1186         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1187         if (csig->hasthis) {
1188                 arg_info [0].offset = 0;
1189         }
1190
1191         for (k = 0; k < param_count; k++) {
1192                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1193                 /* FIXME: */
1194                 arg_info [k + 1].size = 0;
1195         }
1196
1197         g_free (cinfo);
1198
1199         return args_size;
1200 }
1201
1202 gboolean
1203 mono_amd64_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1204 {
1205         CallInfo *c1, *c2;
1206         gboolean res;
1207
1208         c1 = get_call_info (NULL, NULL, caller_sig);
1209         c2 = get_call_info (NULL, NULL, callee_sig);
1210         res = c1->stack_usage >= c2->stack_usage;
1211         if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
1212                 /* An address on the callee's stack is passed as the first argument */
1213                 res = FALSE;
1214
1215         g_free (c1);
1216         g_free (c2);
1217
1218         return res;
1219 }
1220
1221 static int
1222 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
1223 {
1224 #if defined(MONO_CROSS_COMPILE)
1225         return 0;
1226 #else
1227 #ifndef _MSC_VER
1228         __asm__ __volatile__ ("cpuid"
1229                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
1230                 : "a" (id));
1231 #else
1232         int info[4];
1233         __cpuid(info, id);
1234         *p_eax = info[0];
1235         *p_ebx = info[1];
1236         *p_ecx = info[2];
1237         *p_edx = info[3];
1238 #endif
1239         return 1;
1240 #endif
1241 }
1242
1243 /*
1244  * Initialize the cpu to execute managed code.
1245  */
1246 void
1247 mono_arch_cpu_init (void)
1248 {
1249 #ifndef _MSC_VER
1250         guint16 fpcw;
1251
1252         /* spec compliance requires running with double precision */
1253         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1254         fpcw &= ~X86_FPCW_PRECC_MASK;
1255         fpcw |= X86_FPCW_PREC_DOUBLE;
1256         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1257         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1258 #else
1259         /* TODO: This is crashing on Win64 right now.
1260         * _control87 (_PC_53, MCW_PC);
1261         */
1262 #endif
1263 }
1264
1265 /*
1266  * Initialize architecture specific code.
1267  */
1268 void
1269 mono_arch_init (void)
1270 {
1271         int flags;
1272
1273         InitializeCriticalSection (&mini_arch_mutex);
1274 #if defined(__native_client_codegen__)
1275         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1276         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1277         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1278         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1279 #endif
1280
1281 #ifdef MONO_ARCH_NOMAP32BIT
1282         flags = MONO_MMAP_READ;
1283         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1284         breakpoint_size = 13;
1285         breakpoint_fault_size = 3;
1286 #else
1287         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1288         /* amd64_mov_reg_mem () */
1289         breakpoint_size = 8;
1290         breakpoint_fault_size = 8;
1291 #endif
1292
1293         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1294         single_step_fault_size = 4;
1295
1296         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1297         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1298         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1299
1300         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1301         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1302         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1303 }
1304
1305 /*
1306  * Cleanup architecture specific code.
1307  */
1308 void
1309 mono_arch_cleanup (void)
1310 {
1311         DeleteCriticalSection (&mini_arch_mutex);
1312 #if defined(__native_client_codegen__)
1313         mono_native_tls_free (nacl_instruction_depth);
1314         mono_native_tls_free (nacl_rex_tag);
1315         mono_native_tls_free (nacl_legacy_prefix_tag);
1316 #endif
1317 }
1318
1319 /*
1320  * This function returns the optimizations supported on this cpu.
1321  */
1322 guint32
1323 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1324 {
1325         int eax, ebx, ecx, edx;
1326         guint32 opts = 0;
1327
1328         *exclude_mask = 0;
1329         /* Feature Flags function, flags returned in EDX. */
1330         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1331                 if (edx & (1 << 15)) {
1332                         opts |= MONO_OPT_CMOV;
1333                         if (edx & 1)
1334                                 opts |= MONO_OPT_FCMOV;
1335                         else
1336                                 *exclude_mask |= MONO_OPT_FCMOV;
1337                 } else
1338                         *exclude_mask |= MONO_OPT_CMOV;
1339         }
1340
1341         return opts;
1342 }
1343
1344 /*
1345  * This function test for all SSE functions supported.
1346  *
1347  * Returns a bitmask corresponding to all supported versions.
1348  *
1349  */
1350 guint32
1351 mono_arch_cpu_enumerate_simd_versions (void)
1352 {
1353         int eax, ebx, ecx, edx;
1354         guint32 sse_opts = 0;
1355
1356         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1357                 if (edx & (1 << 25))
1358                         sse_opts |= SIMD_VERSION_SSE1;
1359                 if (edx & (1 << 26))
1360                         sse_opts |= SIMD_VERSION_SSE2;
1361                 if (ecx & (1 << 0))
1362                         sse_opts |= SIMD_VERSION_SSE3;
1363                 if (ecx & (1 << 9))
1364                         sse_opts |= SIMD_VERSION_SSSE3;
1365                 if (ecx & (1 << 19))
1366                         sse_opts |= SIMD_VERSION_SSE41;
1367                 if (ecx & (1 << 20))
1368                         sse_opts |= SIMD_VERSION_SSE42;
1369         }
1370
1371         /* Yes, all this needs to be done to check for sse4a.
1372            See: "Amd: CPUID Specification"
1373          */
1374         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1375                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1376                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1377                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1378                         if (ecx & (1 << 6))
1379                                 sse_opts |= SIMD_VERSION_SSE4a;
1380                 }
1381         }
1382
1383         return sse_opts;
1384 }
1385
1386 #ifndef DISABLE_JIT
1387
1388 GList *
1389 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1390 {
1391         GList *vars = NULL;
1392         int i;
1393
1394         for (i = 0; i < cfg->num_varinfo; i++) {
1395                 MonoInst *ins = cfg->varinfo [i];
1396                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1397
1398                 /* unused vars */
1399                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1400                         continue;
1401
1402                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1403                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1404                         continue;
1405
1406                 if (mono_is_regsize_var (ins->inst_vtype)) {
1407                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1408                         g_assert (i == vmv->idx);
1409                         vars = g_list_prepend (vars, vmv);
1410                 }
1411         }
1412
1413         vars = mono_varlist_sort (cfg, vars, 0);
1414
1415         return vars;
1416 }
1417
1418 /**
1419  * mono_arch_compute_omit_fp:
1420  *
1421  *   Determine whenever the frame pointer can be eliminated.
1422  */
1423 static void
1424 mono_arch_compute_omit_fp (MonoCompile *cfg)
1425 {
1426         MonoMethodSignature *sig;
1427         MonoMethodHeader *header;
1428         int i, locals_size;
1429         CallInfo *cinfo;
1430
1431         if (cfg->arch.omit_fp_computed)
1432                 return;
1433
1434         header = cfg->header;
1435
1436         sig = mono_method_signature (cfg->method);
1437
1438         if (!cfg->arch.cinfo)
1439                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1440         cinfo = cfg->arch.cinfo;
1441
1442         /*
1443          * FIXME: Remove some of the restrictions.
1444          */
1445         cfg->arch.omit_fp = TRUE;
1446         cfg->arch.omit_fp_computed = TRUE;
1447
1448 #ifdef __native_client_codegen__
1449         /* NaCl modules may not change the value of RBP, so it cannot be */
1450         /* used as a normal register, but it can be used as a frame pointer*/
1451         cfg->disable_omit_fp = TRUE;
1452         cfg->arch.omit_fp = FALSE;
1453 #endif
1454
1455         if (cfg->disable_omit_fp)
1456                 cfg->arch.omit_fp = FALSE;
1457
1458         if (!debug_omit_fp ())
1459                 cfg->arch.omit_fp = FALSE;
1460         /*
1461         if (cfg->method->save_lmf)
1462                 cfg->arch.omit_fp = FALSE;
1463         */
1464         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1465                 cfg->arch.omit_fp = FALSE;
1466         if (header->num_clauses)
1467                 cfg->arch.omit_fp = FALSE;
1468         if (cfg->param_area)
1469                 cfg->arch.omit_fp = FALSE;
1470         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1471                 cfg->arch.omit_fp = FALSE;
1472         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1473                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1474                 cfg->arch.omit_fp = FALSE;
1475         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1476                 ArgInfo *ainfo = &cinfo->args [i];
1477
1478                 if (ainfo->storage == ArgOnStack) {
1479                         /*
1480                          * The stack offset can only be determined when the frame
1481                          * size is known.
1482                          */
1483                         cfg->arch.omit_fp = FALSE;
1484                 }
1485         }
1486
1487         locals_size = 0;
1488         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1489                 MonoInst *ins = cfg->varinfo [i];
1490                 int ialign;
1491
1492                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1493         }
1494 }
1495
1496 GList *
1497 mono_arch_get_global_int_regs (MonoCompile *cfg)
1498 {
1499         GList *regs = NULL;
1500
1501         mono_arch_compute_omit_fp (cfg);
1502
1503         if (cfg->globalra) {
1504                 if (cfg->arch.omit_fp)
1505                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1506
1507                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1508                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1509                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1510                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1511 #ifndef __native_client_codegen__
1512                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1513 #endif
1514
1515                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1516                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1517                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1518                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1519                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1522                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1523         } else {
1524                 if (cfg->arch.omit_fp)
1525                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1526
1527                 /* We use the callee saved registers for global allocation */
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1531                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1532 #ifndef __native_client_codegen__
1533                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1534 #endif
1535 #ifdef HOST_WIN32
1536                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1537                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1538 #endif
1539         }
1540
1541         return regs;
1542 }
1543
1544 GList*
1545 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1546 {
1547         GList *regs = NULL;
1548         int i;
1549
1550         /* All XMM registers */
1551         for (i = 0; i < 16; ++i)
1552                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1553
1554         return regs;
1555 }
1556
1557 GList*
1558 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1559 {
1560         static GList *r = NULL;
1561
1562         if (r == NULL) {
1563                 GList *regs = NULL;
1564
1565                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1566                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1567                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1568                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1569                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1570 #ifndef __native_client_codegen__
1571                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1572 #endif
1573
1574                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1575                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1576                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1577                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1581                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1582
1583                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1584         }
1585
1586         return r;
1587 }
1588
1589 GList*
1590 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1591 {
1592         int i;
1593         static GList *r = NULL;
1594
1595         if (r == NULL) {
1596                 GList *regs = NULL;
1597
1598                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1599                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1600
1601                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1602         }
1603
1604         return r;
1605 }
1606
1607 /*
1608  * mono_arch_regalloc_cost:
1609  *
1610  *  Return the cost, in number of memory references, of the action of
1611  * allocating the variable VMV into a register during global register
1612  * allocation.
1613  */
1614 guint32
1615 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1616 {
1617         MonoInst *ins = cfg->varinfo [vmv->idx];
1618
1619         if (cfg->method->save_lmf)
1620                 /* The register is already saved */
1621                 /* substract 1 for the invisible store in the prolog */
1622                 return (ins->opcode == OP_ARG) ? 0 : 1;
1623         else
1624                 /* push+pop */
1625                 return (ins->opcode == OP_ARG) ? 1 : 2;
1626 }
1627
1628 /*
1629  * mono_arch_fill_argument_info:
1630  *
1631  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1632  * of the method.
1633  */
1634 void
1635 mono_arch_fill_argument_info (MonoCompile *cfg)
1636 {
1637         MonoMethodSignature *sig;
1638         MonoMethodHeader *header;
1639         MonoInst *ins;
1640         int i;
1641         CallInfo *cinfo;
1642
1643         header = cfg->header;
1644
1645         sig = mono_method_signature (cfg->method);
1646
1647         cinfo = cfg->arch.cinfo;
1648
1649         /*
1650          * Contrary to mono_arch_allocate_vars (), the information should describe
1651          * where the arguments are at the beginning of the method, not where they can be
1652          * accessed during the execution of the method. The later makes no sense for the
1653          * global register allocator, since a variable can be in more than one location.
1654          */
1655         if (sig->ret->type != MONO_TYPE_VOID) {
1656                 switch (cinfo->ret.storage) {
1657                 case ArgInIReg:
1658                 case ArgInFloatSSEReg:
1659                 case ArgInDoubleSSEReg:
1660                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1661                                 cfg->vret_addr->opcode = OP_REGVAR;
1662                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1663                         }
1664                         else {
1665                                 cfg->ret->opcode = OP_REGVAR;
1666                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1667                         }
1668                         break;
1669                 case ArgValuetypeInReg:
1670                         cfg->ret->opcode = OP_REGOFFSET;
1671                         cfg->ret->inst_basereg = -1;
1672                         cfg->ret->inst_offset = -1;
1673                         break;
1674                 default:
1675                         g_assert_not_reached ();
1676                 }
1677         }
1678
1679         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1680                 ArgInfo *ainfo = &cinfo->args [i];
1681                 MonoType *arg_type;
1682
1683                 ins = cfg->args [i];
1684
1685                 if (sig->hasthis && (i == 0))
1686                         arg_type = &mono_defaults.object_class->byval_arg;
1687                 else
1688                         arg_type = sig->params [i - sig->hasthis];
1689
1690                 switch (ainfo->storage) {
1691                 case ArgInIReg:
1692                 case ArgInFloatSSEReg:
1693                 case ArgInDoubleSSEReg:
1694                         ins->opcode = OP_REGVAR;
1695                         ins->inst_c0 = ainfo->reg;
1696                         break;
1697                 case ArgOnStack:
1698                         ins->opcode = OP_REGOFFSET;
1699                         ins->inst_basereg = -1;
1700                         ins->inst_offset = -1;
1701                         break;
1702                 case ArgValuetypeInReg:
1703                         /* Dummy */
1704                         ins->opcode = OP_NOP;
1705                         break;
1706                 default:
1707                         g_assert_not_reached ();
1708                 }
1709         }
1710 }
1711
1712 void
1713 mono_arch_allocate_vars (MonoCompile *cfg)
1714 {
1715         MonoMethodSignature *sig;
1716         MonoMethodHeader *header;
1717         MonoInst *ins;
1718         int i, offset;
1719         guint32 locals_stack_size, locals_stack_align;
1720         gint32 *offsets;
1721         CallInfo *cinfo;
1722
1723         header = cfg->header;
1724
1725         sig = mono_method_signature (cfg->method);
1726
1727         cinfo = cfg->arch.cinfo;
1728
1729         mono_arch_compute_omit_fp (cfg);
1730
1731         /*
1732          * We use the ABI calling conventions for managed code as well.
1733          * Exception: valuetypes are only sometimes passed or returned in registers.
1734          */
1735
1736         /*
1737          * The stack looks like this:
1738          * <incoming arguments passed on the stack>
1739          * <return value>
1740          * <lmf/caller saved registers>
1741          * <locals>
1742          * <spill area>
1743          * <localloc area>  -> grows dynamically
1744          * <params area>
1745          */
1746
1747         if (cfg->arch.omit_fp) {
1748                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1749                 cfg->frame_reg = AMD64_RSP;
1750                 offset = 0;
1751         } else {
1752                 /* Locals are allocated backwards from %fp */
1753                 cfg->frame_reg = AMD64_RBP;
1754                 offset = 0;
1755         }
1756
1757         if (cfg->method->save_lmf) {
1758                 /* The LMF var is allocated normally */
1759         } else {
1760                 if (cfg->arch.omit_fp)
1761                         cfg->arch.reg_save_area_offset = offset;
1762                 /* Reserve space for callee saved registers */
1763                 for (i = 0; i < AMD64_NREG; ++i)
1764                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1765                                 offset += sizeof(mgreg_t);
1766                         }
1767         }
1768
1769         if (sig->ret->type != MONO_TYPE_VOID) {
1770                 switch (cinfo->ret.storage) {
1771                 case ArgInIReg:
1772                 case ArgInFloatSSEReg:
1773                 case ArgInDoubleSSEReg:
1774                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1775                                 if (cfg->globalra) {
1776                                         cfg->vret_addr->opcode = OP_REGVAR;
1777                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1778                                 } else {
1779                                         /* The register is volatile */
1780                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1781                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1782                                         if (cfg->arch.omit_fp) {
1783                                                 cfg->vret_addr->inst_offset = offset;
1784                                                 offset += 8;
1785                                         } else {
1786                                                 offset += 8;
1787                                                 cfg->vret_addr->inst_offset = -offset;
1788                                         }
1789                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1790                                                 printf ("vret_addr =");
1791                                                 mono_print_ins (cfg->vret_addr);
1792                                         }
1793                                 }
1794                         }
1795                         else {
1796                                 cfg->ret->opcode = OP_REGVAR;
1797                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1798                         }
1799                         break;
1800                 case ArgValuetypeInReg:
1801                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1802                         cfg->ret->opcode = OP_REGOFFSET;
1803                         cfg->ret->inst_basereg = cfg->frame_reg;
1804                         if (cfg->arch.omit_fp) {
1805                                 cfg->ret->inst_offset = offset;
1806                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1807                         } else {
1808                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1809                                 cfg->ret->inst_offset = - offset;
1810                         }
1811                         break;
1812                 default:
1813                         g_assert_not_reached ();
1814                 }
1815                 if (!cfg->globalra)
1816                         cfg->ret->dreg = cfg->ret->inst_c0;
1817         }
1818
1819         /* Allocate locals */
1820         if (!cfg->globalra) {
1821                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1822                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1823                         char *mname = mono_method_full_name (cfg->method, TRUE);
1824                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1825                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1826                         g_free (mname);
1827                         return;
1828                 }
1829
1830                 if (locals_stack_align) {
1831                         offset += (locals_stack_align - 1);
1832                         offset &= ~(locals_stack_align - 1);
1833                 }
1834                 if (cfg->arch.omit_fp) {
1835                         cfg->locals_min_stack_offset = offset;
1836                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1837                 } else {
1838                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1839                         cfg->locals_max_stack_offset = - offset;
1840                 }
1841
1842                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1843                         if (offsets [i] != -1) {
1844                                 MonoInst *ins = cfg->varinfo [i];
1845                                 ins->opcode = OP_REGOFFSET;
1846                                 ins->inst_basereg = cfg->frame_reg;
1847                                 if (cfg->arch.omit_fp)
1848                                         ins->inst_offset = (offset + offsets [i]);
1849                                 else
1850                                         ins->inst_offset = - (offset + offsets [i]);
1851                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1852                         }
1853                 }
1854                 offset += locals_stack_size;
1855         }
1856
1857         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1858                 g_assert (!cfg->arch.omit_fp);
1859                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1860                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1861         }
1862
1863         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1864                 ins = cfg->args [i];
1865                 if (ins->opcode != OP_REGVAR) {
1866                         ArgInfo *ainfo = &cinfo->args [i];
1867                         gboolean inreg = TRUE;
1868                         MonoType *arg_type;
1869
1870                         if (sig->hasthis && (i == 0))
1871                                 arg_type = &mono_defaults.object_class->byval_arg;
1872                         else
1873                                 arg_type = sig->params [i - sig->hasthis];
1874
1875                         if (cfg->globalra) {
1876                                 /* The new allocator needs info about the original locations of the arguments */
1877                                 switch (ainfo->storage) {
1878                                 case ArgInIReg:
1879                                 case ArgInFloatSSEReg:
1880                                 case ArgInDoubleSSEReg:
1881                                         ins->opcode = OP_REGVAR;
1882                                         ins->inst_c0 = ainfo->reg;
1883                                         break;
1884                                 case ArgOnStack:
1885                                         g_assert (!cfg->arch.omit_fp);
1886                                         ins->opcode = OP_REGOFFSET;
1887                                         ins->inst_basereg = cfg->frame_reg;
1888                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1889                                         break;
1890                                 case ArgValuetypeInReg:
1891                                         ins->opcode = OP_REGOFFSET;
1892                                         ins->inst_basereg = cfg->frame_reg;
1893                                         /* These arguments are saved to the stack in the prolog */
1894                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1895                                         if (cfg->arch.omit_fp) {
1896                                                 ins->inst_offset = offset;
1897                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1898                                         } else {
1899                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1900                                                 ins->inst_offset = - offset;
1901                                         }
1902                                         break;
1903                                 default:
1904                                         g_assert_not_reached ();
1905                                 }
1906
1907                                 continue;
1908                         }
1909
1910                         /* FIXME: Allocate volatile arguments to registers */
1911                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1912                                 inreg = FALSE;
1913
1914                         /*
1915                          * Under AMD64, all registers used to pass arguments to functions
1916                          * are volatile across calls.
1917                          * FIXME: Optimize this.
1918                          */
1919                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1920                                 inreg = FALSE;
1921
1922                         ins->opcode = OP_REGOFFSET;
1923
1924                         switch (ainfo->storage) {
1925                         case ArgInIReg:
1926                         case ArgInFloatSSEReg:
1927                         case ArgInDoubleSSEReg:
1928                                 if (inreg) {
1929                                         ins->opcode = OP_REGVAR;
1930                                         ins->dreg = ainfo->reg;
1931                                 }
1932                                 break;
1933                         case ArgOnStack:
1934                                 g_assert (!cfg->arch.omit_fp);
1935                                 ins->opcode = OP_REGOFFSET;
1936                                 ins->inst_basereg = cfg->frame_reg;
1937                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1938                                 break;
1939                         case ArgValuetypeInReg:
1940                                 break;
1941                         case ArgValuetypeAddrInIReg: {
1942                                 MonoInst *indir;
1943                                 g_assert (!cfg->arch.omit_fp);
1944
1945                                 MONO_INST_NEW (cfg, indir, 0);
1946                                 indir->opcode = OP_REGOFFSET;
1947                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1948                                         indir->inst_basereg = cfg->frame_reg;
1949                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1950                                         offset += (sizeof (gpointer));
1951                                         indir->inst_offset = - offset;
1952                                 }
1953                                 else {
1954                                         indir->inst_basereg = cfg->frame_reg;
1955                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1956                                 }
1957
1958                                 ins->opcode = OP_VTARG_ADDR;
1959                                 ins->inst_left = indir;
1960
1961                                 break;
1962                         }
1963                         default:
1964                                 NOT_IMPLEMENTED;
1965                         }
1966
1967                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1968                                 ins->opcode = OP_REGOFFSET;
1969                                 ins->inst_basereg = cfg->frame_reg;
1970                                 /* These arguments are saved to the stack in the prolog */
1971                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1972                                 if (cfg->arch.omit_fp) {
1973                                         ins->inst_offset = offset;
1974                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1975                                         // Arguments are yet supported by the stack map creation code
1976                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1977                                 } else {
1978                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1979                                         ins->inst_offset = - offset;
1980                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1981                                 }
1982                         }
1983                 }
1984         }
1985
1986         cfg->stack_offset = offset;
1987 }
1988
1989 void
1990 mono_arch_create_vars (MonoCompile *cfg)
1991 {
1992         MonoMethodSignature *sig;
1993         CallInfo *cinfo;
1994
1995         sig = mono_method_signature (cfg->method);
1996
1997         if (!cfg->arch.cinfo)
1998                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1999         cinfo = cfg->arch.cinfo;
2000
2001         if (cinfo->ret.storage == ArgValuetypeInReg)
2002                 cfg->ret_var_is_local = TRUE;
2003
2004         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
2005                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2006                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2007                         printf ("vret_addr = ");
2008                         mono_print_ins (cfg->vret_addr);
2009                 }
2010         }
2011
2012         if (cfg->gen_seq_points) {
2013                 MonoInst *ins;
2014
2015                 if (cfg->compile_aot) {
2016                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2017                         ins->flags |= MONO_INST_VOLATILE;
2018                         cfg->arch.seq_point_info_var = ins;
2019                 }
2020
2021             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2022                 ins->flags |= MONO_INST_VOLATILE;
2023                 cfg->arch.ss_trigger_page_var = ins;
2024         }
2025
2026 #ifdef MONO_AMD64_NO_PUSHES
2027         /*
2028          * When this is set, we pass arguments on the stack by moves, and by allocating
2029          * a bigger stack frame, instead of pushes.
2030          * Pushes complicate exception handling because the arguments on the stack have
2031          * to be popped each time a frame is unwound. They also make fp elimination
2032          * impossible.
2033          * FIXME: This doesn't work inside filter/finally clauses, since those execute
2034          * on a new frame which doesn't include a param area.
2035          */
2036         cfg->arch.no_pushes = TRUE;
2037 #endif
2038
2039         if (cfg->method->save_lmf) {
2040                 MonoInst *lmf_var = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2041                 lmf_var->flags |= MONO_INST_VOLATILE;
2042                 lmf_var->flags |= MONO_INST_LMF;
2043                 cfg->arch.lmf_var = lmf_var;
2044         }
2045
2046 #ifndef MONO_AMD64_NO_PUSHES
2047         cfg->arch_eh_jit_info = 1;
2048 #endif
2049 }
2050
2051 static void
2052 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2053 {
2054         MonoInst *ins;
2055
2056         switch (storage) {
2057         case ArgInIReg:
2058                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2059                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2060                 ins->sreg1 = tree->dreg;
2061                 MONO_ADD_INS (cfg->cbb, ins);
2062                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2063                 break;
2064         case ArgInFloatSSEReg:
2065                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2066                 ins->dreg = mono_alloc_freg (cfg);
2067                 ins->sreg1 = tree->dreg;
2068                 MONO_ADD_INS (cfg->cbb, ins);
2069
2070                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2071                 break;
2072         case ArgInDoubleSSEReg:
2073                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2074                 ins->dreg = mono_alloc_freg (cfg);
2075                 ins->sreg1 = tree->dreg;
2076                 MONO_ADD_INS (cfg->cbb, ins);
2077
2078                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2079
2080                 break;
2081         default:
2082                 g_assert_not_reached ();
2083         }
2084 }
2085
2086 static int
2087 arg_storage_to_load_membase (ArgStorage storage)
2088 {
2089         switch (storage) {
2090         case ArgInIReg:
2091 #if defined(__mono_ilp32__)
2092                 return OP_LOADI8_MEMBASE;
2093 #else
2094                 return OP_LOAD_MEMBASE;
2095 #endif
2096         case ArgInDoubleSSEReg:
2097                 return OP_LOADR8_MEMBASE;
2098         case ArgInFloatSSEReg:
2099                 return OP_LOADR4_MEMBASE;
2100         default:
2101                 g_assert_not_reached ();
2102         }
2103
2104         return -1;
2105 }
2106
2107 static void
2108 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2109 {
2110         MonoInst *arg;
2111         MonoMethodSignature *tmp_sig;
2112         int sig_reg;
2113
2114         if (call->tail_call)
2115                 NOT_IMPLEMENTED;
2116
2117         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2118
2119         /*
2120          * mono_ArgIterator_Setup assumes the signature cookie is
2121          * passed first and all the arguments which were before it are
2122          * passed on the stack after the signature. So compensate by
2123          * passing a different signature.
2124          */
2125         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2126         tmp_sig->param_count -= call->signature->sentinelpos;
2127         tmp_sig->sentinelpos = 0;
2128         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2129
2130         sig_reg = mono_alloc_ireg (cfg);
2131         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2132
2133         if (cfg->arch.no_pushes) {
2134                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2135         } else {
2136                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2137                 arg->sreg1 = sig_reg;
2138                 MONO_ADD_INS (cfg->cbb, arg);
2139         }
2140 }
2141
2142 static inline LLVMArgStorage
2143 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2144 {
2145         switch (storage) {
2146         case ArgInIReg:
2147                 return LLVMArgInIReg;
2148         case ArgNone:
2149                 return LLVMArgNone;
2150         default:
2151                 g_assert_not_reached ();
2152                 return LLVMArgNone;
2153         }
2154 }
2155
2156 #ifdef ENABLE_LLVM
2157 LLVMCallInfo*
2158 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2159 {
2160         int i, n;
2161         CallInfo *cinfo;
2162         ArgInfo *ainfo;
2163         int j;
2164         LLVMCallInfo *linfo;
2165         MonoType *t;
2166
2167         n = sig->param_count + sig->hasthis;
2168
2169         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2170
2171         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2172
2173         /*
2174          * LLVM always uses the native ABI while we use our own ABI, the
2175          * only difference is the handling of vtypes:
2176          * - we only pass/receive them in registers in some cases, and only
2177          *   in 1 or 2 integer registers.
2178          */
2179         if (cinfo->ret.storage == ArgValuetypeInReg) {
2180                 if (sig->pinvoke) {
2181                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2182                         cfg->disable_llvm = TRUE;
2183                         return linfo;
2184                 }
2185
2186                 linfo->ret.storage = LLVMArgVtypeInReg;
2187                 for (j = 0; j < 2; ++j)
2188                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2189         }
2190
2191         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
2192                 /* Vtype returned using a hidden argument */
2193                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2194                 linfo->vret_arg_index = cinfo->vret_arg_index;
2195         }
2196
2197         for (i = 0; i < n; ++i) {
2198                 ainfo = cinfo->args + i;
2199
2200                 if (i >= sig->hasthis)
2201                         t = sig->params [i - sig->hasthis];
2202                 else
2203                         t = &mono_defaults.int_class->byval_arg;
2204
2205                 linfo->args [i].storage = LLVMArgNone;
2206
2207                 switch (ainfo->storage) {
2208                 case ArgInIReg:
2209                         linfo->args [i].storage = LLVMArgInIReg;
2210                         break;
2211                 case ArgInDoubleSSEReg:
2212                 case ArgInFloatSSEReg:
2213                         linfo->args [i].storage = LLVMArgInFPReg;
2214                         break;
2215                 case ArgOnStack:
2216                         if (MONO_TYPE_ISSTRUCT (t)) {
2217                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2218                         } else {
2219                                 linfo->args [i].storage = LLVMArgInIReg;
2220                                 if (!t->byref) {
2221                                         if (t->type == MONO_TYPE_R4)
2222                                                 linfo->args [i].storage = LLVMArgInFPReg;
2223                                         else if (t->type == MONO_TYPE_R8)
2224                                                 linfo->args [i].storage = LLVMArgInFPReg;
2225                                 }
2226                         }
2227                         break;
2228                 case ArgValuetypeInReg:
2229                         if (sig->pinvoke) {
2230                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2231                                 cfg->disable_llvm = TRUE;
2232                                 return linfo;
2233                         }
2234
2235                         linfo->args [i].storage = LLVMArgVtypeInReg;
2236                         for (j = 0; j < 2; ++j)
2237                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2238                         break;
2239                 default:
2240                         cfg->exception_message = g_strdup ("ainfo->storage");
2241                         cfg->disable_llvm = TRUE;
2242                         break;
2243                 }
2244         }
2245
2246         return linfo;
2247 }
2248 #endif
2249
2250 void
2251 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2252 {
2253         MonoInst *arg, *in;
2254         MonoMethodSignature *sig;
2255         int i, n, stack_size;
2256         CallInfo *cinfo;
2257         ArgInfo *ainfo;
2258
2259         stack_size = 0;
2260
2261         sig = call->signature;
2262         n = sig->param_count + sig->hasthis;
2263
2264         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2265
2266         if (COMPILE_LLVM (cfg)) {
2267                 /* We shouldn't be called in the llvm case */
2268                 cfg->disable_llvm = TRUE;
2269                 return;
2270         }
2271
2272         if (cinfo->need_stack_align) {
2273                 if (!cfg->arch.no_pushes)
2274                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2275         }
2276
2277         /*
2278          * Emit all arguments which are passed on the stack to prevent register
2279          * allocation problems.
2280          */
2281         if (cfg->arch.no_pushes) {
2282                 for (i = 0; i < n; ++i) {
2283                         MonoType *t;
2284                         ainfo = cinfo->args + i;
2285
2286                         in = call->args [i];
2287
2288                         if (sig->hasthis && i == 0)
2289                                 t = &mono_defaults.object_class->byval_arg;
2290                         else
2291                                 t = sig->params [i - sig->hasthis];
2292
2293                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2294                                 if (!t->byref) {
2295                                         if (t->type == MONO_TYPE_R4)
2296                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2297                                         else if (t->type == MONO_TYPE_R8)
2298                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2299                                         else
2300                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2301                                 } else {
2302                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2303                                 }
2304                                 if (cfg->compute_gc_maps) {
2305                                         MonoInst *def;
2306
2307                                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2308                                 }
2309                         }
2310                 }
2311         }
2312
2313         /*
2314          * Emit all parameters passed in registers in non-reverse order for better readability
2315          * and to help the optimization in emit_prolog ().
2316          */
2317         for (i = 0; i < n; ++i) {
2318                 ainfo = cinfo->args + i;
2319
2320                 in = call->args [i];
2321
2322                 if (ainfo->storage == ArgInIReg)
2323                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2324         }
2325
2326         for (i = n - 1; i >= 0; --i) {
2327                 ainfo = cinfo->args + i;
2328
2329                 in = call->args [i];
2330
2331                 switch (ainfo->storage) {
2332                 case ArgInIReg:
2333                         /* Already done */
2334                         break;
2335                 case ArgInFloatSSEReg:
2336                 case ArgInDoubleSSEReg:
2337                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2338                         break;
2339                 case ArgOnStack:
2340                 case ArgValuetypeInReg:
2341                 case ArgValuetypeAddrInIReg:
2342                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2343                                 MonoInst *call_inst = (MonoInst*)call;
2344                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2345                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2346                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2347                                 guint32 align;
2348                                 guint32 size;
2349
2350                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2351                                         size = sizeof (MonoTypedRef);
2352                                         align = sizeof (gpointer);
2353                                 }
2354                                 else {
2355                                         if (sig->pinvoke)
2356                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2357                                         else {
2358                                                 /*
2359                                                  * Other backends use mono_type_stack_size (), but that
2360                                                  * aligns the size to 8, which is larger than the size of
2361                                                  * the source, leading to reads of invalid memory if the
2362                                                  * source is at the end of address space.
2363                                                  */
2364                                                 size = mono_class_value_size (in->klass, &align);
2365                                         }
2366                                 }
2367                                 g_assert (in->klass);
2368
2369                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2370                                         /* Avoid asserts in emit_memcpy () */
2371                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2372                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2373                                         /* Continue normally */
2374                                 }
2375
2376                                 if (size > 0) {
2377                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2378                                         arg->sreg1 = in->dreg;
2379                                         arg->klass = in->klass;
2380                                         arg->backend.size = size;
2381                                         arg->inst_p0 = call;
2382                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2383                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2384
2385                                         MONO_ADD_INS (cfg->cbb, arg);
2386                                 }
2387                         } else {
2388                                 if (cfg->arch.no_pushes) {
2389                                         /* Already done */
2390                                 } else {
2391                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2392                                         arg->sreg1 = in->dreg;
2393                                         if (!sig->params [i - sig->hasthis]->byref) {
2394                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2395                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2396                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2397                                                         arg->inst_destbasereg = X86_ESP;
2398                                                         arg->inst_offset = 0;
2399                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2400                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2401                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2402                                                         arg->inst_destbasereg = X86_ESP;
2403                                                         arg->inst_offset = 0;
2404                                                 }
2405                                         }
2406                                         MONO_ADD_INS (cfg->cbb, arg);
2407                                 }
2408                         }
2409                         break;
2410                 default:
2411                         g_assert_not_reached ();
2412                 }
2413
2414                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2415                         /* Emit the signature cookie just before the implicit arguments */
2416                         emit_sig_cookie (cfg, call, cinfo);
2417         }
2418
2419         /* Handle the case where there are no implicit arguments */
2420         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2421                 emit_sig_cookie (cfg, call, cinfo);
2422
2423         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2424                 MonoInst *vtarg;
2425
2426                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2427                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2428                                 /*
2429                                  * Tell the JIT to use a more efficient calling convention: call using
2430                                  * OP_CALL, compute the result location after the call, and save the
2431                                  * result there.
2432                                  */
2433                                 call->vret_in_reg = TRUE;
2434                                 /*
2435                                  * Nullify the instruction computing the vret addr to enable
2436                                  * future optimizations.
2437                                  */
2438                                 if (call->vret_var)
2439                                         NULLIFY_INS (call->vret_var);
2440                         } else {
2441                                 if (call->tail_call)
2442                                         NOT_IMPLEMENTED;
2443                                 /*
2444                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2445                                  * the stack. Push the address here, so the call instruction can
2446                                  * access it.
2447                                  */
2448                                 if (!cfg->arch.vret_addr_loc) {
2449                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2450                                         /* Prevent it from being register allocated or optimized away */
2451                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2452                                 }
2453
2454                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2455                         }
2456                 }
2457                 else {
2458                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2459                         vtarg->sreg1 = call->vret_var->dreg;
2460                         vtarg->dreg = mono_alloc_preg (cfg);
2461                         MONO_ADD_INS (cfg->cbb, vtarg);
2462
2463                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2464                 }
2465         }
2466
2467 #ifdef HOST_WIN32
2468         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2469                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2470         }
2471 #endif
2472
2473         if (cfg->method->save_lmf) {
2474                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2475                 MONO_ADD_INS (cfg->cbb, arg);
2476         }
2477
2478         call->stack_usage = cinfo->stack_usage;
2479 }
2480
2481 void
2482 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2483 {
2484         MonoInst *arg;
2485         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2486         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2487         int size = ins->backend.size;
2488
2489         if (ainfo->storage == ArgValuetypeInReg) {
2490                 MonoInst *load;
2491                 int part;
2492
2493                 for (part = 0; part < 2; ++part) {
2494                         if (ainfo->pair_storage [part] == ArgNone)
2495                                 continue;
2496
2497                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2498                         load->inst_basereg = src->dreg;
2499                         load->inst_offset = part * sizeof(mgreg_t);
2500
2501                         switch (ainfo->pair_storage [part]) {
2502                         case ArgInIReg:
2503                                 load->dreg = mono_alloc_ireg (cfg);
2504                                 break;
2505                         case ArgInDoubleSSEReg:
2506                         case ArgInFloatSSEReg:
2507                                 load->dreg = mono_alloc_freg (cfg);
2508                                 break;
2509                         default:
2510                                 g_assert_not_reached ();
2511                         }
2512                         MONO_ADD_INS (cfg->cbb, load);
2513
2514                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2515                 }
2516         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2517                 MonoInst *vtaddr, *load;
2518                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2519
2520                 g_assert (!cfg->arch.no_pushes);
2521
2522                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2523                 load->inst_p0 = vtaddr;
2524                 vtaddr->flags |= MONO_INST_INDIRECT;
2525                 load->type = STACK_MP;
2526                 load->klass = vtaddr->klass;
2527                 load->dreg = mono_alloc_ireg (cfg);
2528                 MONO_ADD_INS (cfg->cbb, load);
2529                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2530
2531                 if (ainfo->pair_storage [0] == ArgInIReg) {
2532                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2533                         arg->dreg = mono_alloc_ireg (cfg);
2534                         arg->sreg1 = load->dreg;
2535                         arg->inst_imm = 0;
2536                         MONO_ADD_INS (cfg->cbb, arg);
2537                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2538                 } else {
2539                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2540                         arg->sreg1 = load->dreg;
2541                         MONO_ADD_INS (cfg->cbb, arg);
2542                 }
2543         } else {
2544                 if (size == 8) {
2545                         if (cfg->arch.no_pushes) {
2546                                 int dreg = mono_alloc_ireg (cfg);
2547
2548                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2549                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2550                         } else {
2551                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2552                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2553                                 arg->inst_basereg = src->dreg;
2554                                 arg->inst_offset = 0;
2555                                 MONO_ADD_INS (cfg->cbb, arg);
2556                         }
2557                 } else if (size <= 40) {
2558                         if (cfg->arch.no_pushes) {
2559                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2560                         } else {
2561                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2562                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2563                         }
2564                 } else {
2565                         if (cfg->arch.no_pushes) {
2566                                 // FIXME: Code growth
2567                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2568                         } else {
2569                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2570                                 arg->inst_basereg = src->dreg;
2571                                 arg->inst_offset = 0;
2572                                 arg->inst_imm = size;
2573                                 MONO_ADD_INS (cfg->cbb, arg);
2574                         }
2575                 }
2576
2577                 if (cfg->compute_gc_maps) {
2578                         MonoInst *def;
2579                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2580                 }
2581         }
2582 }
2583
2584 void
2585 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2586 {
2587         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2588
2589         if (ret->type == MONO_TYPE_R4) {
2590                 if (COMPILE_LLVM (cfg))
2591                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2592                 else
2593                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2594                 return;
2595         } else if (ret->type == MONO_TYPE_R8) {
2596                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2597                 return;
2598         }
2599
2600         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2601 }
2602
2603 #endif /* DISABLE_JIT */
2604
2605 #define EMIT_COND_BRANCH(ins,cond,sign) \
2606         if (ins->inst_true_bb->native_offset) { \
2607                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2608         } else { \
2609                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2610                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2611             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2612                         x86_branch8 (code, cond, 0, sign); \
2613                 else \
2614                         x86_branch32 (code, cond, 0, sign); \
2615 }
2616
2617 typedef struct {
2618         MonoMethodSignature *sig;
2619         CallInfo *cinfo;
2620 } ArchDynCallInfo;
2621
2622 typedef struct {
2623         mgreg_t regs [PARAM_REGS];
2624         mgreg_t res;
2625         guint8 *ret;
2626 } DynCallArgs;
2627
2628 static gboolean
2629 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2630 {
2631         int i;
2632
2633 #ifdef HOST_WIN32
2634         return FALSE;
2635 #endif
2636
2637         switch (cinfo->ret.storage) {
2638         case ArgNone:
2639         case ArgInIReg:
2640                 break;
2641         case ArgValuetypeInReg: {
2642                 ArgInfo *ainfo = &cinfo->ret;
2643
2644                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2645                         return FALSE;
2646                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2647                         return FALSE;
2648                 break;
2649         }
2650         default:
2651                 return FALSE;
2652         }
2653
2654         for (i = 0; i < cinfo->nargs; ++i) {
2655                 ArgInfo *ainfo = &cinfo->args [i];
2656                 switch (ainfo->storage) {
2657                 case ArgInIReg:
2658                         break;
2659                 case ArgValuetypeInReg:
2660                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2661                                 return FALSE;
2662                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2663                                 return FALSE;
2664                         break;
2665                 default:
2666                         return FALSE;
2667                 }
2668         }
2669
2670         return TRUE;
2671 }
2672
2673 /*
2674  * mono_arch_dyn_call_prepare:
2675  *
2676  *   Return a pointer to an arch-specific structure which contains information
2677  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2678  * supported for SIG.
2679  * This function is equivalent to ffi_prep_cif in libffi.
2680  */
2681 MonoDynCallInfo*
2682 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2683 {
2684         ArchDynCallInfo *info;
2685         CallInfo *cinfo;
2686
2687         cinfo = get_call_info (NULL, NULL, sig);
2688
2689         if (!dyn_call_supported (sig, cinfo)) {
2690                 g_free (cinfo);
2691                 return NULL;
2692         }
2693
2694         info = g_new0 (ArchDynCallInfo, 1);
2695         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2696         info->sig = sig;
2697         info->cinfo = cinfo;
2698
2699         return (MonoDynCallInfo*)info;
2700 }
2701
2702 /*
2703  * mono_arch_dyn_call_free:
2704  *
2705  *   Free a MonoDynCallInfo structure.
2706  */
2707 void
2708 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2709 {
2710         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2711
2712         g_free (ainfo->cinfo);
2713         g_free (ainfo);
2714 }
2715
2716 #if !defined(__native_client__)
2717 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2718 #define GREG_TO_PTR(greg) (gpointer)(greg)
2719 #else
2720 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2721 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2722 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2723 #endif
2724
2725 /*
2726  * mono_arch_get_start_dyn_call:
2727  *
2728  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2729  * store the result into BUF.
2730  * ARGS should be an array of pointers pointing to the arguments.
2731  * RET should point to a memory buffer large enought to hold the result of the
2732  * call.
2733  * This function should be as fast as possible, any work which does not depend
2734  * on the actual values of the arguments should be done in
2735  * mono_arch_dyn_call_prepare ().
2736  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2737  * libffi.
2738  */
2739 void
2740 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2741 {
2742         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2743         DynCallArgs *p = (DynCallArgs*)buf;
2744         int arg_index, greg, i, pindex;
2745         MonoMethodSignature *sig = dinfo->sig;
2746
2747         g_assert (buf_len >= sizeof (DynCallArgs));
2748
2749         p->res = 0;
2750         p->ret = ret;
2751
2752         arg_index = 0;
2753         greg = 0;
2754         pindex = 0;
2755
2756         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2757                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2758                 if (!sig->hasthis)
2759                         pindex = 1;
2760         }
2761
2762         if (dinfo->cinfo->vtype_retaddr)
2763                 p->regs [greg ++] = PTR_TO_GREG(ret);
2764
2765         for (i = pindex; i < sig->param_count; i++) {
2766                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2767                 gpointer *arg = args [arg_index ++];
2768
2769                 if (t->byref) {
2770                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2771                         continue;
2772                 }
2773
2774                 switch (t->type) {
2775                 case MONO_TYPE_STRING:
2776                 case MONO_TYPE_CLASS:
2777                 case MONO_TYPE_ARRAY:
2778                 case MONO_TYPE_SZARRAY:
2779                 case MONO_TYPE_OBJECT:
2780                 case MONO_TYPE_PTR:
2781                 case MONO_TYPE_I:
2782                 case MONO_TYPE_U:
2783 #if !defined(__mono_ilp32__)
2784                 case MONO_TYPE_I8:
2785                 case MONO_TYPE_U8:
2786 #endif
2787                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2788                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2789                         break;
2790 #if defined(__mono_ilp32__)
2791                 case MONO_TYPE_I8:
2792                 case MONO_TYPE_U8:
2793                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2794                         p->regs [greg ++] = *(guint64*)(arg);
2795                         break;
2796 #endif
2797                 case MONO_TYPE_BOOLEAN:
2798                 case MONO_TYPE_U1:
2799                         p->regs [greg ++] = *(guint8*)(arg);
2800                         break;
2801                 case MONO_TYPE_I1:
2802                         p->regs [greg ++] = *(gint8*)(arg);
2803                         break;
2804                 case MONO_TYPE_I2:
2805                         p->regs [greg ++] = *(gint16*)(arg);
2806                         break;
2807                 case MONO_TYPE_U2:
2808                 case MONO_TYPE_CHAR:
2809                         p->regs [greg ++] = *(guint16*)(arg);
2810                         break;
2811                 case MONO_TYPE_I4:
2812                         p->regs [greg ++] = *(gint32*)(arg);
2813                         break;
2814                 case MONO_TYPE_U4:
2815                         p->regs [greg ++] = *(guint32*)(arg);
2816                         break;
2817                 case MONO_TYPE_GENERICINST:
2818                     if (MONO_TYPE_IS_REFERENCE (t)) {
2819                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2820                                 break;
2821                         } else {
2822                                 /* Fall through */
2823                         }
2824                 case MONO_TYPE_VALUETYPE: {
2825                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2826
2827                         g_assert (ainfo->storage == ArgValuetypeInReg);
2828                         if (ainfo->pair_storage [0] != ArgNone) {
2829                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2830                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2831                         }
2832                         if (ainfo->pair_storage [1] != ArgNone) {
2833                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2834                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2835                         }
2836                         break;
2837                 }
2838                 default:
2839                         g_assert_not_reached ();
2840                 }
2841         }
2842
2843         g_assert (greg <= PARAM_REGS);
2844 }
2845
2846 /*
2847  * mono_arch_finish_dyn_call:
2848  *
2849  *   Store the result of a dyn call into the return value buffer passed to
2850  * start_dyn_call ().
2851  * This function should be as fast as possible, any work which does not depend
2852  * on the actual values of the arguments should be done in
2853  * mono_arch_dyn_call_prepare ().
2854  */
2855 void
2856 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2857 {
2858         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2859         MonoMethodSignature *sig = dinfo->sig;
2860         guint8 *ret = ((DynCallArgs*)buf)->ret;
2861         mgreg_t res = ((DynCallArgs*)buf)->res;
2862
2863         switch (mono_type_get_underlying_type (sig->ret)->type) {
2864         case MONO_TYPE_VOID:
2865                 *(gpointer*)ret = NULL;
2866                 break;
2867         case MONO_TYPE_STRING:
2868         case MONO_TYPE_CLASS:
2869         case MONO_TYPE_ARRAY:
2870         case MONO_TYPE_SZARRAY:
2871         case MONO_TYPE_OBJECT:
2872         case MONO_TYPE_I:
2873         case MONO_TYPE_U:
2874         case MONO_TYPE_PTR:
2875                 *(gpointer*)ret = GREG_TO_PTR(res);
2876                 break;
2877         case MONO_TYPE_I1:
2878                 *(gint8*)ret = res;
2879                 break;
2880         case MONO_TYPE_U1:
2881         case MONO_TYPE_BOOLEAN:
2882                 *(guint8*)ret = res;
2883                 break;
2884         case MONO_TYPE_I2:
2885                 *(gint16*)ret = res;
2886                 break;
2887         case MONO_TYPE_U2:
2888         case MONO_TYPE_CHAR:
2889                 *(guint16*)ret = res;
2890                 break;
2891         case MONO_TYPE_I4:
2892                 *(gint32*)ret = res;
2893                 break;
2894         case MONO_TYPE_U4:
2895                 *(guint32*)ret = res;
2896                 break;
2897         case MONO_TYPE_I8:
2898                 *(gint64*)ret = res;
2899                 break;
2900         case MONO_TYPE_U8:
2901                 *(guint64*)ret = res;
2902                 break;
2903         case MONO_TYPE_GENERICINST:
2904                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2905                         *(gpointer*)ret = GREG_TO_PTR(res);
2906                         break;
2907                 } else {
2908                         /* Fall through */
2909                 }
2910         case MONO_TYPE_VALUETYPE:
2911                 if (dinfo->cinfo->vtype_retaddr) {
2912                         /* Nothing to do */
2913                 } else {
2914                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2915
2916                         g_assert (ainfo->storage == ArgValuetypeInReg);
2917
2918                         if (ainfo->pair_storage [0] != ArgNone) {
2919                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2920                                 ((mgreg_t*)ret)[0] = res;
2921                         }
2922
2923                         g_assert (ainfo->pair_storage [1] == ArgNone);
2924                 }
2925                 break;
2926         default:
2927                 g_assert_not_reached ();
2928         }
2929 }
2930
2931 /* emit an exception if condition is fail */
2932 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2933         do {                                                        \
2934                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2935                 if (tins == NULL) {                                                                             \
2936                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2937                                         MONO_PATCH_INFO_EXC, exc_name);  \
2938                         x86_branch32 (code, cond, 0, signed);               \
2939                 } else {        \
2940                         EMIT_COND_BRANCH (tins, cond, signed);  \
2941                 }                       \
2942         } while (0);
2943
2944 #define EMIT_FPCOMPARE(code) do { \
2945         amd64_fcompp (code); \
2946         amd64_fnstsw (code); \
2947 } while (0);
2948
2949 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2950     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2951         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2952         amd64_ ##op (code); \
2953         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2954         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2955 } while (0);
2956
2957 static guint8*
2958 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2959 {
2960         gboolean no_patch = FALSE;
2961
2962         /*
2963          * FIXME: Add support for thunks
2964          */
2965         {
2966                 gboolean near_call = FALSE;
2967
2968                 /*
2969                  * Indirect calls are expensive so try to make a near call if possible.
2970                  * The caller memory is allocated by the code manager so it is
2971                  * guaranteed to be at a 32 bit offset.
2972                  */
2973
2974                 if (patch_type != MONO_PATCH_INFO_ABS) {
2975                         /* The target is in memory allocated using the code manager */
2976                         near_call = TRUE;
2977
2978                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2979                                 if (((MonoMethod*)data)->klass->image->aot_module)
2980                                         /* The callee might be an AOT method */
2981                                         near_call = FALSE;
2982                                 if (((MonoMethod*)data)->dynamic)
2983                                         /* The target is in malloc-ed memory */
2984                                         near_call = FALSE;
2985                         }
2986
2987                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2988                                 /*
2989                                  * The call might go directly to a native function without
2990                                  * the wrapper.
2991                                  */
2992                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2993                                 if (mi) {
2994                                         gconstpointer target = mono_icall_get_wrapper (mi);
2995                                         if ((((guint64)target) >> 32) != 0)
2996                                                 near_call = FALSE;
2997                                 }
2998                         }
2999                 }
3000                 else {
3001                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
3002                                 /*
3003                                  * This is not really an optimization, but required because the
3004                                  * generic class init trampolines use R11 to pass the vtable.
3005                                  */
3006                                 near_call = TRUE;
3007                         } else {
3008                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3009                                 if (info) {
3010                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
3011                                                 strstr (cfg->method->name, info->name)) {
3012                                                 /* A call to the wrapped function */
3013                                                 if ((((guint64)data) >> 32) == 0)
3014                                                         near_call = TRUE;
3015                                                 no_patch = TRUE;
3016                                         }
3017                                         else if (info->func == info->wrapper) {
3018                                                 /* No wrapper */
3019                                                 if ((((guint64)info->func) >> 32) == 0)
3020                                                         near_call = TRUE;
3021                                         }
3022                                         else {
3023                                                 /* See the comment in mono_codegen () */
3024                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3025                                                         near_call = TRUE;
3026                                         }
3027                                 }
3028                                 else if ((((guint64)data) >> 32) == 0) {
3029                                         near_call = TRUE;
3030                                         no_patch = TRUE;
3031                                 }
3032                         }
3033                 }
3034
3035                 if (cfg->method->dynamic)
3036                         /* These methods are allocated using malloc */
3037                         near_call = FALSE;
3038
3039 #ifdef MONO_ARCH_NOMAP32BIT
3040                 near_call = FALSE;
3041 #endif
3042
3043                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3044                 if (optimize_for_xen)
3045                         near_call = FALSE;
3046
3047                 if (cfg->compile_aot) {
3048                         near_call = TRUE;
3049                         no_patch = TRUE;
3050                 }
3051
3052                 if (near_call) {
3053                         /*
3054                          * Align the call displacement to an address divisible by 4 so it does
3055                          * not span cache lines. This is required for code patching to work on SMP
3056                          * systems.
3057                          */
3058                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3059                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3060                                 amd64_padding (code, pad_size);
3061                         }
3062                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3063                         amd64_call_code (code, 0);
3064                 }
3065                 else {
3066                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3067                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3068                         amd64_call_reg (code, GP_SCRATCH_REG);
3069                 }
3070         }
3071
3072         return code;
3073 }
3074
3075 static inline guint8*
3076 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3077 {
3078 #ifdef HOST_WIN32
3079         if (win64_adjust_stack)
3080                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3081 #endif
3082         code = emit_call_body (cfg, code, patch_type, data);
3083 #ifdef HOST_WIN32
3084         if (win64_adjust_stack)
3085                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3086 #endif
3087
3088         return code;
3089 }
3090
3091 static inline int
3092 store_membase_imm_to_store_membase_reg (int opcode)
3093 {
3094         switch (opcode) {
3095         case OP_STORE_MEMBASE_IMM:
3096                 return OP_STORE_MEMBASE_REG;
3097         case OP_STOREI4_MEMBASE_IMM:
3098                 return OP_STOREI4_MEMBASE_REG;
3099         case OP_STOREI8_MEMBASE_IMM:
3100                 return OP_STOREI8_MEMBASE_REG;
3101         }
3102
3103         return -1;
3104 }
3105
3106 #ifndef DISABLE_JIT
3107
3108 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3109
3110 /*
3111  * mono_arch_peephole_pass_1:
3112  *
3113  *   Perform peephole opts which should/can be performed before local regalloc
3114  */
3115 void
3116 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3117 {
3118         MonoInst *ins, *n;
3119
3120         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3121                 MonoInst *last_ins = ins->prev;
3122
3123                 switch (ins->opcode) {
3124                 case OP_ADD_IMM:
3125                 case OP_IADD_IMM:
3126                 case OP_LADD_IMM:
3127                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3128                                 /*
3129                                  * X86_LEA is like ADD, but doesn't have the
3130                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3131                                  * its operand to 64 bit.
3132                                  */
3133                                 ins->opcode = OP_X86_LEA_MEMBASE;
3134                                 ins->inst_basereg = ins->sreg1;
3135                         }
3136                         break;
3137                 case OP_LXOR:
3138                 case OP_IXOR:
3139                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3140                                 MonoInst *ins2;
3141
3142                                 /*
3143                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3144                                  * the latter has length 2-3 instead of 6 (reverse constant
3145                                  * propagation). These instruction sequences are very common
3146                                  * in the initlocals bblock.
3147                                  */
3148                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3149                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3150                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3151                                                 ins2->sreg1 = ins->dreg;
3152                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3153                                                 /* Continue */
3154                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3155                                                 NULLIFY_INS (ins2);
3156                                                 /* Continue */
3157                                         } else {
3158                                                 break;
3159                                         }
3160                                 }
3161                         }
3162                         break;
3163                 case OP_COMPARE_IMM:
3164                 case OP_LCOMPARE_IMM:
3165                         /* OP_COMPARE_IMM (reg, 0)
3166                          * -->
3167                          * OP_AMD64_TEST_NULL (reg)
3168                          */
3169                         if (!ins->inst_imm)
3170                                 ins->opcode = OP_AMD64_TEST_NULL;
3171                         break;
3172                 case OP_ICOMPARE_IMM:
3173                         if (!ins->inst_imm)
3174                                 ins->opcode = OP_X86_TEST_NULL;
3175                         break;
3176                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3177                         /*
3178                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3179                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3180                          * -->
3181                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3182                          * OP_COMPARE_IMM reg, imm
3183                          *
3184                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3185                          */
3186                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3187                             ins->inst_basereg == last_ins->inst_destbasereg &&
3188                             ins->inst_offset == last_ins->inst_offset) {
3189                                         ins->opcode = OP_ICOMPARE_IMM;
3190                                         ins->sreg1 = last_ins->sreg1;
3191
3192                                         /* check if we can remove cmp reg,0 with test null */
3193                                         if (!ins->inst_imm)
3194                                                 ins->opcode = OP_X86_TEST_NULL;
3195                                 }
3196
3197                         break;
3198                 }
3199
3200                 mono_peephole_ins (bb, ins);
3201         }
3202 }
3203
3204 void
3205 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3206 {
3207         MonoInst *ins, *n;
3208
3209         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3210                 switch (ins->opcode) {
3211                 case OP_ICONST:
3212                 case OP_I8CONST: {
3213                         /* reg = 0 -> XOR (reg, reg) */
3214                         /* XOR sets cflags on x86, so we cant do it always */
3215                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3216                                 ins->opcode = OP_LXOR;
3217                                 ins->sreg1 = ins->dreg;
3218                                 ins->sreg2 = ins->dreg;
3219                                 /* Fall through */
3220                         } else {
3221                                 break;
3222                         }
3223                 }
3224                 case OP_LXOR:
3225                         /*
3226                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3227                          * 0 result into 64 bits.
3228                          */
3229                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3230                                 ins->opcode = OP_IXOR;
3231                         }
3232                         /* Fall through */
3233                 case OP_IXOR:
3234                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3235                                 MonoInst *ins2;
3236
3237                                 /*
3238                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3239                                  * the latter has length 2-3 instead of 6 (reverse constant
3240                                  * propagation). These instruction sequences are very common
3241                                  * in the initlocals bblock.
3242                                  */
3243                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3244                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3245                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3246                                                 ins2->sreg1 = ins->dreg;
3247                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3248                                                 /* Continue */
3249                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3250                                                 NULLIFY_INS (ins2);
3251                                                 /* Continue */
3252                                         } else {
3253                                                 break;
3254                                         }
3255                                 }
3256                         }
3257                         break;
3258                 case OP_IADD_IMM:
3259                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3260                                 ins->opcode = OP_X86_INC_REG;
3261                         break;
3262                 case OP_ISUB_IMM:
3263                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3264                                 ins->opcode = OP_X86_DEC_REG;
3265                         break;
3266                 }
3267
3268                 mono_peephole_ins (bb, ins);
3269         }
3270 }
3271
3272 #define NEW_INS(cfg,ins,dest,op) do {   \
3273                 MONO_INST_NEW ((cfg), (dest), (op)); \
3274         (dest)->cil_code = (ins)->cil_code; \
3275         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3276         } while (0)
3277
3278 /*
3279  * mono_arch_lowering_pass:
3280  *
3281  *  Converts complex opcodes into simpler ones so that each IR instruction
3282  * corresponds to one machine instruction.
3283  */
3284 void
3285 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3286 {
3287         MonoInst *ins, *n, *temp;
3288
3289         /*
3290          * FIXME: Need to add more instructions, but the current machine
3291          * description can't model some parts of the composite instructions like
3292          * cdq.
3293          */
3294         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3295                 switch (ins->opcode) {
3296                 case OP_DIV_IMM:
3297                 case OP_REM_IMM:
3298                 case OP_IDIV_IMM:
3299                 case OP_IDIV_UN_IMM:
3300                 case OP_IREM_UN_IMM:
3301                         mono_decompose_op_imm (cfg, bb, ins);
3302                         break;
3303                 case OP_IREM_IMM:
3304                         /* Keep the opcode if we can implement it efficiently */
3305                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
3306                                 mono_decompose_op_imm (cfg, bb, ins);
3307                         break;
3308                 case OP_COMPARE_IMM:
3309                 case OP_LCOMPARE_IMM:
3310                         if (!amd64_is_imm32 (ins->inst_imm)) {
3311                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3312                                 temp->inst_c0 = ins->inst_imm;
3313                                 temp->dreg = mono_alloc_ireg (cfg);
3314                                 ins->opcode = OP_COMPARE;
3315                                 ins->sreg2 = temp->dreg;
3316                         }
3317                         break;
3318 #ifndef __mono_ilp32__
3319                 case OP_LOAD_MEMBASE:
3320 #endif
3321                 case OP_LOADI8_MEMBASE:
3322 #ifndef __native_client_codegen__
3323                 /*  Don't generate memindex opcodes (to simplify */
3324                 /*  read sandboxing) */
3325                         if (!amd64_is_imm32 (ins->inst_offset)) {
3326                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3327                                 temp->inst_c0 = ins->inst_offset;
3328                                 temp->dreg = mono_alloc_ireg (cfg);
3329                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3330                                 ins->inst_indexreg = temp->dreg;
3331                         }
3332 #endif
3333                         break;
3334 #ifndef __mono_ilp32__
3335                 case OP_STORE_MEMBASE_IMM:
3336 #endif
3337                 case OP_STOREI8_MEMBASE_IMM:
3338                         if (!amd64_is_imm32 (ins->inst_imm)) {
3339                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3340                                 temp->inst_c0 = ins->inst_imm;
3341                                 temp->dreg = mono_alloc_ireg (cfg);
3342                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3343                                 ins->sreg1 = temp->dreg;
3344                         }
3345                         break;
3346 #ifdef MONO_ARCH_SIMD_INTRINSICS
3347                 case OP_EXPAND_I1: {
3348                                 int temp_reg1 = mono_alloc_ireg (cfg);
3349                                 int temp_reg2 = mono_alloc_ireg (cfg);
3350                                 int original_reg = ins->sreg1;
3351
3352                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3353                                 temp->sreg1 = original_reg;
3354                                 temp->dreg = temp_reg1;
3355
3356                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3357                                 temp->sreg1 = temp_reg1;
3358                                 temp->dreg = temp_reg2;
3359                                 temp->inst_imm = 8;
3360
3361                                 NEW_INS (cfg, ins, temp, OP_LOR);
3362                                 temp->sreg1 = temp->dreg = temp_reg2;
3363                                 temp->sreg2 = temp_reg1;
3364
3365                                 ins->opcode = OP_EXPAND_I2;
3366                                 ins->sreg1 = temp_reg2;
3367                         }
3368                         break;
3369 #endif
3370                 default:
3371                         break;
3372                 }
3373         }
3374
3375         bb->max_vreg = cfg->next_vreg;
3376 }
3377
3378 static const int
3379 branch_cc_table [] = {
3380         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3381         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3382         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3383 };
3384
3385 /* Maps CMP_... constants to X86_CC_... constants */
3386 static const int
3387 cc_table [] = {
3388         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3389         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3390 };
3391
3392 static const int
3393 cc_signed_table [] = {
3394         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3395         FALSE, FALSE, FALSE, FALSE
3396 };
3397
3398 /*#include "cprop.c"*/
3399
3400 static unsigned char*
3401 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3402 {
3403         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3404
3405         if (size == 1)
3406                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3407         else if (size == 2)
3408                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3409         return code;
3410 }
3411
3412 static unsigned char*
3413 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3414 {
3415         int sreg = tree->sreg1;
3416         int need_touch = FALSE;
3417
3418 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3419         if (!tree->flags & MONO_INST_INIT)
3420                 need_touch = TRUE;
3421 #endif
3422
3423         if (need_touch) {
3424                 guint8* br[5];
3425
3426                 /*
3427                  * Under Windows:
3428                  * If requested stack size is larger than one page,
3429                  * perform stack-touch operation
3430                  */
3431                 /*
3432                  * Generate stack probe code.
3433                  * Under Windows, it is necessary to allocate one page at a time,
3434                  * "touching" stack after each successful sub-allocation. This is
3435                  * because of the way stack growth is implemented - there is a
3436                  * guard page before the lowest stack page that is currently commited.
3437                  * Stack normally grows sequentially so OS traps access to the
3438                  * guard page and commits more pages when needed.
3439                  */
3440                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3441                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3442
3443                 br[2] = code; /* loop */
3444                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3445                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3446                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3447                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3448                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3449                 amd64_patch (br[3], br[2]);
3450                 amd64_test_reg_reg (code, sreg, sreg);
3451                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3452                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3453
3454                 br[1] = code; x86_jump8 (code, 0);
3455
3456                 amd64_patch (br[0], code);
3457                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3458                 amd64_patch (br[1], code);
3459                 amd64_patch (br[4], code);
3460         }
3461         else
3462                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3463
3464         if (tree->flags & MONO_INST_INIT) {
3465                 int offset = 0;
3466                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3467                         amd64_push_reg (code, AMD64_RAX);
3468                         offset += 8;
3469                 }
3470                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3471                         amd64_push_reg (code, AMD64_RCX);
3472                         offset += 8;
3473                 }
3474                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3475                         amd64_push_reg (code, AMD64_RDI);
3476                         offset += 8;
3477                 }
3478
3479                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3480                 if (sreg != AMD64_RCX)
3481                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3482                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3483
3484                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3485                 if (cfg->param_area && cfg->arch.no_pushes)
3486                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3487                 amd64_cld (code);
3488 #if defined(__default_codegen__)
3489                 amd64_prefix (code, X86_REP_PREFIX);
3490                 amd64_stosl (code);
3491 #elif defined(__native_client_codegen__)
3492                 /* NaCl stos pseudo-instruction */
3493                 amd64_codegen_pre(code);
3494                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3495                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3496                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3497                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3498                 amd64_prefix (code, X86_REP_PREFIX);
3499                 amd64_stosl (code);
3500                 amd64_codegen_post(code);
3501 #endif /* __native_client_codegen__ */
3502
3503                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3504                         amd64_pop_reg (code, AMD64_RDI);
3505                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3506                         amd64_pop_reg (code, AMD64_RCX);
3507                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3508                         amd64_pop_reg (code, AMD64_RAX);
3509         }
3510         return code;
3511 }
3512
3513 static guint8*
3514 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3515 {
3516         CallInfo *cinfo;
3517         guint32 quad;
3518
3519         /* Move return value to the target register */
3520         /* FIXME: do this in the local reg allocator */
3521         switch (ins->opcode) {
3522         case OP_CALL:
3523         case OP_CALL_REG:
3524         case OP_CALL_MEMBASE:
3525         case OP_LCALL:
3526         case OP_LCALL_REG:
3527         case OP_LCALL_MEMBASE:
3528                 g_assert (ins->dreg == AMD64_RAX);
3529                 break;
3530         case OP_FCALL:
3531         case OP_FCALL_REG:
3532         case OP_FCALL_MEMBASE:
3533                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3534                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3535                 }
3536                 else {
3537                         if (ins->dreg != AMD64_XMM0)
3538                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3539                 }
3540                 break;
3541         case OP_VCALL:
3542         case OP_VCALL_REG:
3543         case OP_VCALL_MEMBASE:
3544         case OP_VCALL2:
3545         case OP_VCALL2_REG:
3546         case OP_VCALL2_MEMBASE:
3547                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3548                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3549                         MonoInst *loc = cfg->arch.vret_addr_loc;
3550
3551                         /* Load the destination address */
3552                         g_assert (loc->opcode == OP_REGOFFSET);
3553                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3554
3555                         for (quad = 0; quad < 2; quad ++) {
3556                                 switch (cinfo->ret.pair_storage [quad]) {
3557                                 case ArgInIReg:
3558                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3559                                         break;
3560                                 case ArgInFloatSSEReg:
3561                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3562                                         break;
3563                                 case ArgInDoubleSSEReg:
3564                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3565                                         break;
3566                                 case ArgNone:
3567                                         break;
3568                                 default:
3569                                         NOT_IMPLEMENTED;
3570                                 }
3571                         }
3572                 }
3573                 break;
3574         }
3575
3576         return code;
3577 }
3578
3579 #endif /* DISABLE_JIT */
3580
3581 #ifdef __APPLE__
3582 static int tls_gs_offset;
3583 #endif
3584
3585 gboolean
3586 mono_amd64_have_tls_get (void)
3587 {
3588 #ifdef __APPLE__
3589         static gboolean have_tls_get = FALSE;
3590         static gboolean inited = FALSE;
3591         guint8 *ins;
3592
3593         if (inited)
3594                 return have_tls_get;
3595
3596         ins = (guint8*)pthread_getspecific;
3597
3598         /*
3599          * We're looking for these two instructions:
3600          *
3601          * mov    %gs:[offset](,%rdi,8),%rax
3602          * retq
3603          */
3604         have_tls_get = ins [0] == 0x65 &&
3605                        ins [1] == 0x48 &&
3606                        ins [2] == 0x8b &&
3607                        ins [3] == 0x04 &&
3608                        ins [4] == 0xfd &&
3609                        ins [6] == 0x00 &&
3610                        ins [7] == 0x00 &&
3611                        ins [8] == 0x00 &&
3612                        ins [9] == 0xc3;
3613
3614         inited = TRUE;
3615
3616         tls_gs_offset = ins[5];
3617
3618         return have_tls_get;
3619 #else
3620         return TRUE;
3621 #endif
3622 }
3623
3624 /*
3625  * mono_amd64_emit_tls_get:
3626  * @code: buffer to store code to
3627  * @dreg: hard register where to place the result
3628  * @tls_offset: offset info
3629  *
3630  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3631  * the dreg register the item in the thread local storage identified
3632  * by tls_offset.
3633  *
3634  * Returns: a pointer to the end of the stored code
3635  */
3636 guint8*
3637 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3638 {
3639 #ifdef HOST_WIN32
3640         g_assert (tls_offset < 64);
3641         x86_prefix (code, X86_GS_PREFIX);
3642         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3643 #elif defined(__APPLE__)
3644         x86_prefix (code, X86_GS_PREFIX);
3645         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3646 #else
3647         if (optimize_for_xen) {
3648                 x86_prefix (code, X86_FS_PREFIX);
3649                 amd64_mov_reg_mem (code, dreg, 0, 8);
3650                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3651         } else {
3652                 x86_prefix (code, X86_FS_PREFIX);
3653                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3654         }
3655 #endif
3656         return code;
3657 }
3658
3659 /*
3660  * emit_setup_lmf:
3661  *
3662  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3663  */
3664 static guint8*
3665 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3666 {
3667         int i;
3668
3669         /*
3670          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3671          */
3672         /*
3673          * sp is saved right before calls but we need to save it here too so
3674          * async stack walks would work.
3675          */
3676         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3677         /* Skip method (only needed for trampoline LMF frames) */
3678         /* Save callee saved regs */
3679         for (i = 0; i < MONO_MAX_IREGS; ++i) {
3680                 int offset;
3681
3682                 switch (i) {
3683                 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
3684                 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
3685                 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
3686                 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
3687                 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
3688 #ifndef __native_client_codegen__
3689                 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
3690 #endif
3691 #ifdef HOST_WIN32
3692                 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
3693                 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
3694 #endif
3695                 default:
3696                         offset = -1;
3697                         break;
3698                 }
3699
3700                 if (offset != -1) {
3701                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
3702                         if ((cfg->arch.omit_fp || (i != AMD64_RBP)) && cfa_offset != -1)
3703                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
3704                 }
3705         }
3706
3707         /* These can't contain refs */
3708         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3709         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3710         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
3711         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3712         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3713
3714         /* These are handled automatically by the stack marking code */
3715         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), SLOT_NOREF);
3716         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3717         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), SLOT_NOREF);
3718         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), SLOT_NOREF);
3719         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), SLOT_NOREF);
3720         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), SLOT_NOREF);
3721 #ifdef HOST_WIN32
3722         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), SLOT_NOREF);
3723         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), SLOT_NOREF);
3724 #endif
3725
3726         return code;
3727 }
3728
3729 /*
3730  * emit_save_lmf:
3731  *
3732  *   Emit code to push an LMF structure on the LMF stack.
3733  */
3734 static guint8*
3735 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, gboolean *args_clobbered)
3736 {
3737         if ((lmf_tls_offset != -1) && !optimize_for_xen) {
3738                 /*
3739                  * Optimized version which uses the mono_lmf TLS variable instead of
3740                  * indirection through the mono_lmf_addr TLS variable.
3741                  */
3742                 /* %rax = previous_lmf */
3743                 x86_prefix (code, X86_FS_PREFIX);
3744                 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
3745
3746                 /* Save previous_lmf */
3747                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
3748                 /* Set new lmf */
3749                 if (lmf_offset == 0) {
3750                         x86_prefix (code, X86_FS_PREFIX);
3751                         amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
3752                 } else {
3753                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3754                         x86_prefix (code, X86_FS_PREFIX);
3755                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
3756                 }
3757         } else {
3758                 if (lmf_addr_tls_offset != -1) {
3759                         /* Load lmf quicky using the FS register */
3760                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
3761 #ifdef HOST_WIN32
3762                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
3763                         /* FIXME: Add a separate key for LMF to avoid this */
3764                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
3765 #endif
3766                 }
3767                 else {
3768                         /*
3769                          * The call might clobber argument registers, but they are already
3770                          * saved to the stack/global regs.
3771                          */
3772                         if (args_clobbered)
3773                                 *args_clobbered = TRUE;
3774                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3775                                                           (gpointer)"mono_get_lmf_addr", TRUE);
3776                 }
3777
3778                 /* Save lmf_addr */
3779                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3780                 /* Save previous_lmf */
3781                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
3782                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3783                 /* Set new lmf */
3784                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3785                 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
3786         }
3787
3788         return code;
3789 }
3790
3791 /*
3792  * emit_save_lmf:
3793  *
3794  *   Emit code to pop an LMF structure from the LMF stack.
3795  */
3796 static guint8*
3797 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
3798 {
3799         if ((lmf_tls_offset != -1) && !optimize_for_xen) {
3800                 /*
3801                  * Optimized version which uses the mono_lmf TLS variable instead of indirection
3802                  * through the mono_lmf_addr TLS variable.
3803                  */
3804                 /* reg = previous_lmf */
3805                 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3806                 x86_prefix (code, X86_FS_PREFIX);
3807                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
3808         } else {
3809                 /* Restore previous lmf */
3810                 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3811                 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3812                 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
3813         }
3814
3815         return code;
3816 }
3817
3818 #define REAL_PRINT_REG(text,reg) \
3819 mono_assert (reg >= 0); \
3820 amd64_push_reg (code, AMD64_RAX); \
3821 amd64_push_reg (code, AMD64_RDX); \
3822 amd64_push_reg (code, AMD64_RCX); \
3823 amd64_push_reg (code, reg); \
3824 amd64_push_imm (code, reg); \
3825 amd64_push_imm (code, text " %d %p\n"); \
3826 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3827 amd64_call_reg (code, AMD64_RAX); \
3828 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3829 amd64_pop_reg (code, AMD64_RCX); \
3830 amd64_pop_reg (code, AMD64_RDX); \
3831 amd64_pop_reg (code, AMD64_RAX);
3832
3833 /* benchmark and set based on cpu */
3834 #define LOOP_ALIGNMENT 8
3835 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3836
3837 #ifndef DISABLE_JIT
3838
3839 #if defined(__native_client__) || defined(__native_client_codegen__)
3840 void mono_nacl_gc()
3841 {
3842 #ifdef __native_client_gc__
3843         __nacl_suspend_thread_if_needed();
3844 #endif
3845 }
3846 #endif
3847
3848 void
3849 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3850 {
3851         MonoInst *ins;
3852         MonoCallInst *call;
3853         guint offset;
3854         guint8 *code = cfg->native_code + cfg->code_len;
3855         MonoInst *last_ins = NULL;
3856         guint last_offset = 0;
3857         int max_len;
3858
3859         /* Fix max_offset estimate for each successor bb */
3860         if (cfg->opt & MONO_OPT_BRANCH) {
3861                 int current_offset = cfg->code_len;
3862                 MonoBasicBlock *current_bb;
3863                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3864                         current_bb->max_offset = current_offset;
3865                         current_offset += current_bb->max_length;
3866                 }
3867         }
3868
3869         if (cfg->opt & MONO_OPT_LOOP) {
3870                 int pad, align = LOOP_ALIGNMENT;
3871                 /* set alignment depending on cpu */
3872                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3873                         pad = align - pad;
3874                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3875                         amd64_padding (code, pad);
3876                         cfg->code_len += pad;
3877                         bb->native_offset = cfg->code_len;
3878                 }
3879         }
3880
3881 #if defined(__native_client_codegen__)
3882         /* For Native Client, all indirect call/jump targets must be */
3883         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3884         /* indirectly as well.                                       */
3885         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3886                                       (bb->flags & BB_EXCEPTION_HANDLER);
3887
3888         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3889                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3890                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3891                 cfg->code_len += pad;
3892                 bb->native_offset = cfg->code_len;
3893         }
3894 #endif  /*__native_client_codegen__*/
3895
3896         if (cfg->verbose_level > 2)
3897                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3898
3899         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3900                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3901                 g_assert (!cfg->compile_aot);
3902
3903                 cov->data [bb->dfn].cil_code = bb->cil_code;
3904                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3905                 /* this is not thread save, but good enough */
3906                 amd64_inc_membase (code, AMD64_R11, 0);
3907         }
3908
3909         offset = code - cfg->native_code;
3910
3911         mono_debug_open_block (cfg, bb, offset);
3912
3913     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3914                 x86_breakpoint (code);
3915
3916         MONO_BB_FOR_EACH_INS (bb, ins) {
3917                 offset = code - cfg->native_code;
3918
3919                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3920
3921 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3922
3923                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3924                         cfg->code_size *= 2;
3925                         cfg->native_code = mono_realloc_native_code(cfg);
3926                         code = cfg->native_code + offset;
3927                         cfg->stat_code_reallocs++;
3928                 }
3929
3930                 if (cfg->debug_info)
3931                         mono_debug_record_line_number (cfg, ins, offset);
3932
3933                 switch (ins->opcode) {
3934                 case OP_BIGMUL:
3935                         amd64_mul_reg (code, ins->sreg2, TRUE);
3936                         break;
3937                 case OP_BIGMUL_UN:
3938                         amd64_mul_reg (code, ins->sreg2, FALSE);
3939                         break;
3940                 case OP_X86_SETEQ_MEMBASE:
3941                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3942                         break;
3943                 case OP_STOREI1_MEMBASE_IMM:
3944                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3945                         break;
3946                 case OP_STOREI2_MEMBASE_IMM:
3947                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3948                         break;
3949                 case OP_STOREI4_MEMBASE_IMM:
3950                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3951                         break;
3952                 case OP_STOREI1_MEMBASE_REG:
3953                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3954                         break;
3955                 case OP_STOREI2_MEMBASE_REG:
3956                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3957                         break;
3958                 /* In AMD64 NaCl, pointers are 4 bytes, */
3959                 /*  so STORE_* != STOREI8_*. Likewise below. */
3960                 case OP_STORE_MEMBASE_REG:
3961                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3962                         break;
3963                 case OP_STOREI8_MEMBASE_REG:
3964                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3965                         break;
3966                 case OP_STOREI4_MEMBASE_REG:
3967                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3968                         break;
3969                 case OP_STORE_MEMBASE_IMM:
3970 #ifndef __native_client_codegen__
3971                         /* In NaCl, this could be a PCONST type, which could */
3972                         /* mean a pointer type was copied directly into the  */
3973                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3974                         /* the value would be 0x00000000FFFFFFFF which is    */
3975                         /* not proper for an imm32 unless you cast it.       */
3976                         g_assert (amd64_is_imm32 (ins->inst_imm));
3977 #endif
3978                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3979                         break;
3980                 case OP_STOREI8_MEMBASE_IMM:
3981                         g_assert (amd64_is_imm32 (ins->inst_imm));
3982                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3983                         break;
3984                 case OP_LOAD_MEM:
3985 #ifdef __mono_ilp32__
3986                         /* In ILP32, pointers are 4 bytes, so separate these */
3987                         /* cases, use literal 8 below where we really want 8 */
3988                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3989                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3990                         break;
3991 #endif
3992                 case OP_LOADI8_MEM:
3993                         // FIXME: Decompose this earlier
3994                         if (amd64_is_imm32 (ins->inst_imm))
3995                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3996                         else {
3997                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3998                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3999                         }
4000                         break;
4001                 case OP_LOADI4_MEM:
4002                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4003                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4004                         break;
4005                 case OP_LOADU4_MEM:
4006                         // FIXME: Decompose this earlier
4007                         if (amd64_is_imm32 (ins->inst_imm))
4008                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4009                         else {
4010                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4011                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4012                         }
4013                         break;
4014                 case OP_LOADU1_MEM:
4015                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4016                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4017                         break;
4018                 case OP_LOADU2_MEM:
4019                         /* For NaCl, pointers are 4 bytes, so separate these */
4020                         /* cases, use literal 8 below where we really want 8 */
4021                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4022                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4023                         break;
4024                 case OP_LOAD_MEMBASE:
4025                         g_assert (amd64_is_imm32 (ins->inst_offset));
4026                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4027                         break;
4028                 case OP_LOADI8_MEMBASE:
4029                         /* Use literal 8 instead of sizeof pointer or */
4030                         /* register, we really want 8 for this opcode */
4031                         g_assert (amd64_is_imm32 (ins->inst_offset));
4032                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4033                         break;
4034                 case OP_LOADI4_MEMBASE:
4035                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4036                         break;
4037                 case OP_LOADU4_MEMBASE:
4038                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4039                         break;
4040                 case OP_LOADU1_MEMBASE:
4041                         /* The cpu zero extends the result into 64 bits */
4042                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4043                         break;
4044                 case OP_LOADI1_MEMBASE:
4045                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4046                         break;
4047                 case OP_LOADU2_MEMBASE:
4048                         /* The cpu zero extends the result into 64 bits */
4049                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4050                         break;
4051                 case OP_LOADI2_MEMBASE:
4052                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4053                         break;
4054                 case OP_AMD64_LOADI8_MEMINDEX:
4055                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4056                         break;
4057                 case OP_LCONV_TO_I1:
4058                 case OP_ICONV_TO_I1:
4059                 case OP_SEXT_I1:
4060                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4061                         break;
4062                 case OP_LCONV_TO_I2:
4063                 case OP_ICONV_TO_I2:
4064                 case OP_SEXT_I2:
4065                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4066                         break;
4067                 case OP_LCONV_TO_U1:
4068                 case OP_ICONV_TO_U1:
4069                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4070                         break;
4071                 case OP_LCONV_TO_U2:
4072                 case OP_ICONV_TO_U2:
4073                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4074                         break;
4075                 case OP_ZEXT_I4:
4076                         /* Clean out the upper word */
4077                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4078                         break;
4079                 case OP_SEXT_I4:
4080                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4081                         break;
4082                 case OP_COMPARE:
4083                 case OP_LCOMPARE:
4084                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4085                         break;
4086                 case OP_COMPARE_IMM:
4087                 case OP_LCOMPARE_IMM:
4088                         g_assert (amd64_is_imm32 (ins->inst_imm));
4089                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4090                         break;
4091                 case OP_X86_COMPARE_REG_MEMBASE:
4092                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4093                         break;
4094                 case OP_X86_TEST_NULL:
4095                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4096                         break;
4097                 case OP_AMD64_TEST_NULL:
4098                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4099                         break;
4100
4101                 case OP_X86_ADD_REG_MEMBASE:
4102                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4103                         break;
4104                 case OP_X86_SUB_REG_MEMBASE:
4105                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4106                         break;
4107                 case OP_X86_AND_REG_MEMBASE:
4108                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4109                         break;
4110                 case OP_X86_OR_REG_MEMBASE:
4111                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4112                         break;
4113                 case OP_X86_XOR_REG_MEMBASE:
4114                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4115                         break;
4116
4117                 case OP_X86_ADD_MEMBASE_IMM:
4118                         /* FIXME: Make a 64 version too */
4119                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4120                         break;
4121                 case OP_X86_SUB_MEMBASE_IMM:
4122                         g_assert (amd64_is_imm32 (ins->inst_imm));
4123                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4124                         break;
4125                 case OP_X86_AND_MEMBASE_IMM:
4126                         g_assert (amd64_is_imm32 (ins->inst_imm));
4127                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4128                         break;
4129                 case OP_X86_OR_MEMBASE_IMM:
4130                         g_assert (amd64_is_imm32 (ins->inst_imm));
4131                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4132                         break;
4133                 case OP_X86_XOR_MEMBASE_IMM:
4134                         g_assert (amd64_is_imm32 (ins->inst_imm));
4135                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4136                         break;
4137                 case OP_X86_ADD_MEMBASE_REG:
4138                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4139                         break;
4140                 case OP_X86_SUB_MEMBASE_REG:
4141                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4142                         break;
4143                 case OP_X86_AND_MEMBASE_REG:
4144                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4145                         break;
4146                 case OP_X86_OR_MEMBASE_REG:
4147                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4148                         break;
4149                 case OP_X86_XOR_MEMBASE_REG:
4150                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4151                         break;
4152                 case OP_X86_INC_MEMBASE:
4153                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4154                         break;
4155                 case OP_X86_INC_REG:
4156                         amd64_inc_reg_size (code, ins->dreg, 4);
4157                         break;
4158                 case OP_X86_DEC_MEMBASE:
4159                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4160                         break;
4161                 case OP_X86_DEC_REG:
4162                         amd64_dec_reg_size (code, ins->dreg, 4);
4163                         break;
4164                 case OP_X86_MUL_REG_MEMBASE:
4165                 case OP_X86_MUL_MEMBASE_REG:
4166                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4167                         break;
4168                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4169                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4170                         break;
4171                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4172                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4173                         break;
4174                 case OP_AMD64_COMPARE_MEMBASE_REG:
4175                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4176                         break;
4177                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4178                         g_assert (amd64_is_imm32 (ins->inst_imm));
4179                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4180                         break;
4181                 case OP_X86_COMPARE_MEMBASE8_IMM:
4182                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4183                         break;
4184                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4185                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4186                         break;
4187                 case OP_AMD64_COMPARE_REG_MEMBASE:
4188                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4189                         break;
4190
4191                 case OP_AMD64_ADD_REG_MEMBASE:
4192                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4193                         break;
4194                 case OP_AMD64_SUB_REG_MEMBASE:
4195                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4196                         break;
4197                 case OP_AMD64_AND_REG_MEMBASE:
4198                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4199                         break;
4200                 case OP_AMD64_OR_REG_MEMBASE:
4201                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4202                         break;
4203                 case OP_AMD64_XOR_REG_MEMBASE:
4204                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4205                         break;
4206
4207                 case OP_AMD64_ADD_MEMBASE_REG:
4208                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4209                         break;
4210                 case OP_AMD64_SUB_MEMBASE_REG:
4211                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4212                         break;
4213                 case OP_AMD64_AND_MEMBASE_REG:
4214                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4215                         break;
4216                 case OP_AMD64_OR_MEMBASE_REG:
4217                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4218                         break;
4219                 case OP_AMD64_XOR_MEMBASE_REG:
4220                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4221                         break;
4222
4223                 case OP_AMD64_ADD_MEMBASE_IMM:
4224                         g_assert (amd64_is_imm32 (ins->inst_imm));
4225                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4226                         break;
4227                 case OP_AMD64_SUB_MEMBASE_IMM:
4228                         g_assert (amd64_is_imm32 (ins->inst_imm));
4229                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4230                         break;
4231                 case OP_AMD64_AND_MEMBASE_IMM:
4232                         g_assert (amd64_is_imm32 (ins->inst_imm));
4233                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4234                         break;
4235                 case OP_AMD64_OR_MEMBASE_IMM:
4236                         g_assert (amd64_is_imm32 (ins->inst_imm));
4237                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4238                         break;
4239                 case OP_AMD64_XOR_MEMBASE_IMM:
4240                         g_assert (amd64_is_imm32 (ins->inst_imm));
4241                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4242                         break;
4243
4244                 case OP_BREAK:
4245                         amd64_breakpoint (code);
4246                         break;
4247                 case OP_RELAXED_NOP:
4248                         x86_prefix (code, X86_REP_PREFIX);
4249                         x86_nop (code);
4250                         break;
4251                 case OP_HARD_NOP:
4252                         x86_nop (code);
4253                         break;
4254                 case OP_NOP:
4255                 case OP_DUMMY_USE:
4256                 case OP_DUMMY_STORE:
4257                 case OP_NOT_REACHED:
4258                 case OP_NOT_NULL:
4259                         break;
4260                 case OP_SEQ_POINT: {
4261                         int i;
4262
4263                         /*
4264                          * Read from the single stepping trigger page. This will cause a
4265                          * SIGSEGV when single stepping is enabled.
4266                          * We do this _before_ the breakpoint, so single stepping after
4267                          * a breakpoint is hit will step to the next IL offset.
4268                          */
4269                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4270                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4271
4272                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4273                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4274                         }
4275
4276                         /*
4277                          * This is the address which is saved in seq points,
4278                          */
4279                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4280
4281                         if (cfg->compile_aot) {
4282                                 guint32 offset = code - cfg->native_code;
4283                                 guint32 val;
4284                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4285
4286                                 /* Load info var */
4287                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4288                                 val = ((offset) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4289                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4290                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4291                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4292                         } else {
4293                                 /*
4294                                  * A placeholder for a possible breakpoint inserted by
4295                                  * mono_arch_set_breakpoint ().
4296                                  */
4297                                 for (i = 0; i < breakpoint_size; ++i)
4298                                         x86_nop (code);
4299                         }
4300                         /*
4301                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4302                          * to another IL offset.
4303                          */
4304                         x86_nop (code);
4305                         break;
4306                 }
4307                 case OP_ADDCC:
4308                 case OP_LADD:
4309                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4310                         break;
4311                 case OP_ADC:
4312                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4313                         break;
4314                 case OP_ADD_IMM:
4315                 case OP_LADD_IMM:
4316                         g_assert (amd64_is_imm32 (ins->inst_imm));
4317                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4318                         break;
4319                 case OP_ADC_IMM:
4320                         g_assert (amd64_is_imm32 (ins->inst_imm));
4321                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4322                         break;
4323                 case OP_SUBCC:
4324                 case OP_LSUB:
4325                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4326                         break;
4327                 case OP_SBB:
4328                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4329                         break;
4330                 case OP_SUB_IMM:
4331                 case OP_LSUB_IMM:
4332                         g_assert (amd64_is_imm32 (ins->inst_imm));
4333                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4334                         break;
4335                 case OP_SBB_IMM:
4336                         g_assert (amd64_is_imm32 (ins->inst_imm));
4337                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4338                         break;
4339                 case OP_LAND:
4340                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4341                         break;
4342                 case OP_AND_IMM:
4343                 case OP_LAND_IMM:
4344                         g_assert (amd64_is_imm32 (ins->inst_imm));
4345                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4346                         break;
4347                 case OP_LMUL:
4348                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4349                         break;
4350                 case OP_MUL_IMM:
4351                 case OP_LMUL_IMM:
4352                 case OP_IMUL_IMM: {
4353                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4354
4355                         switch (ins->inst_imm) {
4356                         case 2:
4357                                 /* MOV r1, r2 */
4358                                 /* ADD r1, r1 */
4359                                 if (ins->dreg != ins->sreg1)
4360                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4361                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4362                                 break;
4363                         case 3:
4364                                 /* LEA r1, [r2 + r2*2] */
4365                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4366                                 break;
4367                         case 5:
4368                                 /* LEA r1, [r2 + r2*4] */
4369                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4370                                 break;
4371                         case 6:
4372                                 /* LEA r1, [r2 + r2*2] */
4373                                 /* ADD r1, r1          */
4374                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4375                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4376                                 break;
4377                         case 9:
4378                                 /* LEA r1, [r2 + r2*8] */
4379                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4380                                 break;
4381                         case 10:
4382                                 /* LEA r1, [r2 + r2*4] */
4383                                 /* ADD r1, r1          */
4384                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4385                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4386                                 break;
4387                         case 12:
4388                                 /* LEA r1, [r2 + r2*2] */
4389                                 /* SHL r1, 2           */
4390                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4391                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4392                                 break;
4393                         case 25:
4394                                 /* LEA r1, [r2 + r2*4] */
4395                                 /* LEA r1, [r1 + r1*4] */
4396                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4397                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4398                                 break;
4399                         case 100:
4400                                 /* LEA r1, [r2 + r2*4] */
4401                                 /* SHL r1, 2           */
4402                                 /* LEA r1, [r1 + r1*4] */
4403                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4404                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4405                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4406                                 break;
4407                         default:
4408                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4409                                 break;
4410                         }
4411                         break;
4412                 }
4413                 case OP_LDIV:
4414                 case OP_LREM:
4415                         /* Regalloc magic makes the div/rem cases the same */
4416                         if (ins->sreg2 == AMD64_RDX) {
4417                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4418                                 amd64_cdq (code);
4419                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4420                         } else {
4421                                 amd64_cdq (code);
4422                                 amd64_div_reg (code, ins->sreg2, TRUE);
4423                         }
4424                         break;
4425                 case OP_LDIV_UN:
4426                 case OP_LREM_UN:
4427                         if (ins->sreg2 == AMD64_RDX) {
4428                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4429                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4430                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4431                         } else {
4432                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4433                                 amd64_div_reg (code, ins->sreg2, FALSE);
4434                         }
4435                         break;
4436                 case OP_IDIV:
4437                 case OP_IREM:
4438                         if (ins->sreg2 == AMD64_RDX) {
4439                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4440                                 amd64_cdq_size (code, 4);
4441                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4442                         } else {
4443                                 amd64_cdq_size (code, 4);
4444                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4445                         }
4446                         break;
4447                 case OP_IDIV_UN:
4448                 case OP_IREM_UN:
4449                         if (ins->sreg2 == AMD64_RDX) {
4450                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4451                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4452                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4453                         } else {
4454                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4455                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4456                         }
4457                         break;
4458                 case OP_IREM_IMM: {
4459                         int power = mono_is_power_of_two (ins->inst_imm);
4460
4461                         g_assert (ins->sreg1 == X86_EAX);
4462                         g_assert (ins->dreg == X86_EAX);
4463                         g_assert (power >= 0);
4464
4465                         if (power == 0) {
4466                                 amd64_mov_reg_imm (code, ins->dreg, 0);
4467                                 break;
4468                         }
4469
4470                         /* Based on gcc code */
4471
4472                         /* Add compensation for negative dividents */
4473                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
4474                         if (power > 1)
4475                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
4476                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
4477                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
4478                         /* Compute remainder */
4479                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
4480                         /* Remove compensation */
4481                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
4482                         break;
4483                 }
4484                 case OP_LMUL_OVF:
4485                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4486                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4487                         break;
4488                 case OP_LOR:
4489                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4490                         break;
4491                 case OP_OR_IMM:
4492                 case OP_LOR_IMM:
4493                         g_assert (amd64_is_imm32 (ins->inst_imm));
4494                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4495                         break;
4496                 case OP_LXOR:
4497                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4498                         break;
4499                 case OP_XOR_IMM:
4500                 case OP_LXOR_IMM:
4501                         g_assert (amd64_is_imm32 (ins->inst_imm));
4502                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4503                         break;
4504                 case OP_LSHL:
4505                         g_assert (ins->sreg2 == AMD64_RCX);
4506                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4507                         break;
4508                 case OP_LSHR:
4509                         g_assert (ins->sreg2 == AMD64_RCX);
4510                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4511                         break;
4512                 case OP_SHR_IMM:
4513                         g_assert (amd64_is_imm32 (ins->inst_imm));
4514                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4515                         break;
4516                 case OP_LSHR_IMM:
4517                         g_assert (amd64_is_imm32 (ins->inst_imm));
4518                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4519                         break;
4520                 case OP_SHR_UN_IMM:
4521                         g_assert (amd64_is_imm32 (ins->inst_imm));
4522                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4523                         break;
4524                 case OP_LSHR_UN_IMM:
4525                         g_assert (amd64_is_imm32 (ins->inst_imm));
4526                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4527                         break;
4528                 case OP_LSHR_UN:
4529                         g_assert (ins->sreg2 == AMD64_RCX);
4530                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4531                         break;
4532                 case OP_SHL_IMM:
4533                         g_assert (amd64_is_imm32 (ins->inst_imm));
4534                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4535                         break;
4536                 case OP_LSHL_IMM:
4537                         g_assert (amd64_is_imm32 (ins->inst_imm));
4538                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4539                         break;
4540
4541                 case OP_IADDCC:
4542                 case OP_IADD:
4543                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4544                         break;
4545                 case OP_IADC:
4546                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4547                         break;
4548                 case OP_IADD_IMM:
4549                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4550                         break;
4551                 case OP_IADC_IMM:
4552                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4553                         break;
4554                 case OP_ISUBCC:
4555                 case OP_ISUB:
4556                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4557                         break;
4558                 case OP_ISBB:
4559                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4560                         break;
4561                 case OP_ISUB_IMM:
4562                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4563                         break;
4564                 case OP_ISBB_IMM:
4565                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4566                         break;
4567                 case OP_IAND:
4568                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4569                         break;
4570                 case OP_IAND_IMM:
4571                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4572                         break;
4573                 case OP_IOR:
4574                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4575                         break;
4576                 case OP_IOR_IMM:
4577                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4578                         break;
4579                 case OP_IXOR:
4580                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4581                         break;
4582                 case OP_IXOR_IMM:
4583                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4584                         break;
4585                 case OP_INEG:
4586                         amd64_neg_reg_size (code, ins->sreg1, 4);
4587                         break;
4588                 case OP_INOT:
4589                         amd64_not_reg_size (code, ins->sreg1, 4);
4590                         break;
4591                 case OP_ISHL:
4592                         g_assert (ins->sreg2 == AMD64_RCX);
4593                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4594                         break;
4595                 case OP_ISHR:
4596                         g_assert (ins->sreg2 == AMD64_RCX);
4597                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4598                         break;
4599                 case OP_ISHR_IMM:
4600                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4601                         break;
4602                 case OP_ISHR_UN_IMM:
4603                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4604                         break;
4605                 case OP_ISHR_UN:
4606                         g_assert (ins->sreg2 == AMD64_RCX);
4607                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4608                         break;
4609                 case OP_ISHL_IMM:
4610                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4611                         break;
4612                 case OP_IMUL:
4613                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4614                         break;
4615                 case OP_IMUL_OVF:
4616                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4617                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4618                         break;
4619                 case OP_IMUL_OVF_UN:
4620                 case OP_LMUL_OVF_UN: {
4621                         /* the mul operation and the exception check should most likely be split */
4622                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4623                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4624                         /*g_assert (ins->sreg2 == X86_EAX);
4625                         g_assert (ins->dreg == X86_EAX);*/
4626                         if (ins->sreg2 == X86_EAX) {
4627                                 non_eax_reg = ins->sreg1;
4628                         } else if (ins->sreg1 == X86_EAX) {
4629                                 non_eax_reg = ins->sreg2;
4630                         } else {
4631                                 /* no need to save since we're going to store to it anyway */
4632                                 if (ins->dreg != X86_EAX) {
4633                                         saved_eax = TRUE;
4634                                         amd64_push_reg (code, X86_EAX);
4635                                 }
4636                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4637                                 non_eax_reg = ins->sreg2;
4638                         }
4639                         if (ins->dreg == X86_EDX) {
4640                                 if (!saved_eax) {
4641                                         saved_eax = TRUE;
4642                                         amd64_push_reg (code, X86_EAX);
4643                                 }
4644                         } else {
4645                                 saved_edx = TRUE;
4646                                 amd64_push_reg (code, X86_EDX);
4647                         }
4648                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4649                         /* save before the check since pop and mov don't change the flags */
4650                         if (ins->dreg != X86_EAX)
4651                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4652                         if (saved_edx)
4653                                 amd64_pop_reg (code, X86_EDX);
4654                         if (saved_eax)
4655                                 amd64_pop_reg (code, X86_EAX);
4656                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4657                         break;
4658                 }
4659                 case OP_ICOMPARE:
4660                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4661                         break;
4662                 case OP_ICOMPARE_IMM:
4663                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4664                         break;
4665                 case OP_IBEQ:
4666                 case OP_IBLT:
4667                 case OP_IBGT:
4668                 case OP_IBGE:
4669                 case OP_IBLE:
4670                 case OP_LBEQ:
4671                 case OP_LBLT:
4672                 case OP_LBGT:
4673                 case OP_LBGE:
4674                 case OP_LBLE:
4675                 case OP_IBNE_UN:
4676                 case OP_IBLT_UN:
4677                 case OP_IBGT_UN:
4678                 case OP_IBGE_UN:
4679                 case OP_IBLE_UN:
4680                 case OP_LBNE_UN:
4681                 case OP_LBLT_UN:
4682                 case OP_LBGT_UN:
4683                 case OP_LBGE_UN:
4684                 case OP_LBLE_UN:
4685                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4686                         break;
4687
4688                 case OP_CMOV_IEQ:
4689                 case OP_CMOV_IGE:
4690                 case OP_CMOV_IGT:
4691                 case OP_CMOV_ILE:
4692                 case OP_CMOV_ILT:
4693                 case OP_CMOV_INE_UN:
4694                 case OP_CMOV_IGE_UN:
4695                 case OP_CMOV_IGT_UN:
4696                 case OP_CMOV_ILE_UN:
4697                 case OP_CMOV_ILT_UN:
4698                 case OP_CMOV_LEQ:
4699                 case OP_CMOV_LGE:
4700                 case OP_CMOV_LGT:
4701                 case OP_CMOV_LLE:
4702                 case OP_CMOV_LLT:
4703                 case OP_CMOV_LNE_UN:
4704                 case OP_CMOV_LGE_UN:
4705                 case OP_CMOV_LGT_UN:
4706                 case OP_CMOV_LLE_UN:
4707                 case OP_CMOV_LLT_UN:
4708                         g_assert (ins->dreg == ins->sreg1);
4709                         /* This needs to operate on 64 bit values */
4710                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4711                         break;
4712
4713                 case OP_LNOT:
4714                         amd64_not_reg (code, ins->sreg1);
4715                         break;
4716                 case OP_LNEG:
4717                         amd64_neg_reg (code, ins->sreg1);
4718                         break;
4719
4720                 case OP_ICONST:
4721                 case OP_I8CONST:
4722                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4723                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4724                         else
4725                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4726                         break;
4727                 case OP_AOTCONST:
4728                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4729                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4730                         break;
4731                 case OP_JUMP_TABLE:
4732                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4733                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4734                         break;
4735                 case OP_MOVE:
4736                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4737                         break;
4738                 case OP_AMD64_SET_XMMREG_R4: {
4739                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4740                         break;
4741                 }
4742                 case OP_AMD64_SET_XMMREG_R8: {
4743                         if (ins->dreg != ins->sreg1)
4744                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4745                         break;
4746                 }
4747                 case OP_TAILCALL: {
4748                         MonoCallInst *call = (MonoCallInst*)ins;
4749                         int pos = 0, i;
4750
4751                         /* FIXME: no tracing support... */
4752                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4753                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, TRUE);
4754
4755                         g_assert (!cfg->method->save_lmf);
4756
4757                         if (cfg->arch.omit_fp) {
4758                                 guint32 save_offset = 0;
4759                                 /* Pop callee-saved registers */
4760                                 for (i = 0; i < AMD64_NREG; ++i)
4761                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4762                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4763                                                 save_offset += 8;
4764                                         }
4765                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4766
4767                                 // FIXME:
4768                                 if (call->stack_usage)
4769                                         NOT_IMPLEMENTED;
4770                         }
4771                         else {
4772                                 for (i = 0; i < AMD64_NREG; ++i)
4773                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4774                                                 pos -= sizeof(mgreg_t);
4775
4776                                 /* Restore callee-saved registers */
4777                                 for (i = AMD64_NREG - 1; i > 0; --i) {
4778                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4779                                                 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, sizeof(mgreg_t));
4780                                                 pos += sizeof(mgreg_t);
4781                                         }
4782                                 }
4783
4784                                 /* Copy arguments on the stack to our argument area */
4785                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4786                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4787                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4788                                 }
4789
4790                                 if (pos)
4791                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4792
4793                                 amd64_leave (code);
4794                         }
4795
4796                         offset = code - cfg->native_code;
4797                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4798                         if (cfg->compile_aot)
4799                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4800                         else
4801                                 amd64_set_reg_template (code, AMD64_R11);
4802                         amd64_jump_reg (code, AMD64_R11);
4803                         ins->flags |= MONO_INST_GC_CALLSITE;
4804                         ins->backend.pc_offset = code - cfg->native_code;
4805                         break;
4806                 }
4807                 case OP_CHECK_THIS:
4808                         /* ensure ins->sreg1 is not NULL */
4809                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4810                         break;
4811                 case OP_ARGLIST: {
4812                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4813                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4814                         break;
4815                 }
4816                 case OP_CALL:
4817                 case OP_FCALL:
4818                 case OP_LCALL:
4819                 case OP_VCALL:
4820                 case OP_VCALL2:
4821                 case OP_VOIDCALL:
4822                         call = (MonoCallInst*)ins;
4823                         /*
4824                          * The AMD64 ABI forces callers to know about varargs.
4825                          */
4826                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4827                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4828                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4829                                 /*
4830                                  * Since the unmanaged calling convention doesn't contain a
4831                                  * 'vararg' entry, we have to treat every pinvoke call as a
4832                                  * potential vararg call.
4833                                  */
4834                                 guint32 nregs, i;
4835                                 nregs = 0;
4836                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4837                                         if (call->used_fregs & (1 << i))
4838                                                 nregs ++;
4839                                 if (!nregs)
4840                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4841                                 else
4842                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4843                         }
4844
4845                         if (ins->flags & MONO_INST_HAS_METHOD)
4846                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4847                         else
4848                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4849                         ins->flags |= MONO_INST_GC_CALLSITE;
4850                         ins->backend.pc_offset = code - cfg->native_code;
4851                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4852                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4853                         code = emit_move_return_value (cfg, ins, code);
4854                         break;
4855                 case OP_FCALL_REG:
4856                 case OP_LCALL_REG:
4857                 case OP_VCALL_REG:
4858                 case OP_VCALL2_REG:
4859                 case OP_VOIDCALL_REG:
4860                 case OP_CALL_REG:
4861                         call = (MonoCallInst*)ins;
4862
4863                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4864                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4865                                 ins->sreg1 = AMD64_R11;
4866                         }
4867
4868                         /*
4869                          * The AMD64 ABI forces callers to know about varargs.
4870                          */
4871                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4872                                 if (ins->sreg1 == AMD64_RAX) {
4873                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4874                                         ins->sreg1 = AMD64_R11;
4875                                 }
4876                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4877                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4878                                 /*
4879                                  * Since the unmanaged calling convention doesn't contain a
4880                                  * 'vararg' entry, we have to treat every pinvoke call as a
4881                                  * potential vararg call.
4882                                  */
4883                                 guint32 nregs, i;
4884                                 nregs = 0;
4885                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4886                                         if (call->used_fregs & (1 << i))
4887                                                 nregs ++;
4888                                 if (ins->sreg1 == AMD64_RAX) {
4889                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4890                                         ins->sreg1 = AMD64_R11;
4891                                 }
4892                                 if (!nregs)
4893                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4894                                 else
4895                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4896                         }
4897
4898                         amd64_call_reg (code, ins->sreg1);
4899                         ins->flags |= MONO_INST_GC_CALLSITE;
4900                         ins->backend.pc_offset = code - cfg->native_code;
4901                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4902                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4903                         code = emit_move_return_value (cfg, ins, code);
4904                         break;
4905                 case OP_FCALL_MEMBASE:
4906                 case OP_LCALL_MEMBASE:
4907                 case OP_VCALL_MEMBASE:
4908                 case OP_VCALL2_MEMBASE:
4909                 case OP_VOIDCALL_MEMBASE:
4910                 case OP_CALL_MEMBASE:
4911                         call = (MonoCallInst*)ins;
4912
4913                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4914                         ins->flags |= MONO_INST_GC_CALLSITE;
4915                         ins->backend.pc_offset = code - cfg->native_code;
4916                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4917                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4918                         code = emit_move_return_value (cfg, ins, code);
4919                         break;
4920                 case OP_DYN_CALL: {
4921                         int i;
4922                         MonoInst *var = cfg->dyn_call_var;
4923
4924                         g_assert (var->opcode == OP_REGOFFSET);
4925
4926                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4927                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4928                         /* r10 = ftn */
4929                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4930
4931                         /* Save args buffer */
4932                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4933
4934                         /* Set argument registers */
4935                         for (i = 0; i < PARAM_REGS; ++i)
4936                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4937
4938                         /* Make the call */
4939                         amd64_call_reg (code, AMD64_R10);
4940
4941                         ins->flags |= MONO_INST_GC_CALLSITE;
4942                         ins->backend.pc_offset = code - cfg->native_code;
4943
4944                         /* Save result */
4945                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4946                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4947                         break;
4948                 }
4949                 case OP_AMD64_SAVE_SP_TO_LMF: {
4950                         MonoInst *lmf_var = cfg->arch.lmf_var;
4951                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4952                         break;
4953                 }
4954                 case OP_X86_PUSH:
4955                         g_assert (!cfg->arch.no_pushes);
4956                         amd64_push_reg (code, ins->sreg1);
4957                         break;
4958                 case OP_X86_PUSH_IMM:
4959                         g_assert (!cfg->arch.no_pushes);
4960                         g_assert (amd64_is_imm32 (ins->inst_imm));
4961                         amd64_push_imm (code, ins->inst_imm);
4962                         break;
4963                 case OP_X86_PUSH_MEMBASE:
4964                         g_assert (!cfg->arch.no_pushes);
4965                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4966                         break;
4967                 case OP_X86_PUSH_OBJ: {
4968                         int size = ALIGN_TO (ins->inst_imm, 8);
4969
4970                         g_assert (!cfg->arch.no_pushes);
4971
4972                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4973                         amd64_push_reg (code, AMD64_RDI);
4974                         amd64_push_reg (code, AMD64_RSI);
4975                         amd64_push_reg (code, AMD64_RCX);
4976                         if (ins->inst_offset)
4977                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4978                         else
4979                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4980                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4981                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4982                         amd64_cld (code);
4983                         amd64_prefix (code, X86_REP_PREFIX);
4984                         amd64_movsd (code);
4985                         amd64_pop_reg (code, AMD64_RCX);
4986                         amd64_pop_reg (code, AMD64_RSI);
4987                         amd64_pop_reg (code, AMD64_RDI);
4988                         break;
4989                 }
4990                 case OP_X86_LEA:
4991                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4992                         break;
4993                 case OP_X86_LEA_MEMBASE:
4994                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4995                         break;
4996                 case OP_X86_XCHG:
4997                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4998                         break;
4999                 case OP_LOCALLOC:
5000                         /* keep alignment */
5001                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5002                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5003                         code = mono_emit_stack_alloc (cfg, code, ins);
5004                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5005                         if (cfg->param_area && cfg->arch.no_pushes)
5006                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5007                         break;
5008                 case OP_LOCALLOC_IMM: {
5009                         guint32 size = ins->inst_imm;
5010                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5011
5012                         if (ins->flags & MONO_INST_INIT) {
5013                                 if (size < 64) {
5014                                         int i;
5015
5016                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5017                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5018
5019                                         for (i = 0; i < size; i += 8)
5020                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5021                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5022                                 } else {
5023                                         amd64_mov_reg_imm (code, ins->dreg, size);
5024                                         ins->sreg1 = ins->dreg;
5025
5026                                         code = mono_emit_stack_alloc (cfg, code, ins);
5027                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5028                                 }
5029                         } else {
5030                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5031                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5032                         }
5033                         if (cfg->param_area && cfg->arch.no_pushes)
5034                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5035                         break;
5036                 }
5037                 case OP_THROW: {
5038                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5039                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5040                                              (gpointer)"mono_arch_throw_exception", FALSE);
5041                         ins->flags |= MONO_INST_GC_CALLSITE;
5042                         ins->backend.pc_offset = code - cfg->native_code;
5043                         break;
5044                 }
5045                 case OP_RETHROW: {
5046                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5047                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5048                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5049                         ins->flags |= MONO_INST_GC_CALLSITE;
5050                         ins->backend.pc_offset = code - cfg->native_code;
5051                         break;
5052                 }
5053                 case OP_CALL_HANDLER:
5054                         /* Align stack */
5055                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5056                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5057                         amd64_call_imm (code, 0);
5058                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5059                         /* Restore stack alignment */
5060                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5061                         break;
5062                 case OP_START_HANDLER: {
5063                         /* Even though we're saving RSP, use sizeof */
5064                         /* gpointer because spvar is of type IntPtr */
5065                         /* see: mono_create_spvar_for_region */
5066                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5067                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5068
5069                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5070                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5071                                 cfg->param_area && cfg->arch.no_pushes) {
5072                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5073                         }
5074                         break;
5075                 }
5076                 case OP_ENDFINALLY: {
5077                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5078                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5079                         amd64_ret (code);
5080                         break;
5081                 }
5082                 case OP_ENDFILTER: {
5083                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5084                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5085                         /* The local allocator will put the result into RAX */
5086                         amd64_ret (code);
5087                         break;
5088                 }
5089
5090                 case OP_LABEL:
5091                         ins->inst_c0 = code - cfg->native_code;
5092                         break;
5093                 case OP_BR:
5094                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5095                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5096                         //break;
5097                                 if (ins->inst_target_bb->native_offset) {
5098                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5099                                 } else {
5100                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5101                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5102                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5103                                                 x86_jump8 (code, 0);
5104                                         else
5105                                                 x86_jump32 (code, 0);
5106                         }
5107                         break;
5108                 case OP_BR_REG:
5109                         amd64_jump_reg (code, ins->sreg1);
5110                         break;
5111                 case OP_CEQ:
5112                 case OP_LCEQ:
5113                 case OP_ICEQ:
5114                 case OP_CLT:
5115                 case OP_LCLT:
5116                 case OP_ICLT:
5117                 case OP_CGT:
5118                 case OP_ICGT:
5119                 case OP_LCGT:
5120                 case OP_CLT_UN:
5121                 case OP_LCLT_UN:
5122                 case OP_ICLT_UN:
5123                 case OP_CGT_UN:
5124                 case OP_LCGT_UN:
5125                 case OP_ICGT_UN:
5126                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5127                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5128                         break;
5129                 case OP_COND_EXC_EQ:
5130                 case OP_COND_EXC_NE_UN:
5131                 case OP_COND_EXC_LT:
5132                 case OP_COND_EXC_LT_UN:
5133                 case OP_COND_EXC_GT:
5134                 case OP_COND_EXC_GT_UN:
5135                 case OP_COND_EXC_GE:
5136                 case OP_COND_EXC_GE_UN:
5137                 case OP_COND_EXC_LE:
5138                 case OP_COND_EXC_LE_UN:
5139                 case OP_COND_EXC_IEQ:
5140                 case OP_COND_EXC_INE_UN:
5141                 case OP_COND_EXC_ILT:
5142                 case OP_COND_EXC_ILT_UN:
5143                 case OP_COND_EXC_IGT:
5144                 case OP_COND_EXC_IGT_UN:
5145                 case OP_COND_EXC_IGE:
5146                 case OP_COND_EXC_IGE_UN:
5147                 case OP_COND_EXC_ILE:
5148                 case OP_COND_EXC_ILE_UN:
5149                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5150                         break;
5151                 case OP_COND_EXC_OV:
5152                 case OP_COND_EXC_NO:
5153                 case OP_COND_EXC_C:
5154                 case OP_COND_EXC_NC:
5155                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5156                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5157                         break;
5158                 case OP_COND_EXC_IOV:
5159                 case OP_COND_EXC_INO:
5160                 case OP_COND_EXC_IC:
5161                 case OP_COND_EXC_INC:
5162                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5163                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5164                         break;
5165
5166                 /* floating point opcodes */
5167                 case OP_R8CONST: {
5168                         double d = *(double *)ins->inst_p0;
5169
5170                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5171                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5172                         }
5173                         else {
5174                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5175                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5176                         }
5177                         break;
5178                 }
5179                 case OP_R4CONST: {
5180                         float f = *(float *)ins->inst_p0;
5181
5182                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5183                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5184                         }
5185                         else {
5186                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5187                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5188                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5189                         }
5190                         break;
5191                 }
5192                 case OP_STORER8_MEMBASE_REG:
5193                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5194                         break;
5195                 case OP_LOADR8_MEMBASE:
5196                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5197                         break;
5198                 case OP_STORER4_MEMBASE_REG:
5199                         /* This requires a double->single conversion */
5200                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5201                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5202                         break;
5203                 case OP_LOADR4_MEMBASE:
5204                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5205                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5206                         break;
5207                 case OP_ICONV_TO_R4: /* FIXME: change precision */
5208                 case OP_ICONV_TO_R8:
5209                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5210                         break;
5211                 case OP_LCONV_TO_R4: /* FIXME: change precision */
5212                 case OP_LCONV_TO_R8:
5213                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5214                         break;
5215                 case OP_FCONV_TO_R4:
5216                         /* FIXME: nothing to do ?? */
5217                         break;
5218                 case OP_FCONV_TO_I1:
5219                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5220                         break;
5221                 case OP_FCONV_TO_U1:
5222                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5223                         break;
5224                 case OP_FCONV_TO_I2:
5225                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5226                         break;
5227                 case OP_FCONV_TO_U2:
5228                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5229                         break;
5230                 case OP_FCONV_TO_U4:
5231                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5232                         break;
5233                 case OP_FCONV_TO_I4:
5234                 case OP_FCONV_TO_I:
5235                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5236                         break;
5237                 case OP_FCONV_TO_I8:
5238                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5239                         break;
5240                 case OP_LCONV_TO_R_UN: {
5241                         guint8 *br [2];
5242
5243                         /* Based on gcc code */
5244                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5245                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5246
5247                         /* Positive case */
5248                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5249                         br [1] = code; x86_jump8 (code, 0);
5250                         amd64_patch (br [0], code);
5251
5252                         /* Negative case */
5253                         /* Save to the red zone */
5254                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5255                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5256                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5257                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5258                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5259                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5260                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5261                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5262                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5263                         /* Restore */
5264                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5265                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5266                         amd64_patch (br [1], code);
5267                         break;
5268                 }
5269                 case OP_LCONV_TO_OVF_U4:
5270                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5271                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5272                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5273                         break;
5274                 case OP_LCONV_TO_OVF_I4_UN:
5275                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5276                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5277                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5278                         break;
5279                 case OP_FMOVE:
5280                         if (ins->dreg != ins->sreg1)
5281                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5282                         break;
5283                 case OP_FADD:
5284                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5285                         break;
5286                 case OP_FSUB:
5287                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5288                         break;
5289                 case OP_FMUL:
5290                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5291                         break;
5292                 case OP_FDIV:
5293                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5294                         break;
5295                 case OP_FNEG: {
5296                         static double r8_0 = -0.0;
5297
5298                         g_assert (ins->sreg1 == ins->dreg);
5299
5300                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5301                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5302                         break;
5303                 }
5304                 case OP_SIN:
5305                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5306                         break;
5307                 case OP_COS:
5308                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5309                         break;
5310                 case OP_ABS: {
5311                         static guint64 d = 0x7fffffffffffffffUL;
5312
5313                         g_assert (ins->sreg1 == ins->dreg);
5314
5315                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5316                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5317                         break;
5318                 }
5319                 case OP_SQRT:
5320                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5321                         break;
5322                 case OP_IMIN:
5323                         g_assert (cfg->opt & MONO_OPT_CMOV);
5324                         g_assert (ins->dreg == ins->sreg1);
5325                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5326                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5327                         break;
5328                 case OP_IMIN_UN:
5329                         g_assert (cfg->opt & MONO_OPT_CMOV);
5330                         g_assert (ins->dreg == ins->sreg1);
5331                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5332                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5333                         break;
5334                 case OP_IMAX:
5335                         g_assert (cfg->opt & MONO_OPT_CMOV);
5336                         g_assert (ins->dreg == ins->sreg1);
5337                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5338                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5339                         break;
5340                 case OP_IMAX_UN:
5341                         g_assert (cfg->opt & MONO_OPT_CMOV);
5342                         g_assert (ins->dreg == ins->sreg1);
5343                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5344                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5345                         break;
5346                 case OP_LMIN:
5347                         g_assert (cfg->opt & MONO_OPT_CMOV);
5348                         g_assert (ins->dreg == ins->sreg1);
5349                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5350                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5351                         break;
5352                 case OP_LMIN_UN:
5353                         g_assert (cfg->opt & MONO_OPT_CMOV);
5354                         g_assert (ins->dreg == ins->sreg1);
5355                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5356                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5357                         break;
5358                 case OP_LMAX:
5359                         g_assert (cfg->opt & MONO_OPT_CMOV);
5360                         g_assert (ins->dreg == ins->sreg1);
5361                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5362                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5363                         break;
5364                 case OP_LMAX_UN:
5365                         g_assert (cfg->opt & MONO_OPT_CMOV);
5366                         g_assert (ins->dreg == ins->sreg1);
5367                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5368                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5369                         break;
5370                 case OP_X86_FPOP:
5371                         break;
5372                 case OP_FCOMPARE:
5373                         /*
5374                          * The two arguments are swapped because the fbranch instructions
5375                          * depend on this for the non-sse case to work.
5376                          */
5377                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5378                         break;
5379                 case OP_FCEQ: {
5380                         /* zeroing the register at the start results in
5381                          * shorter and faster code (we can also remove the widening op)
5382                          */
5383                         guchar *unordered_check;
5384                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5385                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5386                         unordered_check = code;
5387                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5388                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5389                         amd64_patch (unordered_check, code);
5390                         break;
5391                 }
5392                 case OP_FCLT:
5393                 case OP_FCLT_UN:
5394                         /* zeroing the register at the start results in
5395                          * shorter and faster code (we can also remove the widening op)
5396                          */
5397                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5398                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5399                         if (ins->opcode == OP_FCLT_UN) {
5400                                 guchar *unordered_check = code;
5401                                 guchar *jump_to_end;
5402                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5403                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5404                                 jump_to_end = code;
5405                                 x86_jump8 (code, 0);
5406                                 amd64_patch (unordered_check, code);
5407                                 amd64_inc_reg (code, ins->dreg);
5408                                 amd64_patch (jump_to_end, code);
5409                         } else {
5410                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5411                         }
5412                         break;
5413                 case OP_FCGT:
5414                 case OP_FCGT_UN: {
5415                         /* zeroing the register at the start results in
5416                          * shorter and faster code (we can also remove the widening op)
5417                          */
5418                         guchar *unordered_check;
5419                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5420                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5421                         if (ins->opcode == OP_FCGT) {
5422                                 unordered_check = code;
5423                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5424                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5425                                 amd64_patch (unordered_check, code);
5426                         } else {
5427                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5428                         }
5429                         break;
5430                 }
5431                 case OP_FCLT_MEMBASE:
5432                 case OP_FCGT_MEMBASE:
5433                 case OP_FCLT_UN_MEMBASE:
5434                 case OP_FCGT_UN_MEMBASE:
5435                 case OP_FCEQ_MEMBASE: {
5436                         guchar *unordered_check, *jump_to_end;
5437                         int x86_cond;
5438
5439                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5440                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5441
5442                         switch (ins->opcode) {
5443                         case OP_FCEQ_MEMBASE:
5444                                 x86_cond = X86_CC_EQ;
5445                                 break;
5446                         case OP_FCLT_MEMBASE:
5447                         case OP_FCLT_UN_MEMBASE:
5448                                 x86_cond = X86_CC_LT;
5449                                 break;
5450                         case OP_FCGT_MEMBASE:
5451                         case OP_FCGT_UN_MEMBASE:
5452                                 x86_cond = X86_CC_GT;
5453                                 break;
5454                         default:
5455                                 g_assert_not_reached ();
5456                         }
5457
5458                         unordered_check = code;
5459                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5460                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5461
5462                         switch (ins->opcode) {
5463                         case OP_FCEQ_MEMBASE:
5464                         case OP_FCLT_MEMBASE:
5465                         case OP_FCGT_MEMBASE:
5466                                 amd64_patch (unordered_check, code);
5467                                 break;
5468                         case OP_FCLT_UN_MEMBASE:
5469                         case OP_FCGT_UN_MEMBASE:
5470                                 jump_to_end = code;
5471                                 x86_jump8 (code, 0);
5472                                 amd64_patch (unordered_check, code);
5473                                 amd64_inc_reg (code, ins->dreg);
5474                                 amd64_patch (jump_to_end, code);
5475                                 break;
5476                         default:
5477                                 break;
5478                         }
5479                         break;
5480                 }
5481                 case OP_FBEQ: {
5482                         guchar *jump = code;
5483                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5484                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5485                         amd64_patch (jump, code);
5486                         break;
5487                 }
5488                 case OP_FBNE_UN:
5489                         /* Branch if C013 != 100 */
5490                         /* branch if !ZF or (PF|CF) */
5491                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5492                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5493                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5494                         break;
5495                 case OP_FBLT:
5496                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5497                         break;
5498                 case OP_FBLT_UN:
5499                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5500                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5501                         break;
5502                 case OP_FBGT:
5503                 case OP_FBGT_UN:
5504                         if (ins->opcode == OP_FBGT) {
5505                                 guchar *br1;
5506
5507                                 /* skip branch if C1=1 */
5508                                 br1 = code;
5509                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5510                                 /* branch if (C0 | C3) = 1 */
5511                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5512                                 amd64_patch (br1, code);
5513                                 break;
5514                         } else {
5515                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5516                         }
5517                         break;
5518                 case OP_FBGE: {
5519                         /* Branch if C013 == 100 or 001 */
5520                         guchar *br1;
5521
5522                         /* skip branch if C1=1 */
5523                         br1 = code;
5524                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5525                         /* branch if (C0 | C3) = 1 */
5526                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5527                         amd64_patch (br1, code);
5528                         break;
5529                 }
5530                 case OP_FBGE_UN:
5531                         /* Branch if C013 == 000 */
5532                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5533                         break;
5534                 case OP_FBLE: {
5535                         /* Branch if C013=000 or 100 */
5536                         guchar *br1;
5537
5538                         /* skip branch if C1=1 */
5539                         br1 = code;
5540                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5541                         /* branch if C0=0 */
5542                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5543                         amd64_patch (br1, code);
5544                         break;
5545                 }
5546                 case OP_FBLE_UN:
5547                         /* Branch if C013 != 001 */
5548                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5549                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5550                         break;
5551                 case OP_CKFINITE:
5552                         /* Transfer value to the fp stack */
5553                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5554                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5555                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5556
5557                         amd64_push_reg (code, AMD64_RAX);
5558                         amd64_fxam (code);
5559                         amd64_fnstsw (code);
5560                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5561                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5562                         amd64_pop_reg (code, AMD64_RAX);
5563                         amd64_fstp (code, 0);
5564                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5565                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5566                         break;
5567                 case OP_TLS_GET: {
5568                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5569                         break;
5570                 }
5571                 case OP_MEMORY_BARRIER: {
5572                         switch (ins->backend.memory_barrier_kind) {
5573                         case StoreLoadBarrier:
5574                         case FullBarrier:
5575                                 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5576                                 x86_prefix (code, X86_LOCK_PREFIX);
5577                                 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5578                                 break;
5579                         }
5580                         break;
5581                 }
5582                 case OP_ATOMIC_ADD_I4:
5583                 case OP_ATOMIC_ADD_I8: {
5584                         int dreg = ins->dreg;
5585                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5586
5587                         if (dreg == ins->inst_basereg)
5588                                 dreg = AMD64_R11;
5589
5590                         if (dreg != ins->sreg2)
5591                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5592
5593                         x86_prefix (code, X86_LOCK_PREFIX);
5594                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5595
5596                         if (dreg != ins->dreg)
5597                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5598
5599                         break;
5600                 }
5601                 case OP_ATOMIC_ADD_NEW_I4:
5602                 case OP_ATOMIC_ADD_NEW_I8: {
5603                         int dreg = ins->dreg;
5604                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
5605
5606                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5607                                 dreg = AMD64_R11;
5608
5609                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5610                         amd64_prefix (code, X86_LOCK_PREFIX);
5611                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5612                         /* dreg contains the old value, add with sreg2 value */
5613                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5614
5615                         if (ins->dreg != dreg)
5616                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5617
5618                         break;
5619                 }
5620                 case OP_ATOMIC_EXCHANGE_I4:
5621                 case OP_ATOMIC_EXCHANGE_I8: {
5622                         guchar *br[2];
5623                         int sreg2 = ins->sreg2;
5624                         int breg = ins->inst_basereg;
5625                         guint32 size;
5626                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5627
5628                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5629                                 size = 8;
5630                         else
5631                                 size = 4;
5632
5633                         /*
5634                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5635                          * an explanation of how this works.
5636                          */
5637
5638                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5639                          * hack to overcome limits in x86 reg allocator
5640                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5641                          */
5642                         g_assert (ins->dreg == AMD64_RAX);
5643
5644                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5645                                 /* Highly unlikely, but possible */
5646                                 need_push = TRUE;
5647
5648                         /* The pushes invalidate rsp */
5649                         if ((breg == AMD64_RAX) || need_push) {
5650                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5651                                 breg = AMD64_R11;
5652                         }
5653
5654                         /* We need the EAX reg for the comparand */
5655                         if (ins->sreg2 == AMD64_RAX) {
5656                                 if (breg != AMD64_R11) {
5657                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5658                                         sreg2 = AMD64_R11;
5659                                 } else {
5660                                         g_assert (need_push);
5661                                         amd64_push_reg (code, AMD64_RDX);
5662                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5663                                         sreg2 = AMD64_RDX;
5664                                         rdx_pushed = TRUE;
5665                                 }
5666                         }
5667
5668                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5669
5670                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5671                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5672                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5673                         amd64_patch (br [1], br [0]);
5674
5675                         if (rdx_pushed)
5676                                 amd64_pop_reg (code, AMD64_RDX);
5677
5678                         break;
5679                 }
5680                 case OP_ATOMIC_CAS_I4:
5681                 case OP_ATOMIC_CAS_I8: {
5682                         guint32 size;
5683
5684                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5685                                 size = 8;
5686                         else
5687                                 size = 4;
5688
5689                         /*
5690                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5691                          * an explanation of how this works.
5692                          */
5693                         g_assert (ins->sreg3 == AMD64_RAX);
5694                         g_assert (ins->sreg1 != AMD64_RAX);
5695                         g_assert (ins->sreg1 != ins->sreg2);
5696
5697                         amd64_prefix (code, X86_LOCK_PREFIX);
5698                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5699
5700                         if (ins->dreg != AMD64_RAX)
5701                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5702                         break;
5703                 }
5704                 case OP_CARD_TABLE_WBARRIER: {
5705                         int ptr = ins->sreg1;
5706                         int value = ins->sreg2;
5707                         guchar *br;
5708                         int nursery_shift, card_table_shift;
5709                         gpointer card_table_mask;
5710                         size_t nursery_size;
5711
5712                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5713                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5714                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5715
5716                         /*If either point to the stack we can simply avoid the WB. This happens due to
5717                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5718                          */
5719                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5720                                 continue;
5721
5722                         /*
5723                          * We need one register we can clobber, we choose EDX and make sreg1
5724                          * fixed EAX to work around limitations in the local register allocator.
5725                          * sreg2 might get allocated to EDX, but that is not a problem since
5726                          * we use it before clobbering EDX.
5727                          */
5728                         g_assert (ins->sreg1 == AMD64_RAX);
5729
5730                         /*
5731                          * This is the code we produce:
5732                          *
5733                          *   edx = value
5734                          *   edx >>= nursery_shift
5735                          *   cmp edx, (nursery_start >> nursery_shift)
5736                          *   jne done
5737                          *   edx = ptr
5738                          *   edx >>= card_table_shift
5739                          *   edx += cardtable
5740                          *   [edx] = 1
5741                          * done:
5742                          */
5743
5744                         if (mono_gc_card_table_nursery_check ()) {
5745                                 if (value != AMD64_RDX)
5746                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5747                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5748                                 if (shifted_nursery_start >> 31) {
5749                                         /*
5750                                          * The value we need to compare against is 64 bits, so we need
5751                                          * another spare register.  We use RBX, which we save and
5752                                          * restore.
5753                                          */
5754                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5755                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5756                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5757                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5758                                 } else {
5759                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5760                                 }
5761                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5762                         }
5763                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5764                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5765                         if (card_table_mask)
5766                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5767
5768                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5769                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5770
5771                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5772                         if (mono_gc_card_table_nursery_check ())
5773                                 x86_patch (br, code);
5774                         break;
5775                 }
5776 #ifdef MONO_ARCH_SIMD_INTRINSICS
5777                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5778                 case OP_ADDPS:
5779                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5780                         break;
5781                 case OP_DIVPS:
5782                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5783                         break;
5784                 case OP_MULPS:
5785                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5786                         break;
5787                 case OP_SUBPS:
5788                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5789                         break;
5790                 case OP_MAXPS:
5791                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5792                         break;
5793                 case OP_MINPS:
5794                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5795                         break;
5796                 case OP_COMPPS:
5797                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5798                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5799                         break;
5800                 case OP_ANDPS:
5801                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5802                         break;
5803                 case OP_ANDNPS:
5804                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5805                         break;
5806                 case OP_ORPS:
5807                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5808                         break;
5809                 case OP_XORPS:
5810                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5811                         break;
5812                 case OP_SQRTPS:
5813                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5814                         break;
5815                 case OP_RSQRTPS:
5816                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5817                         break;
5818                 case OP_RCPPS:
5819                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5820                         break;
5821                 case OP_ADDSUBPS:
5822                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5823                         break;
5824                 case OP_HADDPS:
5825                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5826                         break;
5827                 case OP_HSUBPS:
5828                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5829                         break;
5830                 case OP_DUPPS_HIGH:
5831                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5832                         break;
5833                 case OP_DUPPS_LOW:
5834                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5835                         break;
5836
5837                 case OP_PSHUFLEW_HIGH:
5838                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5839                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5840                         break;
5841                 case OP_PSHUFLEW_LOW:
5842                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5843                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5844                         break;
5845                 case OP_PSHUFLED:
5846                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5847                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5848                         break;
5849                 case OP_SHUFPS:
5850                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5851                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5852                         break;
5853                 case OP_SHUFPD:
5854                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5855                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5856                         break;
5857
5858                 case OP_ADDPD:
5859                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5860                         break;
5861                 case OP_DIVPD:
5862                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5863                         break;
5864                 case OP_MULPD:
5865                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5866                         break;
5867                 case OP_SUBPD:
5868                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5869                         break;
5870                 case OP_MAXPD:
5871                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5872                         break;
5873                 case OP_MINPD:
5874                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5875                         break;
5876                 case OP_COMPPD:
5877                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5878                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5879                         break;
5880                 case OP_ANDPD:
5881                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5882                         break;
5883                 case OP_ANDNPD:
5884                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5885                         break;
5886                 case OP_ORPD:
5887                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5888                         break;
5889                 case OP_XORPD:
5890                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5891                         break;
5892                 case OP_SQRTPD:
5893                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5894                         break;
5895                 case OP_ADDSUBPD:
5896                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5897                         break;
5898                 case OP_HADDPD:
5899                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5900                         break;
5901                 case OP_HSUBPD:
5902                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5903                         break;
5904                 case OP_DUPPD:
5905                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5906                         break;
5907
5908                 case OP_EXTRACT_MASK:
5909                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5910                         break;
5911
5912                 case OP_PAND:
5913                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5914                         break;
5915                 case OP_POR:
5916                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5917                         break;
5918                 case OP_PXOR:
5919                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5920                         break;
5921
5922                 case OP_PADDB:
5923                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5924                         break;
5925                 case OP_PADDW:
5926                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5927                         break;
5928                 case OP_PADDD:
5929                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5930                         break;
5931                 case OP_PADDQ:
5932                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5933                         break;
5934
5935                 case OP_PSUBB:
5936                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5937                         break;
5938                 case OP_PSUBW:
5939                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5940                         break;
5941                 case OP_PSUBD:
5942                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5943                         break;
5944                 case OP_PSUBQ:
5945                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5946                         break;
5947
5948                 case OP_PMAXB_UN:
5949                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5950                         break;
5951                 case OP_PMAXW_UN:
5952                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5953                         break;
5954                 case OP_PMAXD_UN:
5955                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5956                         break;
5957
5958                 case OP_PMAXB:
5959                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5960                         break;
5961                 case OP_PMAXW:
5962                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5963                         break;
5964                 case OP_PMAXD:
5965                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5966                         break;
5967
5968                 case OP_PAVGB_UN:
5969                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5970                         break;
5971                 case OP_PAVGW_UN:
5972                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5973                         break;
5974
5975                 case OP_PMINB_UN:
5976                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978                 case OP_PMINW_UN:
5979                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981                 case OP_PMIND_UN:
5982                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984
5985                 case OP_PMINB:
5986                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988                 case OP_PMINW:
5989                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5990                         break;
5991                 case OP_PMIND:
5992                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5993                         break;
5994
5995                 case OP_PCMPEQB:
5996                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998                 case OP_PCMPEQW:
5999                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_PCMPEQD:
6002                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6003                         break;
6004                 case OP_PCMPEQQ:
6005                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007
6008                 case OP_PCMPGTB:
6009                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011                 case OP_PCMPGTW:
6012                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014                 case OP_PCMPGTD:
6015                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017                 case OP_PCMPGTQ:
6018                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6019                         break;
6020
6021                 case OP_PSUM_ABS_DIFF:
6022                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024
6025                 case OP_UNPACK_LOWB:
6026                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028                 case OP_UNPACK_LOWW:
6029                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6030                         break;
6031                 case OP_UNPACK_LOWD:
6032                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_UNPACK_LOWQ:
6035                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_UNPACK_LOWPS:
6038                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040                 case OP_UNPACK_LOWPD:
6041                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043
6044                 case OP_UNPACK_HIGHB:
6045                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047                 case OP_UNPACK_HIGHW:
6048                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6049                         break;
6050                 case OP_UNPACK_HIGHD:
6051                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6052                         break;
6053                 case OP_UNPACK_HIGHQ:
6054                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6055                         break;
6056                 case OP_UNPACK_HIGHPS:
6057                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6058                         break;
6059                 case OP_UNPACK_HIGHPD:
6060                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062
6063                 case OP_PACKW:
6064                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6065                         break;
6066                 case OP_PACKD:
6067                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6068                         break;
6069                 case OP_PACKW_UN:
6070                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6071                         break;
6072                 case OP_PACKD_UN:
6073                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6074                         break;
6075
6076                 case OP_PADDB_SAT_UN:
6077                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079                 case OP_PSUBB_SAT_UN:
6080                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082                 case OP_PADDW_SAT_UN:
6083                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6084                         break;
6085                 case OP_PSUBW_SAT_UN:
6086                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6087                         break;
6088
6089                 case OP_PADDB_SAT:
6090                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_PSUBB_SAT:
6093                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_PADDW_SAT:
6096                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098                 case OP_PSUBW_SAT:
6099                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6100                         break;
6101
6102                 case OP_PMULW:
6103                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_PMULD:
6106                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108                 case OP_PMULQ:
6109                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6110                         break;
6111                 case OP_PMULW_HIGH_UN:
6112                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114                 case OP_PMULW_HIGH:
6115                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6116                         break;
6117
6118                 case OP_PSHRW:
6119                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6120                         break;
6121                 case OP_PSHRW_REG:
6122                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6123                         break;
6124
6125                 case OP_PSARW:
6126                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6127                         break;
6128                 case OP_PSARW_REG:
6129                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6130                         break;
6131
6132                 case OP_PSHLW:
6133                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6134                         break;
6135                 case OP_PSHLW_REG:
6136                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6137                         break;
6138
6139                 case OP_PSHRD:
6140                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6141                         break;
6142                 case OP_PSHRD_REG:
6143                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6144                         break;
6145
6146                 case OP_PSARD:
6147                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6148                         break;
6149                 case OP_PSARD_REG:
6150                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6151                         break;
6152
6153                 case OP_PSHLD:
6154                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6155                         break;
6156                 case OP_PSHLD_REG:
6157                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6158                         break;
6159
6160                 case OP_PSHRQ:
6161                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6162                         break;
6163                 case OP_PSHRQ_REG:
6164                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6165                         break;
6166
6167                 /*TODO: This is appart of the sse spec but not added
6168                 case OP_PSARQ:
6169                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6170                         break;
6171                 case OP_PSARQ_REG:
6172                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6173                         break;
6174                 */
6175
6176                 case OP_PSHLQ:
6177                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6178                         break;
6179                 case OP_PSHLQ_REG:
6180                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6181                         break;
6182                 case OP_CVTDQ2PD:
6183                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6184                         break;
6185                 case OP_CVTDQ2PS:
6186                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6187                         break;
6188                 case OP_CVTPD2DQ:
6189                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6190                         break;
6191                 case OP_CVTPD2PS:
6192                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6193                         break;
6194                 case OP_CVTPS2DQ:
6195                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6196                         break;
6197                 case OP_CVTPS2PD:
6198                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6199                         break;
6200                 case OP_CVTTPD2DQ:
6201                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6202                         break;
6203                 case OP_CVTTPS2DQ:
6204                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6205                         break;
6206
6207                 case OP_ICONV_TO_X:
6208                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6209                         break;
6210                 case OP_EXTRACT_I4:
6211                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6212                         break;
6213                 case OP_EXTRACT_I8:
6214                         if (ins->inst_c0) {
6215                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6216                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6217                         } else {
6218                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6219                         }
6220                         break;
6221                 case OP_EXTRACT_I1:
6222                 case OP_EXTRACT_U1:
6223                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6224                         if (ins->inst_c0)
6225                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6226                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6227                         break;
6228                 case OP_EXTRACT_I2:
6229                 case OP_EXTRACT_U2:
6230                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6231                         if (ins->inst_c0)
6232                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6233                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6234                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6235                         break;
6236                 case OP_EXTRACT_R8:
6237                         if (ins->inst_c0)
6238                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6239                         else
6240                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6241                         break;
6242                 case OP_INSERT_I2:
6243                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6244                         break;
6245                 case OP_EXTRACTX_U2:
6246                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6247                         break;
6248                 case OP_INSERTX_U1_SLOW:
6249                         /*sreg1 is the extracted ireg (scratch)
6250                         /sreg2 is the to be inserted ireg (scratch)
6251                         /dreg is the xreg to receive the value*/
6252
6253                         /*clear the bits from the extracted word*/
6254                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6255                         /*shift the value to insert if needed*/
6256                         if (ins->inst_c0 & 1)
6257                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6258                         /*join them together*/
6259                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6260                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6261                         break;
6262                 case OP_INSERTX_I4_SLOW:
6263                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6264                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6265                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6266                         break;
6267                 case OP_INSERTX_I8_SLOW:
6268                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6269                         if (ins->inst_c0)
6270                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6271                         else
6272                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6273                         break;
6274
6275                 case OP_INSERTX_R4_SLOW:
6276                         switch (ins->inst_c0) {
6277                         case 0:
6278                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6279                                 break;
6280                         case 1:
6281                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6282                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6283                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6284                                 break;
6285                         case 2:
6286                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6287                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6288                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6289                                 break;
6290                         case 3:
6291                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6292                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6293                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6294                                 break;
6295                         }
6296                         break;
6297                 case OP_INSERTX_R8_SLOW:
6298                         if (ins->inst_c0)
6299                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6300                         else
6301                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6302                         break;
6303                 case OP_STOREX_MEMBASE_REG:
6304                 case OP_STOREX_MEMBASE:
6305                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6306                         break;
6307                 case OP_LOADX_MEMBASE:
6308                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6309                         break;
6310                 case OP_LOADX_ALIGNED_MEMBASE:
6311                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6312                         break;
6313                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6314                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6315                         break;
6316                 case OP_STOREX_NTA_MEMBASE_REG:
6317                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6318                         break;
6319                 case OP_PREFETCH_MEMBASE:
6320                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6321                         break;
6322
6323                 case OP_XMOVE:
6324                         /*FIXME the peephole pass should have killed this*/
6325                         if (ins->dreg != ins->sreg1)
6326                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6327                         break;
6328                 case OP_XZERO:
6329                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6330                         break;
6331                 case OP_ICONV_TO_R8_RAW:
6332                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6333                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6334                         break;
6335
6336                 case OP_FCONV_TO_R8_X:
6337                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6338                         break;
6339
6340                 case OP_XCONV_R8_TO_I4:
6341                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6342                         switch (ins->backend.source_opcode) {
6343                         case OP_FCONV_TO_I1:
6344                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6345                                 break;
6346                         case OP_FCONV_TO_U1:
6347                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6348                                 break;
6349                         case OP_FCONV_TO_I2:
6350                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6351                                 break;
6352                         case OP_FCONV_TO_U2:
6353                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6354                                 break;
6355                         }
6356                         break;
6357
6358                 case OP_EXPAND_I2:
6359                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6360                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6361                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6362                         break;
6363                 case OP_EXPAND_I4:
6364                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6365                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6366                         break;
6367                 case OP_EXPAND_I8:
6368                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6369                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6370                         break;
6371                 case OP_EXPAND_R4:
6372                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6373                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6374                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6375                         break;
6376                 case OP_EXPAND_R8:
6377                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6378                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6379                         break;
6380 #endif
6381                 case OP_LIVERANGE_START: {
6382                         if (cfg->verbose_level > 1)
6383                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6384                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6385                         break;
6386                 }
6387                 case OP_LIVERANGE_END: {
6388                         if (cfg->verbose_level > 1)
6389                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6390                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6391                         break;
6392                 }
6393                 case OP_NACL_GC_SAFE_POINT: {
6394 #if defined(__native_client_codegen__)
6395                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6396 #endif
6397                         break;
6398                 }
6399                 case OP_GC_LIVENESS_DEF:
6400                 case OP_GC_LIVENESS_USE:
6401                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6402                         ins->backend.pc_offset = code - cfg->native_code;
6403                         break;
6404                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6405                         ins->backend.pc_offset = code - cfg->native_code;
6406                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6407                         break;
6408                 default:
6409                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6410                         g_assert_not_reached ();
6411                 }
6412
6413                 if ((code - cfg->native_code - offset) > max_len) {
6414 #if !defined(__native_client_codegen__)
6415                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6416                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6417                         g_assert_not_reached ();
6418 #endif
6419                 }
6420
6421                 last_ins = ins;
6422                 last_offset = offset;
6423         }
6424
6425         cfg->code_len = code - cfg->native_code;
6426 }
6427
6428 #endif /* DISABLE_JIT */
6429
6430 void
6431 mono_arch_register_lowlevel_calls (void)
6432 {
6433         /* The signature doesn't matter */
6434         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6435 }
6436
6437 void
6438 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6439 {
6440         MonoJumpInfo *patch_info;
6441         gboolean compile_aot = !run_cctors;
6442
6443         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6444                 unsigned char *ip = patch_info->ip.i + code;
6445                 unsigned char *target;
6446
6447                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6448
6449                 if (compile_aot) {
6450                         switch (patch_info->type) {
6451                         case MONO_PATCH_INFO_BB:
6452                         case MONO_PATCH_INFO_LABEL:
6453                                 break;
6454                         default:
6455                                 /* No need to patch these */
6456                                 continue;
6457                         }
6458                 }
6459
6460                 switch (patch_info->type) {
6461                 case MONO_PATCH_INFO_NONE:
6462                         continue;
6463                 case MONO_PATCH_INFO_METHOD_REL:
6464                 case MONO_PATCH_INFO_R8:
6465                 case MONO_PATCH_INFO_R4:
6466                         g_assert_not_reached ();
6467                         continue;
6468                 case MONO_PATCH_INFO_BB:
6469                         break;
6470                 default:
6471                         break;
6472                 }
6473
6474                 /*
6475                  * Debug code to help track down problems where the target of a near call is
6476                  * is not valid.
6477                  */
6478                 if (amd64_is_near_call (ip)) {
6479                         gint64 disp = (guint8*)target - (guint8*)ip;
6480
6481                         if (!amd64_is_imm32 (disp)) {
6482                                 printf ("TYPE: %d\n", patch_info->type);
6483                                 switch (patch_info->type) {
6484                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6485                                         printf ("V: %s\n", patch_info->data.name);
6486                                         break;
6487                                 case MONO_PATCH_INFO_METHOD_JUMP:
6488                                 case MONO_PATCH_INFO_METHOD:
6489                                         printf ("V: %s\n", patch_info->data.method->name);
6490                                         break;
6491                                 default:
6492                                         break;
6493                                 }
6494                         }
6495                 }
6496
6497                 amd64_patch (ip, (gpointer)target);
6498         }
6499 }
6500
6501 #ifndef DISABLE_JIT
6502
6503 static int
6504 get_max_epilog_size (MonoCompile *cfg)
6505 {
6506         int max_epilog_size = 16;
6507
6508         if (cfg->method->save_lmf)
6509                 max_epilog_size += 256;
6510
6511         if (mono_jit_trace_calls != NULL)
6512                 max_epilog_size += 50;
6513
6514         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6515                 max_epilog_size += 50;
6516
6517         max_epilog_size += (AMD64_NREG * 2);
6518
6519         return max_epilog_size;
6520 }
6521
6522 /*
6523  * This macro is used for testing whenever the unwinder works correctly at every point
6524  * where an async exception can happen.
6525  */
6526 /* This will generate a SIGSEGV at the given point in the code */
6527 #define async_exc_point(code) do { \
6528     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6529          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6530              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6531          cfg->arch.async_point_count ++; \
6532     } \
6533 } while (0)
6534
6535 guint8 *
6536 mono_arch_emit_prolog (MonoCompile *cfg)
6537 {
6538         MonoMethod *method = cfg->method;
6539         MonoBasicBlock *bb;
6540         MonoMethodSignature *sig;
6541         MonoInst *ins;
6542         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6543         guint8 *code;
6544         CallInfo *cinfo;
6545         MonoInst *lmf_var = cfg->arch.lmf_var;
6546         gboolean args_clobbered = FALSE;
6547         gboolean trace = FALSE;
6548 #ifdef __native_client_codegen__
6549         guint alignment_check;
6550 #endif
6551
6552         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
6553
6554 #if defined(__default_codegen__)
6555         code = cfg->native_code = g_malloc (cfg->code_size);
6556 #elif defined(__native_client_codegen__)
6557         /* native_code_alloc is not 32-byte aligned, native_code is. */
6558         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6559
6560         /* Align native_code to next nearest kNaclAlignment byte. */
6561         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6562         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6563
6564         code = cfg->native_code;
6565
6566         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6567         g_assert (alignment_check == 0);
6568 #endif
6569
6570         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6571                 trace = TRUE;
6572
6573         /* Amount of stack space allocated by register saving code */
6574         pos = 0;
6575
6576         /* Offset between RSP and the CFA */
6577         cfa_offset = 0;
6578
6579         /*
6580          * The prolog consists of the following parts:
6581          * FP present:
6582          * - push rbp, mov rbp, rsp
6583          * - save callee saved regs using pushes
6584          * - allocate frame
6585          * - save rgctx if needed
6586          * - save lmf if needed
6587          * FP not present:
6588          * - allocate frame
6589          * - save rgctx if needed
6590          * - save lmf if needed
6591          * - save callee saved regs using moves
6592          */
6593
6594         // CFA = sp + 8
6595         cfa_offset = 8;
6596         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6597         // IP saved at CFA - 8
6598         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6599         async_exc_point (code);
6600         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6601
6602         if (!cfg->arch.omit_fp) {
6603                 amd64_push_reg (code, AMD64_RBP);
6604                 cfa_offset += 8;
6605                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6606                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6607                 async_exc_point (code);
6608 #ifdef HOST_WIN32
6609                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6610 #endif
6611                 /* These are handled automatically by the stack marking code */
6612                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6613
6614                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6615                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6616                 async_exc_point (code);
6617 #ifdef HOST_WIN32
6618                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6619 #endif
6620         }
6621
6622         /* Save callee saved registers */
6623         if (!cfg->arch.omit_fp && !method->save_lmf) {
6624                 int offset = cfa_offset;
6625
6626                 for (i = 0; i < AMD64_NREG; ++i)
6627                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6628                                 amd64_push_reg (code, i);
6629                                 pos += 8; /* AMD64 push inst is always 8 bytes, no way to change it */
6630                                 offset += 8;
6631                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
6632                                 async_exc_point (code);
6633
6634                                 /* These are handled automatically by the stack marking code */
6635                                 mini_gc_set_slot_type_from_cfa (cfg, - offset, SLOT_NOREF);
6636                         }
6637         }
6638
6639         /* The param area is always at offset 0 from sp */
6640         /* This needs to be allocated here, since it has to come after the spill area */
6641         if (cfg->arch.no_pushes && cfg->param_area) {
6642                 if (cfg->arch.omit_fp)
6643                         // FIXME:
6644                         g_assert_not_reached ();
6645                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6646         }
6647
6648         if (cfg->arch.omit_fp) {
6649                 /*
6650                  * On enter, the stack is misaligned by the pushing of the return
6651                  * address. It is either made aligned by the pushing of %rbp, or by
6652                  * this.
6653                  */
6654                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6655                 if ((alloc_size % 16) == 0) {
6656                         alloc_size += 8;
6657                         /* Mark the padding slot as NOREF */
6658                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6659                 }
6660         } else {
6661                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6662                 if (cfg->stack_offset != alloc_size) {
6663                         /* Mark the padding slot as NOREF */
6664                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6665                 }
6666                 cfg->arch.sp_fp_offset = alloc_size;
6667                 alloc_size -= pos;
6668         }
6669
6670         cfg->arch.stack_alloc_size = alloc_size;
6671
6672         /* Allocate stack frame */
6673         if (alloc_size) {
6674                 /* See mono_emit_stack_alloc */
6675 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6676                 guint32 remaining_size = alloc_size;
6677                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6678                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6679                 guint32 offset = code - cfg->native_code;
6680                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6681                         while (required_code_size >= (cfg->code_size - offset))
6682                                 cfg->code_size *= 2;
6683                         cfg->native_code = mono_realloc_native_code (cfg);
6684                         code = cfg->native_code + offset;
6685                         cfg->stat_code_reallocs++;
6686                 }
6687
6688                 while (remaining_size >= 0x1000) {
6689                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6690                         if (cfg->arch.omit_fp) {
6691                                 cfa_offset += 0x1000;
6692                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6693                         }
6694                         async_exc_point (code);
6695 #ifdef HOST_WIN32
6696                         if (cfg->arch.omit_fp)
6697                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6698 #endif
6699
6700                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6701                         remaining_size -= 0x1000;
6702                 }
6703                 if (remaining_size) {
6704                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6705                         if (cfg->arch.omit_fp) {
6706                                 cfa_offset += remaining_size;
6707                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6708                                 async_exc_point (code);
6709                         }
6710 #ifdef HOST_WIN32
6711                         if (cfg->arch.omit_fp)
6712                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6713 #endif
6714                 }
6715 #else
6716                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6717                 if (cfg->arch.omit_fp) {
6718                         cfa_offset += alloc_size;
6719                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6720                         async_exc_point (code);
6721                 }
6722 #endif
6723         }
6724
6725         /* Stack alignment check */
6726 #if 0
6727         {
6728                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6729                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6730                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6731                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6732                 amd64_breakpoint (code);
6733         }
6734 #endif
6735
6736 #ifndef TARGET_WIN32
6737         if (mini_get_debug_options ()->init_stacks) {
6738                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6739
6740                 /* Save registers to the red zone */
6741                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6742                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6743
6744                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6745                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6746                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6747
6748                 amd64_cld (code);
6749 #if defined(__default_codegen__)
6750                 amd64_prefix (code, X86_REP_PREFIX);
6751                 amd64_stosl (code);
6752 #elif defined(__native_client_codegen__)
6753                 /* NaCl stos pseudo-instruction */
6754                 amd64_codegen_pre (code);
6755                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6756                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6757                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6758                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6759                 amd64_prefix (code, X86_REP_PREFIX);
6760                 amd64_stosl (code);
6761                 amd64_codegen_post (code);
6762 #endif /* __native_client_codegen__ */
6763
6764                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6765                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6766         }
6767 #endif
6768
6769         /* Save LMF */
6770         if (method->save_lmf) {
6771                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6772         }
6773
6774         /* Save callee saved registers */
6775         if (cfg->arch.omit_fp && !method->save_lmf) {
6776                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6777
6778                 /* Save caller saved registers after sp is adjusted */
6779                 /* The registers are saved at the bottom of the frame */
6780                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6781                 for (i = 0; i < AMD64_NREG; ++i)
6782                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6783                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
6784                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6785
6786                                 /* These are handled automatically by the stack marking code */
6787                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6788
6789                                 save_area_offset += 8;
6790                                 async_exc_point (code);
6791                         }
6792         }
6793
6794         /* store runtime generic context */
6795         if (cfg->rgctx_var) {
6796                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6797                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6798
6799                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6800
6801                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6802                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6803         }
6804
6805         /* compute max_length in order to use short forward jumps */
6806         max_epilog_size = get_max_epilog_size (cfg);
6807         if (cfg->opt & MONO_OPT_BRANCH) {
6808                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6809                         MonoInst *ins;
6810                         int max_length = 0;
6811
6812                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6813                                 max_length += 6;
6814                         /* max alignment for loops */
6815                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6816                                 max_length += LOOP_ALIGNMENT;
6817 #ifdef __native_client_codegen__
6818                         /* max alignment for native client */
6819                         max_length += kNaClAlignment;
6820 #endif
6821
6822                         MONO_BB_FOR_EACH_INS (bb, ins) {
6823 #ifdef __native_client_codegen__
6824                                 {
6825                                         int space_in_block = kNaClAlignment -
6826                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6827                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6828                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6829                                                 max_length += space_in_block;
6830                                         }
6831                                 }
6832 #endif  /*__native_client_codegen__*/
6833                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6834                         }
6835
6836                         /* Take prolog and epilog instrumentation into account */
6837                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6838                                 max_length += max_epilog_size;
6839
6840                         bb->max_length = max_length;
6841                 }
6842         }
6843
6844         sig = mono_method_signature (method);
6845         pos = 0;
6846
6847         cinfo = cfg->arch.cinfo;
6848
6849         if (sig->ret->type != MONO_TYPE_VOID) {
6850                 /* Save volatile arguments to the stack */
6851                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6852                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6853         }
6854
6855         /* Keep this in sync with emit_load_volatile_arguments */
6856         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6857                 ArgInfo *ainfo = cinfo->args + i;
6858                 gint32 stack_offset;
6859                 MonoType *arg_type;
6860
6861                 ins = cfg->args [i];
6862
6863                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6864                         /* Unused arguments */
6865                         continue;
6866
6867                 if (sig->hasthis && (i == 0))
6868                         arg_type = &mono_defaults.object_class->byval_arg;
6869                 else
6870                         arg_type = sig->params [i - sig->hasthis];
6871
6872                 stack_offset = ainfo->offset + ARGS_OFFSET;
6873
6874                 if (cfg->globalra) {
6875                         /* All the other moves are done by the register allocator */
6876                         switch (ainfo->storage) {
6877                         case ArgInFloatSSEReg:
6878                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6879                                 break;
6880                         case ArgValuetypeInReg:
6881                                 for (quad = 0; quad < 2; quad ++) {
6882                                         switch (ainfo->pair_storage [quad]) {
6883                                         case ArgInIReg:
6884                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6885                                                 break;
6886                                         case ArgInFloatSSEReg:
6887                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6888                                                 break;
6889                                         case ArgInDoubleSSEReg:
6890                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6891                                                 break;
6892                                         case ArgNone:
6893                                                 break;
6894                                         default:
6895                                                 g_assert_not_reached ();
6896                                         }
6897                                 }
6898                                 break;
6899                         default:
6900                                 break;
6901                         }
6902
6903                         continue;
6904                 }
6905
6906                 /* Save volatile arguments to the stack */
6907                 if (ins->opcode != OP_REGVAR) {
6908                         switch (ainfo->storage) {
6909                         case ArgInIReg: {
6910                                 guint32 size = 8;
6911
6912                                 /* FIXME: I1 etc */
6913                                 /*
6914                                 if (stack_offset & 0x1)
6915                                         size = 1;
6916                                 else if (stack_offset & 0x2)
6917                                         size = 2;
6918                                 else if (stack_offset & 0x4)
6919                                         size = 4;
6920                                 else
6921                                         size = 8;
6922                                 */
6923                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6924
6925                                 /*
6926                                  * Save the original location of 'this',
6927                                  * get_generic_info_from_stack_frame () needs this to properly look up
6928                                  * the argument value during the handling of async exceptions.
6929                                  */
6930                                 if (ins == cfg->args [0]) {
6931                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6932                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6933                                 }
6934                                 break;
6935                         }
6936                         case ArgInFloatSSEReg:
6937                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6938                                 break;
6939                         case ArgInDoubleSSEReg:
6940                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6941                                 break;
6942                         case ArgValuetypeInReg:
6943                                 for (quad = 0; quad < 2; quad ++) {
6944                                         switch (ainfo->pair_storage [quad]) {
6945                                         case ArgInIReg:
6946                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6947                                                 break;
6948                                         case ArgInFloatSSEReg:
6949                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6950                                                 break;
6951                                         case ArgInDoubleSSEReg:
6952                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6953                                                 break;
6954                                         case ArgNone:
6955                                                 break;
6956                                         default:
6957                                                 g_assert_not_reached ();
6958                                         }
6959                                 }
6960                                 break;
6961                         case ArgValuetypeAddrInIReg:
6962                                 if (ainfo->pair_storage [0] == ArgInIReg)
6963                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6964                                 break;
6965                         default:
6966                                 break;
6967                         }
6968                 } else {
6969                         /* Argument allocated to (non-volatile) register */
6970                         switch (ainfo->storage) {
6971                         case ArgInIReg:
6972                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6973                                 break;
6974                         case ArgOnStack:
6975                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6976                                 break;
6977                         default:
6978                                 g_assert_not_reached ();
6979                         }
6980
6981                         if (ins == cfg->args [0]) {
6982                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6983                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6984                         }
6985                 }
6986         }
6987
6988         if (method->save_lmf) {
6989                 code = emit_save_lmf (cfg, code, lmf_var->inst_offset, &args_clobbered);
6990         }
6991
6992         if (trace) {
6993                 args_clobbered = TRUE;
6994                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6995         }
6996
6997         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6998                 args_clobbered = TRUE;
6999
7000         /*
7001          * Optimize the common case of the first bblock making a call with the same
7002          * arguments as the method. This works because the arguments are still in their
7003          * original argument registers.
7004          * FIXME: Generalize this
7005          */
7006         if (!args_clobbered) {
7007                 MonoBasicBlock *first_bb = cfg->bb_entry;
7008                 MonoInst *next;
7009
7010                 next = mono_bb_first_ins (first_bb);
7011                 if (!next && first_bb->next_bb) {
7012                         first_bb = first_bb->next_bb;
7013                         next = mono_bb_first_ins (first_bb);
7014                 }
7015
7016                 if (first_bb->in_count > 1)
7017                         next = NULL;
7018
7019                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7020                         ArgInfo *ainfo = cinfo->args + i;
7021                         gboolean match = FALSE;
7022
7023                         ins = cfg->args [i];
7024                         if (ins->opcode != OP_REGVAR) {
7025                                 switch (ainfo->storage) {
7026                                 case ArgInIReg: {
7027                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7028                                                 if (next->dreg == ainfo->reg) {
7029                                                         NULLIFY_INS (next);
7030                                                         match = TRUE;
7031                                                 } else {
7032                                                         next->opcode = OP_MOVE;
7033                                                         next->sreg1 = ainfo->reg;
7034                                                         /* Only continue if the instruction doesn't change argument regs */
7035                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7036                                                                 match = TRUE;
7037                                                 }
7038                                         }
7039                                         break;
7040                                 }
7041                                 default:
7042                                         break;
7043                                 }
7044                         } else {
7045                                 /* Argument allocated to (non-volatile) register */
7046                                 switch (ainfo->storage) {
7047                                 case ArgInIReg:
7048                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7049                                                 NULLIFY_INS (next);
7050                                                 match = TRUE;
7051                                         }
7052                                         break;
7053                                 default:
7054                                         break;
7055                                 }
7056                         }
7057
7058                         if (match) {
7059                                 next = next->next;
7060                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7061                                 if (!next)
7062                                         break;
7063                         }
7064                 }
7065         }
7066
7067         if (cfg->gen_seq_points) {
7068                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7069
7070                 /* Initialize seq_point_info_var */
7071                 if (cfg->compile_aot) {
7072                         /* Initialize the variable from a GOT slot */
7073                         /* Same as OP_AOTCONST */
7074                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7075                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7076                         g_assert (info_var->opcode == OP_REGOFFSET);
7077                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7078                 }
7079
7080                 /* Initialize ss_trigger_page_var */
7081                 ins = cfg->arch.ss_trigger_page_var;
7082
7083                 g_assert (ins->opcode == OP_REGOFFSET);
7084
7085                 if (cfg->compile_aot) {
7086                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7087                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7088                 } else {
7089                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7090                 }
7091                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7092         }
7093
7094         cfg->code_len = code - cfg->native_code;
7095
7096         g_assert (cfg->code_len < cfg->code_size);
7097
7098         return code;
7099 }
7100
7101 void
7102 mono_arch_emit_epilog (MonoCompile *cfg)
7103 {
7104         MonoMethod *method = cfg->method;
7105         int quad, pos, i;
7106         guint8 *code;
7107         int max_epilog_size;
7108         CallInfo *cinfo;
7109         gint32 lmf_offset = cfg->arch.lmf_var ? ((MonoInst*)cfg->arch.lmf_var)->inst_offset : -1;
7110
7111         max_epilog_size = get_max_epilog_size (cfg);
7112
7113         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7114                 cfg->code_size *= 2;
7115                 cfg->native_code = mono_realloc_native_code (cfg);
7116                 cfg->stat_code_reallocs++;
7117         }
7118
7119         code = cfg->native_code + cfg->code_len;
7120
7121         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7122                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7123
7124         /* the code restoring the registers must be kept in sync with OP_JMP */
7125         pos = 0;
7126
7127         if (method->save_lmf) {
7128                 /* check if we need to restore protection of the stack after a stack overflow */
7129                 if (mono_get_jit_tls_offset () != -1) {
7130                         guint8 *patch;
7131                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7132                         /* we load the value in a separate instruction: this mechanism may be
7133                          * used later as a safer way to do thread interruption
7134                          */
7135                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7136                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7137                         patch = code;
7138                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7139                         /* note that the call trampoline will preserve eax/edx */
7140                         x86_call_reg (code, X86_ECX);
7141                         x86_patch (patch, code);
7142                 } else {
7143                         /* FIXME: maybe save the jit tls in the prolog */
7144                 }
7145
7146                 code = emit_restore_lmf (cfg, code, lmf_offset);
7147
7148                 /* Restore caller saved regs */
7149                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7150                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7151                 }
7152                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
7153                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
7154                 }
7155                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
7156                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
7157                 }
7158                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
7159                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
7160                 }
7161                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
7162                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
7163                 }
7164                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
7165 #if defined(__default_codegen__)
7166                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
7167 #elif defined(__native_client_codegen__)
7168                         g_assert_not_reached();
7169 #endif
7170                 }
7171 #ifdef HOST_WIN32
7172                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
7173                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
7174                 }
7175                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
7176                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
7177                 }
7178 #endif
7179         } else {
7180
7181                 if (cfg->arch.omit_fp) {
7182                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7183
7184                         for (i = 0; i < AMD64_NREG; ++i)
7185                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7186                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
7187                                         save_area_offset += 8;
7188                                 }
7189                 }
7190                 else {
7191                         for (i = 0; i < AMD64_NREG; ++i)
7192                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
7193                                         pos -= sizeof(mgreg_t);
7194
7195                         if (pos) {
7196                                 if (pos == - sizeof(mgreg_t)) {
7197                                         /* Only one register, so avoid lea */
7198                                         for (i = AMD64_NREG - 1; i > 0; --i)
7199                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7200                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
7201                                                 }
7202                                 }
7203                                 else {
7204                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
7205
7206                                         /* Pop registers in reverse order */
7207                                         for (i = AMD64_NREG - 1; i > 0; --i)
7208                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7209                                                         amd64_pop_reg (code, i);
7210                                                 }
7211                                 }
7212                         }
7213                 }
7214         }
7215
7216         /* Load returned vtypes into registers if needed */
7217         cinfo = cfg->arch.cinfo;
7218         if (cinfo->ret.storage == ArgValuetypeInReg) {
7219                 ArgInfo *ainfo = &cinfo->ret;
7220                 MonoInst *inst = cfg->ret;
7221
7222                 for (quad = 0; quad < 2; quad ++) {
7223                         switch (ainfo->pair_storage [quad]) {
7224                         case ArgInIReg:
7225                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7226                                 break;
7227                         case ArgInFloatSSEReg:
7228                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7229                                 break;
7230                         case ArgInDoubleSSEReg:
7231                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7232                                 break;
7233                         case ArgNone:
7234                                 break;
7235                         default:
7236                                 g_assert_not_reached ();
7237                         }
7238                 }
7239         }
7240
7241         if (cfg->arch.omit_fp) {
7242                 if (cfg->arch.stack_alloc_size)
7243                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7244         } else {
7245                 amd64_leave (code);
7246         }
7247         async_exc_point (code);
7248         amd64_ret (code);
7249
7250         cfg->code_len = code - cfg->native_code;
7251
7252         g_assert (cfg->code_len < cfg->code_size);
7253 }
7254
7255 void
7256 mono_arch_emit_exceptions (MonoCompile *cfg)
7257 {
7258         MonoJumpInfo *patch_info;
7259         int nthrows, i;
7260         guint8 *code;
7261         MonoClass *exc_classes [16];
7262         guint8 *exc_throw_start [16], *exc_throw_end [16];
7263         guint32 code_size = 0;
7264
7265         /* Compute needed space */
7266         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7267                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7268                         code_size += 40;
7269                 if (patch_info->type == MONO_PATCH_INFO_R8)
7270                         code_size += 8 + 15; /* sizeof (double) + alignment */
7271                 if (patch_info->type == MONO_PATCH_INFO_R4)
7272                         code_size += 4 + 15; /* sizeof (float) + alignment */
7273                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7274                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7275         }
7276
7277 #ifdef __native_client_codegen__
7278         /* Give us extra room on Native Client.  This could be   */
7279         /* more carefully calculated, but bundle alignment makes */
7280         /* it much trickier, so *2 like other places is good.    */
7281         code_size *= 2;
7282 #endif
7283
7284         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7285                 cfg->code_size *= 2;
7286                 cfg->native_code = mono_realloc_native_code (cfg);
7287                 cfg->stat_code_reallocs++;
7288         }
7289
7290         code = cfg->native_code + cfg->code_len;
7291
7292         /* add code to raise exceptions */
7293         nthrows = 0;
7294         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7295                 switch (patch_info->type) {
7296                 case MONO_PATCH_INFO_EXC: {
7297                         MonoClass *exc_class;
7298                         guint8 *buf, *buf2;
7299                         guint32 throw_ip;
7300
7301                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7302
7303                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7304                         g_assert (exc_class);
7305                         throw_ip = patch_info->ip.i;
7306
7307                         //x86_breakpoint (code);
7308                         /* Find a throw sequence for the same exception class */
7309                         for (i = 0; i < nthrows; ++i)
7310                                 if (exc_classes [i] == exc_class)
7311                                         break;
7312                         if (i < nthrows) {
7313                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7314                                 x86_jump_code (code, exc_throw_start [i]);
7315                                 patch_info->type = MONO_PATCH_INFO_NONE;
7316                         }
7317                         else {
7318                                 buf = code;
7319                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7320                                 buf2 = code;
7321
7322                                 if (nthrows < 16) {
7323                                         exc_classes [nthrows] = exc_class;
7324                                         exc_throw_start [nthrows] = code;
7325                                 }
7326                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7327
7328                                 patch_info->type = MONO_PATCH_INFO_NONE;
7329
7330                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7331
7332                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7333                                 while (buf < buf2)
7334                                         x86_nop (buf);
7335
7336                                 if (nthrows < 16) {
7337                                         exc_throw_end [nthrows] = code;
7338                                         nthrows ++;
7339                                 }
7340                         }
7341                         break;
7342                 }
7343                 default:
7344                         /* do nothing */
7345                         break;
7346                 }
7347                 g_assert(code < cfg->native_code + cfg->code_size);
7348         }
7349
7350         /* Handle relocations with RIP relative addressing */
7351         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7352                 gboolean remove = FALSE;
7353                 guint8 *orig_code = code;
7354
7355                 switch (patch_info->type) {
7356                 case MONO_PATCH_INFO_R8:
7357                 case MONO_PATCH_INFO_R4: {
7358                         guint8 *pos, *patch_pos;
7359                         guint32 target_pos;
7360
7361                         /* The SSE opcodes require a 16 byte alignment */
7362 #if defined(__default_codegen__)
7363                         code = (guint8*)ALIGN_TO (code, 16);
7364 #elif defined(__native_client_codegen__)
7365                         {
7366                                 /* Pad this out with HLT instructions  */
7367                                 /* or we can get garbage bytes emitted */
7368                                 /* which will fail validation          */
7369                                 guint8 *aligned_code;
7370                                 /* extra align to make room for  */
7371                                 /* mov/push below                      */
7372                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7373                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7374                                 /* The technique of hiding data in an  */
7375                                 /* instruction has a problem here: we  */
7376                                 /* need the data aligned to a 16-byte  */
7377                                 /* boundary but the instruction cannot */
7378                                 /* cross the bundle boundary. so only  */
7379                                 /* odd multiples of 16 can be used     */
7380                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7381                                         aligned_code += 16;
7382                                 }
7383                                 while (code < aligned_code) {
7384                                         *(code++) = 0xf4; /* hlt */
7385                                 }
7386                         }
7387 #endif
7388
7389                         pos = cfg->native_code + patch_info->ip.i;
7390                         if (IS_REX (pos [1])) {
7391                                 patch_pos = pos + 5;
7392                                 target_pos = code - pos - 9;
7393                         }
7394                         else {
7395                                 patch_pos = pos + 4;
7396                                 target_pos = code - pos - 8;
7397                         }
7398
7399                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7400 #ifdef __native_client_codegen__
7401                                 /* Hide 64-bit data in a         */
7402                                 /* "mov imm64, r11" instruction. */
7403                                 /* write it before the start of  */
7404                                 /* the data*/
7405                                 *(code-2) = 0x49; /* prefix      */
7406                                 *(code-1) = 0xbb; /* mov X, %r11 */
7407 #endif
7408                                 *(double*)code = *(double*)patch_info->data.target;
7409                                 code += sizeof (double);
7410                         } else {
7411 #ifdef __native_client_codegen__
7412                                 /* Hide 32-bit data in a        */
7413                                 /* "push imm32" instruction.    */
7414                                 *(code-1) = 0x68; /* push */
7415 #endif
7416                                 *(float*)code = *(float*)patch_info->data.target;
7417                                 code += sizeof (float);
7418                         }
7419
7420                         *(guint32*)(patch_pos) = target_pos;
7421
7422                         remove = TRUE;
7423                         break;
7424                 }
7425                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7426                         guint8 *pos;
7427
7428                         if (cfg->compile_aot)
7429                                 continue;
7430
7431                         /*loading is faster against aligned addresses.*/
7432                         code = (guint8*)ALIGN_TO (code, 8);
7433                         memset (orig_code, 0, code - orig_code);
7434
7435                         pos = cfg->native_code + patch_info->ip.i;
7436
7437                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7438                         if (IS_REX (pos [1]))
7439                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7440                         else
7441                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7442
7443                         *(gpointer*)code = (gpointer)patch_info->data.target;
7444                         code += sizeof (gpointer);
7445
7446                         remove = TRUE;
7447                         break;
7448                 }
7449                 default:
7450                         break;
7451                 }
7452
7453                 if (remove) {
7454                         if (patch_info == cfg->patch_info)
7455                                 cfg->patch_info = patch_info->next;
7456                         else {
7457                                 MonoJumpInfo *tmp;
7458
7459                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7460                                         ;
7461                                 tmp->next = patch_info->next;
7462                         }
7463                 }
7464                 g_assert (code < cfg->native_code + cfg->code_size);
7465         }
7466
7467         cfg->code_len = code - cfg->native_code;
7468
7469         g_assert (cfg->code_len < cfg->code_size);
7470
7471 }
7472
7473 #endif /* DISABLE_JIT */
7474
7475 void*
7476 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7477 {
7478         guchar *code = p;
7479         CallInfo *cinfo = NULL;
7480         MonoMethodSignature *sig;
7481         MonoInst *inst;
7482         int i, n, stack_area = 0;
7483
7484         /* Keep this in sync with mono_arch_get_argument_info */
7485
7486         if (enable_arguments) {
7487                 /* Allocate a new area on the stack and save arguments there */
7488                 sig = mono_method_signature (cfg->method);
7489
7490                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7491
7492                 n = sig->param_count + sig->hasthis;
7493
7494                 stack_area = ALIGN_TO (n * 8, 16);
7495
7496                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7497
7498                 for (i = 0; i < n; ++i) {
7499                         inst = cfg->args [i];
7500
7501                         if (inst->opcode == OP_REGVAR)
7502                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7503                         else {
7504                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7505                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7506                         }
7507                 }
7508         }
7509
7510         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7511         amd64_set_reg_template (code, AMD64_ARG_REG1);
7512         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7513         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7514
7515         if (enable_arguments)
7516                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7517
7518         return code;
7519 }
7520
7521 enum {
7522         SAVE_NONE,
7523         SAVE_STRUCT,
7524         SAVE_EAX,
7525         SAVE_EAX_EDX,
7526         SAVE_XMM
7527 };
7528
7529 void*
7530 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7531 {
7532         guchar *code = p;
7533         int save_mode = SAVE_NONE;
7534         MonoMethod *method = cfg->method;
7535         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
7536         int i;
7537
7538         switch (ret_type->type) {
7539         case MONO_TYPE_VOID:
7540                 /* special case string .ctor icall */
7541                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7542                         save_mode = SAVE_EAX;
7543                 else
7544                         save_mode = SAVE_NONE;
7545                 break;
7546         case MONO_TYPE_I8:
7547         case MONO_TYPE_U8:
7548                 save_mode = SAVE_EAX;
7549                 break;
7550         case MONO_TYPE_R4:
7551         case MONO_TYPE_R8:
7552                 save_mode = SAVE_XMM;
7553                 break;
7554         case MONO_TYPE_GENERICINST:
7555                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7556                         save_mode = SAVE_EAX;
7557                         break;
7558                 }
7559                 /* Fall through */
7560         case MONO_TYPE_VALUETYPE:
7561                 save_mode = SAVE_STRUCT;
7562                 break;
7563         default:
7564                 save_mode = SAVE_EAX;
7565                 break;
7566         }
7567
7568         /* Save the result and copy it into the proper argument register */
7569         switch (save_mode) {
7570         case SAVE_EAX:
7571                 amd64_push_reg (code, AMD64_RAX);
7572                 /* Align stack */
7573                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7574                 if (enable_arguments)
7575                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7576                 break;
7577         case SAVE_STRUCT:
7578                 /* FIXME: */
7579                 if (enable_arguments)
7580                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7581                 break;
7582         case SAVE_XMM:
7583                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7584                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7585                 /* Align stack */
7586                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7587                 /*
7588                  * The result is already in the proper argument register so no copying
7589                  * needed.
7590                  */
7591                 break;
7592         case SAVE_NONE:
7593                 break;
7594         default:
7595                 g_assert_not_reached ();
7596         }
7597
7598         /* Set %al since this is a varargs call */
7599         if (save_mode == SAVE_XMM)
7600                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7601         else
7602                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7603
7604         if (preserve_argument_registers) {
7605                 for (i = 0; i < PARAM_REGS; ++i)
7606                         amd64_push_reg (code, param_regs [i]);
7607         }
7608
7609         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7610         amd64_set_reg_template (code, AMD64_ARG_REG1);
7611         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7612
7613         if (preserve_argument_registers) {
7614                 for (i = PARAM_REGS - 1; i >= 0; --i)
7615                         amd64_pop_reg (code, param_regs [i]);
7616         }
7617
7618         /* Restore result */
7619         switch (save_mode) {
7620         case SAVE_EAX:
7621                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7622                 amd64_pop_reg (code, AMD64_RAX);
7623                 break;
7624         case SAVE_STRUCT:
7625                 /* FIXME: */
7626                 break;
7627         case SAVE_XMM:
7628                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7629                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7630                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7631                 break;
7632         case SAVE_NONE:
7633                 break;
7634         default:
7635                 g_assert_not_reached ();
7636         }
7637
7638         return code;
7639 }
7640
7641 void
7642 mono_arch_flush_icache (guint8 *code, gint size)
7643 {
7644         /* Not needed */
7645 }
7646
7647 void
7648 mono_arch_flush_register_windows (void)
7649 {
7650 }
7651
7652 gboolean
7653 mono_arch_is_inst_imm (gint64 imm)
7654 {
7655         return amd64_is_imm32 (imm);
7656 }
7657
7658 /*
7659  * Determine whenever the trap whose info is in SIGINFO is caused by
7660  * integer overflow.
7661  */
7662 gboolean
7663 mono_arch_is_int_overflow (void *sigctx, void *info)
7664 {
7665         MonoContext ctx;
7666         guint8* rip;
7667         int reg;
7668         gint64 value;
7669
7670         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7671
7672         rip = (guint8*)ctx.rip;
7673
7674         if (IS_REX (rip [0])) {
7675                 reg = amd64_rex_b (rip [0]);
7676                 rip ++;
7677         }
7678         else
7679                 reg = 0;
7680
7681         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7682                 /* idiv REG */
7683                 reg += x86_modrm_rm (rip [1]);
7684
7685                 switch (reg) {
7686                 case AMD64_RAX:
7687                         value = ctx.rax;
7688                         break;
7689                 case AMD64_RBX:
7690                         value = ctx.rbx;
7691                         break;
7692                 case AMD64_RCX:
7693                         value = ctx.rcx;
7694                         break;
7695                 case AMD64_RDX:
7696                         value = ctx.rdx;
7697                         break;
7698                 case AMD64_RBP:
7699                         value = ctx.rbp;
7700                         break;
7701                 case AMD64_RSP:
7702                         value = ctx.rsp;
7703                         break;
7704                 case AMD64_RSI:
7705                         value = ctx.rsi;
7706                         break;
7707                 case AMD64_RDI:
7708                         value = ctx.rdi;
7709                         break;
7710                 case AMD64_R12:
7711                         value = ctx.r12;
7712                         break;
7713                 case AMD64_R13:
7714                         value = ctx.r13;
7715                         break;
7716                 case AMD64_R14:
7717                         value = ctx.r14;
7718                         break;
7719                 case AMD64_R15:
7720                         value = ctx.r15;
7721                         break;
7722                 default:
7723                         g_assert_not_reached ();
7724                         reg = -1;
7725                 }
7726
7727                 if (value == -1)
7728                         return TRUE;
7729         }
7730
7731         return FALSE;
7732 }
7733
7734 guint32
7735 mono_arch_get_patch_offset (guint8 *code)
7736 {
7737         return 3;
7738 }
7739
7740 /**
7741  * mono_breakpoint_clean_code:
7742  *
7743  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7744  * breakpoints in the original code, they are removed in the copy.
7745  *
7746  * Returns TRUE if no sw breakpoint was present.
7747  */
7748 gboolean
7749 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7750 {
7751         int i;
7752         gboolean can_write = TRUE;
7753         /*
7754          * If method_start is non-NULL we need to perform bound checks, since we access memory
7755          * at code - offset we could go before the start of the method and end up in a different
7756          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7757          * instead.
7758          */
7759         if (!method_start || code - offset >= method_start) {
7760                 memcpy (buf, code - offset, size);
7761         } else {
7762                 int diff = code - method_start;
7763                 memset (buf, 0, size);
7764                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7765         }
7766         code -= offset;
7767         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7768                 int idx = mono_breakpoint_info_index [i];
7769                 guint8 *ptr;
7770                 if (idx < 1)
7771                         continue;
7772                 ptr = mono_breakpoint_info [idx].address;
7773                 if (ptr >= code && ptr < code + size) {
7774                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7775                         can_write = FALSE;
7776                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7777                         buf [ptr - code] = saved_byte;
7778                 }
7779         }
7780         return can_write;
7781 }
7782
7783 #if defined(__native_client_codegen__)
7784 /* For membase calls, we want the base register. for Native Client,  */
7785 /* all indirect calls have the following sequence with the given sizes: */
7786 /* mov %eXX,%eXX                                [2-3]   */
7787 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7788 /* and $0xffffffffffffffe0,%r11d                [4]     */
7789 /* add %r15,%r11                                [3]     */
7790 /* callq *%r11                                  [3]     */
7791
7792
7793 /* Determine if code points to a NaCl call-through-register sequence, */
7794 /* (i.e., the last 3 instructions listed above) */
7795 int
7796 is_nacl_call_reg_sequence(guint8* code)
7797 {
7798         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7799                                "\x4d\x03\xdf"     /* add */
7800                                "\x41\xff\xd3";   /* call */
7801         return memcmp(code, sequence, 10) == 0;
7802 }
7803
7804 /* Determine if code points to the first opcode of the mov membase component */
7805 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7806 /* (there could be a REX prefix before the opcode but it is ignored) */
7807 static int
7808 is_nacl_indirect_call_membase_sequence(guint8* code)
7809 {
7810                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7811         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7812                /* and that src reg = dest reg */
7813                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7814                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7815                IS_REX(code[2]) &&
7816                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7817                /* and has dst of r11 and base of r15 */
7818                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7819                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7820 }
7821 #endif /* __native_client_codegen__ */
7822
7823 int
7824 mono_arch_get_this_arg_reg (guint8 *code)
7825 {
7826         return AMD64_ARG_REG1;
7827 }
7828
7829 gpointer
7830 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7831 {
7832         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7833 }
7834
7835 #define MAX_ARCH_DELEGATE_PARAMS 10
7836
7837 static gpointer
7838 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7839 {
7840         guint8 *code, *start;
7841         int i;
7842
7843         if (has_target) {
7844                 start = code = mono_global_codeman_reserve (64);
7845
7846                 /* Replace the this argument with the target */
7847                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7848                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7849                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7850
7851                 g_assert ((code - start) < 64);
7852         } else {
7853                 start = code = mono_global_codeman_reserve (64);
7854
7855                 if (param_count == 0) {
7856                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7857                 } else {
7858                         /* We have to shift the arguments left */
7859                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7860                         for (i = 0; i < param_count; ++i) {
7861 #ifdef HOST_WIN32
7862                                 if (i < 3)
7863                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7864                                 else
7865                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7866 #else
7867                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7868 #endif
7869                         }
7870
7871                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7872                 }
7873                 g_assert ((code - start) < 64);
7874         }
7875
7876         nacl_global_codeman_validate(&start, 64, &code);
7877
7878         mono_debug_add_delegate_trampoline (start, code - start);
7879
7880         if (code_len)
7881                 *code_len = code - start;
7882
7883
7884         if (mono_jit_map_is_enabled ()) {
7885                 char *buff;
7886                 if (has_target)
7887                         buff = (char*)"delegate_invoke_has_target";
7888                 else
7889                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7890                 mono_emit_jit_tramp (start, code - start, buff);
7891                 if (!has_target)
7892                         g_free (buff);
7893         }
7894
7895         return start;
7896 }
7897
7898 /*
7899  * mono_arch_get_delegate_invoke_impls:
7900  *
7901  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7902  * trampolines.
7903  */
7904 GSList*
7905 mono_arch_get_delegate_invoke_impls (void)
7906 {
7907         GSList *res = NULL;
7908         guint8 *code;
7909         guint32 code_len;
7910         int i;
7911
7912         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7913         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7914
7915         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7916                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7917                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7918         }
7919
7920         return res;
7921 }
7922
7923 gpointer
7924 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7925 {
7926         guint8 *code, *start;
7927         int i;
7928
7929         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7930                 return NULL;
7931
7932         /* FIXME: Support more cases */
7933         if (MONO_TYPE_ISSTRUCT (sig->ret))
7934                 return NULL;
7935
7936         if (has_target) {
7937                 static guint8* cached = NULL;
7938
7939                 if (cached)
7940                         return cached;
7941
7942                 if (mono_aot_only)
7943                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7944                 else
7945                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7946
7947                 mono_memory_barrier ();
7948
7949                 cached = start;
7950         } else {
7951                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7952                 for (i = 0; i < sig->param_count; ++i)
7953                         if (!mono_is_regsize_var (sig->params [i]))
7954                                 return NULL;
7955                 if (sig->param_count > 4)
7956                         return NULL;
7957
7958                 code = cache [sig->param_count];
7959                 if (code)
7960                         return code;
7961
7962                 if (mono_aot_only) {
7963                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7964                         start = mono_aot_get_trampoline (name);
7965                         g_free (name);
7966                 } else {
7967                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7968                 }
7969
7970                 mono_memory_barrier ();
7971
7972                 cache [sig->param_count] = start;
7973         }
7974
7975         return start;
7976 }
7977 void
7978 mono_arch_finish_init (void)
7979 {
7980 #ifdef HOST_WIN32
7981         /*
7982          * We need to init this multiple times, since when we are first called, the key might not
7983          * be initialized yet.
7984          */
7985         appdomain_tls_offset = mono_domain_get_tls_key ();
7986         lmf_tls_offset = mono_get_jit_tls_key ();
7987         lmf_addr_tls_offset = mono_get_jit_tls_key ();
7988
7989         /* Only 64 tls entries can be accessed using inline code */
7990         if (appdomain_tls_offset >= 64)
7991                 appdomain_tls_offset = -1;
7992         if (lmf_tls_offset >= 64)
7993                 lmf_tls_offset = -1;
7994         if (lmf_addr_tls_offset >= 64)
7995                 lmf_addr_tls_offset = -1;
7996 #else
7997 #ifdef MONO_XEN_OPT
7998         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7999 #endif
8000         appdomain_tls_offset = mono_domain_get_tls_offset ();
8001         lmf_tls_offset = mono_get_lmf_tls_offset ();
8002         lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
8003 #endif
8004 }
8005
8006 void
8007 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8008 {
8009 }
8010
8011 #ifdef MONO_ARCH_HAVE_IMT
8012
8013 #if defined(__default_codegen__)
8014 #define CMP_SIZE (6 + 1)
8015 #define CMP_REG_REG_SIZE (4 + 1)
8016 #define BR_SMALL_SIZE 2
8017 #define BR_LARGE_SIZE 6
8018 #define MOV_REG_IMM_SIZE 10
8019 #define MOV_REG_IMM_32BIT_SIZE 6
8020 #define JUMP_REG_SIZE (2 + 1)
8021 #elif defined(__native_client_codegen__)
8022 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8023 #define CMP_SIZE ((6 + 1) * 2 - 1)
8024 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8025 #define BR_SMALL_SIZE (2 * 2 - 1)
8026 #define BR_LARGE_SIZE (6 * 2 - 1)
8027 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8028 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8029 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8030 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8031 /* Jump membase's size is large and unpredictable    */
8032 /* in native client, just pad it out a whole bundle. */
8033 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8034 #endif
8035
8036 static int
8037 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8038 {
8039         int i, distance = 0;
8040         for (i = start; i < target; ++i)
8041                 distance += imt_entries [i]->chunk_size;
8042         return distance;
8043 }
8044
8045 /*
8046  * LOCKING: called with the domain lock held
8047  */
8048 gpointer
8049 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8050         gpointer fail_tramp)
8051 {
8052         int i;
8053         int size = 0;
8054         guint8 *code, *start;
8055         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8056
8057         for (i = 0; i < count; ++i) {
8058                 MonoIMTCheckItem *item = imt_entries [i];
8059                 if (item->is_equals) {
8060                         if (item->check_target_idx) {
8061                                 if (!item->compare_done) {
8062                                         if (amd64_is_imm32 (item->key))
8063                                                 item->chunk_size += CMP_SIZE;
8064                                         else
8065                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8066                                 }
8067                                 if (item->has_target_code) {
8068                                         item->chunk_size += MOV_REG_IMM_SIZE;
8069                                 } else {
8070                                         if (vtable_is_32bit)
8071                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8072                                         else
8073                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8074 #ifdef __native_client_codegen__
8075                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8076 #endif
8077                                 }
8078                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8079                         } else {
8080                                 if (fail_tramp) {
8081                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8082                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8083                                 } else {
8084                                         if (vtable_is_32bit)
8085                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8086                                         else
8087                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8088                                         item->chunk_size += JUMP_REG_SIZE;
8089                                         /* with assert below:
8090                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8091                                          */
8092 #ifdef __native_client_codegen__
8093                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8094 #endif
8095                                 }
8096                         }
8097                 } else {
8098                         if (amd64_is_imm32 (item->key))
8099                                 item->chunk_size += CMP_SIZE;
8100                         else
8101                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8102                         item->chunk_size += BR_LARGE_SIZE;
8103                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8104                 }
8105                 size += item->chunk_size;
8106         }
8107 #if defined(__native_client__) && defined(__native_client_codegen__)
8108         /* In Native Client, we don't re-use thunks, allocate from the */
8109         /* normal code manager paths. */
8110         code = mono_domain_code_reserve (domain, size);
8111 #else
8112         if (fail_tramp)
8113                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8114         else
8115                 code = mono_domain_code_reserve (domain, size);
8116 #endif
8117         start = code;
8118         for (i = 0; i < count; ++i) {
8119                 MonoIMTCheckItem *item = imt_entries [i];
8120                 item->code_target = code;
8121                 if (item->is_equals) {
8122                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8123
8124                         if (item->check_target_idx || fail_case) {
8125                                 if (!item->compare_done || fail_case) {
8126                                         if (amd64_is_imm32 (item->key))
8127                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
8128                                         else {
8129                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8130                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8131                                         }
8132                                 }
8133                                 item->jmp_code = code;
8134                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8135                                 if (item->has_target_code) {
8136                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8137                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8138                                 } else {
8139                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8140                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8141                                 }
8142
8143                                 if (fail_case) {
8144                                         amd64_patch (item->jmp_code, code);
8145                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8146                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8147                                         item->jmp_code = NULL;
8148                                 }
8149                         } else {
8150                                 /* enable the commented code to assert on wrong method */
8151 #if 0
8152                                 if (amd64_is_imm32 (item->key))
8153                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
8154                                 else {
8155                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8156                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8157                                 }
8158                                 item->jmp_code = code;
8159                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8160                                 /* See the comment below about R10 */
8161                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8162                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8163                                 amd64_patch (item->jmp_code, code);
8164                                 amd64_breakpoint (code);
8165                                 item->jmp_code = NULL;
8166 #else
8167                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8168                                    needs to be preserved.  R10 needs
8169                                    to be preserved for calls which
8170                                    require a runtime generic context,
8171                                    but interface calls don't. */
8172                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8173                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8174 #endif
8175                         }
8176                 } else {
8177                         if (amd64_is_imm32 (item->key))
8178                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
8179                         else {
8180                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8181                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8182                         }
8183                         item->jmp_code = code;
8184                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8185                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8186                         else
8187                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8188                 }
8189                 g_assert (code - item->code_target <= item->chunk_size);
8190         }
8191         /* patch the branches to get to the target items */
8192         for (i = 0; i < count; ++i) {
8193                 MonoIMTCheckItem *item = imt_entries [i];
8194                 if (item->jmp_code) {
8195                         if (item->check_target_idx) {
8196                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8197                         }
8198                 }
8199         }
8200
8201         if (!fail_tramp)
8202                 mono_stats.imt_thunks_size += code - start;
8203         g_assert (code - start <= size);
8204
8205         nacl_domain_code_validate(domain, &start, size, &code);
8206
8207         return start;
8208 }
8209
8210 MonoMethod*
8211 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8212 {
8213         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8214 }
8215 #endif
8216
8217 MonoVTable*
8218 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8219 {
8220         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8221 }
8222
8223 GSList*
8224 mono_arch_get_cie_program (void)
8225 {
8226         GSList *l = NULL;
8227
8228         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8229         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8230
8231         return l;
8232 }
8233
8234 MonoInst*
8235 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8236 {
8237         MonoInst *ins = NULL;
8238         int opcode = 0;
8239
8240         if (cmethod->klass == mono_defaults.math_class) {
8241                 if (strcmp (cmethod->name, "Sin") == 0) {
8242                         opcode = OP_SIN;
8243                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8244                         opcode = OP_COS;
8245                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8246                         opcode = OP_SQRT;
8247                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8248                         opcode = OP_ABS;
8249                 }
8250
8251                 if (opcode) {
8252                         MONO_INST_NEW (cfg, ins, opcode);
8253                         ins->type = STACK_R8;
8254                         ins->dreg = mono_alloc_freg (cfg);
8255                         ins->sreg1 = args [0]->dreg;
8256                         MONO_ADD_INS (cfg->cbb, ins);
8257                 }
8258
8259                 opcode = 0;
8260                 if (cfg->opt & MONO_OPT_CMOV) {
8261                         if (strcmp (cmethod->name, "Min") == 0) {
8262                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8263                                         opcode = OP_IMIN;
8264                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8265                                         opcode = OP_IMIN_UN;
8266                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8267                                         opcode = OP_LMIN;
8268                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8269                                         opcode = OP_LMIN_UN;
8270                         } else if (strcmp (cmethod->name, "Max") == 0) {
8271                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8272                                         opcode = OP_IMAX;
8273                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8274                                         opcode = OP_IMAX_UN;
8275                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8276                                         opcode = OP_LMAX;
8277                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8278                                         opcode = OP_LMAX_UN;
8279                         }
8280                 }
8281
8282                 if (opcode) {
8283                         MONO_INST_NEW (cfg, ins, opcode);
8284                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8285                         ins->dreg = mono_alloc_ireg (cfg);
8286                         ins->sreg1 = args [0]->dreg;
8287                         ins->sreg2 = args [1]->dreg;
8288                         MONO_ADD_INS (cfg->cbb, ins);
8289                 }
8290
8291 #if 0
8292                 /* OP_FREM is not IEEE compatible */
8293                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8294                         MONO_INST_NEW (cfg, ins, OP_FREM);
8295                         ins->inst_i0 = args [0];
8296                         ins->inst_i1 = args [1];
8297                 }
8298 #endif
8299         }
8300
8301         /*
8302          * Can't implement CompareExchange methods this way since they have
8303          * three arguments.
8304          */
8305
8306         return ins;
8307 }
8308
8309 gboolean
8310 mono_arch_print_tree (MonoInst *tree, int arity)
8311 {
8312         return 0;
8313 }
8314
8315 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
8316 {
8317         MonoInst* ins;
8318
8319         if (appdomain_tls_offset == -1)
8320                 return NULL;
8321
8322         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
8323         ins->inst_offset = appdomain_tls_offset;
8324         return ins;
8325 }
8326
8327 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8328
8329 mgreg_t
8330 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8331 {
8332         switch (reg) {
8333         case AMD64_RCX: return ctx->rcx;
8334         case AMD64_RDX: return ctx->rdx;
8335         case AMD64_RBX: return ctx->rbx;
8336         case AMD64_RBP: return ctx->rbp;
8337         case AMD64_RSP: return ctx->rsp;
8338         default:
8339                 if (reg < 8)
8340                         return _CTX_REG (ctx, rax, reg);
8341                 else if (reg >= 12)
8342                         return _CTX_REG (ctx, r12, reg - 12);
8343                 else
8344                         g_assert_not_reached ();
8345         }
8346 }
8347
8348 void
8349 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8350 {
8351         switch (reg) {
8352         case AMD64_RCX:
8353                 ctx->rcx = val;
8354                 break;
8355         case AMD64_RDX:
8356                 ctx->rdx = val;
8357                 break;
8358         case AMD64_RBX:
8359                 ctx->rbx = val;
8360                 break;
8361         case AMD64_RBP:
8362                 ctx->rbp = val;
8363                 break;
8364         case AMD64_RSP:
8365                 ctx->rsp = val;
8366                 break;
8367         default:
8368                 if (reg < 8)
8369                         _CTX_REG (ctx, rax, reg) = val;
8370                 else if (reg >= 12)
8371                         _CTX_REG (ctx, r12, reg - 12) = val;
8372                 else
8373                         g_assert_not_reached ();
8374         }
8375 }
8376
8377 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8378 gpointer
8379 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8380 {
8381         int offset;
8382         gpointer *sp, old_value;
8383         char *bp;
8384         const unsigned char *handler;
8385
8386         /*Decode the first instruction to figure out where did we store the spvar*/
8387         /*Our jit MUST generate the following:
8388          mov    %rsp, ?(%rbp)
8389
8390          Which is encoded as: REX.W 0x89 mod_rm
8391          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8392                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8393                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8394
8395         FIXME can we generate frameless methods on this case?
8396
8397         */
8398         handler = clause->handler_start;
8399
8400         /*REX.W*/
8401         if (*handler != 0x48)
8402                 return NULL;
8403         ++handler;
8404
8405         /*mov r, r/m */
8406         if (*handler != 0x89)
8407                 return NULL;
8408         ++handler;
8409
8410         if (*handler == 0x65)
8411                 offset = *(signed char*)(handler + 1);
8412         else if (*handler == 0xA5)
8413                 offset = *(int*)(handler + 1);
8414         else
8415                 return NULL;
8416
8417         /*Load the spvar*/
8418         bp = MONO_CONTEXT_GET_BP (ctx);
8419         sp = *(gpointer*)(bp + offset);
8420
8421         old_value = *sp;
8422         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8423                 return old_value;
8424
8425         *sp = new_value;
8426
8427         return old_value;
8428 }
8429
8430 /*
8431  * mono_arch_emit_load_aotconst:
8432  *
8433  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8434  * TARGET from the mscorlib GOT in full-aot code.
8435  * On AMD64, the result is placed into R11.
8436  */
8437 guint8*
8438 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8439 {
8440         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8441         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8442
8443         return code;
8444 }
8445
8446 /*
8447  * mono_arch_get_trampolines:
8448  *
8449  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8450  * for AOT.
8451  */
8452 GSList *
8453 mono_arch_get_trampolines (gboolean aot)
8454 {
8455         return mono_amd64_get_exception_trampolines (aot);
8456 }
8457
8458 /* Soft Debug support */
8459 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8460
8461 /*
8462  * mono_arch_set_breakpoint:
8463  *
8464  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8465  * The location should contain code emitted by OP_SEQ_POINT.
8466  */
8467 void
8468 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8469 {
8470         guint8 *code = ip;
8471         guint8 *orig_code = code;
8472
8473         if (ji->from_aot) {
8474                 guint32 native_offset = ip - (guint8*)ji->code_start;
8475                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8476
8477                 g_assert (info->bp_addrs [native_offset] == 0);
8478                 info->bp_addrs [native_offset] = bp_trigger_page;
8479         } else {
8480                 /*
8481                  * In production, we will use int3 (has to fix the size in the md
8482                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8483                  * instead.
8484                  */
8485                 g_assert (code [0] == 0x90);
8486                 if (breakpoint_size == 8) {
8487                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8488                 } else {
8489                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8490                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8491                 }
8492
8493                 g_assert (code - orig_code == breakpoint_size);
8494         }
8495 }
8496
8497 /*
8498  * mono_arch_clear_breakpoint:
8499  *
8500  *   Clear the breakpoint at IP.
8501  */
8502 void
8503 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8504 {
8505         guint8 *code = ip;
8506         int i;
8507
8508         if (ji->from_aot) {
8509                 guint32 native_offset = ip - (guint8*)ji->code_start;
8510                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8511
8512                 g_assert (info->bp_addrs [native_offset] == 0);
8513                 info->bp_addrs [native_offset] = info;
8514         } else {
8515                 for (i = 0; i < breakpoint_size; ++i)
8516                         x86_nop (code);
8517         }
8518 }
8519
8520 gboolean
8521 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8522 {
8523 #ifdef HOST_WIN32
8524         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8525         return FALSE;
8526 #else
8527         siginfo_t* sinfo = (siginfo_t*) info;
8528         /* Sometimes the address is off by 4 */
8529         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8530                 return TRUE;
8531         else
8532                 return FALSE;
8533 #endif
8534 }
8535
8536 /*
8537  * mono_arch_skip_breakpoint:
8538  *
8539  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8540  * we resume, the instruction is not executed again.
8541  */
8542 void
8543 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8544 {
8545         if (ji->from_aot) {
8546                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8547                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8548         } else {
8549                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8550         }
8551 }
8552
8553 /*
8554  * mono_arch_start_single_stepping:
8555  *
8556  *   Start single stepping.
8557  */
8558 void
8559 mono_arch_start_single_stepping (void)
8560 {
8561         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8562 }
8563
8564 /*
8565  * mono_arch_stop_single_stepping:
8566  *
8567  *   Stop single stepping.
8568  */
8569 void
8570 mono_arch_stop_single_stepping (void)
8571 {
8572         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8573 }
8574
8575 /*
8576  * mono_arch_is_single_step_event:
8577  *
8578  *   Return whenever the machine state in SIGCTX corresponds to a single
8579  * step event.
8580  */
8581 gboolean
8582 mono_arch_is_single_step_event (void *info, void *sigctx)
8583 {
8584 #ifdef HOST_WIN32
8585         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8586         return FALSE;
8587 #else
8588         siginfo_t* sinfo = (siginfo_t*) info;
8589         /* Sometimes the address is off by 4 */
8590         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8591                 return TRUE;
8592         else
8593                 return FALSE;
8594 #endif
8595 }
8596
8597 /*
8598  * mono_arch_skip_single_step:
8599  *
8600  *   Modify CTX so the ip is placed after the single step trigger instruction,
8601  * we resume, the instruction is not executed again.
8602  */
8603 void
8604 mono_arch_skip_single_step (MonoContext *ctx)
8605 {
8606         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8607 }
8608
8609 /*
8610  * mono_arch_create_seq_point_info:
8611  *
8612  *   Return a pointer to a data structure which is used by the sequence
8613  * point implementation in AOTed code.
8614  */
8615 gpointer
8616 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8617 {
8618         SeqPointInfo *info;
8619         MonoJitInfo *ji;
8620         int i;
8621
8622         // FIXME: Add a free function
8623
8624         mono_domain_lock (domain);
8625         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8626                                                                 code);
8627         mono_domain_unlock (domain);
8628
8629         if (!info) {
8630                 ji = mono_jit_info_table_find (domain, (char*)code);
8631                 g_assert (ji);
8632
8633                 // FIXME: Optimize the size
8634                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8635
8636                 info->ss_trigger_page = ss_trigger_page;
8637                 info->bp_trigger_page = bp_trigger_page;
8638                 /* Initialize to a valid address */
8639                 for (i = 0; i < ji->code_size; ++i)
8640                         info->bp_addrs [i] = info;
8641
8642                 mono_domain_lock (domain);
8643                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8644                                                          code, info);
8645                 mono_domain_unlock (domain);
8646         }
8647
8648         return info;
8649 }
8650
8651 #endif