mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internals.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 /* The single step trampoline */
  69 static gpointer ss_trampoline;
  70
  71 /* The breakpoint trampoline */
  72 static gpointer bp_trampoline;
  73
  74 /* Offset between fp and the first argument in the callee */
  75 #define ARGS_OFFSET 16
  76 #define GP_SCRATCH_REG AMD64_R11
  77
  78 /*
  79  * AMD64 register usage:
  80  * - callee saved registers are used for global register allocation
  81  * - %r11 is used for materializing 64 bit constants in opcodes
  82  * - the rest is used for local allocation
  83  */
  84
  85 /*
  86  * Floating point comparison results:
  87  *                  ZF PF CF
  88  * A > B            0  0  0
  89  * A < B            0  0  1
  90  * A = B            1  0  0
  91  * A > B            0  0  0
  92  * UNORDERED        1  1  1
  93  */
  94
  95 const char*
  96 mono_arch_regname (int reg)
  97 {
  98         switch (reg) {
  99         case AMD64_RAX: return "%rax";
 100         case AMD64_RBX: return "%rbx";
 101         case AMD64_RCX: return "%rcx";
 102         case AMD64_RDX: return "%rdx";
 103         case AMD64_RSP: return "%rsp";
 104         case AMD64_RBP: return "%rbp";
 105         case AMD64_RDI: return "%rdi";
 106         case AMD64_RSI: return "%rsi";
 107         case AMD64_R8: return "%r8";
 108         case AMD64_R9: return "%r9";
 109         case AMD64_R10: return "%r10";
 110         case AMD64_R11: return "%r11";
 111         case AMD64_R12: return "%r12";
 112         case AMD64_R13: return "%r13";
 113         case AMD64_R14: return "%r14";
 114         case AMD64_R15: return "%r15";
 115         }
 116         return "unknown";
 117 }
 118
 119 static const char * packed_xmmregs [] = {
 120         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 121         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 122 };
 123
 124 static const char * single_xmmregs [] = {
 125         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 126         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 127 };
 128
 129 const char*
 130 mono_arch_fregname (int reg)
 131 {
 132         if (reg < AMD64_XMM_NREG)
 133                 return single_xmmregs [reg];
 134         else
 135                 return "unknown";
 136 }
 137
 138 const char *
 139 mono_arch_xregname (int reg)
 140 {
 141         if (reg < AMD64_XMM_NREG)
 142                 return packed_xmmregs [reg];
 143         else
 144                 return "unknown";
 145 }
 146
 147 static gboolean
 148 debug_omit_fp (void)
 149 {
 150 #if 0
 151         return mono_debug_count ();
 152 #else
 153         return TRUE;
 154 #endif
 155 }
 156
 157 static inline gboolean
 158 amd64_is_near_call (guint8 *code)
 159 {
 160         /* Skip REX */
 161         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 162                 code += 1;
 163
 164         return code [0] == 0xe8;
 165 }
 166
 167 static inline gboolean
 168 amd64_use_imm32 (gint64 val)
 169 {
 170         if (mini_get_debug_options()->single_imm_size)
 171                 return FALSE;
 172
 173         return amd64_is_imm32 (val);
 174 }
 175
 176 #ifdef __native_client_codegen__
 177
 178 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 179 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 180 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 181 /* We only want to force bundle alignment for the top level instruction,    */
 182 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 183 static MonoNativeTlsKey nacl_instruction_depth;
 184
 185 static MonoNativeTlsKey nacl_rex_tag;
 186 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 187
 188 void
 189 amd64_nacl_clear_legacy_prefix_tag ()
 190 {
 191         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 192 }
 193
 194 void
 195 amd64_nacl_tag_legacy_prefix (guint8* code)
 196 {
 197         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 198                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 199 }
 200
 201 void
 202 amd64_nacl_tag_rex (guint8* code)
 203 {
 204         mono_native_tls_set_value (nacl_rex_tag, code);
 205 }
 206
 207 guint8*
 208 amd64_nacl_get_legacy_prefix_tag ()
 209 {
 210         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 211 }
 212
 213 guint8*
 214 amd64_nacl_get_rex_tag ()
 215 {
 216         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 217 }
 218
 219 /* Increment the instruction "depth" described above */
 220 void
 221 amd64_nacl_instruction_pre ()
 222 {
 223         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 224         depth++;
 225         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 226 }
 227
 228 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 229 /* alignment if depth == 0 (top level instruction)                          */
 230 /* IN: start, end    pointers to instruction beginning and end              */
 231 /* OUT: start, end   pointers to beginning and end after possible alignment */
 232 /* GLOBALS: nacl_instruction_depth     defined above                        */
 233 void
 234 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 235 {
 236         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 237         depth--;
 238         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 239
 240         g_assert ( depth >= 0 );
 241         if (depth == 0) {
 242                 uintptr_t space_in_block;
 243                 uintptr_t instlen;
 244                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 245                 /* if legacy prefix is present, and if it was emitted before */
 246                 /* the start of the instruction sequence, adjust the start   */
 247                 if (prefix != NULL && prefix < *start) {
 248                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 249                         *start = prefix;
 250                 }
 251                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 252                 instlen = (uintptr_t)(*end - *start);
 253                 /* Only check for instructions which are less than        */
 254                 /* kNaClAlignment. The only instructions that should ever */
 255                 /* be that long are call sequences, which are already     */
 256                 /* padded out to align the return to the next bundle.     */
 257                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 258                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 259                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 260                         const size_t length = (size_t)((*end)-(*start));
 261                         g_assert (length < MAX_NACL_INST_LENGTH);
 262
 263                         memcpy (copy_of_instruction, *start, length);
 264                         *start = mono_arch_nacl_pad (*start, space_in_block);
 265                         memcpy (*start, copy_of_instruction, length);
 266                         *end = *start + length;
 267                 }
 268                 amd64_nacl_clear_legacy_prefix_tag ();
 269                 amd64_nacl_tag_rex (NULL);
 270         }
 271 }
 272
 273 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 274 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 275 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 276 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 277 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 278 /* IN:      code                                                            */
 279 /*             pointer to current instruction stream (in the                */
 280 /*             middle of an instruction, after opcode is emitted)           */
 281 /*          basereg/offset/dreg                                             */
 282 /*             operands of normal membase address                           */
 283 /* OUT:     code                                                            */
 284 /*             pointer to the end of the membase/memindex emit              */
 285 /* GLOBALS: nacl_rex_tag                                                    */
 286 /*             position in instruction stream that rex prefix was emitted   */
 287 /*          nacl_legacy_prefix_tag                                          */
 288 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 289 void
 290 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 291 {
 292         gint8 true_basereg = basereg;
 293
 294         /* Cache these values, they might change  */
 295         /* as new instructions are emitted below. */
 296         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 297         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 298
 299         /* 'basereg' is given masked to 0x7 at this point, so check */
 300         /* the rex prefix to see if this is an extended register.   */
 301         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 302                 true_basereg |= 0x8;
 303         }
 304
 305 #define X86_LEA_OPCODE (0x8D)
 306
 307         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 308                 guint8* old_instruction_start;
 309
 310                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 311                 /* 32-bits of the old base register (new index register)     */
 312                 guint8 buf[32];
 313                 guint8* buf_ptr = buf;
 314                 size_t insert_len;
 315
 316                 g_assert (rex_tag != NULL);
 317
 318                 if (IS_REX(*rex_tag)) {
 319                         /* The old rex.B should be the new rex.X */
 320                         if (*rex_tag & AMD64_REX_B) {
 321                                 *rex_tag |= AMD64_REX_X;
 322                         }
 323                         /* Since our new base is %r15 set rex.B */
 324                         *rex_tag |= AMD64_REX_B;
 325                 } else {
 326                         /* Shift the instruction by one byte  */
 327                         /* so we can insert a rex prefix      */
 328                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 329                         *code += 1;
 330                         /* New rex prefix only needs rex.B for %r15 base */
 331                         *rex_tag = AMD64_REX(AMD64_REX_B);
 332                 }
 333
 334                 if (legacy_prefix_tag) {
 335                         old_instruction_start = legacy_prefix_tag;
 336                 } else {
 337                         old_instruction_start = rex_tag;
 338                 }
 339
 340                 /* Clears the upper 32-bits of the previous base register */
 341                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 342                 insert_len = buf_ptr - buf;
 343
 344                 /* Move the old instruction forward to make */
 345                 /* room for 'mov' stored in 'buf_ptr'       */
 346                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 347                 *code += insert_len;
 348                 memcpy (old_instruction_start, buf, insert_len);
 349
 350                 /* Sandboxed replacement for the normal membase_emit */
 351                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 352
 353         } else {
 354                 /* Normal default behavior, emit membase memory location */
 355                 x86_membase_emit_body (*code, dreg, basereg, offset);
 356         }
 357 }
 358
 359
 360 static inline unsigned char*
 361 amd64_skip_nops (unsigned char* code)
 362 {
 363         guint8 in_nop;
 364         do {
 365                 in_nop = 0;
 366                 if (   code[0] == 0x90) {
 367                         in_nop = 1;
 368                         code += 1;
 369                 }
 370                 if (   code[0] == 0x66 && code[1] == 0x90) {
 371                         in_nop = 1;
 372                         code += 2;
 373                 }
 374                 if (code[0] == 0x0f && code[1] == 0x1f
 375                  && code[2] == 0x00) {
 376                         in_nop = 1;
 377                         code += 3;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x40 && code[3] == 0x00) {
 381                         in_nop = 1;
 382                         code += 4;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x44 && code[3] == 0x00
 386                  && code[4] == 0x00) {
 387                         in_nop = 1;
 388                         code += 5;
 389                 }
 390                 if (code[0] == 0x66 && code[1] == 0x0f
 391                  && code[2] == 0x1f && code[3] == 0x44
 392                  && code[4] == 0x00 && code[5] == 0x00) {
 393                         in_nop = 1;
 394                         code += 6;
 395                 }
 396                 if (code[0] == 0x0f && code[1] == 0x1f
 397                  && code[2] == 0x80 && code[3] == 0x00
 398                  && code[4] == 0x00 && code[5] == 0x00
 399                  && code[6] == 0x00) {
 400                         in_nop = 1;
 401                         code += 7;
 402                 }
 403                 if (code[0] == 0x0f && code[1] == 0x1f
 404                  && code[2] == 0x84 && code[3] == 0x00
 405                  && code[4] == 0x00 && code[5] == 0x00
 406                  && code[6] == 0x00 && code[7] == 0x00) {
 407                         in_nop = 1;
 408                         code += 8;
 409                 }
 410         } while ( in_nop );
 411         return code;
 412 }
 413
 414 guint8*
 415 mono_arch_nacl_skip_nops (guint8* code)
 416 {
 417   return amd64_skip_nops(code);
 418 }
 419
 420 #endif /*__native_client_codegen__*/
 421
 422 static void
 423 amd64_patch (unsigned char* code, gpointer target)
 424 {
 425         guint8 rex = 0;
 426
 427 #ifdef __native_client_codegen__
 428         code = amd64_skip_nops (code);
 429 #endif
 430 #if defined(__native_client_codegen__) && defined(__native_client__)
 431         if (nacl_is_code_address (code)) {
 432                 /* For tail calls, code is patched after being installed */
 433                 /* but not through the normal "patch callsite" method.   */
 434                 unsigned char buf[kNaClAlignment];
 435                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 436                 int ret;
 437                 memcpy (buf, aligned_code, kNaClAlignment);
 438                 /* Patch a temp buffer of bundle size, */
 439                 /* then install to actual location.    */
 440                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 441                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 442                 g_assert (ret == 0);
 443                 return;
 444         }
 445         target = nacl_modify_patch_target (target);
 446 #endif
 447
 448         /* Skip REX */
 449         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 450                 rex = code [0];
 451                 code += 1;
 452         }
 453
 454         if ((code [0] & 0xf8) == 0xb8) {
 455                 /* amd64_set_reg_template */
 456                 *(guint64*)(code + 1) = (guint64)target;
 457         }
 458         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 459                 /* mov 0(%rip), %dreg */
 460                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 461         }
 462         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 463                 /* call *<OFFSET>(%rip) */
 464                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 465         }
 466         else if (code [0] == 0xe8) {
 467                 /* call <DISP> */
 468                 gint64 disp = (guint8*)target - (guint8*)code;
 469                 g_assert (amd64_is_imm32 (disp));
 470                 x86_patch (code, (unsigned char*)target);
 471         }
 472         else
 473                 x86_patch (code, (unsigned char*)target);
 474 }
 475
 476 void
 477 mono_amd64_patch (unsigned char* code, gpointer target)
 478 {
 479         amd64_patch (code, target);
 480 }
 481
 482 typedef enum {
 483         ArgInIReg,
 484         ArgInFloatSSEReg,
 485         ArgInDoubleSSEReg,
 486         ArgOnStack,
 487         ArgValuetypeInReg,
 488         ArgValuetypeAddrInIReg,
 489         /* gsharedvt argument passed by addr */
 490         ArgGSharedVtInReg,
 491         ArgGSharedVtOnStack,
 492         ArgNone /* only in pair_storage */
 493 } ArgStorage;
 494
 495 typedef struct {
 496         gint16 offset;
 497         gint8  reg;
 498         ArgStorage storage;
 499
 500         /* Only if storage == ArgValuetypeInReg */
 501         ArgStorage pair_storage [2];
 502         gint8 pair_regs [2];
 503         /* The size of each pair */
 504         int pair_size [2];
 505         int nregs;
 506 } ArgInfo;
 507
 508 typedef struct {
 509         int nargs;
 510         guint32 stack_usage;
 511         guint32 reg_usage;
 512         guint32 freg_usage;
 513         gboolean need_stack_align;
 514         /* The index of the vret arg in the argument list */
 515         int vret_arg_index;
 516         ArgInfo ret;
 517         ArgInfo sig_cookie;
 518         ArgInfo args [1];
 519 } CallInfo;
 520
 521 #define DEBUG(a) if (cfg->verbose_level > 1) a
 522
 523 #ifdef TARGET_WIN32
 524 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 525
 526 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 527 #else
 528 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 529
 530  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 531 #endif
 532
 533 static void inline
 534 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 535 {
 536     ainfo->offset = *stack_size;
 537
 538     if (*gr >= PARAM_REGS) {
 539                 ainfo->storage = ArgOnStack;
 540                 /* Since the same stack slot size is used for all arg */
 541                 /*  types, it needs to be big enough to hold them all */
 542                 (*stack_size) += sizeof(mgreg_t);
 543     }
 544     else {
 545                 ainfo->storage = ArgInIReg;
 546                 ainfo->reg = param_regs [*gr];
 547                 (*gr) ++;
 548     }
 549 }
 550
 551 #ifdef TARGET_WIN32
 552 #define FLOAT_PARAM_REGS 4
 553 #else
 554 #define FLOAT_PARAM_REGS 8
 555 #endif
 556
 557 static void inline
 558 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 559 {
 560     ainfo->offset = *stack_size;
 561
 562     if (*gr >= FLOAT_PARAM_REGS) {
 563                 ainfo->storage = ArgOnStack;
 564                 /* Since the same stack slot size is used for both float */
 565                 /*  types, it needs to be big enough to hold them both */
 566                 (*stack_size) += sizeof(mgreg_t);
 567     }
 568     else {
 569                 /* A double register */
 570                 if (is_double)
 571                         ainfo->storage = ArgInDoubleSSEReg;
 572                 else
 573                         ainfo->storage = ArgInFloatSSEReg;
 574                 ainfo->reg = *gr;
 575                 (*gr) += 1;
 576     }
 577 }
 578
 579 typedef enum ArgumentClass {
 580         ARG_CLASS_NO_CLASS,
 581         ARG_CLASS_MEMORY,
 582         ARG_CLASS_INTEGER,
 583         ARG_CLASS_SSE
 584 } ArgumentClass;
 585
 586 static ArgumentClass
 587 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 588 {
 589         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 590         MonoType *ptype;
 591
 592         ptype = mini_get_underlying_type (type);
 593         switch (ptype->type) {
 594         case MONO_TYPE_I1:
 595         case MONO_TYPE_U1:
 596         case MONO_TYPE_I2:
 597         case MONO_TYPE_U2:
 598         case MONO_TYPE_I4:
 599         case MONO_TYPE_U4:
 600         case MONO_TYPE_I:
 601         case MONO_TYPE_U:
 602         case MONO_TYPE_STRING:
 603         case MONO_TYPE_OBJECT:
 604         case MONO_TYPE_CLASS:
 605         case MONO_TYPE_SZARRAY:
 606         case MONO_TYPE_PTR:
 607         case MONO_TYPE_FNPTR:
 608         case MONO_TYPE_ARRAY:
 609         case MONO_TYPE_I8:
 610         case MONO_TYPE_U8:
 611                 class2 = ARG_CLASS_INTEGER;
 612                 break;
 613         case MONO_TYPE_R4:
 614         case MONO_TYPE_R8:
 615 #ifdef TARGET_WIN32
 616                 class2 = ARG_CLASS_INTEGER;
 617 #else
 618                 class2 = ARG_CLASS_SSE;
 619 #endif
 620                 break;
 621
 622         case MONO_TYPE_TYPEDBYREF:
 623                 g_assert_not_reached ();
 624
 625         case MONO_TYPE_GENERICINST:
 626                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 627                         class2 = ARG_CLASS_INTEGER;
 628                         break;
 629                 }
 630                 /* fall through */
 631         case MONO_TYPE_VALUETYPE: {
 632                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 633                 int i;
 634
 635                 for (i = 0; i < info->num_fields; ++i) {
 636                         class2 = class1;
 637                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 638                 }
 639                 break;
 640         }
 641         default:
 642                 g_assert_not_reached ();
 643         }
 644
 645         /* Merge */
 646         if (class1 == class2)
 647                 ;
 648         else if (class1 == ARG_CLASS_NO_CLASS)
 649                 class1 = class2;
 650         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 651                 class1 = ARG_CLASS_MEMORY;
 652         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 653                 class1 = ARG_CLASS_INTEGER;
 654         else
 655                 class1 = ARG_CLASS_SSE;
 656
 657         return class1;
 658 }
 659 #ifdef __native_client_codegen__
 660
 661 /* Default alignment for Native Client is 32-byte. */
 662 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 663
 664 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 665 /* Check that alignment doesn't cross an alignment boundary.             */
 666 guint8*
 667 mono_arch_nacl_pad(guint8 *code, int pad)
 668 {
 669         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 670
 671         if (pad == 0) return code;
 672         /* assertion: alignment cannot cross a block boundary */
 673         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 674                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 675         while (pad >= kMaxPadding) {
 676                 amd64_padding (code, kMaxPadding);
 677                 pad -= kMaxPadding;
 678         }
 679         if (pad != 0) amd64_padding (code, pad);
 680         return code;
 681 }
 682 #endif
 683
 684 static int
 685 count_fields_nested (MonoClass *klass)
 686 {
 687         MonoMarshalType *info;
 688         int i, count;
 689
 690         info = mono_marshal_load_type_info (klass);
 691         g_assert(info);
 692         count = 0;
 693         for (i = 0; i < info->num_fields; ++i) {
 694                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 695                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 696                 else
 697                         count ++;
 698         }
 699         return count;
 700 }
 701
 702 static int
 703 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 704 {
 705         MonoMarshalType *info;
 706         int i;
 707
 708         info = mono_marshal_load_type_info (klass);
 709         g_assert(info);
 710         for (i = 0; i < info->num_fields; ++i) {
 711                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 712                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 713                 } else {
 714                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 715                         fields [index].offset += offset;
 716                         index ++;
 717                 }
 718         }
 719         return index;
 720 }
 721
 722 #ifdef TARGET_WIN32
 723 static void
 724 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 725                                          gboolean is_return,
 726                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 727 {
 728         guint32 size, i, nfields;
 729         guint32 argsize = 8;
 730         ArgumentClass arg_class;
 731         MonoMarshalType *info = NULL;
 732         MonoMarshalField *fields = NULL;
 733         MonoClass *klass;
 734         gboolean pass_on_stack = FALSE;
 735
 736         klass = mono_class_from_mono_type (type);
 737         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 738         if (!sig->pinvoke)
 739                 pass_on_stack = TRUE;
 740
 741         /* If this struct can't be split up naturally into 8-byte */
 742         /* chunks (registers), pass it on the stack.              */
 743         if (sig->pinvoke && !pass_on_stack) {
 744                 guint32 align;
 745                 guint32 field_size;
 746
 747                 info = mono_marshal_load_type_info (klass);
 748                 g_assert (info);
 749
 750                 /*
 751                  * Collect field information recursively to be able to
 752                  * handle nested structures.
 753                  */
 754                 nfields = count_fields_nested (klass);
 755                 fields = g_new0 (MonoMarshalField, nfields);
 756                 collect_field_info_nested (klass, fields, 0, 0);
 757
 758                 for (i = 0; i < nfields; ++i) {
 759                         field_size = mono_marshal_type_size (fields [i].field->type,
 760                                                            fields [i].mspec,
 761                                                            &align, TRUE, klass->unicode);
 762                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 763                                 pass_on_stack = TRUE;
 764                                 break;
 765                         }
 766                 }
 767         }
 768
 769         if (pass_on_stack) {
 770                 /* Allways pass in memory */
 771                 ainfo->offset = *stack_size;
 772                 *stack_size += ALIGN_TO (size, 8);
 773                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 774
 775                 g_free (fields);
 776                 return;
 777         }
 778
 779         if (!sig->pinvoke) {
 780                 int n = mono_class_value_size (klass, NULL);
 781
 782                 argsize = n;
 783
 784                 if (n > 8)
 785                         arg_class = ARG_CLASS_MEMORY;
 786                 else
 787                         /* Always pass in 1 integer register */
 788                         arg_class = ARG_CLASS_INTEGER;
 789         } else {
 790                 g_assert (info);
 791
 792                 if (!fields) {
 793                         ainfo->storage = ArgValuetypeInReg;
 794                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 795                         return;
 796                 }
 797
 798                 switch (info->native_size) {
 799                 case 1: case 2: case 4: case 8:
 800                         break;
 801                 default:
 802                         if (is_return) {
 803                                 ainfo->storage = ArgValuetypeAddrInIReg;
 804                                 ainfo->offset = *stack_size;
 805                                 *stack_size += ALIGN_TO (info->native_size, 8);
 806                         }
 807                         else {
 808                                 ainfo->storage = ArgValuetypeAddrInIReg;
 809
 810                                 if (*gr < PARAM_REGS) {
 811                                         ainfo->pair_storage [0] = ArgInIReg;
 812                                         ainfo->pair_regs [0] = param_regs [*gr];
 813                                         (*gr) ++;
 814                                 }
 815                                 else {
 816                                         ainfo->pair_storage [0] = ArgOnStack;
 817                                         ainfo->offset = *stack_size;
 818                                         *stack_size += 8;
 819                                 }
 820                         }
 821
 822                         g_free (fields);
 823                         return;
 824                 }
 825
 826                 int size;
 827                 guint32 align;
 828                 ArgumentClass class1;
 829
 830                 if (nfields == 0)
 831                         class1 = ARG_CLASS_MEMORY;
 832                 else
 833                         class1 = ARG_CLASS_NO_CLASS;
 834                 for (i = 0; i < nfields; ++i) {
 835                         size = mono_marshal_type_size (fields [i].field->type,
 836                                                                                    fields [i].mspec,
 837                                                                                    &align, TRUE, klass->unicode);
 838                         /* How far into this quad this data extends.*/
 839                         /* (8 is size of quad) */
 840                         argsize = fields [i].offset + size;
 841
 842                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 843                 }
 844                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 845                 arg_class = class1;
 846         }
 847
 848         g_free (fields);
 849
 850         /* Allocate registers */
 851         {
 852                 int orig_gr = *gr;
 853                 int orig_fr = *fr;
 854
 855                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 856                         argsize ++;
 857
 858                 ainfo->storage = ArgValuetypeInReg;
 859                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 860                 ainfo->pair_size [0] = argsize;
 861                 ainfo->pair_size [1] = 0;
 862                 ainfo->nregs = 1;
 863                 switch (arg_class) {
 864                 case ARG_CLASS_INTEGER:
 865                         if (*gr >= PARAM_REGS)
 866                                 arg_class = ARG_CLASS_MEMORY;
 867                         else {
 868                                 ainfo->pair_storage [0] = ArgInIReg;
 869                                 if (is_return)
 870                                         ainfo->pair_regs [0] = return_regs [*gr];
 871                                 else
 872                                         ainfo->pair_regs [0] = param_regs [*gr];
 873                                 (*gr) ++;
 874                         }
 875                         break;
 876                 case ARG_CLASS_SSE:
 877                         if (*fr >= FLOAT_PARAM_REGS)
 878                                 arg_class = ARG_CLASS_MEMORY;
 879                         else {
 880                                 if (argsize <= 4)
 881                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 882                                 else
 883                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 884                                 ainfo->pair_regs [0] = *fr;
 885                                 (*fr) ++;
 886                         }
 887                         break;
 888                 case ARG_CLASS_MEMORY:
 889                         break;
 890                 default:
 891                         g_assert_not_reached ();
 892                 }
 893
 894                 if (arg_class == ARG_CLASS_MEMORY) {
 895                         /* Revert possible register assignments */
 896                         *gr = orig_gr;
 897                         *fr = orig_fr;
 898
 899                         ainfo->offset = *stack_size;
 900                         *stack_size += sizeof (mgreg_t);
 901                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 902                 }
 903         }
 904 }
 905 #endif /* TARGET_WIN32 */
 906
 907 static void
 908 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 909                            gboolean is_return,
 910                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 911 {
 912 #ifdef TARGET_WIN32
 913         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 914 #else
 915         guint32 size, quad, nquads, i, nfields;
 916         /* Keep track of the size used in each quad so we can */
 917         /* use the right size when copying args/return vars.  */
 918         guint32 quadsize [2] = {8, 8};
 919         ArgumentClass args [2];
 920         MonoMarshalType *info = NULL;
 921         MonoMarshalField *fields = NULL;
 922         MonoClass *klass;
 923         gboolean pass_on_stack = FALSE;
 924
 925         klass = mono_class_from_mono_type (type);
 926         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 927         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 928                 /* We pass and return vtypes of size 8 in a register */
 929         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 930                 pass_on_stack = TRUE;
 931         }
 932
 933         /* If this struct can't be split up naturally into 8-byte */
 934         /* chunks (registers), pass it on the stack.              */
 935         if (sig->pinvoke && !pass_on_stack) {
 936                 guint32 align;
 937                 guint32 field_size;
 938
 939                 info = mono_marshal_load_type_info (klass);
 940                 g_assert (info);
 941
 942                 /*
 943                  * Collect field information recursively to be able to
 944                  * handle nested structures.
 945                  */
 946                 nfields = count_fields_nested (klass);
 947                 fields = g_new0 (MonoMarshalField, nfields);
 948                 collect_field_info_nested (klass, fields, 0, 0);
 949
 950                 for (i = 0; i < nfields; ++i) {
 951                         field_size = mono_marshal_type_size (fields [i].field->type,
 952                                                            fields [i].mspec,
 953                                                            &align, TRUE, klass->unicode);
 954                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 955                                 pass_on_stack = TRUE;
 956                                 break;
 957                         }
 958                 }
 959         }
 960
 961         if (size == 0) {
 962                 ainfo->storage = ArgValuetypeInReg;
 963                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 964                 return;
 965         }
 966
 967         if (pass_on_stack) {
 968                 /* Allways pass in memory */
 969                 ainfo->offset = *stack_size;
 970                 *stack_size += ALIGN_TO (size, 8);
 971                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 972
 973                 g_free (fields);
 974                 return;
 975         }
 976
 977         if (size > 8)
 978                 nquads = 2;
 979         else
 980                 nquads = 1;
 981
 982         if (!sig->pinvoke) {
 983                 int n = mono_class_value_size (klass, NULL);
 984
 985                 quadsize [0] = n >= 8 ? 8 : n;
 986                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 987
 988                 /* Always pass in 1 or 2 integer registers */
 989                 args [0] = ARG_CLASS_INTEGER;
 990                 args [1] = ARG_CLASS_INTEGER;
 991                 /* Only the simplest cases are supported */
 992                 if (is_return && nquads != 1) {
 993                         args [0] = ARG_CLASS_MEMORY;
 994                         args [1] = ARG_CLASS_MEMORY;
 995                 }
 996         } else {
 997                 /*
 998                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 999                  * The X87 and SSEUP stuff is left out since there are no such types in
1000                  * the CLR.
1001                  */
1002                 g_assert (info);
1003
1004                 if (!fields) {
1005                         ainfo->storage = ArgValuetypeInReg;
1006                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1007                         return;
1008                 }
1009
1010                 if (info->native_size > 16) {
1011                         ainfo->offset = *stack_size;
1012                         *stack_size += ALIGN_TO (info->native_size, 8);
1013                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1014
1015                         g_free (fields);
1016                         return;
1017                 }
1018
1019                 args [0] = ARG_CLASS_NO_CLASS;
1020                 args [1] = ARG_CLASS_NO_CLASS;
1021                 for (quad = 0; quad < nquads; ++quad) {
1022                         int size;
1023                         guint32 align;
1024                         ArgumentClass class1;
1025
1026                         if (nfields == 0)
1027                                 class1 = ARG_CLASS_MEMORY;
1028                         else
1029                                 class1 = ARG_CLASS_NO_CLASS;
1030                         for (i = 0; i < nfields; ++i) {
1031                                 size = mono_marshal_type_size (fields [i].field->type,
1032                                                                                            fields [i].mspec,
1033                                                                                            &align, TRUE, klass->unicode);
1034                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
1035                                         /* Unaligned field */
1036                                         NOT_IMPLEMENTED;
1037                                 }
1038
1039                                 /* Skip fields in other quad */
1040                                 if ((quad == 0) && (fields [i].offset >= 8))
1041                                         continue;
1042                                 if ((quad == 1) && (fields [i].offset < 8))
1043                                         continue;
1044
1045                                 /* How far into this quad this data extends.*/
1046                                 /* (8 is size of quad) */
1047                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
1048
1049                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
1050                         }
1051                         g_assert (class1 != ARG_CLASS_NO_CLASS);
1052                         args [quad] = class1;
1053                 }
1054         }
1055
1056         g_free (fields);
1057
1058         /* Post merger cleanup */
1059         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
1060                 args [0] = args [1] = ARG_CLASS_MEMORY;
1061
1062         /* Allocate registers */
1063         {
1064                 int orig_gr = *gr;
1065                 int orig_fr = *fr;
1066
1067                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
1068                         quadsize [0] ++;
1069                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1070                         quadsize [1] ++;
1071
1072                 ainfo->storage = ArgValuetypeInReg;
1073                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1074                 g_assert (quadsize [0] <= 8);
1075                 g_assert (quadsize [1] <= 8);
1076                 ainfo->pair_size [0] = quadsize [0];
1077                 ainfo->pair_size [1] = quadsize [1];
1078                 ainfo->nregs = nquads;
1079                 for (quad = 0; quad < nquads; ++quad) {
1080                         switch (args [quad]) {
1081                         case ARG_CLASS_INTEGER:
1082                                 if (*gr >= PARAM_REGS)
1083                                         args [quad] = ARG_CLASS_MEMORY;
1084                                 else {
1085                                         ainfo->pair_storage [quad] = ArgInIReg;
1086                                         if (is_return)
1087                                                 ainfo->pair_regs [quad] = return_regs [*gr];
1088                                         else
1089                                                 ainfo->pair_regs [quad] = param_regs [*gr];
1090                                         (*gr) ++;
1091                                 }
1092                                 break;
1093                         case ARG_CLASS_SSE:
1094                                 if (*fr >= FLOAT_PARAM_REGS)
1095                                         args [quad] = ARG_CLASS_MEMORY;
1096                                 else {
1097                                         if (quadsize[quad] <= 4)
1098                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
1099                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
1100                                         ainfo->pair_regs [quad] = *fr;
1101                                         (*fr) ++;
1102                                 }
1103                                 break;
1104                         case ARG_CLASS_MEMORY:
1105                                 break;
1106                         default:
1107                                 g_assert_not_reached ();
1108                         }
1109                 }
1110
1111                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
1112                         /* Revert possible register assignments */
1113                         *gr = orig_gr;
1114                         *fr = orig_fr;
1115
1116                         ainfo->offset = *stack_size;
1117                         if (sig->pinvoke)
1118                                 *stack_size += ALIGN_TO (info->native_size, 8);
1119                         else
1120                                 *stack_size += nquads * sizeof(mgreg_t);
1121                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1122                 }
1123         }
1124 #endif /* !TARGET_WIN32 */
1125 }
1126
1127 /*
1128  * get_call_info:
1129  *
1130  *  Obtain information about a call according to the calling convention.
1131  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1132  * Draft Version 0.23" document for more information.
1133  */
1134 static CallInfo*
1135 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1136 {
1137         guint32 i, gr, fr, pstart;
1138         MonoType *ret_type;
1139         int n = sig->hasthis + sig->param_count;
1140         guint32 stack_size = 0;
1141         CallInfo *cinfo;
1142         gboolean is_pinvoke = sig->pinvoke;
1143
1144         if (mp)
1145                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1146         else
1147                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1148
1149         cinfo->nargs = n;
1150
1151         gr = 0;
1152         fr = 0;
1153
1154 #ifdef TARGET_WIN32
1155         /* Reserve space where the callee can save the argument registers */
1156         stack_size = 4 * sizeof (mgreg_t);
1157 #endif
1158
1159         /* return value */
1160         ret_type = mini_get_underlying_type (sig->ret);
1161         switch (ret_type->type) {
1162         case MONO_TYPE_I1:
1163         case MONO_TYPE_U1:
1164         case MONO_TYPE_I2:
1165         case MONO_TYPE_U2:
1166         case MONO_TYPE_I4:
1167         case MONO_TYPE_U4:
1168         case MONO_TYPE_I:
1169         case MONO_TYPE_U:
1170         case MONO_TYPE_PTR:
1171         case MONO_TYPE_FNPTR:
1172         case MONO_TYPE_CLASS:
1173         case MONO_TYPE_OBJECT:
1174         case MONO_TYPE_SZARRAY:
1175         case MONO_TYPE_ARRAY:
1176         case MONO_TYPE_STRING:
1177                 cinfo->ret.storage = ArgInIReg;
1178                 cinfo->ret.reg = AMD64_RAX;
1179                 break;
1180         case MONO_TYPE_U8:
1181         case MONO_TYPE_I8:
1182                 cinfo->ret.storage = ArgInIReg;
1183                 cinfo->ret.reg = AMD64_RAX;
1184                 break;
1185         case MONO_TYPE_R4:
1186                 cinfo->ret.storage = ArgInFloatSSEReg;
1187                 cinfo->ret.reg = AMD64_XMM0;
1188                 break;
1189         case MONO_TYPE_R8:
1190                 cinfo->ret.storage = ArgInDoubleSSEReg;
1191                 cinfo->ret.reg = AMD64_XMM0;
1192                 break;
1193         case MONO_TYPE_GENERICINST:
1194                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1195                         cinfo->ret.storage = ArgInIReg;
1196                         cinfo->ret.reg = AMD64_RAX;
1197                         break;
1198                 }
1199                 if (mini_is_gsharedvt_type (ret_type)) {
1200                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1201                         break;
1202                 }
1203                 /* fall through */
1204         case MONO_TYPE_VALUETYPE:
1205         case MONO_TYPE_TYPEDBYREF: {
1206                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1207
1208                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1209                 g_assert (cinfo->ret.storage != ArgInIReg);
1210                 break;
1211         }
1212         case MONO_TYPE_VAR:
1213         case MONO_TYPE_MVAR:
1214                 g_assert (mini_is_gsharedvt_type (ret_type));
1215                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1216                 break;
1217         case MONO_TYPE_VOID:
1218                 break;
1219         default:
1220                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1221         }
1222
1223         pstart = 0;
1224         /*
1225          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1226          * the first argument, allowing 'this' to be always passed in the first arg reg.
1227          * Also do this if the first argument is a reference type, since virtual calls
1228          * are sometimes made using calli without sig->hasthis set, like in the delegate
1229          * invoke wrappers.
1230          */
1231         if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1232                 if (sig->hasthis) {
1233                         add_general (&gr, &stack_size, cinfo->args + 0);
1234                 } else {
1235                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1236                         pstart = 1;
1237                 }
1238                 add_general (&gr, &stack_size, &cinfo->ret);
1239                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1240                 cinfo->vret_arg_index = 1;
1241         } else {
1242                 /* this */
1243                 if (sig->hasthis)
1244                         add_general (&gr, &stack_size, cinfo->args + 0);
1245
1246                 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1247                         add_general (&gr, &stack_size, &cinfo->ret);
1248                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1249                 }
1250         }
1251
1252         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1253                 gr = PARAM_REGS;
1254                 fr = FLOAT_PARAM_REGS;
1255
1256                 /* Emit the signature cookie just before the implicit arguments */
1257                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1258         }
1259
1260         for (i = pstart; i < sig->param_count; ++i) {
1261                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1262                 MonoType *ptype;
1263
1264 #ifdef TARGET_WIN32
1265                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1266                 if (gr > fr)
1267                         fr = gr;
1268                 else if (fr > gr)
1269                         gr = fr;
1270 #endif
1271
1272                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1273                         /* We allways pass the sig cookie on the stack for simplicity */
1274                         /*
1275                          * Prevent implicit arguments + the sig cookie from being passed
1276                          * in registers.
1277                          */
1278                         gr = PARAM_REGS;
1279                         fr = FLOAT_PARAM_REGS;
1280
1281                         /* Emit the signature cookie just before the implicit arguments */
1282                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1283                 }
1284
1285                 ptype = mini_get_underlying_type (sig->params [i]);
1286                 switch (ptype->type) {
1287                 case MONO_TYPE_I1:
1288                 case MONO_TYPE_U1:
1289                         add_general (&gr, &stack_size, ainfo);
1290                         break;
1291                 case MONO_TYPE_I2:
1292                 case MONO_TYPE_U2:
1293                         add_general (&gr, &stack_size, ainfo);
1294                         break;
1295                 case MONO_TYPE_I4:
1296                 case MONO_TYPE_U4:
1297                         add_general (&gr, &stack_size, ainfo);
1298                         break;
1299                 case MONO_TYPE_I:
1300                 case MONO_TYPE_U:
1301                 case MONO_TYPE_PTR:
1302                 case MONO_TYPE_FNPTR:
1303                 case MONO_TYPE_CLASS:
1304                 case MONO_TYPE_OBJECT:
1305                 case MONO_TYPE_STRING:
1306                 case MONO_TYPE_SZARRAY:
1307                 case MONO_TYPE_ARRAY:
1308                         add_general (&gr, &stack_size, ainfo);
1309                         break;
1310                 case MONO_TYPE_GENERICINST:
1311                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1312                                 add_general (&gr, &stack_size, ainfo);
1313                                 break;
1314                         }
1315                         if (mini_is_gsharedvt_type (ptype)) {
1316                                 /* gsharedvt arguments are passed by ref */
1317                                 add_general (&gr, &stack_size, ainfo);
1318                                 if (ainfo->storage == ArgInIReg)
1319                                         ainfo->storage = ArgGSharedVtInReg;
1320                                 else
1321                                         ainfo->storage = ArgGSharedVtOnStack;
1322                                 break;
1323                         }
1324                         /* fall through */
1325                 case MONO_TYPE_VALUETYPE:
1326                 case MONO_TYPE_TYPEDBYREF:
1327                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1328                         break;
1329                 case MONO_TYPE_U8:
1330
1331                 case MONO_TYPE_I8:
1332                         add_general (&gr, &stack_size, ainfo);
1333                         break;
1334                 case MONO_TYPE_R4:
1335                         add_float (&fr, &stack_size, ainfo, FALSE);
1336                         break;
1337                 case MONO_TYPE_R8:
1338                         add_float (&fr, &stack_size, ainfo, TRUE);
1339                         break;
1340                 case MONO_TYPE_VAR:
1341                 case MONO_TYPE_MVAR:
1342                         /* gsharedvt arguments are passed by ref */
1343                         g_assert (mini_is_gsharedvt_type (ptype));
1344                         add_general (&gr, &stack_size, ainfo);
1345                         if (ainfo->storage == ArgInIReg)
1346                                 ainfo->storage = ArgGSharedVtInReg;
1347                         else
1348                                 ainfo->storage = ArgGSharedVtOnStack;
1349                         break;
1350                 default:
1351                         g_assert_not_reached ();
1352                 }
1353         }
1354
1355         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1356                 gr = PARAM_REGS;
1357                 fr = FLOAT_PARAM_REGS;
1358
1359                 /* Emit the signature cookie just before the implicit arguments */
1360                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1361         }
1362
1363         cinfo->stack_usage = stack_size;
1364         cinfo->reg_usage = gr;
1365         cinfo->freg_usage = fr;
1366         return cinfo;
1367 }
1368
1369 /*
1370  * mono_arch_get_argument_info:
1371  * @csig:  a method signature
1372  * @param_count: the number of parameters to consider
1373  * @arg_info: an array to store the result infos
1374  *
1375  * Gathers information on parameters such as size, alignment and
1376  * padding. arg_info should be large enought to hold param_count + 1 entries.
1377  *
1378  * Returns the size of the argument area on the stack.
1379  */
1380 int
1381 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1382 {
1383         int k;
1384         CallInfo *cinfo = get_call_info (NULL, csig);
1385         guint32 args_size = cinfo->stack_usage;
1386
1387         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1388         if (csig->hasthis) {
1389                 arg_info [0].offset = 0;
1390         }
1391
1392         for (k = 0; k < param_count; k++) {
1393                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1394                 /* FIXME: */
1395                 arg_info [k + 1].size = 0;
1396         }
1397
1398         g_free (cinfo);
1399
1400         return args_size;
1401 }
1402
1403 gboolean
1404 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1405 {
1406         CallInfo *c1, *c2;
1407         gboolean res;
1408         MonoType *callee_ret;
1409
1410         c1 = get_call_info (NULL, caller_sig);
1411         c2 = get_call_info (NULL, callee_sig);
1412         res = c1->stack_usage >= c2->stack_usage;
1413         callee_ret = mini_get_underlying_type (callee_sig->ret);
1414         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1415                 /* An address on the callee's stack is passed as the first argument */
1416                 res = FALSE;
1417
1418         g_free (c1);
1419         g_free (c2);
1420
1421         return res;
1422 }
1423
1424 /*
1425  * Initialize the cpu to execute managed code.
1426  */
1427 void
1428 mono_arch_cpu_init (void)
1429 {
1430 #ifndef _MSC_VER
1431         guint16 fpcw;
1432
1433         /* spec compliance requires running with double precision */
1434         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1435         fpcw &= ~X86_FPCW_PRECC_MASK;
1436         fpcw |= X86_FPCW_PREC_DOUBLE;
1437         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1438         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1439 #else
1440         /* TODO: This is crashing on Win64 right now.
1441         * _control87 (_PC_53, MCW_PC);
1442         */
1443 #endif
1444 }
1445
1446 /*
1447  * Initialize architecture specific code.
1448  */
1449 void
1450 mono_arch_init (void)
1451 {
1452         mono_mutex_init_recursive (&mini_arch_mutex);
1453 #if defined(__native_client_codegen__)
1454         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1455         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1456         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1457         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1458 #endif
1459
1460         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1461         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1462         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1463         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1464
1465         if (!mono_aot_only)
1466                 bp_trampoline = mini_get_breakpoint_trampoline ();
1467 }
1468
1469 /*
1470  * Cleanup architecture specific code.
1471  */
1472 void
1473 mono_arch_cleanup (void)
1474 {
1475         mono_mutex_destroy (&mini_arch_mutex);
1476 #if defined(__native_client_codegen__)
1477         mono_native_tls_free (nacl_instruction_depth);
1478         mono_native_tls_free (nacl_rex_tag);
1479         mono_native_tls_free (nacl_legacy_prefix_tag);
1480 #endif
1481 }
1482
1483 /*
1484  * This function returns the optimizations supported on this cpu.
1485  */
1486 guint32
1487 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1488 {
1489         guint32 opts = 0;
1490
1491         *exclude_mask = 0;
1492
1493         if (mono_hwcap_x86_has_cmov) {
1494                 opts |= MONO_OPT_CMOV;
1495
1496                 if (mono_hwcap_x86_has_fcmov)
1497                         opts |= MONO_OPT_FCMOV;
1498                 else
1499                         *exclude_mask |= MONO_OPT_FCMOV;
1500         } else {
1501                 *exclude_mask |= MONO_OPT_CMOV;
1502         }
1503
1504         return opts;
1505 }
1506
1507 /*
1508  * This function test for all SSE functions supported.
1509  *
1510  * Returns a bitmask corresponding to all supported versions.
1511  *
1512  */
1513 guint32
1514 mono_arch_cpu_enumerate_simd_versions (void)
1515 {
1516         guint32 sse_opts = 0;
1517
1518         if (mono_hwcap_x86_has_sse1)
1519                 sse_opts |= SIMD_VERSION_SSE1;
1520
1521         if (mono_hwcap_x86_has_sse2)
1522                 sse_opts |= SIMD_VERSION_SSE2;
1523
1524         if (mono_hwcap_x86_has_sse3)
1525                 sse_opts |= SIMD_VERSION_SSE3;
1526
1527         if (mono_hwcap_x86_has_ssse3)
1528                 sse_opts |= SIMD_VERSION_SSSE3;
1529
1530         if (mono_hwcap_x86_has_sse41)
1531                 sse_opts |= SIMD_VERSION_SSE41;
1532
1533         if (mono_hwcap_x86_has_sse42)
1534                 sse_opts |= SIMD_VERSION_SSE42;
1535
1536         if (mono_hwcap_x86_has_sse4a)
1537                 sse_opts |= SIMD_VERSION_SSE4a;
1538
1539         return sse_opts;
1540 }
1541
1542 #ifndef DISABLE_JIT
1543
1544 GList *
1545 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1546 {
1547         GList *vars = NULL;
1548         int i;
1549
1550         for (i = 0; i < cfg->num_varinfo; i++) {
1551                 MonoInst *ins = cfg->varinfo [i];
1552                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1553
1554                 /* unused vars */
1555                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1556                         continue;
1557
1558                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1559                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1560                         continue;
1561
1562                 if (mono_is_regsize_var (ins->inst_vtype)) {
1563                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1564                         g_assert (i == vmv->idx);
1565                         vars = g_list_prepend (vars, vmv);
1566                 }
1567         }
1568
1569         vars = mono_varlist_sort (cfg, vars, 0);
1570
1571         return vars;
1572 }
1573
1574 /**
1575  * mono_arch_compute_omit_fp:
1576  *
1577  *   Determine whenever the frame pointer can be eliminated.
1578  */
1579 static void
1580 mono_arch_compute_omit_fp (MonoCompile *cfg)
1581 {
1582         MonoMethodSignature *sig;
1583         MonoMethodHeader *header;
1584         int i, locals_size;
1585         CallInfo *cinfo;
1586
1587         if (cfg->arch.omit_fp_computed)
1588                 return;
1589
1590         header = cfg->header;
1591
1592         sig = mono_method_signature (cfg->method);
1593
1594         if (!cfg->arch.cinfo)
1595                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1596         cinfo = cfg->arch.cinfo;
1597
1598         /*
1599          * FIXME: Remove some of the restrictions.
1600          */
1601         cfg->arch.omit_fp = TRUE;
1602         cfg->arch.omit_fp_computed = TRUE;
1603
1604 #ifdef __native_client_codegen__
1605         /* NaCl modules may not change the value of RBP, so it cannot be */
1606         /* used as a normal register, but it can be used as a frame pointer*/
1607         cfg->disable_omit_fp = TRUE;
1608         cfg->arch.omit_fp = FALSE;
1609 #endif
1610
1611         if (cfg->disable_omit_fp)
1612                 cfg->arch.omit_fp = FALSE;
1613
1614         if (!debug_omit_fp ())
1615                 cfg->arch.omit_fp = FALSE;
1616         /*
1617         if (cfg->method->save_lmf)
1618                 cfg->arch.omit_fp = FALSE;
1619         */
1620         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1621                 cfg->arch.omit_fp = FALSE;
1622         if (header->num_clauses)
1623                 cfg->arch.omit_fp = FALSE;
1624         if (cfg->param_area)
1625                 cfg->arch.omit_fp = FALSE;
1626         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1627                 cfg->arch.omit_fp = FALSE;
1628         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1629                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1630                 cfg->arch.omit_fp = FALSE;
1631         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1632                 ArgInfo *ainfo = &cinfo->args [i];
1633
1634                 if (ainfo->storage == ArgOnStack) {
1635                         /*
1636                          * The stack offset can only be determined when the frame
1637                          * size is known.
1638                          */
1639                         cfg->arch.omit_fp = FALSE;
1640                 }
1641         }
1642
1643         locals_size = 0;
1644         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1645                 MonoInst *ins = cfg->varinfo [i];
1646                 int ialign;
1647
1648                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1649         }
1650 }
1651
1652 GList *
1653 mono_arch_get_global_int_regs (MonoCompile *cfg)
1654 {
1655         GList *regs = NULL;
1656
1657         mono_arch_compute_omit_fp (cfg);
1658
1659         if (cfg->arch.omit_fp)
1660                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1661
1662         /* We use the callee saved registers for global allocation */
1663         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1664         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1665         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1666         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1667 #ifndef __native_client_codegen__
1668         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1669 #endif
1670 #ifdef TARGET_WIN32
1671         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1672         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1673 #endif
1674
1675         return regs;
1676 }
1677
1678 GList*
1679 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1680 {
1681         GList *regs = NULL;
1682         int i;
1683
1684         /* All XMM registers */
1685         for (i = 0; i < 16; ++i)
1686                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1687
1688         return regs;
1689 }
1690
1691 GList*
1692 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1693 {
1694         static GList *r = NULL;
1695
1696         if (r == NULL) {
1697                 GList *regs = NULL;
1698
1699                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1700                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1701                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1702                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1703                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1704 #ifndef __native_client_codegen__
1705                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1706 #endif
1707
1708                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1709                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1710                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1711                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1712                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1713                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1714                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1715                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1716
1717                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1718         }
1719
1720         return r;
1721 }
1722
1723 GList*
1724 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1725 {
1726         int i;
1727         static GList *r = NULL;
1728
1729         if (r == NULL) {
1730                 GList *regs = NULL;
1731
1732                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1733                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1734
1735                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1736         }
1737
1738         return r;
1739 }
1740
1741 /*
1742  * mono_arch_regalloc_cost:
1743  *
1744  *  Return the cost, in number of memory references, of the action of
1745  * allocating the variable VMV into a register during global register
1746  * allocation.
1747  */
1748 guint32
1749 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1750 {
1751         MonoInst *ins = cfg->varinfo [vmv->idx];
1752
1753         if (cfg->method->save_lmf)
1754                 /* The register is already saved */
1755                 /* substract 1 for the invisible store in the prolog */
1756                 return (ins->opcode == OP_ARG) ? 0 : 1;
1757         else
1758                 /* push+pop */
1759                 return (ins->opcode == OP_ARG) ? 1 : 2;
1760 }
1761
1762 /*
1763  * mono_arch_fill_argument_info:
1764  *
1765  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1766  * of the method.
1767  */
1768 void
1769 mono_arch_fill_argument_info (MonoCompile *cfg)
1770 {
1771         MonoType *sig_ret;
1772         MonoMethodSignature *sig;
1773         MonoInst *ins;
1774         int i;
1775         CallInfo *cinfo;
1776
1777         sig = mono_method_signature (cfg->method);
1778
1779         cinfo = cfg->arch.cinfo;
1780         sig_ret = mini_get_underlying_type (sig->ret);
1781
1782         /*
1783          * Contrary to mono_arch_allocate_vars (), the information should describe
1784          * where the arguments are at the beginning of the method, not where they can be
1785          * accessed during the execution of the method. The later makes no sense for the
1786          * global register allocator, since a variable can be in more than one location.
1787          */
1788         switch (cinfo->ret.storage) {
1789         case ArgInIReg:
1790         case ArgInFloatSSEReg:
1791         case ArgInDoubleSSEReg:
1792                 cfg->ret->opcode = OP_REGVAR;
1793                 cfg->ret->inst_c0 = cinfo->ret.reg;
1794                 break;
1795         case ArgValuetypeInReg:
1796                 cfg->ret->opcode = OP_REGOFFSET;
1797                 cfg->ret->inst_basereg = -1;
1798                 cfg->ret->inst_offset = -1;
1799                 break;
1800         case ArgNone:
1801                 break;
1802         default:
1803                 g_assert_not_reached ();
1804         }
1805
1806         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1807                 ArgInfo *ainfo = &cinfo->args [i];
1808
1809                 ins = cfg->args [i];
1810
1811                 switch (ainfo->storage) {
1812                 case ArgInIReg:
1813                 case ArgInFloatSSEReg:
1814                 case ArgInDoubleSSEReg:
1815                         ins->opcode = OP_REGVAR;
1816                         ins->inst_c0 = ainfo->reg;
1817                         break;
1818                 case ArgOnStack:
1819                         ins->opcode = OP_REGOFFSET;
1820                         ins->inst_basereg = -1;
1821                         ins->inst_offset = -1;
1822                         break;
1823                 case ArgValuetypeInReg:
1824                         /* Dummy */
1825                         ins->opcode = OP_NOP;
1826                         break;
1827                 default:
1828                         g_assert_not_reached ();
1829                 }
1830         }
1831 }
1832
1833 void
1834 mono_arch_allocate_vars (MonoCompile *cfg)
1835 {
1836         MonoType *sig_ret;
1837         MonoMethodSignature *sig;
1838         MonoInst *ins;
1839         int i, offset;
1840         guint32 locals_stack_size, locals_stack_align;
1841         gint32 *offsets;
1842         CallInfo *cinfo;
1843
1844         sig = mono_method_signature (cfg->method);
1845
1846         cinfo = cfg->arch.cinfo;
1847         sig_ret = mini_get_underlying_type (sig->ret);
1848
1849         mono_arch_compute_omit_fp (cfg);
1850
1851         /*
1852          * We use the ABI calling conventions for managed code as well.
1853          * Exception: valuetypes are only sometimes passed or returned in registers.
1854          */
1855
1856         /*
1857          * The stack looks like this:
1858          * <incoming arguments passed on the stack>
1859          * <return value>
1860          * <lmf/caller saved registers>
1861          * <locals>
1862          * <spill area>
1863          * <localloc area>  -> grows dynamically
1864          * <params area>
1865          */
1866
1867         if (cfg->arch.omit_fp) {
1868                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1869                 cfg->frame_reg = AMD64_RSP;
1870                 offset = 0;
1871         } else {
1872                 /* Locals are allocated backwards from %fp */
1873                 cfg->frame_reg = AMD64_RBP;
1874                 offset = 0;
1875         }
1876
1877         cfg->arch.saved_iregs = cfg->used_int_regs;
1878         if (cfg->method->save_lmf)
1879                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1880                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1881
1882         if (cfg->arch.omit_fp)
1883                 cfg->arch.reg_save_area_offset = offset;
1884         /* Reserve space for callee saved registers */
1885         for (i = 0; i < AMD64_NREG; ++i)
1886                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1887                         offset += sizeof(mgreg_t);
1888                 }
1889         if (!cfg->arch.omit_fp)
1890                 cfg->arch.reg_save_area_offset = -offset;
1891
1892         if (sig_ret->type != MONO_TYPE_VOID) {
1893                 switch (cinfo->ret.storage) {
1894                 case ArgInIReg:
1895                 case ArgInFloatSSEReg:
1896                 case ArgInDoubleSSEReg:
1897                         cfg->ret->opcode = OP_REGVAR;
1898                         cfg->ret->inst_c0 = cinfo->ret.reg;
1899                         break;
1900                 case ArgValuetypeAddrInIReg:
1901                         /* The register is volatile */
1902                         cfg->vret_addr->opcode = OP_REGOFFSET;
1903                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1904                         if (cfg->arch.omit_fp) {
1905                                 cfg->vret_addr->inst_offset = offset;
1906                                 offset += 8;
1907                         } else {
1908                                 offset += 8;
1909                                 cfg->vret_addr->inst_offset = -offset;
1910                         }
1911                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1912                                 printf ("vret_addr =");
1913                                 mono_print_ins (cfg->vret_addr);
1914                         }
1915                         break;
1916                 case ArgValuetypeInReg:
1917                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1918                         cfg->ret->opcode = OP_REGOFFSET;
1919                         cfg->ret->inst_basereg = cfg->frame_reg;
1920                         if (cfg->arch.omit_fp) {
1921                                 cfg->ret->inst_offset = offset;
1922                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1923                         } else {
1924                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1925                                 cfg->ret->inst_offset = - offset;
1926                         }
1927                         break;
1928                 default:
1929                         g_assert_not_reached ();
1930                 }
1931                 cfg->ret->dreg = cfg->ret->inst_c0;
1932         }
1933
1934         /* Allocate locals */
1935         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1936         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1937                 char *mname = mono_method_full_name (cfg->method, TRUE);
1938                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1939                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1940                 g_free (mname);
1941                 return;
1942         }
1943
1944         if (locals_stack_align) {
1945                 offset += (locals_stack_align - 1);
1946                 offset &= ~(locals_stack_align - 1);
1947         }
1948         if (cfg->arch.omit_fp) {
1949                 cfg->locals_min_stack_offset = offset;
1950                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1951         } else {
1952                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1953                 cfg->locals_max_stack_offset = - offset;
1954         }
1955
1956         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1957                 if (offsets [i] != -1) {
1958                         MonoInst *ins = cfg->varinfo [i];
1959                         ins->opcode = OP_REGOFFSET;
1960                         ins->inst_basereg = cfg->frame_reg;
1961                         if (cfg->arch.omit_fp)
1962                                 ins->inst_offset = (offset + offsets [i]);
1963                         else
1964                                 ins->inst_offset = - (offset + offsets [i]);
1965                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1966                 }
1967         }
1968         offset += locals_stack_size;
1969
1970         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1971                 g_assert (!cfg->arch.omit_fp);
1972                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1973                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1974         }
1975
1976         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1977                 ins = cfg->args [i];
1978                 if (ins->opcode != OP_REGVAR) {
1979                         ArgInfo *ainfo = &cinfo->args [i];
1980                         gboolean inreg = TRUE;
1981
1982                         /* FIXME: Allocate volatile arguments to registers */
1983                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1984                                 inreg = FALSE;
1985
1986                         /*
1987                          * Under AMD64, all registers used to pass arguments to functions
1988                          * are volatile across calls.
1989                          * FIXME: Optimize this.
1990                          */
1991                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1992                                 inreg = FALSE;
1993
1994                         ins->opcode = OP_REGOFFSET;
1995
1996                         switch (ainfo->storage) {
1997                         case ArgInIReg:
1998                         case ArgInFloatSSEReg:
1999                         case ArgInDoubleSSEReg:
2000                         case ArgGSharedVtInReg:
2001                                 if (inreg) {
2002                                         ins->opcode = OP_REGVAR;
2003                                         ins->dreg = ainfo->reg;
2004                                 }
2005                                 break;
2006                         case ArgOnStack:
2007                         case ArgGSharedVtOnStack:
2008                                 g_assert (!cfg->arch.omit_fp);
2009                                 ins->opcode = OP_REGOFFSET;
2010                                 ins->inst_basereg = cfg->frame_reg;
2011                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
2012                                 break;
2013                         case ArgValuetypeInReg:
2014                                 break;
2015                         case ArgValuetypeAddrInIReg: {
2016                                 MonoInst *indir;
2017                                 g_assert (!cfg->arch.omit_fp);
2018
2019                                 MONO_INST_NEW (cfg, indir, 0);
2020                                 indir->opcode = OP_REGOFFSET;
2021                                 if (ainfo->pair_storage [0] == ArgInIReg) {
2022                                         indir->inst_basereg = cfg->frame_reg;
2023                                         offset = ALIGN_TO (offset, sizeof (gpointer));
2024                                         offset += (sizeof (gpointer));
2025                                         indir->inst_offset = - offset;
2026                                 }
2027                                 else {
2028                                         indir->inst_basereg = cfg->frame_reg;
2029                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
2030                                 }
2031
2032                                 ins->opcode = OP_VTARG_ADDR;
2033                                 ins->inst_left = indir;
2034
2035                                 break;
2036                         }
2037                         default:
2038                                 NOT_IMPLEMENTED;
2039                         }
2040
2041                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
2042                                 ins->opcode = OP_REGOFFSET;
2043                                 ins->inst_basereg = cfg->frame_reg;
2044                                 /* These arguments are saved to the stack in the prolog */
2045                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
2046                                 if (cfg->arch.omit_fp) {
2047                                         ins->inst_offset = offset;
2048                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2049                                         // Arguments are yet supported by the stack map creation code
2050                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2051                                 } else {
2052                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2053                                         ins->inst_offset = - offset;
2054                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2055                                 }
2056                         }
2057                 }
2058         }
2059
2060         cfg->stack_offset = offset;
2061 }
2062
2063 void
2064 mono_arch_create_vars (MonoCompile *cfg)
2065 {
2066         MonoMethodSignature *sig;
2067         CallInfo *cinfo;
2068         MonoType *sig_ret;
2069
2070         sig = mono_method_signature (cfg->method);
2071
2072         if (!cfg->arch.cinfo)
2073                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2074         cinfo = cfg->arch.cinfo;
2075
2076         if (cinfo->ret.storage == ArgValuetypeInReg)
2077                 cfg->ret_var_is_local = TRUE;
2078
2079         sig_ret = mini_get_underlying_type (sig->ret);
2080         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2081                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2082                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2083                         printf ("vret_addr = ");
2084                         mono_print_ins (cfg->vret_addr);
2085                 }
2086         }
2087
2088         if (cfg->gen_sdb_seq_points) {
2089                 MonoInst *ins;
2090
2091                 if (cfg->compile_aot) {
2092                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2093                         ins->flags |= MONO_INST_VOLATILE;
2094                         cfg->arch.seq_point_info_var = ins;
2095                 }
2096                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2097                 ins->flags |= MONO_INST_VOLATILE;
2098                 cfg->arch.ss_tramp_var = ins;
2099
2100                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2101                 ins->flags |= MONO_INST_VOLATILE;
2102                 cfg->arch.bp_tramp_var = ins;
2103         }
2104
2105         if (cfg->method->save_lmf)
2106                 cfg->create_lmf_var = TRUE;
2107
2108         if (cfg->method->save_lmf) {
2109                 cfg->lmf_ir = TRUE;
2110 #if !defined(TARGET_WIN32)
2111                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2112                         cfg->lmf_ir_mono_lmf = TRUE;
2113 #endif
2114         }
2115 }
2116
2117 static void
2118 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2119 {
2120         MonoInst *ins;
2121
2122         switch (storage) {
2123         case ArgInIReg:
2124                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2125                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2126                 ins->sreg1 = tree->dreg;
2127                 MONO_ADD_INS (cfg->cbb, ins);
2128                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2129                 break;
2130         case ArgInFloatSSEReg:
2131                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2132                 ins->dreg = mono_alloc_freg (cfg);
2133                 ins->sreg1 = tree->dreg;
2134                 MONO_ADD_INS (cfg->cbb, ins);
2135
2136                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2137                 break;
2138         case ArgInDoubleSSEReg:
2139                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2140                 ins->dreg = mono_alloc_freg (cfg);
2141                 ins->sreg1 = tree->dreg;
2142                 MONO_ADD_INS (cfg->cbb, ins);
2143
2144                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2145
2146                 break;
2147         default:
2148                 g_assert_not_reached ();
2149         }
2150 }
2151
2152 static int
2153 arg_storage_to_load_membase (ArgStorage storage)
2154 {
2155         switch (storage) {
2156         case ArgInIReg:
2157 #if defined(__mono_ilp32__)
2158                 return OP_LOADI8_MEMBASE;
2159 #else
2160                 return OP_LOAD_MEMBASE;
2161 #endif
2162         case ArgInDoubleSSEReg:
2163                 return OP_LOADR8_MEMBASE;
2164         case ArgInFloatSSEReg:
2165                 return OP_LOADR4_MEMBASE;
2166         default:
2167                 g_assert_not_reached ();
2168         }
2169
2170         return -1;
2171 }
2172
2173 static void
2174 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2175 {
2176         MonoMethodSignature *tmp_sig;
2177         int sig_reg;
2178
2179         if (call->tail_call)
2180                 NOT_IMPLEMENTED;
2181
2182         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2183
2184         /*
2185          * mono_ArgIterator_Setup assumes the signature cookie is
2186          * passed first and all the arguments which were before it are
2187          * passed on the stack after the signature. So compensate by
2188          * passing a different signature.
2189          */
2190         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2191         tmp_sig->param_count -= call->signature->sentinelpos;
2192         tmp_sig->sentinelpos = 0;
2193         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2194
2195         sig_reg = mono_alloc_ireg (cfg);
2196         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2197
2198         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2199 }
2200
2201 #ifdef ENABLE_LLVM
2202 static inline LLVMArgStorage
2203 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2204 {
2205         switch (storage) {
2206         case ArgInIReg:
2207                 return LLVMArgInIReg;
2208         case ArgNone:
2209                 return LLVMArgNone;
2210         case ArgGSharedVtInReg:
2211         case ArgGSharedVtOnStack:
2212                 return LLVMArgGSharedVt;
2213         default:
2214                 g_assert_not_reached ();
2215                 return LLVMArgNone;
2216         }
2217 }
2218
2219 LLVMCallInfo*
2220 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2221 {
2222         int i, n;
2223         CallInfo *cinfo;
2224         ArgInfo *ainfo;
2225         int j;
2226         LLVMCallInfo *linfo;
2227         MonoType *t, *sig_ret;
2228
2229         n = sig->param_count + sig->hasthis;
2230         sig_ret = mini_get_underlying_type (sig->ret);
2231
2232         cinfo = get_call_info (cfg->mempool, sig);
2233
2234         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2235
2236         /*
2237          * LLVM always uses the native ABI while we use our own ABI, the
2238          * only difference is the handling of vtypes:
2239          * - we only pass/receive them in registers in some cases, and only
2240          *   in 1 or 2 integer registers.
2241          */
2242         switch (cinfo->ret.storage) {
2243         case ArgNone:
2244                 linfo->ret.storage = LLVMArgNone;
2245                 break;
2246         case ArgInIReg:
2247         case ArgInFloatSSEReg:
2248         case ArgInDoubleSSEReg:
2249                 linfo->ret.storage = LLVMArgNormal;
2250                 break;
2251         case ArgValuetypeInReg:
2252                 if (sig->pinvoke) {
2253                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2254                         cfg->disable_llvm = TRUE;
2255                         return linfo;
2256                 }
2257
2258                 linfo->ret.storage = LLVMArgVtypeInReg;
2259                 for (j = 0; j < 2; ++j)
2260                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2261                 break;
2262         case ArgValuetypeAddrInIReg:
2263                 /* Vtype returned using a hidden argument */
2264                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2265                 linfo->vret_arg_index = cinfo->vret_arg_index;
2266                 break;
2267         default:
2268                 g_assert_not_reached ();
2269                 break;
2270         }
2271
2272         for (i = 0; i < n; ++i) {
2273                 ainfo = cinfo->args + i;
2274
2275                 if (i >= sig->hasthis)
2276                         t = sig->params [i - sig->hasthis];
2277                 else
2278                         t = &mono_defaults.int_class->byval_arg;
2279
2280                 linfo->args [i].storage = LLVMArgNone;
2281
2282                 switch (ainfo->storage) {
2283                 case ArgInIReg:
2284                         linfo->args [i].storage = LLVMArgNormal;
2285                         break;
2286                 case ArgInDoubleSSEReg:
2287                 case ArgInFloatSSEReg:
2288                         linfo->args [i].storage = LLVMArgNormal;
2289                         break;
2290                 case ArgOnStack:
2291                         if (MONO_TYPE_ISSTRUCT (t))
2292                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2293                         else
2294                                 linfo->args [i].storage = LLVMArgNormal;
2295                         break;
2296                 case ArgValuetypeInReg:
2297                         if (sig->pinvoke) {
2298                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2299                                 cfg->disable_llvm = TRUE;
2300                                 return linfo;
2301                         }
2302
2303                         linfo->args [i].storage = LLVMArgVtypeInReg;
2304                         for (j = 0; j < 2; ++j)
2305                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2306                         break;
2307                 case ArgGSharedVtInReg:
2308                 case ArgGSharedVtOnStack:
2309                         linfo->args [i].storage = LLVMArgGSharedVt;
2310                         break;
2311                 default:
2312                         cfg->exception_message = g_strdup ("ainfo->storage");
2313                         cfg->disable_llvm = TRUE;
2314                         break;
2315                 }
2316         }
2317
2318         return linfo;
2319 }
2320 #endif
2321
2322 void
2323 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2324 {
2325         MonoInst *arg, *in;
2326         MonoMethodSignature *sig;
2327         MonoType *sig_ret;
2328         int i, n;
2329         CallInfo *cinfo;
2330         ArgInfo *ainfo;
2331
2332         sig = call->signature;
2333         n = sig->param_count + sig->hasthis;
2334
2335         cinfo = get_call_info (cfg->mempool, sig);
2336
2337         sig_ret = sig->ret;
2338
2339         if (COMPILE_LLVM (cfg)) {
2340                 /* We shouldn't be called in the llvm case */
2341                 cfg->disable_llvm = TRUE;
2342                 return;
2343         }
2344
2345         /*
2346          * Emit all arguments which are passed on the stack to prevent register
2347          * allocation problems.
2348          */
2349         for (i = 0; i < n; ++i) {
2350                 MonoType *t;
2351                 ainfo = cinfo->args + i;
2352
2353                 in = call->args [i];
2354
2355                 if (sig->hasthis && i == 0)
2356                         t = &mono_defaults.object_class->byval_arg;
2357                 else
2358                         t = sig->params [i - sig->hasthis];
2359
2360                 t = mini_get_underlying_type (t);
2361                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2362                         if (!t->byref) {
2363                                 if (t->type == MONO_TYPE_R4)
2364                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2365                                 else if (t->type == MONO_TYPE_R8)
2366                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2367                                 else
2368                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2369                         } else {
2370                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2371                         }
2372                         if (cfg->compute_gc_maps) {
2373                                 MonoInst *def;
2374
2375                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2376                         }
2377                 }
2378         }
2379
2380         /*
2381          * Emit all parameters passed in registers in non-reverse order for better readability
2382          * and to help the optimization in emit_prolog ().
2383          */
2384         for (i = 0; i < n; ++i) {
2385                 ainfo = cinfo->args + i;
2386
2387                 in = call->args [i];
2388
2389                 if (ainfo->storage == ArgInIReg)
2390                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2391         }
2392
2393         for (i = n - 1; i >= 0; --i) {
2394                 MonoType *t;
2395
2396                 ainfo = cinfo->args + i;
2397
2398                 in = call->args [i];
2399
2400                 if (sig->hasthis && i == 0)
2401                         t = &mono_defaults.object_class->byval_arg;
2402                 else
2403                         t = sig->params [i - sig->hasthis];
2404                 t = mini_get_underlying_type (t);
2405
2406                 switch (ainfo->storage) {
2407                 case ArgInIReg:
2408                         /* Already done */
2409                         break;
2410                 case ArgInFloatSSEReg:
2411                 case ArgInDoubleSSEReg:
2412                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2413                         break;
2414                 case ArgOnStack:
2415                 case ArgValuetypeInReg:
2416                 case ArgValuetypeAddrInIReg:
2417                 case ArgGSharedVtInReg:
2418                 case ArgGSharedVtOnStack: {
2419                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2420                                 /* Already emitted above */
2421                                 break;
2422                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2423                                 MonoInst *call_inst = (MonoInst*)call;
2424                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2425                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2426                                 break;
2427                         }
2428
2429                         guint32 align;
2430                         guint32 size;
2431
2432                         if (sig->pinvoke)
2433                                 size = mono_type_native_stack_size (t, &align);
2434                         else {
2435                                 /*
2436                                  * Other backends use mono_type_stack_size (), but that
2437                                  * aligns the size to 8, which is larger than the size of
2438                                  * the source, leading to reads of invalid memory if the
2439                                  * source is at the end of address space.
2440                                  */
2441                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2442                         }
2443
2444                         if (size >= 10000) {
2445                                 /* Avoid asserts in emit_memcpy () */
2446                                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2447                                 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2448                                 /* Continue normally */
2449                         }
2450
2451                         if (size > 0) {
2452                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2453                                 arg->sreg1 = in->dreg;
2454                                 arg->klass = mono_class_from_mono_type (t);
2455                                 arg->backend.size = size;
2456                                 arg->inst_p0 = call;
2457                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2458                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2459
2460                                 MONO_ADD_INS (cfg->cbb, arg);
2461                         }
2462                         break;
2463                 }
2464                 default:
2465                         g_assert_not_reached ();
2466                 }
2467
2468                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2469                         /* Emit the signature cookie just before the implicit arguments */
2470                         emit_sig_cookie (cfg, call, cinfo);
2471         }
2472
2473         /* Handle the case where there are no implicit arguments */
2474         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2475                 emit_sig_cookie (cfg, call, cinfo);
2476
2477         switch (cinfo->ret.storage) {
2478         case ArgValuetypeInReg:
2479                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2480                         /*
2481                          * Tell the JIT to use a more efficient calling convention: call using
2482                          * OP_CALL, compute the result location after the call, and save the
2483                          * result there.
2484                          */
2485                         call->vret_in_reg = TRUE;
2486                         /*
2487                          * Nullify the instruction computing the vret addr to enable
2488                          * future optimizations.
2489                          */
2490                         if (call->vret_var)
2491                                 NULLIFY_INS (call->vret_var);
2492                 } else {
2493                         if (call->tail_call)
2494                                 NOT_IMPLEMENTED;
2495                         /*
2496                          * The valuetype is in RAX:RDX after the call, need to be copied to
2497                          * the stack. Push the address here, so the call instruction can
2498                          * access it.
2499                          */
2500                         if (!cfg->arch.vret_addr_loc) {
2501                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2502                                 /* Prevent it from being register allocated or optimized away */
2503                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2504                         }
2505
2506                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2507                 }
2508                 break;
2509         case ArgValuetypeAddrInIReg: {
2510                 MonoInst *vtarg;
2511                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2512                 vtarg->sreg1 = call->vret_var->dreg;
2513                 vtarg->dreg = mono_alloc_preg (cfg);
2514                 MONO_ADD_INS (cfg->cbb, vtarg);
2515
2516                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2517                 break;
2518         }
2519         default:
2520                 break;
2521         }
2522
2523         if (cfg->method->save_lmf) {
2524                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2525                 MONO_ADD_INS (cfg->cbb, arg);
2526         }
2527
2528         call->stack_usage = cinfo->stack_usage;
2529 }
2530
2531 void
2532 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2533 {
2534         MonoInst *arg;
2535         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2536         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2537         int size = ins->backend.size;
2538
2539         switch (ainfo->storage) {
2540         case ArgValuetypeInReg: {
2541                 MonoInst *load;
2542                 int part;
2543
2544                 for (part = 0; part < 2; ++part) {
2545                         if (ainfo->pair_storage [part] == ArgNone)
2546                                 continue;
2547
2548                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2549                         load->inst_basereg = src->dreg;
2550                         load->inst_offset = part * sizeof(mgreg_t);
2551
2552                         switch (ainfo->pair_storage [part]) {
2553                         case ArgInIReg:
2554                                 load->dreg = mono_alloc_ireg (cfg);
2555                                 break;
2556                         case ArgInDoubleSSEReg:
2557                         case ArgInFloatSSEReg:
2558                                 load->dreg = mono_alloc_freg (cfg);
2559                                 break;
2560                         default:
2561                                 g_assert_not_reached ();
2562                         }
2563                         MONO_ADD_INS (cfg->cbb, load);
2564
2565                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2566                 }
2567                 break;
2568         }
2569         case ArgValuetypeAddrInIReg: {
2570                 MonoInst *vtaddr, *load;
2571                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2572
2573                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2574                 cfg->has_indirection = TRUE;
2575                 load->inst_p0 = vtaddr;
2576                 vtaddr->flags |= MONO_INST_INDIRECT;
2577                 load->type = STACK_MP;
2578                 load->klass = vtaddr->klass;
2579                 load->dreg = mono_alloc_ireg (cfg);
2580                 MONO_ADD_INS (cfg->cbb, load);
2581                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2582
2583                 if (ainfo->pair_storage [0] == ArgInIReg) {
2584                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2585                         arg->dreg = mono_alloc_ireg (cfg);
2586                         arg->sreg1 = load->dreg;
2587                         arg->inst_imm = 0;
2588                         MONO_ADD_INS (cfg->cbb, arg);
2589                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2590                 } else {
2591                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2592                 }
2593                 break;
2594         }
2595         case ArgGSharedVtInReg:
2596                 /* Pass by addr */
2597                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2598                 break;
2599         case ArgGSharedVtOnStack:
2600                 g_assert_not_reached ();
2601                 break;
2602         default:
2603                 if (size == 8) {
2604                         int dreg = mono_alloc_ireg (cfg);
2605
2606                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2607                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2608                 } else if (size <= 40) {
2609                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2610                 } else {
2611                         // FIXME: Code growth
2612                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2613                 }
2614
2615                 if (cfg->compute_gc_maps) {
2616                         MonoInst *def;
2617                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2618                 }
2619         }
2620 }
2621
2622 void
2623 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2624 {
2625         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2626
2627         if (ret->type == MONO_TYPE_R4) {
2628                 if (COMPILE_LLVM (cfg))
2629                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2630                 else
2631                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2632                 return;
2633         } else if (ret->type == MONO_TYPE_R8) {
2634                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2635                 return;
2636         }
2637
2638         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2639 }
2640
2641 #endif /* DISABLE_JIT */
2642
2643 #define EMIT_COND_BRANCH(ins,cond,sign) \
2644         if (ins->inst_true_bb->native_offset) { \
2645                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2646         } else { \
2647                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2648                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2649             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2650                         x86_branch8 (code, cond, 0, sign); \
2651                 else \
2652                         x86_branch32 (code, cond, 0, sign); \
2653 }
2654
2655 typedef struct {
2656         MonoMethodSignature *sig;
2657         CallInfo *cinfo;
2658 } ArchDynCallInfo;
2659
2660 static gboolean
2661 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2662 {
2663         int i;
2664
2665 #ifdef HOST_WIN32
2666         return FALSE;
2667 #endif
2668
2669         switch (cinfo->ret.storage) {
2670         case ArgNone:
2671         case ArgInIReg:
2672                 break;
2673         case ArgValuetypeInReg: {
2674                 ArgInfo *ainfo = &cinfo->ret;
2675
2676                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2677                         return FALSE;
2678                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2679                         return FALSE;
2680                 break;
2681         }
2682         default:
2683                 return FALSE;
2684         }
2685
2686         for (i = 0; i < cinfo->nargs; ++i) {
2687                 ArgInfo *ainfo = &cinfo->args [i];
2688                 switch (ainfo->storage) {
2689                 case ArgInIReg:
2690                         break;
2691                 case ArgValuetypeInReg:
2692                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2693                                 return FALSE;
2694                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2695                                 return FALSE;
2696                         break;
2697                 default:
2698                         return FALSE;
2699                 }
2700         }
2701
2702         return TRUE;
2703 }
2704
2705 /*
2706  * mono_arch_dyn_call_prepare:
2707  *
2708  *   Return a pointer to an arch-specific structure which contains information
2709  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2710  * supported for SIG.
2711  * This function is equivalent to ffi_prep_cif in libffi.
2712  */
2713 MonoDynCallInfo*
2714 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2715 {
2716         ArchDynCallInfo *info;
2717         CallInfo *cinfo;
2718
2719         cinfo = get_call_info (NULL, sig);
2720
2721         if (!dyn_call_supported (sig, cinfo)) {
2722                 g_free (cinfo);
2723                 return NULL;
2724         }
2725
2726         info = g_new0 (ArchDynCallInfo, 1);
2727         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2728         info->sig = sig;
2729         info->cinfo = cinfo;
2730
2731         return (MonoDynCallInfo*)info;
2732 }
2733
2734 /*
2735  * mono_arch_dyn_call_free:
2736  *
2737  *   Free a MonoDynCallInfo structure.
2738  */
2739 void
2740 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2741 {
2742         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2743
2744         g_free (ainfo->cinfo);
2745         g_free (ainfo);
2746 }
2747
2748 #if !defined(__native_client__)
2749 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2750 #define GREG_TO_PTR(greg) (gpointer)(greg)
2751 #else
2752 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2753 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2754 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2755 #endif
2756
2757 /*
2758  * mono_arch_get_start_dyn_call:
2759  *
2760  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2761  * store the result into BUF.
2762  * ARGS should be an array of pointers pointing to the arguments.
2763  * RET should point to a memory buffer large enought to hold the result of the
2764  * call.
2765  * This function should be as fast as possible, any work which does not depend
2766  * on the actual values of the arguments should be done in
2767  * mono_arch_dyn_call_prepare ().
2768  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2769  * libffi.
2770  */
2771 void
2772 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2773 {
2774         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2775         DynCallArgs *p = (DynCallArgs*)buf;
2776         int arg_index, greg, i, pindex;
2777         MonoMethodSignature *sig = dinfo->sig;
2778
2779         g_assert (buf_len >= sizeof (DynCallArgs));
2780
2781         p->res = 0;
2782         p->ret = ret;
2783
2784         arg_index = 0;
2785         greg = 0;
2786         pindex = 0;
2787
2788         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2789                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2790                 if (!sig->hasthis)
2791                         pindex = 1;
2792         }
2793
2794         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg)
2795                 p->regs [greg ++] = PTR_TO_GREG(ret);
2796
2797         for (i = pindex; i < sig->param_count; i++) {
2798                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2799                 gpointer *arg = args [arg_index ++];
2800
2801                 if (t->byref) {
2802                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2803                         continue;
2804                 }
2805
2806                 switch (t->type) {
2807                 case MONO_TYPE_STRING:
2808                 case MONO_TYPE_CLASS:
2809                 case MONO_TYPE_ARRAY:
2810                 case MONO_TYPE_SZARRAY:
2811                 case MONO_TYPE_OBJECT:
2812                 case MONO_TYPE_PTR:
2813                 case MONO_TYPE_I:
2814                 case MONO_TYPE_U:
2815 #if !defined(__mono_ilp32__)
2816                 case MONO_TYPE_I8:
2817                 case MONO_TYPE_U8:
2818 #endif
2819                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2820                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2821                         break;
2822 #if defined(__mono_ilp32__)
2823                 case MONO_TYPE_I8:
2824                 case MONO_TYPE_U8:
2825                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2826                         p->regs [greg ++] = *(guint64*)(arg);
2827                         break;
2828 #endif
2829                 case MONO_TYPE_U1:
2830                         p->regs [greg ++] = *(guint8*)(arg);
2831                         break;
2832                 case MONO_TYPE_I1:
2833                         p->regs [greg ++] = *(gint8*)(arg);
2834                         break;
2835                 case MONO_TYPE_I2:
2836                         p->regs [greg ++] = *(gint16*)(arg);
2837                         break;
2838                 case MONO_TYPE_U2:
2839                         p->regs [greg ++] = *(guint16*)(arg);
2840                         break;
2841                 case MONO_TYPE_I4:
2842                         p->regs [greg ++] = *(gint32*)(arg);
2843                         break;
2844                 case MONO_TYPE_U4:
2845                         p->regs [greg ++] = *(guint32*)(arg);
2846                         break;
2847                 case MONO_TYPE_GENERICINST:
2848                     if (MONO_TYPE_IS_REFERENCE (t)) {
2849                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2850                                 break;
2851                         } else {
2852                                 /* Fall through */
2853                         }
2854                 case MONO_TYPE_VALUETYPE: {
2855                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2856
2857                         g_assert (ainfo->storage == ArgValuetypeInReg);
2858                         if (ainfo->pair_storage [0] != ArgNone) {
2859                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2860                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2861                         }
2862                         if (ainfo->pair_storage [1] != ArgNone) {
2863                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2864                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2865                         }
2866                         break;
2867                 }
2868                 default:
2869                         g_assert_not_reached ();
2870                 }
2871         }
2872
2873         g_assert (greg <= PARAM_REGS);
2874 }
2875
2876 /*
2877  * mono_arch_finish_dyn_call:
2878  *
2879  *   Store the result of a dyn call into the return value buffer passed to
2880  * start_dyn_call ().
2881  * This function should be as fast as possible, any work which does not depend
2882  * on the actual values of the arguments should be done in
2883  * mono_arch_dyn_call_prepare ().
2884  */
2885 void
2886 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2887 {
2888         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2889         MonoMethodSignature *sig = dinfo->sig;
2890         guint8 *ret = ((DynCallArgs*)buf)->ret;
2891         mgreg_t res = ((DynCallArgs*)buf)->res;
2892         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2893
2894         switch (sig_ret->type) {
2895         case MONO_TYPE_VOID:
2896                 *(gpointer*)ret = NULL;
2897                 break;
2898         case MONO_TYPE_STRING:
2899         case MONO_TYPE_CLASS:
2900         case MONO_TYPE_ARRAY:
2901         case MONO_TYPE_SZARRAY:
2902         case MONO_TYPE_OBJECT:
2903         case MONO_TYPE_I:
2904         case MONO_TYPE_U:
2905         case MONO_TYPE_PTR:
2906                 *(gpointer*)ret = GREG_TO_PTR(res);
2907                 break;
2908         case MONO_TYPE_I1:
2909                 *(gint8*)ret = res;
2910                 break;
2911         case MONO_TYPE_U1:
2912                 *(guint8*)ret = res;
2913                 break;
2914         case MONO_TYPE_I2:
2915                 *(gint16*)ret = res;
2916                 break;
2917         case MONO_TYPE_U2:
2918                 *(guint16*)ret = res;
2919                 break;
2920         case MONO_TYPE_I4:
2921                 *(gint32*)ret = res;
2922                 break;
2923         case MONO_TYPE_U4:
2924                 *(guint32*)ret = res;
2925                 break;
2926         case MONO_TYPE_I8:
2927                 *(gint64*)ret = res;
2928                 break;
2929         case MONO_TYPE_U8:
2930                 *(guint64*)ret = res;
2931                 break;
2932         case MONO_TYPE_GENERICINST:
2933                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2934                         *(gpointer*)ret = GREG_TO_PTR(res);
2935                         break;
2936                 } else {
2937                         /* Fall through */
2938                 }
2939         case MONO_TYPE_VALUETYPE:
2940                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2941                         /* Nothing to do */
2942                 } else {
2943                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2944
2945                         g_assert (ainfo->storage == ArgValuetypeInReg);
2946
2947                         if (ainfo->pair_storage [0] != ArgNone) {
2948                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2949                                 ((mgreg_t*)ret)[0] = res;
2950                         }
2951
2952                         g_assert (ainfo->pair_storage [1] == ArgNone);
2953                 }
2954                 break;
2955         default:
2956                 g_assert_not_reached ();
2957         }
2958 }
2959
2960 /* emit an exception if condition is fail */
2961 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2962         do {                                                        \
2963                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2964                 if (tins == NULL) {                                                                             \
2965                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2966                                         MONO_PATCH_INFO_EXC, exc_name);  \
2967                         x86_branch32 (code, cond, 0, signed);               \
2968                 } else {        \
2969                         EMIT_COND_BRANCH (tins, cond, signed);  \
2970                 }                       \
2971         } while (0);
2972
2973 #define EMIT_FPCOMPARE(code) do { \
2974         amd64_fcompp (code); \
2975         amd64_fnstsw (code); \
2976 } while (0);
2977
2978 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2979     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2980         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2981         amd64_ ##op (code); \
2982         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2983         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2984 } while (0);
2985
2986 static guint8*
2987 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2988 {
2989         gboolean no_patch = FALSE;
2990
2991         /*
2992          * FIXME: Add support for thunks
2993          */
2994         {
2995                 gboolean near_call = FALSE;
2996
2997                 /*
2998                  * Indirect calls are expensive so try to make a near call if possible.
2999                  * The caller memory is allocated by the code manager so it is
3000                  * guaranteed to be at a 32 bit offset.
3001                  */
3002
3003                 if (patch_type != MONO_PATCH_INFO_ABS) {
3004                         /* The target is in memory allocated using the code manager */
3005                         near_call = TRUE;
3006
3007                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3008                                 if (((MonoMethod*)data)->klass->image->aot_module)
3009                                         /* The callee might be an AOT method */
3010                                         near_call = FALSE;
3011                                 if (((MonoMethod*)data)->dynamic)
3012                                         /* The target is in malloc-ed memory */
3013                                         near_call = FALSE;
3014                         }
3015
3016                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3017                                 /*
3018                                  * The call might go directly to a native function without
3019                                  * the wrapper.
3020                                  */
3021                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
3022                                 if (mi) {
3023                                         gconstpointer target = mono_icall_get_wrapper (mi);
3024                                         if ((((guint64)target) >> 32) != 0)
3025                                                 near_call = FALSE;
3026                                 }
3027                         }
3028                 }
3029                 else {
3030                         MonoJumpInfo *jinfo = NULL;
3031
3032                         if (cfg->abs_patches)
3033                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
3034                         if (jinfo) {
3035                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3036                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3037                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3038                                                 near_call = TRUE;
3039                                         no_patch = TRUE;
3040                                 } else {
3041                                         /*
3042                                          * This is not really an optimization, but required because the
3043                                          * generic class init trampolines use R11 to pass the vtable.
3044                                          */
3045                                         near_call = TRUE;
3046                                 }
3047                         } else {
3048                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3049                                 if (info) {
3050                                         if (info->func == info->wrapper) {
3051                                                 /* No wrapper */
3052                                                 if ((((guint64)info->func) >> 32) == 0)
3053                                                         near_call = TRUE;
3054                                         }
3055                                         else {
3056                                                 /* See the comment in mono_codegen () */
3057                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3058                                                         near_call = TRUE;
3059                                         }
3060                                 }
3061                                 else if ((((guint64)data) >> 32) == 0) {
3062                                         near_call = TRUE;
3063                                         no_patch = TRUE;
3064                                 }
3065                         }
3066                 }
3067
3068                 if (cfg->method->dynamic)
3069                         /* These methods are allocated using malloc */
3070                         near_call = FALSE;
3071
3072 #ifdef MONO_ARCH_NOMAP32BIT
3073                 near_call = FALSE;
3074 #endif
3075 #if defined(__native_client__)
3076                 /* Always use near_call == TRUE for Native Client */
3077                 near_call = TRUE;
3078 #endif
3079                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3080                 if (optimize_for_xen)
3081                         near_call = FALSE;
3082
3083                 if (cfg->compile_aot) {
3084                         near_call = TRUE;
3085                         no_patch = TRUE;
3086                 }
3087
3088                 if (near_call) {
3089                         /*
3090                          * Align the call displacement to an address divisible by 4 so it does
3091                          * not span cache lines. This is required for code patching to work on SMP
3092                          * systems.
3093                          */
3094                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3095                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3096                                 amd64_padding (code, pad_size);
3097                         }
3098                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3099                         amd64_call_code (code, 0);
3100                 }
3101                 else {
3102                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3103                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3104                         amd64_call_reg (code, GP_SCRATCH_REG);
3105                 }
3106         }
3107
3108         return code;
3109 }
3110
3111 static inline guint8*
3112 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3113 {
3114 #ifdef TARGET_WIN32
3115         if (win64_adjust_stack)
3116                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3117 #endif
3118         code = emit_call_body (cfg, code, patch_type, data);
3119 #ifdef TARGET_WIN32
3120         if (win64_adjust_stack)
3121                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3122 #endif
3123
3124         return code;
3125 }
3126
3127 static inline int
3128 store_membase_imm_to_store_membase_reg (int opcode)
3129 {
3130         switch (opcode) {
3131         case OP_STORE_MEMBASE_IMM:
3132                 return OP_STORE_MEMBASE_REG;
3133         case OP_STOREI4_MEMBASE_IMM:
3134                 return OP_STOREI4_MEMBASE_REG;
3135         case OP_STOREI8_MEMBASE_IMM:
3136                 return OP_STOREI8_MEMBASE_REG;
3137         }
3138
3139         return -1;
3140 }
3141
3142 #ifndef DISABLE_JIT
3143
3144 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3145
3146 /*
3147  * mono_arch_peephole_pass_1:
3148  *
3149  *   Perform peephole opts which should/can be performed before local regalloc
3150  */
3151 void
3152 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3153 {
3154         MonoInst *ins, *n;
3155
3156         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3157                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3158
3159                 switch (ins->opcode) {
3160                 case OP_ADD_IMM:
3161                 case OP_IADD_IMM:
3162                 case OP_LADD_IMM:
3163                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3164                                 /*
3165                                  * X86_LEA is like ADD, but doesn't have the
3166                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3167                                  * its operand to 64 bit.
3168                                  */
3169                                 ins->opcode = OP_X86_LEA_MEMBASE;
3170                                 ins->inst_basereg = ins->sreg1;
3171                         }
3172                         break;
3173                 case OP_LXOR:
3174                 case OP_IXOR:
3175                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3176                                 MonoInst *ins2;
3177
3178                                 /*
3179                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3180                                  * the latter has length 2-3 instead of 6 (reverse constant
3181                                  * propagation). These instruction sequences are very common
3182                                  * in the initlocals bblock.
3183                                  */
3184                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3185                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3186                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3187                                                 ins2->sreg1 = ins->dreg;
3188                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3189                                                 /* Continue */
3190                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3191                                                 NULLIFY_INS (ins2);
3192                                                 /* Continue */
3193                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3194                                                 /* Continue */
3195                                         } else {
3196                                                 break;
3197                                         }
3198                                 }
3199                         }
3200                         break;
3201                 case OP_COMPARE_IMM:
3202                 case OP_LCOMPARE_IMM:
3203                         /* OP_COMPARE_IMM (reg, 0)
3204                          * -->
3205                          * OP_AMD64_TEST_NULL (reg)
3206                          */
3207                         if (!ins->inst_imm)
3208                                 ins->opcode = OP_AMD64_TEST_NULL;
3209                         break;
3210                 case OP_ICOMPARE_IMM:
3211                         if (!ins->inst_imm)
3212                                 ins->opcode = OP_X86_TEST_NULL;
3213                         break;
3214                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3215                         /*
3216                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3217                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3218                          * -->
3219                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3220                          * OP_COMPARE_IMM reg, imm
3221                          *
3222                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3223                          */
3224                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3225                             ins->inst_basereg == last_ins->inst_destbasereg &&
3226                             ins->inst_offset == last_ins->inst_offset) {
3227                                         ins->opcode = OP_ICOMPARE_IMM;
3228                                         ins->sreg1 = last_ins->sreg1;
3229
3230                                         /* check if we can remove cmp reg,0 with test null */
3231                                         if (!ins->inst_imm)
3232                                                 ins->opcode = OP_X86_TEST_NULL;
3233                                 }
3234
3235                         break;
3236                 }
3237
3238                 mono_peephole_ins (bb, ins);
3239         }
3240 }
3241
3242 void
3243 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3244 {
3245         MonoInst *ins, *n;
3246
3247         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3248                 switch (ins->opcode) {
3249                 case OP_ICONST:
3250                 case OP_I8CONST: {
3251                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3252                         /* reg = 0 -> XOR (reg, reg) */
3253                         /* XOR sets cflags on x86, so we cant do it always */
3254                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3255                                 ins->opcode = OP_LXOR;
3256                                 ins->sreg1 = ins->dreg;
3257                                 ins->sreg2 = ins->dreg;
3258                                 /* Fall through */
3259                         } else {
3260                                 break;
3261                         }
3262                 }
3263                 case OP_LXOR:
3264                         /*
3265                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3266                          * 0 result into 64 bits.
3267                          */
3268                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3269                                 ins->opcode = OP_IXOR;
3270                         }
3271                         /* Fall through */
3272                 case OP_IXOR:
3273                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3274                                 MonoInst *ins2;
3275
3276                                 /*
3277                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3278                                  * the latter has length 2-3 instead of 6 (reverse constant
3279                                  * propagation). These instruction sequences are very common
3280                                  * in the initlocals bblock.
3281                                  */
3282                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3283                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3284                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3285                                                 ins2->sreg1 = ins->dreg;
3286                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3287                                                 /* Continue */
3288                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3289                                                 NULLIFY_INS (ins2);
3290                                                 /* Continue */
3291                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3292                                                 /* Continue */
3293                                         } else {
3294                                                 break;
3295                                         }
3296                                 }
3297                         }
3298                         break;
3299                 case OP_IADD_IMM:
3300                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3301                                 ins->opcode = OP_X86_INC_REG;
3302                         break;
3303                 case OP_ISUB_IMM:
3304                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3305                                 ins->opcode = OP_X86_DEC_REG;
3306                         break;
3307                 }
3308
3309                 mono_peephole_ins (bb, ins);
3310         }
3311 }
3312
3313 #define NEW_INS(cfg,ins,dest,op) do {   \
3314                 MONO_INST_NEW ((cfg), (dest), (op)); \
3315         (dest)->cil_code = (ins)->cil_code; \
3316         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3317         } while (0)
3318
3319 /*
3320  * mono_arch_lowering_pass:
3321  *
3322  *  Converts complex opcodes into simpler ones so that each IR instruction
3323  * corresponds to one machine instruction.
3324  */
3325 void
3326 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3327 {
3328         MonoInst *ins, *n, *temp;
3329
3330         /*
3331          * FIXME: Need to add more instructions, but the current machine
3332          * description can't model some parts of the composite instructions like
3333          * cdq.
3334          */
3335         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3336                 switch (ins->opcode) {
3337                 case OP_DIV_IMM:
3338                 case OP_REM_IMM:
3339                 case OP_IDIV_IMM:
3340                 case OP_IDIV_UN_IMM:
3341                 case OP_IREM_UN_IMM:
3342                 case OP_LREM_IMM:
3343                 case OP_IREM_IMM:
3344                         mono_decompose_op_imm (cfg, bb, ins);
3345                         break;
3346                 case OP_COMPARE_IMM:
3347                 case OP_LCOMPARE_IMM:
3348                         if (!amd64_use_imm32 (ins->inst_imm)) {
3349                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3350                                 temp->inst_c0 = ins->inst_imm;
3351                                 temp->dreg = mono_alloc_ireg (cfg);
3352                                 ins->opcode = OP_COMPARE;
3353                                 ins->sreg2 = temp->dreg;
3354                         }
3355                         break;
3356 #ifndef __mono_ilp32__
3357                 case OP_LOAD_MEMBASE:
3358 #endif
3359                 case OP_LOADI8_MEMBASE:
3360 #ifndef __native_client_codegen__
3361                 /*  Don't generate memindex opcodes (to simplify */
3362                 /*  read sandboxing) */
3363                         if (!amd64_use_imm32 (ins->inst_offset)) {
3364                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3365                                 temp->inst_c0 = ins->inst_offset;
3366                                 temp->dreg = mono_alloc_ireg (cfg);
3367                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3368                                 ins->inst_indexreg = temp->dreg;
3369                         }
3370 #endif
3371                         break;
3372 #ifndef __mono_ilp32__
3373                 case OP_STORE_MEMBASE_IMM:
3374 #endif
3375                 case OP_STOREI8_MEMBASE_IMM:
3376                         if (!amd64_use_imm32 (ins->inst_imm)) {
3377                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3378                                 temp->inst_c0 = ins->inst_imm;
3379                                 temp->dreg = mono_alloc_ireg (cfg);
3380                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3381                                 ins->sreg1 = temp->dreg;
3382                         }
3383                         break;
3384 #ifdef MONO_ARCH_SIMD_INTRINSICS
3385                 case OP_EXPAND_I1: {
3386                                 int temp_reg1 = mono_alloc_ireg (cfg);
3387                                 int temp_reg2 = mono_alloc_ireg (cfg);
3388                                 int original_reg = ins->sreg1;
3389
3390                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3391                                 temp->sreg1 = original_reg;
3392                                 temp->dreg = temp_reg1;
3393
3394                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3395                                 temp->sreg1 = temp_reg1;
3396                                 temp->dreg = temp_reg2;
3397                                 temp->inst_imm = 8;
3398
3399                                 NEW_INS (cfg, ins, temp, OP_LOR);
3400                                 temp->sreg1 = temp->dreg = temp_reg2;
3401                                 temp->sreg2 = temp_reg1;
3402
3403                                 ins->opcode = OP_EXPAND_I2;
3404                                 ins->sreg1 = temp_reg2;
3405                         }
3406                         break;
3407 #endif
3408                 default:
3409                         break;
3410                 }
3411         }
3412
3413         bb->max_vreg = cfg->next_vreg;
3414 }
3415
3416 static const int
3417 branch_cc_table [] = {
3418         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3419         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3420         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3421 };
3422
3423 /* Maps CMP_... constants to X86_CC_... constants */
3424 static const int
3425 cc_table [] = {
3426         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3427         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3428 };
3429
3430 static const int
3431 cc_signed_table [] = {
3432         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3433         FALSE, FALSE, FALSE, FALSE
3434 };
3435
3436 /*#include "cprop.c"*/
3437
3438 static unsigned char*
3439 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3440 {
3441         if (size == 8)
3442                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3443         else
3444                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3445
3446         if (size == 1)
3447                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3448         else if (size == 2)
3449                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3450         return code;
3451 }
3452
3453 static unsigned char*
3454 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3455 {
3456         int sreg = tree->sreg1;
3457         int need_touch = FALSE;
3458
3459 #if defined(TARGET_WIN32)
3460         need_touch = TRUE;
3461 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3462         if (!tree->flags & MONO_INST_INIT)
3463                 need_touch = TRUE;
3464 #endif
3465
3466         if (need_touch) {
3467                 guint8* br[5];
3468
3469                 /*
3470                  * Under Windows:
3471                  * If requested stack size is larger than one page,
3472                  * perform stack-touch operation
3473                  */
3474                 /*
3475                  * Generate stack probe code.
3476                  * Under Windows, it is necessary to allocate one page at a time,
3477                  * "touching" stack after each successful sub-allocation. This is
3478                  * because of the way stack growth is implemented - there is a
3479                  * guard page before the lowest stack page that is currently commited.
3480                  * Stack normally grows sequentially so OS traps access to the
3481                  * guard page and commits more pages when needed.
3482                  */
3483                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3484                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3485
3486                 br[2] = code; /* loop */
3487                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3488                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3489                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3490                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3491                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3492                 amd64_patch (br[3], br[2]);
3493                 amd64_test_reg_reg (code, sreg, sreg);
3494                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3495                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3496
3497                 br[1] = code; x86_jump8 (code, 0);
3498
3499                 amd64_patch (br[0], code);
3500                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3501                 amd64_patch (br[1], code);
3502                 amd64_patch (br[4], code);
3503         }
3504         else
3505                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3506
3507         if (tree->flags & MONO_INST_INIT) {
3508                 int offset = 0;
3509                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3510                         amd64_push_reg (code, AMD64_RAX);
3511                         offset += 8;
3512                 }
3513                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3514                         amd64_push_reg (code, AMD64_RCX);
3515                         offset += 8;
3516                 }
3517                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3518                         amd64_push_reg (code, AMD64_RDI);
3519                         offset += 8;
3520                 }
3521
3522                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3523                 if (sreg != AMD64_RCX)
3524                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3525                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3526
3527                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3528                 if (cfg->param_area)
3529                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3530                 amd64_cld (code);
3531 #if defined(__default_codegen__)
3532                 amd64_prefix (code, X86_REP_PREFIX);
3533                 amd64_stosl (code);
3534 #elif defined(__native_client_codegen__)
3535                 /* NaCl stos pseudo-instruction */
3536                 amd64_codegen_pre(code);
3537                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3538                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3539                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3540                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3541                 amd64_prefix (code, X86_REP_PREFIX);
3542                 amd64_stosl (code);
3543                 amd64_codegen_post(code);
3544 #endif /* __native_client_codegen__ */
3545
3546                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3547                         amd64_pop_reg (code, AMD64_RDI);
3548                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3549                         amd64_pop_reg (code, AMD64_RCX);
3550                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3551                         amd64_pop_reg (code, AMD64_RAX);
3552         }
3553         return code;
3554 }
3555
3556 static guint8*
3557 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3558 {
3559         CallInfo *cinfo;
3560         guint32 quad;
3561
3562         /* Move return value to the target register */
3563         /* FIXME: do this in the local reg allocator */
3564         switch (ins->opcode) {
3565         case OP_CALL:
3566         case OP_CALL_REG:
3567         case OP_CALL_MEMBASE:
3568         case OP_LCALL:
3569         case OP_LCALL_REG:
3570         case OP_LCALL_MEMBASE:
3571                 g_assert (ins->dreg == AMD64_RAX);
3572                 break;
3573         case OP_FCALL:
3574         case OP_FCALL_REG:
3575         case OP_FCALL_MEMBASE: {
3576                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3577                 if (rtype->type == MONO_TYPE_R4) {
3578                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3579                 }
3580                 else {
3581                         if (ins->dreg != AMD64_XMM0)
3582                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3583                 }
3584                 break;
3585         }
3586         case OP_RCALL:
3587         case OP_RCALL_REG:
3588         case OP_RCALL_MEMBASE:
3589                 if (ins->dreg != AMD64_XMM0)
3590                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3591                 break;
3592         case OP_VCALL:
3593         case OP_VCALL_REG:
3594         case OP_VCALL_MEMBASE:
3595         case OP_VCALL2:
3596         case OP_VCALL2_REG:
3597         case OP_VCALL2_MEMBASE:
3598                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3599                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3600                         MonoInst *loc = cfg->arch.vret_addr_loc;
3601
3602                         /* Load the destination address */
3603                         g_assert (loc->opcode == OP_REGOFFSET);
3604                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3605
3606                         for (quad = 0; quad < 2; quad ++) {
3607                                 switch (cinfo->ret.pair_storage [quad]) {
3608                                 case ArgInIReg:
3609                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3610                                         break;
3611                                 case ArgInFloatSSEReg:
3612                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3613                                         break;
3614                                 case ArgInDoubleSSEReg:
3615                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3616                                         break;
3617                                 case ArgNone:
3618                                         break;
3619                                 default:
3620                                         NOT_IMPLEMENTED;
3621                                 }
3622                         }
3623                 }
3624                 break;
3625         }
3626
3627         return code;
3628 }
3629
3630 #endif /* DISABLE_JIT */
3631
3632 #ifdef __APPLE__
3633 static int tls_gs_offset;
3634 #endif
3635
3636 gboolean
3637 mono_amd64_have_tls_get (void)
3638 {
3639 #ifdef TARGET_MACH
3640         static gboolean have_tls_get = FALSE;
3641         static gboolean inited = FALSE;
3642
3643         if (inited)
3644                 return have_tls_get;
3645
3646 #if MONO_HAVE_FAST_TLS
3647         guint8 *ins = (guint8*)pthread_getspecific;
3648
3649         /*
3650          * We're looking for these two instructions:
3651          *
3652          * mov    %gs:[offset](,%rdi,8),%rax
3653          * retq
3654          */
3655         have_tls_get = ins [0] == 0x65 &&
3656                        ins [1] == 0x48 &&
3657                        ins [2] == 0x8b &&
3658                        ins [3] == 0x04 &&
3659                        ins [4] == 0xfd &&
3660                        ins [6] == 0x00 &&
3661                        ins [7] == 0x00 &&
3662                        ins [8] == 0x00 &&
3663                        ins [9] == 0xc3;
3664
3665         tls_gs_offset = ins[5];
3666
3667         /*
3668          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3669          * For that version we're looking for these instructions:
3670          *
3671          * pushq  %rbp
3672          * movq   %rsp, %rbp
3673          * mov    %gs:[offset](,%rdi,8),%rax
3674          * popq   %rbp
3675          * retq
3676          */
3677         if (!have_tls_get) {
3678                 have_tls_get = ins [0] == 0x55 &&
3679                                ins [1] == 0x48 &&
3680                                ins [2] == 0x89 &&
3681                                ins [3] == 0xe5 &&
3682                                ins [4] == 0x65 &&
3683                                ins [5] == 0x48 &&
3684                                ins [6] == 0x8b &&
3685                                ins [7] == 0x04 &&
3686                                ins [8] == 0xfd &&
3687                                ins [10] == 0x00 &&
3688                                ins [11] == 0x00 &&
3689                                ins [12] == 0x00 &&
3690                                ins [13] == 0x5d &&
3691                                ins [14] == 0xc3;
3692
3693                 tls_gs_offset = ins[9];
3694         }
3695 #endif
3696
3697         inited = TRUE;
3698
3699         return have_tls_get;
3700 #elif defined(TARGET_ANDROID)
3701         return FALSE;
3702 #else
3703         return TRUE;
3704 #endif
3705 }
3706
3707 int
3708 mono_amd64_get_tls_gs_offset (void)
3709 {
3710 #ifdef TARGET_OSX
3711         return tls_gs_offset;
3712 #else
3713         g_assert_not_reached ();
3714         return -1;
3715 #endif
3716 }
3717
3718 /*
3719  * mono_amd64_emit_tls_get:
3720  * @code: buffer to store code to
3721  * @dreg: hard register where to place the result
3722  * @tls_offset: offset info
3723  *
3724  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3725  * the dreg register the item in the thread local storage identified
3726  * by tls_offset.
3727  *
3728  * Returns: a pointer to the end of the stored code
3729  */
3730 guint8*
3731 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3732 {
3733 #ifdef TARGET_WIN32
3734         if (tls_offset < 64) {
3735                 x86_prefix (code, X86_GS_PREFIX);
3736                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3737         } else {
3738                 guint8 *buf [16];
3739
3740                 g_assert (tls_offset < 0x440);
3741                 /* Load TEB->TlsExpansionSlots */
3742                 x86_prefix (code, X86_GS_PREFIX);
3743                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3744                 amd64_test_reg_reg (code, dreg, dreg);
3745                 buf [0] = code;
3746                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3747                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3748                 amd64_patch (buf [0], code);
3749         }
3750 #elif defined(__APPLE__)
3751         x86_prefix (code, X86_GS_PREFIX);
3752         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3753 #else
3754         if (optimize_for_xen) {
3755                 x86_prefix (code, X86_FS_PREFIX);
3756                 amd64_mov_reg_mem (code, dreg, 0, 8);
3757                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3758         } else {
3759                 x86_prefix (code, X86_FS_PREFIX);
3760                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3761         }
3762 #endif
3763         return code;
3764 }
3765
3766 static guint8*
3767 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3768 {
3769         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3770 #ifdef TARGET_OSX
3771         if (dreg != offset_reg)
3772                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3773         amd64_prefix (code, X86_GS_PREFIX);
3774         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3775 #elif defined(__linux__)
3776         int tmpreg = -1;
3777
3778         if (dreg == offset_reg) {
3779                 /* Use a temporary reg by saving it to the redzone */
3780                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3781                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3782                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3783                 offset_reg = tmpreg;
3784         }
3785         x86_prefix (code, X86_FS_PREFIX);
3786         amd64_mov_reg_mem (code, dreg, 0, 8);
3787         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3788         if (tmpreg != -1)
3789                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3790 #else
3791         g_assert_not_reached ();
3792 #endif
3793         return code;
3794 }
3795
3796 static guint8*
3797 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3798 {
3799 #ifdef TARGET_WIN32
3800         g_assert_not_reached ();
3801 #elif defined(__APPLE__)
3802         x86_prefix (code, X86_GS_PREFIX);
3803         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3804 #else
3805         g_assert (!optimize_for_xen);
3806         x86_prefix (code, X86_FS_PREFIX);
3807         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3808 #endif
3809         return code;
3810 }
3811
3812 static guint8*
3813 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3814 {
3815         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3816 #ifdef TARGET_WIN32
3817         g_assert_not_reached ();
3818 #elif defined(__APPLE__)
3819         x86_prefix (code, X86_GS_PREFIX);
3820         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3821 #else
3822         x86_prefix (code, X86_FS_PREFIX);
3823         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3824 #endif
3825         return code;
3826 }
3827
3828  /*
3829  * mono_arch_translate_tls_offset:
3830  *
3831  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3832  */
3833 int
3834 mono_arch_translate_tls_offset (int offset)
3835 {
3836 #ifdef __APPLE__
3837         return tls_gs_offset + (offset * 8);
3838 #else
3839         return offset;
3840 #endif
3841 }
3842
3843 /*
3844  * emit_setup_lmf:
3845  *
3846  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3847  */
3848 static guint8*
3849 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3850 {
3851         /*
3852          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3853          */
3854         /*
3855          * sp is saved right before calls but we need to save it here too so
3856          * async stack walks would work.
3857          */
3858         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3859         /* Save rbp */
3860         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3861         if (cfg->arch.omit_fp && cfa_offset != -1)
3862                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3863
3864         /* These can't contain refs */
3865         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3866         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3867         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3868         /* These are handled automatically by the stack marking code */
3869         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3870
3871         return code;
3872 }
3873
3874 #define REAL_PRINT_REG(text,reg) \
3875 mono_assert (reg >= 0); \
3876 amd64_push_reg (code, AMD64_RAX); \
3877 amd64_push_reg (code, AMD64_RDX); \
3878 amd64_push_reg (code, AMD64_RCX); \
3879 amd64_push_reg (code, reg); \
3880 amd64_push_imm (code, reg); \
3881 amd64_push_imm (code, text " %d %p\n"); \
3882 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3883 amd64_call_reg (code, AMD64_RAX); \
3884 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3885 amd64_pop_reg (code, AMD64_RCX); \
3886 amd64_pop_reg (code, AMD64_RDX); \
3887 amd64_pop_reg (code, AMD64_RAX);
3888
3889 /* benchmark and set based on cpu */
3890 #define LOOP_ALIGNMENT 8
3891 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3892
3893 #ifndef DISABLE_JIT
3894 void
3895 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3896 {
3897         MonoInst *ins;
3898         MonoCallInst *call;
3899         guint offset;
3900         guint8 *code = cfg->native_code + cfg->code_len;
3901         int max_len;
3902
3903         /* Fix max_offset estimate for each successor bb */
3904         if (cfg->opt & MONO_OPT_BRANCH) {
3905                 int current_offset = cfg->code_len;
3906                 MonoBasicBlock *current_bb;
3907                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3908                         current_bb->max_offset = current_offset;
3909                         current_offset += current_bb->max_length;
3910                 }
3911         }
3912
3913         if (cfg->opt & MONO_OPT_LOOP) {
3914                 int pad, align = LOOP_ALIGNMENT;
3915                 /* set alignment depending on cpu */
3916                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3917                         pad = align - pad;
3918                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3919                         amd64_padding (code, pad);
3920                         cfg->code_len += pad;
3921                         bb->native_offset = cfg->code_len;
3922                 }
3923         }
3924
3925 #if defined(__native_client_codegen__)
3926         /* For Native Client, all indirect call/jump targets must be */
3927         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3928         /* indirectly as well.                                       */
3929         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3930                                       (bb->flags & BB_EXCEPTION_HANDLER);
3931
3932         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3933                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3934                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3935                 cfg->code_len += pad;
3936                 bb->native_offset = cfg->code_len;
3937         }
3938 #endif  /*__native_client_codegen__*/
3939
3940         if (cfg->verbose_level > 2)
3941                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3942
3943         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3944                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3945                 g_assert (!cfg->compile_aot);
3946
3947                 cov->data [bb->dfn].cil_code = bb->cil_code;
3948                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3949                 /* this is not thread save, but good enough */
3950                 amd64_inc_membase (code, AMD64_R11, 0);
3951         }
3952
3953         offset = code - cfg->native_code;
3954
3955         mono_debug_open_block (cfg, bb, offset);
3956
3957     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3958                 x86_breakpoint (code);
3959
3960         MONO_BB_FOR_EACH_INS (bb, ins) {
3961                 offset = code - cfg->native_code;
3962
3963                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3964
3965 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3966
3967                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3968                         cfg->code_size *= 2;
3969                         cfg->native_code = mono_realloc_native_code(cfg);
3970                         code = cfg->native_code + offset;
3971                         cfg->stat_code_reallocs++;
3972                 }
3973
3974                 if (cfg->debug_info)
3975                         mono_debug_record_line_number (cfg, ins, offset);
3976
3977                 switch (ins->opcode) {
3978                 case OP_BIGMUL:
3979                         amd64_mul_reg (code, ins->sreg2, TRUE);
3980                         break;
3981                 case OP_BIGMUL_UN:
3982                         amd64_mul_reg (code, ins->sreg2, FALSE);
3983                         break;
3984                 case OP_X86_SETEQ_MEMBASE:
3985                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3986                         break;
3987                 case OP_STOREI1_MEMBASE_IMM:
3988                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3989                         break;
3990                 case OP_STOREI2_MEMBASE_IMM:
3991                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3992                         break;
3993                 case OP_STOREI4_MEMBASE_IMM:
3994                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3995                         break;
3996                 case OP_STOREI1_MEMBASE_REG:
3997                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3998                         break;
3999                 case OP_STOREI2_MEMBASE_REG:
4000                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4001                         break;
4002                 /* In AMD64 NaCl, pointers are 4 bytes, */
4003                 /*  so STORE_* != STOREI8_*. Likewise below. */
4004                 case OP_STORE_MEMBASE_REG:
4005                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4006                         break;
4007                 case OP_STOREI8_MEMBASE_REG:
4008                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4009                         break;
4010                 case OP_STOREI4_MEMBASE_REG:
4011                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4012                         break;
4013                 case OP_STORE_MEMBASE_IMM:
4014 #ifndef __native_client_codegen__
4015                         /* In NaCl, this could be a PCONST type, which could */
4016                         /* mean a pointer type was copied directly into the  */
4017                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4018                         /* the value would be 0x00000000FFFFFFFF which is    */
4019                         /* not proper for an imm32 unless you cast it.       */
4020                         g_assert (amd64_is_imm32 (ins->inst_imm));
4021 #endif
4022                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4023                         break;
4024                 case OP_STOREI8_MEMBASE_IMM:
4025                         g_assert (amd64_is_imm32 (ins->inst_imm));
4026                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4027                         break;
4028                 case OP_LOAD_MEM:
4029 #ifdef __mono_ilp32__
4030                         /* In ILP32, pointers are 4 bytes, so separate these */
4031                         /* cases, use literal 8 below where we really want 8 */
4032                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4033                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4034                         break;
4035 #endif
4036                 case OP_LOADI8_MEM:
4037                         // FIXME: Decompose this earlier
4038                         if (amd64_use_imm32 (ins->inst_imm))
4039                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4040                         else {
4041                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4042                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4043                         }
4044                         break;
4045                 case OP_LOADI4_MEM:
4046                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4047                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4048                         break;
4049                 case OP_LOADU4_MEM:
4050                         // FIXME: Decompose this earlier
4051                         if (amd64_use_imm32 (ins->inst_imm))
4052                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4053                         else {
4054                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4055                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4056                         }
4057                         break;
4058                 case OP_LOADU1_MEM:
4059                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4060                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4061                         break;
4062                 case OP_LOADU2_MEM:
4063                         /* For NaCl, pointers are 4 bytes, so separate these */
4064                         /* cases, use literal 8 below where we really want 8 */
4065                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4066                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4067                         break;
4068                 case OP_LOAD_MEMBASE:
4069                         g_assert (amd64_is_imm32 (ins->inst_offset));
4070                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4071                         break;
4072                 case OP_LOADI8_MEMBASE:
4073                         /* Use literal 8 instead of sizeof pointer or */
4074                         /* register, we really want 8 for this opcode */
4075                         g_assert (amd64_is_imm32 (ins->inst_offset));
4076                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4077                         break;
4078                 case OP_LOADI4_MEMBASE:
4079                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4080                         break;
4081                 case OP_LOADU4_MEMBASE:
4082                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4083                         break;
4084                 case OP_LOADU1_MEMBASE:
4085                         /* The cpu zero extends the result into 64 bits */
4086                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4087                         break;
4088                 case OP_LOADI1_MEMBASE:
4089                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4090                         break;
4091                 case OP_LOADU2_MEMBASE:
4092                         /* The cpu zero extends the result into 64 bits */
4093                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4094                         break;
4095                 case OP_LOADI2_MEMBASE:
4096                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4097                         break;
4098                 case OP_AMD64_LOADI8_MEMINDEX:
4099                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4100                         break;
4101                 case OP_LCONV_TO_I1:
4102                 case OP_ICONV_TO_I1:
4103                 case OP_SEXT_I1:
4104                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4105                         break;
4106                 case OP_LCONV_TO_I2:
4107                 case OP_ICONV_TO_I2:
4108                 case OP_SEXT_I2:
4109                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4110                         break;
4111                 case OP_LCONV_TO_U1:
4112                 case OP_ICONV_TO_U1:
4113                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4114                         break;
4115                 case OP_LCONV_TO_U2:
4116                 case OP_ICONV_TO_U2:
4117                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4118                         break;
4119                 case OP_ZEXT_I4:
4120                         /* Clean out the upper word */
4121                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4122                         break;
4123                 case OP_SEXT_I4:
4124                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4125                         break;
4126                 case OP_COMPARE:
4127                 case OP_LCOMPARE:
4128                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4129                         break;
4130                 case OP_COMPARE_IMM:
4131 #if defined(__mono_ilp32__)
4132                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4133                         g_assert (amd64_is_imm32 (ins->inst_imm));
4134                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4135                         break;
4136 #endif
4137                 case OP_LCOMPARE_IMM:
4138                         g_assert (amd64_is_imm32 (ins->inst_imm));
4139                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4140                         break;
4141                 case OP_X86_COMPARE_REG_MEMBASE:
4142                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4143                         break;
4144                 case OP_X86_TEST_NULL:
4145                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4146                         break;
4147                 case OP_AMD64_TEST_NULL:
4148                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4149                         break;
4150
4151                 case OP_X86_ADD_REG_MEMBASE:
4152                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4153                         break;
4154                 case OP_X86_SUB_REG_MEMBASE:
4155                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4156                         break;
4157                 case OP_X86_AND_REG_MEMBASE:
4158                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4159                         break;
4160                 case OP_X86_OR_REG_MEMBASE:
4161                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4162                         break;
4163                 case OP_X86_XOR_REG_MEMBASE:
4164                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4165                         break;
4166
4167                 case OP_X86_ADD_MEMBASE_IMM:
4168                         /* FIXME: Make a 64 version too */
4169                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4170                         break;
4171                 case OP_X86_SUB_MEMBASE_IMM:
4172                         g_assert (amd64_is_imm32 (ins->inst_imm));
4173                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4174                         break;
4175                 case OP_X86_AND_MEMBASE_IMM:
4176                         g_assert (amd64_is_imm32 (ins->inst_imm));
4177                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4178                         break;
4179                 case OP_X86_OR_MEMBASE_IMM:
4180                         g_assert (amd64_is_imm32 (ins->inst_imm));
4181                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4182                         break;
4183                 case OP_X86_XOR_MEMBASE_IMM:
4184                         g_assert (amd64_is_imm32 (ins->inst_imm));
4185                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4186                         break;
4187                 case OP_X86_ADD_MEMBASE_REG:
4188                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4189                         break;
4190                 case OP_X86_SUB_MEMBASE_REG:
4191                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4192                         break;
4193                 case OP_X86_AND_MEMBASE_REG:
4194                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4195                         break;
4196                 case OP_X86_OR_MEMBASE_REG:
4197                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4198                         break;
4199                 case OP_X86_XOR_MEMBASE_REG:
4200                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4201                         break;
4202                 case OP_X86_INC_MEMBASE:
4203                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4204                         break;
4205                 case OP_X86_INC_REG:
4206                         amd64_inc_reg_size (code, ins->dreg, 4);
4207                         break;
4208                 case OP_X86_DEC_MEMBASE:
4209                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4210                         break;
4211                 case OP_X86_DEC_REG:
4212                         amd64_dec_reg_size (code, ins->dreg, 4);
4213                         break;
4214                 case OP_X86_MUL_REG_MEMBASE:
4215                 case OP_X86_MUL_MEMBASE_REG:
4216                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4217                         break;
4218                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4219                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4220                         break;
4221                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4222                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4223                         break;
4224                 case OP_AMD64_COMPARE_MEMBASE_REG:
4225                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4226                         break;
4227                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4228                         g_assert (amd64_is_imm32 (ins->inst_imm));
4229                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4230                         break;
4231                 case OP_X86_COMPARE_MEMBASE8_IMM:
4232                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4233                         break;
4234                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4235                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4236                         break;
4237                 case OP_AMD64_COMPARE_REG_MEMBASE:
4238                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4239                         break;
4240
4241                 case OP_AMD64_ADD_REG_MEMBASE:
4242                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4243                         break;
4244                 case OP_AMD64_SUB_REG_MEMBASE:
4245                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4246                         break;
4247                 case OP_AMD64_AND_REG_MEMBASE:
4248                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4249                         break;
4250                 case OP_AMD64_OR_REG_MEMBASE:
4251                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4252                         break;
4253                 case OP_AMD64_XOR_REG_MEMBASE:
4254                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4255                         break;
4256
4257                 case OP_AMD64_ADD_MEMBASE_REG:
4258                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4259                         break;
4260                 case OP_AMD64_SUB_MEMBASE_REG:
4261                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4262                         break;
4263                 case OP_AMD64_AND_MEMBASE_REG:
4264                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4265                         break;
4266                 case OP_AMD64_OR_MEMBASE_REG:
4267                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4268                         break;
4269                 case OP_AMD64_XOR_MEMBASE_REG:
4270                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4271                         break;
4272
4273                 case OP_AMD64_ADD_MEMBASE_IMM:
4274                         g_assert (amd64_is_imm32 (ins->inst_imm));
4275                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4276                         break;
4277                 case OP_AMD64_SUB_MEMBASE_IMM:
4278                         g_assert (amd64_is_imm32 (ins->inst_imm));
4279                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4280                         break;
4281                 case OP_AMD64_AND_MEMBASE_IMM:
4282                         g_assert (amd64_is_imm32 (ins->inst_imm));
4283                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4284                         break;
4285                 case OP_AMD64_OR_MEMBASE_IMM:
4286                         g_assert (amd64_is_imm32 (ins->inst_imm));
4287                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4288                         break;
4289                 case OP_AMD64_XOR_MEMBASE_IMM:
4290                         g_assert (amd64_is_imm32 (ins->inst_imm));
4291                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4292                         break;
4293
4294                 case OP_BREAK:
4295                         amd64_breakpoint (code);
4296                         break;
4297                 case OP_RELAXED_NOP:
4298                         x86_prefix (code, X86_REP_PREFIX);
4299                         x86_nop (code);
4300                         break;
4301                 case OP_HARD_NOP:
4302                         x86_nop (code);
4303                         break;
4304                 case OP_NOP:
4305                 case OP_DUMMY_USE:
4306                 case OP_DUMMY_STORE:
4307                 case OP_DUMMY_ICONST:
4308                 case OP_DUMMY_R8CONST:
4309                 case OP_NOT_REACHED:
4310                 case OP_NOT_NULL:
4311                         break;
4312                 case OP_IL_SEQ_POINT:
4313                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4314                         break;
4315                 case OP_SEQ_POINT: {
4316                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4317                                 MonoInst *var = cfg->arch.ss_tramp_var;
4318                                 guint8 *label;
4319
4320                                 /* Load ss_tramp_var */
4321                                 /* This is equal to &ss_trampoline */
4322                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4323                                 /* Load the trampoline address */
4324                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4325                                 /* Call it if it is non-null */
4326                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4327                                 label = code;
4328                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4329                                 amd64_call_reg (code, AMD64_R11);
4330                                 amd64_patch (label, code);
4331                         }
4332
4333                         /*
4334                          * This is the address which is saved in seq points,
4335                          */
4336                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4337
4338                         if (cfg->compile_aot) {
4339                                 guint32 offset = code - cfg->native_code;
4340                                 guint32 val;
4341                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4342                                 guint8 *label;
4343
4344                                 /* Load info var */
4345                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4346                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4347                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4348                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4349                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4350                                 label = code;
4351                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4352                                 /* Call the trampoline */
4353                                 amd64_call_reg (code, AMD64_R11);
4354                                 amd64_patch (label, code);
4355                         } else {
4356                                 MonoInst *var = cfg->arch.bp_tramp_var;
4357                                 guint8 *label;
4358
4359                                 /*
4360                                  * Emit a test+branch against a constant, the constant will be overwritten
4361                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4362                                  */
4363                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4364                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4365                                 label = code;
4366                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4367
4368                                 g_assert (var);
4369                                 g_assert (var->opcode == OP_REGOFFSET);
4370                                 /* Load bp_tramp_var */
4371                                 /* This is equal to &bp_trampoline */
4372                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4373                                 /* Call the trampoline */
4374                                 amd64_call_membase (code, AMD64_R11, 0);
4375                                 amd64_patch (label, code);
4376                         }
4377                         /*
4378                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4379                          * to another IL offset.
4380                          */
4381                         x86_nop (code);
4382                         break;
4383                 }
4384                 case OP_ADDCC:
4385                 case OP_LADDCC:
4386                 case OP_LADD:
4387                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4388                         break;
4389                 case OP_ADC:
4390                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4391                         break;
4392                 case OP_ADD_IMM:
4393                 case OP_LADD_IMM:
4394                         g_assert (amd64_is_imm32 (ins->inst_imm));
4395                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4396                         break;
4397                 case OP_ADC_IMM:
4398                         g_assert (amd64_is_imm32 (ins->inst_imm));
4399                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4400                         break;
4401                 case OP_SUBCC:
4402                 case OP_LSUBCC:
4403                 case OP_LSUB:
4404                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4405                         break;
4406                 case OP_SBB:
4407                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4408                         break;
4409                 case OP_SUB_IMM:
4410                 case OP_LSUB_IMM:
4411                         g_assert (amd64_is_imm32 (ins->inst_imm));
4412                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4413                         break;
4414                 case OP_SBB_IMM:
4415                         g_assert (amd64_is_imm32 (ins->inst_imm));
4416                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4417                         break;
4418                 case OP_LAND:
4419                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4420                         break;
4421                 case OP_AND_IMM:
4422                 case OP_LAND_IMM:
4423                         g_assert (amd64_is_imm32 (ins->inst_imm));
4424                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4425                         break;
4426                 case OP_LMUL:
4427                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4428                         break;
4429                 case OP_MUL_IMM:
4430                 case OP_LMUL_IMM:
4431                 case OP_IMUL_IMM: {
4432                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4433
4434                         switch (ins->inst_imm) {
4435                         case 2:
4436                                 /* MOV r1, r2 */
4437                                 /* ADD r1, r1 */
4438                                 if (ins->dreg != ins->sreg1)
4439                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4440                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4441                                 break;
4442                         case 3:
4443                                 /* LEA r1, [r2 + r2*2] */
4444                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4445                                 break;
4446                         case 5:
4447                                 /* LEA r1, [r2 + r2*4] */
4448                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4449                                 break;
4450                         case 6:
4451                                 /* LEA r1, [r2 + r2*2] */
4452                                 /* ADD r1, r1          */
4453                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4454                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4455                                 break;
4456                         case 9:
4457                                 /* LEA r1, [r2 + r2*8] */
4458                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4459                                 break;
4460                         case 10:
4461                                 /* LEA r1, [r2 + r2*4] */
4462                                 /* ADD r1, r1          */
4463                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4464                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4465                                 break;
4466                         case 12:
4467                                 /* LEA r1, [r2 + r2*2] */
4468                                 /* SHL r1, 2           */
4469                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4470                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4471                                 break;
4472                         case 25:
4473                                 /* LEA r1, [r2 + r2*4] */
4474                                 /* LEA r1, [r1 + r1*4] */
4475                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4476                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4477                                 break;
4478                         case 100:
4479                                 /* LEA r1, [r2 + r2*4] */
4480                                 /* SHL r1, 2           */
4481                                 /* LEA r1, [r1 + r1*4] */
4482                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4483                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4484                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4485                                 break;
4486                         default:
4487                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4488                                 break;
4489                         }
4490                         break;
4491                 }
4492                 case OP_LDIV:
4493                 case OP_LREM:
4494 #if defined( __native_client_codegen__ )
4495                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4496                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4497 #endif
4498                         /* Regalloc magic makes the div/rem cases the same */
4499                         if (ins->sreg2 == AMD64_RDX) {
4500                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4501                                 amd64_cdq (code);
4502                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4503                         } else {
4504                                 amd64_cdq (code);
4505                                 amd64_div_reg (code, ins->sreg2, TRUE);
4506                         }
4507                         break;
4508                 case OP_LDIV_UN:
4509                 case OP_LREM_UN:
4510 #if defined( __native_client_codegen__ )
4511                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4512                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4513 #endif
4514                         if (ins->sreg2 == AMD64_RDX) {
4515                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4516                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4517                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4518                         } else {
4519                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4520                                 amd64_div_reg (code, ins->sreg2, FALSE);
4521                         }
4522                         break;
4523                 case OP_IDIV:
4524                 case OP_IREM:
4525 #if defined( __native_client_codegen__ )
4526                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4527                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4528 #endif
4529                         if (ins->sreg2 == AMD64_RDX) {
4530                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4531                                 amd64_cdq_size (code, 4);
4532                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4533                         } else {
4534                                 amd64_cdq_size (code, 4);
4535                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4536                         }
4537                         break;
4538                 case OP_IDIV_UN:
4539                 case OP_IREM_UN:
4540 #if defined( __native_client_codegen__ )
4541                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4542                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4543 #endif
4544                         if (ins->sreg2 == AMD64_RDX) {
4545                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4546                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4547                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4548                         } else {
4549                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4550                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4551                         }
4552                         break;
4553                 case OP_LMUL_OVF:
4554                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4555                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4556                         break;
4557                 case OP_LOR:
4558                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4559                         break;
4560                 case OP_OR_IMM:
4561                 case OP_LOR_IMM:
4562                         g_assert (amd64_is_imm32 (ins->inst_imm));
4563                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4564                         break;
4565                 case OP_LXOR:
4566                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4567                         break;
4568                 case OP_XOR_IMM:
4569                 case OP_LXOR_IMM:
4570                         g_assert (amd64_is_imm32 (ins->inst_imm));
4571                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4572                         break;
4573                 case OP_LSHL:
4574                         g_assert (ins->sreg2 == AMD64_RCX);
4575                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4576                         break;
4577                 case OP_LSHR:
4578                         g_assert (ins->sreg2 == AMD64_RCX);
4579                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4580                         break;
4581                 case OP_SHR_IMM:
4582                 case OP_LSHR_IMM:
4583                         g_assert (amd64_is_imm32 (ins->inst_imm));
4584                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4585                         break;
4586                 case OP_SHR_UN_IMM:
4587                         g_assert (amd64_is_imm32 (ins->inst_imm));
4588                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4589                         break;
4590                 case OP_LSHR_UN_IMM:
4591                         g_assert (amd64_is_imm32 (ins->inst_imm));
4592                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4593                         break;
4594                 case OP_LSHR_UN:
4595                         g_assert (ins->sreg2 == AMD64_RCX);
4596                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4597                         break;
4598                 case OP_SHL_IMM:
4599                 case OP_LSHL_IMM:
4600                         g_assert (amd64_is_imm32 (ins->inst_imm));
4601                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4602                         break;
4603
4604                 case OP_IADDCC:
4605                 case OP_IADD:
4606                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4607                         break;
4608                 case OP_IADC:
4609                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4610                         break;
4611                 case OP_IADD_IMM:
4612                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4613                         break;
4614                 case OP_IADC_IMM:
4615                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4616                         break;
4617                 case OP_ISUBCC:
4618                 case OP_ISUB:
4619                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4620                         break;
4621                 case OP_ISBB:
4622                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4623                         break;
4624                 case OP_ISUB_IMM:
4625                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4626                         break;
4627                 case OP_ISBB_IMM:
4628                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4629                         break;
4630                 case OP_IAND:
4631                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4632                         break;
4633                 case OP_IAND_IMM:
4634                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4635                         break;
4636                 case OP_IOR:
4637                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4638                         break;
4639                 case OP_IOR_IMM:
4640                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4641                         break;
4642                 case OP_IXOR:
4643                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4644                         break;
4645                 case OP_IXOR_IMM:
4646                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4647                         break;
4648                 case OP_INEG:
4649                         amd64_neg_reg_size (code, ins->sreg1, 4);
4650                         break;
4651                 case OP_INOT:
4652                         amd64_not_reg_size (code, ins->sreg1, 4);
4653                         break;
4654                 case OP_ISHL:
4655                         g_assert (ins->sreg2 == AMD64_RCX);
4656                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4657                         break;
4658                 case OP_ISHR:
4659                         g_assert (ins->sreg2 == AMD64_RCX);
4660                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4661                         break;
4662                 case OP_ISHR_IMM:
4663                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4664                         break;
4665                 case OP_ISHR_UN_IMM:
4666                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4667                         break;
4668                 case OP_ISHR_UN:
4669                         g_assert (ins->sreg2 == AMD64_RCX);
4670                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4671                         break;
4672                 case OP_ISHL_IMM:
4673                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4674                         break;
4675                 case OP_IMUL:
4676                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4677                         break;
4678                 case OP_IMUL_OVF:
4679                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4680                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4681                         break;
4682                 case OP_IMUL_OVF_UN:
4683                 case OP_LMUL_OVF_UN: {
4684                         /* the mul operation and the exception check should most likely be split */
4685                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4686                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4687                         /*g_assert (ins->sreg2 == X86_EAX);
4688                         g_assert (ins->dreg == X86_EAX);*/
4689                         if (ins->sreg2 == X86_EAX) {
4690                                 non_eax_reg = ins->sreg1;
4691                         } else if (ins->sreg1 == X86_EAX) {
4692                                 non_eax_reg = ins->sreg2;
4693                         } else {
4694                                 /* no need to save since we're going to store to it anyway */
4695                                 if (ins->dreg != X86_EAX) {
4696                                         saved_eax = TRUE;
4697                                         amd64_push_reg (code, X86_EAX);
4698                                 }
4699                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4700                                 non_eax_reg = ins->sreg2;
4701                         }
4702                         if (ins->dreg == X86_EDX) {
4703                                 if (!saved_eax) {
4704                                         saved_eax = TRUE;
4705                                         amd64_push_reg (code, X86_EAX);
4706                                 }
4707                         } else {
4708                                 saved_edx = TRUE;
4709                                 amd64_push_reg (code, X86_EDX);
4710                         }
4711                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4712                         /* save before the check since pop and mov don't change the flags */
4713                         if (ins->dreg != X86_EAX)
4714                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4715                         if (saved_edx)
4716                                 amd64_pop_reg (code, X86_EDX);
4717                         if (saved_eax)
4718                                 amd64_pop_reg (code, X86_EAX);
4719                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4720                         break;
4721                 }
4722                 case OP_ICOMPARE:
4723                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4724                         break;
4725                 case OP_ICOMPARE_IMM:
4726                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4727                         break;
4728                 case OP_IBEQ:
4729                 case OP_IBLT:
4730                 case OP_IBGT:
4731                 case OP_IBGE:
4732                 case OP_IBLE:
4733                 case OP_LBEQ:
4734                 case OP_LBLT:
4735                 case OP_LBGT:
4736                 case OP_LBGE:
4737                 case OP_LBLE:
4738                 case OP_IBNE_UN:
4739                 case OP_IBLT_UN:
4740                 case OP_IBGT_UN:
4741                 case OP_IBGE_UN:
4742                 case OP_IBLE_UN:
4743                 case OP_LBNE_UN:
4744                 case OP_LBLT_UN:
4745                 case OP_LBGT_UN:
4746                 case OP_LBGE_UN:
4747                 case OP_LBLE_UN:
4748                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4749                         break;
4750
4751                 case OP_CMOV_IEQ:
4752                 case OP_CMOV_IGE:
4753                 case OP_CMOV_IGT:
4754                 case OP_CMOV_ILE:
4755                 case OP_CMOV_ILT:
4756                 case OP_CMOV_INE_UN:
4757                 case OP_CMOV_IGE_UN:
4758                 case OP_CMOV_IGT_UN:
4759                 case OP_CMOV_ILE_UN:
4760                 case OP_CMOV_ILT_UN:
4761                 case OP_CMOV_LEQ:
4762                 case OP_CMOV_LGE:
4763                 case OP_CMOV_LGT:
4764                 case OP_CMOV_LLE:
4765                 case OP_CMOV_LLT:
4766                 case OP_CMOV_LNE_UN:
4767                 case OP_CMOV_LGE_UN:
4768                 case OP_CMOV_LGT_UN:
4769                 case OP_CMOV_LLE_UN:
4770                 case OP_CMOV_LLT_UN:
4771                         g_assert (ins->dreg == ins->sreg1);
4772                         /* This needs to operate on 64 bit values */
4773                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4774                         break;
4775
4776                 case OP_LNOT:
4777                         amd64_not_reg (code, ins->sreg1);
4778                         break;
4779                 case OP_LNEG:
4780                         amd64_neg_reg (code, ins->sreg1);
4781                         break;
4782
4783                 case OP_ICONST:
4784                 case OP_I8CONST:
4785                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4786                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4787                         else
4788                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4789                         break;
4790                 case OP_AOTCONST:
4791                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4792                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4793                         break;
4794                 case OP_JUMP_TABLE:
4795                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4796                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4797                         break;
4798                 case OP_MOVE:
4799                         if (ins->dreg != ins->sreg1)
4800                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4801                         break;
4802                 case OP_AMD64_SET_XMMREG_R4: {
4803                         if (cfg->r4fp) {
4804                                 if (ins->dreg != ins->sreg1)
4805                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4806                         } else {
4807                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4808                         }
4809                         break;
4810                 }
4811                 case OP_AMD64_SET_XMMREG_R8: {
4812                         if (ins->dreg != ins->sreg1)
4813                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4814                         break;
4815                 }
4816                 case OP_TAILCALL: {
4817                         MonoCallInst *call = (MonoCallInst*)ins;
4818                         int i, save_area_offset;
4819
4820                         g_assert (!cfg->method->save_lmf);
4821
4822                         /* Restore callee saved registers */
4823                         save_area_offset = cfg->arch.reg_save_area_offset;
4824                         for (i = 0; i < AMD64_NREG; ++i)
4825                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4826                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4827                                         save_area_offset += 8;
4828                                 }
4829
4830                         if (cfg->arch.omit_fp) {
4831                                 if (cfg->arch.stack_alloc_size)
4832                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4833                                 // FIXME:
4834                                 if (call->stack_usage)
4835                                         NOT_IMPLEMENTED;
4836                         } else {
4837                                 /* Copy arguments on the stack to our argument area */
4838                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4839                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4840                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4841                                 }
4842
4843                                 amd64_leave (code);
4844                         }
4845
4846                         offset = code - cfg->native_code;
4847                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4848                         if (cfg->compile_aot)
4849                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4850                         else
4851                                 amd64_set_reg_template (code, AMD64_R11);
4852                         amd64_jump_reg (code, AMD64_R11);
4853                         ins->flags |= MONO_INST_GC_CALLSITE;
4854                         ins->backend.pc_offset = code - cfg->native_code;
4855                         break;
4856                 }
4857                 case OP_CHECK_THIS:
4858                         /* ensure ins->sreg1 is not NULL */
4859                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4860                         break;
4861                 case OP_ARGLIST: {
4862                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4863                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4864                         break;
4865                 }
4866                 case OP_CALL:
4867                 case OP_FCALL:
4868                 case OP_RCALL:
4869                 case OP_LCALL:
4870                 case OP_VCALL:
4871                 case OP_VCALL2:
4872                 case OP_VOIDCALL:
4873                         call = (MonoCallInst*)ins;
4874                         /*
4875                          * The AMD64 ABI forces callers to know about varargs.
4876                          */
4877                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4878                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4879                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4880                                 /*
4881                                  * Since the unmanaged calling convention doesn't contain a
4882                                  * 'vararg' entry, we have to treat every pinvoke call as a
4883                                  * potential vararg call.
4884                                  */
4885                                 guint32 nregs, i;
4886                                 nregs = 0;
4887                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4888                                         if (call->used_fregs & (1 << i))
4889                                                 nregs ++;
4890                                 if (!nregs)
4891                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4892                                 else
4893                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4894                         }
4895
4896                         if (ins->flags & MONO_INST_HAS_METHOD)
4897                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4898                         else
4899                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4900                         ins->flags |= MONO_INST_GC_CALLSITE;
4901                         ins->backend.pc_offset = code - cfg->native_code;
4902                         code = emit_move_return_value (cfg, ins, code);
4903                         break;
4904                 case OP_FCALL_REG:
4905                 case OP_RCALL_REG:
4906                 case OP_LCALL_REG:
4907                 case OP_VCALL_REG:
4908                 case OP_VCALL2_REG:
4909                 case OP_VOIDCALL_REG:
4910                 case OP_CALL_REG:
4911                         call = (MonoCallInst*)ins;
4912
4913                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4914                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4915                                 ins->sreg1 = AMD64_R11;
4916                         }
4917
4918                         /*
4919                          * The AMD64 ABI forces callers to know about varargs.
4920                          */
4921                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4922                                 if (ins->sreg1 == AMD64_RAX) {
4923                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4924                                         ins->sreg1 = AMD64_R11;
4925                                 }
4926                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4927                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4928                                 /*
4929                                  * Since the unmanaged calling convention doesn't contain a
4930                                  * 'vararg' entry, we have to treat every pinvoke call as a
4931                                  * potential vararg call.
4932                                  */
4933                                 guint32 nregs, i;
4934                                 nregs = 0;
4935                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4936                                         if (call->used_fregs & (1 << i))
4937                                                 nregs ++;
4938                                 if (ins->sreg1 == AMD64_RAX) {
4939                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4940                                         ins->sreg1 = AMD64_R11;
4941                                 }
4942                                 if (!nregs)
4943                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4944                                 else
4945                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4946                         }
4947
4948                         amd64_call_reg (code, ins->sreg1);
4949                         ins->flags |= MONO_INST_GC_CALLSITE;
4950                         ins->backend.pc_offset = code - cfg->native_code;
4951                         code = emit_move_return_value (cfg, ins, code);
4952                         break;
4953                 case OP_FCALL_MEMBASE:
4954                 case OP_RCALL_MEMBASE:
4955                 case OP_LCALL_MEMBASE:
4956                 case OP_VCALL_MEMBASE:
4957                 case OP_VCALL2_MEMBASE:
4958                 case OP_VOIDCALL_MEMBASE:
4959                 case OP_CALL_MEMBASE:
4960                         call = (MonoCallInst*)ins;
4961
4962                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4963                         ins->flags |= MONO_INST_GC_CALLSITE;
4964                         ins->backend.pc_offset = code - cfg->native_code;
4965                         code = emit_move_return_value (cfg, ins, code);
4966                         break;
4967                 case OP_DYN_CALL: {
4968                         int i;
4969                         MonoInst *var = cfg->dyn_call_var;
4970
4971                         g_assert (var->opcode == OP_REGOFFSET);
4972
4973                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4974                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4975                         /* r10 = ftn */
4976                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4977
4978                         /* Save args buffer */
4979                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4980
4981                         /* Set argument registers */
4982                         for (i = 0; i < PARAM_REGS; ++i)
4983                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4984
4985                         /* Make the call */
4986                         amd64_call_reg (code, AMD64_R10);
4987
4988                         ins->flags |= MONO_INST_GC_CALLSITE;
4989                         ins->backend.pc_offset = code - cfg->native_code;
4990
4991                         /* Save result */
4992                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4993                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4994                         break;
4995                 }
4996                 case OP_AMD64_SAVE_SP_TO_LMF: {
4997                         MonoInst *lmf_var = cfg->lmf_var;
4998                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4999                         break;
5000                 }
5001                 case OP_X86_PUSH:
5002                         g_assert_not_reached ();
5003                         amd64_push_reg (code, ins->sreg1);
5004                         break;
5005                 case OP_X86_PUSH_IMM:
5006                         g_assert_not_reached ();
5007                         g_assert (amd64_is_imm32 (ins->inst_imm));
5008                         amd64_push_imm (code, ins->inst_imm);
5009                         break;
5010                 case OP_X86_PUSH_MEMBASE:
5011                         g_assert_not_reached ();
5012                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5013                         break;
5014                 case OP_X86_PUSH_OBJ: {
5015                         int size = ALIGN_TO (ins->inst_imm, 8);
5016
5017                         g_assert_not_reached ();
5018
5019                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5020                         amd64_push_reg (code, AMD64_RDI);
5021                         amd64_push_reg (code, AMD64_RSI);
5022                         amd64_push_reg (code, AMD64_RCX);
5023                         if (ins->inst_offset)
5024                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5025                         else
5026                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5027                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5028                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5029                         amd64_cld (code);
5030                         amd64_prefix (code, X86_REP_PREFIX);
5031                         amd64_movsd (code);
5032                         amd64_pop_reg (code, AMD64_RCX);
5033                         amd64_pop_reg (code, AMD64_RSI);
5034                         amd64_pop_reg (code, AMD64_RDI);
5035                         break;
5036                 }
5037                 case OP_GENERIC_CLASS_INIT: {
5038                         static int byte_offset = -1;
5039                         static guint8 bitmask;
5040                         guint8 *jump;
5041
5042                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
5043
5044                         if (byte_offset < 0)
5045                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5046
5047                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
5048                         jump = code;
5049                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
5050
5051                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5052                         ins->flags |= MONO_INST_GC_CALLSITE;
5053                         ins->backend.pc_offset = code - cfg->native_code;
5054
5055                         x86_patch (jump, code);
5056                         break;
5057                 }
5058
5059                 case OP_X86_LEA:
5060                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5061                         break;
5062                 case OP_X86_LEA_MEMBASE:
5063                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5064                         break;
5065                 case OP_X86_XCHG:
5066                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5067                         break;
5068                 case OP_LOCALLOC:
5069                         /* keep alignment */
5070                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5071                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5072                         code = mono_emit_stack_alloc (cfg, code, ins);
5073                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5074                         if (cfg->param_area)
5075                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5076                         break;
5077                 case OP_LOCALLOC_IMM: {
5078                         guint32 size = ins->inst_imm;
5079                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5080
5081                         if (ins->flags & MONO_INST_INIT) {
5082                                 if (size < 64) {
5083                                         int i;
5084
5085                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5086                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5087
5088                                         for (i = 0; i < size; i += 8)
5089                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5090                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5091                                 } else {
5092                                         amd64_mov_reg_imm (code, ins->dreg, size);
5093                                         ins->sreg1 = ins->dreg;
5094
5095                                         code = mono_emit_stack_alloc (cfg, code, ins);
5096                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5097                                 }
5098                         } else {
5099                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5100                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5101                         }
5102                         if (cfg->param_area)
5103                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5104                         break;
5105                 }
5106                 case OP_THROW: {
5107                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5108                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5109                                              (gpointer)"mono_arch_throw_exception", FALSE);
5110                         ins->flags |= MONO_INST_GC_CALLSITE;
5111                         ins->backend.pc_offset = code - cfg->native_code;
5112                         break;
5113                 }
5114                 case OP_RETHROW: {
5115                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5116                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5117                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5118                         ins->flags |= MONO_INST_GC_CALLSITE;
5119                         ins->backend.pc_offset = code - cfg->native_code;
5120                         break;
5121                 }
5122                 case OP_CALL_HANDLER:
5123                         /* Align stack */
5124                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5125                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5126                         amd64_call_imm (code, 0);
5127                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5128                         /* Restore stack alignment */
5129                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5130                         break;
5131                 case OP_START_HANDLER: {
5132                         /* Even though we're saving RSP, use sizeof */
5133                         /* gpointer because spvar is of type IntPtr */
5134                         /* see: mono_create_spvar_for_region */
5135                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5136                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5137
5138                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5139                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5140                                 cfg->param_area) {
5141                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5142                         }
5143                         break;
5144                 }
5145                 case OP_ENDFINALLY: {
5146                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5147                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5148                         amd64_ret (code);
5149                         break;
5150                 }
5151                 case OP_ENDFILTER: {
5152                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5153                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5154                         /* The local allocator will put the result into RAX */
5155                         amd64_ret (code);
5156                         break;
5157                 }
5158                 case OP_GET_EX_OBJ:
5159                         if (ins->dreg != AMD64_RAX)
5160                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5161                         break;
5162                 case OP_LABEL:
5163                         ins->inst_c0 = code - cfg->native_code;
5164                         break;
5165                 case OP_BR:
5166                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5167                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5168                         //break;
5169                                 if (ins->inst_target_bb->native_offset) {
5170                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5171                                 } else {
5172                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5173                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5174                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5175                                                 x86_jump8 (code, 0);
5176                                         else
5177                                                 x86_jump32 (code, 0);
5178                         }
5179                         break;
5180                 case OP_BR_REG:
5181                         amd64_jump_reg (code, ins->sreg1);
5182                         break;
5183                 case OP_ICNEQ:
5184                 case OP_ICGE:
5185                 case OP_ICLE:
5186                 case OP_ICGE_UN:
5187                 case OP_ICLE_UN:
5188
5189                 case OP_CEQ:
5190                 case OP_LCEQ:
5191                 case OP_ICEQ:
5192                 case OP_CLT:
5193                 case OP_LCLT:
5194                 case OP_ICLT:
5195                 case OP_CGT:
5196                 case OP_ICGT:
5197                 case OP_LCGT:
5198                 case OP_CLT_UN:
5199                 case OP_LCLT_UN:
5200                 case OP_ICLT_UN:
5201                 case OP_CGT_UN:
5202                 case OP_LCGT_UN:
5203                 case OP_ICGT_UN:
5204                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5205                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5206                         break;
5207                 case OP_COND_EXC_EQ:
5208                 case OP_COND_EXC_NE_UN:
5209                 case OP_COND_EXC_LT:
5210                 case OP_COND_EXC_LT_UN:
5211                 case OP_COND_EXC_GT:
5212                 case OP_COND_EXC_GT_UN:
5213                 case OP_COND_EXC_GE:
5214                 case OP_COND_EXC_GE_UN:
5215                 case OP_COND_EXC_LE:
5216                 case OP_COND_EXC_LE_UN:
5217                 case OP_COND_EXC_IEQ:
5218                 case OP_COND_EXC_INE_UN:
5219                 case OP_COND_EXC_ILT:
5220                 case OP_COND_EXC_ILT_UN:
5221                 case OP_COND_EXC_IGT:
5222                 case OP_COND_EXC_IGT_UN:
5223                 case OP_COND_EXC_IGE:
5224                 case OP_COND_EXC_IGE_UN:
5225                 case OP_COND_EXC_ILE:
5226                 case OP_COND_EXC_ILE_UN:
5227                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5228                         break;
5229                 case OP_COND_EXC_OV:
5230                 case OP_COND_EXC_NO:
5231                 case OP_COND_EXC_C:
5232                 case OP_COND_EXC_NC:
5233                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5234                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5235                         break;
5236                 case OP_COND_EXC_IOV:
5237                 case OP_COND_EXC_INO:
5238                 case OP_COND_EXC_IC:
5239                 case OP_COND_EXC_INC:
5240                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5241                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5242                         break;
5243
5244                 /* floating point opcodes */
5245                 case OP_R8CONST: {
5246                         double d = *(double *)ins->inst_p0;
5247
5248                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5249                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5250                         }
5251                         else {
5252                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5253                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5254                         }
5255                         break;
5256                 }
5257                 case OP_R4CONST: {
5258                         float f = *(float *)ins->inst_p0;
5259
5260                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5261                                 if (cfg->r4fp)
5262                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5263                                 else
5264                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5265                         }
5266                         else {
5267                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5268                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5269                                 if (!cfg->r4fp)
5270                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5271                         }
5272                         break;
5273                 }
5274                 case OP_STORER8_MEMBASE_REG:
5275                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5276                         break;
5277                 case OP_LOADR8_MEMBASE:
5278                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5279                         break;
5280                 case OP_STORER4_MEMBASE_REG:
5281                         if (cfg->r4fp) {
5282                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5283                         } else {
5284                                 /* This requires a double->single conversion */
5285                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5286                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5287                         }
5288                         break;
5289                 case OP_LOADR4_MEMBASE:
5290                         if (cfg->r4fp) {
5291                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5292                         } else {
5293                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5294                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5295                         }
5296                         break;
5297                 case OP_ICONV_TO_R4:
5298                         if (cfg->r4fp) {
5299                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5300                         } else {
5301                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5302                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5303                         }
5304                         break;
5305                 case OP_ICONV_TO_R8:
5306                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5307                         break;
5308                 case OP_LCONV_TO_R4:
5309                         if (cfg->r4fp) {
5310                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5311                         } else {
5312                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5313                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5314                         }
5315                         break;
5316                 case OP_LCONV_TO_R8:
5317                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5318                         break;
5319                 case OP_FCONV_TO_R4:
5320                         if (cfg->r4fp) {
5321                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5322                         } else {
5323                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5324                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5325                         }
5326                         break;
5327                 case OP_FCONV_TO_I1:
5328                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5329                         break;
5330                 case OP_FCONV_TO_U1:
5331                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5332                         break;
5333                 case OP_FCONV_TO_I2:
5334                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5335                         break;
5336                 case OP_FCONV_TO_U2:
5337                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5338                         break;
5339                 case OP_FCONV_TO_U4:
5340                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5341                         break;
5342                 case OP_FCONV_TO_I4:
5343                 case OP_FCONV_TO_I:
5344                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5345                         break;
5346                 case OP_FCONV_TO_I8:
5347                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5348                         break;
5349
5350                 case OP_RCONV_TO_I1:
5351                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5352                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5353                         break;
5354                 case OP_RCONV_TO_U1:
5355                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5356                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5357                         break;
5358                 case OP_RCONV_TO_I2:
5359                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5360                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5361                         break;
5362                 case OP_RCONV_TO_U2:
5363                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5364                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5365                         break;
5366                 case OP_RCONV_TO_I4:
5367                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5368                         break;
5369                 case OP_RCONV_TO_U4:
5370                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5371                         break;
5372                 case OP_RCONV_TO_I8:
5373                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5374                         break;
5375                 case OP_RCONV_TO_R8:
5376                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5377                         break;
5378                 case OP_RCONV_TO_R4:
5379                         if (ins->dreg != ins->sreg1)
5380                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5381                         break;
5382
5383                 case OP_LCONV_TO_R_UN: {
5384                         guint8 *br [2];
5385
5386                         /* Based on gcc code */
5387                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5388                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5389
5390                         /* Positive case */
5391                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5392                         br [1] = code; x86_jump8 (code, 0);
5393                         amd64_patch (br [0], code);
5394
5395                         /* Negative case */
5396                         /* Save to the red zone */
5397                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5398                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5399                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5400                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5401                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5402                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5403                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5404                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5405                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5406                         /* Restore */
5407                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5408                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5409                         amd64_patch (br [1], code);
5410                         break;
5411                 }
5412                 case OP_LCONV_TO_OVF_U4:
5413                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5414                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5415                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5416                         break;
5417                 case OP_LCONV_TO_OVF_I4_UN:
5418                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5419                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5420                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5421                         break;
5422                 case OP_FMOVE:
5423                         if (ins->dreg != ins->sreg1)
5424                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5425                         break;
5426                 case OP_RMOVE:
5427                         if (ins->dreg != ins->sreg1)
5428                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5429                         break;
5430                 case OP_MOVE_F_TO_I4:
5431                         if (cfg->r4fp) {
5432                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5433                         } else {
5434                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5435                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5436                         }
5437                         break;
5438                 case OP_MOVE_I4_TO_F:
5439                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5440                         if (!cfg->r4fp)
5441                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5442                         break;
5443                 case OP_MOVE_F_TO_I8:
5444                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5445                         break;
5446                 case OP_MOVE_I8_TO_F:
5447                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5448                         break;
5449                 case OP_FADD:
5450                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5451                         break;
5452                 case OP_FSUB:
5453                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5454                         break;
5455                 case OP_FMUL:
5456                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5457                         break;
5458                 case OP_FDIV:
5459                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5460                         break;
5461                 case OP_FNEG: {
5462                         static double r8_0 = -0.0;
5463
5464                         g_assert (ins->sreg1 == ins->dreg);
5465
5466                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5467                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5468                         break;
5469                 }
5470                 case OP_SIN:
5471                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5472                         break;
5473                 case OP_COS:
5474                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5475                         break;
5476                 case OP_ABS: {
5477                         static guint64 d = 0x7fffffffffffffffUL;
5478
5479                         g_assert (ins->sreg1 == ins->dreg);
5480
5481                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5482                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5483                         break;
5484                 }
5485                 case OP_SQRT:
5486                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5487                         break;
5488
5489                 case OP_RADD:
5490                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5491                         break;
5492                 case OP_RSUB:
5493                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5494                         break;
5495                 case OP_RMUL:
5496                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5497                         break;
5498                 case OP_RDIV:
5499                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5500                         break;
5501                 case OP_RNEG: {
5502                         static float r4_0 = -0.0;
5503
5504                         g_assert (ins->sreg1 == ins->dreg);
5505
5506                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5507                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5508                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5509                         break;
5510                 }
5511
5512                 case OP_IMIN:
5513                         g_assert (cfg->opt & MONO_OPT_CMOV);
5514                         g_assert (ins->dreg == ins->sreg1);
5515                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5516                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5517                         break;
5518                 case OP_IMIN_UN:
5519                         g_assert (cfg->opt & MONO_OPT_CMOV);
5520                         g_assert (ins->dreg == ins->sreg1);
5521                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5522                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5523                         break;
5524                 case OP_IMAX:
5525                         g_assert (cfg->opt & MONO_OPT_CMOV);
5526                         g_assert (ins->dreg == ins->sreg1);
5527                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5528                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5529                         break;
5530                 case OP_IMAX_UN:
5531                         g_assert (cfg->opt & MONO_OPT_CMOV);
5532                         g_assert (ins->dreg == ins->sreg1);
5533                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5534                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5535                         break;
5536                 case OP_LMIN:
5537                         g_assert (cfg->opt & MONO_OPT_CMOV);
5538                         g_assert (ins->dreg == ins->sreg1);
5539                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5540                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5541                         break;
5542                 case OP_LMIN_UN:
5543                         g_assert (cfg->opt & MONO_OPT_CMOV);
5544                         g_assert (ins->dreg == ins->sreg1);
5545                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5546                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5547                         break;
5548                 case OP_LMAX:
5549                         g_assert (cfg->opt & MONO_OPT_CMOV);
5550                         g_assert (ins->dreg == ins->sreg1);
5551                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5552                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5553                         break;
5554                 case OP_LMAX_UN:
5555                         g_assert (cfg->opt & MONO_OPT_CMOV);
5556                         g_assert (ins->dreg == ins->sreg1);
5557                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5558                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5559                         break;
5560                 case OP_X86_FPOP:
5561                         break;
5562                 case OP_FCOMPARE:
5563                         /*
5564                          * The two arguments are swapped because the fbranch instructions
5565                          * depend on this for the non-sse case to work.
5566                          */
5567                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5568                         break;
5569                 case OP_RCOMPARE:
5570                         /*
5571                          * FIXME: Get rid of this.
5572                          * The two arguments are swapped because the fbranch instructions
5573                          * depend on this for the non-sse case to work.
5574                          */
5575                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5576                         break;
5577                 case OP_FCNEQ:
5578                 case OP_FCEQ: {
5579                         /* zeroing the register at the start results in
5580                          * shorter and faster code (we can also remove the widening op)
5581                          */
5582                         guchar *unordered_check;
5583
5584                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5585                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5586                         unordered_check = code;
5587                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5588
5589                         if (ins->opcode == OP_FCEQ) {
5590                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5591                                 amd64_patch (unordered_check, code);
5592                         } else {
5593                                 guchar *jump_to_end;
5594                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5595                                 jump_to_end = code;
5596                                 x86_jump8 (code, 0);
5597                                 amd64_patch (unordered_check, code);
5598                                 amd64_inc_reg (code, ins->dreg);
5599                                 amd64_patch (jump_to_end, code);
5600                         }
5601                         break;
5602                 }
5603                 case OP_FCLT:
5604                 case OP_FCLT_UN: {
5605                         /* zeroing the register at the start results in
5606                          * shorter and faster code (we can also remove the widening op)
5607                          */
5608                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5609                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5610                         if (ins->opcode == OP_FCLT_UN) {
5611                                 guchar *unordered_check = code;
5612                                 guchar *jump_to_end;
5613                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5614                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5615                                 jump_to_end = code;
5616                                 x86_jump8 (code, 0);
5617                                 amd64_patch (unordered_check, code);
5618                                 amd64_inc_reg (code, ins->dreg);
5619                                 amd64_patch (jump_to_end, code);
5620                         } else {
5621                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5622                         }
5623                         break;
5624                 }
5625                 case OP_FCLE: {
5626                         guchar *unordered_check;
5627                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5628                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5629                         unordered_check = code;
5630                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5631                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5632                         amd64_patch (unordered_check, code);
5633                         break;
5634                 }
5635                 case OP_FCGT:
5636                 case OP_FCGT_UN: {
5637                         /* zeroing the register at the start results in
5638                          * shorter and faster code (we can also remove the widening op)
5639                          */
5640                         guchar *unordered_check;
5641
5642                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5643                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5644                         if (ins->opcode == OP_FCGT) {
5645                                 unordered_check = code;
5646                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5647                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5648                                 amd64_patch (unordered_check, code);
5649                         } else {
5650                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5651                         }
5652                         break;
5653                 }
5654                 case OP_FCGE: {
5655                         guchar *unordered_check;
5656                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5657                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5658                         unordered_check = code;
5659                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5660                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5661                         amd64_patch (unordered_check, code);
5662                         break;
5663                 }
5664
5665                 case OP_RCEQ:
5666                 case OP_RCGT:
5667                 case OP_RCLT:
5668                 case OP_RCLT_UN:
5669                 case OP_RCGT_UN: {
5670                         int x86_cond;
5671                         gboolean unordered = FALSE;
5672
5673                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5674                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5675
5676                         switch (ins->opcode) {
5677                         case OP_RCEQ:
5678                                 x86_cond = X86_CC_EQ;
5679                                 break;
5680                         case OP_RCGT:
5681                                 x86_cond = X86_CC_LT;
5682                                 break;
5683                         case OP_RCLT:
5684                                 x86_cond = X86_CC_GT;
5685                                 break;
5686                         case OP_RCLT_UN:
5687                                 x86_cond = X86_CC_GT;
5688                                 unordered = TRUE;
5689                                 break;
5690                         case OP_RCGT_UN:
5691                                 x86_cond = X86_CC_LT;
5692                                 unordered = TRUE;
5693                                 break;
5694                         default:
5695                                 g_assert_not_reached ();
5696                                 break;
5697                         }
5698
5699                         if (unordered) {
5700                                 guchar *unordered_check;
5701                                 guchar *jump_to_end;
5702
5703                                 unordered_check = code;
5704                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5705                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5706                                 jump_to_end = code;
5707                                 x86_jump8 (code, 0);
5708                                 amd64_patch (unordered_check, code);
5709                                 amd64_inc_reg (code, ins->dreg);
5710                                 amd64_patch (jump_to_end, code);
5711                         } else {
5712                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5713                         }
5714                         break;
5715                 }
5716                 case OP_FCLT_MEMBASE:
5717                 case OP_FCGT_MEMBASE:
5718                 case OP_FCLT_UN_MEMBASE:
5719                 case OP_FCGT_UN_MEMBASE:
5720                 case OP_FCEQ_MEMBASE: {
5721                         guchar *unordered_check, *jump_to_end;
5722                         int x86_cond;
5723
5724                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5725                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5726
5727                         switch (ins->opcode) {
5728                         case OP_FCEQ_MEMBASE:
5729                                 x86_cond = X86_CC_EQ;
5730                                 break;
5731                         case OP_FCLT_MEMBASE:
5732                         case OP_FCLT_UN_MEMBASE:
5733                                 x86_cond = X86_CC_LT;
5734                                 break;
5735                         case OP_FCGT_MEMBASE:
5736                         case OP_FCGT_UN_MEMBASE:
5737                                 x86_cond = X86_CC_GT;
5738                                 break;
5739                         default:
5740                                 g_assert_not_reached ();
5741                         }
5742
5743                         unordered_check = code;
5744                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5745                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5746
5747                         switch (ins->opcode) {
5748                         case OP_FCEQ_MEMBASE:
5749                         case OP_FCLT_MEMBASE:
5750                         case OP_FCGT_MEMBASE:
5751                                 amd64_patch (unordered_check, code);
5752                                 break;
5753                         case OP_FCLT_UN_MEMBASE:
5754                         case OP_FCGT_UN_MEMBASE:
5755                                 jump_to_end = code;
5756                                 x86_jump8 (code, 0);
5757                                 amd64_patch (unordered_check, code);
5758                                 amd64_inc_reg (code, ins->dreg);
5759                                 amd64_patch (jump_to_end, code);
5760                                 break;
5761                         default:
5762                                 break;
5763                         }
5764                         break;
5765                 }
5766                 case OP_FBEQ: {
5767                         guchar *jump = code;
5768                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5769                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5770                         amd64_patch (jump, code);
5771                         break;
5772                 }
5773                 case OP_FBNE_UN:
5774                         /* Branch if C013 != 100 */
5775                         /* branch if !ZF or (PF|CF) */
5776                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5777                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5778                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5779                         break;
5780                 case OP_FBLT:
5781                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5782                         break;
5783                 case OP_FBLT_UN:
5784                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5785                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5786                         break;
5787                 case OP_FBGT:
5788                 case OP_FBGT_UN:
5789                         if (ins->opcode == OP_FBGT) {
5790                                 guchar *br1;
5791
5792                                 /* skip branch if C1=1 */
5793                                 br1 = code;
5794                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5795                                 /* branch if (C0 | C3) = 1 */
5796                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5797                                 amd64_patch (br1, code);
5798                                 break;
5799                         } else {
5800                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5801                         }
5802                         break;
5803                 case OP_FBGE: {
5804                         /* Branch if C013 == 100 or 001 */
5805                         guchar *br1;
5806
5807                         /* skip branch if C1=1 */
5808                         br1 = code;
5809                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5810                         /* branch if (C0 | C3) = 1 */
5811                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5812                         amd64_patch (br1, code);
5813                         break;
5814                 }
5815                 case OP_FBGE_UN:
5816                         /* Branch if C013 == 000 */
5817                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5818                         break;
5819                 case OP_FBLE: {
5820                         /* Branch if C013=000 or 100 */
5821                         guchar *br1;
5822
5823                         /* skip branch if C1=1 */
5824                         br1 = code;
5825                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5826                         /* branch if C0=0 */
5827                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5828                         amd64_patch (br1, code);
5829                         break;
5830                 }
5831                 case OP_FBLE_UN:
5832                         /* Branch if C013 != 001 */
5833                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5834                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5835                         break;
5836                 case OP_CKFINITE:
5837                         /* Transfer value to the fp stack */
5838                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5839                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5840                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5841
5842                         amd64_push_reg (code, AMD64_RAX);
5843                         amd64_fxam (code);
5844                         amd64_fnstsw (code);
5845                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5846                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5847                         amd64_pop_reg (code, AMD64_RAX);
5848                         amd64_fstp (code, 0);
5849                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5850                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5851                         break;
5852                 case OP_TLS_GET: {
5853                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5854                         break;
5855                 }
5856                 case OP_TLS_GET_REG:
5857                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5858                         break;
5859                 case OP_TLS_SET: {
5860                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5861                         break;
5862                 }
5863                 case OP_TLS_SET_REG: {
5864                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5865                         break;
5866                 }
5867                 case OP_MEMORY_BARRIER: {
5868                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5869                                 x86_mfence (code);
5870                         break;
5871                 }
5872                 case OP_ATOMIC_ADD_I4:
5873                 case OP_ATOMIC_ADD_I8: {
5874                         int dreg = ins->dreg;
5875                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5876
5877                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5878                                 dreg = AMD64_R11;
5879
5880                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5881                         amd64_prefix (code, X86_LOCK_PREFIX);
5882                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5883                         /* dreg contains the old value, add with sreg2 value */
5884                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5885
5886                         if (ins->dreg != dreg)
5887                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5888
5889                         break;
5890                 }
5891                 case OP_ATOMIC_EXCHANGE_I4:
5892                 case OP_ATOMIC_EXCHANGE_I8: {
5893                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5894
5895                         /* LOCK prefix is implied. */
5896                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5897                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5898                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5899                         break;
5900                 }
5901                 case OP_ATOMIC_CAS_I4:
5902                 case OP_ATOMIC_CAS_I8: {
5903                         guint32 size;
5904
5905                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5906                                 size = 8;
5907                         else
5908                                 size = 4;
5909
5910                         /*
5911                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5912                          * an explanation of how this works.
5913                          */
5914                         g_assert (ins->sreg3 == AMD64_RAX);
5915                         g_assert (ins->sreg1 != AMD64_RAX);
5916                         g_assert (ins->sreg1 != ins->sreg2);
5917
5918                         amd64_prefix (code, X86_LOCK_PREFIX);
5919                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5920
5921                         if (ins->dreg != AMD64_RAX)
5922                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5923                         break;
5924                 }
5925                 case OP_ATOMIC_LOAD_I1: {
5926                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5927                         break;
5928                 }
5929                 case OP_ATOMIC_LOAD_U1: {
5930                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5931                         break;
5932                 }
5933                 case OP_ATOMIC_LOAD_I2: {
5934                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5935                         break;
5936                 }
5937                 case OP_ATOMIC_LOAD_U2: {
5938                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5939                         break;
5940                 }
5941                 case OP_ATOMIC_LOAD_I4: {
5942                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5943                         break;
5944                 }
5945                 case OP_ATOMIC_LOAD_U4:
5946                 case OP_ATOMIC_LOAD_I8:
5947                 case OP_ATOMIC_LOAD_U8: {
5948                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5949                         break;
5950                 }
5951                 case OP_ATOMIC_LOAD_R4: {
5952                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5953                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5954                         break;
5955                 }
5956                 case OP_ATOMIC_LOAD_R8: {
5957                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5958                         break;
5959                 }
5960                 case OP_ATOMIC_STORE_I1:
5961                 case OP_ATOMIC_STORE_U1:
5962                 case OP_ATOMIC_STORE_I2:
5963                 case OP_ATOMIC_STORE_U2:
5964                 case OP_ATOMIC_STORE_I4:
5965                 case OP_ATOMIC_STORE_U4:
5966                 case OP_ATOMIC_STORE_I8:
5967                 case OP_ATOMIC_STORE_U8: {
5968                         int size;
5969
5970                         switch (ins->opcode) {
5971                         case OP_ATOMIC_STORE_I1:
5972                         case OP_ATOMIC_STORE_U1:
5973                                 size = 1;
5974                                 break;
5975                         case OP_ATOMIC_STORE_I2:
5976                         case OP_ATOMIC_STORE_U2:
5977                                 size = 2;
5978                                 break;
5979                         case OP_ATOMIC_STORE_I4:
5980                         case OP_ATOMIC_STORE_U4:
5981                                 size = 4;
5982                                 break;
5983                         case OP_ATOMIC_STORE_I8:
5984                         case OP_ATOMIC_STORE_U8:
5985                                 size = 8;
5986                                 break;
5987                         }
5988
5989                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5990
5991                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5992                                 x86_mfence (code);
5993                         break;
5994                 }
5995                 case OP_ATOMIC_STORE_R4: {
5996                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5997                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5998
5999                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6000                                 x86_mfence (code);
6001                         break;
6002                 }
6003                 case OP_ATOMIC_STORE_R8: {
6004                         x86_nop (code);
6005                         x86_nop (code);
6006                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
6007                         x86_nop (code);
6008                         x86_nop (code);
6009
6010                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6011                                 x86_mfence (code);
6012                         break;
6013                 }
6014                 case OP_CARD_TABLE_WBARRIER: {
6015                         int ptr = ins->sreg1;
6016                         int value = ins->sreg2;
6017                         guchar *br = 0;
6018                         int nursery_shift, card_table_shift;
6019                         gpointer card_table_mask;
6020                         size_t nursery_size;
6021
6022                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
6023                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
6024                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
6025
6026                         /*If either point to the stack we can simply avoid the WB. This happens due to
6027                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6028                          */
6029                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
6030                                 continue;
6031
6032                         /*
6033                          * We need one register we can clobber, we choose EDX and make sreg1
6034                          * fixed EAX to work around limitations in the local register allocator.
6035                          * sreg2 might get allocated to EDX, but that is not a problem since
6036                          * we use it before clobbering EDX.
6037                          */
6038                         g_assert (ins->sreg1 == AMD64_RAX);
6039
6040                         /*
6041                          * This is the code we produce:
6042                          *
6043                          *   edx = value
6044                          *   edx >>= nursery_shift
6045                          *   cmp edx, (nursery_start >> nursery_shift)
6046                          *   jne done
6047                          *   edx = ptr
6048                          *   edx >>= card_table_shift
6049                          *   edx += cardtable
6050                          *   [edx] = 1
6051                          * done:
6052                          */
6053
6054                         if (mono_gc_card_table_nursery_check ()) {
6055                                 if (value != AMD64_RDX)
6056                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
6057                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
6058                                 if (shifted_nursery_start >> 31) {
6059                                         /*
6060                                          * The value we need to compare against is 64 bits, so we need
6061                                          * another spare register.  We use RBX, which we save and
6062                                          * restore.
6063                                          */
6064                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
6065                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
6066                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
6067                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
6068                                 } else {
6069                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
6070                                 }
6071                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
6072                         }
6073                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
6074                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
6075                         if (card_table_mask)
6076                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
6077
6078                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6079                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
6080
6081                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
6082
6083                         if (mono_gc_card_table_nursery_check ())
6084                                 x86_patch (br, code);
6085                         break;
6086                 }
6087 #ifdef MONO_ARCH_SIMD_INTRINSICS
6088                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6089                 case OP_ADDPS:
6090                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_DIVPS:
6093                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_MULPS:
6096                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098                 case OP_SUBPS:
6099                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
6100                         break;
6101                 case OP_MAXPS:
6102                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
6103                         break;
6104                 case OP_MINPS:
6105                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
6106                         break;
6107                 case OP_COMPPS:
6108                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6109                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6110                         break;
6111                 case OP_ANDPS:
6112                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114                 case OP_ANDNPS:
6115                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6116                         break;
6117                 case OP_ORPS:
6118                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6119                         break;
6120                 case OP_XORPS:
6121                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6122                         break;
6123                 case OP_SQRTPS:
6124                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6125                         break;
6126                 case OP_RSQRTPS:
6127                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6128                         break;
6129                 case OP_RCPPS:
6130                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6131                         break;
6132                 case OP_ADDSUBPS:
6133                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6134                         break;
6135                 case OP_HADDPS:
6136                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6137                         break;
6138                 case OP_HSUBPS:
6139                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6140                         break;
6141                 case OP_DUPPS_HIGH:
6142                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6143                         break;
6144                 case OP_DUPPS_LOW:
6145                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6146                         break;
6147
6148                 case OP_PSHUFLEW_HIGH:
6149                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6150                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6151                         break;
6152                 case OP_PSHUFLEW_LOW:
6153                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6154                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6155                         break;
6156                 case OP_PSHUFLED:
6157                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6158                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6159                         break;
6160                 case OP_SHUFPS:
6161                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6162                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6163                         break;
6164                 case OP_SHUFPD:
6165                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6166                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6167                         break;
6168
6169                 case OP_ADDPD:
6170                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6171                         break;
6172                 case OP_DIVPD:
6173                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6174                         break;
6175                 case OP_MULPD:
6176                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6177                         break;
6178                 case OP_SUBPD:
6179                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6180                         break;
6181                 case OP_MAXPD:
6182                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6183                         break;
6184                 case OP_MINPD:
6185                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6186                         break;
6187                 case OP_COMPPD:
6188                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6189                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6190                         break;
6191                 case OP_ANDPD:
6192                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194                 case OP_ANDNPD:
6195                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6196                         break;
6197                 case OP_ORPD:
6198                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6199                         break;
6200                 case OP_XORPD:
6201                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6202                         break;
6203                 case OP_SQRTPD:
6204                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6205                         break;
6206                 case OP_ADDSUBPD:
6207                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6208                         break;
6209                 case OP_HADDPD:
6210                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6211                         break;
6212                 case OP_HSUBPD:
6213                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6214                         break;
6215                 case OP_DUPPD:
6216                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6217                         break;
6218
6219                 case OP_EXTRACT_MASK:
6220                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6221                         break;
6222
6223                 case OP_PAND:
6224                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6225                         break;
6226                 case OP_POR:
6227                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6228                         break;
6229                 case OP_PXOR:
6230                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6231                         break;
6232
6233                 case OP_PADDB:
6234                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6235                         break;
6236                 case OP_PADDW:
6237                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6238                         break;
6239                 case OP_PADDD:
6240                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6241                         break;
6242                 case OP_PADDQ:
6243                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6244                         break;
6245
6246                 case OP_PSUBB:
6247                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6248                         break;
6249                 case OP_PSUBW:
6250                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6251                         break;
6252                 case OP_PSUBD:
6253                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6254                         break;
6255                 case OP_PSUBQ:
6256                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6257                         break;
6258
6259                 case OP_PMAXB_UN:
6260                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6261                         break;
6262                 case OP_PMAXW_UN:
6263                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6264                         break;
6265                 case OP_PMAXD_UN:
6266                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6267                         break;
6268
6269                 case OP_PMAXB:
6270                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6271                         break;
6272                 case OP_PMAXW:
6273                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6274                         break;
6275                 case OP_PMAXD:
6276                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6277                         break;
6278
6279                 case OP_PAVGB_UN:
6280                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6281                         break;
6282                 case OP_PAVGW_UN:
6283                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6284                         break;
6285
6286                 case OP_PMINB_UN:
6287                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6288                         break;
6289                 case OP_PMINW_UN:
6290                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6291                         break;
6292                 case OP_PMIND_UN:
6293                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6294                         break;
6295
6296                 case OP_PMINB:
6297                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6298                         break;
6299                 case OP_PMINW:
6300                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6301                         break;
6302                 case OP_PMIND:
6303                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6304                         break;
6305
6306                 case OP_PCMPEQB:
6307                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6308                         break;
6309                 case OP_PCMPEQW:
6310                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6311                         break;
6312                 case OP_PCMPEQD:
6313                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6314                         break;
6315                 case OP_PCMPEQQ:
6316                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6317                         break;
6318
6319                 case OP_PCMPGTB:
6320                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6321                         break;
6322                 case OP_PCMPGTW:
6323                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6324                         break;
6325                 case OP_PCMPGTD:
6326                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6327                         break;
6328                 case OP_PCMPGTQ:
6329                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6330                         break;
6331
6332                 case OP_PSUM_ABS_DIFF:
6333                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6334                         break;
6335
6336                 case OP_UNPACK_LOWB:
6337                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6338                         break;
6339                 case OP_UNPACK_LOWW:
6340                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6341                         break;
6342                 case OP_UNPACK_LOWD:
6343                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6344                         break;
6345                 case OP_UNPACK_LOWQ:
6346                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6347                         break;
6348                 case OP_UNPACK_LOWPS:
6349                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6350                         break;
6351                 case OP_UNPACK_LOWPD:
6352                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6353                         break;
6354
6355                 case OP_UNPACK_HIGHB:
6356                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6357                         break;
6358                 case OP_UNPACK_HIGHW:
6359                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6360                         break;
6361                 case OP_UNPACK_HIGHD:
6362                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6363                         break;
6364                 case OP_UNPACK_HIGHQ:
6365                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6366                         break;
6367                 case OP_UNPACK_HIGHPS:
6368                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6369                         break;
6370                 case OP_UNPACK_HIGHPD:
6371                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6372                         break;
6373
6374                 case OP_PACKW:
6375                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6376                         break;
6377                 case OP_PACKD:
6378                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6379                         break;
6380                 case OP_PACKW_UN:
6381                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6382                         break;
6383                 case OP_PACKD_UN:
6384                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6385                         break;
6386
6387                 case OP_PADDB_SAT_UN:
6388                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6389                         break;
6390                 case OP_PSUBB_SAT_UN:
6391                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6392                         break;
6393                 case OP_PADDW_SAT_UN:
6394                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6395                         break;
6396                 case OP_PSUBW_SAT_UN:
6397                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6398                         break;
6399
6400                 case OP_PADDB_SAT:
6401                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6402                         break;
6403                 case OP_PSUBB_SAT:
6404                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6405                         break;
6406                 case OP_PADDW_SAT:
6407                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6408                         break;
6409                 case OP_PSUBW_SAT:
6410                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6411                         break;
6412
6413                 case OP_PMULW:
6414                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6415                         break;
6416                 case OP_PMULD:
6417                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6418                         break;
6419                 case OP_PMULQ:
6420                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6421                         break;
6422                 case OP_PMULW_HIGH_UN:
6423                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6424                         break;
6425                 case OP_PMULW_HIGH:
6426                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6427                         break;
6428
6429                 case OP_PSHRW:
6430                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6431                         break;
6432                 case OP_PSHRW_REG:
6433                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6434                         break;
6435
6436                 case OP_PSARW:
6437                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6438                         break;
6439                 case OP_PSARW_REG:
6440                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6441                         break;
6442
6443                 case OP_PSHLW:
6444                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6445                         break;
6446                 case OP_PSHLW_REG:
6447                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6448                         break;
6449
6450                 case OP_PSHRD:
6451                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6452                         break;
6453                 case OP_PSHRD_REG:
6454                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6455                         break;
6456
6457                 case OP_PSARD:
6458                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6459                         break;
6460                 case OP_PSARD_REG:
6461                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6462                         break;
6463
6464                 case OP_PSHLD:
6465                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6466                         break;
6467                 case OP_PSHLD_REG:
6468                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6469                         break;
6470
6471                 case OP_PSHRQ:
6472                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6473                         break;
6474                 case OP_PSHRQ_REG:
6475                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6476                         break;
6477
6478                 /*TODO: This is appart of the sse spec but not added
6479                 case OP_PSARQ:
6480                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6481                         break;
6482                 case OP_PSARQ_REG:
6483                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6484                         break;
6485                 */
6486
6487                 case OP_PSHLQ:
6488                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6489                         break;
6490                 case OP_PSHLQ_REG:
6491                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6492                         break;
6493                 case OP_CVTDQ2PD:
6494                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6495                         break;
6496                 case OP_CVTDQ2PS:
6497                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6498                         break;
6499                 case OP_CVTPD2DQ:
6500                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6501                         break;
6502                 case OP_CVTPD2PS:
6503                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6504                         break;
6505                 case OP_CVTPS2DQ:
6506                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6507                         break;
6508                 case OP_CVTPS2PD:
6509                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6510                         break;
6511                 case OP_CVTTPD2DQ:
6512                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6513                         break;
6514                 case OP_CVTTPS2DQ:
6515                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6516                         break;
6517
6518                 case OP_ICONV_TO_X:
6519                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6520                         break;
6521                 case OP_EXTRACT_I4:
6522                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6523                         break;
6524                 case OP_EXTRACT_I8:
6525                         if (ins->inst_c0) {
6526                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6527                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6528                         } else {
6529                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6530                         }
6531                         break;
6532                 case OP_EXTRACT_I1:
6533                 case OP_EXTRACT_U1:
6534                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6535                         if (ins->inst_c0)
6536                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6537                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6538                         break;
6539                 case OP_EXTRACT_I2:
6540                 case OP_EXTRACT_U2:
6541                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6542                         if (ins->inst_c0)
6543                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6544                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6545                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6546                         break;
6547                 case OP_EXTRACT_R8:
6548                         if (ins->inst_c0)
6549                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6550                         else
6551                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6552                         break;
6553                 case OP_INSERT_I2:
6554                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6555                         break;
6556                 case OP_EXTRACTX_U2:
6557                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6558                         break;
6559                 case OP_INSERTX_U1_SLOW:
6560                         /*sreg1 is the extracted ireg (scratch)
6561                         /sreg2 is the to be inserted ireg (scratch)
6562                         /dreg is the xreg to receive the value*/
6563
6564                         /*clear the bits from the extracted word*/
6565                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6566                         /*shift the value to insert if needed*/
6567                         if (ins->inst_c0 & 1)
6568                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6569                         /*join them together*/
6570                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6571                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6572                         break;
6573                 case OP_INSERTX_I4_SLOW:
6574                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6575                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6576                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6577                         break;
6578                 case OP_INSERTX_I8_SLOW:
6579                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6580                         if (ins->inst_c0)
6581                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6582                         else
6583                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6584                         break;
6585
6586                 case OP_INSERTX_R4_SLOW:
6587                         switch (ins->inst_c0) {
6588                         case 0:
6589                                 if (cfg->r4fp)
6590                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6591                                 else
6592                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6593                                 break;
6594                         case 1:
6595                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6596                                 if (cfg->r4fp)
6597                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6598                                 else
6599                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6600                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6601                                 break;
6602                         case 2:
6603                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6604                                 if (cfg->r4fp)
6605                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6606                                 else
6607                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6608                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6609                                 break;
6610                         case 3:
6611                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6612                                 if (cfg->r4fp)
6613                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6614                                 else
6615                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6616                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6617                                 break;
6618                         }
6619                         break;
6620                 case OP_INSERTX_R8_SLOW:
6621                         if (ins->inst_c0)
6622                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6623                         else
6624                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6625                         break;
6626                 case OP_STOREX_MEMBASE_REG:
6627                 case OP_STOREX_MEMBASE:
6628                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6629                         break;
6630                 case OP_LOADX_MEMBASE:
6631                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6632                         break;
6633                 case OP_LOADX_ALIGNED_MEMBASE:
6634                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6635                         break;
6636                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6637                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6638                         break;
6639                 case OP_STOREX_NTA_MEMBASE_REG:
6640                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6641                         break;
6642                 case OP_PREFETCH_MEMBASE:
6643                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6644                         break;
6645
6646                 case OP_XMOVE:
6647                         /*FIXME the peephole pass should have killed this*/
6648                         if (ins->dreg != ins->sreg1)
6649                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6650                         break;
6651                 case OP_XZERO:
6652                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6653                         break;
6654                 case OP_ICONV_TO_R4_RAW:
6655                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6656                         break;
6657
6658                 case OP_FCONV_TO_R8_X:
6659                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6660                         break;
6661
6662                 case OP_XCONV_R8_TO_I4:
6663                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6664                         switch (ins->backend.source_opcode) {
6665                         case OP_FCONV_TO_I1:
6666                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6667                                 break;
6668                         case OP_FCONV_TO_U1:
6669                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6670                                 break;
6671                         case OP_FCONV_TO_I2:
6672                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6673                                 break;
6674                         case OP_FCONV_TO_U2:
6675                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6676                                 break;
6677                         }
6678                         break;
6679
6680                 case OP_EXPAND_I2:
6681                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6682                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6683                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6684                         break;
6685                 case OP_EXPAND_I4:
6686                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6687                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6688                         break;
6689                 case OP_EXPAND_I8:
6690                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6691                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6692                         break;
6693                 case OP_EXPAND_R4:
6694                         if (cfg->r4fp) {
6695                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6696                         } else {
6697                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6698                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6699                         }
6700                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6701                         break;
6702                 case OP_EXPAND_R8:
6703                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6704                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6705                         break;
6706 #endif
6707                 case OP_LIVERANGE_START: {
6708                         if (cfg->verbose_level > 1)
6709                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6710                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6711                         break;
6712                 }
6713                 case OP_LIVERANGE_END: {
6714                         if (cfg->verbose_level > 1)
6715                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6716                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6717                         break;
6718                 }
6719                 case OP_GC_SAFE_POINT: {
6720                         const char *polling_func = NULL;
6721                         int compare_val = 0;
6722                         guint8 *br [1];
6723
6724 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6725                         polling_func = "mono_nacl_gc";
6726                         compare_val = 0xFFFFFFFF;
6727 #else
6728                         g_assert (mono_threads_is_coop_enabled ());
6729                         polling_func = "mono_threads_state_poll";
6730                         compare_val = 1;
6731 #endif
6732
6733                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6734                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6735                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6736                         amd64_patch (br[0], code);
6737                         break;
6738                 }
6739
6740                 case OP_GC_LIVENESS_DEF:
6741                 case OP_GC_LIVENESS_USE:
6742                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6743                         ins->backend.pc_offset = code - cfg->native_code;
6744                         break;
6745                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6746                         ins->backend.pc_offset = code - cfg->native_code;
6747                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6748                         break;
6749                 default:
6750                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6751                         g_assert_not_reached ();
6752                 }
6753
6754                 if ((code - cfg->native_code - offset) > max_len) {
6755 #if !defined(__native_client_codegen__)
6756                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6757                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6758                         g_assert_not_reached ();
6759 #endif
6760                 }
6761         }
6762
6763         cfg->code_len = code - cfg->native_code;
6764 }
6765
6766 #endif /* DISABLE_JIT */
6767
6768 void
6769 mono_arch_register_lowlevel_calls (void)
6770 {
6771         /* The signature doesn't matter */
6772         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6773 }
6774
6775 void
6776 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6777 {
6778         unsigned char *ip = ji->ip.i + code;
6779
6780         /*
6781          * Debug code to help track down problems where the target of a near call is
6782          * is not valid.
6783          */
6784         if (amd64_is_near_call (ip)) {
6785                 gint64 disp = (guint8*)target - (guint8*)ip;
6786
6787                 if (!amd64_is_imm32 (disp)) {
6788                         printf ("TYPE: %d\n", ji->type);
6789                         switch (ji->type) {
6790                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6791                                 printf ("V: %s\n", ji->data.name);
6792                                 break;
6793                         case MONO_PATCH_INFO_METHOD_JUMP:
6794                         case MONO_PATCH_INFO_METHOD:
6795                                 printf ("V: %s\n", ji->data.method->name);
6796                                 break;
6797                         default:
6798                                 break;
6799                         }
6800                 }
6801         }
6802
6803         amd64_patch (ip, (gpointer)target);
6804 }
6805
6806 #ifndef DISABLE_JIT
6807
6808 static int
6809 get_max_epilog_size (MonoCompile *cfg)
6810 {
6811         int max_epilog_size = 16;
6812
6813         if (cfg->method->save_lmf)
6814                 max_epilog_size += 256;
6815
6816         if (mono_jit_trace_calls != NULL)
6817                 max_epilog_size += 50;
6818
6819         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6820                 max_epilog_size += 50;
6821
6822         max_epilog_size += (AMD64_NREG * 2);
6823
6824         return max_epilog_size;
6825 }
6826
6827 /*
6828  * This macro is used for testing whenever the unwinder works correctly at every point
6829  * where an async exception can happen.
6830  */
6831 /* This will generate a SIGSEGV at the given point in the code */
6832 #define async_exc_point(code) do { \
6833     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6834          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6835              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6836          cfg->arch.async_point_count ++; \
6837     } \
6838 } while (0)
6839
6840 guint8 *
6841 mono_arch_emit_prolog (MonoCompile *cfg)
6842 {
6843         MonoMethod *method = cfg->method;
6844         MonoBasicBlock *bb;
6845         MonoMethodSignature *sig;
6846         MonoInst *ins;
6847         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6848         guint8 *code;
6849         CallInfo *cinfo;
6850         MonoInst *lmf_var = cfg->lmf_var;
6851         gboolean args_clobbered = FALSE;
6852         gboolean trace = FALSE;
6853 #ifdef __native_client_codegen__
6854         guint alignment_check;
6855 #endif
6856
6857         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6858
6859 #if defined(__default_codegen__)
6860         code = cfg->native_code = g_malloc (cfg->code_size);
6861 #elif defined(__native_client_codegen__)
6862         /* native_code_alloc is not 32-byte aligned, native_code is. */
6863         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6864
6865         /* Align native_code to next nearest kNaclAlignment byte. */
6866         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6867         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6868
6869         code = cfg->native_code;
6870
6871         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6872         g_assert (alignment_check == 0);
6873 #endif
6874
6875         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6876                 trace = TRUE;
6877
6878         /* Amount of stack space allocated by register saving code */
6879         pos = 0;
6880
6881         /* Offset between RSP and the CFA */
6882         cfa_offset = 0;
6883
6884         /*
6885          * The prolog consists of the following parts:
6886          * FP present:
6887          * - push rbp, mov rbp, rsp
6888          * - save callee saved regs using pushes
6889          * - allocate frame
6890          * - save rgctx if needed
6891          * - save lmf if needed
6892          * FP not present:
6893          * - allocate frame
6894          * - save rgctx if needed
6895          * - save lmf if needed
6896          * - save callee saved regs using moves
6897          */
6898
6899         // CFA = sp + 8
6900         cfa_offset = 8;
6901         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6902         // IP saved at CFA - 8
6903         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6904         async_exc_point (code);
6905         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6906
6907         if (!cfg->arch.omit_fp) {
6908                 amd64_push_reg (code, AMD64_RBP);
6909                 cfa_offset += 8;
6910                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6911                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6912                 async_exc_point (code);
6913 #ifdef TARGET_WIN32
6914                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6915 #endif
6916                 /* These are handled automatically by the stack marking code */
6917                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6918
6919                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6920                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6921                 async_exc_point (code);
6922 #ifdef TARGET_WIN32
6923                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6924 #endif
6925         }
6926
6927         /* The param area is always at offset 0 from sp */
6928         /* This needs to be allocated here, since it has to come after the spill area */
6929         if (cfg->param_area) {
6930                 if (cfg->arch.omit_fp)
6931                         // FIXME:
6932                         g_assert_not_reached ();
6933                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6934         }
6935
6936         if (cfg->arch.omit_fp) {
6937                 /*
6938                  * On enter, the stack is misaligned by the pushing of the return
6939                  * address. It is either made aligned by the pushing of %rbp, or by
6940                  * this.
6941                  */
6942                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6943                 if ((alloc_size % 16) == 0) {
6944                         alloc_size += 8;
6945                         /* Mark the padding slot as NOREF */
6946                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6947                 }
6948         } else {
6949                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6950                 if (cfg->stack_offset != alloc_size) {
6951                         /* Mark the padding slot as NOREF */
6952                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6953                 }
6954                 cfg->arch.sp_fp_offset = alloc_size;
6955                 alloc_size -= pos;
6956         }
6957
6958         cfg->arch.stack_alloc_size = alloc_size;
6959
6960         /* Allocate stack frame */
6961         if (alloc_size) {
6962                 /* See mono_emit_stack_alloc */
6963 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6964                 guint32 remaining_size = alloc_size;
6965                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6966                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6967                 guint32 offset = code - cfg->native_code;
6968                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6969                         while (required_code_size >= (cfg->code_size - offset))
6970                                 cfg->code_size *= 2;
6971                         cfg->native_code = mono_realloc_native_code (cfg);
6972                         code = cfg->native_code + offset;
6973                         cfg->stat_code_reallocs++;
6974                 }
6975
6976                 while (remaining_size >= 0x1000) {
6977                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6978                         if (cfg->arch.omit_fp) {
6979                                 cfa_offset += 0x1000;
6980                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6981                         }
6982                         async_exc_point (code);
6983 #ifdef TARGET_WIN32
6984                         if (cfg->arch.omit_fp)
6985                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6986 #endif
6987
6988                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6989                         remaining_size -= 0x1000;
6990                 }
6991                 if (remaining_size) {
6992                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6993                         if (cfg->arch.omit_fp) {
6994                                 cfa_offset += remaining_size;
6995                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6996                                 async_exc_point (code);
6997                         }
6998 #ifdef TARGET_WIN32
6999                         if (cfg->arch.omit_fp)
7000                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7001 #endif
7002                 }
7003 #else
7004                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
7005                 if (cfg->arch.omit_fp) {
7006                         cfa_offset += alloc_size;
7007                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7008                         async_exc_point (code);
7009                 }
7010 #endif
7011         }
7012
7013         /* Stack alignment check */
7014 #if 0
7015         {
7016                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
7017                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
7018                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
7019                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
7020                 amd64_breakpoint (code);
7021         }
7022 #endif
7023
7024         if (mini_get_debug_options ()->init_stacks) {
7025                 /* Fill the stack frame with a dummy value to force deterministic behavior */
7026
7027                 /* Save registers to the red zone */
7028                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
7029                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
7030
7031                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
7032                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
7033                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
7034
7035                 amd64_cld (code);
7036 #if defined(__default_codegen__)
7037                 amd64_prefix (code, X86_REP_PREFIX);
7038                 amd64_stosl (code);
7039 #elif defined(__native_client_codegen__)
7040                 /* NaCl stos pseudo-instruction */
7041                 amd64_codegen_pre (code);
7042                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
7043                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
7044                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7045                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
7046                 amd64_prefix (code, X86_REP_PREFIX);
7047                 amd64_stosl (code);
7048                 amd64_codegen_post (code);
7049 #endif /* __native_client_codegen__ */
7050
7051                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
7052                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
7053         }
7054
7055         /* Save LMF */
7056         if (method->save_lmf)
7057                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
7058
7059         /* Save callee saved registers */
7060         if (cfg->arch.omit_fp) {
7061                 save_area_offset = cfg->arch.reg_save_area_offset;
7062                 /* Save caller saved registers after sp is adjusted */
7063                 /* The registers are saved at the bottom of the frame */
7064                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7065         } else {
7066                 /* The registers are saved just below the saved rbp */
7067                 save_area_offset = cfg->arch.reg_save_area_offset;
7068         }
7069
7070         for (i = 0; i < AMD64_NREG; ++i) {
7071                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7072                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
7073
7074                         if (cfg->arch.omit_fp) {
7075                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
7076                                 /* These are handled automatically by the stack marking code */
7077                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
7078                         } else {
7079                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
7080                                 // FIXME: GC
7081                         }
7082
7083                         save_area_offset += 8;
7084                         async_exc_point (code);
7085                 }
7086         }
7087
7088         /* store runtime generic context */
7089         if (cfg->rgctx_var) {
7090                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
7091                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
7092
7093                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7094
7095                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7096                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7097         }
7098
7099         /* compute max_length in order to use short forward jumps */
7100         max_epilog_size = get_max_epilog_size (cfg);
7101         if (cfg->opt & MONO_OPT_BRANCH) {
7102                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
7103                         MonoInst *ins;
7104                         int max_length = 0;
7105
7106                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
7107                                 max_length += 6;
7108                         /* max alignment for loops */
7109                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7110                                 max_length += LOOP_ALIGNMENT;
7111 #ifdef __native_client_codegen__
7112                         /* max alignment for native client */
7113                         max_length += kNaClAlignment;
7114 #endif
7115
7116                         MONO_BB_FOR_EACH_INS (bb, ins) {
7117 #ifdef __native_client_codegen__
7118                                 {
7119                                         int space_in_block = kNaClAlignment -
7120                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7121                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7122                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
7123                                                 max_length += space_in_block;
7124                                         }
7125                                 }
7126 #endif  /*__native_client_codegen__*/
7127                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7128                         }
7129
7130                         /* Take prolog and epilog instrumentation into account */
7131                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7132                                 max_length += max_epilog_size;
7133
7134                         bb->max_length = max_length;
7135                 }
7136         }
7137
7138         sig = mono_method_signature (method);
7139         pos = 0;
7140
7141         cinfo = cfg->arch.cinfo;
7142
7143         if (sig->ret->type != MONO_TYPE_VOID) {
7144                 /* Save volatile arguments to the stack */
7145                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7146                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7147         }
7148
7149         /* Keep this in sync with emit_load_volatile_arguments */
7150         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7151                 ArgInfo *ainfo = cinfo->args + i;
7152
7153                 ins = cfg->args [i];
7154
7155                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7156                         /* Unused arguments */
7157                         continue;
7158
7159                 /* Save volatile arguments to the stack */
7160                 if (ins->opcode != OP_REGVAR) {
7161                         switch (ainfo->storage) {
7162                         case ArgInIReg: {
7163                                 guint32 size = 8;
7164
7165                                 /* FIXME: I1 etc */
7166                                 /*
7167                                 if (stack_offset & 0x1)
7168                                         size = 1;
7169                                 else if (stack_offset & 0x2)
7170                                         size = 2;
7171                                 else if (stack_offset & 0x4)
7172                                         size = 4;
7173                                 else
7174                                         size = 8;
7175                                 */
7176                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7177
7178                                 /*
7179                                  * Save the original location of 'this',
7180                                  * get_generic_info_from_stack_frame () needs this to properly look up
7181                                  * the argument value during the handling of async exceptions.
7182                                  */
7183                                 if (ins == cfg->args [0]) {
7184                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7185                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7186                                 }
7187                                 break;
7188                         }
7189                         case ArgInFloatSSEReg:
7190                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7191                                 break;
7192                         case ArgInDoubleSSEReg:
7193                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7194                                 break;
7195                         case ArgValuetypeInReg:
7196                                 for (quad = 0; quad < 2; quad ++) {
7197                                         switch (ainfo->pair_storage [quad]) {
7198                                         case ArgInIReg:
7199                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7200                                                 break;
7201                                         case ArgInFloatSSEReg:
7202                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7203                                                 break;
7204                                         case ArgInDoubleSSEReg:
7205                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7206                                                 break;
7207                                         case ArgNone:
7208                                                 break;
7209                                         default:
7210                                                 g_assert_not_reached ();
7211                                         }
7212                                 }
7213                                 break;
7214                         case ArgValuetypeAddrInIReg:
7215                                 if (ainfo->pair_storage [0] == ArgInIReg)
7216                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7217                                 break;
7218                         default:
7219                                 break;
7220                         }
7221                 } else {
7222                         /* Argument allocated to (non-volatile) register */
7223                         switch (ainfo->storage) {
7224                         case ArgInIReg:
7225                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7226                                 break;
7227                         case ArgOnStack:
7228                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7229                                 break;
7230                         default:
7231                                 g_assert_not_reached ();
7232                         }
7233
7234                         if (ins == cfg->args [0]) {
7235                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7236                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7237                         }
7238                 }
7239         }
7240
7241         if (cfg->method->save_lmf)
7242                 args_clobbered = TRUE;
7243
7244         if (trace) {
7245                 args_clobbered = TRUE;
7246                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7247         }
7248
7249         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7250                 args_clobbered = TRUE;
7251
7252         /*
7253          * Optimize the common case of the first bblock making a call with the same
7254          * arguments as the method. This works because the arguments are still in their
7255          * original argument registers.
7256          * FIXME: Generalize this
7257          */
7258         if (!args_clobbered) {
7259                 MonoBasicBlock *first_bb = cfg->bb_entry;
7260                 MonoInst *next;
7261                 int filter = FILTER_IL_SEQ_POINT;
7262
7263                 next = mono_bb_first_inst (first_bb, filter);
7264                 if (!next && first_bb->next_bb) {
7265                         first_bb = first_bb->next_bb;
7266                         next = mono_bb_first_inst (first_bb, filter);
7267                 }
7268
7269                 if (first_bb->in_count > 1)
7270                         next = NULL;
7271
7272                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7273                         ArgInfo *ainfo = cinfo->args + i;
7274                         gboolean match = FALSE;
7275
7276                         ins = cfg->args [i];
7277                         if (ins->opcode != OP_REGVAR) {
7278                                 switch (ainfo->storage) {
7279                                 case ArgInIReg: {
7280                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7281                                                 if (next->dreg == ainfo->reg) {
7282                                                         NULLIFY_INS (next);
7283                                                         match = TRUE;
7284                                                 } else {
7285                                                         next->opcode = OP_MOVE;
7286                                                         next->sreg1 = ainfo->reg;
7287                                                         /* Only continue if the instruction doesn't change argument regs */
7288                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7289                                                                 match = TRUE;
7290                                                 }
7291                                         }
7292                                         break;
7293                                 }
7294                                 default:
7295                                         break;
7296                                 }
7297                         } else {
7298                                 /* Argument allocated to (non-volatile) register */
7299                                 switch (ainfo->storage) {
7300                                 case ArgInIReg:
7301                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7302                                                 NULLIFY_INS (next);
7303                                                 match = TRUE;
7304                                         }
7305                                         break;
7306                                 default:
7307                                         break;
7308                                 }
7309                         }
7310
7311                         if (match) {
7312                                 next = mono_inst_next (next, filter);
7313                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7314                                 if (!next)
7315                                         break;
7316                         }
7317                 }
7318         }
7319
7320         if (cfg->gen_sdb_seq_points) {
7321                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7322
7323                 /* Initialize seq_point_info_var */
7324                 if (cfg->compile_aot) {
7325                         /* Initialize the variable from a GOT slot */
7326                         /* Same as OP_AOTCONST */
7327                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7328                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7329                         g_assert (info_var->opcode == OP_REGOFFSET);
7330                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7331                 }
7332
7333                 if (cfg->compile_aot) {
7334                         /* Initialize ss_tramp_var */
7335                         ins = cfg->arch.ss_tramp_var;
7336                         g_assert (ins->opcode == OP_REGOFFSET);
7337
7338                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7339                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7340                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7341                 } else {
7342                         /* Initialize ss_tramp_var */
7343                         ins = cfg->arch.ss_tramp_var;
7344                         g_assert (ins->opcode == OP_REGOFFSET);
7345
7346                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7347                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7348
7349                         /* Initialize bp_tramp_var */
7350                         ins = cfg->arch.bp_tramp_var;
7351                         g_assert (ins->opcode == OP_REGOFFSET);
7352
7353                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7354                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7355                 }
7356         }
7357
7358         cfg->code_len = code - cfg->native_code;
7359
7360         g_assert (cfg->code_len < cfg->code_size);
7361
7362         return code;
7363 }
7364
7365 void
7366 mono_arch_emit_epilog (MonoCompile *cfg)
7367 {
7368         MonoMethod *method = cfg->method;
7369         int quad, i;
7370         guint8 *code;
7371         int max_epilog_size;
7372         CallInfo *cinfo;
7373         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7374         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7375
7376         max_epilog_size = get_max_epilog_size (cfg);
7377
7378         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7379                 cfg->code_size *= 2;
7380                 cfg->native_code = mono_realloc_native_code (cfg);
7381                 cfg->stat_code_reallocs++;
7382         }
7383         code = cfg->native_code + cfg->code_len;
7384
7385         cfg->has_unwind_info_for_epilog = TRUE;
7386
7387         /* Mark the start of the epilog */
7388         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7389
7390         /* Save the uwind state which is needed by the out-of-line code */
7391         mono_emit_unwind_op_remember_state (cfg, code);
7392
7393         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7394                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7395
7396         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7397
7398         if (method->save_lmf) {
7399                 /* check if we need to restore protection of the stack after a stack overflow */
7400                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7401                         guint8 *patch;
7402                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7403                         /* we load the value in a separate instruction: this mechanism may be
7404                          * used later as a safer way to do thread interruption
7405                          */
7406                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7407                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7408                         patch = code;
7409                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7410                         /* note that the call trampoline will preserve eax/edx */
7411                         x86_call_reg (code, X86_ECX);
7412                         x86_patch (patch, code);
7413                 } else {
7414                         /* FIXME: maybe save the jit tls in the prolog */
7415                 }
7416                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7417                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7418                 }
7419         }
7420
7421         /* Restore callee saved regs */
7422         for (i = 0; i < AMD64_NREG; ++i) {
7423                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7424                         /* Restore only used_int_regs, not arch.saved_iregs */
7425                         if (cfg->used_int_regs & (1 << i)) {
7426                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7427                                 mono_emit_unwind_op_same_value (cfg, code, i);
7428                                 async_exc_point (code);
7429                         }
7430                         save_area_offset += 8;
7431                 }
7432         }
7433
7434         /* Load returned vtypes into registers if needed */
7435         cinfo = cfg->arch.cinfo;
7436         if (cinfo->ret.storage == ArgValuetypeInReg) {
7437                 ArgInfo *ainfo = &cinfo->ret;
7438                 MonoInst *inst = cfg->ret;
7439
7440                 for (quad = 0; quad < 2; quad ++) {
7441                         switch (ainfo->pair_storage [quad]) {
7442                         case ArgInIReg:
7443                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7444                                 break;
7445                         case ArgInFloatSSEReg:
7446                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7447                                 break;
7448                         case ArgInDoubleSSEReg:
7449                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7450                                 break;
7451                         case ArgNone:
7452                                 break;
7453                         default:
7454                                 g_assert_not_reached ();
7455                         }
7456                 }
7457         }
7458
7459         if (cfg->arch.omit_fp) {
7460                 if (cfg->arch.stack_alloc_size) {
7461                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7462                 }
7463         } else {
7464                 amd64_leave (code);
7465                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7466         }
7467         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7468         async_exc_point (code);
7469         amd64_ret (code);
7470
7471         /* Restore the unwind state to be the same as before the epilog */
7472         mono_emit_unwind_op_restore_state (cfg, code);
7473
7474         cfg->code_len = code - cfg->native_code;
7475
7476         g_assert (cfg->code_len < cfg->code_size);
7477 }
7478
7479 void
7480 mono_arch_emit_exceptions (MonoCompile *cfg)
7481 {
7482         MonoJumpInfo *patch_info;
7483         int nthrows, i;
7484         guint8 *code;
7485         MonoClass *exc_classes [16];
7486         guint8 *exc_throw_start [16], *exc_throw_end [16];
7487         guint32 code_size = 0;
7488
7489         /* Compute needed space */
7490         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7491                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7492                         code_size += 40;
7493                 if (patch_info->type == MONO_PATCH_INFO_R8)
7494                         code_size += 8 + 15; /* sizeof (double) + alignment */
7495                 if (patch_info->type == MONO_PATCH_INFO_R4)
7496                         code_size += 4 + 15; /* sizeof (float) + alignment */
7497                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7498                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7499         }
7500
7501 #ifdef __native_client_codegen__
7502         /* Give us extra room on Native Client.  This could be   */
7503         /* more carefully calculated, but bundle alignment makes */
7504         /* it much trickier, so *2 like other places is good.    */
7505         code_size *= 2;
7506 #endif
7507
7508         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7509                 cfg->code_size *= 2;
7510                 cfg->native_code = mono_realloc_native_code (cfg);
7511                 cfg->stat_code_reallocs++;
7512         }
7513
7514         code = cfg->native_code + cfg->code_len;
7515
7516         /* add code to raise exceptions */
7517         nthrows = 0;
7518         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7519                 switch (patch_info->type) {
7520                 case MONO_PATCH_INFO_EXC: {
7521                         MonoClass *exc_class;
7522                         guint8 *buf, *buf2;
7523                         guint32 throw_ip;
7524
7525                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7526
7527                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7528                         g_assert (exc_class);
7529                         throw_ip = patch_info->ip.i;
7530
7531                         //x86_breakpoint (code);
7532                         /* Find a throw sequence for the same exception class */
7533                         for (i = 0; i < nthrows; ++i)
7534                                 if (exc_classes [i] == exc_class)
7535                                         break;
7536                         if (i < nthrows) {
7537                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7538                                 x86_jump_code (code, exc_throw_start [i]);
7539                                 patch_info->type = MONO_PATCH_INFO_NONE;
7540                         }
7541                         else {
7542                                 buf = code;
7543                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7544                                 buf2 = code;
7545
7546                                 if (nthrows < 16) {
7547                                         exc_classes [nthrows] = exc_class;
7548                                         exc_throw_start [nthrows] = code;
7549                                 }
7550                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7551
7552                                 patch_info->type = MONO_PATCH_INFO_NONE;
7553
7554                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7555
7556                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7557                                 while (buf < buf2)
7558                                         x86_nop (buf);
7559
7560                                 if (nthrows < 16) {
7561                                         exc_throw_end [nthrows] = code;
7562                                         nthrows ++;
7563                                 }
7564                         }
7565                         break;
7566                 }
7567                 default:
7568                         /* do nothing */
7569                         break;
7570                 }
7571                 g_assert(code < cfg->native_code + cfg->code_size);
7572         }
7573
7574         /* Handle relocations with RIP relative addressing */
7575         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7576                 gboolean remove = FALSE;
7577                 guint8 *orig_code = code;
7578
7579                 switch (patch_info->type) {
7580                 case MONO_PATCH_INFO_R8:
7581                 case MONO_PATCH_INFO_R4: {
7582                         guint8 *pos, *patch_pos;
7583                         guint32 target_pos;
7584
7585                         /* The SSE opcodes require a 16 byte alignment */
7586 #if defined(__default_codegen__)
7587                         code = (guint8*)ALIGN_TO (code, 16);
7588 #elif defined(__native_client_codegen__)
7589                         {
7590                                 /* Pad this out with HLT instructions  */
7591                                 /* or we can get garbage bytes emitted */
7592                                 /* which will fail validation          */
7593                                 guint8 *aligned_code;
7594                                 /* extra align to make room for  */
7595                                 /* mov/push below                      */
7596                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7597                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7598                                 /* The technique of hiding data in an  */
7599                                 /* instruction has a problem here: we  */
7600                                 /* need the data aligned to a 16-byte  */
7601                                 /* boundary but the instruction cannot */
7602                                 /* cross the bundle boundary. so only  */
7603                                 /* odd multiples of 16 can be used     */
7604                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7605                                         aligned_code += 16;
7606                                 }
7607                                 while (code < aligned_code) {
7608                                         *(code++) = 0xf4; /* hlt */
7609                                 }
7610                         }
7611 #endif
7612
7613                         pos = cfg->native_code + patch_info->ip.i;
7614                         if (IS_REX (pos [1])) {
7615                                 patch_pos = pos + 5;
7616                                 target_pos = code - pos - 9;
7617                         }
7618                         else {
7619                                 patch_pos = pos + 4;
7620                                 target_pos = code - pos - 8;
7621                         }
7622
7623                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7624 #ifdef __native_client_codegen__
7625                                 /* Hide 64-bit data in a         */
7626                                 /* "mov imm64, r11" instruction. */
7627                                 /* write it before the start of  */
7628                                 /* the data*/
7629                                 *(code-2) = 0x49; /* prefix      */
7630                                 *(code-1) = 0xbb; /* mov X, %r11 */
7631 #endif
7632                                 *(double*)code = *(double*)patch_info->data.target;
7633                                 code += sizeof (double);
7634                         } else {
7635 #ifdef __native_client_codegen__
7636                                 /* Hide 32-bit data in a        */
7637                                 /* "push imm32" instruction.    */
7638                                 *(code-1) = 0x68; /* push */
7639 #endif
7640                                 *(float*)code = *(float*)patch_info->data.target;
7641                                 code += sizeof (float);
7642                         }
7643
7644                         *(guint32*)(patch_pos) = target_pos;
7645
7646                         remove = TRUE;
7647                         break;
7648                 }
7649                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7650                         guint8 *pos;
7651
7652                         if (cfg->compile_aot)
7653                                 continue;
7654
7655                         /*loading is faster against aligned addresses.*/
7656                         code = (guint8*)ALIGN_TO (code, 8);
7657                         memset (orig_code, 0, code - orig_code);
7658
7659                         pos = cfg->native_code + patch_info->ip.i;
7660
7661                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7662                         if (IS_REX (pos [1]))
7663                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7664                         else
7665                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7666
7667                         *(gpointer*)code = (gpointer)patch_info->data.target;
7668                         code += sizeof (gpointer);
7669
7670                         remove = TRUE;
7671                         break;
7672                 }
7673                 default:
7674                         break;
7675                 }
7676
7677                 if (remove) {
7678                         if (patch_info == cfg->patch_info)
7679                                 cfg->patch_info = patch_info->next;
7680                         else {
7681                                 MonoJumpInfo *tmp;
7682
7683                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7684                                         ;
7685                                 tmp->next = patch_info->next;
7686                         }
7687                 }
7688                 g_assert (code < cfg->native_code + cfg->code_size);
7689         }
7690
7691         cfg->code_len = code - cfg->native_code;
7692
7693         g_assert (cfg->code_len < cfg->code_size);
7694
7695 }
7696
7697 #endif /* DISABLE_JIT */
7698
7699 void*
7700 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7701 {
7702         guchar *code = p;
7703         MonoMethodSignature *sig;
7704         MonoInst *inst;
7705         int i, n, stack_area = 0;
7706
7707         /* Keep this in sync with mono_arch_get_argument_info */
7708
7709         if (enable_arguments) {
7710                 /* Allocate a new area on the stack and save arguments there */
7711                 sig = mono_method_signature (cfg->method);
7712
7713                 n = sig->param_count + sig->hasthis;
7714
7715                 stack_area = ALIGN_TO (n * 8, 16);
7716
7717                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7718
7719                 for (i = 0; i < n; ++i) {
7720                         inst = cfg->args [i];
7721
7722                         if (inst->opcode == OP_REGVAR)
7723                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7724                         else {
7725                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7726                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7727                         }
7728                 }
7729         }
7730
7731         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7732         amd64_set_reg_template (code, AMD64_ARG_REG1);
7733         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7734         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7735
7736         if (enable_arguments)
7737                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7738
7739         return code;
7740 }
7741
7742 enum {
7743         SAVE_NONE,
7744         SAVE_STRUCT,
7745         SAVE_EAX,
7746         SAVE_EAX_EDX,
7747         SAVE_XMM
7748 };
7749
7750 void*
7751 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7752 {
7753         guchar *code = p;
7754         int save_mode = SAVE_NONE;
7755         MonoMethod *method = cfg->method;
7756         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7757         int i;
7758
7759         switch (ret_type->type) {
7760         case MONO_TYPE_VOID:
7761                 /* special case string .ctor icall */
7762                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7763                         save_mode = SAVE_EAX;
7764                 else
7765                         save_mode = SAVE_NONE;
7766                 break;
7767         case MONO_TYPE_I8:
7768         case MONO_TYPE_U8:
7769                 save_mode = SAVE_EAX;
7770                 break;
7771         case MONO_TYPE_R4:
7772         case MONO_TYPE_R8:
7773                 save_mode = SAVE_XMM;
7774                 break;
7775         case MONO_TYPE_GENERICINST:
7776                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7777                         save_mode = SAVE_EAX;
7778                         break;
7779                 }
7780                 /* Fall through */
7781         case MONO_TYPE_VALUETYPE:
7782                 save_mode = SAVE_STRUCT;
7783                 break;
7784         default:
7785                 save_mode = SAVE_EAX;
7786                 break;
7787         }
7788
7789         /* Save the result and copy it into the proper argument register */
7790         switch (save_mode) {
7791         case SAVE_EAX:
7792                 amd64_push_reg (code, AMD64_RAX);
7793                 /* Align stack */
7794                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7795                 if (enable_arguments)
7796                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7797                 break;
7798         case SAVE_STRUCT:
7799                 /* FIXME: */
7800                 if (enable_arguments)
7801                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7802                 break;
7803         case SAVE_XMM:
7804                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7805                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7806                 /* Align stack */
7807                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7808                 /*
7809                  * The result is already in the proper argument register so no copying
7810                  * needed.
7811                  */
7812                 break;
7813         case SAVE_NONE:
7814                 break;
7815         default:
7816                 g_assert_not_reached ();
7817         }
7818
7819         /* Set %al since this is a varargs call */
7820         if (save_mode == SAVE_XMM)
7821                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7822         else
7823                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7824
7825         if (preserve_argument_registers) {
7826                 for (i = 0; i < PARAM_REGS; ++i)
7827                         amd64_push_reg (code, param_regs [i]);
7828         }
7829
7830         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7831         amd64_set_reg_template (code, AMD64_ARG_REG1);
7832         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7833
7834         if (preserve_argument_registers) {
7835                 for (i = PARAM_REGS - 1; i >= 0; --i)
7836                         amd64_pop_reg (code, param_regs [i]);
7837         }
7838
7839         /* Restore result */
7840         switch (save_mode) {
7841         case SAVE_EAX:
7842                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7843                 amd64_pop_reg (code, AMD64_RAX);
7844                 break;
7845         case SAVE_STRUCT:
7846                 /* FIXME: */
7847                 break;
7848         case SAVE_XMM:
7849                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7850                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7851                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7852                 break;
7853         case SAVE_NONE:
7854                 break;
7855         default:
7856                 g_assert_not_reached ();
7857         }
7858
7859         return code;
7860 }
7861
7862 void
7863 mono_arch_flush_icache (guint8 *code, gint size)
7864 {
7865         /* Not needed */
7866 }
7867
7868 void
7869 mono_arch_flush_register_windows (void)
7870 {
7871 }
7872
7873 gboolean
7874 mono_arch_is_inst_imm (gint64 imm)
7875 {
7876         return amd64_use_imm32 (imm);
7877 }
7878
7879 /*
7880  * Determine whenever the trap whose info is in SIGINFO is caused by
7881  * integer overflow.
7882  */
7883 gboolean
7884 mono_arch_is_int_overflow (void *sigctx, void *info)
7885 {
7886         MonoContext ctx;
7887         guint8* rip;
7888         int reg;
7889         gint64 value;
7890
7891         mono_sigctx_to_monoctx (sigctx, &ctx);
7892
7893         rip = (guint8*)ctx.gregs [AMD64_RIP];
7894
7895         if (IS_REX (rip [0])) {
7896                 reg = amd64_rex_b (rip [0]);
7897                 rip ++;
7898         }
7899         else
7900                 reg = 0;
7901
7902         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7903                 /* idiv REG */
7904                 reg += x86_modrm_rm (rip [1]);
7905
7906                 value = ctx.gregs [reg];
7907
7908                 if (value == -1)
7909                         return TRUE;
7910         }
7911
7912         return FALSE;
7913 }
7914
7915 guint32
7916 mono_arch_get_patch_offset (guint8 *code)
7917 {
7918         return 3;
7919 }
7920
7921 /**
7922  * mono_breakpoint_clean_code:
7923  *
7924  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7925  * breakpoints in the original code, they are removed in the copy.
7926  *
7927  * Returns TRUE if no sw breakpoint was present.
7928  */
7929 gboolean
7930 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7931 {
7932         /*
7933          * If method_start is non-NULL we need to perform bound checks, since we access memory
7934          * at code - offset we could go before the start of the method and end up in a different
7935          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7936          * instead.
7937          */
7938         if (!method_start || code - offset >= method_start) {
7939                 memcpy (buf, code - offset, size);
7940         } else {
7941                 int diff = code - method_start;
7942                 memset (buf, 0, size);
7943                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7944         }
7945         return TRUE;
7946 }
7947
7948 #if defined(__native_client_codegen__)
7949 /* For membase calls, we want the base register. for Native Client,  */
7950 /* all indirect calls have the following sequence with the given sizes: */
7951 /* mov %eXX,%eXX                                [2-3]   */
7952 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7953 /* and $0xffffffffffffffe0,%r11d                [4]     */
7954 /* add %r15,%r11                                [3]     */
7955 /* callq *%r11                                  [3]     */
7956
7957
7958 /* Determine if code points to a NaCl call-through-register sequence, */
7959 /* (i.e., the last 3 instructions listed above) */
7960 int
7961 is_nacl_call_reg_sequence(guint8* code)
7962 {
7963         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7964                                "\x4d\x03\xdf"     /* add */
7965                                "\x41\xff\xd3";   /* call */
7966         return memcmp(code, sequence, 10) == 0;
7967 }
7968
7969 /* Determine if code points to the first opcode of the mov membase component */
7970 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7971 /* (there could be a REX prefix before the opcode but it is ignored) */
7972 static int
7973 is_nacl_indirect_call_membase_sequence(guint8* code)
7974 {
7975                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7976         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7977                /* and that src reg = dest reg */
7978                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7979                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7980                IS_REX(code[2]) &&
7981                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7982                /* and has dst of r11 and base of r15 */
7983                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7984                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7985 }
7986 #endif /* __native_client_codegen__ */
7987
7988 int
7989 mono_arch_get_this_arg_reg (guint8 *code)
7990 {
7991         return AMD64_ARG_REG1;
7992 }
7993
7994 gpointer
7995 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7996 {
7997         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7998 }
7999
8000 #define MAX_ARCH_DELEGATE_PARAMS 10
8001
8002 static gpointer
8003 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
8004 {
8005         guint8 *code, *start;
8006         GSList *unwind_ops = NULL;
8007         int i;
8008
8009         unwind_ops = mono_arch_get_cie_program ();
8010
8011         if (has_target) {
8012                 start = code = mono_global_codeman_reserve (64);
8013
8014                 /* Replace the this argument with the target */
8015                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8016                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8017                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8018
8019                 g_assert ((code - start) < 64);
8020         } else {
8021                 start = code = mono_global_codeman_reserve (64);
8022
8023                 if (param_count == 0) {
8024                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8025                 } else {
8026                         /* We have to shift the arguments left */
8027                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8028                         for (i = 0; i < param_count; ++i) {
8029 #ifdef TARGET_WIN32
8030                                 if (i < 3)
8031                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8032                                 else
8033                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
8034 #else
8035                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8036 #endif
8037                         }
8038
8039                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8040                 }
8041                 g_assert ((code - start) < 64);
8042         }
8043
8044         nacl_global_codeman_validate (&start, 64, &code);
8045         mono_arch_flush_icache (start, code - start);
8046
8047         if (has_target) {
8048                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8049         } else {
8050                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
8051                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
8052                 g_free (name);
8053         }
8054
8055         if (mono_jit_map_is_enabled ()) {
8056                 char *buff;
8057                 if (has_target)
8058                         buff = (char*)"delegate_invoke_has_target";
8059                 else
8060                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8061                 mono_emit_jit_tramp (start, code - start, buff);
8062                 if (!has_target)
8063                         g_free (buff);
8064         }
8065         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8066
8067         return start;
8068 }
8069
8070 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8071
8072 static gpointer
8073 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
8074 {
8075         guint8 *code, *start;
8076         int size = 20;
8077         char *tramp_name;
8078         GSList *unwind_ops;
8079
8080         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
8081                 return NULL;
8082
8083         start = code = mono_global_codeman_reserve (size);
8084
8085         unwind_ops = mono_arch_get_cie_program ();
8086
8087         /* Replace the this argument with the target */
8088         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8089         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8090
8091         if (load_imt_reg) {
8092                 /* Load the IMT reg */
8093                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8094         }
8095
8096         /* Load the vtable */
8097         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8098         amd64_jump_membase (code, AMD64_RAX, offset);
8099         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8100
8101         if (load_imt_reg)
8102                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
8103         else
8104                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
8105         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
8106         g_free (tramp_name);
8107
8108         return start;
8109 }
8110
8111 /*
8112  * mono_arch_get_delegate_invoke_impls:
8113  *
8114  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8115  * trampolines.
8116  */
8117 GSList*
8118 mono_arch_get_delegate_invoke_impls (void)
8119 {
8120         GSList *res = NULL;
8121         MonoTrampInfo *info;
8122         int i;
8123
8124         get_delegate_invoke_impl (&info, TRUE, 0);
8125         res = g_slist_prepend (res, info);
8126
8127         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8128                 get_delegate_invoke_impl (&info, FALSE, i);
8129                 res = g_slist_prepend (res, info);
8130         }
8131
8132         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8133                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8134                 res = g_slist_prepend (res, info);
8135
8136                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8137                 res = g_slist_prepend (res, info);
8138         }
8139
8140         return res;
8141 }
8142
8143 gpointer
8144 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8145 {
8146         guint8 *code, *start;
8147         int i;
8148
8149         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8150                 return NULL;
8151
8152         /* FIXME: Support more cases */
8153         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8154                 return NULL;
8155
8156         if (has_target) {
8157                 static guint8* cached = NULL;
8158
8159                 if (cached)
8160                         return cached;
8161
8162                 if (mono_aot_only) {
8163                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8164                 } else {
8165                         MonoTrampInfo *info;
8166                         start = get_delegate_invoke_impl (&info, TRUE, 0);
8167                         mono_tramp_info_register (info, NULL);
8168                 }
8169
8170                 mono_memory_barrier ();
8171
8172                 cached = start;
8173         } else {
8174                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8175                 for (i = 0; i < sig->param_count; ++i)
8176                         if (!mono_is_regsize_var (sig->params [i]))
8177                                 return NULL;
8178                 if (sig->param_count > 4)
8179                         return NULL;
8180
8181                 code = cache [sig->param_count];
8182                 if (code)
8183                         return code;
8184
8185                 if (mono_aot_only) {
8186                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8187                         start = mono_aot_get_trampoline (name);
8188                         g_free (name);
8189                 } else {
8190                         MonoTrampInfo *info;
8191                         start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8192                         mono_tramp_info_register (info, NULL);
8193                 }
8194
8195                 mono_memory_barrier ();
8196
8197                 cache [sig->param_count] = start;
8198         }
8199
8200         return start;
8201 }
8202
8203 gpointer
8204 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8205 {
8206         MonoTrampInfo *info;
8207         gpointer code;
8208
8209         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8210         if (code)
8211                 mono_tramp_info_register (info, NULL);
8212         return code;
8213 }
8214
8215 void
8216 mono_arch_finish_init (void)
8217 {
8218 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8219         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8220 #endif
8221 }
8222
8223 void
8224 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8225 {
8226 }
8227
8228 #if defined(__default_codegen__)
8229 #define CMP_SIZE (6 + 1)
8230 #define CMP_REG_REG_SIZE (4 + 1)
8231 #define BR_SMALL_SIZE 2
8232 #define BR_LARGE_SIZE 6
8233 #define MOV_REG_IMM_SIZE 10
8234 #define MOV_REG_IMM_32BIT_SIZE 6
8235 #define JUMP_REG_SIZE (2 + 1)
8236 #elif defined(__native_client_codegen__)
8237 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8238 #define CMP_SIZE ((6 + 1) * 2 - 1)
8239 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8240 #define BR_SMALL_SIZE (2 * 2 - 1)
8241 #define BR_LARGE_SIZE (6 * 2 - 1)
8242 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8243 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8244 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8245 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8246 /* Jump membase's size is large and unpredictable    */
8247 /* in native client, just pad it out a whole bundle. */
8248 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8249 #endif
8250
8251 static int
8252 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8253 {
8254         int i, distance = 0;
8255         for (i = start; i < target; ++i)
8256                 distance += imt_entries [i]->chunk_size;
8257         return distance;
8258 }
8259
8260 /*
8261  * LOCKING: called with the domain lock held
8262  */
8263 gpointer
8264 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8265         gpointer fail_tramp)
8266 {
8267         int i;
8268         int size = 0;
8269         guint8 *code, *start;
8270         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8271         GSList *unwind_ops;
8272
8273         for (i = 0; i < count; ++i) {
8274                 MonoIMTCheckItem *item = imt_entries [i];
8275                 if (item->is_equals) {
8276                         if (item->check_target_idx) {
8277                                 if (!item->compare_done) {
8278                                         if (amd64_use_imm32 ((gint64)item->key))
8279                                                 item->chunk_size += CMP_SIZE;
8280                                         else
8281                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8282                                 }
8283                                 if (item->has_target_code) {
8284                                         item->chunk_size += MOV_REG_IMM_SIZE;
8285                                 } else {
8286                                         if (vtable_is_32bit)
8287                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8288                                         else
8289                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8290 #ifdef __native_client_codegen__
8291                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8292 #endif
8293                                 }
8294                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8295                         } else {
8296                                 if (fail_tramp) {
8297                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8298                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8299                                 } else {
8300                                         if (vtable_is_32bit)
8301                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8302                                         else
8303                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8304                                         item->chunk_size += JUMP_REG_SIZE;
8305                                         /* with assert below:
8306                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8307                                          */
8308 #ifdef __native_client_codegen__
8309                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8310 #endif
8311                                 }
8312                         }
8313                 } else {
8314                         if (amd64_use_imm32 ((gint64)item->key))
8315                                 item->chunk_size += CMP_SIZE;
8316                         else
8317                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8318                         item->chunk_size += BR_LARGE_SIZE;
8319                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8320                 }
8321                 size += item->chunk_size;
8322         }
8323 #if defined(__native_client__) && defined(__native_client_codegen__)
8324         /* In Native Client, we don't re-use thunks, allocate from the */
8325         /* normal code manager paths. */
8326         code = mono_domain_code_reserve (domain, size);
8327 #else
8328         if (fail_tramp)
8329                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8330         else
8331                 code = mono_domain_code_reserve (domain, size);
8332 #endif
8333         start = code;
8334
8335         unwind_ops = mono_arch_get_cie_program ();
8336
8337         for (i = 0; i < count; ++i) {
8338                 MonoIMTCheckItem *item = imt_entries [i];
8339                 item->code_target = code;
8340                 if (item->is_equals) {
8341                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8342
8343                         if (item->check_target_idx || fail_case) {
8344                                 if (!item->compare_done || fail_case) {
8345                                         if (amd64_use_imm32 ((gint64)item->key))
8346                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8347                                         else {
8348                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8349                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8350                                         }
8351                                 }
8352                                 item->jmp_code = code;
8353                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8354                                 if (item->has_target_code) {
8355                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8356                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8357                                 } else {
8358                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8359                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8360                                 }
8361
8362                                 if (fail_case) {
8363                                         amd64_patch (item->jmp_code, code);
8364                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8365                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8366                                         item->jmp_code = NULL;
8367                                 }
8368                         } else {
8369                                 /* enable the commented code to assert on wrong method */
8370 #if 0
8371                                 if (amd64_is_imm32 (item->key))
8372                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8373                                 else {
8374                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8375                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8376                                 }
8377                                 item->jmp_code = code;
8378                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8379                                 /* See the comment below about R10 */
8380                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8381                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8382                                 amd64_patch (item->jmp_code, code);
8383                                 amd64_breakpoint (code);
8384                                 item->jmp_code = NULL;
8385 #else
8386                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8387                                    needs to be preserved.  R10 needs
8388                                    to be preserved for calls which
8389                                    require a runtime generic context,
8390                                    but interface calls don't. */
8391                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8392                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8393 #endif
8394                         }
8395                 } else {
8396                         if (amd64_use_imm32 ((gint64)item->key))
8397                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8398                         else {
8399                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8400                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8401                         }
8402                         item->jmp_code = code;
8403                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8404                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8405                         else
8406                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8407                 }
8408                 g_assert (code - item->code_target <= item->chunk_size);
8409         }
8410         /* patch the branches to get to the target items */
8411         for (i = 0; i < count; ++i) {
8412                 MonoIMTCheckItem *item = imt_entries [i];
8413                 if (item->jmp_code) {
8414                         if (item->check_target_idx) {
8415                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8416                         }
8417                 }
8418         }
8419
8420         if (!fail_tramp)
8421                 mono_stats.imt_thunks_size += code - start;
8422         g_assert (code - start <= size);
8423
8424         nacl_domain_code_validate(domain, &start, size, &code);
8425         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8426
8427         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8428
8429         return start;
8430 }
8431
8432 MonoMethod*
8433 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8434 {
8435         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8436 }
8437
8438 MonoVTable*
8439 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8440 {
8441         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8442 }
8443
8444 GSList*
8445 mono_arch_get_cie_program (void)
8446 {
8447         GSList *l = NULL;
8448
8449         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8450         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8451
8452         return l;
8453 }
8454
8455 #ifndef DISABLE_JIT
8456
8457 MonoInst*
8458 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8459 {
8460         MonoInst *ins = NULL;
8461         int opcode = 0;
8462
8463         if (cmethod->klass == mono_defaults.math_class) {
8464                 if (strcmp (cmethod->name, "Sin") == 0) {
8465                         opcode = OP_SIN;
8466                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8467                         opcode = OP_COS;
8468                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8469                         opcode = OP_SQRT;
8470                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8471                         opcode = OP_ABS;
8472                 }
8473
8474                 if (opcode && fsig->param_count == 1) {
8475                         MONO_INST_NEW (cfg, ins, opcode);
8476                         ins->type = STACK_R8;
8477                         ins->dreg = mono_alloc_freg (cfg);
8478                         ins->sreg1 = args [0]->dreg;
8479                         MONO_ADD_INS (cfg->cbb, ins);
8480                 }
8481
8482                 opcode = 0;
8483                 if (cfg->opt & MONO_OPT_CMOV) {
8484                         if (strcmp (cmethod->name, "Min") == 0) {
8485                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8486                                         opcode = OP_IMIN;
8487                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8488                                         opcode = OP_IMIN_UN;
8489                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8490                                         opcode = OP_LMIN;
8491                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8492                                         opcode = OP_LMIN_UN;
8493                         } else if (strcmp (cmethod->name, "Max") == 0) {
8494                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8495                                         opcode = OP_IMAX;
8496                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8497                                         opcode = OP_IMAX_UN;
8498                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8499                                         opcode = OP_LMAX;
8500                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8501                                         opcode = OP_LMAX_UN;
8502                         }
8503                 }
8504
8505                 if (opcode && fsig->param_count == 2) {
8506                         MONO_INST_NEW (cfg, ins, opcode);
8507                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8508                         ins->dreg = mono_alloc_ireg (cfg);
8509                         ins->sreg1 = args [0]->dreg;
8510                         ins->sreg2 = args [1]->dreg;
8511                         MONO_ADD_INS (cfg->cbb, ins);
8512                 }
8513
8514 #if 0
8515                 /* OP_FREM is not IEEE compatible */
8516                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8517                         MONO_INST_NEW (cfg, ins, OP_FREM);
8518                         ins->inst_i0 = args [0];
8519                         ins->inst_i1 = args [1];
8520                 }
8521 #endif
8522         }
8523
8524         return ins;
8525 }
8526 #endif
8527
8528 gboolean
8529 mono_arch_print_tree (MonoInst *tree, int arity)
8530 {
8531         return 0;
8532 }
8533
8534 mgreg_t
8535 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8536 {
8537         return ctx->gregs [reg];
8538 }
8539
8540 void
8541 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8542 {
8543         ctx->gregs [reg] = val;
8544 }
8545
8546 gpointer
8547 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8548 {
8549         gpointer *sp, old_value;
8550         char *bp;
8551
8552         /*Load the spvar*/
8553         bp = MONO_CONTEXT_GET_BP (ctx);
8554         sp = *(gpointer*)(bp + clause->exvar_offset);
8555
8556         old_value = *sp;
8557         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8558                 return old_value;
8559
8560         *sp = new_value;
8561
8562         return old_value;
8563 }
8564
8565 /*
8566  * mono_arch_emit_load_aotconst:
8567  *
8568  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8569  * TARGET from the mscorlib GOT in full-aot code.
8570  * On AMD64, the result is placed into R11.
8571  */
8572 guint8*
8573 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8574 {
8575         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8576         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8577
8578         return code;
8579 }
8580
8581 /*
8582  * mono_arch_get_trampolines:
8583  *
8584  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8585  * for AOT.
8586  */
8587 GSList *
8588 mono_arch_get_trampolines (gboolean aot)
8589 {
8590         return mono_amd64_get_exception_trampolines (aot);
8591 }
8592
8593 /* Soft Debug support */
8594 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8595
8596 /*
8597  * mono_arch_set_breakpoint:
8598  *
8599  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8600  * The location should contain code emitted by OP_SEQ_POINT.
8601  */
8602 void
8603 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8604 {
8605         guint8 *code = ip;
8606
8607         if (ji->from_aot) {
8608                 guint32 native_offset = ip - (guint8*)ji->code_start;
8609                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8610
8611                 g_assert (info->bp_addrs [native_offset] == 0);
8612                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8613         } else {
8614                 /* ip points to a mov r11, 0 */
8615                 g_assert (code [0] == 0x41);
8616                 g_assert (code [1] == 0xbb);
8617                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8618         }
8619 }
8620
8621 /*
8622  * mono_arch_clear_breakpoint:
8623  *
8624  *   Clear the breakpoint at IP.
8625  */
8626 void
8627 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8628 {
8629         guint8 *code = ip;
8630
8631         if (ji->from_aot) {
8632                 guint32 native_offset = ip - (guint8*)ji->code_start;
8633                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8634
8635                 info->bp_addrs [native_offset] = NULL;
8636         } else {
8637                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8638         }
8639 }
8640
8641 gboolean
8642 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8643 {
8644         /* We use soft breakpoints on amd64 */
8645         return FALSE;
8646 }
8647
8648 /*
8649  * mono_arch_skip_breakpoint:
8650  *
8651  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8652  * we resume, the instruction is not executed again.
8653  */
8654 void
8655 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8656 {
8657         g_assert_not_reached ();
8658 }
8659
8660 /*
8661  * mono_arch_start_single_stepping:
8662  *
8663  *   Start single stepping.
8664  */
8665 void
8666 mono_arch_start_single_stepping (void)
8667 {
8668         ss_trampoline = mini_get_single_step_trampoline ();
8669 }
8670
8671 /*
8672  * mono_arch_stop_single_stepping:
8673  *
8674  *   Stop single stepping.
8675  */
8676 void
8677 mono_arch_stop_single_stepping (void)
8678 {
8679         ss_trampoline = NULL;
8680 }
8681
8682 /*
8683  * mono_arch_is_single_step_event:
8684  *
8685  *   Return whenever the machine state in SIGCTX corresponds to a single
8686  * step event.
8687  */
8688 gboolean
8689 mono_arch_is_single_step_event (void *info, void *sigctx)
8690 {
8691         /* We use soft breakpoints on amd64 */
8692         return FALSE;
8693 }
8694
8695 /*
8696  * mono_arch_skip_single_step:
8697  *
8698  *   Modify CTX so the ip is placed after the single step trigger instruction,
8699  * we resume, the instruction is not executed again.
8700  */
8701 void
8702 mono_arch_skip_single_step (MonoContext *ctx)
8703 {
8704         g_assert_not_reached ();
8705 }
8706
8707 /*
8708  * mono_arch_create_seq_point_info:
8709  *
8710  *   Return a pointer to a data structure which is used by the sequence
8711  * point implementation in AOTed code.
8712  */
8713 gpointer
8714 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8715 {
8716         SeqPointInfo *info;
8717         MonoJitInfo *ji;
8718
8719         // FIXME: Add a free function
8720
8721         mono_domain_lock (domain);
8722         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8723                                                                 code);
8724         mono_domain_unlock (domain);
8725
8726         if (!info) {
8727                 ji = mono_jit_info_table_find (domain, (char*)code);
8728                 g_assert (ji);
8729
8730                 // FIXME: Optimize the size
8731                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8732
8733                 info->ss_tramp_addr = &ss_trampoline;
8734
8735                 mono_domain_lock (domain);
8736                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8737                                                          code, info);
8738                 mono_domain_unlock (domain);
8739         }
8740
8741         return info;
8742 }
8743
8744 void
8745 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8746 {
8747         ext->lmf.previous_lmf = prev_lmf;
8748         /* Mark that this is a MonoLMFExt */
8749         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8750         ext->lmf.rsp = (gssize)ext;
8751 }
8752
8753 #endif
8754
8755 gboolean
8756 mono_arch_opcode_supported (int opcode)
8757 {
8758         switch (opcode) {
8759         case OP_ATOMIC_ADD_I4:
8760         case OP_ATOMIC_ADD_I8:
8761         case OP_ATOMIC_EXCHANGE_I4:
8762         case OP_ATOMIC_EXCHANGE_I8:
8763         case OP_ATOMIC_CAS_I4:
8764         case OP_ATOMIC_CAS_I8:
8765         case OP_ATOMIC_LOAD_I1:
8766         case OP_ATOMIC_LOAD_I2:
8767         case OP_ATOMIC_LOAD_I4:
8768         case OP_ATOMIC_LOAD_I8:
8769         case OP_ATOMIC_LOAD_U1:
8770         case OP_ATOMIC_LOAD_U2:
8771         case OP_ATOMIC_LOAD_U4:
8772         case OP_ATOMIC_LOAD_U8:
8773         case OP_ATOMIC_LOAD_R4:
8774         case OP_ATOMIC_LOAD_R8:
8775         case OP_ATOMIC_STORE_I1:
8776         case OP_ATOMIC_STORE_I2:
8777         case OP_ATOMIC_STORE_I4:
8778         case OP_ATOMIC_STORE_I8:
8779         case OP_ATOMIC_STORE_U1:
8780         case OP_ATOMIC_STORE_U2:
8781         case OP_ATOMIC_STORE_U4:
8782         case OP_ATOMIC_STORE_U8:
8783         case OP_ATOMIC_STORE_R4:
8784         case OP_ATOMIC_STORE_R8:
8785                 return TRUE;
8786         default:
8787                 return FALSE;
8788         }
8789 }
8790
8791 #if defined(ENABLE_GSHAREDVT)
8792
8793 #include "../../../mono-extensions/mono/mini/mini-amd64-gsharedvt.c"
8794
8795 #endif /* !MONOTOUCH */