mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "ir-emit.h"
  30 #include "mini-amd64.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * xmmregs [] = {
 121         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 122         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 123 };
 124
 125 const char*
 126 mono_arch_fregname (int reg)
 127 {
 128         if (reg < AMD64_XMM_NREG)
 129                 return xmmregs [reg];
 130         else
 131                 return "unknown";
 132 }
 133
 134 G_GNUC_UNUSED static void
 135 break_count (void)
 136 {
 137 }
 138
 139 G_GNUC_UNUSED static gboolean
 140 debug_count (void)
 141 {
 142         static int count = 0;
 143         count ++;
 144
 145         if (!getenv ("COUNT"))
 146                 return TRUE;
 147
 148         if (count == atoi (getenv ("COUNT"))) {
 149                 break_count ();
 150         }
 151
 152         if (count > atoi (getenv ("COUNT"))) {
 153                 return FALSE;
 154         }
 155
 156         return TRUE;
 157 }
 158
 159 static gboolean
 160 debug_omit_fp (void)
 161 {
 162 #if 0
 163         return debug_count ();
 164 #else
 165         return TRUE;
 166 #endif
 167 }
 168
 169 static inline gboolean
 170 amd64_is_near_call (guint8 *code)
 171 {
 172         /* Skip REX */
 173         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 174                 code += 1;
 175
 176         return code [0] == 0xe8;
 177 }
 178
 179 static inline void
 180 amd64_patch (unsigned char* code, gpointer target)
 181 {
 182         guint8 rex = 0;
 183
 184         /* Skip REX */
 185         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 186                 rex = code [0];
 187                 code += 1;
 188         }
 189
 190         if ((code [0] & 0xf8) == 0xb8) {
 191                 /* amd64_set_reg_template */
 192                 *(guint64*)(code + 1) = (guint64)target;
 193         }
 194         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 195                 /* mov 0(%rip), %dreg */
 196                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 197         }
 198         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 199                 /* call *<OFFSET>(%rip) */
 200                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 201         }
 202         else if ((code [0] == 0xe8)) {
 203                 /* call <DISP> */
 204                 gint64 disp = (guint8*)target - (guint8*)code;
 205                 g_assert (amd64_is_imm32 (disp));
 206                 x86_patch (code, (unsigned char*)target);
 207         }
 208         else
 209                 x86_patch (code, (unsigned char*)target);
 210 }
 211
 212 void
 213 mono_amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         amd64_patch (code, target);
 216 }
 217
 218 typedef enum {
 219         ArgInIReg,
 220         ArgInFloatSSEReg,
 221         ArgInDoubleSSEReg,
 222         ArgOnStack,
 223         ArgValuetypeInReg,
 224         ArgValuetypeAddrInIReg,
 225         ArgNone /* only in pair_storage */
 226 } ArgStorage;
 227
 228 typedef struct {
 229         gint16 offset;
 230         gint8  reg;
 231         ArgStorage storage;
 232
 233         /* Only if storage == ArgValuetypeInReg */
 234         ArgStorage pair_storage [2];
 235         gint8 pair_regs [2];
 236 } ArgInfo;
 237
 238 typedef struct {
 239         int nargs;
 240         guint32 stack_usage;
 241         guint32 reg_usage;
 242         guint32 freg_usage;
 243         gboolean need_stack_align;
 244         ArgInfo ret;
 245         ArgInfo sig_cookie;
 246         ArgInfo args [1];
 247 } CallInfo;
 248
 249 #define DEBUG(a) if (cfg->verbose_level > 1) a
 250
 251 #ifdef PLATFORM_WIN32
 252 #define PARAM_REGS 4
 253
 254 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 255
 256 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 257 #else
 258 #define PARAM_REGS 6
 259
 260 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 261
 262  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 263 #endif
 264
 265 static void inline
 266 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 267 {
 268     ainfo->offset = *stack_size;
 269
 270     if (*gr >= PARAM_REGS) {
 271                 ainfo->storage = ArgOnStack;
 272                 (*stack_size) += sizeof (gpointer);
 273     }
 274     else {
 275                 ainfo->storage = ArgInIReg;
 276                 ainfo->reg = param_regs [*gr];
 277                 (*gr) ++;
 278     }
 279 }
 280
 281 #ifdef PLATFORM_WIN32
 282 #define FLOAT_PARAM_REGS 4
 283 #else
 284 #define FLOAT_PARAM_REGS 8
 285 #endif
 286
 287 static void inline
 288 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 289 {
 290     ainfo->offset = *stack_size;
 291
 292     if (*gr >= FLOAT_PARAM_REGS) {
 293                 ainfo->storage = ArgOnStack;
 294                 (*stack_size) += sizeof (gpointer);
 295     }
 296     else {
 297                 /* A double register */
 298                 if (is_double)
 299                         ainfo->storage = ArgInDoubleSSEReg;
 300                 else
 301                         ainfo->storage = ArgInFloatSSEReg;
 302                 ainfo->reg = *gr;
 303                 (*gr) += 1;
 304     }
 305 }
 306
 307 typedef enum ArgumentClass {
 308         ARG_CLASS_NO_CLASS,
 309         ARG_CLASS_MEMORY,
 310         ARG_CLASS_INTEGER,
 311         ARG_CLASS_SSE
 312 } ArgumentClass;
 313
 314 static ArgumentClass
 315 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 316 {
 317         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 318         MonoType *ptype;
 319
 320         ptype = mini_type_get_underlying_type (NULL, type);
 321         switch (ptype->type) {
 322         case MONO_TYPE_BOOLEAN:
 323         case MONO_TYPE_CHAR:
 324         case MONO_TYPE_I1:
 325         case MONO_TYPE_U1:
 326         case MONO_TYPE_I2:
 327         case MONO_TYPE_U2:
 328         case MONO_TYPE_I4:
 329         case MONO_TYPE_U4:
 330         case MONO_TYPE_I:
 331         case MONO_TYPE_U:
 332         case MONO_TYPE_STRING:
 333         case MONO_TYPE_OBJECT:
 334         case MONO_TYPE_CLASS:
 335         case MONO_TYPE_SZARRAY:
 336         case MONO_TYPE_PTR:
 337         case MONO_TYPE_FNPTR:
 338         case MONO_TYPE_ARRAY:
 339         case MONO_TYPE_I8:
 340         case MONO_TYPE_U8:
 341                 class2 = ARG_CLASS_INTEGER;
 342                 break;
 343         case MONO_TYPE_R4:
 344         case MONO_TYPE_R8:
 345 #ifdef PLATFORM_WIN32
 346                 class2 = ARG_CLASS_INTEGER;
 347 #else
 348                 class2 = ARG_CLASS_SSE;
 349 #endif
 350                 break;
 351
 352         case MONO_TYPE_TYPEDBYREF:
 353                 g_assert_not_reached ();
 354
 355         case MONO_TYPE_GENERICINST:
 356                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 357                         class2 = ARG_CLASS_INTEGER;
 358                         break;
 359                 }
 360                 /* fall through */
 361         case MONO_TYPE_VALUETYPE: {
 362                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 363                 int i;
 364
 365                 for (i = 0; i < info->num_fields; ++i) {
 366                         class2 = class1;
 367                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 368                 }
 369                 break;
 370         }
 371         default:
 372                 g_assert_not_reached ();
 373         }
 374
 375         /* Merge */
 376         if (class1 == class2)
 377                 ;
 378         else if (class1 == ARG_CLASS_NO_CLASS)
 379                 class1 = class2;
 380         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 381                 class1 = ARG_CLASS_MEMORY;
 382         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 383                 class1 = ARG_CLASS_INTEGER;
 384         else
 385                 class1 = ARG_CLASS_SSE;
 386
 387         return class1;
 388 }
 389
 390 static void
 391 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 392                gboolean is_return,
 393                guint32 *gr, guint32 *fr, guint32 *stack_size)
 394 {
 395         guint32 size, quad, nquads, i;
 396         ArgumentClass args [2];
 397         MonoMarshalType *info = NULL;
 398         MonoClass *klass;
 399         MonoGenericSharingContext tmp_gsctx;
 400
 401         /*
 402          * The gsctx currently contains no data, it is only used for checking whenever
 403          * open types are allowed, some callers like mono_arch_get_argument_info ()
 404          * don't pass it to us, so work around that.
 405          */
 406         if (!gsctx)
 407                 gsctx = &tmp_gsctx;
 408
 409         klass = mono_class_from_mono_type (type);
 410         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 411 #ifndef PLATFORM_WIN32
 412         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 413                 /* We pass and return vtypes of size 8 in a register */
 414         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 415 #else
 416         if (!sig->pinvoke) {
 417 #endif
 418                 /* Allways pass in memory */
 419                 ainfo->offset = *stack_size;
 420                 *stack_size += ALIGN_TO (size, 8);
 421                 ainfo->storage = ArgOnStack;
 422
 423                 return;
 424         }
 425
 426         /* FIXME: Handle structs smaller than 8 bytes */
 427         //if ((size % 8) != 0)
 428         //      NOT_IMPLEMENTED;
 429
 430         if (size > 8)
 431                 nquads = 2;
 432         else
 433                 nquads = 1;
 434
 435         if (!sig->pinvoke) {
 436                 /* Always pass in 1 or 2 integer registers */
 437                 args [0] = ARG_CLASS_INTEGER;
 438                 args [1] = ARG_CLASS_INTEGER;
 439                 /* Only the simplest cases are supported */
 440                 if (is_return && nquads != 1) {
 441                         args [0] = ARG_CLASS_MEMORY;
 442                         args [1] = ARG_CLASS_MEMORY;
 443                 }
 444         } else {
 445                 /*
 446                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 447                  * The X87 and SSEUP stuff is left out since there are no such types in
 448                  * the CLR.
 449                  */
 450                 info = mono_marshal_load_type_info (klass);
 451                 g_assert (info);
 452
 453 #ifndef PLATFORM_WIN32
 454                 if (info->native_size > 16) {
 455                         ainfo->offset = *stack_size;
 456                         *stack_size += ALIGN_TO (info->native_size, 8);
 457                         ainfo->storage = ArgOnStack;
 458
 459                         return;
 460                 }
 461 #else
 462                 switch (info->native_size) {
 463                 case 1: case 2: case 4: case 8:
 464                         break;
 465                 default:
 466                         if (is_return) {
 467                                 ainfo->storage = ArgOnStack;
 468                                 ainfo->offset = *stack_size;
 469                                 *stack_size += ALIGN_TO (info->native_size, 8);
 470                         }
 471                         else {
 472                                 ainfo->storage = ArgValuetypeAddrInIReg;
 473
 474                                 if (*gr < PARAM_REGS) {
 475                                         ainfo->pair_storage [0] = ArgInIReg;
 476                                         ainfo->pair_regs [0] = param_regs [*gr];
 477                                         (*gr) ++;
 478                                 }
 479                                 else {
 480                                         ainfo->pair_storage [0] = ArgOnStack;
 481                                         ainfo->offset = *stack_size;
 482                                         *stack_size += 8;
 483                                 }
 484                         }
 485
 486                         return;
 487                 }
 488 #endif
 489
 490                 args [0] = ARG_CLASS_NO_CLASS;
 491                 args [1] = ARG_CLASS_NO_CLASS;
 492                 for (quad = 0; quad < nquads; ++quad) {
 493                         int size;
 494                         guint32 align;
 495                         ArgumentClass class1;
 496
 497                         if (info->num_fields == 0)
 498                                 class1 = ARG_CLASS_MEMORY;
 499                         else
 500                                 class1 = ARG_CLASS_NO_CLASS;
 501                         for (i = 0; i < info->num_fields; ++i) {
 502                                 size = mono_marshal_type_size (info->fields [i].field->type,
 503                                                                                            info->fields [i].mspec,
 504                                                                                            &align, TRUE, klass->unicode);
 505                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 506                                         /* Unaligned field */
 507                                         NOT_IMPLEMENTED;
 508                                 }
 509
 510                                 /* Skip fields in other quad */
 511                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 512                                         continue;
 513                                 if ((quad == 1) && (info->fields [i].offset < 8))
 514                                         continue;
 515
 516                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 517                         }
 518                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 519                         args [quad] = class1;
 520                 }
 521         }
 522
 523         /* Post merger cleanup */
 524         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 525                 args [0] = args [1] = ARG_CLASS_MEMORY;
 526
 527         /* Allocate registers */
 528         {
 529                 int orig_gr = *gr;
 530                 int orig_fr = *fr;
 531
 532                 ainfo->storage = ArgValuetypeInReg;
 533                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 534                 for (quad = 0; quad < nquads; ++quad) {
 535                         switch (args [quad]) {
 536                         case ARG_CLASS_INTEGER:
 537                                 if (*gr >= PARAM_REGS)
 538                                         args [quad] = ARG_CLASS_MEMORY;
 539                                 else {
 540                                         ainfo->pair_storage [quad] = ArgInIReg;
 541                                         if (is_return)
 542                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 543                                         else
 544                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 545                                         (*gr) ++;
 546                                 }
 547                                 break;
 548                         case ARG_CLASS_SSE:
 549                                 if (*fr >= FLOAT_PARAM_REGS)
 550                                         args [quad] = ARG_CLASS_MEMORY;
 551                                 else {
 552                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 553                                         ainfo->pair_regs [quad] = *fr;
 554                                         (*fr) ++;
 555                                 }
 556                                 break;
 557                         case ARG_CLASS_MEMORY:
 558                                 break;
 559                         default:
 560                                 g_assert_not_reached ();
 561                         }
 562                 }
 563
 564                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 565                         /* Revert possible register assignments */
 566                         *gr = orig_gr;
 567                         *fr = orig_fr;
 568
 569                         ainfo->offset = *stack_size;
 570                         if (sig->pinvoke)
 571                                 *stack_size += ALIGN_TO (info->native_size, 8);
 572                         else
 573                                 *stack_size += nquads * sizeof (gpointer);
 574                         ainfo->storage = ArgOnStack;
 575                 }
 576         }
 577 }
 578
 579 /*
 580  * get_call_info:
 581  *
 582  *  Obtain information about a call according to the calling convention.
 583  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 584  * Draft Version 0.23" document for more information.
 585  */
 586 static CallInfo*
 587 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 588 {
 589         guint32 i, gr, fr;
 590         MonoType *ret_type;
 591         int n = sig->hasthis + sig->param_count;
 592         guint32 stack_size = 0;
 593         CallInfo *cinfo;
 594
 595         if (mp)
 596                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 597         else
 598                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 599
 600         gr = 0;
 601         fr = 0;
 602
 603         /* return value */
 604         {
 605                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 606                 switch (ret_type->type) {
 607                 case MONO_TYPE_BOOLEAN:
 608                 case MONO_TYPE_I1:
 609                 case MONO_TYPE_U1:
 610                 case MONO_TYPE_I2:
 611                 case MONO_TYPE_U2:
 612                 case MONO_TYPE_CHAR:
 613                 case MONO_TYPE_I4:
 614                 case MONO_TYPE_U4:
 615                 case MONO_TYPE_I:
 616                 case MONO_TYPE_U:
 617                 case MONO_TYPE_PTR:
 618                 case MONO_TYPE_FNPTR:
 619                 case MONO_TYPE_CLASS:
 620                 case MONO_TYPE_OBJECT:
 621                 case MONO_TYPE_SZARRAY:
 622                 case MONO_TYPE_ARRAY:
 623                 case MONO_TYPE_STRING:
 624                         cinfo->ret.storage = ArgInIReg;
 625                         cinfo->ret.reg = AMD64_RAX;
 626                         break;
 627                 case MONO_TYPE_U8:
 628                 case MONO_TYPE_I8:
 629                         cinfo->ret.storage = ArgInIReg;
 630                         cinfo->ret.reg = AMD64_RAX;
 631                         break;
 632                 case MONO_TYPE_R4:
 633                         cinfo->ret.storage = ArgInFloatSSEReg;
 634                         cinfo->ret.reg = AMD64_XMM0;
 635                         break;
 636                 case MONO_TYPE_R8:
 637                         cinfo->ret.storage = ArgInDoubleSSEReg;
 638                         cinfo->ret.reg = AMD64_XMM0;
 639                         break;
 640                 case MONO_TYPE_GENERICINST:
 641                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 642                                 cinfo->ret.storage = ArgInIReg;
 643                                 cinfo->ret.reg = AMD64_RAX;
 644                                 break;
 645                         }
 646                         /* fall through */
 647                 case MONO_TYPE_VALUETYPE: {
 648                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 649
 650                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 651                         if (cinfo->ret.storage == ArgOnStack)
 652                                 /* The caller passes the address where the value is stored */
 653                                 add_general (&gr, &stack_size, &cinfo->ret);
 654                         break;
 655                 }
 656                 case MONO_TYPE_TYPEDBYREF:
 657                         /* Same as a valuetype with size 24 */
 658                         add_general (&gr, &stack_size, &cinfo->ret);
 659                         ;
 660                         break;
 661                 case MONO_TYPE_VOID:
 662                         break;
 663                 default:
 664                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 665                 }
 666         }
 667
 668         /* this */
 669         if (sig->hasthis)
 670                 add_general (&gr, &stack_size, cinfo->args + 0);
 671
 672         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 673                 gr = PARAM_REGS;
 674                 fr = FLOAT_PARAM_REGS;
 675
 676                 /* Emit the signature cookie just before the implicit arguments */
 677                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 678         }
 679
 680         for (i = 0; i < sig->param_count; ++i) {
 681                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 682                 MonoType *ptype;
 683
 684 #ifdef PLATFORM_WIN32
 685                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 686                 if (gr > fr)
 687                         fr = gr;
 688                 else if (fr > gr)
 689                         gr = fr;
 690 #endif
 691
 692                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 693                         /* We allways pass the sig cookie on the stack for simplicity */
 694                         /*
 695                          * Prevent implicit arguments + the sig cookie from being passed
 696                          * in registers.
 697                          */
 698                         gr = PARAM_REGS;
 699                         fr = FLOAT_PARAM_REGS;
 700
 701                         /* Emit the signature cookie just before the implicit arguments */
 702                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 703                 }
 704
 705                 if (sig->params [i]->byref) {
 706                         add_general (&gr, &stack_size, ainfo);
 707                         continue;
 708                 }
 709                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 710                 switch (ptype->type) {
 711                 case MONO_TYPE_BOOLEAN:
 712                 case MONO_TYPE_I1:
 713                 case MONO_TYPE_U1:
 714                         add_general (&gr, &stack_size, ainfo);
 715                         break;
 716                 case MONO_TYPE_I2:
 717                 case MONO_TYPE_U2:
 718                 case MONO_TYPE_CHAR:
 719                         add_general (&gr, &stack_size, ainfo);
 720                         break;
 721                 case MONO_TYPE_I4:
 722                 case MONO_TYPE_U4:
 723                         add_general (&gr, &stack_size, ainfo);
 724                         break;
 725                 case MONO_TYPE_I:
 726                 case MONO_TYPE_U:
 727                 case MONO_TYPE_PTR:
 728                 case MONO_TYPE_FNPTR:
 729                 case MONO_TYPE_CLASS:
 730                 case MONO_TYPE_OBJECT:
 731                 case MONO_TYPE_STRING:
 732                 case MONO_TYPE_SZARRAY:
 733                 case MONO_TYPE_ARRAY:
 734                         add_general (&gr, &stack_size, ainfo);
 735                         break;
 736                 case MONO_TYPE_GENERICINST:
 737                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 738                                 add_general (&gr, &stack_size, ainfo);
 739                                 break;
 740                         }
 741                         /* fall through */
 742                 case MONO_TYPE_VALUETYPE:
 743                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 744                         break;
 745                 case MONO_TYPE_TYPEDBYREF:
 746 #ifdef PLATFORM_WIN32
 747                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 748 #else
 749                         stack_size += sizeof (MonoTypedRef);
 750                         ainfo->storage = ArgOnStack;
 751 #endif
 752                         break;
 753                 case MONO_TYPE_U8:
 754                 case MONO_TYPE_I8:
 755                         add_general (&gr, &stack_size, ainfo);
 756                         break;
 757                 case MONO_TYPE_R4:
 758                         add_float (&fr, &stack_size, ainfo, FALSE);
 759                         break;
 760                 case MONO_TYPE_R8:
 761                         add_float (&fr, &stack_size, ainfo, TRUE);
 762                         break;
 763                 default:
 764                         g_assert_not_reached ();
 765                 }
 766         }
 767
 768         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 769                 gr = PARAM_REGS;
 770                 fr = FLOAT_PARAM_REGS;
 771
 772                 /* Emit the signature cookie just before the implicit arguments */
 773                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 774         }
 775
 776 #ifdef PLATFORM_WIN32
 777         // There always is 32 bytes reserved on the stack when calling on Winx64
 778         stack_size += 0x20;
 779 #endif
 780
 781         if (stack_size & 0x8) {
 782                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 783                 cinfo->need_stack_align = TRUE;
 784                 stack_size += 8;
 785         }
 786
 787         cinfo->stack_usage = stack_size;
 788         cinfo->reg_usage = gr;
 789         cinfo->freg_usage = fr;
 790         return cinfo;
 791 }
 792
 793 /*
 794  * mono_arch_get_argument_info:
 795  * @csig:  a method signature
 796  * @param_count: the number of parameters to consider
 797  * @arg_info: an array to store the result infos
 798  *
 799  * Gathers information on parameters such as size, alignment and
 800  * padding. arg_info should be large enought to hold param_count + 1 entries.
 801  *
 802  * Returns the size of the argument area on the stack.
 803  */
 804 int
 805 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 806 {
 807         int k;
 808         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 809         guint32 args_size = cinfo->stack_usage;
 810
 811         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 812         if (csig->hasthis) {
 813                 arg_info [0].offset = 0;
 814         }
 815
 816         for (k = 0; k < param_count; k++) {
 817                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 818                 /* FIXME: */
 819                 arg_info [k + 1].size = 0;
 820         }
 821
 822         g_free (cinfo);
 823
 824         return args_size;
 825 }
 826
 827 static int
 828 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 829 {
 830 #ifndef _MSC_VER
 831         __asm__ __volatile__ ("cpuid"
 832                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 833                 : "a" (id));
 834 #else
 835         int info[4];
 836         __cpuid(info, id);
 837         *p_eax = info[0];
 838         *p_ebx = info[1];
 839         *p_ecx = info[2];
 840         *p_edx = info[3];
 841 #endif
 842         return 1;
 843 }
 844
 845 /*
 846  * Initialize the cpu to execute managed code.
 847  */
 848 void
 849 mono_arch_cpu_init (void)
 850 {
 851 #ifndef _MSC_VER
 852         guint16 fpcw;
 853
 854         /* spec compliance requires running with double precision */
 855         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 856         fpcw &= ~X86_FPCW_PRECC_MASK;
 857         fpcw |= X86_FPCW_PREC_DOUBLE;
 858         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 859         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 860 #else
 861         /* TODO: This is crashing on Win64 right now.
 862         * _control87 (_PC_53, MCW_PC);
 863         */
 864 #endif
 865 }
 866
 867 /*
 868  * Initialize architecture specific code.
 869  */
 870 void
 871 mono_arch_init (void)
 872 {
 873         InitializeCriticalSection (&mini_arch_mutex);
 874 }
 875
 876 /*
 877  * Cleanup architecture specific code.
 878  */
 879 void
 880 mono_arch_cleanup (void)
 881 {
 882         DeleteCriticalSection (&mini_arch_mutex);
 883 }
 884
 885 /*
 886  * This function returns the optimizations supported on this cpu.
 887  */
 888 guint32
 889 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 890 {
 891         int eax, ebx, ecx, edx;
 892         guint32 opts = 0;
 893
 894         /* FIXME: AMD64 */
 895
 896         *exclude_mask = 0;
 897         /* Feature Flags function, flags returned in EDX. */
 898         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 899                 if (edx & (1 << 15)) {
 900                         opts |= MONO_OPT_CMOV;
 901                         if (edx & 1)
 902                                 opts |= MONO_OPT_FCMOV;
 903                         else
 904                                 *exclude_mask |= MONO_OPT_FCMOV;
 905                 } else
 906                         *exclude_mask |= MONO_OPT_CMOV;
 907         }
 908
 909         return opts;
 910 }
 911
 912 GList *
 913 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 914 {
 915         GList *vars = NULL;
 916         int i;
 917
 918         for (i = 0; i < cfg->num_varinfo; i++) {
 919                 MonoInst *ins = cfg->varinfo [i];
 920                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 921
 922                 /* unused vars */
 923                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 924                         continue;
 925
 926                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 927                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 928                         continue;
 929
 930                 if (mono_is_regsize_var (ins->inst_vtype)) {
 931                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 932                         g_assert (i == vmv->idx);
 933                         vars = g_list_prepend (vars, vmv);
 934                 }
 935         }
 936
 937         vars = mono_varlist_sort (cfg, vars, 0);
 938
 939         return vars;
 940 }
 941
 942 /**
 943  * mono_arch_compute_omit_fp:
 944  *
 945  *   Determine whenever the frame pointer can be eliminated.
 946  */
 947 static void
 948 mono_arch_compute_omit_fp (MonoCompile *cfg)
 949 {
 950         MonoMethodSignature *sig;
 951         MonoMethodHeader *header;
 952         int i, locals_size;
 953         CallInfo *cinfo;
 954
 955         if (cfg->arch.omit_fp_computed)
 956                 return;
 957
 958         header = mono_method_get_header (cfg->method);
 959
 960         sig = mono_method_signature (cfg->method);
 961
 962         if (!cfg->arch.cinfo)
 963                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 964         cinfo = cfg->arch.cinfo;
 965
 966         /*
 967          * FIXME: Remove some of the restrictions.
 968          */
 969         cfg->arch.omit_fp = TRUE;
 970         cfg->arch.omit_fp_computed = TRUE;
 971
 972         if (cfg->disable_omit_fp)
 973                 cfg->arch.omit_fp = FALSE;
 974
 975         if (!debug_omit_fp ())
 976                 cfg->arch.omit_fp = FALSE;
 977         /*
 978         if (cfg->method->save_lmf)
 979                 cfg->arch.omit_fp = FALSE;
 980         */
 981         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 982                 cfg->arch.omit_fp = FALSE;
 983         if (header->num_clauses)
 984                 cfg->arch.omit_fp = FALSE;
 985         if (cfg->param_area)
 986                 cfg->arch.omit_fp = FALSE;
 987         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 988                 cfg->arch.omit_fp = FALSE;
 989         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 990                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 991                 cfg->arch.omit_fp = FALSE;
 992         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 993                 ArgInfo *ainfo = &cinfo->args [i];
 994
 995                 if (ainfo->storage == ArgOnStack) {
 996                         /*
 997                          * The stack offset can only be determined when the frame
 998                          * size is known.
 999                          */
1000                         cfg->arch.omit_fp = FALSE;
1001                 }
1002         }
1003
1004         locals_size = 0;
1005         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1006                 MonoInst *ins = cfg->varinfo [i];
1007                 int ialign;
1008
1009                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1010         }
1011
1012         if ((cfg->num_varinfo > 5000) || (locals_size >= (1 << 15)) || (header->code_size > 110000)) {
1013                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1014                 cfg->arch.omit_fp = FALSE;
1015         }
1016 }
1017
1018 GList *
1019 mono_arch_get_global_int_regs (MonoCompile *cfg)
1020 {
1021         GList *regs = NULL;
1022
1023         mono_arch_compute_omit_fp (cfg);
1024
1025         if (cfg->globalra) {
1026                 if (cfg->arch.omit_fp)
1027                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1028
1029                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1030                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1031                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1032                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1033                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1034
1035                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1036                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1037                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1041                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1042                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1043         } else {
1044                 if (cfg->arch.omit_fp)
1045                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1046
1047                 /* We use the callee saved registers for global allocation */
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1051                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1052                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1053 #ifdef PLATFORM_WIN32
1054                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1055                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1056 #endif
1057         }
1058
1059         return regs;
1060 }
1061
1062 GList*
1063 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1064 {
1065         GList *regs = NULL;
1066         int i;
1067
1068         /* All XMM registers */
1069         for (i = 0; i < 16; ++i)
1070                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1071
1072         return regs;
1073 }
1074
1075 GList*
1076 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1077 {
1078         static GList *r = NULL;
1079
1080         if (r == NULL) {
1081                 GList *regs = NULL;
1082
1083                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1084                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1085                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1086                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1089
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1093                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1094                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1095                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1096                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1097                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1098
1099                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1100         }
1101
1102         return r;
1103 }
1104
1105 GList*
1106 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1107 {
1108         int i;
1109         static GList *r = NULL;
1110
1111         if (r == NULL) {
1112                 GList *regs = NULL;
1113
1114                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1115                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1116
1117                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1118         }
1119
1120         return r;
1121 }
1122
1123 /*
1124  * mono_arch_regalloc_cost:
1125  *
1126  *  Return the cost, in number of memory references, of the action of
1127  * allocating the variable VMV into a register during global register
1128  * allocation.
1129  */
1130 guint32
1131 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1132 {
1133         MonoInst *ins = cfg->varinfo [vmv->idx];
1134
1135         if (cfg->method->save_lmf)
1136                 /* The register is already saved */
1137                 /* substract 1 for the invisible store in the prolog */
1138                 return (ins->opcode == OP_ARG) ? 0 : 1;
1139         else
1140                 /* push+pop */
1141                 return (ins->opcode == OP_ARG) ? 1 : 2;
1142 }
1143
1144 /*
1145  * mono_arch_fill_argument_info:
1146  *
1147  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1148  * of the method.
1149  */
1150 void
1151 mono_arch_fill_argument_info (MonoCompile *cfg)
1152 {
1153         MonoMethodSignature *sig;
1154         MonoMethodHeader *header;
1155         MonoInst *ins;
1156         int i;
1157         CallInfo *cinfo;
1158
1159         header = mono_method_get_header (cfg->method);
1160
1161         sig = mono_method_signature (cfg->method);
1162
1163         cinfo = cfg->arch.cinfo;
1164
1165         /*
1166          * Contrary to mono_arch_allocate_vars (), the information should describe
1167          * where the arguments are at the beginning of the method, not where they can be
1168          * accessed during the execution of the method. The later makes no sense for the
1169          * global register allocator, since a variable can be in more than one location.
1170          */
1171         if (sig->ret->type != MONO_TYPE_VOID) {
1172                 switch (cinfo->ret.storage) {
1173                 case ArgInIReg:
1174                 case ArgInFloatSSEReg:
1175                 case ArgInDoubleSSEReg:
1176                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1177                                 cfg->vret_addr->opcode = OP_REGVAR;
1178                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1179                         }
1180                         else {
1181                                 cfg->ret->opcode = OP_REGVAR;
1182                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1183                         }
1184                         break;
1185                 case ArgValuetypeInReg:
1186                         cfg->ret->opcode = OP_REGOFFSET;
1187                         cfg->ret->inst_basereg = -1;
1188                         cfg->ret->inst_offset = -1;
1189                         break;
1190                 default:
1191                         g_assert_not_reached ();
1192                 }
1193         }
1194
1195         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1196                 ArgInfo *ainfo = &cinfo->args [i];
1197                 MonoType *arg_type;
1198
1199                 ins = cfg->args [i];
1200
1201                 if (sig->hasthis && (i == 0))
1202                         arg_type = &mono_defaults.object_class->byval_arg;
1203                 else
1204                         arg_type = sig->params [i - sig->hasthis];
1205
1206                 switch (ainfo->storage) {
1207                 case ArgInIReg:
1208                 case ArgInFloatSSEReg:
1209                 case ArgInDoubleSSEReg:
1210                         ins->opcode = OP_REGVAR;
1211                         ins->inst_c0 = ainfo->reg;
1212                         break;
1213                 case ArgOnStack:
1214                         ins->opcode = OP_REGOFFSET;
1215                         ins->inst_basereg = -1;
1216                         ins->inst_offset = -1;
1217                         break;
1218                 case ArgValuetypeInReg:
1219                         /* Dummy */
1220                         ins->opcode = OP_NOP;
1221                         break;
1222                 default:
1223                         g_assert_not_reached ();
1224                 }
1225         }
1226 }
1227
1228 void
1229 mono_arch_allocate_vars (MonoCompile *cfg)
1230 {
1231         MonoMethodSignature *sig;
1232         MonoMethodHeader *header;
1233         MonoInst *ins;
1234         int i, offset;
1235         guint32 locals_stack_size, locals_stack_align;
1236         gint32 *offsets;
1237         CallInfo *cinfo;
1238
1239         header = mono_method_get_header (cfg->method);
1240
1241         sig = mono_method_signature (cfg->method);
1242
1243         cinfo = cfg->arch.cinfo;
1244
1245         mono_arch_compute_omit_fp (cfg);
1246
1247         /*
1248          * We use the ABI calling conventions for managed code as well.
1249          * Exception: valuetypes are never passed or returned in registers.
1250          */
1251
1252         if (cfg->arch.omit_fp) {
1253                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1254                 cfg->frame_reg = AMD64_RSP;
1255                 offset = 0;
1256         } else {
1257                 /* Locals are allocated backwards from %fp */
1258                 cfg->frame_reg = AMD64_RBP;
1259                 offset = 0;
1260         }
1261
1262         if (cfg->method->save_lmf) {
1263                 /* Reserve stack space for saving LMF */
1264                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1265                 g_assert (offset == 0);
1266                 if (cfg->arch.omit_fp) {
1267                         cfg->arch.lmf_offset = offset;
1268                         offset += sizeof (MonoLMF);
1269                 }
1270                 else {
1271                         offset += sizeof (MonoLMF);
1272                         cfg->arch.lmf_offset = -offset;
1273                 }
1274         } else {
1275                 if (cfg->arch.omit_fp)
1276                         cfg->arch.reg_save_area_offset = offset;
1277                 /* Reserve space for caller saved registers */
1278                 for (i = 0; i < AMD64_NREG; ++i)
1279                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1280                                 offset += sizeof (gpointer);
1281                         }
1282         }
1283
1284         if (sig->ret->type != MONO_TYPE_VOID) {
1285                 switch (cinfo->ret.storage) {
1286                 case ArgInIReg:
1287                 case ArgInFloatSSEReg:
1288                 case ArgInDoubleSSEReg:
1289                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1290                                 if (cfg->globalra) {
1291                                         cfg->vret_addr->opcode = OP_REGVAR;
1292                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1293                                 } else {
1294                                         /* The register is volatile */
1295                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1296                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1297                                         if (cfg->arch.omit_fp) {
1298                                                 cfg->vret_addr->inst_offset = offset;
1299                                                 offset += 8;
1300                                         } else {
1301                                                 offset += 8;
1302                                                 cfg->vret_addr->inst_offset = -offset;
1303                                         }
1304                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1305                                                 printf ("vret_addr =");
1306                                                 mono_print_ins (cfg->vret_addr);
1307                                         }
1308                                 }
1309                         }
1310                         else {
1311                                 cfg->ret->opcode = OP_REGVAR;
1312                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1313                         }
1314                         break;
1315                 case ArgValuetypeInReg:
1316                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1317                         cfg->ret->opcode = OP_REGOFFSET;
1318                         cfg->ret->inst_basereg = cfg->frame_reg;
1319                         if (cfg->arch.omit_fp) {
1320                                 cfg->ret->inst_offset = offset;
1321                                 offset += 16;
1322                         } else {
1323                                 offset += 16;
1324                                 cfg->ret->inst_offset = - offset;
1325                         }
1326                         break;
1327                 default:
1328                         g_assert_not_reached ();
1329                 }
1330                 if (!cfg->globalra)
1331                         cfg->ret->dreg = cfg->ret->inst_c0;
1332         }
1333
1334         /* Allocate locals */
1335         if (!cfg->globalra) {
1336                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1337                 if (locals_stack_align) {
1338                         offset += (locals_stack_align - 1);
1339                         offset &= ~(locals_stack_align - 1);
1340                 }
1341                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1342                         if (offsets [i] != -1) {
1343                                 MonoInst *ins = cfg->varinfo [i];
1344                                 ins->opcode = OP_REGOFFSET;
1345                                 ins->inst_basereg = cfg->frame_reg;
1346                                 if (cfg->arch.omit_fp)
1347                                         ins->inst_offset = (offset + offsets [i]);
1348                                 else
1349                                         ins->inst_offset = - (offset + offsets [i]);
1350                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1351                         }
1352                 }
1353                 offset += locals_stack_size;
1354         }
1355
1356         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1357                 g_assert (!cfg->arch.omit_fp);
1358                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1359                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1360         }
1361
1362         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1363                 ins = cfg->args [i];
1364                 if (ins->opcode != OP_REGVAR) {
1365                         ArgInfo *ainfo = &cinfo->args [i];
1366                         gboolean inreg = TRUE;
1367                         MonoType *arg_type;
1368
1369                         if (sig->hasthis && (i == 0))
1370                                 arg_type = &mono_defaults.object_class->byval_arg;
1371                         else
1372                                 arg_type = sig->params [i - sig->hasthis];
1373
1374                         if (cfg->globalra) {
1375                                 /* The new allocator needs info about the original locations of the arguments */
1376                                 switch (ainfo->storage) {
1377                                 case ArgInIReg:
1378                                 case ArgInFloatSSEReg:
1379                                 case ArgInDoubleSSEReg:
1380                                         ins->opcode = OP_REGVAR;
1381                                         ins->inst_c0 = ainfo->reg;
1382                                         break;
1383                                 case ArgOnStack:
1384                                         g_assert (!cfg->arch.omit_fp);
1385                                         ins->opcode = OP_REGOFFSET;
1386                                         ins->inst_basereg = cfg->frame_reg;
1387                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1388                                         break;
1389                                 case ArgValuetypeInReg:
1390                                         ins->opcode = OP_REGOFFSET;
1391                                         ins->inst_basereg = cfg->frame_reg;
1392                                         /* These arguments are saved to the stack in the prolog */
1393                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1394                                         if (cfg->arch.omit_fp) {
1395                                                 ins->inst_offset = offset;
1396                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1397                                         } else {
1398                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1399                                                 ins->inst_offset = - offset;
1400                                         }
1401                                         break;
1402                                 default:
1403                                         g_assert_not_reached ();
1404                                 }
1405
1406                                 continue;
1407                         }
1408
1409                         /* FIXME: Allocate volatile arguments to registers */
1410                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1411                                 inreg = FALSE;
1412
1413                         /*
1414                          * Under AMD64, all registers used to pass arguments to functions
1415                          * are volatile across calls.
1416                          * FIXME: Optimize this.
1417                          */
1418                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1419                                 inreg = FALSE;
1420
1421                         ins->opcode = OP_REGOFFSET;
1422
1423                         switch (ainfo->storage) {
1424                         case ArgInIReg:
1425                         case ArgInFloatSSEReg:
1426                         case ArgInDoubleSSEReg:
1427                                 if (inreg) {
1428                                         ins->opcode = OP_REGVAR;
1429                                         ins->dreg = ainfo->reg;
1430                                 }
1431                                 break;
1432                         case ArgOnStack:
1433                                 g_assert (!cfg->arch.omit_fp);
1434                                 ins->opcode = OP_REGOFFSET;
1435                                 ins->inst_basereg = cfg->frame_reg;
1436                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1437                                 break;
1438                         case ArgValuetypeInReg:
1439                                 break;
1440                         case ArgValuetypeAddrInIReg: {
1441                                 MonoInst *indir;
1442                                 g_assert (!cfg->arch.omit_fp);
1443
1444                                 MONO_INST_NEW (cfg, indir, 0);
1445                                 indir->opcode = OP_REGOFFSET;
1446                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1447                                         indir->inst_basereg = cfg->frame_reg;
1448                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1449                                         offset += (sizeof (gpointer));
1450                                         indir->inst_offset = - offset;
1451                                 }
1452                                 else {
1453                                         indir->inst_basereg = cfg->frame_reg;
1454                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1455                                 }
1456
1457                                 ins->opcode = OP_VTARG_ADDR;
1458                                 ins->inst_left = indir;
1459
1460                                 break;
1461                         }
1462                         default:
1463                                 NOT_IMPLEMENTED;
1464                         }
1465
1466                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1467                                 ins->opcode = OP_REGOFFSET;
1468                                 ins->inst_basereg = cfg->frame_reg;
1469                                 /* These arguments are saved to the stack in the prolog */
1470                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1471                                 if (cfg->arch.omit_fp) {
1472                                         ins->inst_offset = offset;
1473                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1474                                 } else {
1475                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1476                                         ins->inst_offset = - offset;
1477                                 }
1478                         }
1479                 }
1480         }
1481
1482         cfg->stack_offset = offset;
1483 }
1484
1485 void
1486 mono_arch_create_vars (MonoCompile *cfg)
1487 {
1488         MonoMethodSignature *sig;
1489         CallInfo *cinfo;
1490
1491         sig = mono_method_signature (cfg->method);
1492
1493         if (!cfg->arch.cinfo)
1494                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1495         cinfo = cfg->arch.cinfo;
1496
1497         if (cinfo->ret.storage == ArgValuetypeInReg)
1498                 cfg->ret_var_is_local = TRUE;
1499
1500         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1501                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1502                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1503                         printf ("vret_addr = ");
1504                         mono_print_ins (cfg->vret_addr);
1505                 }
1506         }
1507 }
1508
1509 static void
1510 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1511 {
1512         MonoInst *ins;
1513
1514         switch (storage) {
1515         case ArgInIReg:
1516                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1517                 ins->dreg = mono_alloc_ireg (cfg);
1518                 ins->sreg1 = tree->dreg;
1519                 MONO_ADD_INS (cfg->cbb, ins);
1520                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1521                 break;
1522         case ArgInFloatSSEReg:
1523                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1524                 ins->dreg = mono_alloc_freg (cfg);
1525                 ins->sreg1 = tree->dreg;
1526                 MONO_ADD_INS (cfg->cbb, ins);
1527
1528                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1529                 break;
1530         case ArgInDoubleSSEReg:
1531                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1532                 ins->dreg = mono_alloc_freg (cfg);
1533                 ins->sreg1 = tree->dreg;
1534                 MONO_ADD_INS (cfg->cbb, ins);
1535
1536                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1537
1538                 break;
1539         default:
1540                 g_assert_not_reached ();
1541         }
1542 }
1543
1544 static int
1545 arg_storage_to_load_membase (ArgStorage storage)
1546 {
1547         switch (storage) {
1548         case ArgInIReg:
1549                 return OP_LOAD_MEMBASE;
1550         case ArgInDoubleSSEReg:
1551                 return OP_LOADR8_MEMBASE;
1552         case ArgInFloatSSEReg:
1553                 return OP_LOADR4_MEMBASE;
1554         default:
1555                 g_assert_not_reached ();
1556         }
1557
1558         return -1;
1559 }
1560
1561 static void
1562 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1563 {
1564         MonoInst *arg;
1565         MonoMethodSignature *tmp_sig;
1566         MonoInst *sig_arg;
1567
1568         if (call->tail_call)
1569                 NOT_IMPLEMENTED;
1570
1571         /* FIXME: Add support for signature tokens to AOT */
1572         cfg->disable_aot = TRUE;
1573
1574         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1575
1576         /*
1577          * mono_ArgIterator_Setup assumes the signature cookie is
1578          * passed first and all the arguments which were before it are
1579          * passed on the stack after the signature. So compensate by
1580          * passing a different signature.
1581          */
1582         tmp_sig = mono_metadata_signature_dup (call->signature);
1583         tmp_sig->param_count -= call->signature->sentinelpos;
1584         tmp_sig->sentinelpos = 0;
1585         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1586
1587         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1588         sig_arg->dreg = mono_alloc_ireg (cfg);
1589         sig_arg->inst_p0 = tmp_sig;
1590         MONO_ADD_INS (cfg->cbb, sig_arg);
1591
1592         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1593         arg->sreg1 = sig_arg->dreg;
1594         MONO_ADD_INS (cfg->cbb, arg);
1595 }
1596
1597 void
1598 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1599 {
1600         MonoInst *arg, *in;
1601         MonoMethodSignature *sig;
1602         int i, n, stack_size;
1603         CallInfo *cinfo;
1604         ArgInfo *ainfo;
1605
1606         stack_size = 0;
1607
1608         sig = call->signature;
1609         n = sig->param_count + sig->hasthis;
1610
1611         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1612
1613         if (cinfo->need_stack_align) {
1614                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1615         }
1616
1617         /*
1618          * Emit all parameters passed in registers in non-reverse order for better readability
1619          * and to help the optimization in emit_prolog ().
1620          */
1621         for (i = 0; i < n; ++i) {
1622                 ainfo = cinfo->args + i;
1623
1624                 in = call->args [i];
1625
1626                 if (ainfo->storage == ArgInIReg)
1627                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1628         }
1629
1630         for (i = n - 1; i >= 0; --i) {
1631                 ainfo = cinfo->args + i;
1632
1633                 in = call->args [i];
1634
1635                 switch (ainfo->storage) {
1636                 case ArgInIReg:
1637                         /* Already done */
1638                         break;
1639                 case ArgInFloatSSEReg:
1640                 case ArgInDoubleSSEReg:
1641                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1642                         break;
1643                 case ArgOnStack:
1644                 case ArgValuetypeInReg:
1645                 case ArgValuetypeAddrInIReg:
1646                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1647                                 MonoInst *call_inst = (MonoInst*)call;
1648                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1649                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1650                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1651                                 guint32 align;
1652                                 guint32 size;
1653
1654                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1655                                         size = sizeof (MonoTypedRef);
1656                                         align = sizeof (gpointer);
1657                                 }
1658                                 else {
1659                                         if (sig->pinvoke)
1660                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1661                                         else {
1662                                                 /*
1663                                                  * Other backends use mono_type_stack_size (), but that
1664                                                  * aligns the size to 8, which is larger than the size of
1665                                                  * the source, leading to reads of invalid memory if the
1666                                                  * source is at the end of address space.
1667                                                  */
1668                                                 size = mono_class_value_size (in->klass, &align);
1669                                         }
1670                                 }
1671                                 g_assert (in->klass);
1672
1673                                 if (size > 0) {
1674                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1675                                         arg->sreg1 = in->dreg;
1676                                         arg->klass = in->klass;
1677                                         arg->backend.size = size;
1678                                         arg->inst_p0 = call;
1679                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1680                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1681
1682                                         MONO_ADD_INS (cfg->cbb, arg);
1683                                 }
1684                         } else {
1685                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1686                                 arg->sreg1 = in->dreg;
1687                                 if (!sig->params [i - sig->hasthis]->byref) {
1688                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1689                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1690                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
1691                                                 arg->inst_destbasereg = X86_ESP;
1692                                                 arg->inst_offset = 0;
1693                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1694                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1695                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
1696                                                 arg->inst_destbasereg = X86_ESP;
1697                                                 arg->inst_offset = 0;
1698                                         }
1699                                 }
1700                                 MONO_ADD_INS (cfg->cbb, arg);
1701                         }
1702                         break;
1703                 default:
1704                         g_assert_not_reached ();
1705                 }
1706
1707                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1708                         /* Emit the signature cookie just before the implicit arguments */
1709                         emit_sig_cookie (cfg, call, cinfo);
1710         }
1711
1712         /* Handle the case where there are no implicit arguments */
1713         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1714                 emit_sig_cookie (cfg, call, cinfo);
1715
1716         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1717                 MonoInst *vtarg;
1718
1719                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1720                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1721                                 /*
1722                                  * Tell the JIT to use a more efficient calling convention: call using
1723                                  * OP_CALL, compute the result location after the call, and save the
1724                                  * result there.
1725                                  */
1726                                 call->vret_in_reg = TRUE;
1727                                 /*
1728                                  * Nullify the instruction computing the vret addr to enable
1729                                  * future optimizations.
1730                                  */
1731                                 if (call->vret_var)
1732                                         NULLIFY_INS (call->vret_var);
1733                         } else {
1734                                 if (call->tail_call)
1735                                         NOT_IMPLEMENTED;
1736                                 /*
1737                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1738                                  * the stack. Push the address here, so the call instruction can
1739                                  * access it.
1740                                  */
1741                                 if (!cfg->arch.vret_addr_loc) {
1742                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1743                                         /* Prevent it from being register allocated or optimized away */
1744                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1745                                 }
1746
1747                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1748                         }
1749                 }
1750                 else {
1751                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1752                         vtarg->sreg1 = call->vret_var->dreg;
1753                         vtarg->dreg = mono_alloc_preg (cfg);
1754                         MONO_ADD_INS (cfg->cbb, vtarg);
1755
1756                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1757                 }
1758         }
1759
1760 #ifdef PLATFORM_WIN32
1761         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1762                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1763         }
1764 #endif
1765
1766         if (cfg->method->save_lmf) {
1767                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1768                 MONO_ADD_INS (cfg->cbb, arg);
1769         }
1770
1771         call->stack_usage = cinfo->stack_usage;
1772 }
1773
1774 void
1775 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1776 {
1777         MonoInst *arg;
1778         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1779         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1780         int size = ins->backend.size;
1781
1782         if (ainfo->storage == ArgValuetypeInReg) {
1783                 MonoInst *load;
1784                 int part;
1785
1786                 for (part = 0; part < 2; ++part) {
1787                         if (ainfo->pair_storage [part] == ArgNone)
1788                                 continue;
1789
1790                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
1791                         load->inst_basereg = src->dreg;
1792                         load->inst_offset = part * sizeof (gpointer);
1793
1794                         switch (ainfo->pair_storage [part]) {
1795                         case ArgInIReg:
1796                                 load->dreg = mono_alloc_ireg (cfg);
1797                                 break;
1798                         case ArgInDoubleSSEReg:
1799                         case ArgInFloatSSEReg:
1800                                 load->dreg = mono_alloc_freg (cfg);
1801                                 break;
1802                         default:
1803                                 g_assert_not_reached ();
1804                         }
1805                         MONO_ADD_INS (cfg->cbb, load);
1806
1807                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
1808                 }
1809         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
1810                 MonoInst *vtaddr, *load;
1811                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
1812
1813                 MONO_INST_NEW (cfg, load, OP_LDADDR);
1814                 load->inst_p0 = vtaddr;
1815                 vtaddr->flags |= MONO_INST_INDIRECT;
1816                 load->type = STACK_MP;
1817                 load->klass = vtaddr->klass;
1818                 load->dreg = mono_alloc_ireg (cfg);
1819                 MONO_ADD_INS (cfg->cbb, load);
1820                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
1821
1822                 if (ainfo->pair_storage [0] == ArgInIReg) {
1823                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
1824                         arg->dreg = mono_alloc_ireg (cfg);
1825                         arg->sreg1 = load->dreg;
1826                         arg->inst_imm = 0;
1827                         MONO_ADD_INS (cfg->cbb, arg);
1828                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
1829                 } else {
1830                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1831                         arg->sreg1 = load->dreg;
1832                         MONO_ADD_INS (cfg->cbb, arg);
1833                 }
1834         } else {
1835                 if (size == 8) {
1836                         /* Can't use this for < 8 since it does an 8 byte memory load */
1837                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1838                         arg->inst_basereg = src->dreg;
1839                         arg->inst_offset = 0;
1840                         MONO_ADD_INS (cfg->cbb, arg);
1841                 } else if (size <= 40) {
1842                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
1843                         mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1844                 } else {
1845                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1846                         arg->inst_basereg = src->dreg;
1847                         arg->inst_offset = 0;
1848                         arg->inst_imm = size;
1849                         MONO_ADD_INS (cfg->cbb, arg);
1850                 }
1851         }
1852 }
1853
1854 void
1855 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1856 {
1857         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
1858
1859         if (!ret->byref) {
1860                 if (ret->type == MONO_TYPE_R4) {
1861                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
1862                         return;
1863                 } else if (ret->type == MONO_TYPE_R8) {
1864                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1865                         return;
1866                 }
1867         }
1868
1869         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1870 }
1871
1872 #define EMIT_COND_BRANCH(ins,cond,sign) \
1873 if (ins->flags & MONO_INST_BRLABEL) { \
1874         if (ins->inst_i0->inst_c0) { \
1875                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1876         } else { \
1877                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1878                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1879                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1880                         x86_branch8 (code, cond, 0, sign); \
1881                 else \
1882                         x86_branch32 (code, cond, 0, sign); \
1883         } \
1884 } else { \
1885         if (ins->inst_true_bb->native_offset) { \
1886                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1887         } else { \
1888                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1889                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1890                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1891                         x86_branch8 (code, cond, 0, sign); \
1892                 else \
1893                         x86_branch32 (code, cond, 0, sign); \
1894         } \
1895 }
1896
1897 /* emit an exception if condition is fail */
1898 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1899         do {                                                        \
1900                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1901                 if (tins == NULL) {                                                                             \
1902                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1903                                         MONO_PATCH_INFO_EXC, exc_name);  \
1904                         x86_branch32 (code, cond, 0, signed);               \
1905                 } else {        \
1906                         EMIT_COND_BRANCH (tins, cond, signed);  \
1907                 }                       \
1908         } while (0);
1909
1910 #define EMIT_FPCOMPARE(code) do { \
1911         amd64_fcompp (code); \
1912         amd64_fnstsw (code); \
1913 } while (0);
1914
1915 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1916     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1917         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1918         amd64_ ##op (code); \
1919         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1920         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1921 } while (0);
1922
1923 static guint8*
1924 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1925 {
1926         gboolean no_patch = FALSE;
1927
1928         /*
1929          * FIXME: Add support for thunks
1930          */
1931         {
1932                 gboolean near_call = FALSE;
1933
1934                 /*
1935                  * Indirect calls are expensive so try to make a near call if possible.
1936                  * The caller memory is allocated by the code manager so it is
1937                  * guaranteed to be at a 32 bit offset.
1938                  */
1939
1940                 if (patch_type != MONO_PATCH_INFO_ABS) {
1941                         /* The target is in memory allocated using the code manager */
1942                         near_call = TRUE;
1943
1944                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1945                                 if (((MonoMethod*)data)->klass->image->aot_module)
1946                                         /* The callee might be an AOT method */
1947                                         near_call = FALSE;
1948                                 if (((MonoMethod*)data)->dynamic)
1949                                         /* The target is in malloc-ed memory */
1950                                         near_call = FALSE;
1951                         }
1952
1953                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1954                                 /*
1955                                  * The call might go directly to a native function without
1956                                  * the wrapper.
1957                                  */
1958                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1959                                 if (mi) {
1960                                         gconstpointer target = mono_icall_get_wrapper (mi);
1961                                         if ((((guint64)target) >> 32) != 0)
1962                                                 near_call = FALSE;
1963                                 }
1964                         }
1965                 }
1966                 else {
1967                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
1968                                 /*
1969                                  * This is not really an optimization, but required because the
1970                                  * generic class init trampolines use R11 to pass the vtable.
1971                                  */
1972                                 near_call = TRUE;
1973                         } else {
1974                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1975                                 if (info) {
1976                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1977                                                 strstr (cfg->method->name, info->name)) {
1978                                                 /* A call to the wrapped function */
1979                                                 if ((((guint64)data) >> 32) == 0)
1980                                                         near_call = TRUE;
1981                                                 no_patch = TRUE;
1982                                         }
1983                                         else if (info->func == info->wrapper) {
1984                                                 /* No wrapper */
1985                                                 if ((((guint64)info->func) >> 32) == 0)
1986                                                         near_call = TRUE;
1987                                         }
1988                                         else {
1989                                                 /* See the comment in mono_codegen () */
1990                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1991                                                         near_call = TRUE;
1992                                         }
1993                                 }
1994                                 else if ((((guint64)data) >> 32) == 0) {
1995                                         near_call = TRUE;
1996                                         no_patch = TRUE;
1997                                 }
1998                         }
1999                 }
2000
2001                 if (cfg->method->dynamic)
2002                         /* These methods are allocated using malloc */
2003                         near_call = FALSE;
2004
2005                 if (cfg->compile_aot) {
2006                         near_call = TRUE;
2007                         no_patch = TRUE;
2008                 }
2009
2010 #ifdef MONO_ARCH_NOMAP32BIT
2011                 near_call = FALSE;
2012 #endif
2013
2014                 if (near_call) {
2015                         /*
2016                          * Align the call displacement to an address divisible by 4 so it does
2017                          * not span cache lines. This is required for code patching to work on SMP
2018                          * systems.
2019                          */
2020                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2021                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2022                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2023                         amd64_call_code (code, 0);
2024                 }
2025                 else {
2026                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2027                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2028                         amd64_call_reg (code, GP_SCRATCH_REG);
2029                 }
2030         }
2031
2032         return code;
2033 }
2034
2035 static inline guint8*
2036 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2037 {
2038 #ifdef PLATFORM_WIN32
2039         if (win64_adjust_stack)
2040                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2041 #endif
2042         code = emit_call_body (cfg, code, patch_type, data);
2043 #ifdef PLATFORM_WIN32
2044         if (win64_adjust_stack)
2045                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2046 #endif
2047
2048         return code;
2049 }
2050
2051 static inline int
2052 store_membase_imm_to_store_membase_reg (int opcode)
2053 {
2054         switch (opcode) {
2055         case OP_STORE_MEMBASE_IMM:
2056                 return OP_STORE_MEMBASE_REG;
2057         case OP_STOREI4_MEMBASE_IMM:
2058                 return OP_STOREI4_MEMBASE_REG;
2059         case OP_STOREI8_MEMBASE_IMM:
2060                 return OP_STOREI8_MEMBASE_REG;
2061         }
2062
2063         return -1;
2064 }
2065
2066 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2067
2068 /*
2069  * mono_arch_peephole_pass_1:
2070  *
2071  *   Perform peephole opts which should/can be performed before local regalloc
2072  */
2073 void
2074 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2075 {
2076         MonoInst *ins, *n;
2077
2078         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2079                 MonoInst *last_ins = ins->prev;
2080
2081                 switch (ins->opcode) {
2082                 case OP_ADD_IMM:
2083                 case OP_IADD_IMM:
2084                 case OP_LADD_IMM:
2085                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2086                                 /*
2087                                  * X86_LEA is like ADD, but doesn't have the
2088                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2089                                  * its operand to 64 bit.
2090                                  */
2091                                 ins->opcode = OP_X86_LEA_MEMBASE;
2092                                 ins->inst_basereg = ins->sreg1;
2093                         }
2094                         break;
2095                 case OP_LXOR:
2096                 case OP_IXOR:
2097                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2098                                 MonoInst *ins2;
2099
2100                                 /*
2101                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2102                                  * the latter has length 2-3 instead of 6 (reverse constant
2103                                  * propagation). These instruction sequences are very common
2104                                  * in the initlocals bblock.
2105                                  */
2106                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2107                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2108                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2109                                                 ins2->sreg1 = ins->dreg;
2110                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2111                                                 /* Continue */
2112                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2113                                                 NULLIFY_INS (ins2);
2114                                                 /* Continue */
2115                                         } else {
2116                                                 break;
2117                                         }
2118                                 }
2119                         }
2120                         break;
2121                 case OP_COMPARE_IMM:
2122                 case OP_LCOMPARE_IMM:
2123                         /* OP_COMPARE_IMM (reg, 0)
2124                          * -->
2125                          * OP_AMD64_TEST_NULL (reg)
2126                          */
2127                         if (!ins->inst_imm)
2128                                 ins->opcode = OP_AMD64_TEST_NULL;
2129                         break;
2130                 case OP_ICOMPARE_IMM:
2131                         if (!ins->inst_imm)
2132                                 ins->opcode = OP_X86_TEST_NULL;
2133                         break;
2134                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2135                         /*
2136                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2137                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2138                          * -->
2139                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2140                          * OP_COMPARE_IMM reg, imm
2141                          *
2142                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2143                          */
2144                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2145                             ins->inst_basereg == last_ins->inst_destbasereg &&
2146                             ins->inst_offset == last_ins->inst_offset) {
2147                                         ins->opcode = OP_ICOMPARE_IMM;
2148                                         ins->sreg1 = last_ins->sreg1;
2149
2150                                         /* check if we can remove cmp reg,0 with test null */
2151                                         if (!ins->inst_imm)
2152                                                 ins->opcode = OP_X86_TEST_NULL;
2153                                 }
2154
2155                         break;
2156                 }
2157
2158                 mono_peephole_ins (bb, ins);
2159         }
2160 }
2161
2162 void
2163 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2164 {
2165         MonoInst *ins, *n;
2166
2167         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2168                 switch (ins->opcode) {
2169                 case OP_ICONST:
2170                 case OP_I8CONST: {
2171                         /* reg = 0 -> XOR (reg, reg) */
2172                         /* XOR sets cflags on x86, so we cant do it always */
2173                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2174                                 ins->opcode = OP_LXOR;
2175                                 ins->sreg1 = ins->dreg;
2176                                 ins->sreg2 = ins->dreg;
2177                                 /* Fall through */
2178                         } else {
2179                                 break;
2180                         }
2181                 }
2182                 case OP_LXOR:
2183                         /*
2184                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2185                          * 0 result into 64 bits.
2186                          */
2187                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2188                                 ins->opcode = OP_IXOR;
2189                         }
2190                         /* Fall through */
2191                 case OP_IXOR:
2192                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2193                                 MonoInst *ins2;
2194
2195                                 /*
2196                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2197                                  * the latter has length 2-3 instead of 6 (reverse constant
2198                                  * propagation). These instruction sequences are very common
2199                                  * in the initlocals bblock.
2200                                  */
2201                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2202                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2203                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2204                                                 ins2->sreg1 = ins->dreg;
2205                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2206                                                 /* Continue */
2207                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2208                                                 NULLIFY_INS (ins2);
2209                                                 /* Continue */
2210                                         } else {
2211                                                 break;
2212                                         }
2213                                 }
2214                         }
2215                         break;
2216                 case OP_IADD_IMM:
2217                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2218                                 ins->opcode = OP_X86_INC_REG;
2219                         break;
2220                 case OP_ISUB_IMM:
2221                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2222                                 ins->opcode = OP_X86_DEC_REG;
2223                         break;
2224                 }
2225
2226                 mono_peephole_ins (bb, ins);
2227         }
2228 }
2229
2230 #define NEW_INS(cfg,ins,dest,op) do {   \
2231                 MONO_INST_NEW ((cfg), (dest), (op)); \
2232         (dest)->cil_code = (ins)->cil_code; \
2233         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2234         } while (0)
2235
2236 /*
2237  * mono_arch_lowering_pass:
2238  *
2239  *  Converts complex opcodes into simpler ones so that each IR instruction
2240  * corresponds to one machine instruction.
2241  */
2242 void
2243 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2244 {
2245         MonoInst *ins, *n, *temp;
2246
2247         /*
2248          * FIXME: Need to add more instructions, but the current machine
2249          * description can't model some parts of the composite instructions like
2250          * cdq.
2251          */
2252         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2253                 switch (ins->opcode) {
2254                 case OP_DIV_IMM:
2255                 case OP_REM_IMM:
2256                 case OP_IDIV_IMM:
2257                 case OP_IDIV_UN_IMM:
2258                 case OP_IREM_UN_IMM:
2259                         mono_decompose_op_imm (cfg, bb, ins);
2260                         break;
2261                 case OP_IREM_IMM:
2262                         /* Keep the opcode if we can implement it efficiently */
2263                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2264                                 mono_decompose_op_imm (cfg, bb, ins);
2265                         break;
2266                 case OP_COMPARE_IMM:
2267                 case OP_LCOMPARE_IMM:
2268                         if (!amd64_is_imm32 (ins->inst_imm)) {
2269                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2270                                 temp->inst_c0 = ins->inst_imm;
2271                                 temp->dreg = mono_alloc_ireg (cfg);
2272                                 ins->opcode = OP_COMPARE;
2273                                 ins->sreg2 = temp->dreg;
2274                         }
2275                         break;
2276                 case OP_LOAD_MEMBASE:
2277                 case OP_LOADI8_MEMBASE:
2278                         if (!amd64_is_imm32 (ins->inst_offset)) {
2279                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2280                                 temp->inst_c0 = ins->inst_offset;
2281                                 temp->dreg = mono_alloc_ireg (cfg);
2282                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2283                                 ins->inst_indexreg = temp->dreg;
2284                         }
2285                         break;
2286                 case OP_STORE_MEMBASE_IMM:
2287                 case OP_STOREI8_MEMBASE_IMM:
2288                         if (!amd64_is_imm32 (ins->inst_imm)) {
2289                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2290                                 temp->inst_c0 = ins->inst_imm;
2291                                 temp->dreg = mono_alloc_ireg (cfg);
2292                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2293                                 ins->sreg1 = temp->dreg;
2294                         }
2295                         break;
2296                 default:
2297                         break;
2298                 }
2299         }
2300
2301         bb->max_vreg = cfg->next_vreg;
2302 }
2303
2304 static const int
2305 branch_cc_table [] = {
2306         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2307         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2308         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2309 };
2310
2311 /* Maps CMP_... constants to X86_CC_... constants */
2312 static const int
2313 cc_table [] = {
2314         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2315         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2316 };
2317
2318 static const int
2319 cc_signed_table [] = {
2320         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2321         FALSE, FALSE, FALSE, FALSE
2322 };
2323
2324 /*#include "cprop.c"*/
2325
2326 static unsigned char*
2327 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2328 {
2329         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2330
2331         if (size == 1)
2332                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2333         else if (size == 2)
2334                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2335         return code;
2336 }
2337
2338 static unsigned char*
2339 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2340 {
2341         int sreg = tree->sreg1;
2342         int need_touch = FALSE;
2343
2344 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2345         if (!tree->flags & MONO_INST_INIT)
2346                 need_touch = TRUE;
2347 #endif
2348
2349         if (need_touch) {
2350                 guint8* br[5];
2351
2352                 /*
2353                  * Under Windows:
2354                  * If requested stack size is larger than one page,
2355                  * perform stack-touch operation
2356                  */
2357                 /*
2358                  * Generate stack probe code.
2359                  * Under Windows, it is necessary to allocate one page at a time,
2360                  * "touching" stack after each successful sub-allocation. This is
2361                  * because of the way stack growth is implemented - there is a
2362                  * guard page before the lowest stack page that is currently commited.
2363                  * Stack normally grows sequentially so OS traps access to the
2364                  * guard page and commits more pages when needed.
2365                  */
2366                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2367                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2368
2369                 br[2] = code; /* loop */
2370                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2371                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2372                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2373                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2374                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2375                 amd64_patch (br[3], br[2]);
2376                 amd64_test_reg_reg (code, sreg, sreg);
2377                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2378                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2379
2380                 br[1] = code; x86_jump8 (code, 0);
2381
2382                 amd64_patch (br[0], code);
2383                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2384                 amd64_patch (br[1], code);
2385                 amd64_patch (br[4], code);
2386         }
2387         else
2388                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2389
2390         if (tree->flags & MONO_INST_INIT) {
2391                 int offset = 0;
2392                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2393                         amd64_push_reg (code, AMD64_RAX);
2394                         offset += 8;
2395                 }
2396                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2397                         amd64_push_reg (code, AMD64_RCX);
2398                         offset += 8;
2399                 }
2400                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2401                         amd64_push_reg (code, AMD64_RDI);
2402                         offset += 8;
2403                 }
2404
2405                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2406                 if (sreg != AMD64_RCX)
2407                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2408                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2409
2410                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2411                 amd64_cld (code);
2412                 amd64_prefix (code, X86_REP_PREFIX);
2413                 amd64_stosl (code);
2414
2415                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2416                         amd64_pop_reg (code, AMD64_RDI);
2417                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2418                         amd64_pop_reg (code, AMD64_RCX);
2419                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2420                         amd64_pop_reg (code, AMD64_RAX);
2421         }
2422         return code;
2423 }
2424
2425 static guint8*
2426 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2427 {
2428         CallInfo *cinfo;
2429         guint32 quad;
2430
2431         /* Move return value to the target register */
2432         /* FIXME: do this in the local reg allocator */
2433         switch (ins->opcode) {
2434         case OP_CALL:
2435         case OP_CALL_REG:
2436         case OP_CALL_MEMBASE:
2437         case OP_LCALL:
2438         case OP_LCALL_REG:
2439         case OP_LCALL_MEMBASE:
2440                 g_assert (ins->dreg == AMD64_RAX);
2441                 break;
2442         case OP_FCALL:
2443         case OP_FCALL_REG:
2444         case OP_FCALL_MEMBASE:
2445                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2446                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2447                 }
2448                 else {
2449                         if (ins->dreg != AMD64_XMM0)
2450                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2451                 }
2452                 break;
2453         case OP_VCALL:
2454         case OP_VCALL_REG:
2455         case OP_VCALL_MEMBASE:
2456         case OP_VCALL2:
2457         case OP_VCALL2_REG:
2458         case OP_VCALL2_MEMBASE:
2459                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2460                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2461                         MonoInst *loc = cfg->arch.vret_addr_loc;
2462
2463                         /* Load the destination address */
2464                         g_assert (loc->opcode == OP_REGOFFSET);
2465                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2466
2467                         for (quad = 0; quad < 2; quad ++) {
2468                                 switch (cinfo->ret.pair_storage [quad]) {
2469                                 case ArgInIReg:
2470                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2471                                         break;
2472                                 case ArgInFloatSSEReg:
2473                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2474                                         break;
2475                                 case ArgInDoubleSSEReg:
2476                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2477                                         break;
2478                                 case ArgNone:
2479                                         break;
2480                                 default:
2481                                         NOT_IMPLEMENTED;
2482                                 }
2483                         }
2484                 }
2485                 break;
2486         }
2487
2488         return code;
2489 }
2490
2491 /*
2492  * mono_amd64_emit_tls_get:
2493  * @code: buffer to store code to
2494  * @dreg: hard register where to place the result
2495  * @tls_offset: offset info
2496  *
2497  * mono_amd64_emit_tls_get emits in @code the native code that puts in
2498  * the dreg register the item in the thread local storage identified
2499  * by tls_offset.
2500  *
2501  * Returns: a pointer to the end of the stored code
2502  */
2503 guint8*
2504 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2505 {
2506 #ifdef PLATFORM_WIN32
2507         g_assert (tls_offset < 64);
2508         x86_prefix (code, X86_GS_PREFIX);
2509         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2510 #else
2511         if (optimize_for_xen) {
2512                 x86_prefix (code, X86_FS_PREFIX);
2513                 amd64_mov_reg_mem (code, dreg, 0, 8);
2514                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2515         } else {
2516                 x86_prefix (code, X86_FS_PREFIX);
2517                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2518         }
2519 #endif
2520         return code;
2521 }
2522
2523 #define REAL_PRINT_REG(text,reg) \
2524 mono_assert (reg >= 0); \
2525 amd64_push_reg (code, AMD64_RAX); \
2526 amd64_push_reg (code, AMD64_RDX); \
2527 amd64_push_reg (code, AMD64_RCX); \
2528 amd64_push_reg (code, reg); \
2529 amd64_push_imm (code, reg); \
2530 amd64_push_imm (code, text " %d %p\n"); \
2531 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2532 amd64_call_reg (code, AMD64_RAX); \
2533 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2534 amd64_pop_reg (code, AMD64_RCX); \
2535 amd64_pop_reg (code, AMD64_RDX); \
2536 amd64_pop_reg (code, AMD64_RAX);
2537
2538 /* benchmark and set based on cpu */
2539 #define LOOP_ALIGNMENT 8
2540 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2541
2542 #ifndef DISABLE_JIT
2543
2544 void
2545 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2546 {
2547         MonoInst *ins;
2548         MonoCallInst *call;
2549         guint offset;
2550         guint8 *code = cfg->native_code + cfg->code_len;
2551         MonoInst *last_ins = NULL;
2552         guint last_offset = 0;
2553         int max_len, cpos;
2554
2555         if (cfg->opt & MONO_OPT_LOOP) {
2556                 int pad, align = LOOP_ALIGNMENT;
2557                 /* set alignment depending on cpu */
2558                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2559                         pad = align - pad;
2560                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2561                         amd64_padding (code, pad);
2562                         cfg->code_len += pad;
2563                         bb->native_offset = cfg->code_len;
2564                 }
2565         }
2566
2567         if (cfg->verbose_level > 2)
2568                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2569
2570         cpos = bb->max_offset;
2571
2572         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2573                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2574                 g_assert (!cfg->compile_aot);
2575                 cpos += 6;
2576
2577                 cov->data [bb->dfn].cil_code = bb->cil_code;
2578                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2579                 /* this is not thread save, but good enough */
2580                 amd64_inc_membase (code, AMD64_R11, 0);
2581         }
2582
2583         offset = code - cfg->native_code;
2584
2585         mono_debug_open_block (cfg, bb, offset);
2586
2587     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2588                 x86_breakpoint (code);
2589
2590         MONO_BB_FOR_EACH_INS (bb, ins) {
2591                 offset = code - cfg->native_code;
2592
2593                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2594
2595                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2596                         cfg->code_size *= 2;
2597                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2598                         code = cfg->native_code + offset;
2599                         mono_jit_stats.code_reallocs++;
2600                 }
2601
2602                 if (cfg->debug_info)
2603                         mono_debug_record_line_number (cfg, ins, offset);
2604
2605                 switch (ins->opcode) {
2606                 case OP_BIGMUL:
2607                         amd64_mul_reg (code, ins->sreg2, TRUE);
2608                         break;
2609                 case OP_BIGMUL_UN:
2610                         amd64_mul_reg (code, ins->sreg2, FALSE);
2611                         break;
2612                 case OP_X86_SETEQ_MEMBASE:
2613                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2614                         break;
2615                 case OP_STOREI1_MEMBASE_IMM:
2616                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2617                         break;
2618                 case OP_STOREI2_MEMBASE_IMM:
2619                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2620                         break;
2621                 case OP_STOREI4_MEMBASE_IMM:
2622                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2623                         break;
2624                 case OP_STOREI1_MEMBASE_REG:
2625                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2626                         break;
2627                 case OP_STOREI2_MEMBASE_REG:
2628                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2629                         break;
2630                 case OP_STORE_MEMBASE_REG:
2631                 case OP_STOREI8_MEMBASE_REG:
2632                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2633                         break;
2634                 case OP_STOREI4_MEMBASE_REG:
2635                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2636                         break;
2637                 case OP_STORE_MEMBASE_IMM:
2638                 case OP_STOREI8_MEMBASE_IMM:
2639                         g_assert (amd64_is_imm32 (ins->inst_imm));
2640                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2641                         break;
2642                 case OP_LOAD_MEM:
2643                 case OP_LOADI8_MEM:
2644                         // FIXME: Decompose this earlier
2645                         if (amd64_is_imm32 (ins->inst_imm))
2646                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2647                         else {
2648                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2649                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2650                         }
2651                         break;
2652                 case OP_LOADI4_MEM:
2653                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2654                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2655                         break;
2656                 case OP_LOADU4_MEM:
2657                         // FIXME: Decompose this earlier
2658                         if (amd64_is_imm32 (ins->inst_imm))
2659                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2660                         else {
2661                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2662                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2663                         }
2664                         break;
2665                 case OP_LOADU1_MEM:
2666                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2667                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2668                         break;
2669                 case OP_LOADU2_MEM:
2670                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2671                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2672                         break;
2673                 case OP_LOAD_MEMBASE:
2674                 case OP_LOADI8_MEMBASE:
2675                         g_assert (amd64_is_imm32 (ins->inst_offset));
2676                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2677                         break;
2678                 case OP_LOADI4_MEMBASE:
2679                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2680                         break;
2681                 case OP_LOADU4_MEMBASE:
2682                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2683                         break;
2684                 case OP_LOADU1_MEMBASE:
2685                         /* The cpu zero extends the result into 64 bits */
2686                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2687                         break;
2688                 case OP_LOADI1_MEMBASE:
2689                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2690                         break;
2691                 case OP_LOADU2_MEMBASE:
2692                         /* The cpu zero extends the result into 64 bits */
2693                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2694                         break;
2695                 case OP_LOADI2_MEMBASE:
2696                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2697                         break;
2698                 case OP_AMD64_LOADI8_MEMINDEX:
2699                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2700                         break;
2701                 case OP_LCONV_TO_I1:
2702                 case OP_ICONV_TO_I1:
2703                 case OP_SEXT_I1:
2704                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2705                         break;
2706                 case OP_LCONV_TO_I2:
2707                 case OP_ICONV_TO_I2:
2708                 case OP_SEXT_I2:
2709                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2710                         break;
2711                 case OP_LCONV_TO_U1:
2712                 case OP_ICONV_TO_U1:
2713                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2714                         break;
2715                 case OP_LCONV_TO_U2:
2716                 case OP_ICONV_TO_U2:
2717                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2718                         break;
2719                 case OP_ZEXT_I4:
2720                         /* Clean out the upper word */
2721                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2722                         break;
2723                 case OP_SEXT_I4:
2724                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2725                         break;
2726                 case OP_COMPARE:
2727                 case OP_LCOMPARE:
2728                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2729                         break;
2730                 case OP_COMPARE_IMM:
2731                 case OP_LCOMPARE_IMM:
2732                         g_assert (amd64_is_imm32 (ins->inst_imm));
2733                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2734                         break;
2735                 case OP_X86_COMPARE_REG_MEMBASE:
2736                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2737                         break;
2738                 case OP_X86_TEST_NULL:
2739                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2740                         break;
2741                 case OP_AMD64_TEST_NULL:
2742                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2743                         break;
2744
2745                 case OP_X86_ADD_REG_MEMBASE:
2746                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2747                         break;
2748                 case OP_X86_SUB_REG_MEMBASE:
2749                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2750                         break;
2751                 case OP_X86_AND_REG_MEMBASE:
2752                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2753                         break;
2754                 case OP_X86_OR_REG_MEMBASE:
2755                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2756                         break;
2757                 case OP_X86_XOR_REG_MEMBASE:
2758                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2759                         break;
2760
2761                 case OP_X86_ADD_MEMBASE_IMM:
2762                         /* FIXME: Make a 64 version too */
2763                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2764                         break;
2765                 case OP_X86_SUB_MEMBASE_IMM:
2766                         g_assert (amd64_is_imm32 (ins->inst_imm));
2767                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2768                         break;
2769                 case OP_X86_AND_MEMBASE_IMM:
2770                         g_assert (amd64_is_imm32 (ins->inst_imm));
2771                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2772                         break;
2773                 case OP_X86_OR_MEMBASE_IMM:
2774                         g_assert (amd64_is_imm32 (ins->inst_imm));
2775                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2776                         break;
2777                 case OP_X86_XOR_MEMBASE_IMM:
2778                         g_assert (amd64_is_imm32 (ins->inst_imm));
2779                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2780                         break;
2781                 case OP_X86_ADD_MEMBASE_REG:
2782                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2783                         break;
2784                 case OP_X86_SUB_MEMBASE_REG:
2785                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2786                         break;
2787                 case OP_X86_AND_MEMBASE_REG:
2788                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2789                         break;
2790                 case OP_X86_OR_MEMBASE_REG:
2791                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2792                         break;
2793                 case OP_X86_XOR_MEMBASE_REG:
2794                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2795                         break;
2796                 case OP_X86_INC_MEMBASE:
2797                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2798                         break;
2799                 case OP_X86_INC_REG:
2800                         amd64_inc_reg_size (code, ins->dreg, 4);
2801                         break;
2802                 case OP_X86_DEC_MEMBASE:
2803                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2804                         break;
2805                 case OP_X86_DEC_REG:
2806                         amd64_dec_reg_size (code, ins->dreg, 4);
2807                         break;
2808                 case OP_X86_MUL_REG_MEMBASE:
2809                 case OP_X86_MUL_MEMBASE_REG:
2810                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2811                         break;
2812                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2813                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2814                         break;
2815                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2816                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2817                         break;
2818                 case OP_AMD64_COMPARE_MEMBASE_REG:
2819                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2820                         break;
2821                 case OP_AMD64_COMPARE_MEMBASE_IMM:
2822                         g_assert (amd64_is_imm32 (ins->inst_imm));
2823                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2824                         break;
2825                 case OP_X86_COMPARE_MEMBASE8_IMM:
2826                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2827                         break;
2828                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2829                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2830                         break;
2831                 case OP_AMD64_COMPARE_REG_MEMBASE:
2832                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2833                         break;
2834
2835                 case OP_AMD64_ADD_REG_MEMBASE:
2836                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2837                         break;
2838                 case OP_AMD64_SUB_REG_MEMBASE:
2839                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2840                         break;
2841                 case OP_AMD64_AND_REG_MEMBASE:
2842                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2843                         break;
2844                 case OP_AMD64_OR_REG_MEMBASE:
2845                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2846                         break;
2847                 case OP_AMD64_XOR_REG_MEMBASE:
2848                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2849                         break;
2850
2851                 case OP_AMD64_ADD_MEMBASE_REG:
2852                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2853                         break;
2854                 case OP_AMD64_SUB_MEMBASE_REG:
2855                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2856                         break;
2857                 case OP_AMD64_AND_MEMBASE_REG:
2858                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2859                         break;
2860                 case OP_AMD64_OR_MEMBASE_REG:
2861                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2862                         break;
2863                 case OP_AMD64_XOR_MEMBASE_REG:
2864                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2865                         break;
2866
2867                 case OP_AMD64_ADD_MEMBASE_IMM:
2868                         g_assert (amd64_is_imm32 (ins->inst_imm));
2869                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2870                         break;
2871                 case OP_AMD64_SUB_MEMBASE_IMM:
2872                         g_assert (amd64_is_imm32 (ins->inst_imm));
2873                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2874                         break;
2875                 case OP_AMD64_AND_MEMBASE_IMM:
2876                         g_assert (amd64_is_imm32 (ins->inst_imm));
2877                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2878                         break;
2879                 case OP_AMD64_OR_MEMBASE_IMM:
2880                         g_assert (amd64_is_imm32 (ins->inst_imm));
2881                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2882                         break;
2883                 case OP_AMD64_XOR_MEMBASE_IMM:
2884                         g_assert (amd64_is_imm32 (ins->inst_imm));
2885                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2886                         break;
2887
2888                 case OP_BREAK:
2889                         amd64_breakpoint (code);
2890                         break;
2891                 case OP_RELAXED_NOP:
2892                         x86_prefix (code, X86_REP_PREFIX);
2893                         x86_nop (code);
2894                         break;
2895                 case OP_HARD_NOP:
2896                         x86_nop (code);
2897                         break;
2898                 case OP_NOP:
2899                 case OP_DUMMY_USE:
2900                 case OP_DUMMY_STORE:
2901                 case OP_NOT_REACHED:
2902                 case OP_NOT_NULL:
2903                         break;
2904                 case OP_ADDCC:
2905                 case OP_LADD:
2906                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2907                         break;
2908                 case OP_ADC:
2909                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2910                         break;
2911                 case OP_ADD_IMM:
2912                 case OP_LADD_IMM:
2913                         g_assert (amd64_is_imm32 (ins->inst_imm));
2914                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2915                         break;
2916                 case OP_ADC_IMM:
2917                         g_assert (amd64_is_imm32 (ins->inst_imm));
2918                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2919                         break;
2920                 case OP_SUBCC:
2921                 case OP_LSUB:
2922                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2923                         break;
2924                 case OP_SBB:
2925                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2926                         break;
2927                 case OP_SUB_IMM:
2928                 case OP_LSUB_IMM:
2929                         g_assert (amd64_is_imm32 (ins->inst_imm));
2930                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2931                         break;
2932                 case OP_SBB_IMM:
2933                         g_assert (amd64_is_imm32 (ins->inst_imm));
2934                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2935                         break;
2936                 case OP_LAND:
2937                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2938                         break;
2939                 case OP_AND_IMM:
2940                 case OP_LAND_IMM:
2941                         g_assert (amd64_is_imm32 (ins->inst_imm));
2942                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2943                         break;
2944                 case OP_LMUL:
2945                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2946                         break;
2947                 case OP_MUL_IMM:
2948                 case OP_LMUL_IMM:
2949                 case OP_IMUL_IMM: {
2950                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2951
2952                         switch (ins->inst_imm) {
2953                         case 2:
2954                                 /* MOV r1, r2 */
2955                                 /* ADD r1, r1 */
2956                                 if (ins->dreg != ins->sreg1)
2957                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2958                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2959                                 break;
2960                         case 3:
2961                                 /* LEA r1, [r2 + r2*2] */
2962                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2963                                 break;
2964                         case 5:
2965                                 /* LEA r1, [r2 + r2*4] */
2966                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2967                                 break;
2968                         case 6:
2969                                 /* LEA r1, [r2 + r2*2] */
2970                                 /* ADD r1, r1          */
2971                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2972                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2973                                 break;
2974                         case 9:
2975                                 /* LEA r1, [r2 + r2*8] */
2976                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2977                                 break;
2978                         case 10:
2979                                 /* LEA r1, [r2 + r2*4] */
2980                                 /* ADD r1, r1          */
2981                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2982                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2983                                 break;
2984                         case 12:
2985                                 /* LEA r1, [r2 + r2*2] */
2986                                 /* SHL r1, 2           */
2987                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2988                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2989                                 break;
2990                         case 25:
2991                                 /* LEA r1, [r2 + r2*4] */
2992                                 /* LEA r1, [r1 + r1*4] */
2993                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2994                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2995                                 break;
2996                         case 100:
2997                                 /* LEA r1, [r2 + r2*4] */
2998                                 /* SHL r1, 2           */
2999                                 /* LEA r1, [r1 + r1*4] */
3000                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3001                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3002                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3003                                 break;
3004                         default:
3005                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3006                                 break;
3007                         }
3008                         break;
3009                 }
3010                 case OP_LDIV:
3011                 case OP_LREM:
3012                         /* Regalloc magic makes the div/rem cases the same */
3013                         if (ins->sreg2 == AMD64_RDX) {
3014                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3015                                 amd64_cdq (code);
3016                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3017                         } else {
3018                                 amd64_cdq (code);
3019                                 amd64_div_reg (code, ins->sreg2, TRUE);
3020                         }
3021                         break;
3022                 case OP_LDIV_UN:
3023                 case OP_LREM_UN:
3024                         if (ins->sreg2 == AMD64_RDX) {
3025                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3026                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3027                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3028                         } else {
3029                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3030                                 amd64_div_reg (code, ins->sreg2, FALSE);
3031                         }
3032                         break;
3033                 case OP_IDIV:
3034                 case OP_IREM:
3035                         if (ins->sreg2 == AMD64_RDX) {
3036                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3037                                 amd64_cdq_size (code, 4);
3038                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3039                         } else {
3040                                 amd64_cdq_size (code, 4);
3041                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3042                         }
3043                         break;
3044                 case OP_IDIV_UN:
3045                 case OP_IREM_UN:
3046                         if (ins->sreg2 == AMD64_RDX) {
3047                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3048                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3049                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3050                         } else {
3051                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3052                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3053                         }
3054                         break;
3055                 case OP_IREM_IMM: {
3056                         int power = mono_is_power_of_two (ins->inst_imm);
3057
3058                         g_assert (ins->sreg1 == X86_EAX);
3059                         g_assert (ins->dreg == X86_EAX);
3060                         g_assert (power >= 0);
3061
3062                         if (power == 0) {
3063                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3064                                 break;
3065                         }
3066
3067                         /* Based on gcc code */
3068
3069                         /* Add compensation for negative dividents */
3070                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3071                         if (power > 1)
3072                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3073                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3074                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3075                         /* Compute remainder */
3076                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3077                         /* Remove compensation */
3078                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3079                         break;
3080                 }
3081                 case OP_LMUL_OVF:
3082                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3083                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3084                         break;
3085                 case OP_LOR:
3086                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3087                         break;
3088                 case OP_OR_IMM:
3089                 case OP_LOR_IMM:
3090                         g_assert (amd64_is_imm32 (ins->inst_imm));
3091                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3092                         break;
3093                 case OP_LXOR:
3094                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3095                         break;
3096                 case OP_XOR_IMM:
3097                 case OP_LXOR_IMM:
3098                         g_assert (amd64_is_imm32 (ins->inst_imm));
3099                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3100                         break;
3101                 case OP_LSHL:
3102                         g_assert (ins->sreg2 == AMD64_RCX);
3103                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3104                         break;
3105                 case OP_LSHR:
3106                         g_assert (ins->sreg2 == AMD64_RCX);
3107                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3108                         break;
3109                 case OP_SHR_IMM:
3110                         g_assert (amd64_is_imm32 (ins->inst_imm));
3111                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3112                         break;
3113                 case OP_LSHR_IMM:
3114                         g_assert (amd64_is_imm32 (ins->inst_imm));
3115                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3116                         break;
3117                 case OP_SHR_UN_IMM:
3118                         g_assert (amd64_is_imm32 (ins->inst_imm));
3119                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3120                         break;
3121                 case OP_LSHR_UN_IMM:
3122                         g_assert (amd64_is_imm32 (ins->inst_imm));
3123                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3124                         break;
3125                 case OP_LSHR_UN:
3126                         g_assert (ins->sreg2 == AMD64_RCX);
3127                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3128                         break;
3129                 case OP_SHL_IMM:
3130                         g_assert (amd64_is_imm32 (ins->inst_imm));
3131                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3132                         break;
3133                 case OP_LSHL_IMM:
3134                         g_assert (amd64_is_imm32 (ins->inst_imm));
3135                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3136                         break;
3137
3138                 case OP_IADDCC:
3139                 case OP_IADD:
3140                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3141                         break;
3142                 case OP_IADC:
3143                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3144                         break;
3145                 case OP_IADD_IMM:
3146                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3147                         break;
3148                 case OP_IADC_IMM:
3149                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3150                         break;
3151                 case OP_ISUBCC:
3152                 case OP_ISUB:
3153                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3154                         break;
3155                 case OP_ISBB:
3156                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3157                         break;
3158                 case OP_ISUB_IMM:
3159                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3160                         break;
3161                 case OP_ISBB_IMM:
3162                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3163                         break;
3164                 case OP_IAND:
3165                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3166                         break;
3167                 case OP_IAND_IMM:
3168                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3169                         break;
3170                 case OP_IOR:
3171                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3172                         break;
3173                 case OP_IOR_IMM:
3174                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3175                         break;
3176                 case OP_IXOR:
3177                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3178                         break;
3179                 case OP_IXOR_IMM:
3180                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3181                         break;
3182                 case OP_INEG:
3183                         amd64_neg_reg_size (code, ins->sreg1, 4);
3184                         break;
3185                 case OP_INOT:
3186                         amd64_not_reg_size (code, ins->sreg1, 4);
3187                         break;
3188                 case OP_ISHL:
3189                         g_assert (ins->sreg2 == AMD64_RCX);
3190                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3191                         break;
3192                 case OP_ISHR:
3193                         g_assert (ins->sreg2 == AMD64_RCX);
3194                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3195                         break;
3196                 case OP_ISHR_IMM:
3197                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3198                         break;
3199                 case OP_ISHR_UN_IMM:
3200                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3201                         break;
3202                 case OP_ISHR_UN:
3203                         g_assert (ins->sreg2 == AMD64_RCX);
3204                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3205                         break;
3206                 case OP_ISHL_IMM:
3207                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3208                         break;
3209                 case OP_IMUL:
3210                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3211                         break;
3212                 case OP_IMUL_OVF:
3213                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3214                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3215                         break;
3216                 case OP_IMUL_OVF_UN:
3217                 case OP_LMUL_OVF_UN: {
3218                         /* the mul operation and the exception check should most likely be split */
3219                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3220                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3221                         /*g_assert (ins->sreg2 == X86_EAX);
3222                         g_assert (ins->dreg == X86_EAX);*/
3223                         if (ins->sreg2 == X86_EAX) {
3224                                 non_eax_reg = ins->sreg1;
3225                         } else if (ins->sreg1 == X86_EAX) {
3226                                 non_eax_reg = ins->sreg2;
3227                         } else {
3228                                 /* no need to save since we're going to store to it anyway */
3229                                 if (ins->dreg != X86_EAX) {
3230                                         saved_eax = TRUE;
3231                                         amd64_push_reg (code, X86_EAX);
3232                                 }
3233                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3234                                 non_eax_reg = ins->sreg2;
3235                         }
3236                         if (ins->dreg == X86_EDX) {
3237                                 if (!saved_eax) {
3238                                         saved_eax = TRUE;
3239                                         amd64_push_reg (code, X86_EAX);
3240                                 }
3241                         } else {
3242                                 saved_edx = TRUE;
3243                                 amd64_push_reg (code, X86_EDX);
3244                         }
3245                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3246                         /* save before the check since pop and mov don't change the flags */
3247                         if (ins->dreg != X86_EAX)
3248                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3249                         if (saved_edx)
3250                                 amd64_pop_reg (code, X86_EDX);
3251                         if (saved_eax)
3252                                 amd64_pop_reg (code, X86_EAX);
3253                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3254                         break;
3255                 }
3256                 case OP_ICOMPARE:
3257                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3258                         break;
3259                 case OP_ICOMPARE_IMM:
3260                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3261                         break;
3262                 case OP_IBEQ:
3263                 case OP_IBLT:
3264                 case OP_IBGT:
3265                 case OP_IBGE:
3266                 case OP_IBLE:
3267                 case OP_LBEQ:
3268                 case OP_LBLT:
3269                 case OP_LBGT:
3270                 case OP_LBGE:
3271                 case OP_LBLE:
3272                 case OP_IBNE_UN:
3273                 case OP_IBLT_UN:
3274                 case OP_IBGT_UN:
3275                 case OP_IBGE_UN:
3276                 case OP_IBLE_UN:
3277                 case OP_LBNE_UN:
3278                 case OP_LBLT_UN:
3279                 case OP_LBGT_UN:
3280                 case OP_LBGE_UN:
3281                 case OP_LBLE_UN:
3282                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3283                         break;
3284
3285                 case OP_CMOV_IEQ:
3286                 case OP_CMOV_IGE:
3287                 case OP_CMOV_IGT:
3288                 case OP_CMOV_ILE:
3289                 case OP_CMOV_ILT:
3290                 case OP_CMOV_INE_UN:
3291                 case OP_CMOV_IGE_UN:
3292                 case OP_CMOV_IGT_UN:
3293                 case OP_CMOV_ILE_UN:
3294                 case OP_CMOV_ILT_UN:
3295                 case OP_CMOV_LEQ:
3296                 case OP_CMOV_LGE:
3297                 case OP_CMOV_LGT:
3298                 case OP_CMOV_LLE:
3299                 case OP_CMOV_LLT:
3300                 case OP_CMOV_LNE_UN:
3301                 case OP_CMOV_LGE_UN:
3302                 case OP_CMOV_LGT_UN:
3303                 case OP_CMOV_LLE_UN:
3304                 case OP_CMOV_LLT_UN:
3305                         g_assert (ins->dreg == ins->sreg1);
3306                         /* This needs to operate on 64 bit values */
3307                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3308                         break;
3309
3310                 case OP_LNOT:
3311                         amd64_not_reg (code, ins->sreg1);
3312                         break;
3313                 case OP_LNEG:
3314                         amd64_neg_reg (code, ins->sreg1);
3315                         break;
3316
3317                 case OP_ICONST:
3318                 case OP_I8CONST:
3319                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3320                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3321                         else
3322                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3323                         break;
3324                 case OP_AOTCONST:
3325                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3326                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3327                         break;
3328                 case OP_JUMP_TABLE:
3329                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3330                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3331                         break;
3332                 case OP_MOVE:
3333                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3334                         break;
3335                 case OP_AMD64_SET_XMMREG_R4: {
3336                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3337                         break;
3338                 }
3339                 case OP_AMD64_SET_XMMREG_R8: {
3340                         if (ins->dreg != ins->sreg1)
3341                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3342                         break;
3343                 }
3344                 case OP_TAILCALL: {
3345                         /*
3346                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3347                          * Keep in sync with the code in emit_epilog.
3348                          */
3349                         int pos = 0, i;
3350
3351                         /* FIXME: no tracing support... */
3352                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3353                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3354
3355                         g_assert (!cfg->method->save_lmf);
3356
3357                         if (cfg->arch.omit_fp) {
3358                                 guint32 save_offset = 0;
3359                                 /* Pop callee-saved registers */
3360                                 for (i = 0; i < AMD64_NREG; ++i)
3361                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3362                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3363                                                 save_offset += 8;
3364                                         }
3365                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3366                         }
3367                         else {
3368                                 for (i = 0; i < AMD64_NREG; ++i)
3369                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3370                                                 pos -= sizeof (gpointer);
3371
3372                                 if (pos)
3373                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3374
3375                                 /* Pop registers in reverse order */
3376                                 for (i = AMD64_NREG - 1; i > 0; --i)
3377                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3378                                                 amd64_pop_reg (code, i);
3379                                         }
3380
3381                                 amd64_leave (code);
3382                         }
3383
3384                         offset = code - cfg->native_code;
3385                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3386                         if (cfg->compile_aot)
3387                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3388                         else
3389                                 amd64_set_reg_template (code, AMD64_R11);
3390                         amd64_jump_reg (code, AMD64_R11);
3391                         break;
3392                 }
3393                 case OP_CHECK_THIS:
3394                         /* ensure ins->sreg1 is not NULL */
3395                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3396                         break;
3397                 case OP_ARGLIST: {
3398                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3399                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3400                         break;
3401                 }
3402                 case OP_CALL:
3403                 case OP_FCALL:
3404                 case OP_LCALL:
3405                 case OP_VCALL:
3406                 case OP_VCALL2:
3407                 case OP_VOIDCALL:
3408                         call = (MonoCallInst*)ins;
3409                         /*
3410                          * The AMD64 ABI forces callers to know about varargs.
3411                          */
3412                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3413                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3414                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3415                                 /*
3416                                  * Since the unmanaged calling convention doesn't contain a
3417                                  * 'vararg' entry, we have to treat every pinvoke call as a
3418                                  * potential vararg call.
3419                                  */
3420                                 guint32 nregs, i;
3421                                 nregs = 0;
3422                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3423                                         if (call->used_fregs & (1 << i))
3424                                                 nregs ++;
3425                                 if (!nregs)
3426                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3427                                 else
3428                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3429                         }
3430
3431                         if (ins->flags & MONO_INST_HAS_METHOD)
3432                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3433                         else
3434                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3435                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3436                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3437                         code = emit_move_return_value (cfg, ins, code);
3438                         break;
3439                 case OP_FCALL_REG:
3440                 case OP_LCALL_REG:
3441                 case OP_VCALL_REG:
3442                 case OP_VCALL2_REG:
3443                 case OP_VOIDCALL_REG:
3444                 case OP_CALL_REG:
3445                         call = (MonoCallInst*)ins;
3446
3447                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3448                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3449                                 ins->sreg1 = AMD64_R11;
3450                         }
3451
3452                         /*
3453                          * The AMD64 ABI forces callers to know about varargs.
3454                          */
3455                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3456                                 if (ins->sreg1 == AMD64_RAX) {
3457                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3458                                         ins->sreg1 = AMD64_R11;
3459                                 }
3460                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3461                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3462                                 /*
3463                                  * Since the unmanaged calling convention doesn't contain a
3464                                  * 'vararg' entry, we have to treat every pinvoke call as a
3465                                  * potential vararg call.
3466                                  */
3467                                 guint32 nregs, i;
3468                                 nregs = 0;
3469                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3470                                         if (call->used_fregs & (1 << i))
3471                                                 nregs ++;
3472                                 if (ins->sreg1 == AMD64_RAX) {
3473                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3474                                         ins->sreg1 = AMD64_R11;
3475                                 }
3476                                 if (!nregs)
3477                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3478                                 else
3479                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3480                         }
3481
3482                         amd64_call_reg (code, ins->sreg1);
3483                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3484                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3485                         code = emit_move_return_value (cfg, ins, code);
3486                         break;
3487                 case OP_FCALL_MEMBASE:
3488                 case OP_LCALL_MEMBASE:
3489                 case OP_VCALL_MEMBASE:
3490                 case OP_VCALL2_MEMBASE:
3491                 case OP_VOIDCALL_MEMBASE:
3492                 case OP_CALL_MEMBASE:
3493                         call = (MonoCallInst*)ins;
3494
3495                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3496                                 /*
3497                                  * Can't use R11 because it is clobbered by the trampoline
3498                                  * code, and the reg value is needed by get_vcall_slot_addr.
3499                                  */
3500                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3501                                 ins->sreg1 = AMD64_RAX;
3502                         }
3503
3504                         if (call->method && ins->inst_offset < 0) {
3505                                 gssize val;
3506
3507                                 /*
3508                                  * This is a possible IMT call so save the IMT method in the proper
3509                                  * register. We don't use the generic code in method-to-ir.c, because
3510                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3511                                  * maintain control over the layout of the code.
3512                                  * Also put the base reg in %rax to simplify find_imt_method ().
3513                                  */
3514                                 if (ins->sreg1 != AMD64_RAX) {
3515                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3516                                         ins->sreg1 = AMD64_RAX;
3517                                 }
3518                                 val = (gssize)(gpointer)call->method;
3519
3520                                 // FIXME: Generics sharing
3521 #if 0
3522                                 if ((((guint64)val) >> 32) == 0)
3523                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3524                                 else
3525                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3526 #endif
3527                         }
3528
3529                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3530                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3531                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3532                         code = emit_move_return_value (cfg, ins, code);
3533                         break;
3534                 case OP_AMD64_SAVE_SP_TO_LMF:
3535                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3536                         break;
3537                 case OP_X86_PUSH:
3538                         amd64_push_reg (code, ins->sreg1);
3539                         break;
3540                 case OP_X86_PUSH_IMM:
3541                         g_assert (amd64_is_imm32 (ins->inst_imm));
3542                         amd64_push_imm (code, ins->inst_imm);
3543                         break;
3544                 case OP_X86_PUSH_MEMBASE:
3545                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3546                         break;
3547                 case OP_X86_PUSH_OBJ: {
3548                         int size = ALIGN_TO (ins->inst_imm, 8);
3549                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3550                         amd64_push_reg (code, AMD64_RDI);
3551                         amd64_push_reg (code, AMD64_RSI);
3552                         amd64_push_reg (code, AMD64_RCX);
3553                         if (ins->inst_offset)
3554                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3555                         else
3556                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3557                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3558                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3559                         amd64_cld (code);
3560                         amd64_prefix (code, X86_REP_PREFIX);
3561                         amd64_movsd (code);
3562                         amd64_pop_reg (code, AMD64_RCX);
3563                         amd64_pop_reg (code, AMD64_RSI);
3564                         amd64_pop_reg (code, AMD64_RDI);
3565                         break;
3566                 }
3567                 case OP_X86_LEA:
3568                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3569                         break;
3570                 case OP_X86_LEA_MEMBASE:
3571                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3572                         break;
3573                 case OP_X86_XCHG:
3574                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3575                         break;
3576                 case OP_LOCALLOC:
3577                         /* keep alignment */
3578                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3579                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3580                         code = mono_emit_stack_alloc (code, ins);
3581                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3582                         break;
3583                 case OP_LOCALLOC_IMM: {
3584                         guint32 size = ins->inst_imm;
3585                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3586
3587                         if (ins->flags & MONO_INST_INIT) {
3588                                 if (size < 64) {
3589                                         int i;
3590
3591                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3592                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3593
3594                                         for (i = 0; i < size; i += 8)
3595                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3596                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3597                                 } else {
3598                                         amd64_mov_reg_imm (code, ins->dreg, size);
3599                                         ins->sreg1 = ins->dreg;
3600
3601                                         code = mono_emit_stack_alloc (code, ins);
3602                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3603                                 }
3604                         } else {
3605                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3606                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3607                         }
3608                         break;
3609                 }
3610                 case OP_THROW: {
3611                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3612                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3613                                              (gpointer)"mono_arch_throw_exception", FALSE);
3614                         break;
3615                 }
3616                 case OP_RETHROW: {
3617                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3618                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3619                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
3620                         break;
3621                 }
3622                 case OP_CALL_HANDLER:
3623                         /* Align stack */
3624                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3625                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3626                         amd64_call_imm (code, 0);
3627                         /* Restore stack alignment */
3628                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3629                         break;
3630                 case OP_START_HANDLER: {
3631                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3632                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3633                         break;
3634                 }
3635                 case OP_ENDFINALLY: {
3636                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3637                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3638                         amd64_ret (code);
3639                         break;
3640                 }
3641                 case OP_ENDFILTER: {
3642                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3643                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3644                         /* The local allocator will put the result into RAX */
3645                         amd64_ret (code);
3646                         break;
3647                 }
3648
3649                 case OP_LABEL:
3650                         ins->inst_c0 = code - cfg->native_code;
3651                         break;
3652                 case OP_BR:
3653                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3654                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3655                         //break;
3656                         if (ins->flags & MONO_INST_BRLABEL) {
3657                                 if (ins->inst_i0->inst_c0) {
3658                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3659                                 } else {
3660                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3661                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3662                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3663                                                 x86_jump8 (code, 0);
3664                                         else
3665                                                 x86_jump32 (code, 0);
3666                                 }
3667                         } else {
3668                                 if (ins->inst_target_bb->native_offset) {
3669                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3670                                 } else {
3671                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3672                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3673                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3674                                                 x86_jump8 (code, 0);
3675                                         else
3676                                                 x86_jump32 (code, 0);
3677                                 }
3678                         }
3679                         break;
3680                 case OP_BR_REG:
3681                         amd64_jump_reg (code, ins->sreg1);
3682                         break;
3683                 case OP_CEQ:
3684                 case OP_LCEQ:
3685                 case OP_ICEQ:
3686                 case OP_CLT:
3687                 case OP_LCLT:
3688                 case OP_ICLT:
3689                 case OP_CGT:
3690                 case OP_ICGT:
3691                 case OP_LCGT:
3692                 case OP_CLT_UN:
3693                 case OP_LCLT_UN:
3694                 case OP_ICLT_UN:
3695                 case OP_CGT_UN:
3696                 case OP_LCGT_UN:
3697                 case OP_ICGT_UN:
3698                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3699                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3700                         break;
3701                 case OP_COND_EXC_EQ:
3702                 case OP_COND_EXC_NE_UN:
3703                 case OP_COND_EXC_LT:
3704                 case OP_COND_EXC_LT_UN:
3705                 case OP_COND_EXC_GT:
3706                 case OP_COND_EXC_GT_UN:
3707                 case OP_COND_EXC_GE:
3708                 case OP_COND_EXC_GE_UN:
3709                 case OP_COND_EXC_LE:
3710                 case OP_COND_EXC_LE_UN:
3711                 case OP_COND_EXC_IEQ:
3712                 case OP_COND_EXC_INE_UN:
3713                 case OP_COND_EXC_ILT:
3714                 case OP_COND_EXC_ILT_UN:
3715                 case OP_COND_EXC_IGT:
3716                 case OP_COND_EXC_IGT_UN:
3717                 case OP_COND_EXC_IGE:
3718                 case OP_COND_EXC_IGE_UN:
3719                 case OP_COND_EXC_ILE:
3720                 case OP_COND_EXC_ILE_UN:
3721                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3722                         break;
3723                 case OP_COND_EXC_OV:
3724                 case OP_COND_EXC_NO:
3725                 case OP_COND_EXC_C:
3726                 case OP_COND_EXC_NC:
3727                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3728                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3729                         break;
3730                 case OP_COND_EXC_IOV:
3731                 case OP_COND_EXC_INO:
3732                 case OP_COND_EXC_IC:
3733                 case OP_COND_EXC_INC:
3734                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3735                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3736                         break;
3737
3738                 /* floating point opcodes */
3739                 case OP_R8CONST: {
3740                         double d = *(double *)ins->inst_p0;
3741
3742                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
3743                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3744                         }
3745                         else {
3746                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3747                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3748                         }
3749                         break;
3750                 }
3751                 case OP_R4CONST: {
3752                         float f = *(float *)ins->inst_p0;
3753
3754                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
3755                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3756                         }
3757                         else {
3758                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3759                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3760                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3761                         }
3762                         break;
3763                 }
3764                 case OP_STORER8_MEMBASE_REG:
3765                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3766                         break;
3767                 case OP_LOADR8_SPILL_MEMBASE:
3768                         g_assert_not_reached ();
3769                         break;
3770                 case OP_LOADR8_MEMBASE:
3771                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3772                         break;
3773                 case OP_STORER4_MEMBASE_REG:
3774                         /* This requires a double->single conversion */
3775                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3776                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3777                         break;
3778                 case OP_LOADR4_MEMBASE:
3779                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3780                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3781                         break;
3782                 case OP_ICONV_TO_R4: /* FIXME: change precision */
3783                 case OP_ICONV_TO_R8:
3784                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3785                         break;
3786                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3787                 case OP_LCONV_TO_R8:
3788                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3789                         break;
3790                 case OP_FCONV_TO_R4:
3791                         /* FIXME: nothing to do ?? */
3792                         break;
3793                 case OP_FCONV_TO_I1:
3794                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3795                         break;
3796                 case OP_FCONV_TO_U1:
3797                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3798                         break;
3799                 case OP_FCONV_TO_I2:
3800                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3801                         break;
3802                 case OP_FCONV_TO_U2:
3803                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3804                         break;
3805                 case OP_FCONV_TO_U4:
3806                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3807                         break;
3808                 case OP_FCONV_TO_I4:
3809                 case OP_FCONV_TO_I:
3810                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3811                         break;
3812                 case OP_FCONV_TO_I8:
3813                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3814                         break;
3815                 case OP_LCONV_TO_R_UN: {
3816                         guint8 *br [2];
3817
3818                         /* Based on gcc code */
3819                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3820                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3821
3822                         /* Positive case */
3823                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3824                         br [1] = code; x86_jump8 (code, 0);
3825                         amd64_patch (br [0], code);
3826
3827                         /* Negative case */
3828                         /* Save to the red zone */
3829                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3830                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3831                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3832                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3833                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3834                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3835                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3836                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3837                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3838                         /* Restore */
3839                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3840                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3841                         amd64_patch (br [1], code);
3842                         break;
3843                 }
3844                 case OP_LCONV_TO_OVF_U4:
3845                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3846                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3847                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3848                         break;
3849                 case OP_LCONV_TO_OVF_I4_UN:
3850                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3851                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3852                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3853                         break;
3854                 case OP_FMOVE:
3855                         if (ins->dreg != ins->sreg1)
3856                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3857                         break;
3858                 case OP_FADD:
3859                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3860                         break;
3861                 case OP_FSUB:
3862                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3863                         break;
3864                 case OP_FMUL:
3865                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3866                         break;
3867                 case OP_FDIV:
3868                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3869                         break;
3870                 case OP_FNEG: {
3871                         static double r8_0 = -0.0;
3872
3873                         g_assert (ins->sreg1 == ins->dreg);
3874
3875                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3876                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3877                         break;
3878                 }
3879                 case OP_SIN:
3880                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3881                         break;
3882                 case OP_COS:
3883                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3884                         break;
3885                 case OP_ABS: {
3886                         static guint64 d = 0x7fffffffffffffffUL;
3887
3888                         g_assert (ins->sreg1 == ins->dreg);
3889
3890                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
3891                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3892                         break;
3893                 }
3894                 case OP_SQRT:
3895                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3896                         break;
3897                 case OP_IMIN:
3898                         g_assert (cfg->opt & MONO_OPT_CMOV);
3899                         g_assert (ins->dreg == ins->sreg1);
3900                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3901                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3902                         break;
3903                 case OP_IMIN_UN:
3904                         g_assert (cfg->opt & MONO_OPT_CMOV);
3905                         g_assert (ins->dreg == ins->sreg1);
3906                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3907                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
3908                         break;
3909                 case OP_IMAX:
3910                         g_assert (cfg->opt & MONO_OPT_CMOV);
3911                         g_assert (ins->dreg == ins->sreg1);
3912                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3913                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3914                         break;
3915                 case OP_IMAX_UN:
3916                         g_assert (cfg->opt & MONO_OPT_CMOV);
3917                         g_assert (ins->dreg == ins->sreg1);
3918                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3919                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
3920                         break;
3921                 case OP_LMIN:
3922                         g_assert (cfg->opt & MONO_OPT_CMOV);
3923                         g_assert (ins->dreg == ins->sreg1);
3924                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3925                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3926                         break;
3927                 case OP_LMIN_UN:
3928                         g_assert (cfg->opt & MONO_OPT_CMOV);
3929                         g_assert (ins->dreg == ins->sreg1);
3930                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3931                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3932                         break;
3933                 case OP_LMAX:
3934                         g_assert (cfg->opt & MONO_OPT_CMOV);
3935                         g_assert (ins->dreg == ins->sreg1);
3936                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3937                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3938                         break;
3939                 case OP_LMAX_UN:
3940                         g_assert (cfg->opt & MONO_OPT_CMOV);
3941                         g_assert (ins->dreg == ins->sreg1);
3942                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3943                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3944                         break;
3945                 case OP_X86_FPOP:
3946                         break;
3947                 case OP_FCOMPARE:
3948                         /*
3949                          * The two arguments are swapped because the fbranch instructions
3950                          * depend on this for the non-sse case to work.
3951                          */
3952                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3953                         break;
3954                 case OP_FCEQ: {
3955                         /* zeroing the register at the start results in
3956                          * shorter and faster code (we can also remove the widening op)
3957                          */
3958                         guchar *unordered_check;
3959                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3960                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3961                         unordered_check = code;
3962                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3963                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3964                         amd64_patch (unordered_check, code);
3965                         break;
3966                 }
3967                 case OP_FCLT:
3968                 case OP_FCLT_UN:
3969                         /* zeroing the register at the start results in
3970                          * shorter and faster code (we can also remove the widening op)
3971                          */
3972                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3973                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3974                         if (ins->opcode == OP_FCLT_UN) {
3975                                 guchar *unordered_check = code;
3976                                 guchar *jump_to_end;
3977                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3978                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3979                                 jump_to_end = code;
3980                                 x86_jump8 (code, 0);
3981                                 amd64_patch (unordered_check, code);
3982                                 amd64_inc_reg (code, ins->dreg);
3983                                 amd64_patch (jump_to_end, code);
3984                         } else {
3985                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3986                         }
3987                         break;
3988                 case OP_FCGT:
3989                 case OP_FCGT_UN: {
3990                         /* zeroing the register at the start results in
3991                          * shorter and faster code (we can also remove the widening op)
3992                          */
3993                         guchar *unordered_check;
3994                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3995                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3996                         if (ins->opcode == OP_FCGT) {
3997                                 unordered_check = code;
3998                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3999                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4000                                 amd64_patch (unordered_check, code);
4001                         } else {
4002                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4003                         }
4004                         break;
4005                 }
4006                 case OP_FCLT_MEMBASE:
4007                 case OP_FCGT_MEMBASE:
4008                 case OP_FCLT_UN_MEMBASE:
4009                 case OP_FCGT_UN_MEMBASE:
4010                 case OP_FCEQ_MEMBASE: {
4011                         guchar *unordered_check, *jump_to_end;
4012                         int x86_cond;
4013
4014                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4015                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4016
4017                         switch (ins->opcode) {
4018                         case OP_FCEQ_MEMBASE:
4019                                 x86_cond = X86_CC_EQ;
4020                                 break;
4021                         case OP_FCLT_MEMBASE:
4022                         case OP_FCLT_UN_MEMBASE:
4023                                 x86_cond = X86_CC_LT;
4024                                 break;
4025                         case OP_FCGT_MEMBASE:
4026                         case OP_FCGT_UN_MEMBASE:
4027                                 x86_cond = X86_CC_GT;
4028                                 break;
4029                         default:
4030                                 g_assert_not_reached ();
4031                         }
4032
4033                         unordered_check = code;
4034                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4035                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4036
4037                         switch (ins->opcode) {
4038                         case OP_FCEQ_MEMBASE:
4039                         case OP_FCLT_MEMBASE:
4040                         case OP_FCGT_MEMBASE:
4041                                 amd64_patch (unordered_check, code);
4042                                 break;
4043                         case OP_FCLT_UN_MEMBASE:
4044                         case OP_FCGT_UN_MEMBASE:
4045                                 jump_to_end = code;
4046                                 x86_jump8 (code, 0);
4047                                 amd64_patch (unordered_check, code);
4048                                 amd64_inc_reg (code, ins->dreg);
4049                                 amd64_patch (jump_to_end, code);
4050                                 break;
4051                         default:
4052                                 break;
4053                         }
4054                         break;
4055                 }
4056                 case OP_FBEQ: {
4057                         guchar *jump = code;
4058                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4059                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4060                         amd64_patch (jump, code);
4061                         break;
4062                 }
4063                 case OP_FBNE_UN:
4064                         /* Branch if C013 != 100 */
4065                         /* branch if !ZF or (PF|CF) */
4066                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4067                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4068                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4069                         break;
4070                 case OP_FBLT:
4071                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4072                         break;
4073                 case OP_FBLT_UN:
4074                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4075                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4076                         break;
4077                 case OP_FBGT:
4078                 case OP_FBGT_UN:
4079                         if (ins->opcode == OP_FBGT) {
4080                                 guchar *br1;
4081
4082                                 /* skip branch if C1=1 */
4083                                 br1 = code;
4084                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4085                                 /* branch if (C0 | C3) = 1 */
4086                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4087                                 amd64_patch (br1, code);
4088                                 break;
4089                         } else {
4090                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4091                         }
4092                         break;
4093                 case OP_FBGE: {
4094                         /* Branch if C013 == 100 or 001 */
4095                         guchar *br1;
4096
4097                         /* skip branch if C1=1 */
4098                         br1 = code;
4099                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4100                         /* branch if (C0 | C3) = 1 */
4101                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4102                         amd64_patch (br1, code);
4103                         break;
4104                 }
4105                 case OP_FBGE_UN:
4106                         /* Branch if C013 == 000 */
4107                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4108                         break;
4109                 case OP_FBLE: {
4110                         /* Branch if C013=000 or 100 */
4111                         guchar *br1;
4112
4113                         /* skip branch if C1=1 */
4114                         br1 = code;
4115                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4116                         /* branch if C0=0 */
4117                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4118                         amd64_patch (br1, code);
4119                         break;
4120                 }
4121                 case OP_FBLE_UN:
4122                         /* Branch if C013 != 001 */
4123                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4124                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4125                         break;
4126                 case OP_CKFINITE:
4127                         /* Transfer value to the fp stack */
4128                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4129                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4130                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4131
4132                         amd64_push_reg (code, AMD64_RAX);
4133                         amd64_fxam (code);
4134                         amd64_fnstsw (code);
4135                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4136                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4137                         amd64_pop_reg (code, AMD64_RAX);
4138                         amd64_fstp (code, 0);
4139                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4140                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4141                         break;
4142                 case OP_TLS_GET: {
4143                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4144                         break;
4145                 }
4146                 case OP_MEMORY_BARRIER: {
4147                         /* Not needed on amd64 */
4148                         break;
4149                 }
4150                 case OP_ATOMIC_ADD_I4:
4151                 case OP_ATOMIC_ADD_I8: {
4152                         int dreg = ins->dreg;
4153                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4154
4155                         if (dreg == ins->inst_basereg)
4156                                 dreg = AMD64_R11;
4157
4158                         if (dreg != ins->sreg2)
4159                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4160
4161                         x86_prefix (code, X86_LOCK_PREFIX);
4162                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4163
4164                         if (dreg != ins->dreg)
4165                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4166
4167                         break;
4168                 }
4169                 case OP_ATOMIC_ADD_NEW_I4:
4170                 case OP_ATOMIC_ADD_NEW_I8: {
4171                         int dreg = ins->dreg;
4172                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4173
4174                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4175                                 dreg = AMD64_R11;
4176
4177                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4178                         amd64_prefix (code, X86_LOCK_PREFIX);
4179                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4180                         /* dreg contains the old value, add with sreg2 value */
4181                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4182
4183                         if (ins->dreg != dreg)
4184                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4185
4186                         break;
4187                 }
4188                 case OP_ATOMIC_EXCHANGE_I4:
4189                 case OP_ATOMIC_EXCHANGE_I8:
4190                 case OP_ATOMIC_CAS_IMM_I4: {
4191                         guchar *br[2];
4192                         int sreg2 = ins->sreg2;
4193                         int breg = ins->inst_basereg;
4194                         guint32 size;
4195                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4196
4197                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4198                                 size = 8;
4199                         else
4200                                 size = 4;
4201
4202                         /*
4203                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4204                          * an explanation of how this works.
4205                          */
4206
4207                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4208                          * hack to overcome limits in x86 reg allocator
4209                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4210                          */
4211                         g_assert (ins->dreg == AMD64_RAX);
4212
4213                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4214                                 /* Highly unlikely, but possible */
4215                                 need_push = TRUE;
4216
4217                         /* The pushes invalidate rsp */
4218                         if ((breg == AMD64_RAX) || need_push) {
4219                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4220                                 breg = AMD64_R11;
4221                         }
4222
4223                         /* We need the EAX reg for the comparand */
4224                         if (ins->sreg2 == AMD64_RAX) {
4225                                 if (breg != AMD64_R11) {
4226                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4227                                         sreg2 = AMD64_R11;
4228                                 } else {
4229                                         g_assert (need_push);
4230                                         amd64_push_reg (code, AMD64_RDX);
4231                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4232                                         sreg2 = AMD64_RDX;
4233                                         rdx_pushed = TRUE;
4234                                 }
4235                         }
4236
4237                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4238                                 if (ins->backend.data == NULL)
4239                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4240                                 else
4241                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4242
4243                                 amd64_prefix (code, X86_LOCK_PREFIX);
4244                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4245                         } else {
4246                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4247
4248                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4249                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4250                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4251                                 amd64_patch (br [1], br [0]);
4252                         }
4253
4254                         if (rdx_pushed)
4255                                 amd64_pop_reg (code, AMD64_RDX);
4256
4257                         break;
4258                 }
4259                 case OP_LIVERANGE_START: {
4260                         if (cfg->verbose_level > 1)
4261                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4262                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4263                         break;
4264                 }
4265                 case OP_LIVERANGE_END: {
4266                         if (cfg->verbose_level > 1)
4267                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4268                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4269                         break;
4270                 }
4271                 default:
4272                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4273                         g_assert_not_reached ();
4274                 }
4275
4276                 if ((code - cfg->native_code - offset) > max_len) {
4277                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4278                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4279                         g_assert_not_reached ();
4280                 }
4281
4282                 cpos += max_len;
4283
4284                 last_ins = ins;
4285                 last_offset = offset;
4286         }
4287
4288         cfg->code_len = code - cfg->native_code;
4289 }
4290
4291 #endif /* DISABLE_JIT */
4292
4293 void
4294 mono_arch_register_lowlevel_calls (void)
4295 {
4296         /* The signature doesn't matter */
4297         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4298 }
4299
4300 void
4301 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4302 {
4303         MonoJumpInfo *patch_info;
4304         gboolean compile_aot = !run_cctors;
4305
4306         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4307                 unsigned char *ip = patch_info->ip.i + code;
4308                 unsigned char *target;
4309
4310                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4311
4312                 if (compile_aot) {
4313                         switch (patch_info->type) {
4314                         case MONO_PATCH_INFO_BB:
4315                         case MONO_PATCH_INFO_LABEL:
4316                                 break;
4317                         default:
4318                                 /* No need to patch these */
4319                                 continue;
4320                         }
4321                 }
4322
4323                 switch (patch_info->type) {
4324                 case MONO_PATCH_INFO_NONE:
4325                         continue;
4326                 case MONO_PATCH_INFO_METHOD_REL:
4327                 case MONO_PATCH_INFO_R8:
4328                 case MONO_PATCH_INFO_R4:
4329                         g_assert_not_reached ();
4330                         continue;
4331                 case MONO_PATCH_INFO_BB:
4332                         break;
4333                 default:
4334                         break;
4335                 }
4336
4337                 /*
4338                  * Debug code to help track down problems where the target of a near call is
4339                  * is not valid.
4340                  */
4341                 if (amd64_is_near_call (ip)) {
4342                         gint64 disp = (guint8*)target - (guint8*)ip;
4343
4344                         if (!amd64_is_imm32 (disp)) {
4345                                 printf ("TYPE: %d\n", patch_info->type);
4346                                 switch (patch_info->type) {
4347                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4348                                         printf ("V: %s\n", patch_info->data.name);
4349                                         break;
4350                                 case MONO_PATCH_INFO_METHOD_JUMP:
4351                                 case MONO_PATCH_INFO_METHOD:
4352                                         printf ("V: %s\n", patch_info->data.method->name);
4353                                         break;
4354                                 default:
4355                                         break;
4356                                 }
4357                         }
4358                 }
4359
4360                 amd64_patch (ip, (gpointer)target);
4361         }
4362 }
4363
4364 static int
4365 get_max_epilog_size (MonoCompile *cfg)
4366 {
4367         int max_epilog_size = 16;
4368
4369         if (cfg->method->save_lmf)
4370                 max_epilog_size += 256;
4371
4372         if (mono_jit_trace_calls != NULL)
4373                 max_epilog_size += 50;
4374
4375         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4376                 max_epilog_size += 50;
4377
4378         max_epilog_size += (AMD64_NREG * 2);
4379
4380         return max_epilog_size;
4381 }
4382
4383 /*
4384  * This macro is used for testing whenever the unwinder works correctly at every point
4385  * where an async exception can happen.
4386  */
4387 /* This will generate a SIGSEGV at the given point in the code */
4388 #define async_exc_point(code) do { \
4389     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4390          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4391              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4392          cfg->arch.async_point_count ++; \
4393     } \
4394 } while (0)
4395
4396 guint8 *
4397 mono_arch_emit_prolog (MonoCompile *cfg)
4398 {
4399         MonoMethod *method = cfg->method;
4400         MonoBasicBlock *bb;
4401         MonoMethodSignature *sig;
4402         MonoInst *ins;
4403         int alloc_size, pos, max_offset, i, cfa_offset, quad, max_epilog_size;
4404         guint8 *code;
4405         CallInfo *cinfo;
4406         gint32 lmf_offset = cfg->arch.lmf_offset;
4407         gboolean args_clobbered = FALSE;
4408         gboolean trace = FALSE;
4409
4410         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4411
4412         code = cfg->native_code = g_malloc (cfg->code_size);
4413
4414         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4415                 trace = TRUE;
4416
4417         /* Amount of stack space allocated by register saving code */
4418         pos = 0;
4419
4420         /* Offset between RSP and the CFA */
4421         cfa_offset = 0;
4422
4423         /*
4424          * The prolog consists of the following parts:
4425          * FP present:
4426          * - push rbp, mov rbp, rsp
4427          * - save callee saved regs using pushes
4428          * - allocate frame
4429          * - save rgctx if needed
4430          * - save lmf if needed
4431          * FP not present:
4432          * - allocate frame
4433          * - save rgctx if needed
4434          * - save lmf if needed
4435          * - save callee saved regs using moves
4436          */
4437
4438         // CFA = sp + 8
4439         cfa_offset = 8;
4440         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4441         // IP saved at CFA - 8
4442         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4443         async_exc_point (code);
4444
4445         if (!cfg->arch.omit_fp) {
4446                 amd64_push_reg (code, AMD64_RBP);
4447                 cfa_offset += 8;
4448                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4449                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4450                 async_exc_point (code);
4451 #ifdef PLATFORM_WIN32
4452                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4453 #endif
4454
4455                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4456                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4457                 async_exc_point (code);
4458 #ifdef PLATFORM_WIN32
4459                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4460 #endif
4461         }
4462
4463         /* Save callee saved registers */
4464         if (!cfg->arch.omit_fp && !method->save_lmf) {
4465                 int offset = cfa_offset;
4466
4467                 for (i = 0; i < AMD64_NREG; ++i)
4468                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4469                                 amd64_push_reg (code, i);
4470                                 pos += sizeof (gpointer);
4471                                 offset += 8;
4472                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4473                                 async_exc_point (code);
4474                         }
4475         }
4476
4477         if (cfg->arch.omit_fp) {
4478                 /*
4479                  * On enter, the stack is misaligned by the the pushing of the return
4480                  * address. It is either made aligned by the pushing of %rbp, or by
4481                  * this.
4482                  */
4483                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4484                 if ((alloc_size % 16) == 0)
4485                         alloc_size += 8;
4486         } else {
4487                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4488
4489                 alloc_size -= pos;
4490         }
4491
4492         cfg->arch.stack_alloc_size = alloc_size;
4493
4494         /* Allocate stack frame */
4495         if (alloc_size) {
4496                 /* See mono_emit_stack_alloc */
4497 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4498                 guint32 remaining_size = alloc_size;
4499                 while (remaining_size >= 0x1000) {
4500                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4501                         if (cfg->arch.omit_fp) {
4502                                 cfa_offset += 0x1000;
4503                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4504                         }
4505                         async_exc_point (code);
4506 #ifdef PLATFORM_WIN32
4507                         if (cfg->arch.omit_fp)
4508                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4509 #endif
4510
4511                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4512                         remaining_size -= 0x1000;
4513                 }
4514                 if (remaining_size) {
4515                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4516                         if (cfg->arch.omit_fp) {
4517                                 cfa_offset += remaining_size;
4518                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4519                                 async_exc_point (code);
4520                         }
4521 #ifdef PLATFORM_WIN32
4522                         if (cfg->arch.omit_fp)
4523                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4524 #endif
4525                 }
4526 #else
4527                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4528                 if (cfg->arch.omit_fp) {
4529                         cfa_offset += alloc_size;
4530                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4531                         async_exc_point (code);
4532                 }
4533 #endif
4534         }
4535
4536         /* Stack alignment check */
4537 #if 0
4538         {
4539                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4540                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4541                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4542                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4543                 amd64_breakpoint (code);
4544         }
4545 #endif
4546
4547         /* Save LMF */
4548         if (method->save_lmf) {
4549                 /*
4550                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4551                  */
4552                 /* sp is saved right before calls */
4553                 /* Skip method (only needed for trampoline LMF frames) */
4554                 /* Save callee saved regs */
4555                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
4556                         int offset;
4557
4558                         switch (i) {
4559                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
4560                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
4561                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
4562                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
4563                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
4564                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
4565 #ifdef PLATFORM_WIN32
4566                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
4567                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
4568 #endif
4569                         default:
4570                                 offset = -1;
4571                                 break;
4572                         }
4573
4574                         if (offset != -1) {
4575                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
4576                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
4577                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
4578                         }
4579                 }
4580         }
4581
4582         /* Save callee saved registers */
4583         if (cfg->arch.omit_fp && !method->save_lmf) {
4584                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4585
4586                 /* Save caller saved registers after sp is adjusted */
4587                 /* The registers are saved at the bottom of the frame */
4588                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4589                 for (i = 0; i < AMD64_NREG; ++i)
4590                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4591                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4592                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
4593                                 save_area_offset += 8;
4594                                 async_exc_point (code);
4595                         }
4596         }
4597
4598         /* store runtime generic context */
4599         if (cfg->rgctx_var) {
4600                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4601                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4602
4603                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4604         }
4605
4606         /* compute max_offset in order to use short forward jumps */
4607         max_offset = 0;
4608         max_epilog_size = get_max_epilog_size (cfg);
4609         if (cfg->opt & MONO_OPT_BRANCH) {
4610                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4611                         MonoInst *ins;
4612                         bb->max_offset = max_offset;
4613
4614                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4615                                 max_offset += 6;
4616                         /* max alignment for loops */
4617                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4618                                 max_offset += LOOP_ALIGNMENT;
4619
4620                         MONO_BB_FOR_EACH_INS (bb, ins) {
4621                                 if (ins->opcode == OP_LABEL)
4622                                         ins->inst_c1 = max_offset;
4623
4624                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4625                         }
4626
4627                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4628                                 /* The tracing code can be quite large */
4629                                 max_offset += max_epilog_size;
4630                 }
4631         }
4632
4633         sig = mono_method_signature (method);
4634         pos = 0;
4635
4636         cinfo = cfg->arch.cinfo;
4637
4638         if (sig->ret->type != MONO_TYPE_VOID) {
4639                 /* Save volatile arguments to the stack */
4640                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4641                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4642         }
4643
4644         /* Keep this in sync with emit_load_volatile_arguments */
4645         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4646                 ArgInfo *ainfo = cinfo->args + i;
4647                 gint32 stack_offset;
4648                 MonoType *arg_type;
4649
4650                 ins = cfg->args [i];
4651
4652                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4653                         /* Unused arguments */
4654                         continue;
4655
4656                 if (sig->hasthis && (i == 0))
4657                         arg_type = &mono_defaults.object_class->byval_arg;
4658                 else
4659                         arg_type = sig->params [i - sig->hasthis];
4660
4661                 stack_offset = ainfo->offset + ARGS_OFFSET;
4662
4663                 if (cfg->globalra) {
4664                         /* All the other moves are done by the register allocator */
4665                         switch (ainfo->storage) {
4666                         case ArgInFloatSSEReg:
4667                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
4668                                 break;
4669                         case ArgValuetypeInReg:
4670                                 for (quad = 0; quad < 2; quad ++) {
4671                                         switch (ainfo->pair_storage [quad]) {
4672                                         case ArgInIReg:
4673                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4674                                                 break;
4675                                         case ArgInFloatSSEReg:
4676                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4677                                                 break;
4678                                         case ArgInDoubleSSEReg:
4679                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4680                                                 break;
4681                                         case ArgNone:
4682                                                 break;
4683                                         default:
4684                                                 g_assert_not_reached ();
4685                                         }
4686                                 }
4687                                 break;
4688                         default:
4689                                 break;
4690                         }
4691
4692                         continue;
4693                 }
4694
4695                 /* Save volatile arguments to the stack */
4696                 if (ins->opcode != OP_REGVAR) {
4697                         switch (ainfo->storage) {
4698                         case ArgInIReg: {
4699                                 guint32 size = 8;
4700
4701                                 /* FIXME: I1 etc */
4702                                 /*
4703                                 if (stack_offset & 0x1)
4704                                         size = 1;
4705                                 else if (stack_offset & 0x2)
4706                                         size = 2;
4707                                 else if (stack_offset & 0x4)
4708                                         size = 4;
4709                                 else
4710                                         size = 8;
4711                                 */
4712                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4713                                 break;
4714                         }
4715                         case ArgInFloatSSEReg:
4716                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4717                                 break;
4718                         case ArgInDoubleSSEReg:
4719                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4720                                 break;
4721                         case ArgValuetypeInReg:
4722                                 for (quad = 0; quad < 2; quad ++) {
4723                                         switch (ainfo->pair_storage [quad]) {
4724                                         case ArgInIReg:
4725                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4726                                                 break;
4727                                         case ArgInFloatSSEReg:
4728                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4729                                                 break;
4730                                         case ArgInDoubleSSEReg:
4731                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4732                                                 break;
4733                                         case ArgNone:
4734                                                 break;
4735                                         default:
4736                                                 g_assert_not_reached ();
4737                                         }
4738                                 }
4739                                 break;
4740                         case ArgValuetypeAddrInIReg:
4741                                 if (ainfo->pair_storage [0] == ArgInIReg)
4742                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
4743                                 break;
4744                         default:
4745                                 break;
4746                         }
4747                 } else {
4748                         /* Argument allocated to (non-volatile) register */
4749                         switch (ainfo->storage) {
4750                         case ArgInIReg:
4751                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4752                                 break;
4753                         case ArgOnStack:
4754                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4755                                 break;
4756                         default:
4757                                 g_assert_not_reached ();
4758                         }
4759                 }
4760         }
4761
4762         /* Might need to attach the thread to the JIT  or change the domain for the callback */
4763         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4764                 guint64 domain = (guint64)cfg->domain;
4765
4766                 args_clobbered = TRUE;
4767
4768                 /*
4769                  * The call might clobber argument registers, but they are already
4770                  * saved to the stack/global regs.
4771                  */
4772                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4773                         guint8 *buf, *no_domain_branch;
4774
4775                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4776                         if ((domain >> 32) == 0)
4777                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4778                         else
4779                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4780                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4781                         no_domain_branch = code;
4782                         x86_branch8 (code, X86_CC_NE, 0, 0);
4783                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4784                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4785                         buf = code;
4786                         x86_branch8 (code, X86_CC_NE, 0, 0);
4787                         amd64_patch (no_domain_branch, code);
4788                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4789                                           (gpointer)"mono_jit_thread_attach", TRUE);
4790                         amd64_patch (buf, code);
4791 #ifdef PLATFORM_WIN32
4792                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4793                         /* FIXME: Add a separate key for LMF to avoid this */
4794                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4795 #endif
4796                 } else {
4797                         g_assert (!cfg->compile_aot);
4798                         if ((domain >> 32) == 0)
4799                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4800                         else
4801                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4802                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4803                                           (gpointer)"mono_jit_thread_attach", TRUE);
4804                 }
4805         }
4806
4807         if (method->save_lmf) {
4808                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4809                         /*
4810                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4811                          * through the mono_lmf_addr TLS variable.
4812                          */
4813                         /* %rax = previous_lmf */
4814                         x86_prefix (code, X86_FS_PREFIX);
4815                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4816
4817                         /* Save previous_lmf */
4818                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4819                         /* Set new lmf */
4820                         if (lmf_offset == 0) {
4821                                 x86_prefix (code, X86_FS_PREFIX);
4822                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4823                         } else {
4824                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4825                                 x86_prefix (code, X86_FS_PREFIX);
4826                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4827                         }
4828                 } else {
4829                         if (lmf_addr_tls_offset != -1) {
4830                                 /* Load lmf quicky using the FS register */
4831                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4832 #ifdef PLATFORM_WIN32
4833                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4834                                 /* FIXME: Add a separate key for LMF to avoid this */
4835                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4836 #endif
4837                         }
4838                         else {
4839                                 /*
4840                                  * The call might clobber argument registers, but they are already
4841                                  * saved to the stack/global regs.
4842                                  */
4843                                 args_clobbered = TRUE;
4844                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4845                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
4846                         }
4847
4848                         /* Save lmf_addr */
4849                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4850                         /* Save previous_lmf */
4851                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4852                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4853                         /* Set new lmf */
4854                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4855                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4856                 }
4857         }
4858
4859         if (trace) {
4860                 args_clobbered = TRUE;
4861                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4862         }
4863
4864         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4865                 args_clobbered = TRUE;
4866
4867         /*
4868          * Optimize the common case of the first bblock making a call with the same
4869          * arguments as the method. This works because the arguments are still in their
4870          * original argument registers.
4871          * FIXME: Generalize this
4872          */
4873         if (!args_clobbered) {
4874                 MonoBasicBlock *first_bb = cfg->bb_entry;
4875                 MonoInst *next;
4876
4877                 next = mono_bb_first_ins (first_bb);
4878                 if (!next && first_bb->next_bb) {
4879                         first_bb = first_bb->next_bb;
4880                         next = mono_bb_first_ins (first_bb);
4881                 }
4882
4883                 if (first_bb->in_count > 1)
4884                         next = NULL;
4885
4886                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4887                         ArgInfo *ainfo = cinfo->args + i;
4888                         gboolean match = FALSE;
4889
4890                         ins = cfg->args [i];
4891                         if (ins->opcode != OP_REGVAR) {
4892                                 switch (ainfo->storage) {
4893                                 case ArgInIReg: {
4894                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4895                                                 if (next->dreg == ainfo->reg) {
4896                                                         NULLIFY_INS (next);
4897                                                         match = TRUE;
4898                                                 } else {
4899                                                         next->opcode = OP_MOVE;
4900                                                         next->sreg1 = ainfo->reg;
4901                                                         /* Only continue if the instruction doesn't change argument regs */
4902                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4903                                                                 match = TRUE;
4904                                                 }
4905                                         }
4906                                         break;
4907                                 }
4908                                 default:
4909                                         break;
4910                                 }
4911                         } else {
4912                                 /* Argument allocated to (non-volatile) register */
4913                                 switch (ainfo->storage) {
4914                                 case ArgInIReg:
4915                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4916                                                 NULLIFY_INS (next);
4917                                                 match = TRUE;
4918                                         }
4919                                         break;
4920                                 default:
4921                                         break;
4922                                 }
4923                         }
4924
4925                         if (match) {
4926                                 next = next->next;
4927                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4928                                 if (!next)
4929                                         break;
4930                         }
4931                 }
4932         }
4933
4934         cfg->code_len = code - cfg->native_code;
4935
4936         g_assert (cfg->code_len < cfg->code_size);
4937
4938         return code;
4939 }
4940
4941 void
4942 mono_arch_emit_epilog (MonoCompile *cfg)
4943 {
4944         MonoMethod *method = cfg->method;
4945         int quad, pos, i;
4946         guint8 *code;
4947         int max_epilog_size;
4948         CallInfo *cinfo;
4949         gint32 lmf_offset = cfg->arch.lmf_offset;
4950
4951         max_epilog_size = get_max_epilog_size (cfg);
4952
4953         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4954                 cfg->code_size *= 2;
4955                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4956                 mono_jit_stats.code_reallocs++;
4957         }
4958
4959         code = cfg->native_code + cfg->code_len;
4960
4961         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4962                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4963
4964         /* the code restoring the registers must be kept in sync with OP_JMP */
4965         pos = 0;
4966
4967         if (method->save_lmf) {
4968                 /* check if we need to restore protection of the stack after a stack overflow */
4969                 if (mono_get_jit_tls_offset () != -1) {
4970                         guint8 *patch;
4971                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4972                         /* we load the value in a separate instruction: this mechanism may be
4973                          * used later as a safer way to do thread interruption
4974                          */
4975                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
4976                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4977                         patch = code;
4978                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
4979                         /* note that the call trampoline will preserve eax/edx */
4980                         x86_call_reg (code, X86_ECX);
4981                         x86_patch (patch, code);
4982                 } else {
4983                         /* FIXME: maybe save the jit tls in the prolog */
4984                 }
4985                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4986                         /*
4987                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4988                          * through the mono_lmf_addr TLS variable.
4989                          */
4990                         /* reg = previous_lmf */
4991                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4992                         x86_prefix (code, X86_FS_PREFIX);
4993                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4994                 } else {
4995                         /* Restore previous lmf */
4996                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4997                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4998                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4999                 }
5000
5001                 /* Restore caller saved regs */
5002                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5003                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5004                 }
5005                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5006                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5007                 }
5008                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5009                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5010                 }
5011                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5012                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5013                 }
5014                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5015                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5016                 }
5017                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5018                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5019                 }
5020 #ifdef PLATFORM_WIN32
5021                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
5022                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
5023                 }
5024                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
5025                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
5026                 }
5027 #endif
5028         } else {
5029
5030                 if (cfg->arch.omit_fp) {
5031                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5032
5033                         for (i = 0; i < AMD64_NREG; ++i)
5034                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5035                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5036                                         save_area_offset += 8;
5037                                 }
5038                 }
5039                 else {
5040                         for (i = 0; i < AMD64_NREG; ++i)
5041                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5042                                         pos -= sizeof (gpointer);
5043
5044                         if (pos) {
5045                                 if (pos == - sizeof (gpointer)) {
5046                                         /* Only one register, so avoid lea */
5047                                         for (i = AMD64_NREG - 1; i > 0; --i)
5048                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5049                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5050                                                 }
5051                                 }
5052                                 else {
5053                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5054
5055                                         /* Pop registers in reverse order */
5056                                         for (i = AMD64_NREG - 1; i > 0; --i)
5057                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5058                                                         amd64_pop_reg (code, i);
5059                                                 }
5060                                 }
5061                         }
5062                 }
5063         }
5064
5065         /* Load returned vtypes into registers if needed */
5066         cinfo = cfg->arch.cinfo;
5067         if (cinfo->ret.storage == ArgValuetypeInReg) {
5068                 ArgInfo *ainfo = &cinfo->ret;
5069                 MonoInst *inst = cfg->ret;
5070
5071                 for (quad = 0; quad < 2; quad ++) {
5072                         switch (ainfo->pair_storage [quad]) {
5073                         case ArgInIReg:
5074                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5075                                 break;
5076                         case ArgInFloatSSEReg:
5077                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5078                                 break;
5079                         case ArgInDoubleSSEReg:
5080                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5081                                 break;
5082                         case ArgNone:
5083                                 break;
5084                         default:
5085                                 g_assert_not_reached ();
5086                         }
5087                 }
5088         }
5089
5090         if (cfg->arch.omit_fp) {
5091                 if (cfg->arch.stack_alloc_size)
5092                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5093         } else {
5094                 amd64_leave (code);
5095         }
5096         async_exc_point (code);
5097         amd64_ret (code);
5098
5099         cfg->code_len = code - cfg->native_code;
5100
5101         g_assert (cfg->code_len < cfg->code_size);
5102
5103         if (cfg->arch.omit_fp) {
5104                 /*
5105                  * Encode the stack size into used_int_regs so the exception handler
5106                  * can access it.
5107                  */
5108                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5109                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5110         }
5111 }
5112
5113 void
5114 mono_arch_emit_exceptions (MonoCompile *cfg)
5115 {
5116         MonoJumpInfo *patch_info;
5117         int nthrows, i;
5118         guint8 *code;
5119         MonoClass *exc_classes [16];
5120         guint8 *exc_throw_start [16], *exc_throw_end [16];
5121         guint32 code_size = 0;
5122
5123         /* Compute needed space */
5124         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5125                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5126                         code_size += 40;
5127                 if (patch_info->type == MONO_PATCH_INFO_R8)
5128                         code_size += 8 + 15; /* sizeof (double) + alignment */
5129                 if (patch_info->type == MONO_PATCH_INFO_R4)
5130                         code_size += 4 + 15; /* sizeof (float) + alignment */
5131         }
5132
5133         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5134                 cfg->code_size *= 2;
5135                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5136                 mono_jit_stats.code_reallocs++;
5137         }
5138
5139         code = cfg->native_code + cfg->code_len;
5140
5141         /* add code to raise exceptions */
5142         nthrows = 0;
5143         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5144                 switch (patch_info->type) {
5145                 case MONO_PATCH_INFO_EXC: {
5146                         MonoClass *exc_class;
5147                         guint8 *buf, *buf2;
5148                         guint32 throw_ip;
5149
5150                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5151
5152                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5153                         g_assert (exc_class);
5154                         throw_ip = patch_info->ip.i;
5155
5156                         //x86_breakpoint (code);
5157                         /* Find a throw sequence for the same exception class */
5158                         for (i = 0; i < nthrows; ++i)
5159                                 if (exc_classes [i] == exc_class)
5160                                         break;
5161                         if (i < nthrows) {
5162                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5163                                 x86_jump_code (code, exc_throw_start [i]);
5164                                 patch_info->type = MONO_PATCH_INFO_NONE;
5165                         }
5166                         else {
5167                                 buf = code;
5168                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5169                                 buf2 = code;
5170
5171                                 if (nthrows < 16) {
5172                                         exc_classes [nthrows] = exc_class;
5173                                         exc_throw_start [nthrows] = code;
5174                                 }
5175                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5176
5177                                 patch_info->type = MONO_PATCH_INFO_NONE;
5178
5179                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5180
5181                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5182                                 while (buf < buf2)
5183                                         x86_nop (buf);
5184
5185                                 if (nthrows < 16) {
5186                                         exc_throw_end [nthrows] = code;
5187                                         nthrows ++;
5188                                 }
5189                         }
5190                         break;
5191                 }
5192                 default:
5193                         /* do nothing */
5194                         break;
5195                 }
5196         }
5197
5198         /* Handle relocations with RIP relative addressing */
5199         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5200                 gboolean remove = FALSE;
5201
5202                 switch (patch_info->type) {
5203                 case MONO_PATCH_INFO_R8:
5204                 case MONO_PATCH_INFO_R4: {
5205                         guint8 *pos;
5206
5207                         /* The SSE opcodes require a 16 byte alignment */
5208                         code = (guint8*)ALIGN_TO (code, 16);
5209
5210                         pos = cfg->native_code + patch_info->ip.i;
5211
5212                         if (IS_REX (pos [1]))
5213                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5214                         else
5215                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5216
5217                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5218                                 *(double*)code = *(double*)patch_info->data.target;
5219                                 code += sizeof (double);
5220                         } else {
5221                                 *(float*)code = *(float*)patch_info->data.target;
5222                                 code += sizeof (float);
5223                         }
5224
5225                         remove = TRUE;
5226                         break;
5227                 }
5228                 default:
5229                         break;
5230                 }
5231
5232                 if (remove) {
5233                         if (patch_info == cfg->patch_info)
5234                                 cfg->patch_info = patch_info->next;
5235                         else {
5236                                 MonoJumpInfo *tmp;
5237
5238                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5239                                         ;
5240                                 tmp->next = patch_info->next;
5241                         }
5242                 }
5243         }
5244
5245         cfg->code_len = code - cfg->native_code;
5246
5247         g_assert (cfg->code_len < cfg->code_size);
5248
5249 }
5250
5251 void*
5252 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5253 {
5254         guchar *code = p;
5255         CallInfo *cinfo = NULL;
5256         MonoMethodSignature *sig;
5257         MonoInst *inst;
5258         int i, n, stack_area = 0;
5259
5260         /* Keep this in sync with mono_arch_get_argument_info */
5261
5262         if (enable_arguments) {
5263                 /* Allocate a new area on the stack and save arguments there */
5264                 sig = mono_method_signature (cfg->method);
5265
5266                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5267
5268                 n = sig->param_count + sig->hasthis;
5269
5270                 stack_area = ALIGN_TO (n * 8, 16);
5271
5272                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5273
5274                 for (i = 0; i < n; ++i) {
5275                         inst = cfg->args [i];
5276
5277                         if (inst->opcode == OP_REGVAR)
5278                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5279                         else {
5280                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5281                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5282                         }
5283                 }
5284         }
5285
5286         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5287         amd64_set_reg_template (code, AMD64_ARG_REG1);
5288         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5289         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5290
5291         if (enable_arguments)
5292                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5293
5294         return code;
5295 }
5296
5297 enum {
5298         SAVE_NONE,
5299         SAVE_STRUCT,
5300         SAVE_EAX,
5301         SAVE_EAX_EDX,
5302         SAVE_XMM
5303 };
5304
5305 void*
5306 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5307 {
5308         guchar *code = p;
5309         int save_mode = SAVE_NONE;
5310         MonoMethod *method = cfg->method;
5311         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5312
5313         switch (rtype) {
5314         case MONO_TYPE_VOID:
5315                 /* special case string .ctor icall */
5316                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5317                         save_mode = SAVE_EAX;
5318                 else
5319                         save_mode = SAVE_NONE;
5320                 break;
5321         case MONO_TYPE_I8:
5322         case MONO_TYPE_U8:
5323                 save_mode = SAVE_EAX;
5324                 break;
5325         case MONO_TYPE_R4:
5326         case MONO_TYPE_R8:
5327                 save_mode = SAVE_XMM;
5328                 break;
5329         case MONO_TYPE_GENERICINST:
5330                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5331                         save_mode = SAVE_EAX;
5332                         break;
5333                 }
5334                 /* Fall through */
5335         case MONO_TYPE_VALUETYPE:
5336                 save_mode = SAVE_STRUCT;
5337                 break;
5338         default:
5339                 save_mode = SAVE_EAX;
5340                 break;
5341         }
5342
5343         /* Save the result and copy it into the proper argument register */
5344         switch (save_mode) {
5345         case SAVE_EAX:
5346                 amd64_push_reg (code, AMD64_RAX);
5347                 /* Align stack */
5348                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5349                 if (enable_arguments)
5350                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5351                 break;
5352         case SAVE_STRUCT:
5353                 /* FIXME: */
5354                 if (enable_arguments)
5355                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5356                 break;
5357         case SAVE_XMM:
5358                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5359                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5360                 /* Align stack */
5361                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5362                 /*
5363                  * The result is already in the proper argument register so no copying
5364                  * needed.
5365                  */
5366                 break;
5367         case SAVE_NONE:
5368                 break;
5369         default:
5370                 g_assert_not_reached ();
5371         }
5372
5373         /* Set %al since this is a varargs call */
5374         if (save_mode == SAVE_XMM)
5375                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5376         else
5377                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5378
5379         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5380         amd64_set_reg_template (code, AMD64_ARG_REG1);
5381         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5382
5383         /* Restore result */
5384         switch (save_mode) {
5385         case SAVE_EAX:
5386                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5387                 amd64_pop_reg (code, AMD64_RAX);
5388                 break;
5389         case SAVE_STRUCT:
5390                 /* FIXME: */
5391                 break;
5392         case SAVE_XMM:
5393                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5394                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5395                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5396                 break;
5397         case SAVE_NONE:
5398                 break;
5399         default:
5400                 g_assert_not_reached ();
5401         }
5402
5403         return code;
5404 }
5405
5406 void
5407 mono_arch_flush_icache (guint8 *code, gint size)
5408 {
5409         /* Not needed */
5410 }
5411
5412 void
5413 mono_arch_flush_register_windows (void)
5414 {
5415 }
5416
5417 gboolean
5418 mono_arch_is_inst_imm (gint64 imm)
5419 {
5420         return amd64_is_imm32 (imm);
5421 }
5422
5423 /*
5424  * Determine whenever the trap whose info is in SIGINFO is caused by
5425  * integer overflow.
5426  */
5427 gboolean
5428 mono_arch_is_int_overflow (void *sigctx, void *info)
5429 {
5430         MonoContext ctx;
5431         guint8* rip;
5432         int reg;
5433         gint64 value;
5434
5435         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5436
5437         rip = (guint8*)ctx.rip;
5438
5439         if (IS_REX (rip [0])) {
5440                 reg = amd64_rex_b (rip [0]);
5441                 rip ++;
5442         }
5443         else
5444                 reg = 0;
5445
5446         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5447                 /* idiv REG */
5448                 reg += x86_modrm_rm (rip [1]);
5449
5450                 switch (reg) {
5451                 case AMD64_RAX:
5452                         value = ctx.rax;
5453                         break;
5454                 case AMD64_RBX:
5455                         value = ctx.rbx;
5456                         break;
5457                 case AMD64_RCX:
5458                         value = ctx.rcx;
5459                         break;
5460                 case AMD64_RDX:
5461                         value = ctx.rdx;
5462                         break;
5463                 case AMD64_RBP:
5464                         value = ctx.rbp;
5465                         break;
5466                 case AMD64_RSP:
5467                         value = ctx.rsp;
5468                         break;
5469                 case AMD64_RSI:
5470                         value = ctx.rsi;
5471                         break;
5472                 case AMD64_RDI:
5473                         value = ctx.rdi;
5474                         break;
5475                 case AMD64_R12:
5476                         value = ctx.r12;
5477                         break;
5478                 case AMD64_R13:
5479                         value = ctx.r13;
5480                         break;
5481                 case AMD64_R14:
5482                         value = ctx.r14;
5483                         break;
5484                 case AMD64_R15:
5485                         value = ctx.r15;
5486                         break;
5487                 default:
5488                         g_assert_not_reached ();
5489                         reg = -1;
5490                 }
5491
5492                 if (value == -1)
5493                         return TRUE;
5494         }
5495
5496         return FALSE;
5497 }
5498
5499 guint32
5500 mono_arch_get_patch_offset (guint8 *code)
5501 {
5502         return 3;
5503 }
5504
5505 /**
5506  * mono_breakpoint_clean_code:
5507  *
5508  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5509  * breakpoints in the original code, they are removed in the copy.
5510  *
5511  * Returns TRUE if no sw breakpoint was present.
5512  */
5513 gboolean
5514 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5515 {
5516         int i;
5517         gboolean can_write = TRUE;
5518         /*
5519          * If method_start is non-NULL we need to perform bound checks, since we access memory
5520          * at code - offset we could go before the start of the method and end up in a different
5521          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5522          * instead.
5523          */
5524         if (!method_start || code - offset >= method_start) {
5525                 memcpy (buf, code - offset, size);
5526         } else {
5527                 int diff = code - method_start;
5528                 memset (buf, 0, size);
5529                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5530         }
5531         code -= offset;
5532         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5533                 int idx = mono_breakpoint_info_index [i];
5534                 guint8 *ptr;
5535                 if (idx < 1)
5536                         continue;
5537                 ptr = mono_breakpoint_info [idx].address;
5538                 if (ptr >= code && ptr < code + size) {
5539                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5540                         can_write = FALSE;
5541                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5542                         buf [ptr - code] = saved_byte;
5543                 }
5544         }
5545         return can_write;
5546 }
5547
5548 gpointer
5549 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5550 {
5551         guint8 buf [10];
5552         guint32 reg;
5553         gint32 disp;
5554         guint8 rex = 0;
5555
5556         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5557         code = buf + 9;
5558
5559         *displacement = 0;
5560
5561         /* go to the start of the call instruction
5562          *
5563          * address_byte = (m << 6) | (o << 3) | reg
5564          * call opcode: 0xff address_byte displacement
5565          * 0xff m=1,o=2 imm8
5566          * 0xff m=2,o=2 imm32
5567          */
5568         code -= 7;
5569
5570         /*
5571          * A given byte sequence can match more than case here, so we have to be
5572          * really careful about the ordering of the cases. Longer sequences
5573          * come first.
5574          * Some of the rules are only needed because the imm in the mov could
5575          * match the
5576          * code [2] == 0xe8 case below.
5577          */
5578 #ifdef MONO_ARCH_HAVE_IMT
5579         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5580                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5581                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5582                  * ff 50 fc                call   *0xfffffffc(%rax)
5583                  */
5584                 reg = amd64_modrm_rm (code [5]);
5585                 disp = (signed char)code [6];
5586                 /* R10 is clobbered by the IMT thunk code */
5587                 g_assert (reg != AMD64_R10);
5588         }
5589 #else
5590         if (0) {
5591         }
5592 #endif
5593         else if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5594                 /*
5595                  * 41 bb e8 e8 e8 e8     mov    $0xe8e8e8e8,%r11d
5596                  * ff 50 60              callq  *0x60(%rax)
5597                  */
5598                 if (IS_REX (code [3]))
5599                         rex = code [3];
5600                 reg = amd64_modrm_rm (code [5]);
5601                 disp = *(gint8*)(code + 6);
5602                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5603         } else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5604                 /*
5605                  * This is a interface call
5606                  * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5607                  * ff 10                  callq  *(%rax)
5608                  */
5609                 if (IS_REX (code [4]))
5610                         rex = code [4];
5611                 reg = amd64_modrm_rm (code [6]);
5612                 disp = 0;
5613                 /* R10 is clobbered by the IMT thunk code */
5614                 g_assert (reg != AMD64_R10);
5615         } else if ((code [-1] >= 0xb8) && (code [-1] < 0xb8 + 8) && (code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5616                 /*
5617                  * ba e8 e8 e8 e8     mov    $0xe8e8e8e8,%edx
5618                  * ff 50 60              callq  *0x60(%rax)
5619                  */
5620                 if (IS_REX (code [3]))
5621                         rex = code [3];
5622                 reg = amd64_modrm_rm (code [5]);
5623                 disp = *(gint8*)(code + 6);
5624         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5625                 /* call OFFSET(%rip) */
5626                 disp = *(guint32*)(code + 3);
5627                 return (gpointer*)(code + disp + 7);
5628         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5629                 /* call *[r12+disp32] */
5630                 if (IS_REX (code [-1]))
5631                         rex = code [-1];
5632                 reg = AMD64_RSP;
5633                 disp = *(gint32*)(code + 3);
5634         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5635                 /* call *[reg+disp32] */
5636                 if (IS_REX (code [0]))
5637                         rex = code [0];
5638                 reg = amd64_modrm_rm (code [2]);
5639                 disp = *(gint32*)(code + 3);
5640                 /* R10 is clobbered by the IMT thunk code */
5641                 g_assert (reg != AMD64_R10);
5642         } else if (code [2] == 0xe8) {
5643                 /* call <ADDR> */
5644                 return NULL;
5645         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5646                 /* call *[r12+disp32] */
5647                 if (IS_REX (code [2]))
5648                         rex = code [2];
5649                 reg = AMD64_RSP;
5650                 disp = *(gint8*)(code + 6);
5651         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5652                 /* call *%reg */
5653                 return NULL;
5654         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5655                 /* call *[reg+disp8] */
5656                 if (IS_REX (code [3]))
5657                         rex = code [3];
5658                 reg = amd64_modrm_rm (code [5]);
5659                 disp = *(gint8*)(code + 6);
5660                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5661         }
5662         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5663                         /*
5664                          * This is a interface call: should check the above code can't catch it earlier
5665                          * 8b 40 30   mov    0x30(%eax),%eax
5666                          * ff 10      call   *(%eax)
5667                          */
5668                 if (IS_REX (code [4]))
5669                         rex = code [4];
5670                 reg = amd64_modrm_rm (code [6]);
5671                 disp = 0;
5672         }
5673         else
5674                 g_assert_not_reached ();
5675
5676         reg += amd64_rex_b (rex);
5677
5678         /* R11 is clobbered by the trampoline code */
5679         g_assert (reg != AMD64_R11);
5680
5681         *displacement = disp;
5682         return regs [reg];
5683 }
5684
5685 gpointer*
5686 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5687 {
5688         gpointer vt;
5689         int displacement;
5690         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5691         if (!vt)
5692                 return NULL;
5693         return (gpointer*)((char*)vt + displacement);
5694 }
5695
5696 int
5697 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5698 {
5699         int this_reg = AMD64_ARG_REG1;
5700
5701         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5702                 CallInfo *cinfo;
5703
5704                 if (!gsctx && code)
5705                         gsctx = mono_get_generic_context_from_code (code);
5706
5707                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5708
5709                 if (cinfo->ret.storage != ArgValuetypeInReg)
5710                         this_reg = AMD64_ARG_REG2;
5711                 g_free (cinfo);
5712         }
5713
5714         return this_reg;
5715 }
5716
5717 gpointer
5718 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5719 {
5720         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
5721 }
5722
5723 #define MAX_ARCH_DELEGATE_PARAMS 10
5724
5725 gpointer
5726 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5727 {
5728         guint8 *code, *start;
5729         int i;
5730
5731         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5732                 return NULL;
5733
5734         /* FIXME: Support more cases */
5735         if (MONO_TYPE_ISSTRUCT (sig->ret))
5736                 return NULL;
5737
5738         if (has_target) {
5739                 static guint8* cached = NULL;
5740
5741                 if (cached)
5742                         return cached;
5743
5744                 start = code = mono_global_codeman_reserve (64);
5745
5746                 /* Replace the this argument with the target */
5747                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5748                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5749                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5750
5751                 g_assert ((code - start) < 64);
5752
5753                 mono_debug_add_delegate_trampoline (start, code - start);
5754
5755                 mono_memory_barrier ();
5756
5757                 cached = start;
5758         } else {
5759                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5760                 for (i = 0; i < sig->param_count; ++i)
5761                         if (!mono_is_regsize_var (sig->params [i]))
5762                                 return NULL;
5763                 if (sig->param_count > 4)
5764                         return NULL;
5765
5766                 code = cache [sig->param_count];
5767                 if (code)
5768                         return code;
5769
5770                 start = code = mono_global_codeman_reserve (64);
5771
5772                 if (sig->param_count == 0) {
5773                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5774                 } else {
5775                         /* We have to shift the arguments left */
5776                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5777                         for (i = 0; i < sig->param_count; ++i) {
5778 #ifdef PLATFORM_WIN32
5779                                 if (i < 3)
5780                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5781                                 else
5782                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
5783 #else
5784                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5785 #endif
5786                         }
5787
5788                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5789                 }
5790                 g_assert ((code - start) < 64);
5791
5792                 mono_debug_add_delegate_trampoline (start, code - start);
5793
5794                 mono_memory_barrier ();
5795
5796                 cache [sig->param_count] = start;
5797         }
5798
5799         return start;
5800 }
5801
5802 /*
5803  * Support for fast access to the thread-local lmf structure using the GS
5804  * segment register on NPTL + kernel 2.6.x.
5805  */
5806
5807 static gboolean tls_offset_inited = FALSE;
5808
5809 void
5810 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5811 {
5812         if (!tls_offset_inited) {
5813 #ifdef PLATFORM_WIN32
5814                 /*
5815                  * We need to init this multiple times, since when we are first called, the key might not
5816                  * be initialized yet.
5817                  */
5818                 appdomain_tls_offset = mono_domain_get_tls_key ();
5819                 lmf_tls_offset = mono_get_jit_tls_key ();
5820                 thread_tls_offset = mono_thread_get_tls_key ();
5821                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
5822
5823                 /* Only 64 tls entries can be accessed using inline code */
5824                 if (appdomain_tls_offset >= 64)
5825                         appdomain_tls_offset = -1;
5826                 if (lmf_tls_offset >= 64)
5827                         lmf_tls_offset = -1;
5828                 if (thread_tls_offset >= 64)
5829                         thread_tls_offset = -1;
5830 #else
5831                 tls_offset_inited = TRUE;
5832 #ifdef MONO_XEN_OPT
5833                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5834 #endif
5835                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5836                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5837                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5838                 thread_tls_offset = mono_thread_get_tls_offset ();
5839 #endif
5840         }
5841 }
5842
5843 void
5844 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5845 {
5846 }
5847
5848 #ifdef MONO_ARCH_HAVE_IMT
5849
5850 #define CMP_SIZE (6 + 1)
5851 #define CMP_REG_REG_SIZE (4 + 1)
5852 #define BR_SMALL_SIZE 2
5853 #define BR_LARGE_SIZE 6
5854 #define MOV_REG_IMM_SIZE 10
5855 #define MOV_REG_IMM_32BIT_SIZE 6
5856 #define JUMP_REG_SIZE (2 + 1)
5857
5858 static int
5859 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5860 {
5861         int i, distance = 0;
5862         for (i = start; i < target; ++i)
5863                 distance += imt_entries [i]->chunk_size;
5864         return distance;
5865 }
5866
5867 /*
5868  * LOCKING: called with the domain lock held
5869  */
5870 gpointer
5871 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5872         gpointer fail_tramp)
5873 {
5874         int i;
5875         int size = 0;
5876         guint8 *code, *start;
5877         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5878
5879         for (i = 0; i < count; ++i) {
5880                 MonoIMTCheckItem *item = imt_entries [i];
5881                 if (item->is_equals) {
5882                         if (item->check_target_idx) {
5883                                 if (!item->compare_done) {
5884                                         if (amd64_is_imm32 (item->key))
5885                                                 item->chunk_size += CMP_SIZE;
5886                                         else
5887                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5888                                 }
5889                                 if (item->has_target_code) {
5890                                         item->chunk_size += MOV_REG_IMM_SIZE;
5891                                 } else {
5892                                         if (vtable_is_32bit)
5893                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5894                                         else
5895                                                 item->chunk_size += MOV_REG_IMM_SIZE;
5896                                 }
5897                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5898                         } else {
5899                                 if (fail_tramp) {
5900                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
5901                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
5902                                 } else {
5903                                         if (vtable_is_32bit)
5904                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5905                                         else
5906                                                 item->chunk_size += MOV_REG_IMM_SIZE;
5907                                         item->chunk_size += JUMP_REG_SIZE;
5908                                         /* with assert below:
5909                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5910                                          */
5911                                 }
5912                         }
5913                 } else {
5914                         if (amd64_is_imm32 (item->key))
5915                                 item->chunk_size += CMP_SIZE;
5916                         else
5917                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5918                         item->chunk_size += BR_LARGE_SIZE;
5919                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5920                 }
5921                 size += item->chunk_size;
5922         }
5923         if (fail_tramp)
5924                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5925         else
5926                 code = mono_domain_code_reserve (domain, size);
5927         start = code;
5928         for (i = 0; i < count; ++i) {
5929                 MonoIMTCheckItem *item = imt_entries [i];
5930                 item->code_target = code;
5931                 if (item->is_equals) {
5932                         if (item->check_target_idx) {
5933                                 if (!item->compare_done) {
5934                                         if (amd64_is_imm32 (item->key))
5935                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5936                                         else {
5937                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5938                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5939                                         }
5940                                 }
5941                                 item->jmp_code = code;
5942                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5943                                 /* See the comment below about R10 */
5944                                 if (item->has_target_code) {
5945                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5946                                         amd64_jump_reg (code, AMD64_R10);
5947                                 } else {
5948                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5949                                         amd64_jump_membase (code, AMD64_R10, 0);
5950                                 }
5951                         } else {
5952                                 if (fail_tramp) {
5953                                         if (amd64_is_imm32 (item->key))
5954                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5955                                         else {
5956                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5957                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5958                                         }
5959                                         item->jmp_code = code;
5960                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5961                                         if (item->has_target_code) {
5962                                                 amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5963                                                 amd64_jump_reg (code, AMD64_R10);
5964                                         } else {
5965                                                 g_assert (vtable);
5966                                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5967                                                 amd64_jump_membase (code, AMD64_R10, 0);
5968                                         }
5969                                         amd64_patch (item->jmp_code, code);
5970                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
5971                                         amd64_jump_reg (code, AMD64_R10);
5972                                         item->jmp_code = NULL;
5973
5974                                 } else {
5975                                         /* enable the commented code to assert on wrong method */
5976 #if 0
5977                                         if (amd64_is_imm32 (item->key))
5978                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5979                                         else {
5980                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5981                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5982                                         }
5983                                         item->jmp_code = code;
5984                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5985                                         /* See the comment below about R10 */
5986                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5987                                         amd64_jump_membase (code, AMD64_R10, 0);
5988                                         amd64_patch (item->jmp_code, code);
5989                                         amd64_breakpoint (code);
5990                                         item->jmp_code = NULL;
5991 #else
5992                                         /* We're using R10 here because R11
5993                                            needs to be preserved.  R10 needs
5994                                            to be preserved for calls which
5995                                            require a runtime generic context,
5996                                            but interface calls don't. */
5997                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5998                                         amd64_jump_membase (code, AMD64_R10, 0);
5999 #endif
6000                                 }
6001                         }
6002                 } else {
6003                         if (amd64_is_imm32 (item->key))
6004                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6005                         else {
6006                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6007                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6008                         }
6009                         item->jmp_code = code;
6010                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6011                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6012                         else
6013                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6014                 }
6015                 g_assert (code - item->code_target <= item->chunk_size);
6016         }
6017         /* patch the branches to get to the target items */
6018         for (i = 0; i < count; ++i) {
6019                 MonoIMTCheckItem *item = imt_entries [i];
6020                 if (item->jmp_code) {
6021                         if (item->check_target_idx) {
6022                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6023                         }
6024                 }
6025         }
6026
6027         if (!fail_tramp)
6028                 mono_stats.imt_thunks_size += code - start;
6029         g_assert (code - start <= size);
6030
6031         return start;
6032 }
6033
6034 MonoMethod*
6035 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6036 {
6037         return regs [MONO_ARCH_IMT_REG];
6038 }
6039
6040 MonoObject*
6041 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6042 {
6043         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6044 }
6045
6046 void
6047 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6048 {
6049         /* Done by the implementation of the CALL_MEMBASE opcodes */
6050 }
6051 #endif
6052
6053 MonoVTable*
6054 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6055 {
6056         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6057 }
6058
6059 MonoInst*
6060 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6061 {
6062         MonoInst *ins = NULL;
6063         int opcode = 0;
6064
6065         if (cmethod->klass == mono_defaults.math_class) {
6066                 if (strcmp (cmethod->name, "Sin") == 0) {
6067                         opcode = OP_SIN;
6068                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6069                         opcode = OP_COS;
6070                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6071                         opcode = OP_SQRT;
6072                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6073                         opcode = OP_ABS;
6074                 }
6075
6076                 if (opcode) {
6077                         MONO_INST_NEW (cfg, ins, opcode);
6078                         ins->type = STACK_R8;
6079                         ins->dreg = mono_alloc_freg (cfg);
6080                         ins->sreg1 = args [0]->dreg;
6081                         MONO_ADD_INS (cfg->cbb, ins);
6082                 }
6083
6084                 opcode = 0;
6085                 if (cfg->opt & MONO_OPT_CMOV) {
6086                         if (strcmp (cmethod->name, "Min") == 0) {
6087                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6088                                         opcode = OP_IMIN;
6089                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6090                                         opcode = OP_IMIN_UN;
6091                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6092                                         opcode = OP_LMIN;
6093                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6094                                         opcode = OP_LMIN_UN;
6095                         } else if (strcmp (cmethod->name, "Max") == 0) {
6096                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6097                                         opcode = OP_IMAX;
6098                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6099                                         opcode = OP_IMAX_UN;
6100                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6101                                         opcode = OP_LMAX;
6102                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6103                                         opcode = OP_LMAX_UN;
6104                         }
6105                 }
6106
6107                 if (opcode) {
6108                         MONO_INST_NEW (cfg, ins, opcode);
6109                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6110                         ins->dreg = mono_alloc_ireg (cfg);
6111                         ins->sreg1 = args [0]->dreg;
6112                         ins->sreg2 = args [1]->dreg;
6113                         MONO_ADD_INS (cfg->cbb, ins);
6114                 }
6115
6116 #if 0
6117                 /* OP_FREM is not IEEE compatible */
6118                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6119                         MONO_INST_NEW (cfg, ins, OP_FREM);
6120                         ins->inst_i0 = args [0];
6121                         ins->inst_i1 = args [1];
6122                 }
6123 #endif
6124         }
6125
6126         /*
6127          * Can't implement CompareExchange methods this way since they have
6128          * three arguments.
6129          */
6130
6131         return ins;
6132 }
6133
6134 gboolean
6135 mono_arch_print_tree (MonoInst *tree, int arity)
6136 {
6137         return 0;
6138 }
6139
6140 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6141 {
6142         MonoInst* ins;
6143
6144         if (appdomain_tls_offset == -1)
6145                 return NULL;
6146
6147         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6148         ins->inst_offset = appdomain_tls_offset;
6149         return ins;
6150 }
6151
6152 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6153 {
6154         MonoInst* ins;
6155
6156         if (thread_tls_offset == -1)
6157                 return NULL;
6158
6159         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6160         ins->inst_offset = thread_tls_offset;
6161         return ins;
6162 }
6163
6164 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6165
6166 gpointer
6167 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6168 {
6169         switch (reg) {
6170         case AMD64_RCX: return (gpointer)ctx->rcx;
6171         case AMD64_RDX: return (gpointer)ctx->rdx;
6172         case AMD64_RBX: return (gpointer)ctx->rbx;
6173         case AMD64_RBP: return (gpointer)ctx->rbp;
6174         case AMD64_RSP: return (gpointer)ctx->rsp;
6175         default:
6176                 if (reg < 8)
6177                         return _CTX_REG (ctx, rax, reg);
6178                 else if (reg >= 12)
6179                         return _CTX_REG (ctx, r12, reg - 12);
6180                 else
6181                         g_assert_not_reached ();
6182         }
6183 }