mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 /* Offset between fp and the first argument in the callee */
  89 #define ARGS_OFFSET 16
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return mono_debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 #ifdef __native_client_codegen__
 182
 183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 184 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 186 /* We only want to force bundle alignment for the top level instruction,    */
 187 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 188 static MonoNativeTlsKey nacl_instruction_depth;
 189
 190 static MonoNativeTlsKey nacl_rex_tag;
 191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 192
 193 void
 194 amd64_nacl_clear_legacy_prefix_tag ()
 195 {
 196         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 197 }
 198
 199 void
 200 amd64_nacl_tag_legacy_prefix (guint8* code)
 201 {
 202         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 203                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 204 }
 205
 206 void
 207 amd64_nacl_tag_rex (guint8* code)
 208 {
 209         mono_native_tls_set_value (nacl_rex_tag, code);
 210 }
 211
 212 guint8*
 213 amd64_nacl_get_legacy_prefix_tag ()
 214 {
 215         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 216 }
 217
 218 guint8*
 219 amd64_nacl_get_rex_tag ()
 220 {
 221         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 222 }
 223
 224 /* Increment the instruction "depth" described above */
 225 void
 226 amd64_nacl_instruction_pre ()
 227 {
 228         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 229         depth++;
 230         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 231 }
 232
 233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 234 /* alignment if depth == 0 (top level instruction)                          */
 235 /* IN: start, end    pointers to instruction beginning and end              */
 236 /* OUT: start, end   pointers to beginning and end after possible alignment */
 237 /* GLOBALS: nacl_instruction_depth     defined above                        */
 238 void
 239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth--;
 243         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 244
 245         g_assert ( depth >= 0 );
 246         if (depth == 0) {
 247                 uintptr_t space_in_block;
 248                 uintptr_t instlen;
 249                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 250                 /* if legacy prefix is present, and if it was emitted before */
 251                 /* the start of the instruction sequence, adjust the start   */
 252                 if (prefix != NULL && prefix < *start) {
 253                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 254                         *start = prefix;
 255                 }
 256                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 257                 instlen = (uintptr_t)(*end - *start);
 258                 /* Only check for instructions which are less than        */
 259                 /* kNaClAlignment. The only instructions that should ever */
 260                 /* be that long are call sequences, which are already     */
 261                 /* padded out to align the return to the next bundle.     */
 262                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 263                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 264                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 265                         const size_t length = (size_t)((*end)-(*start));
 266                         g_assert (length < MAX_NACL_INST_LENGTH);
 267
 268                         memcpy (copy_of_instruction, *start, length);
 269                         *start = mono_arch_nacl_pad (*start, space_in_block);
 270                         memcpy (*start, copy_of_instruction, length);
 271                         *end = *start + length;
 272                 }
 273                 amd64_nacl_clear_legacy_prefix_tag ();
 274                 amd64_nacl_tag_rex (NULL);
 275         }
 276 }
 277
 278 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 279 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 280 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 281 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 282 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 283 /* IN:      code                                                            */
 284 /*             pointer to current instruction stream (in the                */
 285 /*             middle of an instruction, after opcode is emitted)           */
 286 /*          basereg/offset/dreg                                             */
 287 /*             operands of normal membase address                           */
 288 /* OUT:     code                                                            */
 289 /*             pointer to the end of the membase/memindex emit              */
 290 /* GLOBALS: nacl_rex_tag                                                    */
 291 /*             position in instruction stream that rex prefix was emitted   */
 292 /*          nacl_legacy_prefix_tag                                          */
 293 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 294 void
 295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 296 {
 297         gint8 true_basereg = basereg;
 298
 299         /* Cache these values, they might change  */
 300         /* as new instructions are emitted below. */
 301         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 302         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 303
 304         /* 'basereg' is given masked to 0x7 at this point, so check */
 305         /* the rex prefix to see if this is an extended register.   */
 306         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 307                 true_basereg |= 0x8;
 308         }
 309
 310 #define X86_LEA_OPCODE (0x8D)
 311
 312         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 313                 guint8* old_instruction_start;
 314
 315                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 316                 /* 32-bits of the old base register (new index register)     */
 317                 guint8 buf[32];
 318                 guint8* buf_ptr = buf;
 319                 size_t insert_len;
 320
 321                 g_assert (rex_tag != NULL);
 322
 323                 if (IS_REX(*rex_tag)) {
 324                         /* The old rex.B should be the new rex.X */
 325                         if (*rex_tag & AMD64_REX_B) {
 326                                 *rex_tag |= AMD64_REX_X;
 327                         }
 328                         /* Since our new base is %r15 set rex.B */
 329                         *rex_tag |= AMD64_REX_B;
 330                 } else {
 331                         /* Shift the instruction by one byte  */
 332                         /* so we can insert a rex prefix      */
 333                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 334                         *code += 1;
 335                         /* New rex prefix only needs rex.B for %r15 base */
 336                         *rex_tag = AMD64_REX(AMD64_REX_B);
 337                 }
 338
 339                 if (legacy_prefix_tag) {
 340                         old_instruction_start = legacy_prefix_tag;
 341                 } else {
 342                         old_instruction_start = rex_tag;
 343                 }
 344
 345                 /* Clears the upper 32-bits of the previous base register */
 346                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 347                 insert_len = buf_ptr - buf;
 348
 349                 /* Move the old instruction forward to make */
 350                 /* room for 'mov' stored in 'buf_ptr'       */
 351                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 352                 *code += insert_len;
 353                 memcpy (old_instruction_start, buf, insert_len);
 354
 355                 /* Sandboxed replacement for the normal membase_emit */
 356                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 357
 358         } else {
 359                 /* Normal default behavior, emit membase memory location */
 360                 x86_membase_emit_body (*code, dreg, basereg, offset);
 361         }
 362 }
 363
 364
 365 static inline unsigned char*
 366 amd64_skip_nops (unsigned char* code)
 367 {
 368         guint8 in_nop;
 369         do {
 370                 in_nop = 0;
 371                 if (   code[0] == 0x90) {
 372                         in_nop = 1;
 373                         code += 1;
 374                 }
 375                 if (   code[0] == 0x66 && code[1] == 0x90) {
 376                         in_nop = 1;
 377                         code += 2;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x00) {
 381                         in_nop = 1;
 382                         code += 3;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x40 && code[3] == 0x00) {
 386                         in_nop = 1;
 387                         code += 4;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x44 && code[3] == 0x00
 391                  && code[4] == 0x00) {
 392                         in_nop = 1;
 393                         code += 5;
 394                 }
 395                 if (code[0] == 0x66 && code[1] == 0x0f
 396                  && code[2] == 0x1f && code[3] == 0x44
 397                  && code[4] == 0x00 && code[5] == 0x00) {
 398                         in_nop = 1;
 399                         code += 6;
 400                 }
 401                 if (code[0] == 0x0f && code[1] == 0x1f
 402                  && code[2] == 0x80 && code[3] == 0x00
 403                  && code[4] == 0x00 && code[5] == 0x00
 404                  && code[6] == 0x00) {
 405                         in_nop = 1;
 406                         code += 7;
 407                 }
 408                 if (code[0] == 0x0f && code[1] == 0x1f
 409                  && code[2] == 0x84 && code[3] == 0x00
 410                  && code[4] == 0x00 && code[5] == 0x00
 411                  && code[6] == 0x00 && code[7] == 0x00) {
 412                         in_nop = 1;
 413                         code += 8;
 414                 }
 415         } while ( in_nop );
 416         return code;
 417 }
 418
 419 guint8*
 420 mono_arch_nacl_skip_nops (guint8* code)
 421 {
 422   return amd64_skip_nops(code);
 423 }
 424
 425 #endif /*__native_client_codegen__*/
 426
 427 static inline void
 428 amd64_patch (unsigned char* code, gpointer target)
 429 {
 430         guint8 rex = 0;
 431
 432 #ifdef __native_client_codegen__
 433         code = amd64_skip_nops (code);
 434 #endif
 435 #if defined(__native_client_codegen__) && defined(__native_client__)
 436         if (nacl_is_code_address (code)) {
 437                 /* For tail calls, code is patched after being installed */
 438                 /* but not through the normal "patch callsite" method.   */
 439                 unsigned char buf[kNaClAlignment];
 440                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 441                 int ret;
 442                 memcpy (buf, aligned_code, kNaClAlignment);
 443                 /* Patch a temp buffer of bundle size, */
 444                 /* then install to actual location.    */
 445                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 446                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 447                 g_assert (ret == 0);
 448                 return;
 449         }
 450         target = nacl_modify_patch_target (target);
 451 #endif
 452
 453         /* Skip REX */
 454         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 455                 rex = code [0];
 456                 code += 1;
 457         }
 458
 459         if ((code [0] & 0xf8) == 0xb8) {
 460                 /* amd64_set_reg_template */
 461                 *(guint64*)(code + 1) = (guint64)target;
 462         }
 463         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 464                 /* mov 0(%rip), %dreg */
 465                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 466         }
 467         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 468                 /* call *<OFFSET>(%rip) */
 469                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 470         }
 471         else if (code [0] == 0xe8) {
 472                 /* call <DISP> */
 473                 gint64 disp = (guint8*)target - (guint8*)code;
 474                 g_assert (amd64_is_imm32 (disp));
 475                 x86_patch (code, (unsigned char*)target);
 476         }
 477         else
 478                 x86_patch (code, (unsigned char*)target);
 479 }
 480
 481 void
 482 mono_amd64_patch (unsigned char* code, gpointer target)
 483 {
 484         amd64_patch (code, target);
 485 }
 486
 487 typedef enum {
 488         ArgInIReg,
 489         ArgInFloatSSEReg,
 490         ArgInDoubleSSEReg,
 491         ArgOnStack,
 492         ArgValuetypeInReg,
 493         ArgValuetypeAddrInIReg,
 494         ArgNone /* only in pair_storage */
 495 } ArgStorage;
 496
 497 typedef struct {
 498         gint16 offset;
 499         gint8  reg;
 500         ArgStorage storage;
 501
 502         /* Only if storage == ArgValuetypeInReg */
 503         ArgStorage pair_storage [2];
 504         gint8 pair_regs [2];
 505         /* The size of each pair */
 506         int pair_size [2];
 507         int nregs;
 508 } ArgInfo;
 509
 510 typedef struct {
 511         int nargs;
 512         guint32 stack_usage;
 513         guint32 reg_usage;
 514         guint32 freg_usage;
 515         gboolean need_stack_align;
 516         gboolean vtype_retaddr;
 517         /* The index of the vret arg in the argument list */
 518         int vret_arg_index;
 519         ArgInfo ret;
 520         ArgInfo sig_cookie;
 521         ArgInfo args [1];
 522 } CallInfo;
 523
 524 #define DEBUG(a) if (cfg->verbose_level > 1) a
 525
 526 #ifdef HOST_WIN32
 527 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 528
 529 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 530 #else
 531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 532
 533  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #endif
 535
 536 static void inline
 537 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 538 {
 539     ainfo->offset = *stack_size;
 540
 541     if (*gr >= PARAM_REGS) {
 542                 ainfo->storage = ArgOnStack;
 543                 /* Since the same stack slot size is used for all arg */
 544                 /*  types, it needs to be big enough to hold them all */
 545                 (*stack_size) += sizeof(mgreg_t);
 546     }
 547     else {
 548                 ainfo->storage = ArgInIReg;
 549                 ainfo->reg = param_regs [*gr];
 550                 (*gr) ++;
 551     }
 552 }
 553
 554 #ifdef HOST_WIN32
 555 #define FLOAT_PARAM_REGS 4
 556 #else
 557 #define FLOAT_PARAM_REGS 8
 558 #endif
 559
 560 static void inline
 561 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 562 {
 563     ainfo->offset = *stack_size;
 564
 565     if (*gr >= FLOAT_PARAM_REGS) {
 566                 ainfo->storage = ArgOnStack;
 567                 /* Since the same stack slot size is used for both float */
 568                 /*  types, it needs to be big enough to hold them both */
 569                 (*stack_size) += sizeof(mgreg_t);
 570     }
 571     else {
 572                 /* A double register */
 573                 if (is_double)
 574                         ainfo->storage = ArgInDoubleSSEReg;
 575                 else
 576                         ainfo->storage = ArgInFloatSSEReg;
 577                 ainfo->reg = *gr;
 578                 (*gr) += 1;
 579     }
 580 }
 581
 582 typedef enum ArgumentClass {
 583         ARG_CLASS_NO_CLASS,
 584         ARG_CLASS_MEMORY,
 585         ARG_CLASS_INTEGER,
 586         ARG_CLASS_SSE
 587 } ArgumentClass;
 588
 589 static ArgumentClass
 590 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 591 {
 592         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 593         MonoType *ptype;
 594
 595         ptype = mini_type_get_underlying_type (gsctx, type);
 596         switch (ptype->type) {
 597         case MONO_TYPE_BOOLEAN:
 598         case MONO_TYPE_CHAR:
 599         case MONO_TYPE_I1:
 600         case MONO_TYPE_U1:
 601         case MONO_TYPE_I2:
 602         case MONO_TYPE_U2:
 603         case MONO_TYPE_I4:
 604         case MONO_TYPE_U4:
 605         case MONO_TYPE_I:
 606         case MONO_TYPE_U:
 607         case MONO_TYPE_STRING:
 608         case MONO_TYPE_OBJECT:
 609         case MONO_TYPE_CLASS:
 610         case MONO_TYPE_SZARRAY:
 611         case MONO_TYPE_PTR:
 612         case MONO_TYPE_FNPTR:
 613         case MONO_TYPE_ARRAY:
 614         case MONO_TYPE_I8:
 615         case MONO_TYPE_U8:
 616                 class2 = ARG_CLASS_INTEGER;
 617                 break;
 618         case MONO_TYPE_R4:
 619         case MONO_TYPE_R8:
 620 #ifdef HOST_WIN32
 621                 class2 = ARG_CLASS_INTEGER;
 622 #else
 623                 class2 = ARG_CLASS_SSE;
 624 #endif
 625                 break;
 626
 627         case MONO_TYPE_TYPEDBYREF:
 628                 g_assert_not_reached ();
 629
 630         case MONO_TYPE_GENERICINST:
 631                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 632                         class2 = ARG_CLASS_INTEGER;
 633                         break;
 634                 }
 635                 /* fall through */
 636         case MONO_TYPE_VALUETYPE: {
 637                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 638                 int i;
 639
 640                 for (i = 0; i < info->num_fields; ++i) {
 641                         class2 = class1;
 642                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 643                 }
 644                 break;
 645         }
 646         default:
 647                 g_assert_not_reached ();
 648         }
 649
 650         /* Merge */
 651         if (class1 == class2)
 652                 ;
 653         else if (class1 == ARG_CLASS_NO_CLASS)
 654                 class1 = class2;
 655         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 656                 class1 = ARG_CLASS_MEMORY;
 657         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 658                 class1 = ARG_CLASS_INTEGER;
 659         else
 660                 class1 = ARG_CLASS_SSE;
 661
 662         return class1;
 663 }
 664 #ifdef __native_client_codegen__
 665
 666 /* Default alignment for Native Client is 32-byte. */
 667 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 668
 669 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 670 /* Check that alignment doesn't cross an alignment boundary.             */
 671 guint8*
 672 mono_arch_nacl_pad(guint8 *code, int pad)
 673 {
 674         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 675
 676         if (pad == 0) return code;
 677         /* assertion: alignment cannot cross a block boundary */
 678         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 679                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 680         while (pad >= kMaxPadding) {
 681                 amd64_padding (code, kMaxPadding);
 682                 pad -= kMaxPadding;
 683         }
 684         if (pad != 0) amd64_padding (code, pad);
 685         return code;
 686 }
 687 #endif
 688
 689 static int
 690 count_fields_nested (MonoClass *klass)
 691 {
 692         MonoMarshalType *info;
 693         int i, count;
 694
 695         info = mono_marshal_load_type_info (klass);
 696         g_assert(info);
 697         count = 0;
 698         for (i = 0; i < info->num_fields; ++i) {
 699                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 700                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 701                 else
 702                         count ++;
 703         }
 704         return count;
 705 }
 706
 707 static int
 708 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 709 {
 710         MonoMarshalType *info;
 711         int i;
 712
 713         info = mono_marshal_load_type_info (klass);
 714         g_assert(info);
 715         for (i = 0; i < info->num_fields; ++i) {
 716                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 717                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 718                 } else {
 719                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 720                         fields [index].offset += offset;
 721                         index ++;
 722                 }
 723         }
 724         return index;
 725 }
 726
 727 static void
 728 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 729                            gboolean is_return,
 730                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 731 {
 732         guint32 size, quad, nquads, i, nfields;
 733         /* Keep track of the size used in each quad so we can */
 734         /* use the right size when copying args/return vars.  */
 735         guint32 quadsize [2] = {8, 8};
 736         ArgumentClass args [2];
 737         MonoMarshalType *info = NULL;
 738         MonoMarshalField *fields = NULL;
 739         MonoClass *klass;
 740         MonoGenericSharingContext tmp_gsctx;
 741         gboolean pass_on_stack = FALSE;
 742
 743         /*
 744          * The gsctx currently contains no data, it is only used for checking whenever
 745          * open types are allowed, some callers like mono_arch_get_argument_info ()
 746          * don't pass it to us, so work around that.
 747          */
 748         if (!gsctx)
 749                 gsctx = &tmp_gsctx;
 750
 751         klass = mono_class_from_mono_type (type);
 752         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 753 #ifndef HOST_WIN32
 754         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 755                 /* We pass and return vtypes of size 8 in a register */
 756         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 757                 pass_on_stack = TRUE;
 758         }
 759 #else
 760         if (!sig->pinvoke) {
 761                 pass_on_stack = TRUE;
 762         }
 763 #endif
 764
 765         /* If this struct can't be split up naturally into 8-byte */
 766         /* chunks (registers), pass it on the stack.              */
 767         if (sig->pinvoke && !pass_on_stack) {
 768                 guint32 align;
 769                 guint32 field_size;
 770
 771                 info = mono_marshal_load_type_info (klass);
 772                 g_assert (info);
 773
 774                 /*
 775                  * Collect field information recursively to be able to
 776                  * handle nested structures.
 777                  */
 778                 nfields = count_fields_nested (klass);
 779                 fields = g_new0 (MonoMarshalField, nfields);
 780                 collect_field_info_nested (klass, fields, 0, 0);
 781
 782                 for (i = 0; i < nfields; ++i) {
 783                         field_size = mono_marshal_type_size (fields [i].field->type,
 784                                                            fields [i].mspec,
 785                                                            &align, TRUE, klass->unicode);
 786                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 787                                 pass_on_stack = TRUE;
 788                                 break;
 789                         }
 790                 }
 791         }
 792
 793         if (pass_on_stack) {
 794                 /* Allways pass in memory */
 795                 ainfo->offset = *stack_size;
 796                 *stack_size += ALIGN_TO (size, 8);
 797                 ainfo->storage = ArgOnStack;
 798
 799                 g_free (fields);
 800                 return;
 801         }
 802
 803         /* FIXME: Handle structs smaller than 8 bytes */
 804         //if ((size % 8) != 0)
 805         //      NOT_IMPLEMENTED;
 806
 807         if (size > 8)
 808                 nquads = 2;
 809         else
 810                 nquads = 1;
 811
 812         if (!sig->pinvoke) {
 813                 int n = mono_class_value_size (klass, NULL);
 814
 815                 quadsize [0] = n >= 8 ? 8 : n;
 816                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 817
 818                 /* Always pass in 1 or 2 integer registers */
 819                 args [0] = ARG_CLASS_INTEGER;
 820                 args [1] = ARG_CLASS_INTEGER;
 821                 /* Only the simplest cases are supported */
 822                 if (is_return && nquads != 1) {
 823                         args [0] = ARG_CLASS_MEMORY;
 824                         args [1] = ARG_CLASS_MEMORY;
 825                 }
 826         } else {
 827                 /*
 828                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 829                  * The X87 and SSEUP stuff is left out since there are no such types in
 830                  * the CLR.
 831                  */
 832                 g_assert (info);
 833                 g_assert (fields);
 834
 835 #ifndef HOST_WIN32
 836                 if (info->native_size > 16) {
 837                         ainfo->offset = *stack_size;
 838                         *stack_size += ALIGN_TO (info->native_size, 8);
 839                         ainfo->storage = ArgOnStack;
 840
 841                         g_free (fields);
 842                         return;
 843                 }
 844 #else
 845                 switch (info->native_size) {
 846                 case 1: case 2: case 4: case 8:
 847                         break;
 848                 default:
 849                         if (is_return) {
 850                                 ainfo->storage = ArgOnStack;
 851                                 ainfo->offset = *stack_size;
 852                                 *stack_size += ALIGN_TO (info->native_size, 8);
 853                         }
 854                         else {
 855                                 ainfo->storage = ArgValuetypeAddrInIReg;
 856
 857                                 if (*gr < PARAM_REGS) {
 858                                         ainfo->pair_storage [0] = ArgInIReg;
 859                                         ainfo->pair_regs [0] = param_regs [*gr];
 860                                         (*gr) ++;
 861                                 }
 862                                 else {
 863                                         ainfo->pair_storage [0] = ArgOnStack;
 864                                         ainfo->offset = *stack_size;
 865                                         *stack_size += 8;
 866                                 }
 867                         }
 868
 869                         g_free (fields);
 870                         return;
 871                 }
 872 #endif
 873
 874                 args [0] = ARG_CLASS_NO_CLASS;
 875                 args [1] = ARG_CLASS_NO_CLASS;
 876                 for (quad = 0; quad < nquads; ++quad) {
 877                         int size;
 878                         guint32 align;
 879                         ArgumentClass class1;
 880
 881                         if (nfields == 0)
 882                                 class1 = ARG_CLASS_MEMORY;
 883                         else
 884                                 class1 = ARG_CLASS_NO_CLASS;
 885                         for (i = 0; i < nfields; ++i) {
 886                                 size = mono_marshal_type_size (fields [i].field->type,
 887                                                                                            fields [i].mspec,
 888                                                                                            &align, TRUE, klass->unicode);
 889                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 890                                         /* Unaligned field */
 891                                         NOT_IMPLEMENTED;
 892                                 }
 893
 894                                 /* Skip fields in other quad */
 895                                 if ((quad == 0) && (fields [i].offset >= 8))
 896                                         continue;
 897                                 if ((quad == 1) && (fields [i].offset < 8))
 898                                         continue;
 899
 900                                 /* How far into this quad this data extends.*/
 901                                 /* (8 is size of quad) */
 902                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 903
 904                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 905                         }
 906                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 907                         args [quad] = class1;
 908                 }
 909         }
 910
 911         g_free (fields);
 912
 913         /* Post merger cleanup */
 914         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 915                 args [0] = args [1] = ARG_CLASS_MEMORY;
 916
 917         /* Allocate registers */
 918         {
 919                 int orig_gr = *gr;
 920                 int orig_fr = *fr;
 921
 922                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 923                         quadsize [0] ++;
 924                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 925                         quadsize [1] ++;
 926
 927                 ainfo->storage = ArgValuetypeInReg;
 928                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 929                 g_assert (quadsize [0] <= 8);
 930                 g_assert (quadsize [1] <= 8);
 931                 ainfo->pair_size [0] = quadsize [0];
 932                 ainfo->pair_size [1] = quadsize [1];
 933                 ainfo->nregs = nquads;
 934                 for (quad = 0; quad < nquads; ++quad) {
 935                         switch (args [quad]) {
 936                         case ARG_CLASS_INTEGER:
 937                                 if (*gr >= PARAM_REGS)
 938                                         args [quad] = ARG_CLASS_MEMORY;
 939                                 else {
 940                                         ainfo->pair_storage [quad] = ArgInIReg;
 941                                         if (is_return)
 942                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 943                                         else
 944                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 945                                         (*gr) ++;
 946                                 }
 947                                 break;
 948                         case ARG_CLASS_SSE:
 949                                 if (*fr >= FLOAT_PARAM_REGS)
 950                                         args [quad] = ARG_CLASS_MEMORY;
 951                                 else {
 952                                         if (quadsize[quad] <= 4)
 953                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 954                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 955                                         ainfo->pair_regs [quad] = *fr;
 956                                         (*fr) ++;
 957                                 }
 958                                 break;
 959                         case ARG_CLASS_MEMORY:
 960                                 break;
 961                         default:
 962                                 g_assert_not_reached ();
 963                         }
 964                 }
 965
 966                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 967                         /* Revert possible register assignments */
 968                         *gr = orig_gr;
 969                         *fr = orig_fr;
 970
 971                         ainfo->offset = *stack_size;
 972                         if (sig->pinvoke)
 973                                 *stack_size += ALIGN_TO (info->native_size, 8);
 974                         else
 975                                 *stack_size += nquads * sizeof(mgreg_t);
 976                         ainfo->storage = ArgOnStack;
 977                 }
 978         }
 979 }
 980
 981 /*
 982  * get_call_info:
 983  *
 984  *  Obtain information about a call according to the calling convention.
 985  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 986  * Draft Version 0.23" document for more information.
 987  */
 988 static CallInfo*
 989 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 990 {
 991         guint32 i, gr, fr, pstart;
 992         MonoType *ret_type;
 993         int n = sig->hasthis + sig->param_count;
 994         guint32 stack_size = 0;
 995         CallInfo *cinfo;
 996         gboolean is_pinvoke = sig->pinvoke;
 997
 998         if (mp)
 999                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1000         else
1001                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002
1003         cinfo->nargs = n;
1004
1005         gr = 0;
1006         fr = 0;
1007
1008 #ifdef HOST_WIN32
1009         /* Reserve space where the callee can save the argument registers */
1010         stack_size = 4 * sizeof (mgreg_t);
1011 #endif
1012
1013         /* return value */
1014         {
1015                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1016                 switch (ret_type->type) {
1017                 case MONO_TYPE_BOOLEAN:
1018                 case MONO_TYPE_I1:
1019                 case MONO_TYPE_U1:
1020                 case MONO_TYPE_I2:
1021                 case MONO_TYPE_U2:
1022                 case MONO_TYPE_CHAR:
1023                 case MONO_TYPE_I4:
1024                 case MONO_TYPE_U4:
1025                 case MONO_TYPE_I:
1026                 case MONO_TYPE_U:
1027                 case MONO_TYPE_PTR:
1028                 case MONO_TYPE_FNPTR:
1029                 case MONO_TYPE_CLASS:
1030                 case MONO_TYPE_OBJECT:
1031                 case MONO_TYPE_SZARRAY:
1032                 case MONO_TYPE_ARRAY:
1033                 case MONO_TYPE_STRING:
1034                         cinfo->ret.storage = ArgInIReg;
1035                         cinfo->ret.reg = AMD64_RAX;
1036                         break;
1037                 case MONO_TYPE_U8:
1038                 case MONO_TYPE_I8:
1039                         cinfo->ret.storage = ArgInIReg;
1040                         cinfo->ret.reg = AMD64_RAX;
1041                         break;
1042                 case MONO_TYPE_R4:
1043                         cinfo->ret.storage = ArgInFloatSSEReg;
1044                         cinfo->ret.reg = AMD64_XMM0;
1045                         break;
1046                 case MONO_TYPE_R8:
1047                         cinfo->ret.storage = ArgInDoubleSSEReg;
1048                         cinfo->ret.reg = AMD64_XMM0;
1049                         break;
1050                 case MONO_TYPE_GENERICINST:
1051                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1052                                 cinfo->ret.storage = ArgInIReg;
1053                                 cinfo->ret.reg = AMD64_RAX;
1054                                 break;
1055                         }
1056                         /* fall through */
1057 #if defined( __native_client_codegen__ )
1058                 case MONO_TYPE_TYPEDBYREF:
1059 #endif
1060                 case MONO_TYPE_VALUETYPE: {
1061                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1062
1063                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1064                         if (cinfo->ret.storage == ArgOnStack) {
1065                                 cinfo->vtype_retaddr = TRUE;
1066                                 /* The caller passes the address where the value is stored */
1067                         }
1068                         break;
1069                 }
1070 #if !defined( __native_client_codegen__ )
1071                 case MONO_TYPE_TYPEDBYREF:
1072                         /* Same as a valuetype with size 24 */
1073                         cinfo->vtype_retaddr = TRUE;
1074                         break;
1075 #endif
1076                 case MONO_TYPE_VOID:
1077                         break;
1078                 default:
1079                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1080                 }
1081         }
1082
1083         pstart = 0;
1084         /*
1085          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1086          * the first argument, allowing 'this' to be always passed in the first arg reg.
1087          * Also do this if the first argument is a reference type, since virtual calls
1088          * are sometimes made using calli without sig->hasthis set, like in the delegate
1089          * invoke wrappers.
1090          */
1091         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1092                 if (sig->hasthis) {
1093                         add_general (&gr, &stack_size, cinfo->args + 0);
1094                 } else {
1095                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1096                         pstart = 1;
1097                 }
1098                 add_general (&gr, &stack_size, &cinfo->ret);
1099                 cinfo->vret_arg_index = 1;
1100         } else {
1101                 /* this */
1102                 if (sig->hasthis)
1103                         add_general (&gr, &stack_size, cinfo->args + 0);
1104
1105                 if (cinfo->vtype_retaddr)
1106                         add_general (&gr, &stack_size, &cinfo->ret);
1107         }
1108
1109         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1110                 gr = PARAM_REGS;
1111                 fr = FLOAT_PARAM_REGS;
1112
1113                 /* Emit the signature cookie just before the implicit arguments */
1114                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1115         }
1116
1117         for (i = pstart; i < sig->param_count; ++i) {
1118                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1119                 MonoType *ptype;
1120
1121 #ifdef HOST_WIN32
1122                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1123                 if (gr > fr)
1124                         fr = gr;
1125                 else if (fr > gr)
1126                         gr = fr;
1127 #endif
1128
1129                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1130                         /* We allways pass the sig cookie on the stack for simplicity */
1131                         /*
1132                          * Prevent implicit arguments + the sig cookie from being passed
1133                          * in registers.
1134                          */
1135                         gr = PARAM_REGS;
1136                         fr = FLOAT_PARAM_REGS;
1137
1138                         /* Emit the signature cookie just before the implicit arguments */
1139                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1140                 }
1141
1142                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1143                 switch (ptype->type) {
1144                 case MONO_TYPE_BOOLEAN:
1145                 case MONO_TYPE_I1:
1146                 case MONO_TYPE_U1:
1147                         add_general (&gr, &stack_size, ainfo);
1148                         break;
1149                 case MONO_TYPE_I2:
1150                 case MONO_TYPE_U2:
1151                 case MONO_TYPE_CHAR:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I4:
1155                 case MONO_TYPE_U4:
1156                         add_general (&gr, &stack_size, ainfo);
1157                         break;
1158                 case MONO_TYPE_I:
1159                 case MONO_TYPE_U:
1160                 case MONO_TYPE_PTR:
1161                 case MONO_TYPE_FNPTR:
1162                 case MONO_TYPE_CLASS:
1163                 case MONO_TYPE_OBJECT:
1164                 case MONO_TYPE_STRING:
1165                 case MONO_TYPE_SZARRAY:
1166                 case MONO_TYPE_ARRAY:
1167                         add_general (&gr, &stack_size, ainfo);
1168                         break;
1169                 case MONO_TYPE_GENERICINST:
1170                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1171                                 add_general (&gr, &stack_size, ainfo);
1172                                 break;
1173                         }
1174                         /* fall through */
1175                 case MONO_TYPE_VALUETYPE:
1176                 case MONO_TYPE_TYPEDBYREF:
1177                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1178                         break;
1179                 case MONO_TYPE_U8:
1180
1181                 case MONO_TYPE_I8:
1182                         add_general (&gr, &stack_size, ainfo);
1183                         break;
1184                 case MONO_TYPE_R4:
1185                         add_float (&fr, &stack_size, ainfo, FALSE);
1186                         break;
1187                 case MONO_TYPE_R8:
1188                         add_float (&fr, &stack_size, ainfo, TRUE);
1189                         break;
1190                 default:
1191                         g_assert_not_reached ();
1192                 }
1193         }
1194
1195         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1196                 gr = PARAM_REGS;
1197                 fr = FLOAT_PARAM_REGS;
1198
1199                 /* Emit the signature cookie just before the implicit arguments */
1200                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1201         }
1202
1203         cinfo->stack_usage = stack_size;
1204         cinfo->reg_usage = gr;
1205         cinfo->freg_usage = fr;
1206         return cinfo;
1207 }
1208
1209 /*
1210  * mono_arch_get_argument_info:
1211  * @csig:  a method signature
1212  * @param_count: the number of parameters to consider
1213  * @arg_info: an array to store the result infos
1214  *
1215  * Gathers information on parameters such as size, alignment and
1216  * padding. arg_info should be large enought to hold param_count + 1 entries.
1217  *
1218  * Returns the size of the argument area on the stack.
1219  */
1220 int
1221 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1222 {
1223         int k;
1224         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1225         guint32 args_size = cinfo->stack_usage;
1226
1227         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1228         if (csig->hasthis) {
1229                 arg_info [0].offset = 0;
1230         }
1231
1232         for (k = 0; k < param_count; k++) {
1233                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1234                 /* FIXME: */
1235                 arg_info [k + 1].size = 0;
1236         }
1237
1238         g_free (cinfo);
1239
1240         return args_size;
1241 }
1242
1243 gboolean
1244 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1245 {
1246         CallInfo *c1, *c2;
1247         gboolean res;
1248         MonoType *callee_ret;
1249
1250         c1 = get_call_info (NULL, NULL, caller_sig);
1251         c2 = get_call_info (NULL, NULL, callee_sig);
1252         res = c1->stack_usage >= c2->stack_usage;
1253         callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1254         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1255                 /* An address on the callee's stack is passed as the first argument */
1256                 res = FALSE;
1257
1258         g_free (c1);
1259         g_free (c2);
1260
1261         return res;
1262 }
1263
1264 /*
1265  * Initialize the cpu to execute managed code.
1266  */
1267 void
1268 mono_arch_cpu_init (void)
1269 {
1270 #ifndef _MSC_VER
1271         guint16 fpcw;
1272
1273         /* spec compliance requires running with double precision */
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275         fpcw &= ~X86_FPCW_PRECC_MASK;
1276         fpcw |= X86_FPCW_PREC_DOUBLE;
1277         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1278         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1279 #else
1280         /* TODO: This is crashing on Win64 right now.
1281         * _control87 (_PC_53, MCW_PC);
1282         */
1283 #endif
1284 }
1285
1286 /*
1287  * Initialize architecture specific code.
1288  */
1289 void
1290 mono_arch_init (void)
1291 {
1292         int flags;
1293
1294         mono_mutex_init_recursive (&mini_arch_mutex);
1295 #if defined(__native_client_codegen__)
1296         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1297         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1298         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1299         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1300 #endif
1301
1302 #ifdef MONO_ARCH_NOMAP32BIT
1303         flags = MONO_MMAP_READ;
1304         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1305         breakpoint_size = 13;
1306         breakpoint_fault_size = 3;
1307 #else
1308         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1309         /* amd64_mov_reg_mem () */
1310         breakpoint_size = 8;
1311         breakpoint_fault_size = 8;
1312 #endif
1313
1314         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1315         single_step_fault_size = 4;
1316
1317         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1318         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1319         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1320
1321         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1322         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1323         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1324 }
1325
1326 /*
1327  * Cleanup architecture specific code.
1328  */
1329 void
1330 mono_arch_cleanup (void)
1331 {
1332         mono_mutex_destroy (&mini_arch_mutex);
1333 #if defined(__native_client_codegen__)
1334         mono_native_tls_free (nacl_instruction_depth);
1335         mono_native_tls_free (nacl_rex_tag);
1336         mono_native_tls_free (nacl_legacy_prefix_tag);
1337 #endif
1338 }
1339
1340 /*
1341  * This function returns the optimizations supported on this cpu.
1342  */
1343 guint32
1344 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1345 {
1346         guint32 opts = 0;
1347
1348         *exclude_mask = 0;
1349
1350         if (mono_hwcap_x86_has_cmov) {
1351                 opts |= MONO_OPT_CMOV;
1352
1353                 if (mono_hwcap_x86_has_fcmov)
1354                         opts |= MONO_OPT_FCMOV;
1355                 else
1356                         *exclude_mask |= MONO_OPT_FCMOV;
1357         } else {
1358                 *exclude_mask |= MONO_OPT_CMOV;
1359         }
1360
1361         return opts;
1362 }
1363
1364 /*
1365  * This function test for all SSE functions supported.
1366  *
1367  * Returns a bitmask corresponding to all supported versions.
1368  *
1369  */
1370 guint32
1371 mono_arch_cpu_enumerate_simd_versions (void)
1372 {
1373         guint32 sse_opts = 0;
1374
1375         if (mono_hwcap_x86_has_sse1)
1376                 sse_opts |= SIMD_VERSION_SSE1;
1377
1378         if (mono_hwcap_x86_has_sse2)
1379                 sse_opts |= SIMD_VERSION_SSE2;
1380
1381         if (mono_hwcap_x86_has_sse3)
1382                 sse_opts |= SIMD_VERSION_SSE3;
1383
1384         if (mono_hwcap_x86_has_ssse3)
1385                 sse_opts |= SIMD_VERSION_SSSE3;
1386
1387         if (mono_hwcap_x86_has_sse41)
1388                 sse_opts |= SIMD_VERSION_SSE41;
1389
1390         if (mono_hwcap_x86_has_sse42)
1391                 sse_opts |= SIMD_VERSION_SSE42;
1392
1393         if (mono_hwcap_x86_has_sse4a)
1394                 sse_opts |= SIMD_VERSION_SSE4a;
1395
1396         return sse_opts;
1397 }
1398
1399 #ifndef DISABLE_JIT
1400
1401 GList *
1402 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1403 {
1404         GList *vars = NULL;
1405         int i;
1406
1407         for (i = 0; i < cfg->num_varinfo; i++) {
1408                 MonoInst *ins = cfg->varinfo [i];
1409                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1410
1411                 /* unused vars */
1412                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1413                         continue;
1414
1415                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1416                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1417                         continue;
1418
1419                 if (mono_is_regsize_var (ins->inst_vtype)) {
1420                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1421                         g_assert (i == vmv->idx);
1422                         vars = g_list_prepend (vars, vmv);
1423                 }
1424         }
1425
1426         vars = mono_varlist_sort (cfg, vars, 0);
1427
1428         return vars;
1429 }
1430
1431 /**
1432  * mono_arch_compute_omit_fp:
1433  *
1434  *   Determine whenever the frame pointer can be eliminated.
1435  */
1436 static void
1437 mono_arch_compute_omit_fp (MonoCompile *cfg)
1438 {
1439         MonoMethodSignature *sig;
1440         MonoMethodHeader *header;
1441         int i, locals_size;
1442         CallInfo *cinfo;
1443
1444         if (cfg->arch.omit_fp_computed)
1445                 return;
1446
1447         header = cfg->header;
1448
1449         sig = mono_method_signature (cfg->method);
1450
1451         if (!cfg->arch.cinfo)
1452                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1453         cinfo = cfg->arch.cinfo;
1454
1455         /*
1456          * FIXME: Remove some of the restrictions.
1457          */
1458         cfg->arch.omit_fp = TRUE;
1459         cfg->arch.omit_fp_computed = TRUE;
1460
1461 #ifdef __native_client_codegen__
1462         /* NaCl modules may not change the value of RBP, so it cannot be */
1463         /* used as a normal register, but it can be used as a frame pointer*/
1464         cfg->disable_omit_fp = TRUE;
1465         cfg->arch.omit_fp = FALSE;
1466 #endif
1467
1468         if (cfg->disable_omit_fp)
1469                 cfg->arch.omit_fp = FALSE;
1470
1471         if (!debug_omit_fp ())
1472                 cfg->arch.omit_fp = FALSE;
1473         /*
1474         if (cfg->method->save_lmf)
1475                 cfg->arch.omit_fp = FALSE;
1476         */
1477         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1478                 cfg->arch.omit_fp = FALSE;
1479         if (header->num_clauses)
1480                 cfg->arch.omit_fp = FALSE;
1481         if (cfg->param_area)
1482                 cfg->arch.omit_fp = FALSE;
1483         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1484                 cfg->arch.omit_fp = FALSE;
1485         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1486                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1487                 cfg->arch.omit_fp = FALSE;
1488         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1489                 ArgInfo *ainfo = &cinfo->args [i];
1490
1491                 if (ainfo->storage == ArgOnStack) {
1492                         /*
1493                          * The stack offset can only be determined when the frame
1494                          * size is known.
1495                          */
1496                         cfg->arch.omit_fp = FALSE;
1497                 }
1498         }
1499
1500         locals_size = 0;
1501         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1502                 MonoInst *ins = cfg->varinfo [i];
1503                 int ialign;
1504
1505                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1506         }
1507 }
1508
1509 GList *
1510 mono_arch_get_global_int_regs (MonoCompile *cfg)
1511 {
1512         GList *regs = NULL;
1513
1514         mono_arch_compute_omit_fp (cfg);
1515
1516         if (cfg->globalra) {
1517                 if (cfg->arch.omit_fp)
1518                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1519
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1522                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1523                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1524 #ifndef __native_client_codegen__
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1526 #endif
1527
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1531                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1532                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1533                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1534                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1535                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1536         } else {
1537                 if (cfg->arch.omit_fp)
1538                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1539
1540                 /* We use the callee saved registers for global allocation */
1541                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1542                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1543                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1544                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1545 #ifndef __native_client_codegen__
1546                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1547 #endif
1548 #ifdef HOST_WIN32
1549                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1550                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1551 #endif
1552         }
1553
1554         return regs;
1555 }
1556
1557 GList*
1558 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1559 {
1560         GList *regs = NULL;
1561         int i;
1562
1563         /* All XMM registers */
1564         for (i = 0; i < 16; ++i)
1565                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1566
1567         return regs;
1568 }
1569
1570 GList*
1571 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1572 {
1573         static GList *r = NULL;
1574
1575         if (r == NULL) {
1576                 GList *regs = NULL;
1577
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1581                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1582                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1583 #ifndef __native_client_codegen__
1584                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1585 #endif
1586
1587                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1588                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1589                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1590                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1591                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1592                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1593                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1594                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1595
1596                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1597         }
1598
1599         return r;
1600 }
1601
1602 GList*
1603 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1604 {
1605         int i;
1606         static GList *r = NULL;
1607
1608         if (r == NULL) {
1609                 GList *regs = NULL;
1610
1611                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1612                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1613
1614                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1615         }
1616
1617         return r;
1618 }
1619
1620 /*
1621  * mono_arch_regalloc_cost:
1622  *
1623  *  Return the cost, in number of memory references, of the action of
1624  * allocating the variable VMV into a register during global register
1625  * allocation.
1626  */
1627 guint32
1628 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1629 {
1630         MonoInst *ins = cfg->varinfo [vmv->idx];
1631
1632         if (cfg->method->save_lmf)
1633                 /* The register is already saved */
1634                 /* substract 1 for the invisible store in the prolog */
1635                 return (ins->opcode == OP_ARG) ? 0 : 1;
1636         else
1637                 /* push+pop */
1638                 return (ins->opcode == OP_ARG) ? 1 : 2;
1639 }
1640
1641 /*
1642  * mono_arch_fill_argument_info:
1643  *
1644  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1645  * of the method.
1646  */
1647 void
1648 mono_arch_fill_argument_info (MonoCompile *cfg)
1649 {
1650         MonoType *sig_ret;
1651         MonoMethodSignature *sig;
1652         MonoInst *ins;
1653         int i;
1654         CallInfo *cinfo;
1655
1656         sig = mono_method_signature (cfg->method);
1657
1658         cinfo = cfg->arch.cinfo;
1659         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1660
1661         /*
1662          * Contrary to mono_arch_allocate_vars (), the information should describe
1663          * where the arguments are at the beginning of the method, not where they can be
1664          * accessed during the execution of the method. The later makes no sense for the
1665          * global register allocator, since a variable can be in more than one location.
1666          */
1667         if (sig_ret->type != MONO_TYPE_VOID) {
1668                 switch (cinfo->ret.storage) {
1669                 case ArgInIReg:
1670                 case ArgInFloatSSEReg:
1671                 case ArgInDoubleSSEReg:
1672                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1673                                 cfg->vret_addr->opcode = OP_REGVAR;
1674                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1675                         }
1676                         else {
1677                                 cfg->ret->opcode = OP_REGVAR;
1678                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1679                         }
1680                         break;
1681                 case ArgValuetypeInReg:
1682                         cfg->ret->opcode = OP_REGOFFSET;
1683                         cfg->ret->inst_basereg = -1;
1684                         cfg->ret->inst_offset = -1;
1685                         break;
1686                 default:
1687                         g_assert_not_reached ();
1688                 }
1689         }
1690
1691         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1692                 ArgInfo *ainfo = &cinfo->args [i];
1693
1694                 ins = cfg->args [i];
1695
1696                 switch (ainfo->storage) {
1697                 case ArgInIReg:
1698                 case ArgInFloatSSEReg:
1699                 case ArgInDoubleSSEReg:
1700                         ins->opcode = OP_REGVAR;
1701                         ins->inst_c0 = ainfo->reg;
1702                         break;
1703                 case ArgOnStack:
1704                         ins->opcode = OP_REGOFFSET;
1705                         ins->inst_basereg = -1;
1706                         ins->inst_offset = -1;
1707                         break;
1708                 case ArgValuetypeInReg:
1709                         /* Dummy */
1710                         ins->opcode = OP_NOP;
1711                         break;
1712                 default:
1713                         g_assert_not_reached ();
1714                 }
1715         }
1716 }
1717
1718 void
1719 mono_arch_allocate_vars (MonoCompile *cfg)
1720 {
1721         MonoType *sig_ret;
1722         MonoMethodSignature *sig;
1723         MonoInst *ins;
1724         int i, offset;
1725         guint32 locals_stack_size, locals_stack_align;
1726         gint32 *offsets;
1727         CallInfo *cinfo;
1728
1729         sig = mono_method_signature (cfg->method);
1730
1731         cinfo = cfg->arch.cinfo;
1732         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1733
1734         mono_arch_compute_omit_fp (cfg);
1735
1736         /*
1737          * We use the ABI calling conventions for managed code as well.
1738          * Exception: valuetypes are only sometimes passed or returned in registers.
1739          */
1740
1741         /*
1742          * The stack looks like this:
1743          * <incoming arguments passed on the stack>
1744          * <return value>
1745          * <lmf/caller saved registers>
1746          * <locals>
1747          * <spill area>
1748          * <localloc area>  -> grows dynamically
1749          * <params area>
1750          */
1751
1752         if (cfg->arch.omit_fp) {
1753                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1754                 cfg->frame_reg = AMD64_RSP;
1755                 offset = 0;
1756         } else {
1757                 /* Locals are allocated backwards from %fp */
1758                 cfg->frame_reg = AMD64_RBP;
1759                 offset = 0;
1760         }
1761
1762         cfg->arch.saved_iregs = cfg->used_int_regs;
1763         if (cfg->method->save_lmf)
1764                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1765                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1766
1767         if (cfg->arch.omit_fp)
1768                 cfg->arch.reg_save_area_offset = offset;
1769         /* Reserve space for callee saved registers */
1770         for (i = 0; i < AMD64_NREG; ++i)
1771                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1772                         offset += sizeof(mgreg_t);
1773                 }
1774         if (!cfg->arch.omit_fp)
1775                 cfg->arch.reg_save_area_offset = -offset;
1776
1777         if (sig_ret->type != MONO_TYPE_VOID) {
1778                 switch (cinfo->ret.storage) {
1779                 case ArgInIReg:
1780                 case ArgInFloatSSEReg:
1781                 case ArgInDoubleSSEReg:
1782                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1783                                 if (cfg->globalra) {
1784                                         cfg->vret_addr->opcode = OP_REGVAR;
1785                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1786                                 } else {
1787                                         /* The register is volatile */
1788                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1789                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1790                                         if (cfg->arch.omit_fp) {
1791                                                 cfg->vret_addr->inst_offset = offset;
1792                                                 offset += 8;
1793                                         } else {
1794                                                 offset += 8;
1795                                                 cfg->vret_addr->inst_offset = -offset;
1796                                         }
1797                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1798                                                 printf ("vret_addr =");
1799                                                 mono_print_ins (cfg->vret_addr);
1800                                         }
1801                                 }
1802                         }
1803                         else {
1804                                 cfg->ret->opcode = OP_REGVAR;
1805                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1806                         }
1807                         break;
1808                 case ArgValuetypeInReg:
1809                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1810                         cfg->ret->opcode = OP_REGOFFSET;
1811                         cfg->ret->inst_basereg = cfg->frame_reg;
1812                         if (cfg->arch.omit_fp) {
1813                                 cfg->ret->inst_offset = offset;
1814                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1815                         } else {
1816                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1817                                 cfg->ret->inst_offset = - offset;
1818                         }
1819                         break;
1820                 default:
1821                         g_assert_not_reached ();
1822                 }
1823                 if (!cfg->globalra)
1824                         cfg->ret->dreg = cfg->ret->inst_c0;
1825         }
1826
1827         /* Allocate locals */
1828         if (!cfg->globalra) {
1829                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1830                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1831                         char *mname = mono_method_full_name (cfg->method, TRUE);
1832                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1833                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1834                         g_free (mname);
1835                         return;
1836                 }
1837
1838                 if (locals_stack_align) {
1839                         offset += (locals_stack_align - 1);
1840                         offset &= ~(locals_stack_align - 1);
1841                 }
1842                 if (cfg->arch.omit_fp) {
1843                         cfg->locals_min_stack_offset = offset;
1844                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1845                 } else {
1846                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1847                         cfg->locals_max_stack_offset = - offset;
1848                 }
1849
1850                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1851                         if (offsets [i] != -1) {
1852                                 MonoInst *ins = cfg->varinfo [i];
1853                                 ins->opcode = OP_REGOFFSET;
1854                                 ins->inst_basereg = cfg->frame_reg;
1855                                 if (cfg->arch.omit_fp)
1856                                         ins->inst_offset = (offset + offsets [i]);
1857                                 else
1858                                         ins->inst_offset = - (offset + offsets [i]);
1859                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1860                         }
1861                 }
1862                 offset += locals_stack_size;
1863         }
1864
1865         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1866                 g_assert (!cfg->arch.omit_fp);
1867                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1868                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1869         }
1870
1871         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1872                 ins = cfg->args [i];
1873                 if (ins->opcode != OP_REGVAR) {
1874                         ArgInfo *ainfo = &cinfo->args [i];
1875                         gboolean inreg = TRUE;
1876
1877                         if (cfg->globalra) {
1878                                 /* The new allocator needs info about the original locations of the arguments */
1879                                 switch (ainfo->storage) {
1880                                 case ArgInIReg:
1881                                 case ArgInFloatSSEReg:
1882                                 case ArgInDoubleSSEReg:
1883                                         ins->opcode = OP_REGVAR;
1884                                         ins->inst_c0 = ainfo->reg;
1885                                         break;
1886                                 case ArgOnStack:
1887                                         g_assert (!cfg->arch.omit_fp);
1888                                         ins->opcode = OP_REGOFFSET;
1889                                         ins->inst_basereg = cfg->frame_reg;
1890                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1891                                         break;
1892                                 case ArgValuetypeInReg:
1893                                         ins->opcode = OP_REGOFFSET;
1894                                         ins->inst_basereg = cfg->frame_reg;
1895                                         /* These arguments are saved to the stack in the prolog */
1896                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1897                                         if (cfg->arch.omit_fp) {
1898                                                 ins->inst_offset = offset;
1899                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1900                                         } else {
1901                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1902                                                 ins->inst_offset = - offset;
1903                                         }
1904                                         break;
1905                                 default:
1906                                         g_assert_not_reached ();
1907                                 }
1908
1909                                 continue;
1910                         }
1911
1912                         /* FIXME: Allocate volatile arguments to registers */
1913                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1914                                 inreg = FALSE;
1915
1916                         /*
1917                          * Under AMD64, all registers used to pass arguments to functions
1918                          * are volatile across calls.
1919                          * FIXME: Optimize this.
1920                          */
1921                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1922                                 inreg = FALSE;
1923
1924                         ins->opcode = OP_REGOFFSET;
1925
1926                         switch (ainfo->storage) {
1927                         case ArgInIReg:
1928                         case ArgInFloatSSEReg:
1929                         case ArgInDoubleSSEReg:
1930                                 if (inreg) {
1931                                         ins->opcode = OP_REGVAR;
1932                                         ins->dreg = ainfo->reg;
1933                                 }
1934                                 break;
1935                         case ArgOnStack:
1936                                 g_assert (!cfg->arch.omit_fp);
1937                                 ins->opcode = OP_REGOFFSET;
1938                                 ins->inst_basereg = cfg->frame_reg;
1939                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1940                                 break;
1941                         case ArgValuetypeInReg:
1942                                 break;
1943                         case ArgValuetypeAddrInIReg: {
1944                                 MonoInst *indir;
1945                                 g_assert (!cfg->arch.omit_fp);
1946
1947                                 MONO_INST_NEW (cfg, indir, 0);
1948                                 indir->opcode = OP_REGOFFSET;
1949                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1950                                         indir->inst_basereg = cfg->frame_reg;
1951                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1952                                         offset += (sizeof (gpointer));
1953                                         indir->inst_offset = - offset;
1954                                 }
1955                                 else {
1956                                         indir->inst_basereg = cfg->frame_reg;
1957                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1958                                 }
1959
1960                                 ins->opcode = OP_VTARG_ADDR;
1961                                 ins->inst_left = indir;
1962
1963                                 break;
1964                         }
1965                         default:
1966                                 NOT_IMPLEMENTED;
1967                         }
1968
1969                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1970                                 ins->opcode = OP_REGOFFSET;
1971                                 ins->inst_basereg = cfg->frame_reg;
1972                                 /* These arguments are saved to the stack in the prolog */
1973                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1974                                 if (cfg->arch.omit_fp) {
1975                                         ins->inst_offset = offset;
1976                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1977                                         // Arguments are yet supported by the stack map creation code
1978                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1979                                 } else {
1980                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1981                                         ins->inst_offset = - offset;
1982                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1983                                 }
1984                         }
1985                 }
1986         }
1987
1988         cfg->stack_offset = offset;
1989 }
1990
1991 void
1992 mono_arch_create_vars (MonoCompile *cfg)
1993 {
1994         MonoMethodSignature *sig;
1995         CallInfo *cinfo;
1996         MonoType *sig_ret;
1997
1998         sig = mono_method_signature (cfg->method);
1999
2000         if (!cfg->arch.cinfo)
2001                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2002         cinfo = cfg->arch.cinfo;
2003
2004         if (cinfo->ret.storage == ArgValuetypeInReg)
2005                 cfg->ret_var_is_local = TRUE;
2006
2007         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2008         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2009                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2010                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2011                         printf ("vret_addr = ");
2012                         mono_print_ins (cfg->vret_addr);
2013                 }
2014         }
2015
2016         if (cfg->gen_seq_points_debug_data) {
2017                 MonoInst *ins;
2018
2019                 if (cfg->compile_aot) {
2020                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2021                         ins->flags |= MONO_INST_VOLATILE;
2022                         cfg->arch.seq_point_info_var = ins;
2023                 }
2024
2025             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2026                 ins->flags |= MONO_INST_VOLATILE;
2027                 cfg->arch.ss_trigger_page_var = ins;
2028         }
2029
2030         if (cfg->method->save_lmf)
2031                 cfg->create_lmf_var = TRUE;
2032
2033         if (cfg->method->save_lmf) {
2034                 cfg->lmf_ir = TRUE;
2035 #if !defined(HOST_WIN32)
2036                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2037                         cfg->lmf_ir_mono_lmf = TRUE;
2038 #endif
2039         }
2040 }
2041
2042 static void
2043 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2044 {
2045         MonoInst *ins;
2046
2047         switch (storage) {
2048         case ArgInIReg:
2049                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2050                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2051                 ins->sreg1 = tree->dreg;
2052                 MONO_ADD_INS (cfg->cbb, ins);
2053                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2054                 break;
2055         case ArgInFloatSSEReg:
2056                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2057                 ins->dreg = mono_alloc_freg (cfg);
2058                 ins->sreg1 = tree->dreg;
2059                 MONO_ADD_INS (cfg->cbb, ins);
2060
2061                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2062                 break;
2063         case ArgInDoubleSSEReg:
2064                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2065                 ins->dreg = mono_alloc_freg (cfg);
2066                 ins->sreg1 = tree->dreg;
2067                 MONO_ADD_INS (cfg->cbb, ins);
2068
2069                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2070
2071                 break;
2072         default:
2073                 g_assert_not_reached ();
2074         }
2075 }
2076
2077 static int
2078 arg_storage_to_load_membase (ArgStorage storage)
2079 {
2080         switch (storage) {
2081         case ArgInIReg:
2082 #if defined(__mono_ilp32__)
2083                 return OP_LOADI8_MEMBASE;
2084 #else
2085                 return OP_LOAD_MEMBASE;
2086 #endif
2087         case ArgInDoubleSSEReg:
2088                 return OP_LOADR8_MEMBASE;
2089         case ArgInFloatSSEReg:
2090                 return OP_LOADR4_MEMBASE;
2091         default:
2092                 g_assert_not_reached ();
2093         }
2094
2095         return -1;
2096 }
2097
2098 static void
2099 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2100 {
2101         MonoMethodSignature *tmp_sig;
2102         int sig_reg;
2103
2104         if (call->tail_call)
2105                 NOT_IMPLEMENTED;
2106
2107         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2108
2109         /*
2110          * mono_ArgIterator_Setup assumes the signature cookie is
2111          * passed first and all the arguments which were before it are
2112          * passed on the stack after the signature. So compensate by
2113          * passing a different signature.
2114          */
2115         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2116         tmp_sig->param_count -= call->signature->sentinelpos;
2117         tmp_sig->sentinelpos = 0;
2118         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2119
2120         sig_reg = mono_alloc_ireg (cfg);
2121         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2122
2123         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2124 }
2125
2126 #ifdef ENABLE_LLVM
2127 static inline LLVMArgStorage
2128 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2129 {
2130         switch (storage) {
2131         case ArgInIReg:
2132                 return LLVMArgInIReg;
2133         case ArgNone:
2134                 return LLVMArgNone;
2135         default:
2136                 g_assert_not_reached ();
2137                 return LLVMArgNone;
2138         }
2139 }
2140
2141 LLVMCallInfo*
2142 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2143 {
2144         int i, n;
2145         CallInfo *cinfo;
2146         ArgInfo *ainfo;
2147         int j;
2148         LLVMCallInfo *linfo;
2149         MonoType *t, *sig_ret;
2150
2151         n = sig->param_count + sig->hasthis;
2152         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2153
2154         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2155
2156         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2157
2158         /*
2159          * LLVM always uses the native ABI while we use our own ABI, the
2160          * only difference is the handling of vtypes:
2161          * - we only pass/receive them in registers in some cases, and only
2162          *   in 1 or 2 integer registers.
2163          */
2164         if (cinfo->ret.storage == ArgValuetypeInReg) {
2165                 if (sig->pinvoke) {
2166                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2167                         cfg->disable_llvm = TRUE;
2168                         return linfo;
2169                 }
2170
2171                 linfo->ret.storage = LLVMArgVtypeInReg;
2172                 for (j = 0; j < 2; ++j)
2173                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2174         }
2175
2176         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2177                 /* Vtype returned using a hidden argument */
2178                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2179                 linfo->vret_arg_index = cinfo->vret_arg_index;
2180         }
2181
2182         for (i = 0; i < n; ++i) {
2183                 ainfo = cinfo->args + i;
2184
2185                 if (i >= sig->hasthis)
2186                         t = sig->params [i - sig->hasthis];
2187                 else
2188                         t = &mono_defaults.int_class->byval_arg;
2189
2190                 linfo->args [i].storage = LLVMArgNone;
2191
2192                 switch (ainfo->storage) {
2193                 case ArgInIReg:
2194                         linfo->args [i].storage = LLVMArgInIReg;
2195                         break;
2196                 case ArgInDoubleSSEReg:
2197                 case ArgInFloatSSEReg:
2198                         linfo->args [i].storage = LLVMArgInFPReg;
2199                         break;
2200                 case ArgOnStack:
2201                         if (MONO_TYPE_ISSTRUCT (t)) {
2202                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2203                         } else {
2204                                 linfo->args [i].storage = LLVMArgInIReg;
2205                                 if (!t->byref) {
2206                                         if (t->type == MONO_TYPE_R4)
2207                                                 linfo->args [i].storage = LLVMArgInFPReg;
2208                                         else if (t->type == MONO_TYPE_R8)
2209                                                 linfo->args [i].storage = LLVMArgInFPReg;
2210                                 }
2211                         }
2212                         break;
2213                 case ArgValuetypeInReg:
2214                         if (sig->pinvoke) {
2215                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2216                                 cfg->disable_llvm = TRUE;
2217                                 return linfo;
2218                         }
2219
2220                         linfo->args [i].storage = LLVMArgVtypeInReg;
2221                         for (j = 0; j < 2; ++j)
2222                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2223                         break;
2224                 default:
2225                         cfg->exception_message = g_strdup ("ainfo->storage");
2226                         cfg->disable_llvm = TRUE;
2227                         break;
2228                 }
2229         }
2230
2231         return linfo;
2232 }
2233 #endif
2234
2235 void
2236 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2237 {
2238         MonoInst *arg, *in;
2239         MonoMethodSignature *sig;
2240         MonoType *sig_ret;
2241         int i, n;
2242         CallInfo *cinfo;
2243         ArgInfo *ainfo;
2244
2245         sig = call->signature;
2246         n = sig->param_count + sig->hasthis;
2247
2248         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2249
2250         sig_ret = sig->ret;
2251
2252         if (COMPILE_LLVM (cfg)) {
2253                 /* We shouldn't be called in the llvm case */
2254                 cfg->disable_llvm = TRUE;
2255                 return;
2256         }
2257
2258         /*
2259          * Emit all arguments which are passed on the stack to prevent register
2260          * allocation problems.
2261          */
2262         for (i = 0; i < n; ++i) {
2263                 MonoType *t;
2264                 ainfo = cinfo->args + i;
2265
2266                 in = call->args [i];
2267
2268                 if (sig->hasthis && i == 0)
2269                         t = &mono_defaults.object_class->byval_arg;
2270                 else
2271                         t = sig->params [i - sig->hasthis];
2272
2273                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2274                         if (!t->byref) {
2275                                 if (t->type == MONO_TYPE_R4)
2276                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2277                                 else if (t->type == MONO_TYPE_R8)
2278                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2279                                 else
2280                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2281                         } else {
2282                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2283                         }
2284                         if (cfg->compute_gc_maps) {
2285                                 MonoInst *def;
2286
2287                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2288                         }
2289                 }
2290         }
2291
2292         /*
2293          * Emit all parameters passed in registers in non-reverse order for better readability
2294          * and to help the optimization in emit_prolog ().
2295          */
2296         for (i = 0; i < n; ++i) {
2297                 ainfo = cinfo->args + i;
2298
2299                 in = call->args [i];
2300
2301                 if (ainfo->storage == ArgInIReg)
2302                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2303         }
2304
2305         for (i = n - 1; i >= 0; --i) {
2306                 ainfo = cinfo->args + i;
2307
2308                 in = call->args [i];
2309
2310                 switch (ainfo->storage) {
2311                 case ArgInIReg:
2312                         /* Already done */
2313                         break;
2314                 case ArgInFloatSSEReg:
2315                 case ArgInDoubleSSEReg:
2316                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2317                         break;
2318                 case ArgOnStack:
2319                 case ArgValuetypeInReg:
2320                 case ArgValuetypeAddrInIReg:
2321                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2322                                 MonoInst *call_inst = (MonoInst*)call;
2323                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2324                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2325                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2326                                 guint32 align;
2327                                 guint32 size;
2328
2329                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2330                                         size = sizeof (MonoTypedRef);
2331                                         align = sizeof (gpointer);
2332                                 }
2333                                 else {
2334                                         if (sig->pinvoke)
2335                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2336                                         else {
2337                                                 /*
2338                                                  * Other backends use mono_type_stack_size (), but that
2339                                                  * aligns the size to 8, which is larger than the size of
2340                                                  * the source, leading to reads of invalid memory if the
2341                                                  * source is at the end of address space.
2342                                                  */
2343                                                 size = mono_class_value_size (in->klass, &align);
2344                                         }
2345                                 }
2346                                 g_assert (in->klass);
2347
2348                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2349                                         /* Avoid asserts in emit_memcpy () */
2350                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2351                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2352                                         /* Continue normally */
2353                                 }
2354
2355                                 if (size > 0) {
2356                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2357                                         arg->sreg1 = in->dreg;
2358                                         arg->klass = in->klass;
2359                                         arg->backend.size = size;
2360                                         arg->inst_p0 = call;
2361                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2362                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2363
2364                                         MONO_ADD_INS (cfg->cbb, arg);
2365                                 }
2366                         }
2367                         break;
2368                 default:
2369                         g_assert_not_reached ();
2370                 }
2371
2372                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2373                         /* Emit the signature cookie just before the implicit arguments */
2374                         emit_sig_cookie (cfg, call, cinfo);
2375         }
2376
2377         /* Handle the case where there are no implicit arguments */
2378         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2379                 emit_sig_cookie (cfg, call, cinfo);
2380
2381         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2382         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2383                 MonoInst *vtarg;
2384
2385                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2386                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2387                                 /*
2388                                  * Tell the JIT to use a more efficient calling convention: call using
2389                                  * OP_CALL, compute the result location after the call, and save the
2390                                  * result there.
2391                                  */
2392                                 call->vret_in_reg = TRUE;
2393                                 /*
2394                                  * Nullify the instruction computing the vret addr to enable
2395                                  * future optimizations.
2396                                  */
2397                                 if (call->vret_var)
2398                                         NULLIFY_INS (call->vret_var);
2399                         } else {
2400                                 if (call->tail_call)
2401                                         NOT_IMPLEMENTED;
2402                                 /*
2403                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2404                                  * the stack. Push the address here, so the call instruction can
2405                                  * access it.
2406                                  */
2407                                 if (!cfg->arch.vret_addr_loc) {
2408                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2409                                         /* Prevent it from being register allocated or optimized away */
2410                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2411                                 }
2412
2413                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2414                         }
2415                 }
2416                 else {
2417                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2418                         vtarg->sreg1 = call->vret_var->dreg;
2419                         vtarg->dreg = mono_alloc_preg (cfg);
2420                         MONO_ADD_INS (cfg->cbb, vtarg);
2421
2422                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2423                 }
2424         }
2425
2426         if (cfg->method->save_lmf) {
2427                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2428                 MONO_ADD_INS (cfg->cbb, arg);
2429         }
2430
2431         call->stack_usage = cinfo->stack_usage;
2432 }
2433
2434 void
2435 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2436 {
2437         MonoInst *arg;
2438         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2439         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2440         int size = ins->backend.size;
2441
2442         if (ainfo->storage == ArgValuetypeInReg) {
2443                 MonoInst *load;
2444                 int part;
2445
2446                 for (part = 0; part < 2; ++part) {
2447                         if (ainfo->pair_storage [part] == ArgNone)
2448                                 continue;
2449
2450                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2451                         load->inst_basereg = src->dreg;
2452                         load->inst_offset = part * sizeof(mgreg_t);
2453
2454                         switch (ainfo->pair_storage [part]) {
2455                         case ArgInIReg:
2456                                 load->dreg = mono_alloc_ireg (cfg);
2457                                 break;
2458                         case ArgInDoubleSSEReg:
2459                         case ArgInFloatSSEReg:
2460                                 load->dreg = mono_alloc_freg (cfg);
2461                                 break;
2462                         default:
2463                                 g_assert_not_reached ();
2464                         }
2465                         MONO_ADD_INS (cfg->cbb, load);
2466
2467                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2468                 }
2469         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2470                 MonoInst *vtaddr, *load;
2471                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2472
2473                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2474                 cfg->has_indirection = TRUE;
2475                 load->inst_p0 = vtaddr;
2476                 vtaddr->flags |= MONO_INST_INDIRECT;
2477                 load->type = STACK_MP;
2478                 load->klass = vtaddr->klass;
2479                 load->dreg = mono_alloc_ireg (cfg);
2480                 MONO_ADD_INS (cfg->cbb, load);
2481                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2482
2483                 if (ainfo->pair_storage [0] == ArgInIReg) {
2484                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2485                         arg->dreg = mono_alloc_ireg (cfg);
2486                         arg->sreg1 = load->dreg;
2487                         arg->inst_imm = 0;
2488                         MONO_ADD_INS (cfg->cbb, arg);
2489                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2490                 } else {
2491                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2492                 }
2493         } else {
2494                 if (size == 8) {
2495                         int dreg = mono_alloc_ireg (cfg);
2496
2497                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2498                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2499                 } else if (size <= 40) {
2500                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2501                 } else {
2502                         // FIXME: Code growth
2503                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2504                 }
2505
2506                 if (cfg->compute_gc_maps) {
2507                         MonoInst *def;
2508                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2509                 }
2510         }
2511 }
2512
2513 void
2514 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2515 {
2516         MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2517
2518         if (ret->type == MONO_TYPE_R4) {
2519                 if (COMPILE_LLVM (cfg))
2520                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2521                 else
2522                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2523                 return;
2524         } else if (ret->type == MONO_TYPE_R8) {
2525                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2526                 return;
2527         }
2528
2529         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2530 }
2531
2532 #endif /* DISABLE_JIT */
2533
2534 #define EMIT_COND_BRANCH(ins,cond,sign) \
2535         if (ins->inst_true_bb->native_offset) { \
2536                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2537         } else { \
2538                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2539                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2540             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2541                         x86_branch8 (code, cond, 0, sign); \
2542                 else \
2543                         x86_branch32 (code, cond, 0, sign); \
2544 }
2545
2546 typedef struct {
2547         MonoMethodSignature *sig;
2548         CallInfo *cinfo;
2549 } ArchDynCallInfo;
2550
2551 static gboolean
2552 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2553 {
2554         int i;
2555
2556 #ifdef HOST_WIN32
2557         return FALSE;
2558 #endif
2559
2560         switch (cinfo->ret.storage) {
2561         case ArgNone:
2562         case ArgInIReg:
2563                 break;
2564         case ArgValuetypeInReg: {
2565                 ArgInfo *ainfo = &cinfo->ret;
2566
2567                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2568                         return FALSE;
2569                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2570                         return FALSE;
2571                 break;
2572         }
2573         default:
2574                 return FALSE;
2575         }
2576
2577         for (i = 0; i < cinfo->nargs; ++i) {
2578                 ArgInfo *ainfo = &cinfo->args [i];
2579                 switch (ainfo->storage) {
2580                 case ArgInIReg:
2581                         break;
2582                 case ArgValuetypeInReg:
2583                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2584                                 return FALSE;
2585                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2586                                 return FALSE;
2587                         break;
2588                 default:
2589                         return FALSE;
2590                 }
2591         }
2592
2593         return TRUE;
2594 }
2595
2596 /*
2597  * mono_arch_dyn_call_prepare:
2598  *
2599  *   Return a pointer to an arch-specific structure which contains information
2600  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2601  * supported for SIG.
2602  * This function is equivalent to ffi_prep_cif in libffi.
2603  */
2604 MonoDynCallInfo*
2605 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2606 {
2607         ArchDynCallInfo *info;
2608         CallInfo *cinfo;
2609
2610         cinfo = get_call_info (NULL, NULL, sig);
2611
2612         if (!dyn_call_supported (sig, cinfo)) {
2613                 g_free (cinfo);
2614                 return NULL;
2615         }
2616
2617         info = g_new0 (ArchDynCallInfo, 1);
2618         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2619         info->sig = sig;
2620         info->cinfo = cinfo;
2621
2622         return (MonoDynCallInfo*)info;
2623 }
2624
2625 /*
2626  * mono_arch_dyn_call_free:
2627  *
2628  *   Free a MonoDynCallInfo structure.
2629  */
2630 void
2631 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2632 {
2633         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2634
2635         g_free (ainfo->cinfo);
2636         g_free (ainfo);
2637 }
2638
2639 #if !defined(__native_client__)
2640 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2641 #define GREG_TO_PTR(greg) (gpointer)(greg)
2642 #else
2643 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2644 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2645 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2646 #endif
2647
2648 /*
2649  * mono_arch_get_start_dyn_call:
2650  *
2651  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2652  * store the result into BUF.
2653  * ARGS should be an array of pointers pointing to the arguments.
2654  * RET should point to a memory buffer large enought to hold the result of the
2655  * call.
2656  * This function should be as fast as possible, any work which does not depend
2657  * on the actual values of the arguments should be done in
2658  * mono_arch_dyn_call_prepare ().
2659  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2660  * libffi.
2661  */
2662 void
2663 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2664 {
2665         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2666         DynCallArgs *p = (DynCallArgs*)buf;
2667         int arg_index, greg, i, pindex;
2668         MonoMethodSignature *sig = dinfo->sig;
2669
2670         g_assert (buf_len >= sizeof (DynCallArgs));
2671
2672         p->res = 0;
2673         p->ret = ret;
2674
2675         arg_index = 0;
2676         greg = 0;
2677         pindex = 0;
2678
2679         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2680                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2681                 if (!sig->hasthis)
2682                         pindex = 1;
2683         }
2684
2685         if (dinfo->cinfo->vtype_retaddr)
2686                 p->regs [greg ++] = PTR_TO_GREG(ret);
2687
2688         for (i = pindex; i < sig->param_count; i++) {
2689                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2690                 gpointer *arg = args [arg_index ++];
2691
2692                 if (t->byref) {
2693                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2694                         continue;
2695                 }
2696
2697                 switch (t->type) {
2698                 case MONO_TYPE_STRING:
2699                 case MONO_TYPE_CLASS:
2700                 case MONO_TYPE_ARRAY:
2701                 case MONO_TYPE_SZARRAY:
2702                 case MONO_TYPE_OBJECT:
2703                 case MONO_TYPE_PTR:
2704                 case MONO_TYPE_I:
2705                 case MONO_TYPE_U:
2706 #if !defined(__mono_ilp32__)
2707                 case MONO_TYPE_I8:
2708                 case MONO_TYPE_U8:
2709 #endif
2710                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2711                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2712                         break;
2713 #if defined(__mono_ilp32__)
2714                 case MONO_TYPE_I8:
2715                 case MONO_TYPE_U8:
2716                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2717                         p->regs [greg ++] = *(guint64*)(arg);
2718                         break;
2719 #endif
2720                 case MONO_TYPE_BOOLEAN:
2721                 case MONO_TYPE_U1:
2722                         p->regs [greg ++] = *(guint8*)(arg);
2723                         break;
2724                 case MONO_TYPE_I1:
2725                         p->regs [greg ++] = *(gint8*)(arg);
2726                         break;
2727                 case MONO_TYPE_I2:
2728                         p->regs [greg ++] = *(gint16*)(arg);
2729                         break;
2730                 case MONO_TYPE_U2:
2731                 case MONO_TYPE_CHAR:
2732                         p->regs [greg ++] = *(guint16*)(arg);
2733                         break;
2734                 case MONO_TYPE_I4:
2735                         p->regs [greg ++] = *(gint32*)(arg);
2736                         break;
2737                 case MONO_TYPE_U4:
2738                         p->regs [greg ++] = *(guint32*)(arg);
2739                         break;
2740                 case MONO_TYPE_GENERICINST:
2741                     if (MONO_TYPE_IS_REFERENCE (t)) {
2742                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2743                                 break;
2744                         } else {
2745                                 /* Fall through */
2746                         }
2747                 case MONO_TYPE_VALUETYPE: {
2748                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2749
2750                         g_assert (ainfo->storage == ArgValuetypeInReg);
2751                         if (ainfo->pair_storage [0] != ArgNone) {
2752                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2753                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2754                         }
2755                         if (ainfo->pair_storage [1] != ArgNone) {
2756                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2757                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2758                         }
2759                         break;
2760                 }
2761                 default:
2762                         g_assert_not_reached ();
2763                 }
2764         }
2765
2766         g_assert (greg <= PARAM_REGS);
2767 }
2768
2769 /*
2770  * mono_arch_finish_dyn_call:
2771  *
2772  *   Store the result of a dyn call into the return value buffer passed to
2773  * start_dyn_call ().
2774  * This function should be as fast as possible, any work which does not depend
2775  * on the actual values of the arguments should be done in
2776  * mono_arch_dyn_call_prepare ().
2777  */
2778 void
2779 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2780 {
2781         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2782         MonoMethodSignature *sig = dinfo->sig;
2783         guint8 *ret = ((DynCallArgs*)buf)->ret;
2784         mgreg_t res = ((DynCallArgs*)buf)->res;
2785         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2786
2787         switch (sig_ret->type) {
2788         case MONO_TYPE_VOID:
2789                 *(gpointer*)ret = NULL;
2790                 break;
2791         case MONO_TYPE_STRING:
2792         case MONO_TYPE_CLASS:
2793         case MONO_TYPE_ARRAY:
2794         case MONO_TYPE_SZARRAY:
2795         case MONO_TYPE_OBJECT:
2796         case MONO_TYPE_I:
2797         case MONO_TYPE_U:
2798         case MONO_TYPE_PTR:
2799                 *(gpointer*)ret = GREG_TO_PTR(res);
2800                 break;
2801         case MONO_TYPE_I1:
2802                 *(gint8*)ret = res;
2803                 break;
2804         case MONO_TYPE_U1:
2805         case MONO_TYPE_BOOLEAN:
2806                 *(guint8*)ret = res;
2807                 break;
2808         case MONO_TYPE_I2:
2809                 *(gint16*)ret = res;
2810                 break;
2811         case MONO_TYPE_U2:
2812         case MONO_TYPE_CHAR:
2813                 *(guint16*)ret = res;
2814                 break;
2815         case MONO_TYPE_I4:
2816                 *(gint32*)ret = res;
2817                 break;
2818         case MONO_TYPE_U4:
2819                 *(guint32*)ret = res;
2820                 break;
2821         case MONO_TYPE_I8:
2822                 *(gint64*)ret = res;
2823                 break;
2824         case MONO_TYPE_U8:
2825                 *(guint64*)ret = res;
2826                 break;
2827         case MONO_TYPE_GENERICINST:
2828                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2829                         *(gpointer*)ret = GREG_TO_PTR(res);
2830                         break;
2831                 } else {
2832                         /* Fall through */
2833                 }
2834         case MONO_TYPE_VALUETYPE:
2835                 if (dinfo->cinfo->vtype_retaddr) {
2836                         /* Nothing to do */
2837                 } else {
2838                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2839
2840                         g_assert (ainfo->storage == ArgValuetypeInReg);
2841
2842                         if (ainfo->pair_storage [0] != ArgNone) {
2843                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2844                                 ((mgreg_t*)ret)[0] = res;
2845                         }
2846
2847                         g_assert (ainfo->pair_storage [1] == ArgNone);
2848                 }
2849                 break;
2850         default:
2851                 g_assert_not_reached ();
2852         }
2853 }
2854
2855 /* emit an exception if condition is fail */
2856 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2857         do {                                                        \
2858                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2859                 if (tins == NULL) {                                                                             \
2860                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2861                                         MONO_PATCH_INFO_EXC, exc_name);  \
2862                         x86_branch32 (code, cond, 0, signed);               \
2863                 } else {        \
2864                         EMIT_COND_BRANCH (tins, cond, signed);  \
2865                 }                       \
2866         } while (0);
2867
2868 #define EMIT_FPCOMPARE(code) do { \
2869         amd64_fcompp (code); \
2870         amd64_fnstsw (code); \
2871 } while (0);
2872
2873 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2874     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2875         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2876         amd64_ ##op (code); \
2877         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2878         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2879 } while (0);
2880
2881 static guint8*
2882 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2883 {
2884         gboolean no_patch = FALSE;
2885
2886         /*
2887          * FIXME: Add support for thunks
2888          */
2889         {
2890                 gboolean near_call = FALSE;
2891
2892                 /*
2893                  * Indirect calls are expensive so try to make a near call if possible.
2894                  * The caller memory is allocated by the code manager so it is
2895                  * guaranteed to be at a 32 bit offset.
2896                  */
2897
2898                 if (patch_type != MONO_PATCH_INFO_ABS) {
2899                         /* The target is in memory allocated using the code manager */
2900                         near_call = TRUE;
2901
2902                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2903                                 if (((MonoMethod*)data)->klass->image->aot_module)
2904                                         /* The callee might be an AOT method */
2905                                         near_call = FALSE;
2906                                 if (((MonoMethod*)data)->dynamic)
2907                                         /* The target is in malloc-ed memory */
2908                                         near_call = FALSE;
2909                         }
2910
2911                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2912                                 /*
2913                                  * The call might go directly to a native function without
2914                                  * the wrapper.
2915                                  */
2916                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2917                                 if (mi) {
2918                                         gconstpointer target = mono_icall_get_wrapper (mi);
2919                                         if ((((guint64)target) >> 32) != 0)
2920                                                 near_call = FALSE;
2921                                 }
2922                         }
2923                 }
2924                 else {
2925                         MonoJumpInfo *jinfo = NULL;
2926
2927                         if (cfg->abs_patches)
2928                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2929                         if (jinfo) {
2930                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2931                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2932                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2933                                                 near_call = TRUE;
2934                                         no_patch = TRUE;
2935                                 } else {
2936                                         /*
2937                                          * This is not really an optimization, but required because the
2938                                          * generic class init trampolines use R11 to pass the vtable.
2939                                          */
2940                                         near_call = TRUE;
2941                                 }
2942                         } else {
2943                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2944                                 if (info) {
2945                                         if (info->func == info->wrapper) {
2946                                                 /* No wrapper */
2947                                                 if ((((guint64)info->func) >> 32) == 0)
2948                                                         near_call = TRUE;
2949                                         }
2950                                         else {
2951                                                 /* See the comment in mono_codegen () */
2952                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2953                                                         near_call = TRUE;
2954                                         }
2955                                 }
2956                                 else if ((((guint64)data) >> 32) == 0) {
2957                                         near_call = TRUE;
2958                                         no_patch = TRUE;
2959                                 }
2960                         }
2961                 }
2962
2963                 if (cfg->method->dynamic)
2964                         /* These methods are allocated using malloc */
2965                         near_call = FALSE;
2966
2967 #ifdef MONO_ARCH_NOMAP32BIT
2968                 near_call = FALSE;
2969 #endif
2970 #if defined(__native_client__)
2971                 /* Always use near_call == TRUE for Native Client */
2972                 near_call = TRUE;
2973 #endif
2974                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2975                 if (optimize_for_xen)
2976                         near_call = FALSE;
2977
2978                 if (cfg->compile_aot) {
2979                         near_call = TRUE;
2980                         no_patch = TRUE;
2981                 }
2982
2983                 if (near_call) {
2984                         /*
2985                          * Align the call displacement to an address divisible by 4 so it does
2986                          * not span cache lines. This is required for code patching to work on SMP
2987                          * systems.
2988                          */
2989                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2990                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2991                                 amd64_padding (code, pad_size);
2992                         }
2993                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2994                         amd64_call_code (code, 0);
2995                 }
2996                 else {
2997                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2998                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2999                         amd64_call_reg (code, GP_SCRATCH_REG);
3000                 }
3001         }
3002
3003         return code;
3004 }
3005
3006 static inline guint8*
3007 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3008 {
3009 #ifdef HOST_WIN32
3010         if (win64_adjust_stack)
3011                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3012 #endif
3013         code = emit_call_body (cfg, code, patch_type, data);
3014 #ifdef HOST_WIN32
3015         if (win64_adjust_stack)
3016                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3017 #endif
3018
3019         return code;
3020 }
3021
3022 static inline int
3023 store_membase_imm_to_store_membase_reg (int opcode)
3024 {
3025         switch (opcode) {
3026         case OP_STORE_MEMBASE_IMM:
3027                 return OP_STORE_MEMBASE_REG;
3028         case OP_STOREI4_MEMBASE_IMM:
3029                 return OP_STOREI4_MEMBASE_REG;
3030         case OP_STOREI8_MEMBASE_IMM:
3031                 return OP_STOREI8_MEMBASE_REG;
3032         }
3033
3034         return -1;
3035 }
3036
3037 #ifndef DISABLE_JIT
3038
3039 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3040
3041 /*
3042  * mono_arch_peephole_pass_1:
3043  *
3044  *   Perform peephole opts which should/can be performed before local regalloc
3045  */
3046 void
3047 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3048 {
3049         MonoInst *ins, *n;
3050
3051         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3052                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3053
3054                 switch (ins->opcode) {
3055                 case OP_ADD_IMM:
3056                 case OP_IADD_IMM:
3057                 case OP_LADD_IMM:
3058                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3059                                 /*
3060                                  * X86_LEA is like ADD, but doesn't have the
3061                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3062                                  * its operand to 64 bit.
3063                                  */
3064                                 ins->opcode = OP_X86_LEA_MEMBASE;
3065                                 ins->inst_basereg = ins->sreg1;
3066                         }
3067                         break;
3068                 case OP_LXOR:
3069                 case OP_IXOR:
3070                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3071                                 MonoInst *ins2;
3072
3073                                 /*
3074                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3075                                  * the latter has length 2-3 instead of 6 (reverse constant
3076                                  * propagation). These instruction sequences are very common
3077                                  * in the initlocals bblock.
3078                                  */
3079                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3080                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3081                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3082                                                 ins2->sreg1 = ins->dreg;
3083                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3084                                                 /* Continue */
3085                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3086                                                 NULLIFY_INS (ins2);
3087                                                 /* Continue */
3088                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3089                                                 /* Continue */
3090                                         } else {
3091                                                 break;
3092                                         }
3093                                 }
3094                         }
3095                         break;
3096                 case OP_COMPARE_IMM:
3097                 case OP_LCOMPARE_IMM:
3098                         /* OP_COMPARE_IMM (reg, 0)
3099                          * -->
3100                          * OP_AMD64_TEST_NULL (reg)
3101                          */
3102                         if (!ins->inst_imm)
3103                                 ins->opcode = OP_AMD64_TEST_NULL;
3104                         break;
3105                 case OP_ICOMPARE_IMM:
3106                         if (!ins->inst_imm)
3107                                 ins->opcode = OP_X86_TEST_NULL;
3108                         break;
3109                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3110                         /*
3111                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3112                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3113                          * -->
3114                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3115                          * OP_COMPARE_IMM reg, imm
3116                          *
3117                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3118                          */
3119                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3120                             ins->inst_basereg == last_ins->inst_destbasereg &&
3121                             ins->inst_offset == last_ins->inst_offset) {
3122                                         ins->opcode = OP_ICOMPARE_IMM;
3123                                         ins->sreg1 = last_ins->sreg1;
3124
3125                                         /* check if we can remove cmp reg,0 with test null */
3126                                         if (!ins->inst_imm)
3127                                                 ins->opcode = OP_X86_TEST_NULL;
3128                                 }
3129
3130                         break;
3131                 }
3132
3133                 mono_peephole_ins (bb, ins);
3134         }
3135 }
3136
3137 void
3138 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3139 {
3140         MonoInst *ins, *n;
3141
3142         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3143                 switch (ins->opcode) {
3144                 case OP_ICONST:
3145                 case OP_I8CONST: {
3146                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3147                         /* reg = 0 -> XOR (reg, reg) */
3148                         /* XOR sets cflags on x86, so we cant do it always */
3149                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3150                                 ins->opcode = OP_LXOR;
3151                                 ins->sreg1 = ins->dreg;
3152                                 ins->sreg2 = ins->dreg;
3153                                 /* Fall through */
3154                         } else {
3155                                 break;
3156                         }
3157                 }
3158                 case OP_LXOR:
3159                         /*
3160                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3161                          * 0 result into 64 bits.
3162                          */
3163                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3164                                 ins->opcode = OP_IXOR;
3165                         }
3166                         /* Fall through */
3167                 case OP_IXOR:
3168                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3169                                 MonoInst *ins2;
3170
3171                                 /*
3172                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3173                                  * the latter has length 2-3 instead of 6 (reverse constant
3174                                  * propagation). These instruction sequences are very common
3175                                  * in the initlocals bblock.
3176                                  */
3177                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3178                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3179                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3180                                                 ins2->sreg1 = ins->dreg;
3181                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3182                                                 /* Continue */
3183                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3184                                                 NULLIFY_INS (ins2);
3185                                                 /* Continue */
3186                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3187                                                 /* Continue */
3188                                         } else {
3189                                                 break;
3190                                         }
3191                                 }
3192                         }
3193                         break;
3194                 case OP_IADD_IMM:
3195                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3196                                 ins->opcode = OP_X86_INC_REG;
3197                         break;
3198                 case OP_ISUB_IMM:
3199                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3200                                 ins->opcode = OP_X86_DEC_REG;
3201                         break;
3202                 }
3203
3204                 mono_peephole_ins (bb, ins);
3205         }
3206 }
3207
3208 #define NEW_INS(cfg,ins,dest,op) do {   \
3209                 MONO_INST_NEW ((cfg), (dest), (op)); \
3210         (dest)->cil_code = (ins)->cil_code; \
3211         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3212         } while (0)
3213
3214 /*
3215  * mono_arch_lowering_pass:
3216  *
3217  *  Converts complex opcodes into simpler ones so that each IR instruction
3218  * corresponds to one machine instruction.
3219  */
3220 void
3221 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3222 {
3223         MonoInst *ins, *n, *temp;
3224
3225         /*
3226          * FIXME: Need to add more instructions, but the current machine
3227          * description can't model some parts of the composite instructions like
3228          * cdq.
3229          */
3230         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3231                 switch (ins->opcode) {
3232                 case OP_DIV_IMM:
3233                 case OP_REM_IMM:
3234                 case OP_IDIV_IMM:
3235                 case OP_IDIV_UN_IMM:
3236                 case OP_IREM_UN_IMM:
3237                 case OP_LREM_IMM:
3238                 case OP_IREM_IMM:
3239                         mono_decompose_op_imm (cfg, bb, ins);
3240                         break;
3241                 case OP_COMPARE_IMM:
3242                 case OP_LCOMPARE_IMM:
3243                         if (!amd64_is_imm32 (ins->inst_imm)) {
3244                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3245                                 temp->inst_c0 = ins->inst_imm;
3246                                 temp->dreg = mono_alloc_ireg (cfg);
3247                                 ins->opcode = OP_COMPARE;
3248                                 ins->sreg2 = temp->dreg;
3249                         }
3250                         break;
3251 #ifndef __mono_ilp32__
3252                 case OP_LOAD_MEMBASE:
3253 #endif
3254                 case OP_LOADI8_MEMBASE:
3255 #ifndef __native_client_codegen__
3256                 /*  Don't generate memindex opcodes (to simplify */
3257                 /*  read sandboxing) */
3258                         if (!amd64_is_imm32 (ins->inst_offset)) {
3259                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3260                                 temp->inst_c0 = ins->inst_offset;
3261                                 temp->dreg = mono_alloc_ireg (cfg);
3262                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3263                                 ins->inst_indexreg = temp->dreg;
3264                         }
3265 #endif
3266                         break;
3267 #ifndef __mono_ilp32__
3268                 case OP_STORE_MEMBASE_IMM:
3269 #endif
3270                 case OP_STOREI8_MEMBASE_IMM:
3271                         if (!amd64_is_imm32 (ins->inst_imm)) {
3272                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3273                                 temp->inst_c0 = ins->inst_imm;
3274                                 temp->dreg = mono_alloc_ireg (cfg);
3275                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3276                                 ins->sreg1 = temp->dreg;
3277                         }
3278                         break;
3279 #ifdef MONO_ARCH_SIMD_INTRINSICS
3280                 case OP_EXPAND_I1: {
3281                                 int temp_reg1 = mono_alloc_ireg (cfg);
3282                                 int temp_reg2 = mono_alloc_ireg (cfg);
3283                                 int original_reg = ins->sreg1;
3284
3285                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3286                                 temp->sreg1 = original_reg;
3287                                 temp->dreg = temp_reg1;
3288
3289                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3290                                 temp->sreg1 = temp_reg1;
3291                                 temp->dreg = temp_reg2;
3292                                 temp->inst_imm = 8;
3293
3294                                 NEW_INS (cfg, ins, temp, OP_LOR);
3295                                 temp->sreg1 = temp->dreg = temp_reg2;
3296                                 temp->sreg2 = temp_reg1;
3297
3298                                 ins->opcode = OP_EXPAND_I2;
3299                                 ins->sreg1 = temp_reg2;
3300                         }
3301                         break;
3302 #endif
3303                 default:
3304                         break;
3305                 }
3306         }
3307
3308         bb->max_vreg = cfg->next_vreg;
3309 }
3310
3311 static const int
3312 branch_cc_table [] = {
3313         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3314         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3315         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3316 };
3317
3318 /* Maps CMP_... constants to X86_CC_... constants */
3319 static const int
3320 cc_table [] = {
3321         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3322         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3323 };
3324
3325 static const int
3326 cc_signed_table [] = {
3327         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3328         FALSE, FALSE, FALSE, FALSE
3329 };
3330
3331 /*#include "cprop.c"*/
3332
3333 static unsigned char*
3334 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3335 {
3336         if (size == 8)
3337                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3338         else
3339                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3340
3341         if (size == 1)
3342                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3343         else if (size == 2)
3344                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3345         return code;
3346 }
3347
3348 static unsigned char*
3349 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3350 {
3351         int sreg = tree->sreg1;
3352         int need_touch = FALSE;
3353
3354 #if defined(HOST_WIN32)
3355         need_touch = TRUE;
3356 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3357         if (!tree->flags & MONO_INST_INIT)
3358                 need_touch = TRUE;
3359 #endif
3360
3361         if (need_touch) {
3362                 guint8* br[5];
3363
3364                 /*
3365                  * Under Windows:
3366                  * If requested stack size is larger than one page,
3367                  * perform stack-touch operation
3368                  */
3369                 /*
3370                  * Generate stack probe code.
3371                  * Under Windows, it is necessary to allocate one page at a time,
3372                  * "touching" stack after each successful sub-allocation. This is
3373                  * because of the way stack growth is implemented - there is a
3374                  * guard page before the lowest stack page that is currently commited.
3375                  * Stack normally grows sequentially so OS traps access to the
3376                  * guard page and commits more pages when needed.
3377                  */
3378                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3379                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3380
3381                 br[2] = code; /* loop */
3382                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3383                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3384                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3385                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3386                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3387                 amd64_patch (br[3], br[2]);
3388                 amd64_test_reg_reg (code, sreg, sreg);
3389                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3390                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3391
3392                 br[1] = code; x86_jump8 (code, 0);
3393
3394                 amd64_patch (br[0], code);
3395                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3396                 amd64_patch (br[1], code);
3397                 amd64_patch (br[4], code);
3398         }
3399         else
3400                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3401
3402         if (tree->flags & MONO_INST_INIT) {
3403                 int offset = 0;
3404                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3405                         amd64_push_reg (code, AMD64_RAX);
3406                         offset += 8;
3407                 }
3408                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3409                         amd64_push_reg (code, AMD64_RCX);
3410                         offset += 8;
3411                 }
3412                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3413                         amd64_push_reg (code, AMD64_RDI);
3414                         offset += 8;
3415                 }
3416
3417                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3418                 if (sreg != AMD64_RCX)
3419                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3420                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3421
3422                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3423                 if (cfg->param_area)
3424                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3425                 amd64_cld (code);
3426 #if defined(__default_codegen__)
3427                 amd64_prefix (code, X86_REP_PREFIX);
3428                 amd64_stosl (code);
3429 #elif defined(__native_client_codegen__)
3430                 /* NaCl stos pseudo-instruction */
3431                 amd64_codegen_pre(code);
3432                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3433                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3434                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3435                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3436                 amd64_prefix (code, X86_REP_PREFIX);
3437                 amd64_stosl (code);
3438                 amd64_codegen_post(code);
3439 #endif /* __native_client_codegen__ */
3440
3441                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3442                         amd64_pop_reg (code, AMD64_RDI);
3443                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3444                         amd64_pop_reg (code, AMD64_RCX);
3445                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3446                         amd64_pop_reg (code, AMD64_RAX);
3447         }
3448         return code;
3449 }
3450
3451 static guint8*
3452 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3453 {
3454         CallInfo *cinfo;
3455         guint32 quad;
3456
3457         /* Move return value to the target register */
3458         /* FIXME: do this in the local reg allocator */
3459         switch (ins->opcode) {
3460         case OP_CALL:
3461         case OP_CALL_REG:
3462         case OP_CALL_MEMBASE:
3463         case OP_LCALL:
3464         case OP_LCALL_REG:
3465         case OP_LCALL_MEMBASE:
3466                 g_assert (ins->dreg == AMD64_RAX);
3467                 break;
3468         case OP_FCALL:
3469         case OP_FCALL_REG:
3470         case OP_FCALL_MEMBASE:
3471                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3472                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3473                 }
3474                 else {
3475                         if (ins->dreg != AMD64_XMM0)
3476                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3477                 }
3478                 break;
3479         case OP_RCALL:
3480         case OP_RCALL_REG:
3481         case OP_RCALL_MEMBASE:
3482                 if (ins->dreg != AMD64_XMM0)
3483                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3484                 break;
3485         case OP_VCALL:
3486         case OP_VCALL_REG:
3487         case OP_VCALL_MEMBASE:
3488         case OP_VCALL2:
3489         case OP_VCALL2_REG:
3490         case OP_VCALL2_MEMBASE:
3491                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3492                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3493                         MonoInst *loc = cfg->arch.vret_addr_loc;
3494
3495                         /* Load the destination address */
3496                         g_assert (loc->opcode == OP_REGOFFSET);
3497                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3498
3499                         for (quad = 0; quad < 2; quad ++) {
3500                                 switch (cinfo->ret.pair_storage [quad]) {
3501                                 case ArgInIReg:
3502                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3503                                         break;
3504                                 case ArgInFloatSSEReg:
3505                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3506                                         break;
3507                                 case ArgInDoubleSSEReg:
3508                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3509                                         break;
3510                                 case ArgNone:
3511                                         break;
3512                                 default:
3513                                         NOT_IMPLEMENTED;
3514                                 }
3515                         }
3516                 }
3517                 break;
3518         }
3519
3520         return code;
3521 }
3522
3523 #endif /* DISABLE_JIT */
3524
3525 #ifdef __APPLE__
3526 static int tls_gs_offset;
3527 #endif
3528
3529 gboolean
3530 mono_amd64_have_tls_get (void)
3531 {
3532 #ifdef TARGET_MACH
3533         static gboolean have_tls_get = FALSE;
3534         static gboolean inited = FALSE;
3535         guint8 *ins;
3536
3537         if (inited)
3538                 return have_tls_get;
3539
3540         ins = (guint8*)pthread_getspecific;
3541
3542         /*
3543          * We're looking for these two instructions:
3544          *
3545          * mov    %gs:[offset](,%rdi,8),%rax
3546          * retq
3547          */
3548         have_tls_get = ins [0] == 0x65 &&
3549                        ins [1] == 0x48 &&
3550                        ins [2] == 0x8b &&
3551                        ins [3] == 0x04 &&
3552                        ins [4] == 0xfd &&
3553                        ins [6] == 0x00 &&
3554                        ins [7] == 0x00 &&
3555                        ins [8] == 0x00 &&
3556                        ins [9] == 0xc3;
3557
3558         inited = TRUE;
3559
3560         tls_gs_offset = ins[5];
3561
3562         return have_tls_get;
3563 #elif defined(TARGET_ANDROID)
3564         return FALSE;
3565 #else
3566         return TRUE;
3567 #endif
3568 }
3569
3570 int
3571 mono_amd64_get_tls_gs_offset (void)
3572 {
3573 #ifdef TARGET_OSX
3574         return tls_gs_offset;
3575 #else
3576         g_assert_not_reached ();
3577         return -1;
3578 #endif
3579 }
3580
3581 /*
3582  * mono_amd64_emit_tls_get:
3583  * @code: buffer to store code to
3584  * @dreg: hard register where to place the result
3585  * @tls_offset: offset info
3586  *
3587  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3588  * the dreg register the item in the thread local storage identified
3589  * by tls_offset.
3590  *
3591  * Returns: a pointer to the end of the stored code
3592  */
3593 guint8*
3594 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3595 {
3596 #ifdef HOST_WIN32
3597         if (tls_offset < 64) {
3598                 x86_prefix (code, X86_GS_PREFIX);
3599                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3600         } else {
3601                 guint8 *buf [16];
3602
3603                 g_assert (tls_offset < 0x440);
3604                 /* Load TEB->TlsExpansionSlots */
3605                 x86_prefix (code, X86_GS_PREFIX);
3606                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3607                 amd64_test_reg_reg (code, dreg, dreg);
3608                 buf [0] = code;
3609                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3610                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3611                 amd64_patch (buf [0], code);
3612         }
3613 #elif defined(__APPLE__)
3614         x86_prefix (code, X86_GS_PREFIX);
3615         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3616 #else
3617         if (optimize_for_xen) {
3618                 x86_prefix (code, X86_FS_PREFIX);
3619                 amd64_mov_reg_mem (code, dreg, 0, 8);
3620                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3621         } else {
3622                 x86_prefix (code, X86_FS_PREFIX);
3623                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3624         }
3625 #endif
3626         return code;
3627 }
3628
3629 static guint8*
3630 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3631 {
3632         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3633 #ifdef TARGET_OSX
3634         if (dreg != offset_reg)
3635                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3636         amd64_prefix (code, X86_GS_PREFIX);
3637         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3638 #elif defined(__linux__)
3639         int tmpreg = -1;
3640
3641         if (dreg == offset_reg) {
3642                 /* Use a temporary reg by saving it to the redzone */
3643                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3644                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3645                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3646                 offset_reg = tmpreg;
3647         }
3648         x86_prefix (code, X86_FS_PREFIX);
3649         amd64_mov_reg_mem (code, dreg, 0, 8);
3650         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3651         if (tmpreg != -1)
3652                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3653 #else
3654         g_assert_not_reached ();
3655 #endif
3656         return code;
3657 }
3658
3659 static guint8*
3660 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3661 {
3662 #ifdef HOST_WIN32
3663         g_assert_not_reached ();
3664 #elif defined(__APPLE__)
3665         x86_prefix (code, X86_GS_PREFIX);
3666         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3667 #else
3668         g_assert (!optimize_for_xen);
3669         x86_prefix (code, X86_FS_PREFIX);
3670         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3671 #endif
3672         return code;
3673 }
3674
3675 static guint8*
3676 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3677 {
3678         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3679 #ifdef HOST_WIN32
3680         g_assert_not_reached ();
3681 #elif defined(__APPLE__)
3682         x86_prefix (code, X86_GS_PREFIX);
3683         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3684 #else
3685         x86_prefix (code, X86_FS_PREFIX);
3686         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3687 #endif
3688         return code;
3689 }
3690
3691  /*
3692  * mono_arch_translate_tls_offset:
3693  *
3694  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3695  */
3696 int
3697 mono_arch_translate_tls_offset (int offset)
3698 {
3699 #ifdef __APPLE__
3700         return tls_gs_offset + (offset * 8);
3701 #else
3702         return offset;
3703 #endif
3704 }
3705
3706 /*
3707  * emit_setup_lmf:
3708  *
3709  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3710  */
3711 static guint8*
3712 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3713 {
3714         /*
3715          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3716          */
3717         /*
3718          * sp is saved right before calls but we need to save it here too so
3719          * async stack walks would work.
3720          */
3721         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3722         /* Save rbp */
3723         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3724         if (cfg->arch.omit_fp && cfa_offset != -1)
3725                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3726
3727         /* These can't contain refs */
3728         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3729         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3730         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3731         /* These are handled automatically by the stack marking code */
3732         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3733
3734         return code;
3735 }
3736
3737 #define REAL_PRINT_REG(text,reg) \
3738 mono_assert (reg >= 0); \
3739 amd64_push_reg (code, AMD64_RAX); \
3740 amd64_push_reg (code, AMD64_RDX); \
3741 amd64_push_reg (code, AMD64_RCX); \
3742 amd64_push_reg (code, reg); \
3743 amd64_push_imm (code, reg); \
3744 amd64_push_imm (code, text " %d %p\n"); \
3745 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3746 amd64_call_reg (code, AMD64_RAX); \
3747 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3748 amd64_pop_reg (code, AMD64_RCX); \
3749 amd64_pop_reg (code, AMD64_RDX); \
3750 amd64_pop_reg (code, AMD64_RAX);
3751
3752 /* benchmark and set based on cpu */
3753 #define LOOP_ALIGNMENT 8
3754 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3755
3756 #ifndef DISABLE_JIT
3757 void
3758 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3759 {
3760         MonoInst *ins;
3761         MonoCallInst *call;
3762         guint offset;
3763         guint8 *code = cfg->native_code + cfg->code_len;
3764         int max_len;
3765
3766         /* Fix max_offset estimate for each successor bb */
3767         if (cfg->opt & MONO_OPT_BRANCH) {
3768                 int current_offset = cfg->code_len;
3769                 MonoBasicBlock *current_bb;
3770                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3771                         current_bb->max_offset = current_offset;
3772                         current_offset += current_bb->max_length;
3773                 }
3774         }
3775
3776         if (cfg->opt & MONO_OPT_LOOP) {
3777                 int pad, align = LOOP_ALIGNMENT;
3778                 /* set alignment depending on cpu */
3779                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3780                         pad = align - pad;
3781                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3782                         amd64_padding (code, pad);
3783                         cfg->code_len += pad;
3784                         bb->native_offset = cfg->code_len;
3785                 }
3786         }
3787
3788 #if defined(__native_client_codegen__)
3789         /* For Native Client, all indirect call/jump targets must be */
3790         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3791         /* indirectly as well.                                       */
3792         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3793                                       (bb->flags & BB_EXCEPTION_HANDLER);
3794
3795         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3796                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3797                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3798                 cfg->code_len += pad;
3799                 bb->native_offset = cfg->code_len;
3800         }
3801 #endif  /*__native_client_codegen__*/
3802
3803         if (cfg->verbose_level > 2)
3804                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3805
3806         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3807                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3808                 g_assert (!cfg->compile_aot);
3809
3810                 cov->data [bb->dfn].cil_code = bb->cil_code;
3811                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3812                 /* this is not thread save, but good enough */
3813                 amd64_inc_membase (code, AMD64_R11, 0);
3814         }
3815
3816         offset = code - cfg->native_code;
3817
3818         mono_debug_open_block (cfg, bb, offset);
3819
3820     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3821                 x86_breakpoint (code);
3822
3823         MONO_BB_FOR_EACH_INS (bb, ins) {
3824                 offset = code - cfg->native_code;
3825
3826                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3827
3828 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3829
3830                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3831                         cfg->code_size *= 2;
3832                         cfg->native_code = mono_realloc_native_code(cfg);
3833                         code = cfg->native_code + offset;
3834                         cfg->stat_code_reallocs++;
3835                 }
3836
3837                 if (cfg->debug_info)
3838                         mono_debug_record_line_number (cfg, ins, offset);
3839
3840                 switch (ins->opcode) {
3841                 case OP_BIGMUL:
3842                         amd64_mul_reg (code, ins->sreg2, TRUE);
3843                         break;
3844                 case OP_BIGMUL_UN:
3845                         amd64_mul_reg (code, ins->sreg2, FALSE);
3846                         break;
3847                 case OP_X86_SETEQ_MEMBASE:
3848                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3849                         break;
3850                 case OP_STOREI1_MEMBASE_IMM:
3851                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3852                         break;
3853                 case OP_STOREI2_MEMBASE_IMM:
3854                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3855                         break;
3856                 case OP_STOREI4_MEMBASE_IMM:
3857                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3858                         break;
3859                 case OP_STOREI1_MEMBASE_REG:
3860                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3861                         break;
3862                 case OP_STOREI2_MEMBASE_REG:
3863                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3864                         break;
3865                 /* In AMD64 NaCl, pointers are 4 bytes, */
3866                 /*  so STORE_* != STOREI8_*. Likewise below. */
3867                 case OP_STORE_MEMBASE_REG:
3868                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3869                         break;
3870                 case OP_STOREI8_MEMBASE_REG:
3871                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3872                         break;
3873                 case OP_STOREI4_MEMBASE_REG:
3874                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3875                         break;
3876                 case OP_STORE_MEMBASE_IMM:
3877 #ifndef __native_client_codegen__
3878                         /* In NaCl, this could be a PCONST type, which could */
3879                         /* mean a pointer type was copied directly into the  */
3880                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3881                         /* the value would be 0x00000000FFFFFFFF which is    */
3882                         /* not proper for an imm32 unless you cast it.       */
3883                         g_assert (amd64_is_imm32 (ins->inst_imm));
3884 #endif
3885                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3886                         break;
3887                 case OP_STOREI8_MEMBASE_IMM:
3888                         g_assert (amd64_is_imm32 (ins->inst_imm));
3889                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3890                         break;
3891                 case OP_LOAD_MEM:
3892 #ifdef __mono_ilp32__
3893                         /* In ILP32, pointers are 4 bytes, so separate these */
3894                         /* cases, use literal 8 below where we really want 8 */
3895                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3896                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3897                         break;
3898 #endif
3899                 case OP_LOADI8_MEM:
3900                         // FIXME: Decompose this earlier
3901                         if (amd64_is_imm32 (ins->inst_imm))
3902                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3903                         else {
3904                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3905                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3906                         }
3907                         break;
3908                 case OP_LOADI4_MEM:
3909                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3910                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3911                         break;
3912                 case OP_LOADU4_MEM:
3913                         // FIXME: Decompose this earlier
3914                         if (amd64_is_imm32 (ins->inst_imm))
3915                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3916                         else {
3917                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3918                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3919                         }
3920                         break;
3921                 case OP_LOADU1_MEM:
3922                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3923                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3924                         break;
3925                 case OP_LOADU2_MEM:
3926                         /* For NaCl, pointers are 4 bytes, so separate these */
3927                         /* cases, use literal 8 below where we really want 8 */
3928                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3929                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3930                         break;
3931                 case OP_LOAD_MEMBASE:
3932                         g_assert (amd64_is_imm32 (ins->inst_offset));
3933                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3934                         break;
3935                 case OP_LOADI8_MEMBASE:
3936                         /* Use literal 8 instead of sizeof pointer or */
3937                         /* register, we really want 8 for this opcode */
3938                         g_assert (amd64_is_imm32 (ins->inst_offset));
3939                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3940                         break;
3941                 case OP_LOADI4_MEMBASE:
3942                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3943                         break;
3944                 case OP_LOADU4_MEMBASE:
3945                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3946                         break;
3947                 case OP_LOADU1_MEMBASE:
3948                         /* The cpu zero extends the result into 64 bits */
3949                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3950                         break;
3951                 case OP_LOADI1_MEMBASE:
3952                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3953                         break;
3954                 case OP_LOADU2_MEMBASE:
3955                         /* The cpu zero extends the result into 64 bits */
3956                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3957                         break;
3958                 case OP_LOADI2_MEMBASE:
3959                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3960                         break;
3961                 case OP_AMD64_LOADI8_MEMINDEX:
3962                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3963                         break;
3964                 case OP_LCONV_TO_I1:
3965                 case OP_ICONV_TO_I1:
3966                 case OP_SEXT_I1:
3967                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3968                         break;
3969                 case OP_LCONV_TO_I2:
3970                 case OP_ICONV_TO_I2:
3971                 case OP_SEXT_I2:
3972                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3973                         break;
3974                 case OP_LCONV_TO_U1:
3975                 case OP_ICONV_TO_U1:
3976                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3977                         break;
3978                 case OP_LCONV_TO_U2:
3979                 case OP_ICONV_TO_U2:
3980                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3981                         break;
3982                 case OP_ZEXT_I4:
3983                         /* Clean out the upper word */
3984                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3985                         break;
3986                 case OP_SEXT_I4:
3987                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3988                         break;
3989                 case OP_COMPARE:
3990                 case OP_LCOMPARE:
3991                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3992                         break;
3993                 case OP_COMPARE_IMM:
3994 #if defined(__mono_ilp32__)
3995                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3996                         g_assert (amd64_is_imm32 (ins->inst_imm));
3997                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3998                         break;
3999 #endif
4000                 case OP_LCOMPARE_IMM:
4001                         g_assert (amd64_is_imm32 (ins->inst_imm));
4002                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4003                         break;
4004                 case OP_X86_COMPARE_REG_MEMBASE:
4005                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4006                         break;
4007                 case OP_X86_TEST_NULL:
4008                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4009                         break;
4010                 case OP_AMD64_TEST_NULL:
4011                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4012                         break;
4013
4014                 case OP_X86_ADD_REG_MEMBASE:
4015                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4016                         break;
4017                 case OP_X86_SUB_REG_MEMBASE:
4018                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4019                         break;
4020                 case OP_X86_AND_REG_MEMBASE:
4021                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4022                         break;
4023                 case OP_X86_OR_REG_MEMBASE:
4024                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4025                         break;
4026                 case OP_X86_XOR_REG_MEMBASE:
4027                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4028                         break;
4029
4030                 case OP_X86_ADD_MEMBASE_IMM:
4031                         /* FIXME: Make a 64 version too */
4032                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4033                         break;
4034                 case OP_X86_SUB_MEMBASE_IMM:
4035                         g_assert (amd64_is_imm32 (ins->inst_imm));
4036                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4037                         break;
4038                 case OP_X86_AND_MEMBASE_IMM:
4039                         g_assert (amd64_is_imm32 (ins->inst_imm));
4040                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4041                         break;
4042                 case OP_X86_OR_MEMBASE_IMM:
4043                         g_assert (amd64_is_imm32 (ins->inst_imm));
4044                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4045                         break;
4046                 case OP_X86_XOR_MEMBASE_IMM:
4047                         g_assert (amd64_is_imm32 (ins->inst_imm));
4048                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4049                         break;
4050                 case OP_X86_ADD_MEMBASE_REG:
4051                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4052                         break;
4053                 case OP_X86_SUB_MEMBASE_REG:
4054                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4055                         break;
4056                 case OP_X86_AND_MEMBASE_REG:
4057                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4058                         break;
4059                 case OP_X86_OR_MEMBASE_REG:
4060                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4061                         break;
4062                 case OP_X86_XOR_MEMBASE_REG:
4063                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4064                         break;
4065                 case OP_X86_INC_MEMBASE:
4066                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4067                         break;
4068                 case OP_X86_INC_REG:
4069                         amd64_inc_reg_size (code, ins->dreg, 4);
4070                         break;
4071                 case OP_X86_DEC_MEMBASE:
4072                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4073                         break;
4074                 case OP_X86_DEC_REG:
4075                         amd64_dec_reg_size (code, ins->dreg, 4);
4076                         break;
4077                 case OP_X86_MUL_REG_MEMBASE:
4078                 case OP_X86_MUL_MEMBASE_REG:
4079                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4080                         break;
4081                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4082                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4083                         break;
4084                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4085                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4086                         break;
4087                 case OP_AMD64_COMPARE_MEMBASE_REG:
4088                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4089                         break;
4090                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4091                         g_assert (amd64_is_imm32 (ins->inst_imm));
4092                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4093                         break;
4094                 case OP_X86_COMPARE_MEMBASE8_IMM:
4095                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4096                         break;
4097                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4098                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4099                         break;
4100                 case OP_AMD64_COMPARE_REG_MEMBASE:
4101                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4102                         break;
4103
4104                 case OP_AMD64_ADD_REG_MEMBASE:
4105                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4106                         break;
4107                 case OP_AMD64_SUB_REG_MEMBASE:
4108                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4109                         break;
4110                 case OP_AMD64_AND_REG_MEMBASE:
4111                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4112                         break;
4113                 case OP_AMD64_OR_REG_MEMBASE:
4114                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4115                         break;
4116                 case OP_AMD64_XOR_REG_MEMBASE:
4117                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4118                         break;
4119
4120                 case OP_AMD64_ADD_MEMBASE_REG:
4121                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4122                         break;
4123                 case OP_AMD64_SUB_MEMBASE_REG:
4124                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4125                         break;
4126                 case OP_AMD64_AND_MEMBASE_REG:
4127                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4128                         break;
4129                 case OP_AMD64_OR_MEMBASE_REG:
4130                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4131                         break;
4132                 case OP_AMD64_XOR_MEMBASE_REG:
4133                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4134                         break;
4135
4136                 case OP_AMD64_ADD_MEMBASE_IMM:
4137                         g_assert (amd64_is_imm32 (ins->inst_imm));
4138                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4139                         break;
4140                 case OP_AMD64_SUB_MEMBASE_IMM:
4141                         g_assert (amd64_is_imm32 (ins->inst_imm));
4142                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4143                         break;
4144                 case OP_AMD64_AND_MEMBASE_IMM:
4145                         g_assert (amd64_is_imm32 (ins->inst_imm));
4146                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4147                         break;
4148                 case OP_AMD64_OR_MEMBASE_IMM:
4149                         g_assert (amd64_is_imm32 (ins->inst_imm));
4150                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4151                         break;
4152                 case OP_AMD64_XOR_MEMBASE_IMM:
4153                         g_assert (amd64_is_imm32 (ins->inst_imm));
4154                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4155                         break;
4156
4157                 case OP_BREAK:
4158                         amd64_breakpoint (code);
4159                         break;
4160                 case OP_RELAXED_NOP:
4161                         x86_prefix (code, X86_REP_PREFIX);
4162                         x86_nop (code);
4163                         break;
4164                 case OP_HARD_NOP:
4165                         x86_nop (code);
4166                         break;
4167                 case OP_NOP:
4168                 case OP_DUMMY_USE:
4169                 case OP_DUMMY_STORE:
4170                 case OP_DUMMY_ICONST:
4171                 case OP_DUMMY_R8CONST:
4172                 case OP_NOT_REACHED:
4173                 case OP_NOT_NULL:
4174                         break;
4175                 case OP_IL_SEQ_POINT:
4176                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4177                         break;
4178                 case OP_SEQ_POINT: {
4179                         int i;
4180
4181                         /*
4182                          * Read from the single stepping trigger page. This will cause a
4183                          * SIGSEGV when single stepping is enabled.
4184                          * We do this _before_ the breakpoint, so single stepping after
4185                          * a breakpoint is hit will step to the next IL offset.
4186                          */
4187                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4188                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4189
4190                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4191                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4192                         }
4193
4194                         /*
4195                          * This is the address which is saved in seq points,
4196                          */
4197                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4198
4199                         if (cfg->compile_aot) {
4200                                 guint32 offset = code - cfg->native_code;
4201                                 guint32 val;
4202                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4203
4204                                 /* Load info var */
4205                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4206                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4207                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4208                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4209                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4210                         } else {
4211                                 /*
4212                                  * A placeholder for a possible breakpoint inserted by
4213                                  * mono_arch_set_breakpoint ().
4214                                  */
4215                                 for (i = 0; i < breakpoint_size; ++i)
4216                                         x86_nop (code);
4217                         }
4218                         /*
4219                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4220                          * to another IL offset.
4221                          */
4222                         x86_nop (code);
4223                         break;
4224                 }
4225                 case OP_ADDCC:
4226                 case OP_LADDCC:
4227                 case OP_LADD:
4228                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4229                         break;
4230                 case OP_ADC:
4231                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4232                         break;
4233                 case OP_ADD_IMM:
4234                 case OP_LADD_IMM:
4235                         g_assert (amd64_is_imm32 (ins->inst_imm));
4236                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4237                         break;
4238                 case OP_ADC_IMM:
4239                         g_assert (amd64_is_imm32 (ins->inst_imm));
4240                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4241                         break;
4242                 case OP_SUBCC:
4243                 case OP_LSUBCC:
4244                 case OP_LSUB:
4245                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4246                         break;
4247                 case OP_SBB:
4248                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4249                         break;
4250                 case OP_SUB_IMM:
4251                 case OP_LSUB_IMM:
4252                         g_assert (amd64_is_imm32 (ins->inst_imm));
4253                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4254                         break;
4255                 case OP_SBB_IMM:
4256                         g_assert (amd64_is_imm32 (ins->inst_imm));
4257                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4258                         break;
4259                 case OP_LAND:
4260                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4261                         break;
4262                 case OP_AND_IMM:
4263                 case OP_LAND_IMM:
4264                         g_assert (amd64_is_imm32 (ins->inst_imm));
4265                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4266                         break;
4267                 case OP_LMUL:
4268                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4269                         break;
4270                 case OP_MUL_IMM:
4271                 case OP_LMUL_IMM:
4272                 case OP_IMUL_IMM: {
4273                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4274
4275                         switch (ins->inst_imm) {
4276                         case 2:
4277                                 /* MOV r1, r2 */
4278                                 /* ADD r1, r1 */
4279                                 if (ins->dreg != ins->sreg1)
4280                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4281                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4282                                 break;
4283                         case 3:
4284                                 /* LEA r1, [r2 + r2*2] */
4285                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4286                                 break;
4287                         case 5:
4288                                 /* LEA r1, [r2 + r2*4] */
4289                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4290                                 break;
4291                         case 6:
4292                                 /* LEA r1, [r2 + r2*2] */
4293                                 /* ADD r1, r1          */
4294                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4295                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4296                                 break;
4297                         case 9:
4298                                 /* LEA r1, [r2 + r2*8] */
4299                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4300                                 break;
4301                         case 10:
4302                                 /* LEA r1, [r2 + r2*4] */
4303                                 /* ADD r1, r1          */
4304                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4305                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4306                                 break;
4307                         case 12:
4308                                 /* LEA r1, [r2 + r2*2] */
4309                                 /* SHL r1, 2           */
4310                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4311                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4312                                 break;
4313                         case 25:
4314                                 /* LEA r1, [r2 + r2*4] */
4315                                 /* LEA r1, [r1 + r1*4] */
4316                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4317                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4318                                 break;
4319                         case 100:
4320                                 /* LEA r1, [r2 + r2*4] */
4321                                 /* SHL r1, 2           */
4322                                 /* LEA r1, [r1 + r1*4] */
4323                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4324                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4325                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4326                                 break;
4327                         default:
4328                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4329                                 break;
4330                         }
4331                         break;
4332                 }
4333                 case OP_LDIV:
4334                 case OP_LREM:
4335 #if defined( __native_client_codegen__ )
4336                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4337                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4338 #endif
4339                         /* Regalloc magic makes the div/rem cases the same */
4340                         if (ins->sreg2 == AMD64_RDX) {
4341                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4342                                 amd64_cdq (code);
4343                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4344                         } else {
4345                                 amd64_cdq (code);
4346                                 amd64_div_reg (code, ins->sreg2, TRUE);
4347                         }
4348                         break;
4349                 case OP_LDIV_UN:
4350                 case OP_LREM_UN:
4351 #if defined( __native_client_codegen__ )
4352                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4353                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4354 #endif
4355                         if (ins->sreg2 == AMD64_RDX) {
4356                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4357                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4358                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4359                         } else {
4360                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4361                                 amd64_div_reg (code, ins->sreg2, FALSE);
4362                         }
4363                         break;
4364                 case OP_IDIV:
4365                 case OP_IREM:
4366 #if defined( __native_client_codegen__ )
4367                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4368                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4369 #endif
4370                         if (ins->sreg2 == AMD64_RDX) {
4371                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4372                                 amd64_cdq_size (code, 4);
4373                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4374                         } else {
4375                                 amd64_cdq_size (code, 4);
4376                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4377                         }
4378                         break;
4379                 case OP_IDIV_UN:
4380                 case OP_IREM_UN:
4381 #if defined( __native_client_codegen__ )
4382                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4383                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4384 #endif
4385                         if (ins->sreg2 == AMD64_RDX) {
4386                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4387                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4388                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4389                         } else {
4390                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4391                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4392                         }
4393                         break;
4394                 case OP_LMUL_OVF:
4395                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4396                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4397                         break;
4398                 case OP_LOR:
4399                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4400                         break;
4401                 case OP_OR_IMM:
4402                 case OP_LOR_IMM:
4403                         g_assert (amd64_is_imm32 (ins->inst_imm));
4404                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4405                         break;
4406                 case OP_LXOR:
4407                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4408                         break;
4409                 case OP_XOR_IMM:
4410                 case OP_LXOR_IMM:
4411                         g_assert (amd64_is_imm32 (ins->inst_imm));
4412                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4413                         break;
4414                 case OP_LSHL:
4415                         g_assert (ins->sreg2 == AMD64_RCX);
4416                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4417                         break;
4418                 case OP_LSHR:
4419                         g_assert (ins->sreg2 == AMD64_RCX);
4420                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4421                         break;
4422                 case OP_SHR_IMM:
4423                         g_assert (amd64_is_imm32 (ins->inst_imm));
4424                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4425                         break;
4426                 case OP_LSHR_IMM:
4427                         g_assert (amd64_is_imm32 (ins->inst_imm));
4428                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4429                         break;
4430                 case OP_SHR_UN_IMM:
4431                         g_assert (amd64_is_imm32 (ins->inst_imm));
4432                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4433                         break;
4434                 case OP_LSHR_UN_IMM:
4435                         g_assert (amd64_is_imm32 (ins->inst_imm));
4436                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4437                         break;
4438                 case OP_LSHR_UN:
4439                         g_assert (ins->sreg2 == AMD64_RCX);
4440                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4441                         break;
4442                 case OP_SHL_IMM:
4443                         g_assert (amd64_is_imm32 (ins->inst_imm));
4444                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4445                         break;
4446                 case OP_LSHL_IMM:
4447                         g_assert (amd64_is_imm32 (ins->inst_imm));
4448                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4449                         break;
4450
4451                 case OP_IADDCC:
4452                 case OP_IADD:
4453                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4454                         break;
4455                 case OP_IADC:
4456                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4457                         break;
4458                 case OP_IADD_IMM:
4459                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4460                         break;
4461                 case OP_IADC_IMM:
4462                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4463                         break;
4464                 case OP_ISUBCC:
4465                 case OP_ISUB:
4466                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4467                         break;
4468                 case OP_ISBB:
4469                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4470                         break;
4471                 case OP_ISUB_IMM:
4472                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4473                         break;
4474                 case OP_ISBB_IMM:
4475                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4476                         break;
4477                 case OP_IAND:
4478                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4479                         break;
4480                 case OP_IAND_IMM:
4481                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4482                         break;
4483                 case OP_IOR:
4484                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4485                         break;
4486                 case OP_IOR_IMM:
4487                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4488                         break;
4489                 case OP_IXOR:
4490                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4491                         break;
4492                 case OP_IXOR_IMM:
4493                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4494                         break;
4495                 case OP_INEG:
4496                         amd64_neg_reg_size (code, ins->sreg1, 4);
4497                         break;
4498                 case OP_INOT:
4499                         amd64_not_reg_size (code, ins->sreg1, 4);
4500                         break;
4501                 case OP_ISHL:
4502                         g_assert (ins->sreg2 == AMD64_RCX);
4503                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4504                         break;
4505                 case OP_ISHR:
4506                         g_assert (ins->sreg2 == AMD64_RCX);
4507                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4508                         break;
4509                 case OP_ISHR_IMM:
4510                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4511                         break;
4512                 case OP_ISHR_UN_IMM:
4513                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4514                         break;
4515                 case OP_ISHR_UN:
4516                         g_assert (ins->sreg2 == AMD64_RCX);
4517                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4518                         break;
4519                 case OP_ISHL_IMM:
4520                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4521                         break;
4522                 case OP_IMUL:
4523                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4524                         break;
4525                 case OP_IMUL_OVF:
4526                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4527                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4528                         break;
4529                 case OP_IMUL_OVF_UN:
4530                 case OP_LMUL_OVF_UN: {
4531                         /* the mul operation and the exception check should most likely be split */
4532                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4533                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4534                         /*g_assert (ins->sreg2 == X86_EAX);
4535                         g_assert (ins->dreg == X86_EAX);*/
4536                         if (ins->sreg2 == X86_EAX) {
4537                                 non_eax_reg = ins->sreg1;
4538                         } else if (ins->sreg1 == X86_EAX) {
4539                                 non_eax_reg = ins->sreg2;
4540                         } else {
4541                                 /* no need to save since we're going to store to it anyway */
4542                                 if (ins->dreg != X86_EAX) {
4543                                         saved_eax = TRUE;
4544                                         amd64_push_reg (code, X86_EAX);
4545                                 }
4546                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4547                                 non_eax_reg = ins->sreg2;
4548                         }
4549                         if (ins->dreg == X86_EDX) {
4550                                 if (!saved_eax) {
4551                                         saved_eax = TRUE;
4552                                         amd64_push_reg (code, X86_EAX);
4553                                 }
4554                         } else {
4555                                 saved_edx = TRUE;
4556                                 amd64_push_reg (code, X86_EDX);
4557                         }
4558                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4559                         /* save before the check since pop and mov don't change the flags */
4560                         if (ins->dreg != X86_EAX)
4561                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4562                         if (saved_edx)
4563                                 amd64_pop_reg (code, X86_EDX);
4564                         if (saved_eax)
4565                                 amd64_pop_reg (code, X86_EAX);
4566                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4567                         break;
4568                 }
4569                 case OP_ICOMPARE:
4570                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4571                         break;
4572                 case OP_ICOMPARE_IMM:
4573                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4574                         break;
4575                 case OP_IBEQ:
4576                 case OP_IBLT:
4577                 case OP_IBGT:
4578                 case OP_IBGE:
4579                 case OP_IBLE:
4580                 case OP_LBEQ:
4581                 case OP_LBLT:
4582                 case OP_LBGT:
4583                 case OP_LBGE:
4584                 case OP_LBLE:
4585                 case OP_IBNE_UN:
4586                 case OP_IBLT_UN:
4587                 case OP_IBGT_UN:
4588                 case OP_IBGE_UN:
4589                 case OP_IBLE_UN:
4590                 case OP_LBNE_UN:
4591                 case OP_LBLT_UN:
4592                 case OP_LBGT_UN:
4593                 case OP_LBGE_UN:
4594                 case OP_LBLE_UN:
4595                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4596                         break;
4597
4598                 case OP_CMOV_IEQ:
4599                 case OP_CMOV_IGE:
4600                 case OP_CMOV_IGT:
4601                 case OP_CMOV_ILE:
4602                 case OP_CMOV_ILT:
4603                 case OP_CMOV_INE_UN:
4604                 case OP_CMOV_IGE_UN:
4605                 case OP_CMOV_IGT_UN:
4606                 case OP_CMOV_ILE_UN:
4607                 case OP_CMOV_ILT_UN:
4608                 case OP_CMOV_LEQ:
4609                 case OP_CMOV_LGE:
4610                 case OP_CMOV_LGT:
4611                 case OP_CMOV_LLE:
4612                 case OP_CMOV_LLT:
4613                 case OP_CMOV_LNE_UN:
4614                 case OP_CMOV_LGE_UN:
4615                 case OP_CMOV_LGT_UN:
4616                 case OP_CMOV_LLE_UN:
4617                 case OP_CMOV_LLT_UN:
4618                         g_assert (ins->dreg == ins->sreg1);
4619                         /* This needs to operate on 64 bit values */
4620                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4621                         break;
4622
4623                 case OP_LNOT:
4624                         amd64_not_reg (code, ins->sreg1);
4625                         break;
4626                 case OP_LNEG:
4627                         amd64_neg_reg (code, ins->sreg1);
4628                         break;
4629
4630                 case OP_ICONST:
4631                 case OP_I8CONST:
4632                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4633                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4634                         else
4635                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4636                         break;
4637                 case OP_AOTCONST:
4638                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4639                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4640                         break;
4641                 case OP_JUMP_TABLE:
4642                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4643                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4644                         break;
4645                 case OP_MOVE:
4646                         if (ins->dreg != ins->sreg1)
4647                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4648                         break;
4649                 case OP_AMD64_SET_XMMREG_R4: {
4650                         if (cfg->r4fp) {
4651                                 if (ins->dreg != ins->sreg1)
4652                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4653                         } else {
4654                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4655                         }
4656                         break;
4657                 }
4658                 case OP_AMD64_SET_XMMREG_R8: {
4659                         if (ins->dreg != ins->sreg1)
4660                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4661                         break;
4662                 }
4663                 case OP_TAILCALL: {
4664                         MonoCallInst *call = (MonoCallInst*)ins;
4665                         int i, save_area_offset;
4666
4667                         g_assert (!cfg->method->save_lmf);
4668
4669                         /* Restore callee saved registers */
4670                         save_area_offset = cfg->arch.reg_save_area_offset;
4671                         for (i = 0; i < AMD64_NREG; ++i)
4672                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4673                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4674                                         save_area_offset += 8;
4675                                 }
4676
4677                         if (cfg->arch.omit_fp) {
4678                                 if (cfg->arch.stack_alloc_size)
4679                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4680                                 // FIXME:
4681                                 if (call->stack_usage)
4682                                         NOT_IMPLEMENTED;
4683                         } else {
4684                                 /* Copy arguments on the stack to our argument area */
4685                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4686                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4687                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4688                                 }
4689
4690                                 amd64_leave (code);
4691                         }
4692
4693                         offset = code - cfg->native_code;
4694                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4695                         if (cfg->compile_aot)
4696                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4697                         else
4698                                 amd64_set_reg_template (code, AMD64_R11);
4699                         amd64_jump_reg (code, AMD64_R11);
4700                         ins->flags |= MONO_INST_GC_CALLSITE;
4701                         ins->backend.pc_offset = code - cfg->native_code;
4702                         break;
4703                 }
4704                 case OP_CHECK_THIS:
4705                         /* ensure ins->sreg1 is not NULL */
4706                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4707                         break;
4708                 case OP_ARGLIST: {
4709                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4710                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4711                         break;
4712                 }
4713                 case OP_CALL:
4714                 case OP_FCALL:
4715                 case OP_RCALL:
4716                 case OP_LCALL:
4717                 case OP_VCALL:
4718                 case OP_VCALL2:
4719                 case OP_VOIDCALL:
4720                         call = (MonoCallInst*)ins;
4721                         /*
4722                          * The AMD64 ABI forces callers to know about varargs.
4723                          */
4724                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4725                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4726                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4727                                 /*
4728                                  * Since the unmanaged calling convention doesn't contain a
4729                                  * 'vararg' entry, we have to treat every pinvoke call as a
4730                                  * potential vararg call.
4731                                  */
4732                                 guint32 nregs, i;
4733                                 nregs = 0;
4734                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4735                                         if (call->used_fregs & (1 << i))
4736                                                 nregs ++;
4737                                 if (!nregs)
4738                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4739                                 else
4740                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4741                         }
4742
4743                         if (ins->flags & MONO_INST_HAS_METHOD)
4744                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4745                         else
4746                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4747                         ins->flags |= MONO_INST_GC_CALLSITE;
4748                         ins->backend.pc_offset = code - cfg->native_code;
4749                         code = emit_move_return_value (cfg, ins, code);
4750                         break;
4751                 case OP_FCALL_REG:
4752                 case OP_RCALL_REG:
4753                 case OP_LCALL_REG:
4754                 case OP_VCALL_REG:
4755                 case OP_VCALL2_REG:
4756                 case OP_VOIDCALL_REG:
4757                 case OP_CALL_REG:
4758                         call = (MonoCallInst*)ins;
4759
4760                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4761                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4762                                 ins->sreg1 = AMD64_R11;
4763                         }
4764
4765                         /*
4766                          * The AMD64 ABI forces callers to know about varargs.
4767                          */
4768                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4769                                 if (ins->sreg1 == AMD64_RAX) {
4770                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4771                                         ins->sreg1 = AMD64_R11;
4772                                 }
4773                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4774                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4775                                 /*
4776                                  * Since the unmanaged calling convention doesn't contain a
4777                                  * 'vararg' entry, we have to treat every pinvoke call as a
4778                                  * potential vararg call.
4779                                  */
4780                                 guint32 nregs, i;
4781                                 nregs = 0;
4782                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4783                                         if (call->used_fregs & (1 << i))
4784                                                 nregs ++;
4785                                 if (ins->sreg1 == AMD64_RAX) {
4786                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4787                                         ins->sreg1 = AMD64_R11;
4788                                 }
4789                                 if (!nregs)
4790                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4791                                 else
4792                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4793                         }
4794
4795                         amd64_call_reg (code, ins->sreg1);
4796                         ins->flags |= MONO_INST_GC_CALLSITE;
4797                         ins->backend.pc_offset = code - cfg->native_code;
4798                         code = emit_move_return_value (cfg, ins, code);
4799                         break;
4800                 case OP_FCALL_MEMBASE:
4801                 case OP_RCALL_MEMBASE:
4802                 case OP_LCALL_MEMBASE:
4803                 case OP_VCALL_MEMBASE:
4804                 case OP_VCALL2_MEMBASE:
4805                 case OP_VOIDCALL_MEMBASE:
4806                 case OP_CALL_MEMBASE:
4807                         call = (MonoCallInst*)ins;
4808
4809                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4810                         ins->flags |= MONO_INST_GC_CALLSITE;
4811                         ins->backend.pc_offset = code - cfg->native_code;
4812                         code = emit_move_return_value (cfg, ins, code);
4813                         break;
4814                 case OP_DYN_CALL: {
4815                         int i;
4816                         MonoInst *var = cfg->dyn_call_var;
4817
4818                         g_assert (var->opcode == OP_REGOFFSET);
4819
4820                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4821                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4822                         /* r10 = ftn */
4823                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4824
4825                         /* Save args buffer */
4826                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4827
4828                         /* Set argument registers */
4829                         for (i = 0; i < PARAM_REGS; ++i)
4830                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4831
4832                         /* Make the call */
4833                         amd64_call_reg (code, AMD64_R10);
4834
4835                         ins->flags |= MONO_INST_GC_CALLSITE;
4836                         ins->backend.pc_offset = code - cfg->native_code;
4837
4838                         /* Save result */
4839                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4840                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4841                         break;
4842                 }
4843                 case OP_AMD64_SAVE_SP_TO_LMF: {
4844                         MonoInst *lmf_var = cfg->lmf_var;
4845                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4846                         break;
4847                 }
4848                 case OP_X86_PUSH:
4849                         g_assert_not_reached ();
4850                         amd64_push_reg (code, ins->sreg1);
4851                         break;
4852                 case OP_X86_PUSH_IMM:
4853                         g_assert_not_reached ();
4854                         g_assert (amd64_is_imm32 (ins->inst_imm));
4855                         amd64_push_imm (code, ins->inst_imm);
4856                         break;
4857                 case OP_X86_PUSH_MEMBASE:
4858                         g_assert_not_reached ();
4859                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4860                         break;
4861                 case OP_X86_PUSH_OBJ: {
4862                         int size = ALIGN_TO (ins->inst_imm, 8);
4863
4864                         g_assert_not_reached ();
4865
4866                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4867                         amd64_push_reg (code, AMD64_RDI);
4868                         amd64_push_reg (code, AMD64_RSI);
4869                         amd64_push_reg (code, AMD64_RCX);
4870                         if (ins->inst_offset)
4871                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4872                         else
4873                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4874                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4875                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4876                         amd64_cld (code);
4877                         amd64_prefix (code, X86_REP_PREFIX);
4878                         amd64_movsd (code);
4879                         amd64_pop_reg (code, AMD64_RCX);
4880                         amd64_pop_reg (code, AMD64_RSI);
4881                         amd64_pop_reg (code, AMD64_RDI);
4882                         break;
4883                 }
4884                 case OP_X86_LEA:
4885                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4886                         break;
4887                 case OP_X86_LEA_MEMBASE:
4888                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4889                         break;
4890                 case OP_X86_XCHG:
4891                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4892                         break;
4893                 case OP_LOCALLOC:
4894                         /* keep alignment */
4895                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4896                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4897                         code = mono_emit_stack_alloc (cfg, code, ins);
4898                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4899                         if (cfg->param_area)
4900                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4901                         break;
4902                 case OP_LOCALLOC_IMM: {
4903                         guint32 size = ins->inst_imm;
4904                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4905
4906                         if (ins->flags & MONO_INST_INIT) {
4907                                 if (size < 64) {
4908                                         int i;
4909
4910                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4911                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4912
4913                                         for (i = 0; i < size; i += 8)
4914                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4915                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4916                                 } else {
4917                                         amd64_mov_reg_imm (code, ins->dreg, size);
4918                                         ins->sreg1 = ins->dreg;
4919
4920                                         code = mono_emit_stack_alloc (cfg, code, ins);
4921                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4922                                 }
4923                         } else {
4924                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4925                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4926                         }
4927                         if (cfg->param_area)
4928                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4929                         break;
4930                 }
4931                 case OP_THROW: {
4932                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4933                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4934                                              (gpointer)"mono_arch_throw_exception", FALSE);
4935                         ins->flags |= MONO_INST_GC_CALLSITE;
4936                         ins->backend.pc_offset = code - cfg->native_code;
4937                         break;
4938                 }
4939                 case OP_RETHROW: {
4940                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4941                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4942                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4943                         ins->flags |= MONO_INST_GC_CALLSITE;
4944                         ins->backend.pc_offset = code - cfg->native_code;
4945                         break;
4946                 }
4947                 case OP_CALL_HANDLER:
4948                         /* Align stack */
4949                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4950                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4951                         amd64_call_imm (code, 0);
4952                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4953                         /* Restore stack alignment */
4954                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4955                         break;
4956                 case OP_START_HANDLER: {
4957                         /* Even though we're saving RSP, use sizeof */
4958                         /* gpointer because spvar is of type IntPtr */
4959                         /* see: mono_create_spvar_for_region */
4960                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4961                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4962
4963                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4964                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4965                                 cfg->param_area) {
4966                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4967                         }
4968                         break;
4969                 }
4970                 case OP_ENDFINALLY: {
4971                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4972                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4973                         amd64_ret (code);
4974                         break;
4975                 }
4976                 case OP_ENDFILTER: {
4977                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4978                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4979                         /* The local allocator will put the result into RAX */
4980                         amd64_ret (code);
4981                         break;
4982                 }
4983
4984                 case OP_LABEL:
4985                         ins->inst_c0 = code - cfg->native_code;
4986                         break;
4987                 case OP_BR:
4988                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4989                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4990                         //break;
4991                                 if (ins->inst_target_bb->native_offset) {
4992                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4993                                 } else {
4994                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4995                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4996                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4997                                                 x86_jump8 (code, 0);
4998                                         else
4999                                                 x86_jump32 (code, 0);
5000                         }
5001                         break;
5002                 case OP_BR_REG:
5003                         amd64_jump_reg (code, ins->sreg1);
5004                         break;
5005                 case OP_ICNEQ:
5006                 case OP_ICGE:
5007                 case OP_ICLE:
5008                 case OP_ICGE_UN:
5009                 case OP_ICLE_UN:
5010
5011                 case OP_CEQ:
5012                 case OP_LCEQ:
5013                 case OP_ICEQ:
5014                 case OP_CLT:
5015                 case OP_LCLT:
5016                 case OP_ICLT:
5017                 case OP_CGT:
5018                 case OP_ICGT:
5019                 case OP_LCGT:
5020                 case OP_CLT_UN:
5021                 case OP_LCLT_UN:
5022                 case OP_ICLT_UN:
5023                 case OP_CGT_UN:
5024                 case OP_LCGT_UN:
5025                 case OP_ICGT_UN:
5026                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5027                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5028                         break;
5029                 case OP_COND_EXC_EQ:
5030                 case OP_COND_EXC_NE_UN:
5031                 case OP_COND_EXC_LT:
5032                 case OP_COND_EXC_LT_UN:
5033                 case OP_COND_EXC_GT:
5034                 case OP_COND_EXC_GT_UN:
5035                 case OP_COND_EXC_GE:
5036                 case OP_COND_EXC_GE_UN:
5037                 case OP_COND_EXC_LE:
5038                 case OP_COND_EXC_LE_UN:
5039                 case OP_COND_EXC_IEQ:
5040                 case OP_COND_EXC_INE_UN:
5041                 case OP_COND_EXC_ILT:
5042                 case OP_COND_EXC_ILT_UN:
5043                 case OP_COND_EXC_IGT:
5044                 case OP_COND_EXC_IGT_UN:
5045                 case OP_COND_EXC_IGE:
5046                 case OP_COND_EXC_IGE_UN:
5047                 case OP_COND_EXC_ILE:
5048                 case OP_COND_EXC_ILE_UN:
5049                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5050                         break;
5051                 case OP_COND_EXC_OV:
5052                 case OP_COND_EXC_NO:
5053                 case OP_COND_EXC_C:
5054                 case OP_COND_EXC_NC:
5055                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5056                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5057                         break;
5058                 case OP_COND_EXC_IOV:
5059                 case OP_COND_EXC_INO:
5060                 case OP_COND_EXC_IC:
5061                 case OP_COND_EXC_INC:
5062                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5063                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5064                         break;
5065
5066                 /* floating point opcodes */
5067                 case OP_R8CONST: {
5068                         double d = *(double *)ins->inst_p0;
5069
5070                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5071                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5072                         }
5073                         else {
5074                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5075                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5076                         }
5077                         break;
5078                 }
5079                 case OP_R4CONST: {
5080                         float f = *(float *)ins->inst_p0;
5081
5082                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5083                                 if (cfg->r4fp)
5084                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5085                                 else
5086                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5087                         }
5088                         else {
5089                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5090                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5091                                 if (!cfg->r4fp)
5092                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5093                         }
5094                         break;
5095                 }
5096                 case OP_STORER8_MEMBASE_REG:
5097                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5098                         break;
5099                 case OP_LOADR8_MEMBASE:
5100                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5101                         break;
5102                 case OP_STORER4_MEMBASE_REG:
5103                         if (cfg->r4fp) {
5104                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5105                         } else {
5106                                 /* This requires a double->single conversion */
5107                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5108                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5109                         }
5110                         break;
5111                 case OP_LOADR4_MEMBASE:
5112                         if (cfg->r4fp) {
5113                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5114                         } else {
5115                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5116                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5117                         }
5118                         break;
5119                 case OP_ICONV_TO_R4:
5120                         if (cfg->r4fp) {
5121                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5122                         } else {
5123                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5124                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5125                         }
5126                         break;
5127                 case OP_ICONV_TO_R8:
5128                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5129                         break;
5130                 case OP_LCONV_TO_R4:
5131                         if (cfg->r4fp) {
5132                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5133                         } else {
5134                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5135                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5136                         }
5137                         break;
5138                 case OP_LCONV_TO_R8:
5139                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5140                         break;
5141                 case OP_FCONV_TO_R4:
5142                         if (cfg->r4fp) {
5143                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5144                         } else {
5145                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5146                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5147                         }
5148                         break;
5149                 case OP_FCONV_TO_I1:
5150                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5151                         break;
5152                 case OP_FCONV_TO_U1:
5153                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5154                         break;
5155                 case OP_FCONV_TO_I2:
5156                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5157                         break;
5158                 case OP_FCONV_TO_U2:
5159                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5160                         break;
5161                 case OP_FCONV_TO_U4:
5162                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5163                         break;
5164                 case OP_FCONV_TO_I4:
5165                 case OP_FCONV_TO_I:
5166                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5167                         break;
5168                 case OP_FCONV_TO_I8:
5169                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5170                         break;
5171
5172                 case OP_RCONV_TO_I1:
5173                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5174                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5175                         break;
5176                 case OP_RCONV_TO_U1:
5177                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5178                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5179                         break;
5180                 case OP_RCONV_TO_I2:
5181                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5182                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5183                         break;
5184                 case OP_RCONV_TO_U2:
5185                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5186                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5187                         break;
5188                 case OP_RCONV_TO_I4:
5189                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5190                         break;
5191                 case OP_RCONV_TO_U4:
5192                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5193                         break;
5194                 case OP_RCONV_TO_I8:
5195                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5196                         break;
5197                 case OP_RCONV_TO_R8:
5198                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5199                         break;
5200                 case OP_RCONV_TO_R4:
5201                         if (ins->dreg != ins->sreg1)
5202                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5203                         break;
5204
5205                 case OP_LCONV_TO_R_UN: {
5206                         guint8 *br [2];
5207
5208                         /* Based on gcc code */
5209                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5210                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5211
5212                         /* Positive case */
5213                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5214                         br [1] = code; x86_jump8 (code, 0);
5215                         amd64_patch (br [0], code);
5216
5217                         /* Negative case */
5218                         /* Save to the red zone */
5219                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5220                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5221                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5222                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5223                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5224                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5225                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5226                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5227                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5228                         /* Restore */
5229                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5230                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5231                         amd64_patch (br [1], code);
5232                         break;
5233                 }
5234                 case OP_LCONV_TO_OVF_U4:
5235                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5236                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5237                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5238                         break;
5239                 case OP_LCONV_TO_OVF_I4_UN:
5240                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5241                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5242                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5243                         break;
5244                 case OP_FMOVE:
5245                         if (ins->dreg != ins->sreg1)
5246                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5247                         break;
5248                 case OP_RMOVE:
5249                         if (ins->dreg != ins->sreg1)
5250                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5251                         break;
5252                 case OP_MOVE_F_TO_I4:
5253                         if (cfg->r4fp) {
5254                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5255                         } else {
5256                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5257                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5258                         }
5259                         break;
5260                 case OP_MOVE_I4_TO_F:
5261                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5262                         if (!cfg->r4fp)
5263                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5264                         break;
5265                 case OP_MOVE_F_TO_I8:
5266                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5267                         break;
5268                 case OP_MOVE_I8_TO_F:
5269                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5270                         break;
5271                 case OP_FADD:
5272                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5273                         break;
5274                 case OP_FSUB:
5275                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5276                         break;
5277                 case OP_FMUL:
5278                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5279                         break;
5280                 case OP_FDIV:
5281                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5282                         break;
5283                 case OP_FNEG: {
5284                         static double r8_0 = -0.0;
5285
5286                         g_assert (ins->sreg1 == ins->dreg);
5287
5288                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5289                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5290                         break;
5291                 }
5292                 case OP_SIN:
5293                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5294                         break;
5295                 case OP_COS:
5296                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5297                         break;
5298                 case OP_ABS: {
5299                         static guint64 d = 0x7fffffffffffffffUL;
5300
5301                         g_assert (ins->sreg1 == ins->dreg);
5302
5303                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5304                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5305                         break;
5306                 }
5307                 case OP_SQRT:
5308                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5309                         break;
5310
5311                 case OP_RADD:
5312                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5313                         break;
5314                 case OP_RSUB:
5315                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5316                         break;
5317                 case OP_RMUL:
5318                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5319                         break;
5320                 case OP_RDIV:
5321                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5322                         break;
5323                 case OP_RNEG: {
5324                         static float r4_0 = -0.0;
5325
5326                         g_assert (ins->sreg1 == ins->dreg);
5327
5328                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5329                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5330                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5331                         break;
5332                 }
5333
5334                 case OP_IMIN:
5335                         g_assert (cfg->opt & MONO_OPT_CMOV);
5336                         g_assert (ins->dreg == ins->sreg1);
5337                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5338                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5339                         break;
5340                 case OP_IMIN_UN:
5341                         g_assert (cfg->opt & MONO_OPT_CMOV);
5342                         g_assert (ins->dreg == ins->sreg1);
5343                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5344                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5345                         break;
5346                 case OP_IMAX:
5347                         g_assert (cfg->opt & MONO_OPT_CMOV);
5348                         g_assert (ins->dreg == ins->sreg1);
5349                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5350                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5351                         break;
5352                 case OP_IMAX_UN:
5353                         g_assert (cfg->opt & MONO_OPT_CMOV);
5354                         g_assert (ins->dreg == ins->sreg1);
5355                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5356                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5357                         break;
5358                 case OP_LMIN:
5359                         g_assert (cfg->opt & MONO_OPT_CMOV);
5360                         g_assert (ins->dreg == ins->sreg1);
5361                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5362                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5363                         break;
5364                 case OP_LMIN_UN:
5365                         g_assert (cfg->opt & MONO_OPT_CMOV);
5366                         g_assert (ins->dreg == ins->sreg1);
5367                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5368                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5369                         break;
5370                 case OP_LMAX:
5371                         g_assert (cfg->opt & MONO_OPT_CMOV);
5372                         g_assert (ins->dreg == ins->sreg1);
5373                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5374                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5375                         break;
5376                 case OP_LMAX_UN:
5377                         g_assert (cfg->opt & MONO_OPT_CMOV);
5378                         g_assert (ins->dreg == ins->sreg1);
5379                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5380                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5381                         break;
5382                 case OP_X86_FPOP:
5383                         break;
5384                 case OP_FCOMPARE:
5385                         /*
5386                          * The two arguments are swapped because the fbranch instructions
5387                          * depend on this for the non-sse case to work.
5388                          */
5389                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5390                         break;
5391                 case OP_RCOMPARE:
5392                         /*
5393                          * FIXME: Get rid of this.
5394                          * The two arguments are swapped because the fbranch instructions
5395                          * depend on this for the non-sse case to work.
5396                          */
5397                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5398                         break;
5399                 case OP_FCNEQ:
5400                 case OP_FCEQ: {
5401                         /* zeroing the register at the start results in
5402                          * shorter and faster code (we can also remove the widening op)
5403                          */
5404                         guchar *unordered_check;
5405
5406                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5407                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5408                         unordered_check = code;
5409                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5410
5411                         if (ins->opcode == OP_FCEQ) {
5412                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5413                                 amd64_patch (unordered_check, code);
5414                         } else {
5415                                 guchar *jump_to_end;
5416                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5417                                 jump_to_end = code;
5418                                 x86_jump8 (code, 0);
5419                                 amd64_patch (unordered_check, code);
5420                                 amd64_inc_reg (code, ins->dreg);
5421                                 amd64_patch (jump_to_end, code);
5422                         }
5423                         break;
5424                 }
5425                 case OP_FCLT:
5426                 case OP_FCLT_UN: {
5427                         /* zeroing the register at the start results in
5428                          * shorter and faster code (we can also remove the widening op)
5429                          */
5430                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5431                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5432                         if (ins->opcode == OP_FCLT_UN) {
5433                                 guchar *unordered_check = code;
5434                                 guchar *jump_to_end;
5435                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5436                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5437                                 jump_to_end = code;
5438                                 x86_jump8 (code, 0);
5439                                 amd64_patch (unordered_check, code);
5440                                 amd64_inc_reg (code, ins->dreg);
5441                                 amd64_patch (jump_to_end, code);
5442                         } else {
5443                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5444                         }
5445                         break;
5446                 }
5447                 case OP_FCLE: {
5448                         guchar *unordered_check;
5449                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5450                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5451                         unordered_check = code;
5452                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5453                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5454                         amd64_patch (unordered_check, code);
5455                         break;
5456                 }
5457                 case OP_FCGT:
5458                 case OP_FCGT_UN: {
5459                         /* zeroing the register at the start results in
5460                          * shorter and faster code (we can also remove the widening op)
5461                          */
5462                         guchar *unordered_check;
5463
5464                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5465                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5466                         if (ins->opcode == OP_FCGT) {
5467                                 unordered_check = code;
5468                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5469                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5470                                 amd64_patch (unordered_check, code);
5471                         } else {
5472                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5473                         }
5474                         break;
5475                 }
5476                 case OP_FCGE: {
5477                         guchar *unordered_check;
5478                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5479                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5480                         unordered_check = code;
5481                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5482                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5483                         amd64_patch (unordered_check, code);
5484                         break;
5485                 }
5486
5487                 case OP_RCEQ:
5488                 case OP_RCGT:
5489                 case OP_RCLT:
5490                 case OP_RCLT_UN:
5491                 case OP_RCGT_UN: {
5492                         int x86_cond;
5493                         gboolean unordered = FALSE;
5494
5495                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5496                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5497
5498                         switch (ins->opcode) {
5499                         case OP_RCEQ:
5500                                 x86_cond = X86_CC_EQ;
5501                                 break;
5502                         case OP_RCGT:
5503                                 x86_cond = X86_CC_LT;
5504                                 break;
5505                         case OP_RCLT:
5506                                 x86_cond = X86_CC_GT;
5507                                 break;
5508                         case OP_RCLT_UN:
5509                                 x86_cond = X86_CC_GT;
5510                                 unordered = TRUE;
5511                                 break;
5512                         case OP_RCGT_UN:
5513                                 x86_cond = X86_CC_LT;
5514                                 unordered = TRUE;
5515                                 break;
5516                         default:
5517                                 g_assert_not_reached ();
5518                                 break;
5519                         }
5520
5521                         if (unordered) {
5522                                 guchar *unordered_check;
5523                                 guchar *jump_to_end;
5524
5525                                 unordered_check = code;
5526                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5527                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5528                                 jump_to_end = code;
5529                                 x86_jump8 (code, 0);
5530                                 amd64_patch (unordered_check, code);
5531                                 amd64_inc_reg (code, ins->dreg);
5532                                 amd64_patch (jump_to_end, code);
5533                         } else {
5534                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5535                         }
5536                         break;
5537                 }
5538                 case OP_FCLT_MEMBASE:
5539                 case OP_FCGT_MEMBASE:
5540                 case OP_FCLT_UN_MEMBASE:
5541                 case OP_FCGT_UN_MEMBASE:
5542                 case OP_FCEQ_MEMBASE: {
5543                         guchar *unordered_check, *jump_to_end;
5544                         int x86_cond;
5545
5546                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5547                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5548
5549                         switch (ins->opcode) {
5550                         case OP_FCEQ_MEMBASE:
5551                                 x86_cond = X86_CC_EQ;
5552                                 break;
5553                         case OP_FCLT_MEMBASE:
5554                         case OP_FCLT_UN_MEMBASE:
5555                                 x86_cond = X86_CC_LT;
5556                                 break;
5557                         case OP_FCGT_MEMBASE:
5558                         case OP_FCGT_UN_MEMBASE:
5559                                 x86_cond = X86_CC_GT;
5560                                 break;
5561                         default:
5562                                 g_assert_not_reached ();
5563                         }
5564
5565                         unordered_check = code;
5566                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5567                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5568
5569                         switch (ins->opcode) {
5570                         case OP_FCEQ_MEMBASE:
5571                         case OP_FCLT_MEMBASE:
5572                         case OP_FCGT_MEMBASE:
5573                                 amd64_patch (unordered_check, code);
5574                                 break;
5575                         case OP_FCLT_UN_MEMBASE:
5576                         case OP_FCGT_UN_MEMBASE:
5577                                 jump_to_end = code;
5578                                 x86_jump8 (code, 0);
5579                                 amd64_patch (unordered_check, code);
5580                                 amd64_inc_reg (code, ins->dreg);
5581                                 amd64_patch (jump_to_end, code);
5582                                 break;
5583                         default:
5584                                 break;
5585                         }
5586                         break;
5587                 }
5588                 case OP_FBEQ: {
5589                         guchar *jump = code;
5590                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5591                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5592                         amd64_patch (jump, code);
5593                         break;
5594                 }
5595                 case OP_FBNE_UN:
5596                         /* Branch if C013 != 100 */
5597                         /* branch if !ZF or (PF|CF) */
5598                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5599                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5600                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5601                         break;
5602                 case OP_FBLT:
5603                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5604                         break;
5605                 case OP_FBLT_UN:
5606                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5607                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5608                         break;
5609                 case OP_FBGT:
5610                 case OP_FBGT_UN:
5611                         if (ins->opcode == OP_FBGT) {
5612                                 guchar *br1;
5613
5614                                 /* skip branch if C1=1 */
5615                                 br1 = code;
5616                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5617                                 /* branch if (C0 | C3) = 1 */
5618                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5619                                 amd64_patch (br1, code);
5620                                 break;
5621                         } else {
5622                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5623                         }
5624                         break;
5625                 case OP_FBGE: {
5626                         /* Branch if C013 == 100 or 001 */
5627                         guchar *br1;
5628
5629                         /* skip branch if C1=1 */
5630                         br1 = code;
5631                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5632                         /* branch if (C0 | C3) = 1 */
5633                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5634                         amd64_patch (br1, code);
5635                         break;
5636                 }
5637                 case OP_FBGE_UN:
5638                         /* Branch if C013 == 000 */
5639                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5640                         break;
5641                 case OP_FBLE: {
5642                         /* Branch if C013=000 or 100 */
5643                         guchar *br1;
5644
5645                         /* skip branch if C1=1 */
5646                         br1 = code;
5647                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5648                         /* branch if C0=0 */
5649                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5650                         amd64_patch (br1, code);
5651                         break;
5652                 }
5653                 case OP_FBLE_UN:
5654                         /* Branch if C013 != 001 */
5655                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5656                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5657                         break;
5658                 case OP_CKFINITE:
5659                         /* Transfer value to the fp stack */
5660                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5661                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5662                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5663
5664                         amd64_push_reg (code, AMD64_RAX);
5665                         amd64_fxam (code);
5666                         amd64_fnstsw (code);
5667                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5668                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5669                         amd64_pop_reg (code, AMD64_RAX);
5670                         amd64_fstp (code, 0);
5671                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5672                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5673                         break;
5674                 case OP_TLS_GET: {
5675                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5676                         break;
5677                 }
5678                 case OP_TLS_GET_REG:
5679                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5680                         break;
5681                 case OP_TLS_SET: {
5682                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5683                         break;
5684                 }
5685                 case OP_TLS_SET_REG: {
5686                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5687                         break;
5688                 }
5689                 case OP_MEMORY_BARRIER: {
5690                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5691                                 x86_mfence (code);
5692                         break;
5693                 }
5694                 case OP_ATOMIC_ADD_I4:
5695                 case OP_ATOMIC_ADD_I8: {
5696                         int dreg = ins->dreg;
5697                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5698
5699                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5700                                 dreg = AMD64_R11;
5701
5702                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5703                         amd64_prefix (code, X86_LOCK_PREFIX);
5704                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5705                         /* dreg contains the old value, add with sreg2 value */
5706                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5707
5708                         if (ins->dreg != dreg)
5709                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5710
5711                         break;
5712                 }
5713                 case OP_ATOMIC_EXCHANGE_I4:
5714                 case OP_ATOMIC_EXCHANGE_I8: {
5715                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5716
5717                         /* LOCK prefix is implied. */
5718                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5719                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5720                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5721                         break;
5722                 }
5723                 case OP_ATOMIC_CAS_I4:
5724                 case OP_ATOMIC_CAS_I8: {
5725                         guint32 size;
5726
5727                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5728                                 size = 8;
5729                         else
5730                                 size = 4;
5731
5732                         /*
5733                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5734                          * an explanation of how this works.
5735                          */
5736                         g_assert (ins->sreg3 == AMD64_RAX);
5737                         g_assert (ins->sreg1 != AMD64_RAX);
5738                         g_assert (ins->sreg1 != ins->sreg2);
5739
5740                         amd64_prefix (code, X86_LOCK_PREFIX);
5741                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5742
5743                         if (ins->dreg != AMD64_RAX)
5744                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5745                         break;
5746                 }
5747                 case OP_ATOMIC_LOAD_I1: {
5748                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5749                         break;
5750                 }
5751                 case OP_ATOMIC_LOAD_U1: {
5752                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5753                         break;
5754                 }
5755                 case OP_ATOMIC_LOAD_I2: {
5756                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5757                         break;
5758                 }
5759                 case OP_ATOMIC_LOAD_U2: {
5760                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5761                         break;
5762                 }
5763                 case OP_ATOMIC_LOAD_I4: {
5764                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5765                         break;
5766                 }
5767                 case OP_ATOMIC_LOAD_U4:
5768                 case OP_ATOMIC_LOAD_I8:
5769                 case OP_ATOMIC_LOAD_U8: {
5770                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5771                         break;
5772                 }
5773                 case OP_ATOMIC_LOAD_R4: {
5774                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5775                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5776                         break;
5777                 }
5778                 case OP_ATOMIC_LOAD_R8: {
5779                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5780                         break;
5781                 }
5782                 case OP_ATOMIC_STORE_I1:
5783                 case OP_ATOMIC_STORE_U1:
5784                 case OP_ATOMIC_STORE_I2:
5785                 case OP_ATOMIC_STORE_U2:
5786                 case OP_ATOMIC_STORE_I4:
5787                 case OP_ATOMIC_STORE_U4:
5788                 case OP_ATOMIC_STORE_I8:
5789                 case OP_ATOMIC_STORE_U8: {
5790                         int size;
5791
5792                         switch (ins->opcode) {
5793                         case OP_ATOMIC_STORE_I1:
5794                         case OP_ATOMIC_STORE_U1:
5795                                 size = 1;
5796                                 break;
5797                         case OP_ATOMIC_STORE_I2:
5798                         case OP_ATOMIC_STORE_U2:
5799                                 size = 2;
5800                                 break;
5801                         case OP_ATOMIC_STORE_I4:
5802                         case OP_ATOMIC_STORE_U4:
5803                                 size = 4;
5804                                 break;
5805                         case OP_ATOMIC_STORE_I8:
5806                         case OP_ATOMIC_STORE_U8:
5807                                 size = 8;
5808                                 break;
5809                         }
5810
5811                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5812
5813                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5814                                 x86_mfence (code);
5815                         break;
5816                 }
5817                 case OP_ATOMIC_STORE_R4: {
5818                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5819                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5820
5821                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5822                                 x86_mfence (code);
5823                         break;
5824                 }
5825                 case OP_ATOMIC_STORE_R8: {
5826                         x86_nop (code);
5827                         x86_nop (code);
5828                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5829                         x86_nop (code);
5830                         x86_nop (code);
5831
5832                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5833                                 x86_mfence (code);
5834                         break;
5835                 }
5836                 case OP_CARD_TABLE_WBARRIER: {
5837                         int ptr = ins->sreg1;
5838                         int value = ins->sreg2;
5839                         guchar *br = 0;
5840                         int nursery_shift, card_table_shift;
5841                         gpointer card_table_mask;
5842                         size_t nursery_size;
5843
5844                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5845                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5846                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5847
5848                         /*If either point to the stack we can simply avoid the WB. This happens due to
5849                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5850                          */
5851                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5852                                 continue;
5853
5854                         /*
5855                          * We need one register we can clobber, we choose EDX and make sreg1
5856                          * fixed EAX to work around limitations in the local register allocator.
5857                          * sreg2 might get allocated to EDX, but that is not a problem since
5858                          * we use it before clobbering EDX.
5859                          */
5860                         g_assert (ins->sreg1 == AMD64_RAX);
5861
5862                         /*
5863                          * This is the code we produce:
5864                          *
5865                          *   edx = value
5866                          *   edx >>= nursery_shift
5867                          *   cmp edx, (nursery_start >> nursery_shift)
5868                          *   jne done
5869                          *   edx = ptr
5870                          *   edx >>= card_table_shift
5871                          *   edx += cardtable
5872                          *   [edx] = 1
5873                          * done:
5874                          */
5875
5876                         if (mono_gc_card_table_nursery_check ()) {
5877                                 if (value != AMD64_RDX)
5878                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5879                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5880                                 if (shifted_nursery_start >> 31) {
5881                                         /*
5882                                          * The value we need to compare against is 64 bits, so we need
5883                                          * another spare register.  We use RBX, which we save and
5884                                          * restore.
5885                                          */
5886                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5887                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5888                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5889                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5890                                 } else {
5891                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5892                                 }
5893                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5894                         }
5895                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5896                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5897                         if (card_table_mask)
5898                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5899
5900                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5901                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5902
5903                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5904
5905                         if (mono_gc_card_table_nursery_check ())
5906                                 x86_patch (br, code);
5907                         break;
5908                 }
5909 #ifdef MONO_ARCH_SIMD_INTRINSICS
5910                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5911                 case OP_ADDPS:
5912                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5913                         break;
5914                 case OP_DIVPS:
5915                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5916                         break;
5917                 case OP_MULPS:
5918                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_SUBPS:
5921                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923                 case OP_MAXPS:
5924                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_MINPS:
5927                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929                 case OP_COMPPS:
5930                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5931                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5932                         break;
5933                 case OP_ANDPS:
5934                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936                 case OP_ANDNPS:
5937                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_ORPS:
5940                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942                 case OP_XORPS:
5943                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5944                         break;
5945                 case OP_SQRTPS:
5946                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5947                         break;
5948                 case OP_RSQRTPS:
5949                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5950                         break;
5951                 case OP_RCPPS:
5952                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5953                         break;
5954                 case OP_ADDSUBPS:
5955                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5956                         break;
5957                 case OP_HADDPS:
5958                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5959                         break;
5960                 case OP_HSUBPS:
5961                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5962                         break;
5963                 case OP_DUPPS_HIGH:
5964                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5965                         break;
5966                 case OP_DUPPS_LOW:
5967                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5968                         break;
5969
5970                 case OP_PSHUFLEW_HIGH:
5971                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5972                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5973                         break;
5974                 case OP_PSHUFLEW_LOW:
5975                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5976                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5977                         break;
5978                 case OP_PSHUFLED:
5979                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5980                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5981                         break;
5982                 case OP_SHUFPS:
5983                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5984                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5985                         break;
5986                 case OP_SHUFPD:
5987                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5988                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5989                         break;
5990
5991                 case OP_ADDPD:
5992                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5993                         break;
5994                 case OP_DIVPD:
5995                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5996                         break;
5997                 case OP_MULPD:
5998                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5999                         break;
6000                 case OP_SUBPD:
6001                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6002                         break;
6003                 case OP_MAXPD:
6004                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6005                         break;
6006                 case OP_MINPD:
6007                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009                 case OP_COMPPD:
6010                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6011                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6012                         break;
6013                 case OP_ANDPD:
6014                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6015                         break;
6016                 case OP_ANDNPD:
6017                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6018                         break;
6019                 case OP_ORPD:
6020                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6021                         break;
6022                 case OP_XORPD:
6023                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025                 case OP_SQRTPD:
6026                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6027                         break;
6028                 case OP_ADDSUBPD:
6029                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6030                         break;
6031                 case OP_HADDPD:
6032                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_HSUBPD:
6035                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_DUPPD:
6038                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6039                         break;
6040
6041                 case OP_EXTRACT_MASK:
6042                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6043                         break;
6044
6045                 case OP_PAND:
6046                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6047                         break;
6048                 case OP_POR:
6049                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051                 case OP_PXOR:
6052                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054
6055                 case OP_PADDB:
6056                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6057                         break;
6058                 case OP_PADDW:
6059                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6060                         break;
6061                 case OP_PADDD:
6062                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6063                         break;
6064                 case OP_PADDQ:
6065                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067
6068                 case OP_PSUBB:
6069                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6070                         break;
6071                 case OP_PSUBW:
6072                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6073                         break;
6074                 case OP_PSUBD:
6075                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6076                         break;
6077                 case OP_PSUBQ:
6078                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080
6081                 case OP_PMAXB_UN:
6082                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6083                         break;
6084                 case OP_PMAXW_UN:
6085                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6086                         break;
6087                 case OP_PMAXD_UN:
6088                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6089                         break;
6090
6091                 case OP_PMAXB:
6092                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6093                         break;
6094                 case OP_PMAXW:
6095                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6096                         break;
6097                 case OP_PMAXD:
6098                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6099                         break;
6100
6101                 case OP_PAVGB_UN:
6102                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6103                         break;
6104                 case OP_PAVGW_UN:
6105                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6106                         break;
6107
6108                 case OP_PMINB_UN:
6109                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6110                         break;
6111                 case OP_PMINW_UN:
6112                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114                 case OP_PMIND_UN:
6115                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6116                         break;
6117
6118                 case OP_PMINB:
6119                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121                 case OP_PMINW:
6122                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6123                         break;
6124                 case OP_PMIND:
6125                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6126                         break;
6127
6128                 case OP_PCMPEQB:
6129                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131                 case OP_PCMPEQW:
6132                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6133                         break;
6134                 case OP_PCMPEQD:
6135                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6136                         break;
6137                 case OP_PCMPEQQ:
6138                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6139                         break;
6140
6141                 case OP_PCMPGTB:
6142                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6143                         break;
6144                 case OP_PCMPGTW:
6145                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6146                         break;
6147                 case OP_PCMPGTD:
6148                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6149                         break;
6150                 case OP_PCMPGTQ:
6151                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6152                         break;
6153
6154                 case OP_PSUM_ABS_DIFF:
6155                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6156                         break;
6157
6158                 case OP_UNPACK_LOWB:
6159                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6160                         break;
6161                 case OP_UNPACK_LOWW:
6162                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6163                         break;
6164                 case OP_UNPACK_LOWD:
6165                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6166                         break;
6167                 case OP_UNPACK_LOWQ:
6168                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6169                         break;
6170                 case OP_UNPACK_LOWPS:
6171                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6172                         break;
6173                 case OP_UNPACK_LOWPD:
6174                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6175                         break;
6176
6177                 case OP_UNPACK_HIGHB:
6178                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6179                         break;
6180                 case OP_UNPACK_HIGHW:
6181                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6182                         break;
6183                 case OP_UNPACK_HIGHD:
6184                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6185                         break;
6186                 case OP_UNPACK_HIGHQ:
6187                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6188                         break;
6189                 case OP_UNPACK_HIGHPS:
6190                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6191                         break;
6192                 case OP_UNPACK_HIGHPD:
6193                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6194                         break;
6195
6196                 case OP_PACKW:
6197                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6198                         break;
6199                 case OP_PACKD:
6200                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6201                         break;
6202                 case OP_PACKW_UN:
6203                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6204                         break;
6205                 case OP_PACKD_UN:
6206                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6207                         break;
6208
6209                 case OP_PADDB_SAT_UN:
6210                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6211                         break;
6212                 case OP_PSUBB_SAT_UN:
6213                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6214                         break;
6215                 case OP_PADDW_SAT_UN:
6216                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6217                         break;
6218                 case OP_PSUBW_SAT_UN:
6219                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6220                         break;
6221
6222                 case OP_PADDB_SAT:
6223                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6224                         break;
6225                 case OP_PSUBB_SAT:
6226                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6227                         break;
6228                 case OP_PADDW_SAT:
6229                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6230                         break;
6231                 case OP_PSUBW_SAT:
6232                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6233                         break;
6234
6235                 case OP_PMULW:
6236                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6237                         break;
6238                 case OP_PMULD:
6239                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6240                         break;
6241                 case OP_PMULQ:
6242                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6243                         break;
6244                 case OP_PMULW_HIGH_UN:
6245                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6246                         break;
6247                 case OP_PMULW_HIGH:
6248                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6249                         break;
6250
6251                 case OP_PSHRW:
6252                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6253                         break;
6254                 case OP_PSHRW_REG:
6255                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6256                         break;
6257
6258                 case OP_PSARW:
6259                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6260                         break;
6261                 case OP_PSARW_REG:
6262                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6263                         break;
6264
6265                 case OP_PSHLW:
6266                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6267                         break;
6268                 case OP_PSHLW_REG:
6269                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6270                         break;
6271
6272                 case OP_PSHRD:
6273                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6274                         break;
6275                 case OP_PSHRD_REG:
6276                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6277                         break;
6278
6279                 case OP_PSARD:
6280                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6281                         break;
6282                 case OP_PSARD_REG:
6283                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6284                         break;
6285
6286                 case OP_PSHLD:
6287                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6288                         break;
6289                 case OP_PSHLD_REG:
6290                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6291                         break;
6292
6293                 case OP_PSHRQ:
6294                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6295                         break;
6296                 case OP_PSHRQ_REG:
6297                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6298                         break;
6299
6300                 /*TODO: This is appart of the sse spec but not added
6301                 case OP_PSARQ:
6302                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6303                         break;
6304                 case OP_PSARQ_REG:
6305                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6306                         break;
6307                 */
6308
6309                 case OP_PSHLQ:
6310                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6311                         break;
6312                 case OP_PSHLQ_REG:
6313                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6314                         break;
6315                 case OP_CVTDQ2PD:
6316                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6317                         break;
6318                 case OP_CVTDQ2PS:
6319                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6320                         break;
6321                 case OP_CVTPD2DQ:
6322                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6323                         break;
6324                 case OP_CVTPD2PS:
6325                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6326                         break;
6327                 case OP_CVTPS2DQ:
6328                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6329                         break;
6330                 case OP_CVTPS2PD:
6331                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6332                         break;
6333                 case OP_CVTTPD2DQ:
6334                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6335                         break;
6336                 case OP_CVTTPS2DQ:
6337                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6338                         break;
6339
6340                 case OP_ICONV_TO_X:
6341                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6342                         break;
6343                 case OP_EXTRACT_I4:
6344                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6345                         break;
6346                 case OP_EXTRACT_I8:
6347                         if (ins->inst_c0) {
6348                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6349                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6350                         } else {
6351                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6352                         }
6353                         break;
6354                 case OP_EXTRACT_I1:
6355                 case OP_EXTRACT_U1:
6356                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6357                         if (ins->inst_c0)
6358                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6359                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6360                         break;
6361                 case OP_EXTRACT_I2:
6362                 case OP_EXTRACT_U2:
6363                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6364                         if (ins->inst_c0)
6365                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6366                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6367                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6368                         break;
6369                 case OP_EXTRACT_R8:
6370                         if (ins->inst_c0)
6371                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6372                         else
6373                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6374                         break;
6375                 case OP_INSERT_I2:
6376                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6377                         break;
6378                 case OP_EXTRACTX_U2:
6379                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6380                         break;
6381                 case OP_INSERTX_U1_SLOW:
6382                         /*sreg1 is the extracted ireg (scratch)
6383                         /sreg2 is the to be inserted ireg (scratch)
6384                         /dreg is the xreg to receive the value*/
6385
6386                         /*clear the bits from the extracted word*/
6387                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6388                         /*shift the value to insert if needed*/
6389                         if (ins->inst_c0 & 1)
6390                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6391                         /*join them together*/
6392                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6393                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6394                         break;
6395                 case OP_INSERTX_I4_SLOW:
6396                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6397                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6398                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6399                         break;
6400                 case OP_INSERTX_I8_SLOW:
6401                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6402                         if (ins->inst_c0)
6403                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6404                         else
6405                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6406                         break;
6407
6408                 case OP_INSERTX_R4_SLOW:
6409                         switch (ins->inst_c0) {
6410                         case 0:
6411                                 if (cfg->r4fp)
6412                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6413                                 else
6414                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6415                                 break;
6416                         case 1:
6417                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6418                                 if (cfg->r4fp)
6419                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6420                                 else
6421                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6422                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6423                                 break;
6424                         case 2:
6425                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6426                                 if (cfg->r4fp)
6427                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6428                                 else
6429                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6430                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6431                                 break;
6432                         case 3:
6433                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6434                                 if (cfg->r4fp)
6435                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6436                                 else
6437                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6438                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6439                                 break;
6440                         }
6441                         break;
6442                 case OP_INSERTX_R8_SLOW:
6443                         if (ins->inst_c0)
6444                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6445                         else
6446                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6447                         break;
6448                 case OP_STOREX_MEMBASE_REG:
6449                 case OP_STOREX_MEMBASE:
6450                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6451                         break;
6452                 case OP_LOADX_MEMBASE:
6453                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6454                         break;
6455                 case OP_LOADX_ALIGNED_MEMBASE:
6456                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6457                         break;
6458                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6459                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6460                         break;
6461                 case OP_STOREX_NTA_MEMBASE_REG:
6462                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6463                         break;
6464                 case OP_PREFETCH_MEMBASE:
6465                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6466                         break;
6467
6468                 case OP_XMOVE:
6469                         /*FIXME the peephole pass should have killed this*/
6470                         if (ins->dreg != ins->sreg1)
6471                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6472                         break;
6473                 case OP_XZERO:
6474                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6475                         break;
6476                 case OP_ICONV_TO_R4_RAW:
6477                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6478                         break;
6479
6480                 case OP_FCONV_TO_R8_X:
6481                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6482                         break;
6483
6484                 case OP_XCONV_R8_TO_I4:
6485                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6486                         switch (ins->backend.source_opcode) {
6487                         case OP_FCONV_TO_I1:
6488                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6489                                 break;
6490                         case OP_FCONV_TO_U1:
6491                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6492                                 break;
6493                         case OP_FCONV_TO_I2:
6494                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6495                                 break;
6496                         case OP_FCONV_TO_U2:
6497                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6498                                 break;
6499                         }
6500                         break;
6501
6502                 case OP_EXPAND_I2:
6503                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6504                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6505                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6506                         break;
6507                 case OP_EXPAND_I4:
6508                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6509                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6510                         break;
6511                 case OP_EXPAND_I8:
6512                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6513                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6514                         break;
6515                 case OP_EXPAND_R4:
6516                         if (cfg->r4fp) {
6517                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6518                         } else {
6519                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6520                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6521                         }
6522                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6523                         break;
6524                 case OP_EXPAND_R8:
6525                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6526                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6527                         break;
6528 #endif
6529                 case OP_LIVERANGE_START: {
6530                         if (cfg->verbose_level > 1)
6531                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6532                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6533                         break;
6534                 }
6535                 case OP_LIVERANGE_END: {
6536                         if (cfg->verbose_level > 1)
6537                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6538                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6539                         break;
6540                 }
6541                 case OP_NACL_GC_SAFE_POINT: {
6542 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6543                         if (cfg->compile_aot)
6544                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6545                         else {
6546                                 guint8 *br [1];
6547
6548                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6549                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6550                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6551                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6552                                 amd64_patch (br[0], code);
6553                         }
6554 #endif
6555                         break;
6556                 }
6557                 case OP_GC_LIVENESS_DEF:
6558                 case OP_GC_LIVENESS_USE:
6559                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6560                         ins->backend.pc_offset = code - cfg->native_code;
6561                         break;
6562                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6563                         ins->backend.pc_offset = code - cfg->native_code;
6564                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6565                         break;
6566                 default:
6567                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6568                         g_assert_not_reached ();
6569                 }
6570
6571                 if ((code - cfg->native_code - offset) > max_len) {
6572 #if !defined(__native_client_codegen__)
6573                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6574                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6575                         g_assert_not_reached ();
6576 #endif
6577                 }
6578         }
6579
6580         cfg->code_len = code - cfg->native_code;
6581 }
6582
6583 #endif /* DISABLE_JIT */
6584
6585 void
6586 mono_arch_register_lowlevel_calls (void)
6587 {
6588         /* The signature doesn't matter */
6589         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6590 }
6591
6592 void
6593 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6594 {
6595         MonoJumpInfo *patch_info;
6596         gboolean compile_aot = !run_cctors;
6597
6598         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6599                 unsigned char *ip = patch_info->ip.i + code;
6600                 unsigned char *target;
6601
6602                 if (compile_aot) {
6603                         switch (patch_info->type) {
6604                         case MONO_PATCH_INFO_BB:
6605                         case MONO_PATCH_INFO_LABEL:
6606                                 break;
6607                         default:
6608                                 /* No need to patch these */
6609                                 continue;
6610                         }
6611                 }
6612
6613                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6614
6615                 switch (patch_info->type) {
6616                 case MONO_PATCH_INFO_NONE:
6617                         continue;
6618                 case MONO_PATCH_INFO_METHOD_REL:
6619                 case MONO_PATCH_INFO_R8:
6620                 case MONO_PATCH_INFO_R4:
6621                         g_assert_not_reached ();
6622                         continue;
6623                 case MONO_PATCH_INFO_BB:
6624                         break;
6625                 default:
6626                         break;
6627                 }
6628
6629                 /*
6630                  * Debug code to help track down problems where the target of a near call is
6631                  * is not valid.
6632                  */
6633                 if (amd64_is_near_call (ip)) {
6634                         gint64 disp = (guint8*)target - (guint8*)ip;
6635
6636                         if (!amd64_is_imm32 (disp)) {
6637                                 printf ("TYPE: %d\n", patch_info->type);
6638                                 switch (patch_info->type) {
6639                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6640                                         printf ("V: %s\n", patch_info->data.name);
6641                                         break;
6642                                 case MONO_PATCH_INFO_METHOD_JUMP:
6643                                 case MONO_PATCH_INFO_METHOD:
6644                                         printf ("V: %s\n", patch_info->data.method->name);
6645                                         break;
6646                                 default:
6647                                         break;
6648                                 }
6649                         }
6650                 }
6651
6652                 amd64_patch (ip, (gpointer)target);
6653         }
6654 }
6655
6656 #ifndef DISABLE_JIT
6657
6658 static int
6659 get_max_epilog_size (MonoCompile *cfg)
6660 {
6661         int max_epilog_size = 16;
6662
6663         if (cfg->method->save_lmf)
6664                 max_epilog_size += 256;
6665
6666         if (mono_jit_trace_calls != NULL)
6667                 max_epilog_size += 50;
6668
6669         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6670                 max_epilog_size += 50;
6671
6672         max_epilog_size += (AMD64_NREG * 2);
6673
6674         return max_epilog_size;
6675 }
6676
6677 /*
6678  * This macro is used for testing whenever the unwinder works correctly at every point
6679  * where an async exception can happen.
6680  */
6681 /* This will generate a SIGSEGV at the given point in the code */
6682 #define async_exc_point(code) do { \
6683     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6684          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6685              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6686          cfg->arch.async_point_count ++; \
6687     } \
6688 } while (0)
6689
6690 guint8 *
6691 mono_arch_emit_prolog (MonoCompile *cfg)
6692 {
6693         MonoMethod *method = cfg->method;
6694         MonoBasicBlock *bb;
6695         MonoMethodSignature *sig;
6696         MonoInst *ins;
6697         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6698         guint8 *code;
6699         CallInfo *cinfo;
6700         MonoInst *lmf_var = cfg->lmf_var;
6701         gboolean args_clobbered = FALSE;
6702         gboolean trace = FALSE;
6703 #ifdef __native_client_codegen__
6704         guint alignment_check;
6705 #endif
6706
6707         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6708
6709 #if defined(__default_codegen__)
6710         code = cfg->native_code = g_malloc (cfg->code_size);
6711 #elif defined(__native_client_codegen__)
6712         /* native_code_alloc is not 32-byte aligned, native_code is. */
6713         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6714
6715         /* Align native_code to next nearest kNaclAlignment byte. */
6716         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6717         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6718
6719         code = cfg->native_code;
6720
6721         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6722         g_assert (alignment_check == 0);
6723 #endif
6724
6725         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6726                 trace = TRUE;
6727
6728         /* Amount of stack space allocated by register saving code */
6729         pos = 0;
6730
6731         /* Offset between RSP and the CFA */
6732         cfa_offset = 0;
6733
6734         /*
6735          * The prolog consists of the following parts:
6736          * FP present:
6737          * - push rbp, mov rbp, rsp
6738          * - save callee saved regs using pushes
6739          * - allocate frame
6740          * - save rgctx if needed
6741          * - save lmf if needed
6742          * FP not present:
6743          * - allocate frame
6744          * - save rgctx if needed
6745          * - save lmf if needed
6746          * - save callee saved regs using moves
6747          */
6748
6749         // CFA = sp + 8
6750         cfa_offset = 8;
6751         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6752         // IP saved at CFA - 8
6753         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6754         async_exc_point (code);
6755         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6756
6757         if (!cfg->arch.omit_fp) {
6758                 amd64_push_reg (code, AMD64_RBP);
6759                 cfa_offset += 8;
6760                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6761                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6762                 async_exc_point (code);
6763 #ifdef HOST_WIN32
6764                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6765 #endif
6766                 /* These are handled automatically by the stack marking code */
6767                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6768
6769                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6770                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6771                 async_exc_point (code);
6772 #ifdef HOST_WIN32
6773                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6774 #endif
6775         }
6776
6777         /* The param area is always at offset 0 from sp */
6778         /* This needs to be allocated here, since it has to come after the spill area */
6779         if (cfg->param_area) {
6780                 if (cfg->arch.omit_fp)
6781                         // FIXME:
6782                         g_assert_not_reached ();
6783                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6784         }
6785
6786         if (cfg->arch.omit_fp) {
6787                 /*
6788                  * On enter, the stack is misaligned by the pushing of the return
6789                  * address. It is either made aligned by the pushing of %rbp, or by
6790                  * this.
6791                  */
6792                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6793                 if ((alloc_size % 16) == 0) {
6794                         alloc_size += 8;
6795                         /* Mark the padding slot as NOREF */
6796                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6797                 }
6798         } else {
6799                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6800                 if (cfg->stack_offset != alloc_size) {
6801                         /* Mark the padding slot as NOREF */
6802                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6803                 }
6804                 cfg->arch.sp_fp_offset = alloc_size;
6805                 alloc_size -= pos;
6806         }
6807
6808         cfg->arch.stack_alloc_size = alloc_size;
6809
6810         /* Allocate stack frame */
6811         if (alloc_size) {
6812                 /* See mono_emit_stack_alloc */
6813 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6814                 guint32 remaining_size = alloc_size;
6815                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6816                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6817                 guint32 offset = code - cfg->native_code;
6818                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6819                         while (required_code_size >= (cfg->code_size - offset))
6820                                 cfg->code_size *= 2;
6821                         cfg->native_code = mono_realloc_native_code (cfg);
6822                         code = cfg->native_code + offset;
6823                         cfg->stat_code_reallocs++;
6824                 }
6825
6826                 while (remaining_size >= 0x1000) {
6827                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6828                         if (cfg->arch.omit_fp) {
6829                                 cfa_offset += 0x1000;
6830                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6831                         }
6832                         async_exc_point (code);
6833 #ifdef HOST_WIN32
6834                         if (cfg->arch.omit_fp)
6835                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6836 #endif
6837
6838                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6839                         remaining_size -= 0x1000;
6840                 }
6841                 if (remaining_size) {
6842                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6843                         if (cfg->arch.omit_fp) {
6844                                 cfa_offset += remaining_size;
6845                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6846                                 async_exc_point (code);
6847                         }
6848 #ifdef HOST_WIN32
6849                         if (cfg->arch.omit_fp)
6850                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6851 #endif
6852                 }
6853 #else
6854                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6855                 if (cfg->arch.omit_fp) {
6856                         cfa_offset += alloc_size;
6857                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6858                         async_exc_point (code);
6859                 }
6860 #endif
6861         }
6862
6863         /* Stack alignment check */
6864 #if 0
6865         {
6866                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6867                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6868                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6869                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6870                 amd64_breakpoint (code);
6871         }
6872 #endif
6873
6874         if (mini_get_debug_options ()->init_stacks) {
6875                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6876
6877                 /* Save registers to the red zone */
6878                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6879                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6880
6881                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6882                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6883                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6884
6885                 amd64_cld (code);
6886 #if defined(__default_codegen__)
6887                 amd64_prefix (code, X86_REP_PREFIX);
6888                 amd64_stosl (code);
6889 #elif defined(__native_client_codegen__)
6890                 /* NaCl stos pseudo-instruction */
6891                 amd64_codegen_pre (code);
6892                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6893                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6894                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6895                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6896                 amd64_prefix (code, X86_REP_PREFIX);
6897                 amd64_stosl (code);
6898                 amd64_codegen_post (code);
6899 #endif /* __native_client_codegen__ */
6900
6901                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6902                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6903         }
6904
6905         /* Save LMF */
6906         if (method->save_lmf)
6907                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6908
6909         /* Save callee saved registers */
6910         if (cfg->arch.omit_fp) {
6911                 save_area_offset = cfg->arch.reg_save_area_offset;
6912                 /* Save caller saved registers after sp is adjusted */
6913                 /* The registers are saved at the bottom of the frame */
6914                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6915         } else {
6916                 /* The registers are saved just below the saved rbp */
6917                 save_area_offset = cfg->arch.reg_save_area_offset;
6918         }
6919
6920         for (i = 0; i < AMD64_NREG; ++i) {
6921                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6922                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6923
6924                         if (cfg->arch.omit_fp) {
6925                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6926                                 /* These are handled automatically by the stack marking code */
6927                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6928                         } else {
6929                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6930                                 // FIXME: GC
6931                         }
6932
6933                         save_area_offset += 8;
6934                         async_exc_point (code);
6935                 }
6936         }
6937
6938         /* store runtime generic context */
6939         if (cfg->rgctx_var) {
6940                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6941                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6942
6943                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6944
6945                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6946                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6947         }
6948
6949         /* compute max_length in order to use short forward jumps */
6950         max_epilog_size = get_max_epilog_size (cfg);
6951         if (cfg->opt & MONO_OPT_BRANCH) {
6952                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6953                         MonoInst *ins;
6954                         int max_length = 0;
6955
6956                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6957                                 max_length += 6;
6958                         /* max alignment for loops */
6959                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6960                                 max_length += LOOP_ALIGNMENT;
6961 #ifdef __native_client_codegen__
6962                         /* max alignment for native client */
6963                         max_length += kNaClAlignment;
6964 #endif
6965
6966                         MONO_BB_FOR_EACH_INS (bb, ins) {
6967 #ifdef __native_client_codegen__
6968                                 {
6969                                         int space_in_block = kNaClAlignment -
6970                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6971                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6972                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6973                                                 max_length += space_in_block;
6974                                         }
6975                                 }
6976 #endif  /*__native_client_codegen__*/
6977                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6978                         }
6979
6980                         /* Take prolog and epilog instrumentation into account */
6981                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6982                                 max_length += max_epilog_size;
6983
6984                         bb->max_length = max_length;
6985                 }
6986         }
6987
6988         sig = mono_method_signature (method);
6989         pos = 0;
6990
6991         cinfo = cfg->arch.cinfo;
6992
6993         if (sig->ret->type != MONO_TYPE_VOID) {
6994                 /* Save volatile arguments to the stack */
6995                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6996                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6997         }
6998
6999         /* Keep this in sync with emit_load_volatile_arguments */
7000         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7001                 ArgInfo *ainfo = cinfo->args + i;
7002
7003                 ins = cfg->args [i];
7004
7005                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7006                         /* Unused arguments */
7007                         continue;
7008
7009                 if (cfg->globalra) {
7010                         /* All the other moves are done by the register allocator */
7011                         switch (ainfo->storage) {
7012                         case ArgInFloatSSEReg:
7013                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
7014                                 break;
7015                         case ArgValuetypeInReg:
7016                                 for (quad = 0; quad < 2; quad ++) {
7017                                         switch (ainfo->pair_storage [quad]) {
7018                                         case ArgInIReg:
7019                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7020                                                 break;
7021                                         case ArgInFloatSSEReg:
7022                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7023                                                 break;
7024                                         case ArgInDoubleSSEReg:
7025                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7026                                                 break;
7027                                         case ArgNone:
7028                                                 break;
7029                                         default:
7030                                                 g_assert_not_reached ();
7031                                         }
7032                                 }
7033                                 break;
7034                         default:
7035                                 break;
7036                         }
7037
7038                         continue;
7039                 }
7040
7041                 /* Save volatile arguments to the stack */
7042                 if (ins->opcode != OP_REGVAR) {
7043                         switch (ainfo->storage) {
7044                         case ArgInIReg: {
7045                                 guint32 size = 8;
7046
7047                                 /* FIXME: I1 etc */
7048                                 /*
7049                                 if (stack_offset & 0x1)
7050                                         size = 1;
7051                                 else if (stack_offset & 0x2)
7052                                         size = 2;
7053                                 else if (stack_offset & 0x4)
7054                                         size = 4;
7055                                 else
7056                                         size = 8;
7057                                 */
7058                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7059
7060                                 /*
7061                                  * Save the original location of 'this',
7062                                  * get_generic_info_from_stack_frame () needs this to properly look up
7063                                  * the argument value during the handling of async exceptions.
7064                                  */
7065                                 if (ins == cfg->args [0]) {
7066                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7067                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7068                                 }
7069                                 break;
7070                         }
7071                         case ArgInFloatSSEReg:
7072                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7073                                 break;
7074                         case ArgInDoubleSSEReg:
7075                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7076                                 break;
7077                         case ArgValuetypeInReg:
7078                                 for (quad = 0; quad < 2; quad ++) {
7079                                         switch (ainfo->pair_storage [quad]) {
7080                                         case ArgInIReg:
7081                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7082                                                 break;
7083                                         case ArgInFloatSSEReg:
7084                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7085                                                 break;
7086                                         case ArgInDoubleSSEReg:
7087                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7088                                                 break;
7089                                         case ArgNone:
7090                                                 break;
7091                                         default:
7092                                                 g_assert_not_reached ();
7093                                         }
7094                                 }
7095                                 break;
7096                         case ArgValuetypeAddrInIReg:
7097                                 if (ainfo->pair_storage [0] == ArgInIReg)
7098                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7099                                 break;
7100                         default:
7101                                 break;
7102                         }
7103                 } else {
7104                         /* Argument allocated to (non-volatile) register */
7105                         switch (ainfo->storage) {
7106                         case ArgInIReg:
7107                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7108                                 break;
7109                         case ArgOnStack:
7110                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7111                                 break;
7112                         default:
7113                                 g_assert_not_reached ();
7114                         }
7115
7116                         if (ins == cfg->args [0]) {
7117                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7118                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7119                         }
7120                 }
7121         }
7122
7123         if (cfg->method->save_lmf)
7124                 args_clobbered = TRUE;
7125
7126         if (trace) {
7127                 args_clobbered = TRUE;
7128                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7129         }
7130
7131         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7132                 args_clobbered = TRUE;
7133
7134         /*
7135          * Optimize the common case of the first bblock making a call with the same
7136          * arguments as the method. This works because the arguments are still in their
7137          * original argument registers.
7138          * FIXME: Generalize this
7139          */
7140         if (!args_clobbered) {
7141                 MonoBasicBlock *first_bb = cfg->bb_entry;
7142                 MonoInst *next;
7143                 int filter = FILTER_IL_SEQ_POINT;
7144
7145                 next = mono_bb_first_inst (first_bb, filter);
7146                 if (!next && first_bb->next_bb) {
7147                         first_bb = first_bb->next_bb;
7148                         next = mono_bb_first_inst (first_bb, filter);
7149                 }
7150
7151                 if (first_bb->in_count > 1)
7152                         next = NULL;
7153
7154                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7155                         ArgInfo *ainfo = cinfo->args + i;
7156                         gboolean match = FALSE;
7157
7158                         ins = cfg->args [i];
7159                         if (ins->opcode != OP_REGVAR) {
7160                                 switch (ainfo->storage) {
7161                                 case ArgInIReg: {
7162                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7163                                                 if (next->dreg == ainfo->reg) {
7164                                                         NULLIFY_INS (next);
7165                                                         match = TRUE;
7166                                                 } else {
7167                                                         next->opcode = OP_MOVE;
7168                                                         next->sreg1 = ainfo->reg;
7169                                                         /* Only continue if the instruction doesn't change argument regs */
7170                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7171                                                                 match = TRUE;
7172                                                 }
7173                                         }
7174                                         break;
7175                                 }
7176                                 default:
7177                                         break;
7178                                 }
7179                         } else {
7180                                 /* Argument allocated to (non-volatile) register */
7181                                 switch (ainfo->storage) {
7182                                 case ArgInIReg:
7183                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7184                                                 NULLIFY_INS (next);
7185                                                 match = TRUE;
7186                                         }
7187                                         break;
7188                                 default:
7189                                         break;
7190                                 }
7191                         }
7192
7193                         if (match) {
7194                                 next = mono_inst_next (next, filter);
7195                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7196                                 if (!next)
7197                                         break;
7198                         }
7199                 }
7200         }
7201
7202         if (cfg->gen_seq_points_debug_data) {
7203                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7204
7205                 /* Initialize seq_point_info_var */
7206                 if (cfg->compile_aot) {
7207                         /* Initialize the variable from a GOT slot */
7208                         /* Same as OP_AOTCONST */
7209                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7210                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7211                         g_assert (info_var->opcode == OP_REGOFFSET);
7212                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7213                 }
7214
7215                 /* Initialize ss_trigger_page_var */
7216                 ins = cfg->arch.ss_trigger_page_var;
7217
7218                 g_assert (ins->opcode == OP_REGOFFSET);
7219
7220                 if (cfg->compile_aot) {
7221                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7222                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7223                 } else {
7224                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7225                 }
7226                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7227         }
7228
7229         cfg->code_len = code - cfg->native_code;
7230
7231         g_assert (cfg->code_len < cfg->code_size);
7232
7233         return code;
7234 }
7235
7236 void
7237 mono_arch_emit_epilog (MonoCompile *cfg)
7238 {
7239         MonoMethod *method = cfg->method;
7240         int quad, i;
7241         guint8 *code;
7242         int max_epilog_size;
7243         CallInfo *cinfo;
7244         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7245         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7246
7247         max_epilog_size = get_max_epilog_size (cfg);
7248
7249         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7250                 cfg->code_size *= 2;
7251                 cfg->native_code = mono_realloc_native_code (cfg);
7252                 cfg->stat_code_reallocs++;
7253         }
7254         code = cfg->native_code + cfg->code_len;
7255
7256         cfg->has_unwind_info_for_epilog = TRUE;
7257
7258         /* Mark the start of the epilog */
7259         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7260
7261         /* Save the uwind state which is needed by the out-of-line code */
7262         mono_emit_unwind_op_remember_state (cfg, code);
7263
7264         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7265                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7266
7267         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7268
7269         if (method->save_lmf) {
7270                 /* check if we need to restore protection of the stack after a stack overflow */
7271                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7272                         guint8 *patch;
7273                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7274                         /* we load the value in a separate instruction: this mechanism may be
7275                          * used later as a safer way to do thread interruption
7276                          */
7277                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7278                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7279                         patch = code;
7280                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7281                         /* note that the call trampoline will preserve eax/edx */
7282                         x86_call_reg (code, X86_ECX);
7283                         x86_patch (patch, code);
7284                 } else {
7285                         /* FIXME: maybe save the jit tls in the prolog */
7286                 }
7287                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7288                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7289                 }
7290         }
7291
7292         /* Restore callee saved regs */
7293         for (i = 0; i < AMD64_NREG; ++i) {
7294                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7295                         /* Restore only used_int_regs, not arch.saved_iregs */
7296                         if (cfg->used_int_regs & (1 << i)) {
7297                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7298                                 mono_emit_unwind_op_same_value (cfg, code, i);
7299                                 async_exc_point (code);
7300                         }
7301                         save_area_offset += 8;
7302                 }
7303         }
7304
7305         /* Load returned vtypes into registers if needed */
7306         cinfo = cfg->arch.cinfo;
7307         if (cinfo->ret.storage == ArgValuetypeInReg) {
7308                 ArgInfo *ainfo = &cinfo->ret;
7309                 MonoInst *inst = cfg->ret;
7310
7311                 for (quad = 0; quad < 2; quad ++) {
7312                         switch (ainfo->pair_storage [quad]) {
7313                         case ArgInIReg:
7314                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7315                                 break;
7316                         case ArgInFloatSSEReg:
7317                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7318                                 break;
7319                         case ArgInDoubleSSEReg:
7320                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7321                                 break;
7322                         case ArgNone:
7323                                 break;
7324                         default:
7325                                 g_assert_not_reached ();
7326                         }
7327                 }
7328         }
7329
7330         if (cfg->arch.omit_fp) {
7331                 if (cfg->arch.stack_alloc_size) {
7332                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7333                 }
7334         } else {
7335                 amd64_leave (code);
7336                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7337         }
7338         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7339         async_exc_point (code);
7340         amd64_ret (code);
7341
7342         /* Restore the unwind state to be the same as before the epilog */
7343         mono_emit_unwind_op_restore_state (cfg, code);
7344
7345         cfg->code_len = code - cfg->native_code;
7346
7347         g_assert (cfg->code_len < cfg->code_size);
7348 }
7349
7350 void
7351 mono_arch_emit_exceptions (MonoCompile *cfg)
7352 {
7353         MonoJumpInfo *patch_info;
7354         int nthrows, i;
7355         guint8 *code;
7356         MonoClass *exc_classes [16];
7357         guint8 *exc_throw_start [16], *exc_throw_end [16];
7358         guint32 code_size = 0;
7359
7360         /* Compute needed space */
7361         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7362                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7363                         code_size += 40;
7364                 if (patch_info->type == MONO_PATCH_INFO_R8)
7365                         code_size += 8 + 15; /* sizeof (double) + alignment */
7366                 if (patch_info->type == MONO_PATCH_INFO_R4)
7367                         code_size += 4 + 15; /* sizeof (float) + alignment */
7368                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7369                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7370         }
7371
7372 #ifdef __native_client_codegen__
7373         /* Give us extra room on Native Client.  This could be   */
7374         /* more carefully calculated, but bundle alignment makes */
7375         /* it much trickier, so *2 like other places is good.    */
7376         code_size *= 2;
7377 #endif
7378
7379         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7380                 cfg->code_size *= 2;
7381                 cfg->native_code = mono_realloc_native_code (cfg);
7382                 cfg->stat_code_reallocs++;
7383         }
7384
7385         code = cfg->native_code + cfg->code_len;
7386
7387         /* add code to raise exceptions */
7388         nthrows = 0;
7389         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7390                 switch (patch_info->type) {
7391                 case MONO_PATCH_INFO_EXC: {
7392                         MonoClass *exc_class;
7393                         guint8 *buf, *buf2;
7394                         guint32 throw_ip;
7395
7396                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7397
7398                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7399                         g_assert (exc_class);
7400                         throw_ip = patch_info->ip.i;
7401
7402                         //x86_breakpoint (code);
7403                         /* Find a throw sequence for the same exception class */
7404                         for (i = 0; i < nthrows; ++i)
7405                                 if (exc_classes [i] == exc_class)
7406                                         break;
7407                         if (i < nthrows) {
7408                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7409                                 x86_jump_code (code, exc_throw_start [i]);
7410                                 patch_info->type = MONO_PATCH_INFO_NONE;
7411                         }
7412                         else {
7413                                 buf = code;
7414                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7415                                 buf2 = code;
7416
7417                                 if (nthrows < 16) {
7418                                         exc_classes [nthrows] = exc_class;
7419                                         exc_throw_start [nthrows] = code;
7420                                 }
7421                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7422
7423                                 patch_info->type = MONO_PATCH_INFO_NONE;
7424
7425                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7426
7427                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7428                                 while (buf < buf2)
7429                                         x86_nop (buf);
7430
7431                                 if (nthrows < 16) {
7432                                         exc_throw_end [nthrows] = code;
7433                                         nthrows ++;
7434                                 }
7435                         }
7436                         break;
7437                 }
7438                 default:
7439                         /* do nothing */
7440                         break;
7441                 }
7442                 g_assert(code < cfg->native_code + cfg->code_size);
7443         }
7444
7445         /* Handle relocations with RIP relative addressing */
7446         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7447                 gboolean remove = FALSE;
7448                 guint8 *orig_code = code;
7449
7450                 switch (patch_info->type) {
7451                 case MONO_PATCH_INFO_R8:
7452                 case MONO_PATCH_INFO_R4: {
7453                         guint8 *pos, *patch_pos;
7454                         guint32 target_pos;
7455
7456                         /* The SSE opcodes require a 16 byte alignment */
7457 #if defined(__default_codegen__)
7458                         code = (guint8*)ALIGN_TO (code, 16);
7459 #elif defined(__native_client_codegen__)
7460                         {
7461                                 /* Pad this out with HLT instructions  */
7462                                 /* or we can get garbage bytes emitted */
7463                                 /* which will fail validation          */
7464                                 guint8 *aligned_code;
7465                                 /* extra align to make room for  */
7466                                 /* mov/push below                      */
7467                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7468                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7469                                 /* The technique of hiding data in an  */
7470                                 /* instruction has a problem here: we  */
7471                                 /* need the data aligned to a 16-byte  */
7472                                 /* boundary but the instruction cannot */
7473                                 /* cross the bundle boundary. so only  */
7474                                 /* odd multiples of 16 can be used     */
7475                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7476                                         aligned_code += 16;
7477                                 }
7478                                 while (code < aligned_code) {
7479                                         *(code++) = 0xf4; /* hlt */
7480                                 }
7481                         }
7482 #endif
7483
7484                         pos = cfg->native_code + patch_info->ip.i;
7485                         if (IS_REX (pos [1])) {
7486                                 patch_pos = pos + 5;
7487                                 target_pos = code - pos - 9;
7488                         }
7489                         else {
7490                                 patch_pos = pos + 4;
7491                                 target_pos = code - pos - 8;
7492                         }
7493
7494                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7495 #ifdef __native_client_codegen__
7496                                 /* Hide 64-bit data in a         */
7497                                 /* "mov imm64, r11" instruction. */
7498                                 /* write it before the start of  */
7499                                 /* the data*/
7500                                 *(code-2) = 0x49; /* prefix      */
7501                                 *(code-1) = 0xbb; /* mov X, %r11 */
7502 #endif
7503                                 *(double*)code = *(double*)patch_info->data.target;
7504                                 code += sizeof (double);
7505                         } else {
7506 #ifdef __native_client_codegen__
7507                                 /* Hide 32-bit data in a        */
7508                                 /* "push imm32" instruction.    */
7509                                 *(code-1) = 0x68; /* push */
7510 #endif
7511                                 *(float*)code = *(float*)patch_info->data.target;
7512                                 code += sizeof (float);
7513                         }
7514
7515                         *(guint32*)(patch_pos) = target_pos;
7516
7517                         remove = TRUE;
7518                         break;
7519                 }
7520                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7521                         guint8 *pos;
7522
7523                         if (cfg->compile_aot)
7524                                 continue;
7525
7526                         /*loading is faster against aligned addresses.*/
7527                         code = (guint8*)ALIGN_TO (code, 8);
7528                         memset (orig_code, 0, code - orig_code);
7529
7530                         pos = cfg->native_code + patch_info->ip.i;
7531
7532                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7533                         if (IS_REX (pos [1]))
7534                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7535                         else
7536                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7537
7538                         *(gpointer*)code = (gpointer)patch_info->data.target;
7539                         code += sizeof (gpointer);
7540
7541                         remove = TRUE;
7542                         break;
7543                 }
7544                 default:
7545                         break;
7546                 }
7547
7548                 if (remove) {
7549                         if (patch_info == cfg->patch_info)
7550                                 cfg->patch_info = patch_info->next;
7551                         else {
7552                                 MonoJumpInfo *tmp;
7553
7554                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7555                                         ;
7556                                 tmp->next = patch_info->next;
7557                         }
7558                 }
7559                 g_assert (code < cfg->native_code + cfg->code_size);
7560         }
7561
7562         cfg->code_len = code - cfg->native_code;
7563
7564         g_assert (cfg->code_len < cfg->code_size);
7565
7566 }
7567
7568 #endif /* DISABLE_JIT */
7569
7570 void*
7571 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7572 {
7573         guchar *code = p;
7574         MonoMethodSignature *sig;
7575         MonoInst *inst;
7576         int i, n, stack_area = 0;
7577
7578         /* Keep this in sync with mono_arch_get_argument_info */
7579
7580         if (enable_arguments) {
7581                 /* Allocate a new area on the stack and save arguments there */
7582                 sig = mono_method_signature (cfg->method);
7583
7584                 n = sig->param_count + sig->hasthis;
7585
7586                 stack_area = ALIGN_TO (n * 8, 16);
7587
7588                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7589
7590                 for (i = 0; i < n; ++i) {
7591                         inst = cfg->args [i];
7592
7593                         if (inst->opcode == OP_REGVAR)
7594                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7595                         else {
7596                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7597                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7598                         }
7599                 }
7600         }
7601
7602         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7603         amd64_set_reg_template (code, AMD64_ARG_REG1);
7604         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7605         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7606
7607         if (enable_arguments)
7608                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7609
7610         return code;
7611 }
7612
7613 enum {
7614         SAVE_NONE,
7615         SAVE_STRUCT,
7616         SAVE_EAX,
7617         SAVE_EAX_EDX,
7618         SAVE_XMM
7619 };
7620
7621 void*
7622 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7623 {
7624         guchar *code = p;
7625         int save_mode = SAVE_NONE;
7626         MonoMethod *method = cfg->method;
7627         MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7628         int i;
7629
7630         switch (ret_type->type) {
7631         case MONO_TYPE_VOID:
7632                 /* special case string .ctor icall */
7633                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7634                         save_mode = SAVE_EAX;
7635                 else
7636                         save_mode = SAVE_NONE;
7637                 break;
7638         case MONO_TYPE_I8:
7639         case MONO_TYPE_U8:
7640                 save_mode = SAVE_EAX;
7641                 break;
7642         case MONO_TYPE_R4:
7643         case MONO_TYPE_R8:
7644                 save_mode = SAVE_XMM;
7645                 break;
7646         case MONO_TYPE_GENERICINST:
7647                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7648                         save_mode = SAVE_EAX;
7649                         break;
7650                 }
7651                 /* Fall through */
7652         case MONO_TYPE_VALUETYPE:
7653                 save_mode = SAVE_STRUCT;
7654                 break;
7655         default:
7656                 save_mode = SAVE_EAX;
7657                 break;
7658         }
7659
7660         /* Save the result and copy it into the proper argument register */
7661         switch (save_mode) {
7662         case SAVE_EAX:
7663                 amd64_push_reg (code, AMD64_RAX);
7664                 /* Align stack */
7665                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7666                 if (enable_arguments)
7667                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7668                 break;
7669         case SAVE_STRUCT:
7670                 /* FIXME: */
7671                 if (enable_arguments)
7672                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7673                 break;
7674         case SAVE_XMM:
7675                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7676                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7677                 /* Align stack */
7678                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7679                 /*
7680                  * The result is already in the proper argument register so no copying
7681                  * needed.
7682                  */
7683                 break;
7684         case SAVE_NONE:
7685                 break;
7686         default:
7687                 g_assert_not_reached ();
7688         }
7689
7690         /* Set %al since this is a varargs call */
7691         if (save_mode == SAVE_XMM)
7692                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7693         else
7694                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7695
7696         if (preserve_argument_registers) {
7697                 for (i = 0; i < PARAM_REGS; ++i)
7698                         amd64_push_reg (code, param_regs [i]);
7699         }
7700
7701         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7702         amd64_set_reg_template (code, AMD64_ARG_REG1);
7703         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7704
7705         if (preserve_argument_registers) {
7706                 for (i = PARAM_REGS - 1; i >= 0; --i)
7707                         amd64_pop_reg (code, param_regs [i]);
7708         }
7709
7710         /* Restore result */
7711         switch (save_mode) {
7712         case SAVE_EAX:
7713                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7714                 amd64_pop_reg (code, AMD64_RAX);
7715                 break;
7716         case SAVE_STRUCT:
7717                 /* FIXME: */
7718                 break;
7719         case SAVE_XMM:
7720                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7721                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7722                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7723                 break;
7724         case SAVE_NONE:
7725                 break;
7726         default:
7727                 g_assert_not_reached ();
7728         }
7729
7730         return code;
7731 }
7732
7733 void
7734 mono_arch_flush_icache (guint8 *code, gint size)
7735 {
7736         /* Not needed */
7737 }
7738
7739 void
7740 mono_arch_flush_register_windows (void)
7741 {
7742 }
7743
7744 gboolean
7745 mono_arch_is_inst_imm (gint64 imm)
7746 {
7747         return amd64_is_imm32 (imm);
7748 }
7749
7750 /*
7751  * Determine whenever the trap whose info is in SIGINFO is caused by
7752  * integer overflow.
7753  */
7754 gboolean
7755 mono_arch_is_int_overflow (void *sigctx, void *info)
7756 {
7757         MonoContext ctx;
7758         guint8* rip;
7759         int reg;
7760         gint64 value;
7761
7762         mono_sigctx_to_monoctx (sigctx, &ctx);
7763
7764         rip = (guint8*)ctx.rip;
7765
7766         if (IS_REX (rip [0])) {
7767                 reg = amd64_rex_b (rip [0]);
7768                 rip ++;
7769         }
7770         else
7771                 reg = 0;
7772
7773         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7774                 /* idiv REG */
7775                 reg += x86_modrm_rm (rip [1]);
7776
7777                 switch (reg) {
7778                 case AMD64_RAX:
7779                         value = ctx.rax;
7780                         break;
7781                 case AMD64_RBX:
7782                         value = ctx.rbx;
7783                         break;
7784                 case AMD64_RCX:
7785                         value = ctx.rcx;
7786                         break;
7787                 case AMD64_RDX:
7788                         value = ctx.rdx;
7789                         break;
7790                 case AMD64_RBP:
7791                         value = ctx.rbp;
7792                         break;
7793                 case AMD64_RSP:
7794                         value = ctx.rsp;
7795                         break;
7796                 case AMD64_RSI:
7797                         value = ctx.rsi;
7798                         break;
7799                 case AMD64_RDI:
7800                         value = ctx.rdi;
7801                         break;
7802                 case AMD64_R12:
7803                         value = ctx.r12;
7804                         break;
7805                 case AMD64_R13:
7806                         value = ctx.r13;
7807                         break;
7808                 case AMD64_R14:
7809                         value = ctx.r14;
7810                         break;
7811                 case AMD64_R15:
7812                         value = ctx.r15;
7813                         break;
7814                 default:
7815                         g_assert_not_reached ();
7816                         reg = -1;
7817                 }
7818
7819                 if (value == -1)
7820                         return TRUE;
7821         }
7822
7823         return FALSE;
7824 }
7825
7826 guint32
7827 mono_arch_get_patch_offset (guint8 *code)
7828 {
7829         return 3;
7830 }
7831
7832 /**
7833  * mono_breakpoint_clean_code:
7834  *
7835  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7836  * breakpoints in the original code, they are removed in the copy.
7837  *
7838  * Returns TRUE if no sw breakpoint was present.
7839  */
7840 gboolean
7841 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7842 {
7843         /*
7844          * If method_start is non-NULL we need to perform bound checks, since we access memory
7845          * at code - offset we could go before the start of the method and end up in a different
7846          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7847          * instead.
7848          */
7849         if (!method_start || code - offset >= method_start) {
7850                 memcpy (buf, code - offset, size);
7851         } else {
7852                 int diff = code - method_start;
7853                 memset (buf, 0, size);
7854                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7855         }
7856         return TRUE;
7857 }
7858
7859 #if defined(__native_client_codegen__)
7860 /* For membase calls, we want the base register. for Native Client,  */
7861 /* all indirect calls have the following sequence with the given sizes: */
7862 /* mov %eXX,%eXX                                [2-3]   */
7863 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7864 /* and $0xffffffffffffffe0,%r11d                [4]     */
7865 /* add %r15,%r11                                [3]     */
7866 /* callq *%r11                                  [3]     */
7867
7868
7869 /* Determine if code points to a NaCl call-through-register sequence, */
7870 /* (i.e., the last 3 instructions listed above) */
7871 int
7872 is_nacl_call_reg_sequence(guint8* code)
7873 {
7874         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7875                                "\x4d\x03\xdf"     /* add */
7876                                "\x41\xff\xd3";   /* call */
7877         return memcmp(code, sequence, 10) == 0;
7878 }
7879
7880 /* Determine if code points to the first opcode of the mov membase component */
7881 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7882 /* (there could be a REX prefix before the opcode but it is ignored) */
7883 static int
7884 is_nacl_indirect_call_membase_sequence(guint8* code)
7885 {
7886                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7887         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7888                /* and that src reg = dest reg */
7889                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7890                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7891                IS_REX(code[2]) &&
7892                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7893                /* and has dst of r11 and base of r15 */
7894                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7895                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7896 }
7897 #endif /* __native_client_codegen__ */
7898
7899 int
7900 mono_arch_get_this_arg_reg (guint8 *code)
7901 {
7902         return AMD64_ARG_REG1;
7903 }
7904
7905 gpointer
7906 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7907 {
7908         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7909 }
7910
7911 #define MAX_ARCH_DELEGATE_PARAMS 10
7912
7913 static gpointer
7914 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7915 {
7916         guint8 *code, *start;
7917         int i;
7918
7919         if (has_target) {
7920                 start = code = mono_global_codeman_reserve (64);
7921
7922                 /* Replace the this argument with the target */
7923                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7924                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7925                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7926
7927                 g_assert ((code - start) < 64);
7928         } else {
7929                 start = code = mono_global_codeman_reserve (64);
7930
7931                 if (param_count == 0) {
7932                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7933                 } else {
7934                         /* We have to shift the arguments left */
7935                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7936                         for (i = 0; i < param_count; ++i) {
7937 #ifdef HOST_WIN32
7938                                 if (i < 3)
7939                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7940                                 else
7941                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7942 #else
7943                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7944 #endif
7945                         }
7946
7947                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7948                 }
7949                 g_assert ((code - start) < 64);
7950         }
7951
7952         nacl_global_codeman_validate (&start, 64, &code);
7953
7954         if (code_len)
7955                 *code_len = code - start;
7956
7957         if (mono_jit_map_is_enabled ()) {
7958                 char *buff;
7959                 if (has_target)
7960                         buff = (char*)"delegate_invoke_has_target";
7961                 else
7962                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7963                 mono_emit_jit_tramp (start, code - start, buff);
7964                 if (!has_target)
7965                         g_free (buff);
7966         }
7967         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7968
7969         return start;
7970 }
7971
7972 /*
7973  * mono_arch_get_delegate_invoke_impls:
7974  *
7975  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7976  * trampolines.
7977  */
7978 GSList*
7979 mono_arch_get_delegate_invoke_impls (void)
7980 {
7981         GSList *res = NULL;
7982         guint8 *code;
7983         guint32 code_len;
7984         int i;
7985         char *tramp_name;
7986
7987         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7988         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7989
7990         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7991                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7992                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7993                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7994                 g_free (tramp_name);
7995         }
7996
7997         return res;
7998 }
7999
8000 gpointer
8001 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8002 {
8003         guint8 *code, *start;
8004         int i;
8005
8006         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8007                 return NULL;
8008
8009         /* FIXME: Support more cases */
8010         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
8011                 return NULL;
8012
8013         if (has_target) {
8014                 static guint8* cached = NULL;
8015
8016                 if (cached)
8017                         return cached;
8018
8019                 if (mono_aot_only)
8020                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8021                 else
8022                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
8023
8024                 mono_memory_barrier ();
8025
8026                 cached = start;
8027         } else {
8028                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8029                 for (i = 0; i < sig->param_count; ++i)
8030                         if (!mono_is_regsize_var (sig->params [i]))
8031                                 return NULL;
8032                 if (sig->param_count > 4)
8033                         return NULL;
8034
8035                 code = cache [sig->param_count];
8036                 if (code)
8037                         return code;
8038
8039                 if (mono_aot_only) {
8040                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8041                         start = mono_aot_get_trampoline (name);
8042                         g_free (name);
8043                 } else {
8044                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8045                 }
8046
8047                 mono_memory_barrier ();
8048
8049                 cache [sig->param_count] = start;
8050         }
8051
8052         return start;
8053 }
8054
8055 gpointer
8056 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8057 {
8058         guint8 *code, *start;
8059         int size = 20;
8060
8061         start = code = mono_global_codeman_reserve (size);
8062
8063         /* Replace the this argument with the target */
8064         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8065         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8066
8067         if (load_imt_reg) {
8068                 /* Load the IMT reg */
8069                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8070         }
8071
8072         /* Load the vtable */
8073         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8074         amd64_jump_membase (code, AMD64_RAX, offset);
8075         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8076
8077         return start;
8078 }
8079
8080 void
8081 mono_arch_finish_init (void)
8082 {
8083 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8084         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8085 #endif
8086 }
8087
8088 void
8089 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8090 {
8091 }
8092
8093 #if defined(__default_codegen__)
8094 #define CMP_SIZE (6 + 1)
8095 #define CMP_REG_REG_SIZE (4 + 1)
8096 #define BR_SMALL_SIZE 2
8097 #define BR_LARGE_SIZE 6
8098 #define MOV_REG_IMM_SIZE 10
8099 #define MOV_REG_IMM_32BIT_SIZE 6
8100 #define JUMP_REG_SIZE (2 + 1)
8101 #elif defined(__native_client_codegen__)
8102 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8103 #define CMP_SIZE ((6 + 1) * 2 - 1)
8104 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8105 #define BR_SMALL_SIZE (2 * 2 - 1)
8106 #define BR_LARGE_SIZE (6 * 2 - 1)
8107 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8108 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8109 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8110 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8111 /* Jump membase's size is large and unpredictable    */
8112 /* in native client, just pad it out a whole bundle. */
8113 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8114 #endif
8115
8116 static int
8117 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8118 {
8119         int i, distance = 0;
8120         for (i = start; i < target; ++i)
8121                 distance += imt_entries [i]->chunk_size;
8122         return distance;
8123 }
8124
8125 /*
8126  * LOCKING: called with the domain lock held
8127  */
8128 gpointer
8129 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8130         gpointer fail_tramp)
8131 {
8132         int i;
8133         int size = 0;
8134         guint8 *code, *start;
8135         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8136
8137         for (i = 0; i < count; ++i) {
8138                 MonoIMTCheckItem *item = imt_entries [i];
8139                 if (item->is_equals) {
8140                         if (item->check_target_idx) {
8141                                 if (!item->compare_done) {
8142                                         if (amd64_is_imm32 (item->key))
8143                                                 item->chunk_size += CMP_SIZE;
8144                                         else
8145                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8146                                 }
8147                                 if (item->has_target_code) {
8148                                         item->chunk_size += MOV_REG_IMM_SIZE;
8149                                 } else {
8150                                         if (vtable_is_32bit)
8151                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8152                                         else
8153                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8154 #ifdef __native_client_codegen__
8155                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8156 #endif
8157                                 }
8158                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8159                         } else {
8160                                 if (fail_tramp) {
8161                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8162                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8163                                 } else {
8164                                         if (vtable_is_32bit)
8165                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8166                                         else
8167                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8168                                         item->chunk_size += JUMP_REG_SIZE;
8169                                         /* with assert below:
8170                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8171                                          */
8172 #ifdef __native_client_codegen__
8173                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8174 #endif
8175                                 }
8176                         }
8177                 } else {
8178                         if (amd64_is_imm32 (item->key))
8179                                 item->chunk_size += CMP_SIZE;
8180                         else
8181                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8182                         item->chunk_size += BR_LARGE_SIZE;
8183                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8184                 }
8185                 size += item->chunk_size;
8186         }
8187 #if defined(__native_client__) && defined(__native_client_codegen__)
8188         /* In Native Client, we don't re-use thunks, allocate from the */
8189         /* normal code manager paths. */
8190         code = mono_domain_code_reserve (domain, size);
8191 #else
8192         if (fail_tramp)
8193                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8194         else
8195                 code = mono_domain_code_reserve (domain, size);
8196 #endif
8197         start = code;
8198         for (i = 0; i < count; ++i) {
8199                 MonoIMTCheckItem *item = imt_entries [i];
8200                 item->code_target = code;
8201                 if (item->is_equals) {
8202                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8203
8204                         if (item->check_target_idx || fail_case) {
8205                                 if (!item->compare_done || fail_case) {
8206                                         if (amd64_is_imm32 (item->key))
8207                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8208                                         else {
8209                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8210                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8211                                         }
8212                                 }
8213                                 item->jmp_code = code;
8214                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8215                                 if (item->has_target_code) {
8216                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8217                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8218                                 } else {
8219                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8220                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8221                                 }
8222
8223                                 if (fail_case) {
8224                                         amd64_patch (item->jmp_code, code);
8225                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8226                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8227                                         item->jmp_code = NULL;
8228                                 }
8229                         } else {
8230                                 /* enable the commented code to assert on wrong method */
8231 #if 0
8232                                 if (amd64_is_imm32 (item->key))
8233                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8234                                 else {
8235                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8236                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8237                                 }
8238                                 item->jmp_code = code;
8239                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8240                                 /* See the comment below about R10 */
8241                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8242                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8243                                 amd64_patch (item->jmp_code, code);
8244                                 amd64_breakpoint (code);
8245                                 item->jmp_code = NULL;
8246 #else
8247                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8248                                    needs to be preserved.  R10 needs
8249                                    to be preserved for calls which
8250                                    require a runtime generic context,
8251                                    but interface calls don't. */
8252                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8253                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8254 #endif
8255                         }
8256                 } else {
8257                         if (amd64_is_imm32 (item->key))
8258                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8259                         else {
8260                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8261                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8262                         }
8263                         item->jmp_code = code;
8264                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8265                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8266                         else
8267                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8268                 }
8269                 g_assert (code - item->code_target <= item->chunk_size);
8270         }
8271         /* patch the branches to get to the target items */
8272         for (i = 0; i < count; ++i) {
8273                 MonoIMTCheckItem *item = imt_entries [i];
8274                 if (item->jmp_code) {
8275                         if (item->check_target_idx) {
8276                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8277                         }
8278                 }
8279         }
8280
8281         if (!fail_tramp)
8282                 mono_stats.imt_thunks_size += code - start;
8283         g_assert (code - start <= size);
8284
8285         nacl_domain_code_validate(domain, &start, size, &code);
8286         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8287
8288         return start;
8289 }
8290
8291 MonoMethod*
8292 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8293 {
8294         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8295 }
8296
8297 MonoVTable*
8298 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8299 {
8300         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8301 }
8302
8303 GSList*
8304 mono_arch_get_cie_program (void)
8305 {
8306         GSList *l = NULL;
8307
8308         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8309         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8310
8311         return l;
8312 }
8313
8314 #ifndef DISABLE_JIT
8315
8316 MonoInst*
8317 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8318 {
8319         MonoInst *ins = NULL;
8320         int opcode = 0;
8321
8322         if (cmethod->klass == mono_defaults.math_class) {
8323                 if (strcmp (cmethod->name, "Sin") == 0) {
8324                         opcode = OP_SIN;
8325                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8326                         opcode = OP_COS;
8327                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8328                         opcode = OP_SQRT;
8329                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8330                         opcode = OP_ABS;
8331                 }
8332
8333                 if (opcode && fsig->param_count == 1) {
8334                         MONO_INST_NEW (cfg, ins, opcode);
8335                         ins->type = STACK_R8;
8336                         ins->dreg = mono_alloc_freg (cfg);
8337                         ins->sreg1 = args [0]->dreg;
8338                         MONO_ADD_INS (cfg->cbb, ins);
8339                 }
8340
8341                 opcode = 0;
8342                 if (cfg->opt & MONO_OPT_CMOV) {
8343                         if (strcmp (cmethod->name, "Min") == 0) {
8344                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8345                                         opcode = OP_IMIN;
8346                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8347                                         opcode = OP_IMIN_UN;
8348                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8349                                         opcode = OP_LMIN;
8350                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8351                                         opcode = OP_LMIN_UN;
8352                         } else if (strcmp (cmethod->name, "Max") == 0) {
8353                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8354                                         opcode = OP_IMAX;
8355                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8356                                         opcode = OP_IMAX_UN;
8357                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8358                                         opcode = OP_LMAX;
8359                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8360                                         opcode = OP_LMAX_UN;
8361                         }
8362                 }
8363
8364                 if (opcode && fsig->param_count == 2) {
8365                         MONO_INST_NEW (cfg, ins, opcode);
8366                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8367                         ins->dreg = mono_alloc_ireg (cfg);
8368                         ins->sreg1 = args [0]->dreg;
8369                         ins->sreg2 = args [1]->dreg;
8370                         MONO_ADD_INS (cfg->cbb, ins);
8371                 }
8372
8373 #if 0
8374                 /* OP_FREM is not IEEE compatible */
8375                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8376                         MONO_INST_NEW (cfg, ins, OP_FREM);
8377                         ins->inst_i0 = args [0];
8378                         ins->inst_i1 = args [1];
8379                 }
8380 #endif
8381         }
8382
8383         return ins;
8384 }
8385 #endif
8386
8387 gboolean
8388 mono_arch_print_tree (MonoInst *tree, int arity)
8389 {
8390         return 0;
8391 }
8392
8393 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8394
8395 mgreg_t
8396 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8397 {
8398         switch (reg) {
8399         case AMD64_RCX: return ctx->rcx;
8400         case AMD64_RDX: return ctx->rdx;
8401         case AMD64_RBX: return ctx->rbx;
8402         case AMD64_RBP: return ctx->rbp;
8403         case AMD64_RSP: return ctx->rsp;
8404         default:
8405                 return _CTX_REG (ctx, rax, reg);
8406         }
8407 }
8408
8409 void
8410 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8411 {
8412         switch (reg) {
8413         case AMD64_RCX:
8414                 ctx->rcx = val;
8415                 break;
8416         case AMD64_RDX:
8417                 ctx->rdx = val;
8418                 break;
8419         case AMD64_RBX:
8420                 ctx->rbx = val;
8421                 break;
8422         case AMD64_RBP:
8423                 ctx->rbp = val;
8424                 break;
8425         case AMD64_RSP:
8426                 ctx->rsp = val;
8427                 break;
8428         default:
8429                 _CTX_REG (ctx, rax, reg) = val;
8430         }
8431 }
8432
8433 gpointer
8434 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8435 {
8436         gpointer *sp, old_value;
8437         char *bp;
8438
8439         /*Load the spvar*/
8440         bp = MONO_CONTEXT_GET_BP (ctx);
8441         sp = *(gpointer*)(bp + clause->exvar_offset);
8442
8443         old_value = *sp;
8444         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8445                 return old_value;
8446
8447         *sp = new_value;
8448
8449         return old_value;
8450 }
8451
8452 /*
8453  * mono_arch_emit_load_aotconst:
8454  *
8455  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8456  * TARGET from the mscorlib GOT in full-aot code.
8457  * On AMD64, the result is placed into R11.
8458  */
8459 guint8*
8460 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8461 {
8462         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8463         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8464
8465         return code;
8466 }
8467
8468 /*
8469  * mono_arch_get_trampolines:
8470  *
8471  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8472  * for AOT.
8473  */
8474 GSList *
8475 mono_arch_get_trampolines (gboolean aot)
8476 {
8477         return mono_amd64_get_exception_trampolines (aot);
8478 }
8479
8480 /* Soft Debug support */
8481 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8482
8483 /*
8484  * mono_arch_set_breakpoint:
8485  *
8486  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8487  * The location should contain code emitted by OP_SEQ_POINT.
8488  */
8489 void
8490 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8491 {
8492         guint8 *code = ip;
8493         guint8 *orig_code = code;
8494
8495         if (ji->from_aot) {
8496                 guint32 native_offset = ip - (guint8*)ji->code_start;
8497                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8498
8499                 g_assert (info->bp_addrs [native_offset] == 0);
8500                 info->bp_addrs [native_offset] = bp_trigger_page;
8501         } else {
8502                 /*
8503                  * In production, we will use int3 (has to fix the size in the md
8504                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8505                  * instead.
8506                  */
8507                 g_assert (code [0] == 0x90);
8508                 if (breakpoint_size == 8) {
8509                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8510                 } else {
8511                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8512                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8513                 }
8514
8515                 g_assert (code - orig_code == breakpoint_size);
8516         }
8517 }
8518
8519 /*
8520  * mono_arch_clear_breakpoint:
8521  *
8522  *   Clear the breakpoint at IP.
8523  */
8524 void
8525 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8526 {
8527         guint8 *code = ip;
8528         int i;
8529
8530         if (ji->from_aot) {
8531                 guint32 native_offset = ip - (guint8*)ji->code_start;
8532                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8533
8534                 g_assert (info->bp_addrs [native_offset] == 0);
8535                 info->bp_addrs [native_offset] = info;
8536         } else {
8537                 for (i = 0; i < breakpoint_size; ++i)
8538                         x86_nop (code);
8539         }
8540 }
8541
8542 gboolean
8543 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8544 {
8545 #ifdef HOST_WIN32
8546         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8547         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8548                 return TRUE;
8549         else
8550                 return FALSE;
8551 #else
8552         siginfo_t* sinfo = (siginfo_t*) info;
8553         /* Sometimes the address is off by 4 */
8554         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8555                 return TRUE;
8556         else
8557                 return FALSE;
8558 #endif
8559 }
8560
8561 /*
8562  * mono_arch_skip_breakpoint:
8563  *
8564  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8565  * we resume, the instruction is not executed again.
8566  */
8567 void
8568 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8569 {
8570         if (ji->from_aot) {
8571                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8572                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8573         } else {
8574                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8575         }
8576 }
8577
8578 /*
8579  * mono_arch_start_single_stepping:
8580  *
8581  *   Start single stepping.
8582  */
8583 void
8584 mono_arch_start_single_stepping (void)
8585 {
8586         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8587 }
8588
8589 /*
8590  * mono_arch_stop_single_stepping:
8591  *
8592  *   Stop single stepping.
8593  */
8594 void
8595 mono_arch_stop_single_stepping (void)
8596 {
8597         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8598 }
8599
8600 /*
8601  * mono_arch_is_single_step_event:
8602  *
8603  *   Return whenever the machine state in SIGCTX corresponds to a single
8604  * step event.
8605  */
8606 gboolean
8607 mono_arch_is_single_step_event (void *info, void *sigctx)
8608 {
8609 #ifdef HOST_WIN32
8610         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8611         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8612                 return TRUE;
8613         else
8614                 return FALSE;
8615 #else
8616         siginfo_t* sinfo = (siginfo_t*) info;
8617         /* Sometimes the address is off by 4 */
8618         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8619                 return TRUE;
8620         else
8621                 return FALSE;
8622 #endif
8623 }
8624
8625 /*
8626  * mono_arch_skip_single_step:
8627  *
8628  *   Modify CTX so the ip is placed after the single step trigger instruction,
8629  * we resume, the instruction is not executed again.
8630  */
8631 void
8632 mono_arch_skip_single_step (MonoContext *ctx)
8633 {
8634         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8635 }
8636
8637 /*
8638  * mono_arch_create_seq_point_info:
8639  *
8640  *   Return a pointer to a data structure which is used by the sequence
8641  * point implementation in AOTed code.
8642  */
8643 gpointer
8644 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8645 {
8646         SeqPointInfo *info;
8647         MonoJitInfo *ji;
8648         int i;
8649
8650         // FIXME: Add a free function
8651
8652         mono_domain_lock (domain);
8653         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8654                                                                 code);
8655         mono_domain_unlock (domain);
8656
8657         if (!info) {
8658                 ji = mono_jit_info_table_find (domain, (char*)code);
8659                 g_assert (ji);
8660
8661                 // FIXME: Optimize the size
8662                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8663
8664                 info->ss_trigger_page = ss_trigger_page;
8665                 info->bp_trigger_page = bp_trigger_page;
8666                 /* Initialize to a valid address */
8667                 for (i = 0; i < ji->code_size; ++i)
8668                         info->bp_addrs [i] = info;
8669
8670                 mono_domain_lock (domain);
8671                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8672                                                          code, info);
8673                 mono_domain_unlock (domain);
8674         }
8675
8676         return info;
8677 }
8678
8679 void
8680 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8681 {
8682         ext->lmf.previous_lmf = prev_lmf;
8683         /* Mark that this is a MonoLMFExt */
8684         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8685         ext->lmf.rsp = (gssize)ext;
8686 }
8687
8688 #endif
8689
8690 gboolean
8691 mono_arch_opcode_supported (int opcode)
8692 {
8693         switch (opcode) {
8694         case OP_ATOMIC_ADD_I4:
8695         case OP_ATOMIC_ADD_I8:
8696         case OP_ATOMIC_EXCHANGE_I4:
8697         case OP_ATOMIC_EXCHANGE_I8:
8698         case OP_ATOMIC_CAS_I4:
8699         case OP_ATOMIC_CAS_I8:
8700         case OP_ATOMIC_LOAD_I1:
8701         case OP_ATOMIC_LOAD_I2:
8702         case OP_ATOMIC_LOAD_I4:
8703         case OP_ATOMIC_LOAD_I8:
8704         case OP_ATOMIC_LOAD_U1:
8705         case OP_ATOMIC_LOAD_U2:
8706         case OP_ATOMIC_LOAD_U4:
8707         case OP_ATOMIC_LOAD_U8:
8708         case OP_ATOMIC_LOAD_R4:
8709         case OP_ATOMIC_LOAD_R8:
8710         case OP_ATOMIC_STORE_I1:
8711         case OP_ATOMIC_STORE_I2:
8712         case OP_ATOMIC_STORE_I4:
8713         case OP_ATOMIC_STORE_I8:
8714         case OP_ATOMIC_STORE_U1:
8715         case OP_ATOMIC_STORE_U2:
8716         case OP_ATOMIC_STORE_U4:
8717         case OP_ATOMIC_STORE_U8:
8718         case OP_ATOMIC_STORE_R4:
8719         case OP_ATOMIC_STORE_R8:
8720                 return TRUE;
8721         default:
8722                 return FALSE;
8723         }
8724 }