2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/utils/mono-math.h>
30 #include "mini-amd64.h"
31 #include "cpu-amd64.h"
34 * Can't define this in mini-amd64.h cause that would turn on the generic code in
37 #define MONO_ARCH_IMT_REG AMD64_R11
39 static gint lmf_tls_offset = -1;
40 static gint lmf_addr_tls_offset = -1;
41 static gint appdomain_tls_offset = -1;
42 static gint thread_tls_offset = -1;
45 static gboolean optimize_for_xen = TRUE;
47 #define optimize_for_xen 0
50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
57 /* Under windows, the calling convention is never stdcall */
58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
66 static CRITICAL_SECTION mini_arch_mutex;
69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
72 /* On Win64 always reserve first 32 bytes for first four arguments */
73 #define ARGS_OFFSET 48
75 #define ARGS_OFFSET 16
77 #define GP_SCRATCH_REG AMD64_R11
80 * AMD64 register usage:
81 * - callee saved registers are used for global register allocation
82 * - %r11 is used for materializing 64 bit constants in opcodes
83 * - the rest is used for local allocation
87 * Floating point comparison results:
97 mono_arch_regname (int reg)
100 case AMD64_RAX: return "%rax";
101 case AMD64_RBX: return "%rbx";
102 case AMD64_RCX: return "%rcx";
103 case AMD64_RDX: return "%rdx";
104 case AMD64_RSP: return "%rsp";
105 case AMD64_RBP: return "%rbp";
106 case AMD64_RDI: return "%rdi";
107 case AMD64_RSI: return "%rsi";
108 case AMD64_R8: return "%r8";
109 case AMD64_R9: return "%r9";
110 case AMD64_R10: return "%r10";
111 case AMD64_R11: return "%r11";
112 case AMD64_R12: return "%r12";
113 case AMD64_R13: return "%r13";
114 case AMD64_R14: return "%r14";
115 case AMD64_R15: return "%r15";
120 static const char * xmmregs [] = {
121 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
122 "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
126 mono_arch_fregname (int reg)
128 if (reg < AMD64_XMM_NREG)
129 return xmmregs [reg];
134 G_GNUC_UNUSED static void
139 G_GNUC_UNUSED static gboolean
142 static int count = 0;
145 if (!getenv ("COUNT"))
148 if (count == atoi (getenv ("COUNT"))) {
152 if (count > atoi (getenv ("COUNT"))) {
163 return debug_count ();
169 static inline gboolean
170 amd64_is_near_call (guint8 *code)
173 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
176 return code [0] == 0xe8;
180 amd64_patch (unsigned char* code, gpointer target)
185 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
190 if ((code [0] & 0xf8) == 0xb8) {
191 /* amd64_set_reg_template */
192 *(guint64*)(code + 1) = (guint64)target;
194 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
195 /* mov 0(%rip), %dreg */
196 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
198 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
199 /* call *<OFFSET>(%rip) */
200 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
202 else if ((code [0] == 0xe8)) {
204 gint64 disp = (guint8*)target - (guint8*)code;
205 g_assert (amd64_is_imm32 (disp));
206 x86_patch (code, (unsigned char*)target);
209 x86_patch (code, (unsigned char*)target);
213 mono_amd64_patch (unsigned char* code, gpointer target)
215 amd64_patch (code, target);
224 ArgValuetypeAddrInIReg,
225 ArgNone /* only in pair_storage */
233 /* Only if storage == ArgValuetypeInReg */
234 ArgStorage pair_storage [2];
243 gboolean need_stack_align;
249 #define DEBUG(a) if (cfg->verbose_level > 1) a
251 #ifdef PLATFORM_WIN32
254 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
256 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
260 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
262 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
266 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
268 ainfo->offset = *stack_size;
270 if (*gr >= PARAM_REGS) {
271 ainfo->storage = ArgOnStack;
272 (*stack_size) += sizeof (gpointer);
275 ainfo->storage = ArgInIReg;
276 ainfo->reg = param_regs [*gr];
281 #ifdef PLATFORM_WIN32
282 #define FLOAT_PARAM_REGS 4
284 #define FLOAT_PARAM_REGS 8
288 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
290 ainfo->offset = *stack_size;
292 if (*gr >= FLOAT_PARAM_REGS) {
293 ainfo->storage = ArgOnStack;
294 (*stack_size) += sizeof (gpointer);
297 /* A double register */
299 ainfo->storage = ArgInDoubleSSEReg;
301 ainfo->storage = ArgInFloatSSEReg;
307 typedef enum ArgumentClass {
315 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
317 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
320 ptype = mini_type_get_underlying_type (NULL, type);
321 switch (ptype->type) {
322 case MONO_TYPE_BOOLEAN:
332 case MONO_TYPE_STRING:
333 case MONO_TYPE_OBJECT:
334 case MONO_TYPE_CLASS:
335 case MONO_TYPE_SZARRAY:
337 case MONO_TYPE_FNPTR:
338 case MONO_TYPE_ARRAY:
341 class2 = ARG_CLASS_INTEGER;
345 #ifdef PLATFORM_WIN32
346 class2 = ARG_CLASS_INTEGER;
348 class2 = ARG_CLASS_SSE;
352 case MONO_TYPE_TYPEDBYREF:
353 g_assert_not_reached ();
355 case MONO_TYPE_GENERICINST:
356 if (!mono_type_generic_inst_is_valuetype (ptype)) {
357 class2 = ARG_CLASS_INTEGER;
361 case MONO_TYPE_VALUETYPE: {
362 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
365 for (i = 0; i < info->num_fields; ++i) {
367 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
372 g_assert_not_reached ();
376 if (class1 == class2)
378 else if (class1 == ARG_CLASS_NO_CLASS)
380 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
381 class1 = ARG_CLASS_MEMORY;
382 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
383 class1 = ARG_CLASS_INTEGER;
385 class1 = ARG_CLASS_SSE;
391 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
393 guint32 *gr, guint32 *fr, guint32 *stack_size)
395 guint32 size, quad, nquads, i;
396 ArgumentClass args [2];
397 MonoMarshalType *info = NULL;
399 MonoGenericSharingContext tmp_gsctx;
402 * The gsctx currently contains no data, it is only used for checking whenever
403 * open types are allowed, some callers like mono_arch_get_argument_info ()
404 * don't pass it to us, so work around that.
409 klass = mono_class_from_mono_type (type);
410 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
411 #ifndef PLATFORM_WIN32
412 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
413 /* We pass and return vtypes of size 8 in a register */
414 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
418 /* Allways pass in memory */
419 ainfo->offset = *stack_size;
420 *stack_size += ALIGN_TO (size, 8);
421 ainfo->storage = ArgOnStack;
426 /* FIXME: Handle structs smaller than 8 bytes */
427 //if ((size % 8) != 0)
436 /* Always pass in 1 or 2 integer registers */
437 args [0] = ARG_CLASS_INTEGER;
438 args [1] = ARG_CLASS_INTEGER;
439 /* Only the simplest cases are supported */
440 if (is_return && nquads != 1) {
441 args [0] = ARG_CLASS_MEMORY;
442 args [1] = ARG_CLASS_MEMORY;
446 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
447 * The X87 and SSEUP stuff is left out since there are no such types in
450 info = mono_marshal_load_type_info (klass);
453 #ifndef PLATFORM_WIN32
454 if (info->native_size > 16) {
455 ainfo->offset = *stack_size;
456 *stack_size += ALIGN_TO (info->native_size, 8);
457 ainfo->storage = ArgOnStack;
462 switch (info->native_size) {
463 case 1: case 2: case 4: case 8:
467 ainfo->storage = ArgOnStack;
468 ainfo->offset = *stack_size;
469 *stack_size += ALIGN_TO (info->native_size, 8);
472 ainfo->storage = ArgValuetypeAddrInIReg;
474 if (*gr < PARAM_REGS) {
475 ainfo->pair_storage [0] = ArgInIReg;
476 ainfo->pair_regs [0] = param_regs [*gr];
480 ainfo->pair_storage [0] = ArgOnStack;
481 ainfo->offset = *stack_size;
490 args [0] = ARG_CLASS_NO_CLASS;
491 args [1] = ARG_CLASS_NO_CLASS;
492 for (quad = 0; quad < nquads; ++quad) {
495 ArgumentClass class1;
497 if (info->num_fields == 0)
498 class1 = ARG_CLASS_MEMORY;
500 class1 = ARG_CLASS_NO_CLASS;
501 for (i = 0; i < info->num_fields; ++i) {
502 size = mono_marshal_type_size (info->fields [i].field->type,
503 info->fields [i].mspec,
504 &align, TRUE, klass->unicode);
505 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
506 /* Unaligned field */
510 /* Skip fields in other quad */
511 if ((quad == 0) && (info->fields [i].offset >= 8))
513 if ((quad == 1) && (info->fields [i].offset < 8))
516 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
518 g_assert (class1 != ARG_CLASS_NO_CLASS);
519 args [quad] = class1;
523 /* Post merger cleanup */
524 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
525 args [0] = args [1] = ARG_CLASS_MEMORY;
527 /* Allocate registers */
532 ainfo->storage = ArgValuetypeInReg;
533 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
534 for (quad = 0; quad < nquads; ++quad) {
535 switch (args [quad]) {
536 case ARG_CLASS_INTEGER:
537 if (*gr >= PARAM_REGS)
538 args [quad] = ARG_CLASS_MEMORY;
540 ainfo->pair_storage [quad] = ArgInIReg;
542 ainfo->pair_regs [quad] = return_regs [*gr];
544 ainfo->pair_regs [quad] = param_regs [*gr];
549 if (*fr >= FLOAT_PARAM_REGS)
550 args [quad] = ARG_CLASS_MEMORY;
552 ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
553 ainfo->pair_regs [quad] = *fr;
557 case ARG_CLASS_MEMORY:
560 g_assert_not_reached ();
564 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
565 /* Revert possible register assignments */
569 ainfo->offset = *stack_size;
571 *stack_size += ALIGN_TO (info->native_size, 8);
573 *stack_size += nquads * sizeof (gpointer);
574 ainfo->storage = ArgOnStack;
582 * Obtain information about a call according to the calling convention.
583 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
584 * Draft Version 0.23" document for more information.
587 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
591 int n = sig->hasthis + sig->param_count;
592 guint32 stack_size = 0;
596 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
598 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
605 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
606 switch (ret_type->type) {
607 case MONO_TYPE_BOOLEAN:
618 case MONO_TYPE_FNPTR:
619 case MONO_TYPE_CLASS:
620 case MONO_TYPE_OBJECT:
621 case MONO_TYPE_SZARRAY:
622 case MONO_TYPE_ARRAY:
623 case MONO_TYPE_STRING:
624 cinfo->ret.storage = ArgInIReg;
625 cinfo->ret.reg = AMD64_RAX;
629 cinfo->ret.storage = ArgInIReg;
630 cinfo->ret.reg = AMD64_RAX;
633 cinfo->ret.storage = ArgInFloatSSEReg;
634 cinfo->ret.reg = AMD64_XMM0;
637 cinfo->ret.storage = ArgInDoubleSSEReg;
638 cinfo->ret.reg = AMD64_XMM0;
640 case MONO_TYPE_GENERICINST:
641 if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
642 cinfo->ret.storage = ArgInIReg;
643 cinfo->ret.reg = AMD64_RAX;
647 case MONO_TYPE_VALUETYPE: {
648 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
650 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
651 if (cinfo->ret.storage == ArgOnStack)
652 /* The caller passes the address where the value is stored */
653 add_general (&gr, &stack_size, &cinfo->ret);
656 case MONO_TYPE_TYPEDBYREF:
657 /* Same as a valuetype with size 24 */
658 add_general (&gr, &stack_size, &cinfo->ret);
664 g_error ("Can't handle as return value 0x%x", sig->ret->type);
670 add_general (&gr, &stack_size, cinfo->args + 0);
672 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
674 fr = FLOAT_PARAM_REGS;
676 /* Emit the signature cookie just before the implicit arguments */
677 add_general (&gr, &stack_size, &cinfo->sig_cookie);
680 for (i = 0; i < sig->param_count; ++i) {
681 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
684 #ifdef PLATFORM_WIN32
685 /* The float param registers and other param registers must be the same index on Windows x64.*/
692 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
693 /* We allways pass the sig cookie on the stack for simplicity */
695 * Prevent implicit arguments + the sig cookie from being passed
699 fr = FLOAT_PARAM_REGS;
701 /* Emit the signature cookie just before the implicit arguments */
702 add_general (&gr, &stack_size, &cinfo->sig_cookie);
705 if (sig->params [i]->byref) {
706 add_general (&gr, &stack_size, ainfo);
709 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
710 switch (ptype->type) {
711 case MONO_TYPE_BOOLEAN:
714 add_general (&gr, &stack_size, ainfo);
719 add_general (&gr, &stack_size, ainfo);
723 add_general (&gr, &stack_size, ainfo);
728 case MONO_TYPE_FNPTR:
729 case MONO_TYPE_CLASS:
730 case MONO_TYPE_OBJECT:
731 case MONO_TYPE_STRING:
732 case MONO_TYPE_SZARRAY:
733 case MONO_TYPE_ARRAY:
734 add_general (&gr, &stack_size, ainfo);
736 case MONO_TYPE_GENERICINST:
737 if (!mono_type_generic_inst_is_valuetype (ptype)) {
738 add_general (&gr, &stack_size, ainfo);
742 case MONO_TYPE_VALUETYPE:
743 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
745 case MONO_TYPE_TYPEDBYREF:
746 #ifdef PLATFORM_WIN32
747 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
749 stack_size += sizeof (MonoTypedRef);
750 ainfo->storage = ArgOnStack;
755 add_general (&gr, &stack_size, ainfo);
758 add_float (&fr, &stack_size, ainfo, FALSE);
761 add_float (&fr, &stack_size, ainfo, TRUE);
764 g_assert_not_reached ();
768 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
770 fr = FLOAT_PARAM_REGS;
772 /* Emit the signature cookie just before the implicit arguments */
773 add_general (&gr, &stack_size, &cinfo->sig_cookie);
776 #ifdef PLATFORM_WIN32
777 // There always is 32 bytes reserved on the stack when calling on Winx64
781 if (stack_size & 0x8) {
782 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
783 cinfo->need_stack_align = TRUE;
787 cinfo->stack_usage = stack_size;
788 cinfo->reg_usage = gr;
789 cinfo->freg_usage = fr;
794 * mono_arch_get_argument_info:
795 * @csig: a method signature
796 * @param_count: the number of parameters to consider
797 * @arg_info: an array to store the result infos
799 * Gathers information on parameters such as size, alignment and
800 * padding. arg_info should be large enought to hold param_count + 1 entries.
802 * Returns the size of the argument area on the stack.
805 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
808 CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
809 guint32 args_size = cinfo->stack_usage;
811 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
813 arg_info [0].offset = 0;
816 for (k = 0; k < param_count; k++) {
817 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
819 arg_info [k + 1].size = 0;
828 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
831 __asm__ __volatile__ ("cpuid"
832 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
846 * Initialize the cpu to execute managed code.
849 mono_arch_cpu_init (void)
854 /* spec compliance requires running with double precision */
855 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
856 fpcw &= ~X86_FPCW_PRECC_MASK;
857 fpcw |= X86_FPCW_PREC_DOUBLE;
858 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
859 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
861 /* TODO: This is crashing on Win64 right now.
862 * _control87 (_PC_53, MCW_PC);
868 * Initialize architecture specific code.
871 mono_arch_init (void)
873 InitializeCriticalSection (&mini_arch_mutex);
877 * Cleanup architecture specific code.
880 mono_arch_cleanup (void)
882 DeleteCriticalSection (&mini_arch_mutex);
886 * This function returns the optimizations supported on this cpu.
889 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
891 int eax, ebx, ecx, edx;
897 /* Feature Flags function, flags returned in EDX. */
898 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
899 if (edx & (1 << 15)) {
900 opts |= MONO_OPT_CMOV;
902 opts |= MONO_OPT_FCMOV;
904 *exclude_mask |= MONO_OPT_FCMOV;
906 *exclude_mask |= MONO_OPT_CMOV;
913 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
918 for (i = 0; i < cfg->num_varinfo; i++) {
919 MonoInst *ins = cfg->varinfo [i];
920 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
923 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
926 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
927 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
930 if (mono_is_regsize_var (ins->inst_vtype)) {
931 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
932 g_assert (i == vmv->idx);
933 vars = g_list_prepend (vars, vmv);
937 vars = mono_varlist_sort (cfg, vars, 0);
943 * mono_arch_compute_omit_fp:
945 * Determine whenever the frame pointer can be eliminated.
948 mono_arch_compute_omit_fp (MonoCompile *cfg)
950 MonoMethodSignature *sig;
951 MonoMethodHeader *header;
955 if (cfg->arch.omit_fp_computed)
958 header = mono_method_get_header (cfg->method);
960 sig = mono_method_signature (cfg->method);
962 if (!cfg->arch.cinfo)
963 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
964 cinfo = cfg->arch.cinfo;
967 * FIXME: Remove some of the restrictions.
969 cfg->arch.omit_fp = TRUE;
970 cfg->arch.omit_fp_computed = TRUE;
972 if (cfg->disable_omit_fp)
973 cfg->arch.omit_fp = FALSE;
975 if (!debug_omit_fp ())
976 cfg->arch.omit_fp = FALSE;
978 if (cfg->method->save_lmf)
979 cfg->arch.omit_fp = FALSE;
981 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
982 cfg->arch.omit_fp = FALSE;
983 if (header->num_clauses)
984 cfg->arch.omit_fp = FALSE;
986 cfg->arch.omit_fp = FALSE;
987 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
988 cfg->arch.omit_fp = FALSE;
989 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
990 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
991 cfg->arch.omit_fp = FALSE;
992 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
993 ArgInfo *ainfo = &cinfo->args [i];
995 if (ainfo->storage == ArgOnStack) {
997 * The stack offset can only be determined when the frame
1000 cfg->arch.omit_fp = FALSE;
1005 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1006 MonoInst *ins = cfg->varinfo [i];
1009 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1014 mono_arch_get_global_int_regs (MonoCompile *cfg)
1018 mono_arch_compute_omit_fp (cfg);
1020 if (cfg->globalra) {
1021 if (cfg->arch.omit_fp)
1022 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1024 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1025 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1026 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1027 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1028 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1030 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1031 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1032 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1033 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1034 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1035 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1036 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1037 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1039 if (cfg->arch.omit_fp)
1040 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1042 /* We use the callee saved registers for global allocation */
1043 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1044 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1045 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1046 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1047 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1048 #ifdef PLATFORM_WIN32
1049 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1050 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1058 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1063 /* All XMM registers */
1064 for (i = 0; i < 16; ++i)
1065 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1071 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1073 static GList *r = NULL;
1078 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1079 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1080 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1081 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1082 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1083 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1085 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1086 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1087 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1088 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1089 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1090 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1091 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1092 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1094 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1101 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1104 static GList *r = NULL;
1109 for (i = 0; i < AMD64_XMM_NREG; ++i)
1110 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1112 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1119 * mono_arch_regalloc_cost:
1121 * Return the cost, in number of memory references, of the action of
1122 * allocating the variable VMV into a register during global register
1126 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1128 MonoInst *ins = cfg->varinfo [vmv->idx];
1130 if (cfg->method->save_lmf)
1131 /* The register is already saved */
1132 /* substract 1 for the invisible store in the prolog */
1133 return (ins->opcode == OP_ARG) ? 0 : 1;
1136 return (ins->opcode == OP_ARG) ? 1 : 2;
1140 * mono_arch_fill_argument_info:
1142 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1146 mono_arch_fill_argument_info (MonoCompile *cfg)
1148 MonoMethodSignature *sig;
1149 MonoMethodHeader *header;
1154 header = mono_method_get_header (cfg->method);
1156 sig = mono_method_signature (cfg->method);
1158 cinfo = cfg->arch.cinfo;
1161 * Contrary to mono_arch_allocate_vars (), the information should describe
1162 * where the arguments are at the beginning of the method, not where they can be
1163 * accessed during the execution of the method. The later makes no sense for the
1164 * global register allocator, since a variable can be in more than one location.
1166 if (sig->ret->type != MONO_TYPE_VOID) {
1167 switch (cinfo->ret.storage) {
1169 case ArgInFloatSSEReg:
1170 case ArgInDoubleSSEReg:
1171 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1172 cfg->vret_addr->opcode = OP_REGVAR;
1173 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1176 cfg->ret->opcode = OP_REGVAR;
1177 cfg->ret->inst_c0 = cinfo->ret.reg;
1180 case ArgValuetypeInReg:
1181 cfg->ret->opcode = OP_REGOFFSET;
1182 cfg->ret->inst_basereg = -1;
1183 cfg->ret->inst_offset = -1;
1186 g_assert_not_reached ();
1190 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1191 ArgInfo *ainfo = &cinfo->args [i];
1194 ins = cfg->args [i];
1196 if (sig->hasthis && (i == 0))
1197 arg_type = &mono_defaults.object_class->byval_arg;
1199 arg_type = sig->params [i - sig->hasthis];
1201 switch (ainfo->storage) {
1203 case ArgInFloatSSEReg:
1204 case ArgInDoubleSSEReg:
1205 ins->opcode = OP_REGVAR;
1206 ins->inst_c0 = ainfo->reg;
1209 ins->opcode = OP_REGOFFSET;
1210 ins->inst_basereg = -1;
1211 ins->inst_offset = -1;
1213 case ArgValuetypeInReg:
1215 ins->opcode = OP_NOP;
1218 g_assert_not_reached ();
1224 mono_arch_allocate_vars (MonoCompile *cfg)
1226 MonoMethodSignature *sig;
1227 MonoMethodHeader *header;
1230 guint32 locals_stack_size, locals_stack_align;
1234 header = mono_method_get_header (cfg->method);
1236 sig = mono_method_signature (cfg->method);
1238 cinfo = cfg->arch.cinfo;
1240 mono_arch_compute_omit_fp (cfg);
1243 * We use the ABI calling conventions for managed code as well.
1244 * Exception: valuetypes are never passed or returned in registers.
1247 if (cfg->arch.omit_fp) {
1248 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1249 cfg->frame_reg = AMD64_RSP;
1252 /* Locals are allocated backwards from %fp */
1253 cfg->frame_reg = AMD64_RBP;
1257 if (cfg->method->save_lmf) {
1258 /* Reserve stack space for saving LMF */
1259 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1260 g_assert (offset == 0);
1261 if (cfg->arch.omit_fp) {
1262 cfg->arch.lmf_offset = offset;
1263 offset += sizeof (MonoLMF);
1266 offset += sizeof (MonoLMF);
1267 cfg->arch.lmf_offset = -offset;
1270 if (cfg->arch.omit_fp)
1271 cfg->arch.reg_save_area_offset = offset;
1272 /* Reserve space for caller saved registers */
1273 for (i = 0; i < AMD64_NREG; ++i)
1274 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1275 offset += sizeof (gpointer);
1279 if (sig->ret->type != MONO_TYPE_VOID) {
1280 switch (cinfo->ret.storage) {
1282 case ArgInFloatSSEReg:
1283 case ArgInDoubleSSEReg:
1284 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1285 if (cfg->globalra) {
1286 cfg->vret_addr->opcode = OP_REGVAR;
1287 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1289 /* The register is volatile */
1290 cfg->vret_addr->opcode = OP_REGOFFSET;
1291 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1292 if (cfg->arch.omit_fp) {
1293 cfg->vret_addr->inst_offset = offset;
1297 cfg->vret_addr->inst_offset = -offset;
1299 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1300 printf ("vret_addr =");
1301 mono_print_ins (cfg->vret_addr);
1306 cfg->ret->opcode = OP_REGVAR;
1307 cfg->ret->inst_c0 = cinfo->ret.reg;
1310 case ArgValuetypeInReg:
1311 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1312 cfg->ret->opcode = OP_REGOFFSET;
1313 cfg->ret->inst_basereg = cfg->frame_reg;
1314 if (cfg->arch.omit_fp) {
1315 cfg->ret->inst_offset = offset;
1319 cfg->ret->inst_offset = - offset;
1323 g_assert_not_reached ();
1326 cfg->ret->dreg = cfg->ret->inst_c0;
1329 /* Allocate locals */
1330 if (!cfg->globalra) {
1331 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1332 if (locals_stack_align) {
1333 offset += (locals_stack_align - 1);
1334 offset &= ~(locals_stack_align - 1);
1336 if (cfg->arch.omit_fp) {
1337 cfg->locals_min_stack_offset = offset;
1338 cfg->locals_max_stack_offset = offset + locals_stack_size;
1340 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1341 cfg->locals_max_stack_offset = - offset;
1344 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1345 if (offsets [i] != -1) {
1346 MonoInst *ins = cfg->varinfo [i];
1347 ins->opcode = OP_REGOFFSET;
1348 ins->inst_basereg = cfg->frame_reg;
1349 if (cfg->arch.omit_fp)
1350 ins->inst_offset = (offset + offsets [i]);
1352 ins->inst_offset = - (offset + offsets [i]);
1353 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1356 offset += locals_stack_size;
1359 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1360 g_assert (!cfg->arch.omit_fp);
1361 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1362 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1365 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1366 ins = cfg->args [i];
1367 if (ins->opcode != OP_REGVAR) {
1368 ArgInfo *ainfo = &cinfo->args [i];
1369 gboolean inreg = TRUE;
1372 if (sig->hasthis && (i == 0))
1373 arg_type = &mono_defaults.object_class->byval_arg;
1375 arg_type = sig->params [i - sig->hasthis];
1377 if (cfg->globalra) {
1378 /* The new allocator needs info about the original locations of the arguments */
1379 switch (ainfo->storage) {
1381 case ArgInFloatSSEReg:
1382 case ArgInDoubleSSEReg:
1383 ins->opcode = OP_REGVAR;
1384 ins->inst_c0 = ainfo->reg;
1387 g_assert (!cfg->arch.omit_fp);
1388 ins->opcode = OP_REGOFFSET;
1389 ins->inst_basereg = cfg->frame_reg;
1390 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1392 case ArgValuetypeInReg:
1393 ins->opcode = OP_REGOFFSET;
1394 ins->inst_basereg = cfg->frame_reg;
1395 /* These arguments are saved to the stack in the prolog */
1396 offset = ALIGN_TO (offset, sizeof (gpointer));
1397 if (cfg->arch.omit_fp) {
1398 ins->inst_offset = offset;
1399 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1401 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1402 ins->inst_offset = - offset;
1406 g_assert_not_reached ();
1412 /* FIXME: Allocate volatile arguments to registers */
1413 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1417 * Under AMD64, all registers used to pass arguments to functions
1418 * are volatile across calls.
1419 * FIXME: Optimize this.
1421 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1424 ins->opcode = OP_REGOFFSET;
1426 switch (ainfo->storage) {
1428 case ArgInFloatSSEReg:
1429 case ArgInDoubleSSEReg:
1431 ins->opcode = OP_REGVAR;
1432 ins->dreg = ainfo->reg;
1436 g_assert (!cfg->arch.omit_fp);
1437 ins->opcode = OP_REGOFFSET;
1438 ins->inst_basereg = cfg->frame_reg;
1439 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1441 case ArgValuetypeInReg:
1443 case ArgValuetypeAddrInIReg: {
1445 g_assert (!cfg->arch.omit_fp);
1447 MONO_INST_NEW (cfg, indir, 0);
1448 indir->opcode = OP_REGOFFSET;
1449 if (ainfo->pair_storage [0] == ArgInIReg) {
1450 indir->inst_basereg = cfg->frame_reg;
1451 offset = ALIGN_TO (offset, sizeof (gpointer));
1452 offset += (sizeof (gpointer));
1453 indir->inst_offset = - offset;
1456 indir->inst_basereg = cfg->frame_reg;
1457 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1460 ins->opcode = OP_VTARG_ADDR;
1461 ins->inst_left = indir;
1469 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1470 ins->opcode = OP_REGOFFSET;
1471 ins->inst_basereg = cfg->frame_reg;
1472 /* These arguments are saved to the stack in the prolog */
1473 offset = ALIGN_TO (offset, sizeof (gpointer));
1474 if (cfg->arch.omit_fp) {
1475 ins->inst_offset = offset;
1476 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1478 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1479 ins->inst_offset = - offset;
1485 cfg->stack_offset = offset;
1489 mono_arch_create_vars (MonoCompile *cfg)
1491 MonoMethodSignature *sig;
1494 sig = mono_method_signature (cfg->method);
1496 if (!cfg->arch.cinfo)
1497 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1498 cinfo = cfg->arch.cinfo;
1500 if (cinfo->ret.storage == ArgValuetypeInReg)
1501 cfg->ret_var_is_local = TRUE;
1503 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1504 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1505 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1506 printf ("vret_addr = ");
1507 mono_print_ins (cfg->vret_addr);
1513 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1519 MONO_INST_NEW (cfg, ins, OP_MOVE);
1520 ins->dreg = mono_alloc_ireg (cfg);
1521 ins->sreg1 = tree->dreg;
1522 MONO_ADD_INS (cfg->cbb, ins);
1523 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1525 case ArgInFloatSSEReg:
1526 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1527 ins->dreg = mono_alloc_freg (cfg);
1528 ins->sreg1 = tree->dreg;
1529 MONO_ADD_INS (cfg->cbb, ins);
1531 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1533 case ArgInDoubleSSEReg:
1534 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1535 ins->dreg = mono_alloc_freg (cfg);
1536 ins->sreg1 = tree->dreg;
1537 MONO_ADD_INS (cfg->cbb, ins);
1539 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1543 g_assert_not_reached ();
1548 arg_storage_to_load_membase (ArgStorage storage)
1552 return OP_LOAD_MEMBASE;
1553 case ArgInDoubleSSEReg:
1554 return OP_LOADR8_MEMBASE;
1555 case ArgInFloatSSEReg:
1556 return OP_LOADR4_MEMBASE;
1558 g_assert_not_reached ();
1565 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1568 MonoMethodSignature *tmp_sig;
1571 if (call->tail_call)
1574 /* FIXME: Add support for signature tokens to AOT */
1575 cfg->disable_aot = TRUE;
1577 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1580 * mono_ArgIterator_Setup assumes the signature cookie is
1581 * passed first and all the arguments which were before it are
1582 * passed on the stack after the signature. So compensate by
1583 * passing a different signature.
1585 tmp_sig = mono_metadata_signature_dup (call->signature);
1586 tmp_sig->param_count -= call->signature->sentinelpos;
1587 tmp_sig->sentinelpos = 0;
1588 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1590 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1591 sig_arg->dreg = mono_alloc_ireg (cfg);
1592 sig_arg->inst_p0 = tmp_sig;
1593 MONO_ADD_INS (cfg->cbb, sig_arg);
1595 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1596 arg->sreg1 = sig_arg->dreg;
1597 MONO_ADD_INS (cfg->cbb, arg);
1601 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1604 MonoMethodSignature *sig;
1605 int i, n, stack_size;
1611 sig = call->signature;
1612 n = sig->param_count + sig->hasthis;
1614 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1616 if (COMPILE_LLVM (cfg)) {
1617 for (i = 0; i < n; ++i) {
1620 ainfo = cinfo->args + i;
1622 in = call->args [i];
1624 /* Simply remember the arguments */
1625 switch (ainfo->storage) {
1627 MONO_INST_NEW (cfg, ins, OP_MOVE);
1628 ins->dreg = mono_alloc_ireg (cfg);
1629 ins->sreg1 = in->dreg;
1631 case ArgInDoubleSSEReg:
1632 case ArgInFloatSSEReg:
1633 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1634 ins->dreg = mono_alloc_freg (cfg);
1635 ins->sreg1 = in->dreg;
1638 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1639 cfg->exception_message = g_strdup ("vtype argument");
1640 cfg->disable_llvm = TRUE;
1642 MONO_INST_NEW (cfg, ins, OP_MOVE);
1643 ins->dreg = mono_alloc_ireg (cfg);
1644 ins->sreg1 = in->dreg;
1648 cfg->exception_message = g_strdup ("ainfo->storage");
1649 cfg->disable_llvm = TRUE;
1653 if (!cfg->disable_llvm) {
1654 MONO_ADD_INS (cfg->cbb, ins);
1655 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, 0, FALSE);
1661 if (cinfo->need_stack_align) {
1662 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1666 * Emit all parameters passed in registers in non-reverse order for better readability
1667 * and to help the optimization in emit_prolog ().
1669 for (i = 0; i < n; ++i) {
1670 ainfo = cinfo->args + i;
1672 in = call->args [i];
1674 if (ainfo->storage == ArgInIReg)
1675 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1678 for (i = n - 1; i >= 0; --i) {
1679 ainfo = cinfo->args + i;
1681 in = call->args [i];
1683 switch (ainfo->storage) {
1687 case ArgInFloatSSEReg:
1688 case ArgInDoubleSSEReg:
1689 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1692 case ArgValuetypeInReg:
1693 case ArgValuetypeAddrInIReg:
1694 if (ainfo->storage == ArgOnStack && call->tail_call) {
1695 MonoInst *call_inst = (MonoInst*)call;
1696 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1697 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1698 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1702 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1703 size = sizeof (MonoTypedRef);
1704 align = sizeof (gpointer);
1708 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1711 * Other backends use mono_type_stack_size (), but that
1712 * aligns the size to 8, which is larger than the size of
1713 * the source, leading to reads of invalid memory if the
1714 * source is at the end of address space.
1716 size = mono_class_value_size (in->klass, &align);
1719 g_assert (in->klass);
1722 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1723 arg->sreg1 = in->dreg;
1724 arg->klass = in->klass;
1725 arg->backend.size = size;
1726 arg->inst_p0 = call;
1727 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1728 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1730 MONO_ADD_INS (cfg->cbb, arg);
1733 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1734 arg->sreg1 = in->dreg;
1735 if (!sig->params [i - sig->hasthis]->byref) {
1736 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1737 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1738 arg->opcode = OP_STORER4_MEMBASE_REG;
1739 arg->inst_destbasereg = X86_ESP;
1740 arg->inst_offset = 0;
1741 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1742 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1743 arg->opcode = OP_STORER8_MEMBASE_REG;
1744 arg->inst_destbasereg = X86_ESP;
1745 arg->inst_offset = 0;
1748 MONO_ADD_INS (cfg->cbb, arg);
1752 g_assert_not_reached ();
1755 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1756 /* Emit the signature cookie just before the implicit arguments */
1757 emit_sig_cookie (cfg, call, cinfo);
1760 /* Handle the case where there are no implicit arguments */
1761 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1762 emit_sig_cookie (cfg, call, cinfo);
1764 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1767 if (cinfo->ret.storage == ArgValuetypeInReg) {
1768 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1770 * Tell the JIT to use a more efficient calling convention: call using
1771 * OP_CALL, compute the result location after the call, and save the
1774 call->vret_in_reg = TRUE;
1776 * Nullify the instruction computing the vret addr to enable
1777 * future optimizations.
1780 NULLIFY_INS (call->vret_var);
1782 if (call->tail_call)
1785 * The valuetype is in RAX:RDX after the call, need to be copied to
1786 * the stack. Push the address here, so the call instruction can
1789 if (!cfg->arch.vret_addr_loc) {
1790 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1791 /* Prevent it from being register allocated or optimized away */
1792 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1795 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1799 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1800 vtarg->sreg1 = call->vret_var->dreg;
1801 vtarg->dreg = mono_alloc_preg (cfg);
1802 MONO_ADD_INS (cfg->cbb, vtarg);
1804 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1808 #ifdef PLATFORM_WIN32
1809 if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1810 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1814 if (cfg->method->save_lmf) {
1815 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1816 MONO_ADD_INS (cfg->cbb, arg);
1819 call->stack_usage = cinfo->stack_usage;
1823 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1826 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1827 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1828 int size = ins->backend.size;
1830 if (ainfo->storage == ArgValuetypeInReg) {
1834 for (part = 0; part < 2; ++part) {
1835 if (ainfo->pair_storage [part] == ArgNone)
1838 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
1839 load->inst_basereg = src->dreg;
1840 load->inst_offset = part * sizeof (gpointer);
1842 switch (ainfo->pair_storage [part]) {
1844 load->dreg = mono_alloc_ireg (cfg);
1846 case ArgInDoubleSSEReg:
1847 case ArgInFloatSSEReg:
1848 load->dreg = mono_alloc_freg (cfg);
1851 g_assert_not_reached ();
1853 MONO_ADD_INS (cfg->cbb, load);
1855 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
1857 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
1858 MonoInst *vtaddr, *load;
1859 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
1861 MONO_INST_NEW (cfg, load, OP_LDADDR);
1862 load->inst_p0 = vtaddr;
1863 vtaddr->flags |= MONO_INST_INDIRECT;
1864 load->type = STACK_MP;
1865 load->klass = vtaddr->klass;
1866 load->dreg = mono_alloc_ireg (cfg);
1867 MONO_ADD_INS (cfg->cbb, load);
1868 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
1870 if (ainfo->pair_storage [0] == ArgInIReg) {
1871 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
1872 arg->dreg = mono_alloc_ireg (cfg);
1873 arg->sreg1 = load->dreg;
1875 MONO_ADD_INS (cfg->cbb, arg);
1876 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
1878 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1879 arg->sreg1 = load->dreg;
1880 MONO_ADD_INS (cfg->cbb, arg);
1884 /* Can't use this for < 8 since it does an 8 byte memory load */
1885 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1886 arg->inst_basereg = src->dreg;
1887 arg->inst_offset = 0;
1888 MONO_ADD_INS (cfg->cbb, arg);
1889 } else if (size <= 40) {
1890 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
1891 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1893 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1894 arg->inst_basereg = src->dreg;
1895 arg->inst_offset = 0;
1896 arg->inst_imm = size;
1897 MONO_ADD_INS (cfg->cbb, arg);
1903 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1905 MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
1908 if (ret->type == MONO_TYPE_R4) {
1909 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
1911 } else if (ret->type == MONO_TYPE_R8) {
1912 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1917 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1920 #define EMIT_COND_BRANCH(ins,cond,sign) \
1921 if (ins->flags & MONO_INST_BRLABEL) { \
1922 if (ins->inst_i0->inst_c0) { \
1923 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1925 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1926 if ((cfg->opt & MONO_OPT_BRANCH) && \
1927 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1928 x86_branch8 (code, cond, 0, sign); \
1930 x86_branch32 (code, cond, 0, sign); \
1933 if (ins->inst_true_bb->native_offset) { \
1934 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1936 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1937 if ((cfg->opt & MONO_OPT_BRANCH) && \
1938 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1939 x86_branch8 (code, cond, 0, sign); \
1941 x86_branch32 (code, cond, 0, sign); \
1945 /* emit an exception if condition is fail */
1946 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1948 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1949 if (tins == NULL) { \
1950 mono_add_patch_info (cfg, code - cfg->native_code, \
1951 MONO_PATCH_INFO_EXC, exc_name); \
1952 x86_branch32 (code, cond, 0, signed); \
1954 EMIT_COND_BRANCH (tins, cond, signed); \
1958 #define EMIT_FPCOMPARE(code) do { \
1959 amd64_fcompp (code); \
1960 amd64_fnstsw (code); \
1963 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1964 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1965 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1966 amd64_ ##op (code); \
1967 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1968 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1972 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1974 gboolean no_patch = FALSE;
1977 * FIXME: Add support for thunks
1980 gboolean near_call = FALSE;
1983 * Indirect calls are expensive so try to make a near call if possible.
1984 * The caller memory is allocated by the code manager so it is
1985 * guaranteed to be at a 32 bit offset.
1988 if (patch_type != MONO_PATCH_INFO_ABS) {
1989 /* The target is in memory allocated using the code manager */
1992 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1993 if (((MonoMethod*)data)->klass->image->aot_module)
1994 /* The callee might be an AOT method */
1996 if (((MonoMethod*)data)->dynamic)
1997 /* The target is in malloc-ed memory */
2001 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2003 * The call might go directly to a native function without
2006 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2008 gconstpointer target = mono_icall_get_wrapper (mi);
2009 if ((((guint64)target) >> 32) != 0)
2015 if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2017 * This is not really an optimization, but required because the
2018 * generic class init trampolines use R11 to pass the vtable.
2022 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2024 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2025 strstr (cfg->method->name, info->name)) {
2026 /* A call to the wrapped function */
2027 if ((((guint64)data) >> 32) == 0)
2031 else if (info->func == info->wrapper) {
2033 if ((((guint64)info->func) >> 32) == 0)
2037 /* See the comment in mono_codegen () */
2038 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2042 else if ((((guint64)data) >> 32) == 0) {
2049 if (cfg->method->dynamic)
2050 /* These methods are allocated using malloc */
2053 if (cfg->compile_aot) {
2058 #ifdef MONO_ARCH_NOMAP32BIT
2064 * Align the call displacement to an address divisible by 4 so it does
2065 * not span cache lines. This is required for code patching to work on SMP
2068 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2069 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2070 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2071 amd64_call_code (code, 0);
2074 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2075 amd64_set_reg_template (code, GP_SCRATCH_REG);
2076 amd64_call_reg (code, GP_SCRATCH_REG);
2083 static inline guint8*
2084 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2086 #ifdef PLATFORM_WIN32
2087 if (win64_adjust_stack)
2088 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2090 code = emit_call_body (cfg, code, patch_type, data);
2091 #ifdef PLATFORM_WIN32
2092 if (win64_adjust_stack)
2093 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2100 store_membase_imm_to_store_membase_reg (int opcode)
2103 case OP_STORE_MEMBASE_IMM:
2104 return OP_STORE_MEMBASE_REG;
2105 case OP_STOREI4_MEMBASE_IMM:
2106 return OP_STOREI4_MEMBASE_REG;
2107 case OP_STOREI8_MEMBASE_IMM:
2108 return OP_STOREI8_MEMBASE_REG;
2114 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2117 * mono_arch_peephole_pass_1:
2119 * Perform peephole opts which should/can be performed before local regalloc
2122 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2126 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2127 MonoInst *last_ins = ins->prev;
2129 switch (ins->opcode) {
2133 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2135 * X86_LEA is like ADD, but doesn't have the
2136 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2137 * its operand to 64 bit.
2139 ins->opcode = OP_X86_LEA_MEMBASE;
2140 ins->inst_basereg = ins->sreg1;
2145 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2149 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2150 * the latter has length 2-3 instead of 6 (reverse constant
2151 * propagation). These instruction sequences are very common
2152 * in the initlocals bblock.
2154 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2155 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2156 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2157 ins2->sreg1 = ins->dreg;
2158 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2160 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2169 case OP_COMPARE_IMM:
2170 case OP_LCOMPARE_IMM:
2171 /* OP_COMPARE_IMM (reg, 0)
2173 * OP_AMD64_TEST_NULL (reg)
2176 ins->opcode = OP_AMD64_TEST_NULL;
2178 case OP_ICOMPARE_IMM:
2180 ins->opcode = OP_X86_TEST_NULL;
2182 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2184 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2185 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2187 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2188 * OP_COMPARE_IMM reg, imm
2190 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2192 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2193 ins->inst_basereg == last_ins->inst_destbasereg &&
2194 ins->inst_offset == last_ins->inst_offset) {
2195 ins->opcode = OP_ICOMPARE_IMM;
2196 ins->sreg1 = last_ins->sreg1;
2198 /* check if we can remove cmp reg,0 with test null */
2200 ins->opcode = OP_X86_TEST_NULL;
2206 mono_peephole_ins (bb, ins);
2211 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2215 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2216 switch (ins->opcode) {
2219 /* reg = 0 -> XOR (reg, reg) */
2220 /* XOR sets cflags on x86, so we cant do it always */
2221 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2222 ins->opcode = OP_LXOR;
2223 ins->sreg1 = ins->dreg;
2224 ins->sreg2 = ins->dreg;
2232 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2233 * 0 result into 64 bits.
2235 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2236 ins->opcode = OP_IXOR;
2240 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2244 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2245 * the latter has length 2-3 instead of 6 (reverse constant
2246 * propagation). These instruction sequences are very common
2247 * in the initlocals bblock.
2249 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2250 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2251 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2252 ins2->sreg1 = ins->dreg;
2253 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2255 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2265 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2266 ins->opcode = OP_X86_INC_REG;
2269 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2270 ins->opcode = OP_X86_DEC_REG;
2274 mono_peephole_ins (bb, ins);
2278 #define NEW_INS(cfg,ins,dest,op) do { \
2279 MONO_INST_NEW ((cfg), (dest), (op)); \
2280 (dest)->cil_code = (ins)->cil_code; \
2281 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2285 * mono_arch_lowering_pass:
2287 * Converts complex opcodes into simpler ones so that each IR instruction
2288 * corresponds to one machine instruction.
2291 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2293 MonoInst *ins, *n, *temp;
2296 * FIXME: Need to add more instructions, but the current machine
2297 * description can't model some parts of the composite instructions like
2300 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2301 switch (ins->opcode) {
2305 case OP_IDIV_UN_IMM:
2306 case OP_IREM_UN_IMM:
2307 mono_decompose_op_imm (cfg, bb, ins);
2310 /* Keep the opcode if we can implement it efficiently */
2311 if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2312 mono_decompose_op_imm (cfg, bb, ins);
2314 case OP_COMPARE_IMM:
2315 case OP_LCOMPARE_IMM:
2316 if (!amd64_is_imm32 (ins->inst_imm)) {
2317 NEW_INS (cfg, ins, temp, OP_I8CONST);
2318 temp->inst_c0 = ins->inst_imm;
2319 temp->dreg = mono_alloc_ireg (cfg);
2320 ins->opcode = OP_COMPARE;
2321 ins->sreg2 = temp->dreg;
2324 case OP_LOAD_MEMBASE:
2325 case OP_LOADI8_MEMBASE:
2326 if (!amd64_is_imm32 (ins->inst_offset)) {
2327 NEW_INS (cfg, ins, temp, OP_I8CONST);
2328 temp->inst_c0 = ins->inst_offset;
2329 temp->dreg = mono_alloc_ireg (cfg);
2330 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2331 ins->inst_indexreg = temp->dreg;
2334 case OP_STORE_MEMBASE_IMM:
2335 case OP_STOREI8_MEMBASE_IMM:
2336 if (!amd64_is_imm32 (ins->inst_imm)) {
2337 NEW_INS (cfg, ins, temp, OP_I8CONST);
2338 temp->inst_c0 = ins->inst_imm;
2339 temp->dreg = mono_alloc_ireg (cfg);
2340 ins->opcode = OP_STOREI8_MEMBASE_REG;
2341 ins->sreg1 = temp->dreg;
2349 bb->max_vreg = cfg->next_vreg;
2353 branch_cc_table [] = {
2354 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2355 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2356 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2359 /* Maps CMP_... constants to X86_CC_... constants */
2362 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2363 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2367 cc_signed_table [] = {
2368 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2369 FALSE, FALSE, FALSE, FALSE
2372 /*#include "cprop.c"*/
2374 static unsigned char*
2375 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2377 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2380 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2382 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2386 static unsigned char*
2387 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2389 int sreg = tree->sreg1;
2390 int need_touch = FALSE;
2392 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2393 if (!tree->flags & MONO_INST_INIT)
2402 * If requested stack size is larger than one page,
2403 * perform stack-touch operation
2406 * Generate stack probe code.
2407 * Under Windows, it is necessary to allocate one page at a time,
2408 * "touching" stack after each successful sub-allocation. This is
2409 * because of the way stack growth is implemented - there is a
2410 * guard page before the lowest stack page that is currently commited.
2411 * Stack normally grows sequentially so OS traps access to the
2412 * guard page and commits more pages when needed.
2414 amd64_test_reg_imm (code, sreg, ~0xFFF);
2415 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2417 br[2] = code; /* loop */
2418 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2419 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2420 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2421 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2422 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2423 amd64_patch (br[3], br[2]);
2424 amd64_test_reg_reg (code, sreg, sreg);
2425 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2426 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2428 br[1] = code; x86_jump8 (code, 0);
2430 amd64_patch (br[0], code);
2431 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2432 amd64_patch (br[1], code);
2433 amd64_patch (br[4], code);
2436 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2438 if (tree->flags & MONO_INST_INIT) {
2440 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2441 amd64_push_reg (code, AMD64_RAX);
2444 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2445 amd64_push_reg (code, AMD64_RCX);
2448 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2449 amd64_push_reg (code, AMD64_RDI);
2453 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2454 if (sreg != AMD64_RCX)
2455 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2456 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2458 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2460 amd64_prefix (code, X86_REP_PREFIX);
2463 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2464 amd64_pop_reg (code, AMD64_RDI);
2465 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2466 amd64_pop_reg (code, AMD64_RCX);
2467 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2468 amd64_pop_reg (code, AMD64_RAX);
2474 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2479 /* Move return value to the target register */
2480 /* FIXME: do this in the local reg allocator */
2481 switch (ins->opcode) {
2484 case OP_CALL_MEMBASE:
2487 case OP_LCALL_MEMBASE:
2488 g_assert (ins->dreg == AMD64_RAX);
2492 case OP_FCALL_MEMBASE:
2493 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2494 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2497 if (ins->dreg != AMD64_XMM0)
2498 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2503 case OP_VCALL_MEMBASE:
2506 case OP_VCALL2_MEMBASE:
2507 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2508 if (cinfo->ret.storage == ArgValuetypeInReg) {
2509 MonoInst *loc = cfg->arch.vret_addr_loc;
2511 /* Load the destination address */
2512 g_assert (loc->opcode == OP_REGOFFSET);
2513 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2515 for (quad = 0; quad < 2; quad ++) {
2516 switch (cinfo->ret.pair_storage [quad]) {
2518 amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2520 case ArgInFloatSSEReg:
2521 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2523 case ArgInDoubleSSEReg:
2524 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2540 * mono_amd64_emit_tls_get:
2541 * @code: buffer to store code to
2542 * @dreg: hard register where to place the result
2543 * @tls_offset: offset info
2545 * mono_amd64_emit_tls_get emits in @code the native code that puts in
2546 * the dreg register the item in the thread local storage identified
2549 * Returns: a pointer to the end of the stored code
2552 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2554 #ifdef PLATFORM_WIN32
2555 g_assert (tls_offset < 64);
2556 x86_prefix (code, X86_GS_PREFIX);
2557 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2559 if (optimize_for_xen) {
2560 x86_prefix (code, X86_FS_PREFIX);
2561 amd64_mov_reg_mem (code, dreg, 0, 8);
2562 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2564 x86_prefix (code, X86_FS_PREFIX);
2565 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2571 #define REAL_PRINT_REG(text,reg) \
2572 mono_assert (reg >= 0); \
2573 amd64_push_reg (code, AMD64_RAX); \
2574 amd64_push_reg (code, AMD64_RDX); \
2575 amd64_push_reg (code, AMD64_RCX); \
2576 amd64_push_reg (code, reg); \
2577 amd64_push_imm (code, reg); \
2578 amd64_push_imm (code, text " %d %p\n"); \
2579 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2580 amd64_call_reg (code, AMD64_RAX); \
2581 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2582 amd64_pop_reg (code, AMD64_RCX); \
2583 amd64_pop_reg (code, AMD64_RDX); \
2584 amd64_pop_reg (code, AMD64_RAX);
2586 /* benchmark and set based on cpu */
2587 #define LOOP_ALIGNMENT 8
2588 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2593 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2598 guint8 *code = cfg->native_code + cfg->code_len;
2599 MonoInst *last_ins = NULL;
2600 guint last_offset = 0;
2603 if (cfg->opt & MONO_OPT_LOOP) {
2604 int pad, align = LOOP_ALIGNMENT;
2605 /* set alignment depending on cpu */
2606 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2608 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2609 amd64_padding (code, pad);
2610 cfg->code_len += pad;
2611 bb->native_offset = cfg->code_len;
2615 if (cfg->verbose_level > 2)
2616 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2618 cpos = bb->max_offset;
2620 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2621 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2622 g_assert (!cfg->compile_aot);
2625 cov->data [bb->dfn].cil_code = bb->cil_code;
2626 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2627 /* this is not thread save, but good enough */
2628 amd64_inc_membase (code, AMD64_R11, 0);
2631 offset = code - cfg->native_code;
2633 mono_debug_open_block (cfg, bb, offset);
2635 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2636 x86_breakpoint (code);
2638 MONO_BB_FOR_EACH_INS (bb, ins) {
2639 offset = code - cfg->native_code;
2641 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2643 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2644 cfg->code_size *= 2;
2645 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2646 code = cfg->native_code + offset;
2647 mono_jit_stats.code_reallocs++;
2650 if (cfg->debug_info)
2651 mono_debug_record_line_number (cfg, ins, offset);
2653 switch (ins->opcode) {
2655 amd64_mul_reg (code, ins->sreg2, TRUE);
2658 amd64_mul_reg (code, ins->sreg2, FALSE);
2660 case OP_X86_SETEQ_MEMBASE:
2661 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2663 case OP_STOREI1_MEMBASE_IMM:
2664 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2666 case OP_STOREI2_MEMBASE_IMM:
2667 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2669 case OP_STOREI4_MEMBASE_IMM:
2670 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2672 case OP_STOREI1_MEMBASE_REG:
2673 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2675 case OP_STOREI2_MEMBASE_REG:
2676 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2678 case OP_STORE_MEMBASE_REG:
2679 case OP_STOREI8_MEMBASE_REG:
2680 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2682 case OP_STOREI4_MEMBASE_REG:
2683 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2685 case OP_STORE_MEMBASE_IMM:
2686 case OP_STOREI8_MEMBASE_IMM:
2687 g_assert (amd64_is_imm32 (ins->inst_imm));
2688 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2692 // FIXME: Decompose this earlier
2693 if (amd64_is_imm32 (ins->inst_imm))
2694 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2696 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2697 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2701 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2702 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2705 // FIXME: Decompose this earlier
2706 if (amd64_is_imm32 (ins->inst_imm))
2707 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2709 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2710 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2714 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2715 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2718 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2719 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2721 case OP_LOAD_MEMBASE:
2722 case OP_LOADI8_MEMBASE:
2723 g_assert (amd64_is_imm32 (ins->inst_offset));
2724 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2726 case OP_LOADI4_MEMBASE:
2727 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2729 case OP_LOADU4_MEMBASE:
2730 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2732 case OP_LOADU1_MEMBASE:
2733 /* The cpu zero extends the result into 64 bits */
2734 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2736 case OP_LOADI1_MEMBASE:
2737 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2739 case OP_LOADU2_MEMBASE:
2740 /* The cpu zero extends the result into 64 bits */
2741 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2743 case OP_LOADI2_MEMBASE:
2744 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2746 case OP_AMD64_LOADI8_MEMINDEX:
2747 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2749 case OP_LCONV_TO_I1:
2750 case OP_ICONV_TO_I1:
2752 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2754 case OP_LCONV_TO_I2:
2755 case OP_ICONV_TO_I2:
2757 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2759 case OP_LCONV_TO_U1:
2760 case OP_ICONV_TO_U1:
2761 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2763 case OP_LCONV_TO_U2:
2764 case OP_ICONV_TO_U2:
2765 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2768 /* Clean out the upper word */
2769 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2772 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2776 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2778 case OP_COMPARE_IMM:
2779 case OP_LCOMPARE_IMM:
2780 g_assert (amd64_is_imm32 (ins->inst_imm));
2781 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2783 case OP_X86_COMPARE_REG_MEMBASE:
2784 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2786 case OP_X86_TEST_NULL:
2787 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2789 case OP_AMD64_TEST_NULL:
2790 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2793 case OP_X86_ADD_REG_MEMBASE:
2794 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2796 case OP_X86_SUB_REG_MEMBASE:
2797 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2799 case OP_X86_AND_REG_MEMBASE:
2800 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2802 case OP_X86_OR_REG_MEMBASE:
2803 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2805 case OP_X86_XOR_REG_MEMBASE:
2806 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2809 case OP_X86_ADD_MEMBASE_IMM:
2810 /* FIXME: Make a 64 version too */
2811 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2813 case OP_X86_SUB_MEMBASE_IMM:
2814 g_assert (amd64_is_imm32 (ins->inst_imm));
2815 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2817 case OP_X86_AND_MEMBASE_IMM:
2818 g_assert (amd64_is_imm32 (ins->inst_imm));
2819 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2821 case OP_X86_OR_MEMBASE_IMM:
2822 g_assert (amd64_is_imm32 (ins->inst_imm));
2823 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2825 case OP_X86_XOR_MEMBASE_IMM:
2826 g_assert (amd64_is_imm32 (ins->inst_imm));
2827 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2829 case OP_X86_ADD_MEMBASE_REG:
2830 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2832 case OP_X86_SUB_MEMBASE_REG:
2833 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2835 case OP_X86_AND_MEMBASE_REG:
2836 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2838 case OP_X86_OR_MEMBASE_REG:
2839 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2841 case OP_X86_XOR_MEMBASE_REG:
2842 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2844 case OP_X86_INC_MEMBASE:
2845 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2847 case OP_X86_INC_REG:
2848 amd64_inc_reg_size (code, ins->dreg, 4);
2850 case OP_X86_DEC_MEMBASE:
2851 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2853 case OP_X86_DEC_REG:
2854 amd64_dec_reg_size (code, ins->dreg, 4);
2856 case OP_X86_MUL_REG_MEMBASE:
2857 case OP_X86_MUL_MEMBASE_REG:
2858 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2860 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2861 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2863 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2864 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2866 case OP_AMD64_COMPARE_MEMBASE_REG:
2867 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2869 case OP_AMD64_COMPARE_MEMBASE_IMM:
2870 g_assert (amd64_is_imm32 (ins->inst_imm));
2871 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2873 case OP_X86_COMPARE_MEMBASE8_IMM:
2874 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2876 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2877 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2879 case OP_AMD64_COMPARE_REG_MEMBASE:
2880 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2883 case OP_AMD64_ADD_REG_MEMBASE:
2884 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2886 case OP_AMD64_SUB_REG_MEMBASE:
2887 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2889 case OP_AMD64_AND_REG_MEMBASE:
2890 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2892 case OP_AMD64_OR_REG_MEMBASE:
2893 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2895 case OP_AMD64_XOR_REG_MEMBASE:
2896 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2899 case OP_AMD64_ADD_MEMBASE_REG:
2900 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2902 case OP_AMD64_SUB_MEMBASE_REG:
2903 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2905 case OP_AMD64_AND_MEMBASE_REG:
2906 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2908 case OP_AMD64_OR_MEMBASE_REG:
2909 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2911 case OP_AMD64_XOR_MEMBASE_REG:
2912 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2915 case OP_AMD64_ADD_MEMBASE_IMM:
2916 g_assert (amd64_is_imm32 (ins->inst_imm));
2917 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2919 case OP_AMD64_SUB_MEMBASE_IMM:
2920 g_assert (amd64_is_imm32 (ins->inst_imm));
2921 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2923 case OP_AMD64_AND_MEMBASE_IMM:
2924 g_assert (amd64_is_imm32 (ins->inst_imm));
2925 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2927 case OP_AMD64_OR_MEMBASE_IMM:
2928 g_assert (amd64_is_imm32 (ins->inst_imm));
2929 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2931 case OP_AMD64_XOR_MEMBASE_IMM:
2932 g_assert (amd64_is_imm32 (ins->inst_imm));
2933 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2937 amd64_breakpoint (code);
2939 case OP_RELAXED_NOP:
2940 x86_prefix (code, X86_REP_PREFIX);
2948 case OP_DUMMY_STORE:
2949 case OP_NOT_REACHED:
2954 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2957 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2961 g_assert (amd64_is_imm32 (ins->inst_imm));
2962 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2965 g_assert (amd64_is_imm32 (ins->inst_imm));
2966 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2970 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2973 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2977 g_assert (amd64_is_imm32 (ins->inst_imm));
2978 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2981 g_assert (amd64_is_imm32 (ins->inst_imm));
2982 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2985 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2989 g_assert (amd64_is_imm32 (ins->inst_imm));
2990 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2993 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2998 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3000 switch (ins->inst_imm) {
3004 if (ins->dreg != ins->sreg1)
3005 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3006 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3009 /* LEA r1, [r2 + r2*2] */
3010 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3013 /* LEA r1, [r2 + r2*4] */
3014 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3017 /* LEA r1, [r2 + r2*2] */
3019 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3020 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3023 /* LEA r1, [r2 + r2*8] */
3024 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3027 /* LEA r1, [r2 + r2*4] */
3029 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3030 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3033 /* LEA r1, [r2 + r2*2] */
3035 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3036 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3039 /* LEA r1, [r2 + r2*4] */
3040 /* LEA r1, [r1 + r1*4] */
3041 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3042 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3045 /* LEA r1, [r2 + r2*4] */
3047 /* LEA r1, [r1 + r1*4] */
3048 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3049 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3050 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3053 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3060 /* Regalloc magic makes the div/rem cases the same */
3061 if (ins->sreg2 == AMD64_RDX) {
3062 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3064 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3067 amd64_div_reg (code, ins->sreg2, TRUE);
3072 if (ins->sreg2 == AMD64_RDX) {
3073 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3074 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3075 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3077 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3078 amd64_div_reg (code, ins->sreg2, FALSE);
3083 if (ins->sreg2 == AMD64_RDX) {
3084 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3085 amd64_cdq_size (code, 4);
3086 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3088 amd64_cdq_size (code, 4);
3089 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3094 if (ins->sreg2 == AMD64_RDX) {
3095 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3096 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3097 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3099 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3100 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3104 int power = mono_is_power_of_two (ins->inst_imm);
3106 g_assert (ins->sreg1 == X86_EAX);
3107 g_assert (ins->dreg == X86_EAX);
3108 g_assert (power >= 0);
3111 amd64_mov_reg_imm (code, ins->dreg, 0);
3115 /* Based on gcc code */
3117 /* Add compensation for negative dividents */
3118 amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3120 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3121 amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3122 amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3123 /* Compute remainder */
3124 amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3125 /* Remove compensation */
3126 amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3130 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3131 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3134 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3138 g_assert (amd64_is_imm32 (ins->inst_imm));
3139 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3142 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3146 g_assert (amd64_is_imm32 (ins->inst_imm));
3147 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3150 g_assert (ins->sreg2 == AMD64_RCX);
3151 amd64_shift_reg (code, X86_SHL, ins->dreg);
3154 g_assert (ins->sreg2 == AMD64_RCX);
3155 amd64_shift_reg (code, X86_SAR, ins->dreg);
3158 g_assert (amd64_is_imm32 (ins->inst_imm));
3159 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3162 g_assert (amd64_is_imm32 (ins->inst_imm));
3163 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3166 g_assert (amd64_is_imm32 (ins->inst_imm));
3167 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3169 case OP_LSHR_UN_IMM:
3170 g_assert (amd64_is_imm32 (ins->inst_imm));
3171 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3174 g_assert (ins->sreg2 == AMD64_RCX);
3175 amd64_shift_reg (code, X86_SHR, ins->dreg);
3178 g_assert (amd64_is_imm32 (ins->inst_imm));
3179 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3182 g_assert (amd64_is_imm32 (ins->inst_imm));
3183 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3188 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3191 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3194 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3197 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3201 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3204 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3207 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3210 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3213 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3216 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3219 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3222 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3225 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3228 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3231 amd64_neg_reg_size (code, ins->sreg1, 4);
3234 amd64_not_reg_size (code, ins->sreg1, 4);
3237 g_assert (ins->sreg2 == AMD64_RCX);
3238 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3241 g_assert (ins->sreg2 == AMD64_RCX);
3242 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3245 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3247 case OP_ISHR_UN_IMM:
3248 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3251 g_assert (ins->sreg2 == AMD64_RCX);
3252 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3255 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3258 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3261 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3262 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3264 case OP_IMUL_OVF_UN:
3265 case OP_LMUL_OVF_UN: {
3266 /* the mul operation and the exception check should most likely be split */
3267 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3268 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3269 /*g_assert (ins->sreg2 == X86_EAX);
3270 g_assert (ins->dreg == X86_EAX);*/
3271 if (ins->sreg2 == X86_EAX) {
3272 non_eax_reg = ins->sreg1;
3273 } else if (ins->sreg1 == X86_EAX) {
3274 non_eax_reg = ins->sreg2;
3276 /* no need to save since we're going to store to it anyway */
3277 if (ins->dreg != X86_EAX) {
3279 amd64_push_reg (code, X86_EAX);
3281 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3282 non_eax_reg = ins->sreg2;
3284 if (ins->dreg == X86_EDX) {
3287 amd64_push_reg (code, X86_EAX);
3291 amd64_push_reg (code, X86_EDX);
3293 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3294 /* save before the check since pop and mov don't change the flags */
3295 if (ins->dreg != X86_EAX)
3296 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3298 amd64_pop_reg (code, X86_EDX);
3300 amd64_pop_reg (code, X86_EAX);
3301 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3305 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3307 case OP_ICOMPARE_IMM:
3308 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3330 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3338 case OP_CMOV_INE_UN:
3339 case OP_CMOV_IGE_UN:
3340 case OP_CMOV_IGT_UN:
3341 case OP_CMOV_ILE_UN:
3342 case OP_CMOV_ILT_UN:
3348 case OP_CMOV_LNE_UN:
3349 case OP_CMOV_LGE_UN:
3350 case OP_CMOV_LGT_UN:
3351 case OP_CMOV_LLE_UN:
3352 case OP_CMOV_LLT_UN:
3353 g_assert (ins->dreg == ins->sreg1);
3354 /* This needs to operate on 64 bit values */
3355 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3359 amd64_not_reg (code, ins->sreg1);
3362 amd64_neg_reg (code, ins->sreg1);
3367 if ((((guint64)ins->inst_c0) >> 32) == 0)
3368 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3370 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3373 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3374 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3377 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3378 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3381 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3383 case OP_AMD64_SET_XMMREG_R4: {
3384 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3387 case OP_AMD64_SET_XMMREG_R8: {
3388 if (ins->dreg != ins->sreg1)
3389 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3394 * Note: this 'frame destruction' logic is useful for tail calls, too.
3395 * Keep in sync with the code in emit_epilog.
3399 /* FIXME: no tracing support... */
3400 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3401 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3403 g_assert (!cfg->method->save_lmf);
3405 if (cfg->arch.omit_fp) {
3406 guint32 save_offset = 0;
3407 /* Pop callee-saved registers */
3408 for (i = 0; i < AMD64_NREG; ++i)
3409 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3410 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3413 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3416 for (i = 0; i < AMD64_NREG; ++i)
3417 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3418 pos -= sizeof (gpointer);
3421 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3423 /* Pop registers in reverse order */
3424 for (i = AMD64_NREG - 1; i > 0; --i)
3425 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3426 amd64_pop_reg (code, i);
3432 offset = code - cfg->native_code;
3433 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3434 if (cfg->compile_aot)
3435 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3437 amd64_set_reg_template (code, AMD64_R11);
3438 amd64_jump_reg (code, AMD64_R11);
3442 /* ensure ins->sreg1 is not NULL */
3443 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3446 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3447 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3456 call = (MonoCallInst*)ins;
3458 * The AMD64 ABI forces callers to know about varargs.
3460 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3461 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3462 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3464 * Since the unmanaged calling convention doesn't contain a
3465 * 'vararg' entry, we have to treat every pinvoke call as a
3466 * potential vararg call.
3470 for (i = 0; i < AMD64_XMM_NREG; ++i)
3471 if (call->used_fregs & (1 << i))
3474 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3476 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3479 if (ins->flags & MONO_INST_HAS_METHOD)
3480 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3482 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3483 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3484 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3485 code = emit_move_return_value (cfg, ins, code);
3491 case OP_VOIDCALL_REG:
3493 call = (MonoCallInst*)ins;
3495 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3496 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3497 ins->sreg1 = AMD64_R11;
3501 * The AMD64 ABI forces callers to know about varargs.
3503 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3504 if (ins->sreg1 == AMD64_RAX) {
3505 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3506 ins->sreg1 = AMD64_R11;
3508 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3509 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3511 * Since the unmanaged calling convention doesn't contain a
3512 * 'vararg' entry, we have to treat every pinvoke call as a
3513 * potential vararg call.
3517 for (i = 0; i < AMD64_XMM_NREG; ++i)
3518 if (call->used_fregs & (1 << i))
3520 if (ins->sreg1 == AMD64_RAX) {
3521 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3522 ins->sreg1 = AMD64_R11;
3525 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3527 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3530 amd64_call_reg (code, ins->sreg1);
3531 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3532 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3533 code = emit_move_return_value (cfg, ins, code);
3535 case OP_FCALL_MEMBASE:
3536 case OP_LCALL_MEMBASE:
3537 case OP_VCALL_MEMBASE:
3538 case OP_VCALL2_MEMBASE:
3539 case OP_VOIDCALL_MEMBASE:
3540 case OP_CALL_MEMBASE:
3541 call = (MonoCallInst*)ins;
3543 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3545 * Can't use R11 because it is clobbered by the trampoline
3546 * code, and the reg value is needed by get_vcall_slot_addr.
3548 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3549 ins->sreg1 = AMD64_RAX;
3553 * Emit a few nops to simplify get_vcall_slot ().
3559 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3560 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3561 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3562 code = emit_move_return_value (cfg, ins, code);
3564 case OP_AMD64_SAVE_SP_TO_LMF:
3565 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3568 amd64_push_reg (code, ins->sreg1);
3570 case OP_X86_PUSH_IMM:
3571 g_assert (amd64_is_imm32 (ins->inst_imm));
3572 amd64_push_imm (code, ins->inst_imm);
3574 case OP_X86_PUSH_MEMBASE:
3575 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3577 case OP_X86_PUSH_OBJ: {
3578 int size = ALIGN_TO (ins->inst_imm, 8);
3579 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3580 amd64_push_reg (code, AMD64_RDI);
3581 amd64_push_reg (code, AMD64_RSI);
3582 amd64_push_reg (code, AMD64_RCX);
3583 if (ins->inst_offset)
3584 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3586 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3587 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3588 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3590 amd64_prefix (code, X86_REP_PREFIX);
3592 amd64_pop_reg (code, AMD64_RCX);
3593 amd64_pop_reg (code, AMD64_RSI);
3594 amd64_pop_reg (code, AMD64_RDI);
3598 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3600 case OP_X86_LEA_MEMBASE:
3601 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3604 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3607 /* keep alignment */
3608 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3609 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3610 code = mono_emit_stack_alloc (code, ins);
3611 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3613 case OP_LOCALLOC_IMM: {
3614 guint32 size = ins->inst_imm;
3615 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3617 if (ins->flags & MONO_INST_INIT) {
3621 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3622 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3624 for (i = 0; i < size; i += 8)
3625 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3626 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3628 amd64_mov_reg_imm (code, ins->dreg, size);
3629 ins->sreg1 = ins->dreg;
3631 code = mono_emit_stack_alloc (code, ins);
3632 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3635 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3636 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3641 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3642 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3643 (gpointer)"mono_arch_throw_exception", FALSE);
3647 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3648 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3649 (gpointer)"mono_arch_rethrow_exception", FALSE);
3652 case OP_CALL_HANDLER:
3654 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3655 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3656 amd64_call_imm (code, 0);
3657 /* Restore stack alignment */
3658 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3660 case OP_START_HANDLER: {
3661 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3662 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3665 case OP_ENDFINALLY: {
3666 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3667 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3671 case OP_ENDFILTER: {
3672 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3673 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3674 /* The local allocator will put the result into RAX */
3680 ins->inst_c0 = code - cfg->native_code;
3683 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3684 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3686 if (ins->flags & MONO_INST_BRLABEL) {
3687 if (ins->inst_i0->inst_c0) {
3688 amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3690 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3691 if ((cfg->opt & MONO_OPT_BRANCH) &&
3692 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3693 x86_jump8 (code, 0);
3695 x86_jump32 (code, 0);
3698 if (ins->inst_target_bb->native_offset) {
3699 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3701 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3702 if ((cfg->opt & MONO_OPT_BRANCH) &&
3703 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3704 x86_jump8 (code, 0);
3706 x86_jump32 (code, 0);
3711 amd64_jump_reg (code, ins->sreg1);
3728 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3729 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3731 case OP_COND_EXC_EQ:
3732 case OP_COND_EXC_NE_UN:
3733 case OP_COND_EXC_LT:
3734 case OP_COND_EXC_LT_UN:
3735 case OP_COND_EXC_GT:
3736 case OP_COND_EXC_GT_UN:
3737 case OP_COND_EXC_GE:
3738 case OP_COND_EXC_GE_UN:
3739 case OP_COND_EXC_LE:
3740 case OP_COND_EXC_LE_UN:
3741 case OP_COND_EXC_IEQ:
3742 case OP_COND_EXC_INE_UN:
3743 case OP_COND_EXC_ILT:
3744 case OP_COND_EXC_ILT_UN:
3745 case OP_COND_EXC_IGT:
3746 case OP_COND_EXC_IGT_UN:
3747 case OP_COND_EXC_IGE:
3748 case OP_COND_EXC_IGE_UN:
3749 case OP_COND_EXC_ILE:
3750 case OP_COND_EXC_ILE_UN:
3751 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3753 case OP_COND_EXC_OV:
3754 case OP_COND_EXC_NO:
3756 case OP_COND_EXC_NC:
3757 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3758 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3760 case OP_COND_EXC_IOV:
3761 case OP_COND_EXC_INO:
3762 case OP_COND_EXC_IC:
3763 case OP_COND_EXC_INC:
3764 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3765 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3768 /* floating point opcodes */
3770 double d = *(double *)ins->inst_p0;
3772 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3773 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3776 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3777 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3782 float f = *(float *)ins->inst_p0;
3784 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3785 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3788 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3789 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3790 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3794 case OP_STORER8_MEMBASE_REG:
3795 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3797 case OP_LOADR8_SPILL_MEMBASE:
3798 g_assert_not_reached ();
3800 case OP_LOADR8_MEMBASE:
3801 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3803 case OP_STORER4_MEMBASE_REG:
3804 /* This requires a double->single conversion */
3805 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3806 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3808 case OP_LOADR4_MEMBASE:
3809 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3810 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3812 case OP_ICONV_TO_R4: /* FIXME: change precision */
3813 case OP_ICONV_TO_R8:
3814 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3816 case OP_LCONV_TO_R4: /* FIXME: change precision */
3817 case OP_LCONV_TO_R8:
3818 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3820 case OP_FCONV_TO_R4:
3821 /* FIXME: nothing to do ?? */
3823 case OP_FCONV_TO_I1:
3824 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3826 case OP_FCONV_TO_U1:
3827 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3829 case OP_FCONV_TO_I2:
3830 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3832 case OP_FCONV_TO_U2:
3833 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3835 case OP_FCONV_TO_U4:
3836 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3838 case OP_FCONV_TO_I4:
3840 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3842 case OP_FCONV_TO_I8:
3843 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3845 case OP_LCONV_TO_R_UN: {
3848 /* Based on gcc code */
3849 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3850 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3853 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3854 br [1] = code; x86_jump8 (code, 0);
3855 amd64_patch (br [0], code);
3858 /* Save to the red zone */
3859 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3860 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3861 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3862 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3863 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3864 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3865 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3866 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3867 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3869 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3870 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3871 amd64_patch (br [1], code);
3874 case OP_LCONV_TO_OVF_U4:
3875 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3876 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3877 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3879 case OP_LCONV_TO_OVF_I4_UN:
3880 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3881 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3882 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3885 if (ins->dreg != ins->sreg1)
3886 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3889 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3892 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3895 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3898 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3901 static double r8_0 = -0.0;
3903 g_assert (ins->sreg1 == ins->dreg);
3905 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3906 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3910 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3913 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3916 static guint64 d = 0x7fffffffffffffffUL;
3918 g_assert (ins->sreg1 == ins->dreg);
3920 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
3921 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3925 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3928 g_assert (cfg->opt & MONO_OPT_CMOV);
3929 g_assert (ins->dreg == ins->sreg1);
3930 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3931 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3934 g_assert (cfg->opt & MONO_OPT_CMOV);
3935 g_assert (ins->dreg == ins->sreg1);
3936 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3937 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
3940 g_assert (cfg->opt & MONO_OPT_CMOV);
3941 g_assert (ins->dreg == ins->sreg1);
3942 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3943 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3946 g_assert (cfg->opt & MONO_OPT_CMOV);
3947 g_assert (ins->dreg == ins->sreg1);
3948 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3949 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
3952 g_assert (cfg->opt & MONO_OPT_CMOV);
3953 g_assert (ins->dreg == ins->sreg1);
3954 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3955 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3958 g_assert (cfg->opt & MONO_OPT_CMOV);
3959 g_assert (ins->dreg == ins->sreg1);
3960 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3961 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3964 g_assert (cfg->opt & MONO_OPT_CMOV);
3965 g_assert (ins->dreg == ins->sreg1);
3966 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3967 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3970 g_assert (cfg->opt & MONO_OPT_CMOV);
3971 g_assert (ins->dreg == ins->sreg1);
3972 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3973 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3979 * The two arguments are swapped because the fbranch instructions
3980 * depend on this for the non-sse case to work.
3982 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3985 /* zeroing the register at the start results in
3986 * shorter and faster code (we can also remove the widening op)
3988 guchar *unordered_check;
3989 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3990 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3991 unordered_check = code;
3992 x86_branch8 (code, X86_CC_P, 0, FALSE);
3993 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3994 amd64_patch (unordered_check, code);
3999 /* zeroing the register at the start results in
4000 * shorter and faster code (we can also remove the widening op)
4002 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4003 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4004 if (ins->opcode == OP_FCLT_UN) {
4005 guchar *unordered_check = code;
4006 guchar *jump_to_end;
4007 x86_branch8 (code, X86_CC_P, 0, FALSE);
4008 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4010 x86_jump8 (code, 0);
4011 amd64_patch (unordered_check, code);
4012 amd64_inc_reg (code, ins->dreg);
4013 amd64_patch (jump_to_end, code);
4015 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4020 /* zeroing the register at the start results in
4021 * shorter and faster code (we can also remove the widening op)
4023 guchar *unordered_check;
4024 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4025 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4026 if (ins->opcode == OP_FCGT) {
4027 unordered_check = code;
4028 x86_branch8 (code, X86_CC_P, 0, FALSE);
4029 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4030 amd64_patch (unordered_check, code);
4032 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4036 case OP_FCLT_MEMBASE:
4037 case OP_FCGT_MEMBASE:
4038 case OP_FCLT_UN_MEMBASE:
4039 case OP_FCGT_UN_MEMBASE:
4040 case OP_FCEQ_MEMBASE: {
4041 guchar *unordered_check, *jump_to_end;
4044 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4045 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4047 switch (ins->opcode) {
4048 case OP_FCEQ_MEMBASE:
4049 x86_cond = X86_CC_EQ;
4051 case OP_FCLT_MEMBASE:
4052 case OP_FCLT_UN_MEMBASE:
4053 x86_cond = X86_CC_LT;
4055 case OP_FCGT_MEMBASE:
4056 case OP_FCGT_UN_MEMBASE:
4057 x86_cond = X86_CC_GT;
4060 g_assert_not_reached ();
4063 unordered_check = code;
4064 x86_branch8 (code, X86_CC_P, 0, FALSE);
4065 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4067 switch (ins->opcode) {
4068 case OP_FCEQ_MEMBASE:
4069 case OP_FCLT_MEMBASE:
4070 case OP_FCGT_MEMBASE:
4071 amd64_patch (unordered_check, code);
4073 case OP_FCLT_UN_MEMBASE:
4074 case OP_FCGT_UN_MEMBASE:
4076 x86_jump8 (code, 0);
4077 amd64_patch (unordered_check, code);
4078 amd64_inc_reg (code, ins->dreg);
4079 amd64_patch (jump_to_end, code);
4087 guchar *jump = code;
4088 x86_branch8 (code, X86_CC_P, 0, TRUE);
4089 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4090 amd64_patch (jump, code);
4094 /* Branch if C013 != 100 */
4095 /* branch if !ZF or (PF|CF) */
4096 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4097 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4098 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4101 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4104 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4105 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4109 if (ins->opcode == OP_FBGT) {
4112 /* skip branch if C1=1 */
4114 x86_branch8 (code, X86_CC_P, 0, FALSE);
4115 /* branch if (C0 | C3) = 1 */
4116 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4117 amd64_patch (br1, code);
4120 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4124 /* Branch if C013 == 100 or 001 */
4127 /* skip branch if C1=1 */
4129 x86_branch8 (code, X86_CC_P, 0, FALSE);
4130 /* branch if (C0 | C3) = 1 */
4131 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4132 amd64_patch (br1, code);
4136 /* Branch if C013 == 000 */
4137 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4140 /* Branch if C013=000 or 100 */
4143 /* skip branch if C1=1 */
4145 x86_branch8 (code, X86_CC_P, 0, FALSE);
4146 /* branch if C0=0 */
4147 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4148 amd64_patch (br1, code);
4152 /* Branch if C013 != 001 */
4153 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4154 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4157 /* Transfer value to the fp stack */
4158 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4159 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4160 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4162 amd64_push_reg (code, AMD64_RAX);
4164 amd64_fnstsw (code);
4165 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4166 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4167 amd64_pop_reg (code, AMD64_RAX);
4168 amd64_fstp (code, 0);
4169 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4170 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4173 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4176 case OP_MEMORY_BARRIER: {
4177 /* Not needed on amd64 */
4180 case OP_ATOMIC_ADD_I4:
4181 case OP_ATOMIC_ADD_I8: {
4182 int dreg = ins->dreg;
4183 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4185 if (dreg == ins->inst_basereg)
4188 if (dreg != ins->sreg2)
4189 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4191 x86_prefix (code, X86_LOCK_PREFIX);
4192 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4194 if (dreg != ins->dreg)
4195 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4199 case OP_ATOMIC_ADD_NEW_I4:
4200 case OP_ATOMIC_ADD_NEW_I8: {
4201 int dreg = ins->dreg;
4202 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4204 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4207 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4208 amd64_prefix (code, X86_LOCK_PREFIX);
4209 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4210 /* dreg contains the old value, add with sreg2 value */
4211 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4213 if (ins->dreg != dreg)
4214 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4218 case OP_ATOMIC_EXCHANGE_I4:
4219 case OP_ATOMIC_EXCHANGE_I8: {
4221 int sreg2 = ins->sreg2;
4222 int breg = ins->inst_basereg;
4224 gboolean need_push = FALSE, rdx_pushed = FALSE;
4226 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4232 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4233 * an explanation of how this works.
4236 /* cmpxchg uses eax as comperand, need to make sure we can use it
4237 * hack to overcome limits in x86 reg allocator
4238 * (req: dreg == eax and sreg2 != eax and breg != eax)
4240 g_assert (ins->dreg == AMD64_RAX);
4242 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4243 /* Highly unlikely, but possible */
4246 /* The pushes invalidate rsp */
4247 if ((breg == AMD64_RAX) || need_push) {
4248 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4252 /* We need the EAX reg for the comparand */
4253 if (ins->sreg2 == AMD64_RAX) {
4254 if (breg != AMD64_R11) {
4255 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4258 g_assert (need_push);
4259 amd64_push_reg (code, AMD64_RDX);
4260 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4266 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4268 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4269 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4270 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4271 amd64_patch (br [1], br [0]);
4274 amd64_pop_reg (code, AMD64_RDX);
4278 case OP_ATOMIC_CAS_I4:
4279 case OP_ATOMIC_CAS_I8: {
4282 if (ins->opcode == OP_ATOMIC_CAS_I8)
4288 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4289 * an explanation of how this works.
4291 g_assert (ins->sreg3 == AMD64_RAX);
4292 g_assert (ins->sreg1 != AMD64_RAX);
4293 g_assert (ins->sreg1 != ins->sreg2);
4295 amd64_prefix (code, X86_LOCK_PREFIX);
4296 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4298 if (ins->dreg != AMD64_RAX)
4299 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4302 case OP_LIVERANGE_START: {
4303 if (cfg->verbose_level > 1)
4304 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4305 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4308 case OP_LIVERANGE_END: {
4309 if (cfg->verbose_level > 1)
4310 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4311 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4315 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4316 g_assert_not_reached ();
4319 if ((code - cfg->native_code - offset) > max_len) {
4320 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4321 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4322 g_assert_not_reached ();
4328 last_offset = offset;
4331 cfg->code_len = code - cfg->native_code;
4334 #endif /* DISABLE_JIT */
4337 mono_arch_register_lowlevel_calls (void)
4339 /* The signature doesn't matter */
4340 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4344 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4346 MonoJumpInfo *patch_info;
4347 gboolean compile_aot = !run_cctors;
4349 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4350 unsigned char *ip = patch_info->ip.i + code;
4351 unsigned char *target;
4353 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4356 switch (patch_info->type) {
4357 case MONO_PATCH_INFO_BB:
4358 case MONO_PATCH_INFO_LABEL:
4361 /* No need to patch these */
4366 switch (patch_info->type) {
4367 case MONO_PATCH_INFO_NONE:
4369 case MONO_PATCH_INFO_METHOD_REL:
4370 case MONO_PATCH_INFO_R8:
4371 case MONO_PATCH_INFO_R4:
4372 g_assert_not_reached ();
4374 case MONO_PATCH_INFO_BB:
4381 * Debug code to help track down problems where the target of a near call is
4384 if (amd64_is_near_call (ip)) {
4385 gint64 disp = (guint8*)target - (guint8*)ip;
4387 if (!amd64_is_imm32 (disp)) {
4388 printf ("TYPE: %d\n", patch_info->type);
4389 switch (patch_info->type) {
4390 case MONO_PATCH_INFO_INTERNAL_METHOD:
4391 printf ("V: %s\n", patch_info->data.name);
4393 case MONO_PATCH_INFO_METHOD_JUMP:
4394 case MONO_PATCH_INFO_METHOD:
4395 printf ("V: %s\n", patch_info->data.method->name);
4403 amd64_patch (ip, (gpointer)target);
4408 get_max_epilog_size (MonoCompile *cfg)
4410 int max_epilog_size = 16;
4412 if (cfg->method->save_lmf)
4413 max_epilog_size += 256;
4415 if (mono_jit_trace_calls != NULL)
4416 max_epilog_size += 50;
4418 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4419 max_epilog_size += 50;
4421 max_epilog_size += (AMD64_NREG * 2);
4423 return max_epilog_size;
4427 * This macro is used for testing whenever the unwinder works correctly at every point
4428 * where an async exception can happen.
4430 /* This will generate a SIGSEGV at the given point in the code */
4431 #define async_exc_point(code) do { \
4432 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4433 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4434 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4435 cfg->arch.async_point_count ++; \
4440 mono_arch_emit_prolog (MonoCompile *cfg)
4442 MonoMethod *method = cfg->method;
4444 MonoMethodSignature *sig;
4446 int alloc_size, pos, max_offset, i, cfa_offset, quad, max_epilog_size;
4449 gint32 lmf_offset = cfg->arch.lmf_offset;
4450 gboolean args_clobbered = FALSE;
4451 gboolean trace = FALSE;
4453 cfg->code_size = MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4455 code = cfg->native_code = g_malloc (cfg->code_size);
4457 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4460 /* Amount of stack space allocated by register saving code */
4463 /* Offset between RSP and the CFA */
4467 * The prolog consists of the following parts:
4469 * - push rbp, mov rbp, rsp
4470 * - save callee saved regs using pushes
4472 * - save rgctx if needed
4473 * - save lmf if needed
4476 * - save rgctx if needed
4477 * - save lmf if needed
4478 * - save callee saved regs using moves
4483 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
4484 // IP saved at CFA - 8
4485 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
4486 async_exc_point (code);
4488 if (!cfg->arch.omit_fp) {
4489 amd64_push_reg (code, AMD64_RBP);
4491 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4492 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
4493 async_exc_point (code);
4494 #ifdef PLATFORM_WIN32
4495 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4498 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4499 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
4500 async_exc_point (code);
4501 #ifdef PLATFORM_WIN32
4502 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4506 /* Save callee saved registers */
4507 if (!cfg->arch.omit_fp && !method->save_lmf) {
4508 int offset = cfa_offset;
4510 for (i = 0; i < AMD64_NREG; ++i)
4511 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4512 amd64_push_reg (code, i);
4513 pos += sizeof (gpointer);
4515 mono_emit_unwind_op_offset (cfg, code, i, - offset);
4516 async_exc_point (code);
4520 if (cfg->arch.omit_fp) {
4522 * On enter, the stack is misaligned by the the pushing of the return
4523 * address. It is either made aligned by the pushing of %rbp, or by
4526 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4527 if ((alloc_size % 16) == 0)
4530 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4535 cfg->arch.stack_alloc_size = alloc_size;
4537 /* Allocate stack frame */
4539 /* See mono_emit_stack_alloc */
4540 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4541 guint32 remaining_size = alloc_size;
4542 while (remaining_size >= 0x1000) {
4543 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4544 if (cfg->arch.omit_fp) {
4545 cfa_offset += 0x1000;
4546 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4548 async_exc_point (code);
4549 #ifdef PLATFORM_WIN32
4550 if (cfg->arch.omit_fp)
4551 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4554 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4555 remaining_size -= 0x1000;
4557 if (remaining_size) {
4558 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4559 if (cfg->arch.omit_fp) {
4560 cfa_offset += remaining_size;
4561 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4562 async_exc_point (code);
4564 #ifdef PLATFORM_WIN32
4565 if (cfg->arch.omit_fp)
4566 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4570 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4571 if (cfg->arch.omit_fp) {
4572 cfa_offset += alloc_size;
4573 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4574 async_exc_point (code);
4579 /* Stack alignment check */
4582 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4583 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4584 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4585 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4586 amd64_breakpoint (code);
4591 if (method->save_lmf) {
4593 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4595 /* sp is saved right before calls */
4596 /* Skip method (only needed for trampoline LMF frames) */
4597 /* Save callee saved regs */
4598 for (i = 0; i < MONO_MAX_IREGS; ++i) {
4602 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
4603 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
4604 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
4605 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
4606 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
4607 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
4608 #ifdef PLATFORM_WIN32
4609 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
4610 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
4618 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
4619 if (cfg->arch.omit_fp || (i != AMD64_RBP))
4620 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
4625 /* Save callee saved registers */
4626 if (cfg->arch.omit_fp && !method->save_lmf) {
4627 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4629 /* Save caller saved registers after sp is adjusted */
4630 /* The registers are saved at the bottom of the frame */
4631 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4632 for (i = 0; i < AMD64_NREG; ++i)
4633 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4634 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4635 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
4636 save_area_offset += 8;
4637 async_exc_point (code);
4641 /* store runtime generic context */
4642 if (cfg->rgctx_var) {
4643 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4644 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4646 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4649 /* compute max_offset in order to use short forward jumps */
4651 max_epilog_size = get_max_epilog_size (cfg);
4652 if (cfg->opt & MONO_OPT_BRANCH) {
4653 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4655 bb->max_offset = max_offset;
4657 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4659 /* max alignment for loops */
4660 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4661 max_offset += LOOP_ALIGNMENT;
4663 MONO_BB_FOR_EACH_INS (bb, ins) {
4664 if (ins->opcode == OP_LABEL)
4665 ins->inst_c1 = max_offset;
4667 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4670 if (mono_jit_trace_calls && bb == cfg->bb_exit)
4671 /* The tracing code can be quite large */
4672 max_offset += max_epilog_size;
4676 sig = mono_method_signature (method);
4679 cinfo = cfg->arch.cinfo;
4681 if (sig->ret->type != MONO_TYPE_VOID) {
4682 /* Save volatile arguments to the stack */
4683 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4684 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4687 /* Keep this in sync with emit_load_volatile_arguments */
4688 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4689 ArgInfo *ainfo = cinfo->args + i;
4690 gint32 stack_offset;
4693 ins = cfg->args [i];
4695 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4696 /* Unused arguments */
4699 if (sig->hasthis && (i == 0))
4700 arg_type = &mono_defaults.object_class->byval_arg;
4702 arg_type = sig->params [i - sig->hasthis];
4704 stack_offset = ainfo->offset + ARGS_OFFSET;
4706 if (cfg->globalra) {
4707 /* All the other moves are done by the register allocator */
4708 switch (ainfo->storage) {
4709 case ArgInFloatSSEReg:
4710 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
4712 case ArgValuetypeInReg:
4713 for (quad = 0; quad < 2; quad ++) {
4714 switch (ainfo->pair_storage [quad]) {
4716 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4718 case ArgInFloatSSEReg:
4719 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4721 case ArgInDoubleSSEReg:
4722 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4727 g_assert_not_reached ();
4738 /* Save volatile arguments to the stack */
4739 if (ins->opcode != OP_REGVAR) {
4740 switch (ainfo->storage) {
4746 if (stack_offset & 0x1)
4748 else if (stack_offset & 0x2)
4750 else if (stack_offset & 0x4)
4755 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4758 case ArgInFloatSSEReg:
4759 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4761 case ArgInDoubleSSEReg:
4762 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4764 case ArgValuetypeInReg:
4765 for (quad = 0; quad < 2; quad ++) {
4766 switch (ainfo->pair_storage [quad]) {
4768 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4770 case ArgInFloatSSEReg:
4771 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4773 case ArgInDoubleSSEReg:
4774 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4779 g_assert_not_reached ();
4783 case ArgValuetypeAddrInIReg:
4784 if (ainfo->pair_storage [0] == ArgInIReg)
4785 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
4791 /* Argument allocated to (non-volatile) register */
4792 switch (ainfo->storage) {
4794 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4797 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4800 g_assert_not_reached ();
4805 /* Might need to attach the thread to the JIT or change the domain for the callback */
4806 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4807 guint64 domain = (guint64)cfg->domain;
4809 args_clobbered = TRUE;
4812 * The call might clobber argument registers, but they are already
4813 * saved to the stack/global regs.
4815 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4816 guint8 *buf, *no_domain_branch;
4818 code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4819 if ((domain >> 32) == 0)
4820 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4822 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4823 amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4824 no_domain_branch = code;
4825 x86_branch8 (code, X86_CC_NE, 0, 0);
4826 code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4827 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4829 x86_branch8 (code, X86_CC_NE, 0, 0);
4830 amd64_patch (no_domain_branch, code);
4831 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4832 (gpointer)"mono_jit_thread_attach", TRUE);
4833 amd64_patch (buf, code);
4834 #ifdef PLATFORM_WIN32
4835 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4836 /* FIXME: Add a separate key for LMF to avoid this */
4837 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4840 g_assert (!cfg->compile_aot);
4841 if ((domain >> 32) == 0)
4842 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4844 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4845 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4846 (gpointer)"mono_jit_thread_attach", TRUE);
4850 if (method->save_lmf) {
4851 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4853 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4854 * through the mono_lmf_addr TLS variable.
4856 /* %rax = previous_lmf */
4857 x86_prefix (code, X86_FS_PREFIX);
4858 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4860 /* Save previous_lmf */
4861 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4863 if (lmf_offset == 0) {
4864 x86_prefix (code, X86_FS_PREFIX);
4865 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4867 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4868 x86_prefix (code, X86_FS_PREFIX);
4869 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4872 if (lmf_addr_tls_offset != -1) {
4873 /* Load lmf quicky using the FS register */
4874 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4875 #ifdef PLATFORM_WIN32
4876 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4877 /* FIXME: Add a separate key for LMF to avoid this */
4878 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4883 * The call might clobber argument registers, but they are already
4884 * saved to the stack/global regs.
4886 args_clobbered = TRUE;
4887 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4888 (gpointer)"mono_get_lmf_addr", TRUE);
4892 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4893 /* Save previous_lmf */
4894 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4895 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4897 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4898 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4903 args_clobbered = TRUE;
4904 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4907 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4908 args_clobbered = TRUE;
4911 * Optimize the common case of the first bblock making a call with the same
4912 * arguments as the method. This works because the arguments are still in their
4913 * original argument registers.
4914 * FIXME: Generalize this
4916 if (!args_clobbered) {
4917 MonoBasicBlock *first_bb = cfg->bb_entry;
4920 next = mono_bb_first_ins (first_bb);
4921 if (!next && first_bb->next_bb) {
4922 first_bb = first_bb->next_bb;
4923 next = mono_bb_first_ins (first_bb);
4926 if (first_bb->in_count > 1)
4929 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4930 ArgInfo *ainfo = cinfo->args + i;
4931 gboolean match = FALSE;
4933 ins = cfg->args [i];
4934 if (ins->opcode != OP_REGVAR) {
4935 switch (ainfo->storage) {
4937 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4938 if (next->dreg == ainfo->reg) {
4942 next->opcode = OP_MOVE;
4943 next->sreg1 = ainfo->reg;
4944 /* Only continue if the instruction doesn't change argument regs */
4945 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4955 /* Argument allocated to (non-volatile) register */
4956 switch (ainfo->storage) {
4958 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4970 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4977 cfg->code_len = code - cfg->native_code;
4979 g_assert (cfg->code_len < cfg->code_size);
4985 mono_arch_emit_epilog (MonoCompile *cfg)
4987 MonoMethod *method = cfg->method;
4990 int max_epilog_size;
4992 gint32 lmf_offset = cfg->arch.lmf_offset;
4994 max_epilog_size = get_max_epilog_size (cfg);
4996 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4997 cfg->code_size *= 2;
4998 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4999 mono_jit_stats.code_reallocs++;
5002 code = cfg->native_code + cfg->code_len;
5004 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5005 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5007 /* the code restoring the registers must be kept in sync with OP_JMP */
5010 if (method->save_lmf) {
5011 /* check if we need to restore protection of the stack after a stack overflow */
5012 if (mono_get_jit_tls_offset () != -1) {
5014 code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5015 /* we load the value in a separate instruction: this mechanism may be
5016 * used later as a safer way to do thread interruption
5018 amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
5019 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5021 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5022 /* note that the call trampoline will preserve eax/edx */
5023 x86_call_reg (code, X86_ECX);
5024 x86_patch (patch, code);
5026 /* FIXME: maybe save the jit tls in the prolog */
5028 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5030 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5031 * through the mono_lmf_addr TLS variable.
5033 /* reg = previous_lmf */
5034 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5035 x86_prefix (code, X86_FS_PREFIX);
5036 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5038 /* Restore previous lmf */
5039 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5040 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5041 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5044 /* Restore caller saved regs */
5045 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5046 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5048 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5049 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5051 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5052 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5054 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5055 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5057 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5058 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5060 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5061 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5063 #ifdef PLATFORM_WIN32
5064 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
5065 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
5067 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
5068 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
5073 if (cfg->arch.omit_fp) {
5074 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5076 for (i = 0; i < AMD64_NREG; ++i)
5077 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5078 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5079 save_area_offset += 8;
5083 for (i = 0; i < AMD64_NREG; ++i)
5084 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5085 pos -= sizeof (gpointer);
5088 if (pos == - sizeof (gpointer)) {
5089 /* Only one register, so avoid lea */
5090 for (i = AMD64_NREG - 1; i > 0; --i)
5091 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5092 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5096 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5098 /* Pop registers in reverse order */
5099 for (i = AMD64_NREG - 1; i > 0; --i)
5100 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5101 amd64_pop_reg (code, i);
5108 /* Load returned vtypes into registers if needed */
5109 cinfo = cfg->arch.cinfo;
5110 if (cinfo->ret.storage == ArgValuetypeInReg) {
5111 ArgInfo *ainfo = &cinfo->ret;
5112 MonoInst *inst = cfg->ret;
5114 for (quad = 0; quad < 2; quad ++) {
5115 switch (ainfo->pair_storage [quad]) {
5117 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5119 case ArgInFloatSSEReg:
5120 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5122 case ArgInDoubleSSEReg:
5123 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5128 g_assert_not_reached ();
5133 if (cfg->arch.omit_fp) {
5134 if (cfg->arch.stack_alloc_size)
5135 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5139 async_exc_point (code);
5142 cfg->code_len = code - cfg->native_code;
5144 g_assert (cfg->code_len < cfg->code_size);
5148 mono_arch_emit_exceptions (MonoCompile *cfg)
5150 MonoJumpInfo *patch_info;
5153 MonoClass *exc_classes [16];
5154 guint8 *exc_throw_start [16], *exc_throw_end [16];
5155 guint32 code_size = 0;
5157 /* Compute needed space */
5158 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5159 if (patch_info->type == MONO_PATCH_INFO_EXC)
5161 if (patch_info->type == MONO_PATCH_INFO_R8)
5162 code_size += 8 + 15; /* sizeof (double) + alignment */
5163 if (patch_info->type == MONO_PATCH_INFO_R4)
5164 code_size += 4 + 15; /* sizeof (float) + alignment */
5167 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5168 cfg->code_size *= 2;
5169 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5170 mono_jit_stats.code_reallocs++;
5173 code = cfg->native_code + cfg->code_len;
5175 /* add code to raise exceptions */
5177 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5178 switch (patch_info->type) {
5179 case MONO_PATCH_INFO_EXC: {
5180 MonoClass *exc_class;
5184 amd64_patch (patch_info->ip.i + cfg->native_code, code);
5186 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5187 g_assert (exc_class);
5188 throw_ip = patch_info->ip.i;
5190 //x86_breakpoint (code);
5191 /* Find a throw sequence for the same exception class */
5192 for (i = 0; i < nthrows; ++i)
5193 if (exc_classes [i] == exc_class)
5196 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5197 x86_jump_code (code, exc_throw_start [i]);
5198 patch_info->type = MONO_PATCH_INFO_NONE;
5202 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5206 exc_classes [nthrows] = exc_class;
5207 exc_throw_start [nthrows] = code;
5209 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5211 patch_info->type = MONO_PATCH_INFO_NONE;
5213 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5215 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5220 exc_throw_end [nthrows] = code;
5232 /* Handle relocations with RIP relative addressing */
5233 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5234 gboolean remove = FALSE;
5236 switch (patch_info->type) {
5237 case MONO_PATCH_INFO_R8:
5238 case MONO_PATCH_INFO_R4: {
5241 /* The SSE opcodes require a 16 byte alignment */
5242 code = (guint8*)ALIGN_TO (code, 16);
5244 pos = cfg->native_code + patch_info->ip.i;
5246 if (IS_REX (pos [1]))
5247 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5249 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5251 if (patch_info->type == MONO_PATCH_INFO_R8) {
5252 *(double*)code = *(double*)patch_info->data.target;
5253 code += sizeof (double);
5255 *(float*)code = *(float*)patch_info->data.target;
5256 code += sizeof (float);
5267 if (patch_info == cfg->patch_info)
5268 cfg->patch_info = patch_info->next;
5272 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5274 tmp->next = patch_info->next;
5279 cfg->code_len = code - cfg->native_code;
5281 g_assert (cfg->code_len < cfg->code_size);
5286 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5289 CallInfo *cinfo = NULL;
5290 MonoMethodSignature *sig;
5292 int i, n, stack_area = 0;
5294 /* Keep this in sync with mono_arch_get_argument_info */
5296 if (enable_arguments) {
5297 /* Allocate a new area on the stack and save arguments there */
5298 sig = mono_method_signature (cfg->method);
5300 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5302 n = sig->param_count + sig->hasthis;
5304 stack_area = ALIGN_TO (n * 8, 16);
5306 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5308 for (i = 0; i < n; ++i) {
5309 inst = cfg->args [i];
5311 if (inst->opcode == OP_REGVAR)
5312 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5314 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5315 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5320 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5321 amd64_set_reg_template (code, AMD64_ARG_REG1);
5322 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5323 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5325 if (enable_arguments)
5326 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5340 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5343 int save_mode = SAVE_NONE;
5344 MonoMethod *method = cfg->method;
5345 int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5348 case MONO_TYPE_VOID:
5349 /* special case string .ctor icall */
5350 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5351 save_mode = SAVE_EAX;
5353 save_mode = SAVE_NONE;
5357 save_mode = SAVE_EAX;
5361 save_mode = SAVE_XMM;
5363 case MONO_TYPE_GENERICINST:
5364 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5365 save_mode = SAVE_EAX;
5369 case MONO_TYPE_VALUETYPE:
5370 save_mode = SAVE_STRUCT;
5373 save_mode = SAVE_EAX;
5377 /* Save the result and copy it into the proper argument register */
5378 switch (save_mode) {
5380 amd64_push_reg (code, AMD64_RAX);
5382 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5383 if (enable_arguments)
5384 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5388 if (enable_arguments)
5389 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5392 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5393 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5395 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5397 * The result is already in the proper argument register so no copying
5404 g_assert_not_reached ();
5407 /* Set %al since this is a varargs call */
5408 if (save_mode == SAVE_XMM)
5409 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5411 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5413 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5414 amd64_set_reg_template (code, AMD64_ARG_REG1);
5415 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5417 /* Restore result */
5418 switch (save_mode) {
5420 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5421 amd64_pop_reg (code, AMD64_RAX);
5427 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5428 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5429 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5434 g_assert_not_reached ();
5441 mono_arch_flush_icache (guint8 *code, gint size)
5447 mono_arch_flush_register_windows (void)
5452 mono_arch_is_inst_imm (gint64 imm)
5454 return amd64_is_imm32 (imm);
5458 * Determine whenever the trap whose info is in SIGINFO is caused by
5462 mono_arch_is_int_overflow (void *sigctx, void *info)
5469 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5471 rip = (guint8*)ctx.rip;
5473 if (IS_REX (rip [0])) {
5474 reg = amd64_rex_b (rip [0]);
5480 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5482 reg += x86_modrm_rm (rip [1]);
5522 g_assert_not_reached ();
5534 mono_arch_get_patch_offset (guint8 *code)
5540 * mono_breakpoint_clean_code:
5542 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5543 * breakpoints in the original code, they are removed in the copy.
5545 * Returns TRUE if no sw breakpoint was present.
5548 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5551 gboolean can_write = TRUE;
5553 * If method_start is non-NULL we need to perform bound checks, since we access memory
5554 * at code - offset we could go before the start of the method and end up in a different
5555 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5558 if (!method_start || code - offset >= method_start) {
5559 memcpy (buf, code - offset, size);
5561 int diff = code - method_start;
5562 memset (buf, 0, size);
5563 memcpy (buf + offset - diff, method_start, diff + size - offset);
5566 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5567 int idx = mono_breakpoint_info_index [i];
5571 ptr = mono_breakpoint_info [idx].address;
5572 if (ptr >= code && ptr < code + size) {
5573 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5575 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5576 buf [ptr - code] = saved_byte;
5583 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5590 mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5598 * A given byte sequence can match more than case here, so we have to be
5599 * really careful about the ordering of the cases. Longer sequences
5601 * There are two types of calls:
5602 * - direct calls: 0xff address_byte 8/32 bits displacement
5603 * - indirect calls: nop nop nop <call>
5604 * The nops make sure we don't confuse the instruction preceeding an indirect
5605 * call with a direct call.
5607 if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5608 /* call OFFSET(%rip) */
5609 disp = *(guint32*)(code + 3);
5610 return (gpointer*)(code + disp + 7);
5611 } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
5612 /* call *[reg+disp32] using indexed addressing */
5613 /* The LLVM JIT emits this, and we emit it too for %r12 */
5614 if (IS_REX (code [-1])) {
5616 g_assert (amd64_rex_x (rex) == 0);
5618 reg = amd64_sib_base (code [2]);
5619 disp = *(gint32*)(code + 3);
5620 } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5621 /* call *[reg+disp32] */
5622 if (IS_REX (code [0]))
5624 reg = amd64_modrm_rm (code [2]);
5625 disp = *(gint32*)(code + 3);
5626 /* R10 is clobbered by the IMT thunk code */
5627 g_assert (reg != AMD64_R10);
5628 } else if (code [2] == 0xe8) {
5631 } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
5632 /* call *[r12+disp8] using indexed addressing */
5633 if (IS_REX (code [2]))
5635 reg = amd64_sib_base (code [5]);
5636 disp = *(gint8*)(code + 6);
5637 } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5640 } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5641 /* call *[reg+disp8] */
5642 if (IS_REX (code [3]))
5644 reg = amd64_modrm_rm (code [5]);
5645 disp = *(gint8*)(code + 6);
5646 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5648 else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5650 if (IS_REX (code [4]))
5652 reg = amd64_modrm_rm (code [6]);
5656 g_assert_not_reached ();
5658 reg += amd64_rex_b (rex);
5660 /* R11 is clobbered by the trampoline code */
5661 g_assert (reg != AMD64_R11);
5663 *displacement = disp;
5668 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5672 vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5675 return (gpointer*)((char*)vt + displacement);
5679 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5681 int this_reg = AMD64_ARG_REG1;
5683 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5687 gsctx = mono_get_generic_context_from_code (code);
5689 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5691 if (cinfo->ret.storage != ArgValuetypeInReg)
5692 this_reg = AMD64_ARG_REG2;
5700 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5702 return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
5705 #define MAX_ARCH_DELEGATE_PARAMS 10
5708 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5710 guint8 *code, *start;
5713 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5716 /* FIXME: Support more cases */
5717 if (MONO_TYPE_ISSTRUCT (sig->ret))
5721 static guint8* cached = NULL;
5726 start = code = mono_global_codeman_reserve (64);
5728 /* Replace the this argument with the target */
5729 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5730 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5731 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5733 g_assert ((code - start) < 64);
5735 mono_debug_add_delegate_trampoline (start, code - start);
5737 mono_memory_barrier ();
5741 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5742 for (i = 0; i < sig->param_count; ++i)
5743 if (!mono_is_regsize_var (sig->params [i]))
5745 if (sig->param_count > 4)
5748 code = cache [sig->param_count];
5752 start = code = mono_global_codeman_reserve (64);
5754 if (sig->param_count == 0) {
5755 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5757 /* We have to shift the arguments left */
5758 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5759 for (i = 0; i < sig->param_count; ++i) {
5760 #ifdef PLATFORM_WIN32
5762 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5764 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
5766 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5770 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5772 g_assert ((code - start) < 64);
5774 mono_debug_add_delegate_trampoline (start, code - start);
5776 mono_memory_barrier ();
5778 cache [sig->param_count] = start;
5785 * Support for fast access to the thread-local lmf structure using the GS
5786 * segment register on NPTL + kernel 2.6.x.
5789 static gboolean tls_offset_inited = FALSE;
5792 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5794 if (!tls_offset_inited) {
5795 #ifdef PLATFORM_WIN32
5797 * We need to init this multiple times, since when we are first called, the key might not
5798 * be initialized yet.
5800 appdomain_tls_offset = mono_domain_get_tls_key ();
5801 lmf_tls_offset = mono_get_jit_tls_key ();
5802 thread_tls_offset = mono_thread_get_tls_key ();
5803 lmf_addr_tls_offset = mono_get_jit_tls_key ();
5805 /* Only 64 tls entries can be accessed using inline code */
5806 if (appdomain_tls_offset >= 64)
5807 appdomain_tls_offset = -1;
5808 if (lmf_tls_offset >= 64)
5809 lmf_tls_offset = -1;
5810 if (thread_tls_offset >= 64)
5811 thread_tls_offset = -1;
5813 tls_offset_inited = TRUE;
5815 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5817 appdomain_tls_offset = mono_domain_get_tls_offset ();
5818 lmf_tls_offset = mono_get_lmf_tls_offset ();
5819 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5820 thread_tls_offset = mono_thread_get_tls_offset ();
5826 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5830 #ifdef MONO_ARCH_HAVE_IMT
5832 #define CMP_SIZE (6 + 1)
5833 #define CMP_REG_REG_SIZE (4 + 1)
5834 #define BR_SMALL_SIZE 2
5835 #define BR_LARGE_SIZE 6
5836 #define MOV_REG_IMM_SIZE 10
5837 #define MOV_REG_IMM_32BIT_SIZE 6
5838 #define JUMP_REG_SIZE (2 + 1)
5841 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5843 int i, distance = 0;
5844 for (i = start; i < target; ++i)
5845 distance += imt_entries [i]->chunk_size;
5850 * LOCKING: called with the domain lock held
5853 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5854 gpointer fail_tramp)
5858 guint8 *code, *start;
5859 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5861 for (i = 0; i < count; ++i) {
5862 MonoIMTCheckItem *item = imt_entries [i];
5863 if (item->is_equals) {
5864 if (item->check_target_idx) {
5865 if (!item->compare_done) {
5866 if (amd64_is_imm32 (item->key))
5867 item->chunk_size += CMP_SIZE;
5869 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5871 if (item->has_target_code) {
5872 item->chunk_size += MOV_REG_IMM_SIZE;
5874 if (vtable_is_32bit)
5875 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5877 item->chunk_size += MOV_REG_IMM_SIZE;
5879 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5882 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
5883 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
5885 if (vtable_is_32bit)
5886 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5888 item->chunk_size += MOV_REG_IMM_SIZE;
5889 item->chunk_size += JUMP_REG_SIZE;
5890 /* with assert below:
5891 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5896 if (amd64_is_imm32 (item->key))
5897 item->chunk_size += CMP_SIZE;
5899 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5900 item->chunk_size += BR_LARGE_SIZE;
5901 imt_entries [item->check_target_idx]->compare_done = TRUE;
5903 size += item->chunk_size;
5906 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5908 code = mono_domain_code_reserve (domain, size);
5910 for (i = 0; i < count; ++i) {
5911 MonoIMTCheckItem *item = imt_entries [i];
5912 item->code_target = code;
5913 if (item->is_equals) {
5914 gboolean fail_case = !item->check_target_idx && fail_tramp;
5916 if (item->check_target_idx || fail_case) {
5917 if (!item->compare_done || fail_case) {
5918 if (amd64_is_imm32 (item->key))
5919 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5921 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5922 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5925 item->jmp_code = code;
5926 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5927 /* See the comment below about R10 */
5928 if (item->has_target_code) {
5929 amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
5930 amd64_jump_reg (code, AMD64_R10);
5932 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5933 amd64_jump_membase (code, AMD64_R10, 0);
5937 amd64_patch (item->jmp_code, code);
5938 amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
5939 amd64_jump_reg (code, AMD64_R10);
5940 item->jmp_code = NULL;
5943 /* enable the commented code to assert on wrong method */
5945 if (amd64_is_imm32 (item->key))
5946 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5948 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5949 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5951 item->jmp_code = code;
5952 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5953 /* See the comment below about R10 */
5954 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5955 amd64_jump_membase (code, AMD64_R10, 0);
5956 amd64_patch (item->jmp_code, code);
5957 amd64_breakpoint (code);
5958 item->jmp_code = NULL;
5960 /* We're using R10 here because R11
5961 needs to be preserved. R10 needs
5962 to be preserved for calls which
5963 require a runtime generic context,
5964 but interface calls don't. */
5965 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
5966 amd64_jump_membase (code, AMD64_R10, 0);
5970 if (amd64_is_imm32 (item->key))
5971 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
5973 amd64_mov_reg_imm (code, AMD64_R10, item->key);
5974 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5976 item->jmp_code = code;
5977 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5978 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5980 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5982 g_assert (code - item->code_target <= item->chunk_size);
5984 /* patch the branches to get to the target items */
5985 for (i = 0; i < count; ++i) {
5986 MonoIMTCheckItem *item = imt_entries [i];
5987 if (item->jmp_code) {
5988 if (item->check_target_idx) {
5989 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5995 mono_stats.imt_thunks_size += code - start;
5996 g_assert (code - start <= size);
6002 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6004 return regs [MONO_ARCH_IMT_REG];
6008 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6010 return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6015 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6017 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6021 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6023 MonoInst *ins = NULL;
6026 if (cmethod->klass == mono_defaults.math_class) {
6027 if (strcmp (cmethod->name, "Sin") == 0) {
6029 } else if (strcmp (cmethod->name, "Cos") == 0) {
6031 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6033 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6038 MONO_INST_NEW (cfg, ins, opcode);
6039 ins->type = STACK_R8;
6040 ins->dreg = mono_alloc_freg (cfg);
6041 ins->sreg1 = args [0]->dreg;
6042 MONO_ADD_INS (cfg->cbb, ins);
6046 if (cfg->opt & MONO_OPT_CMOV) {
6047 if (strcmp (cmethod->name, "Min") == 0) {
6048 if (fsig->params [0]->type == MONO_TYPE_I4)
6050 if (fsig->params [0]->type == MONO_TYPE_U4)
6051 opcode = OP_IMIN_UN;
6052 else if (fsig->params [0]->type == MONO_TYPE_I8)
6054 else if (fsig->params [0]->type == MONO_TYPE_U8)
6055 opcode = OP_LMIN_UN;
6056 } else if (strcmp (cmethod->name, "Max") == 0) {
6057 if (fsig->params [0]->type == MONO_TYPE_I4)
6059 if (fsig->params [0]->type == MONO_TYPE_U4)
6060 opcode = OP_IMAX_UN;
6061 else if (fsig->params [0]->type == MONO_TYPE_I8)
6063 else if (fsig->params [0]->type == MONO_TYPE_U8)
6064 opcode = OP_LMAX_UN;
6069 MONO_INST_NEW (cfg, ins, opcode);
6070 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6071 ins->dreg = mono_alloc_ireg (cfg);
6072 ins->sreg1 = args [0]->dreg;
6073 ins->sreg2 = args [1]->dreg;
6074 MONO_ADD_INS (cfg->cbb, ins);
6078 /* OP_FREM is not IEEE compatible */
6079 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6080 MONO_INST_NEW (cfg, ins, OP_FREM);
6081 ins->inst_i0 = args [0];
6082 ins->inst_i1 = args [1];
6088 * Can't implement CompareExchange methods this way since they have
6096 mono_arch_print_tree (MonoInst *tree, int arity)
6101 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6105 if (appdomain_tls_offset == -1)
6108 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6109 ins->inst_offset = appdomain_tls_offset;
6113 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6117 if (thread_tls_offset == -1)
6120 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6121 ins->inst_offset = thread_tls_offset;
6125 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6128 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6131 case AMD64_RCX: return (gpointer)ctx->rcx;
6132 case AMD64_RDX: return (gpointer)ctx->rdx;
6133 case AMD64_RBX: return (gpointer)ctx->rbx;
6134 case AMD64_RBP: return (gpointer)ctx->rbp;
6135 case AMD64_RSP: return (gpointer)ctx->rsp;
6138 return _CTX_REG (ctx, rax, reg);
6140 return _CTX_REG (ctx, r12, reg - 12);
6142 g_assert_not_reached ();