mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "mini-amd64.h"
  30 #include "inssel.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 void mini_emit_memcpy2 (MonoCompile *cfg, int destreg, int doffset, int srcreg, int soffset, int size, int align);
  97
  98 const char*
  99 mono_arch_regname (int reg)
 100 {
 101         switch (reg) {
 102         case AMD64_RAX: return "%rax";
 103         case AMD64_RBX: return "%rbx";
 104         case AMD64_RCX: return "%rcx";
 105         case AMD64_RDX: return "%rdx";
 106         case AMD64_RSP: return "%rsp";
 107         case AMD64_RBP: return "%rbp";
 108         case AMD64_RDI: return "%rdi";
 109         case AMD64_RSI: return "%rsi";
 110         case AMD64_R8: return "%r8";
 111         case AMD64_R9: return "%r9";
 112         case AMD64_R10: return "%r10";
 113         case AMD64_R11: return "%r11";
 114         case AMD64_R12: return "%r12";
 115         case AMD64_R13: return "%r13";
 116         case AMD64_R14: return "%r14";
 117         case AMD64_R15: return "%r15";
 118         }
 119         return "unknown";
 120 }
 121
 122 static const char * xmmregs [] = {
 123         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 124         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 125 };
 126
 127 const char*
 128 mono_arch_fregname (int reg)
 129 {
 130         if (reg < AMD64_XMM_NREG)
 131                 return xmmregs [reg];
 132         else
 133                 return "unknown";
 134 }
 135
 136 G_GNUC_UNUSED static void
 137 break_count (void)
 138 {
 139 }
 140
 141 G_GNUC_UNUSED static gboolean
 142 debug_count (void)
 143 {
 144         static int count = 0;
 145         count ++;
 146
 147         if (!getenv ("COUNT"))
 148                 return TRUE;
 149
 150         if (count == atoi (getenv ("COUNT"))) {
 151                 break_count ();
 152         }
 153
 154         if (count > atoi (getenv ("COUNT"))) {
 155                 return FALSE;
 156         }
 157
 158         return TRUE;
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 static inline void
 182 amd64_patch (unsigned char* code, gpointer target)
 183 {
 184         guint8 rex = 0;
 185
 186         /* Skip REX */
 187         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 188                 rex = code [0];
 189                 code += 1;
 190         }
 191
 192         if ((code [0] & 0xf8) == 0xb8) {
 193                 /* amd64_set_reg_template */
 194                 *(guint64*)(code + 1) = (guint64)target;
 195         }
 196         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 197                 /* mov 0(%rip), %dreg */
 198                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 199         }
 200         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 201                 /* call *<OFFSET>(%rip) */
 202                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 203         }
 204         else if ((code [0] == 0xe8)) {
 205                 /* call <DISP> */
 206                 gint64 disp = (guint8*)target - (guint8*)code;
 207                 g_assert (amd64_is_imm32 (disp));
 208                 x86_patch (code, (unsigned char*)target);
 209         }
 210         else
 211                 x86_patch (code, (unsigned char*)target);
 212 }
 213
 214 void
 215 mono_amd64_patch (unsigned char* code, gpointer target)
 216 {
 217         amd64_patch (code, target);
 218 }
 219
 220 typedef enum {
 221         ArgInIReg,
 222         ArgInFloatSSEReg,
 223         ArgInDoubleSSEReg,
 224         ArgOnStack,
 225         ArgValuetypeInReg,
 226         ArgValuetypeAddrInIReg,
 227         ArgNone /* only in pair_storage */
 228 } ArgStorage;
 229
 230 typedef struct {
 231         gint16 offset;
 232         gint8  reg;
 233         ArgStorage storage;
 234
 235         /* Only if storage == ArgValuetypeInReg */
 236         ArgStorage pair_storage [2];
 237         gint8 pair_regs [2];
 238 } ArgInfo;
 239
 240 typedef struct {
 241         int nargs;
 242         guint32 stack_usage;
 243         guint32 reg_usage;
 244         guint32 freg_usage;
 245         gboolean need_stack_align;
 246         ArgInfo ret;
 247         ArgInfo sig_cookie;
 248         ArgInfo args [1];
 249 } CallInfo;
 250
 251 #define DEBUG(a) if (cfg->verbose_level > 1) a
 252
 253 #define NEW_ICONST(cfg,dest,val) do {   \
 254                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 255                 (dest)->opcode = OP_ICONST;     \
 256                 (dest)->inst_c0 = (val);        \
 257                 (dest)->type = STACK_I4;        \
 258         } while (0)
 259
 260 #ifdef PLATFORM_WIN32
 261 #define PARAM_REGS 4
 262
 263 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 264
 265 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 266 #else
 267 #define PARAM_REGS 6
 268
 269 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 270
 271  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 272 #endif
 273
 274 static void inline
 275 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 276 {
 277     ainfo->offset = *stack_size;
 278
 279     if (*gr >= PARAM_REGS) {
 280                 ainfo->storage = ArgOnStack;
 281                 (*stack_size) += sizeof (gpointer);
 282     }
 283     else {
 284                 ainfo->storage = ArgInIReg;
 285                 ainfo->reg = param_regs [*gr];
 286                 (*gr) ++;
 287     }
 288 }
 289
 290 #ifdef PLATFORM_WIN32
 291 #define FLOAT_PARAM_REGS 4
 292 #else
 293 #define FLOAT_PARAM_REGS 8
 294 #endif
 295
 296 static void inline
 297 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 298 {
 299     ainfo->offset = *stack_size;
 300
 301     if (*gr >= FLOAT_PARAM_REGS) {
 302                 ainfo->storage = ArgOnStack;
 303                 (*stack_size) += sizeof (gpointer);
 304     }
 305     else {
 306                 /* A double register */
 307                 if (is_double)
 308                         ainfo->storage = ArgInDoubleSSEReg;
 309                 else
 310                         ainfo->storage = ArgInFloatSSEReg;
 311                 ainfo->reg = *gr;
 312                 (*gr) += 1;
 313     }
 314 }
 315
 316 typedef enum ArgumentClass {
 317         ARG_CLASS_NO_CLASS,
 318         ARG_CLASS_MEMORY,
 319         ARG_CLASS_INTEGER,
 320         ARG_CLASS_SSE
 321 } ArgumentClass;
 322
 323 static ArgumentClass
 324 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 325 {
 326         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 327         MonoType *ptype;
 328
 329         ptype = mini_type_get_underlying_type (NULL, type);
 330         switch (ptype->type) {
 331         case MONO_TYPE_BOOLEAN:
 332         case MONO_TYPE_CHAR:
 333         case MONO_TYPE_I1:
 334         case MONO_TYPE_U1:
 335         case MONO_TYPE_I2:
 336         case MONO_TYPE_U2:
 337         case MONO_TYPE_I4:
 338         case MONO_TYPE_U4:
 339         case MONO_TYPE_I:
 340         case MONO_TYPE_U:
 341         case MONO_TYPE_STRING:
 342         case MONO_TYPE_OBJECT:
 343         case MONO_TYPE_CLASS:
 344         case MONO_TYPE_SZARRAY:
 345         case MONO_TYPE_PTR:
 346         case MONO_TYPE_FNPTR:
 347         case MONO_TYPE_ARRAY:
 348         case MONO_TYPE_I8:
 349         case MONO_TYPE_U8:
 350                 class2 = ARG_CLASS_INTEGER;
 351                 break;
 352         case MONO_TYPE_R4:
 353         case MONO_TYPE_R8:
 354 #ifdef PLATFORM_WIN32
 355                 class2 = ARG_CLASS_INTEGER;
 356 #else
 357                 class2 = ARG_CLASS_SSE;
 358 #endif
 359                 break;
 360
 361         case MONO_TYPE_TYPEDBYREF:
 362                 g_assert_not_reached ();
 363
 364         case MONO_TYPE_GENERICINST:
 365                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 366                         class2 = ARG_CLASS_INTEGER;
 367                         break;
 368                 }
 369                 /* fall through */
 370         case MONO_TYPE_VALUETYPE: {
 371                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 372                 int i;
 373
 374                 for (i = 0; i < info->num_fields; ++i) {
 375                         class2 = class1;
 376                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 377                 }
 378                 break;
 379         }
 380         default:
 381                 g_assert_not_reached ();
 382         }
 383
 384         /* Merge */
 385         if (class1 == class2)
 386                 ;
 387         else if (class1 == ARG_CLASS_NO_CLASS)
 388                 class1 = class2;
 389         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 390                 class1 = ARG_CLASS_MEMORY;
 391         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 392                 class1 = ARG_CLASS_INTEGER;
 393         else
 394                 class1 = ARG_CLASS_SSE;
 395
 396         return class1;
 397 }
 398
 399 static void
 400 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 401                gboolean is_return,
 402                guint32 *gr, guint32 *fr, guint32 *stack_size)
 403 {
 404         guint32 size, quad, nquads, i;
 405         ArgumentClass args [2];
 406         MonoMarshalType *info = NULL;
 407         MonoClass *klass;
 408         MonoGenericSharingContext tmp_gsctx;
 409
 410         /*
 411          * The gsctx currently contains no data, it is only used for checking whenever
 412          * open types are allowed, some callers like mono_arch_get_argument_info ()
 413          * don't pass it to us, so work around that.
 414          */
 415         if (!gsctx)
 416                 gsctx = &tmp_gsctx;
 417
 418         klass = mono_class_from_mono_type (type);
 419         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 420 #ifndef PLATFORM_WIN32
 421         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 422                 /* We pass and return vtypes of size 8 in a register */
 423         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 424 #else
 425         if (!sig->pinvoke) {
 426 #endif
 427                 /* Allways pass in memory */
 428                 ainfo->offset = *stack_size;
 429                 *stack_size += ALIGN_TO (size, 8);
 430                 ainfo->storage = ArgOnStack;
 431
 432                 return;
 433         }
 434
 435         /* FIXME: Handle structs smaller than 8 bytes */
 436         //if ((size % 8) != 0)
 437         //      NOT_IMPLEMENTED;
 438
 439         if (size > 8)
 440                 nquads = 2;
 441         else
 442                 nquads = 1;
 443
 444         if (!sig->pinvoke) {
 445                 /* Always pass in 1 or 2 integer registers */
 446                 args [0] = ARG_CLASS_INTEGER;
 447                 args [1] = ARG_CLASS_INTEGER;
 448                 /* Only the simplest cases are supported */
 449                 if (is_return && nquads != 1) {
 450                         args [0] = ARG_CLASS_MEMORY;
 451                         args [1] = ARG_CLASS_MEMORY;
 452                 }
 453         } else {
 454                 /*
 455                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 456                  * The X87 and SSEUP stuff is left out since there are no such types in
 457                  * the CLR.
 458                  */
 459                 info = mono_marshal_load_type_info (klass);
 460                 g_assert (info);
 461
 462 #ifndef PLATFORM_WIN32
 463                 if (info->native_size > 16) {
 464                         ainfo->offset = *stack_size;
 465                         *stack_size += ALIGN_TO (info->native_size, 8);
 466                         ainfo->storage = ArgOnStack;
 467
 468                         return;
 469                 }
 470 #else
 471                 switch (info->native_size) {
 472                 case 1: case 2: case 4: case 8:
 473                         break;
 474                 default:
 475                         if (is_return) {
 476                                 ainfo->storage = ArgOnStack;
 477                                 ainfo->offset = *stack_size;
 478                                 *stack_size += ALIGN_TO (info->native_size, 8);
 479                         }
 480                         else {
 481                                 ainfo->storage = ArgValuetypeAddrInIReg;
 482
 483                                 if (*gr < PARAM_REGS) {
 484                                         ainfo->pair_storage [0] = ArgInIReg;
 485                                         ainfo->pair_regs [0] = param_regs [*gr];
 486                                         (*gr) ++;
 487                                 }
 488                                 else {
 489                                         ainfo->pair_storage [0] = ArgOnStack;
 490                                         ainfo->offset = *stack_size;
 491                                         *stack_size += 8;
 492                                 }
 493                         }
 494
 495                         return;
 496                 }
 497 #endif
 498
 499                 args [0] = ARG_CLASS_NO_CLASS;
 500                 args [1] = ARG_CLASS_NO_CLASS;
 501                 for (quad = 0; quad < nquads; ++quad) {
 502                         int size;
 503                         guint32 align;
 504                         ArgumentClass class1;
 505
 506                         if (info->num_fields == 0)
 507                                 class1 = ARG_CLASS_MEMORY;
 508                         else
 509                                 class1 = ARG_CLASS_NO_CLASS;
 510                         for (i = 0; i < info->num_fields; ++i) {
 511                                 size = mono_marshal_type_size (info->fields [i].field->type,
 512                                                                                            info->fields [i].mspec,
 513                                                                                            &align, TRUE, klass->unicode);
 514                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 515                                         /* Unaligned field */
 516                                         NOT_IMPLEMENTED;
 517                                 }
 518
 519                                 /* Skip fields in other quad */
 520                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 521                                         continue;
 522                                 if ((quad == 1) && (info->fields [i].offset < 8))
 523                                         continue;
 524
 525                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 526                         }
 527                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 528                         args [quad] = class1;
 529                 }
 530         }
 531
 532         /* Post merger cleanup */
 533         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 534                 args [0] = args [1] = ARG_CLASS_MEMORY;
 535
 536         /* Allocate registers */
 537         {
 538                 int orig_gr = *gr;
 539                 int orig_fr = *fr;
 540
 541                 ainfo->storage = ArgValuetypeInReg;
 542                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 543                 for (quad = 0; quad < nquads; ++quad) {
 544                         switch (args [quad]) {
 545                         case ARG_CLASS_INTEGER:
 546                                 if (*gr >= PARAM_REGS)
 547                                         args [quad] = ARG_CLASS_MEMORY;
 548                                 else {
 549                                         ainfo->pair_storage [quad] = ArgInIReg;
 550                                         if (is_return)
 551                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 552                                         else
 553                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 554                                         (*gr) ++;
 555                                 }
 556                                 break;
 557                         case ARG_CLASS_SSE:
 558                                 if (*fr >= FLOAT_PARAM_REGS)
 559                                         args [quad] = ARG_CLASS_MEMORY;
 560                                 else {
 561                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 562                                         ainfo->pair_regs [quad] = *fr;
 563                                         (*fr) ++;
 564                                 }
 565                                 break;
 566                         case ARG_CLASS_MEMORY:
 567                                 break;
 568                         default:
 569                                 g_assert_not_reached ();
 570                         }
 571                 }
 572
 573                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 574                         /* Revert possible register assignments */
 575                         *gr = orig_gr;
 576                         *fr = orig_fr;
 577
 578                         ainfo->offset = *stack_size;
 579                         if (sig->pinvoke)
 580                                 *stack_size += ALIGN_TO (info->native_size, 8);
 581                         else
 582                                 *stack_size += nquads * sizeof (gpointer);
 583                         ainfo->storage = ArgOnStack;
 584                 }
 585         }
 586 }
 587
 588 /*
 589  * get_call_info:
 590  *
 591  *  Obtain information about a call according to the calling convention.
 592  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 593  * Draft Version 0.23" document for more information.
 594  */
 595 static CallInfo*
 596 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 597 {
 598         guint32 i, gr, fr;
 599         MonoType *ret_type;
 600         int n = sig->hasthis + sig->param_count;
 601         guint32 stack_size = 0;
 602         CallInfo *cinfo;
 603
 604         if (mp)
 605                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 606         else
 607                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 608
 609         gr = 0;
 610         fr = 0;
 611
 612         /* return value */
 613         {
 614                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 615                 switch (ret_type->type) {
 616                 case MONO_TYPE_BOOLEAN:
 617                 case MONO_TYPE_I1:
 618                 case MONO_TYPE_U1:
 619                 case MONO_TYPE_I2:
 620                 case MONO_TYPE_U2:
 621                 case MONO_TYPE_CHAR:
 622                 case MONO_TYPE_I4:
 623                 case MONO_TYPE_U4:
 624                 case MONO_TYPE_I:
 625                 case MONO_TYPE_U:
 626                 case MONO_TYPE_PTR:
 627                 case MONO_TYPE_FNPTR:
 628                 case MONO_TYPE_CLASS:
 629                 case MONO_TYPE_OBJECT:
 630                 case MONO_TYPE_SZARRAY:
 631                 case MONO_TYPE_ARRAY:
 632                 case MONO_TYPE_STRING:
 633                         cinfo->ret.storage = ArgInIReg;
 634                         cinfo->ret.reg = AMD64_RAX;
 635                         break;
 636                 case MONO_TYPE_U8:
 637                 case MONO_TYPE_I8:
 638                         cinfo->ret.storage = ArgInIReg;
 639                         cinfo->ret.reg = AMD64_RAX;
 640                         break;
 641                 case MONO_TYPE_R4:
 642                         cinfo->ret.storage = ArgInFloatSSEReg;
 643                         cinfo->ret.reg = AMD64_XMM0;
 644                         break;
 645                 case MONO_TYPE_R8:
 646                         cinfo->ret.storage = ArgInDoubleSSEReg;
 647                         cinfo->ret.reg = AMD64_XMM0;
 648                         break;
 649                 case MONO_TYPE_GENERICINST:
 650                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 651                                 cinfo->ret.storage = ArgInIReg;
 652                                 cinfo->ret.reg = AMD64_RAX;
 653                                 break;
 654                         }
 655                         /* fall through */
 656                 case MONO_TYPE_VALUETYPE: {
 657                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 658
 659                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 660                         if (cinfo->ret.storage == ArgOnStack)
 661                                 /* The caller passes the address where the value is stored */
 662                                 add_general (&gr, &stack_size, &cinfo->ret);
 663                         break;
 664                 }
 665                 case MONO_TYPE_TYPEDBYREF:
 666                         /* Same as a valuetype with size 24 */
 667                         add_general (&gr, &stack_size, &cinfo->ret);
 668                         ;
 669                         break;
 670                 case MONO_TYPE_VOID:
 671                         break;
 672                 default:
 673                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 674                 }
 675         }
 676
 677         /* this */
 678         if (sig->hasthis)
 679                 add_general (&gr, &stack_size, cinfo->args + 0);
 680
 681         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 682                 gr = PARAM_REGS;
 683                 fr = FLOAT_PARAM_REGS;
 684
 685                 /* Emit the signature cookie just before the implicit arguments */
 686                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 687         }
 688
 689         for (i = 0; i < sig->param_count; ++i) {
 690                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 691                 MonoType *ptype;
 692
 693 #ifdef PLATFORM_WIN32
 694                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 695                 if (gr > fr)
 696                         fr = gr;
 697                 else if (fr > gr)
 698                         gr = fr;
 699 #endif
 700
 701                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 702                         /* We allways pass the sig cookie on the stack for simplicity */
 703                         /*
 704                          * Prevent implicit arguments + the sig cookie from being passed
 705                          * in registers.
 706                          */
 707                         gr = PARAM_REGS;
 708                         fr = FLOAT_PARAM_REGS;
 709
 710                         /* Emit the signature cookie just before the implicit arguments */
 711                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 712                 }
 713
 714                 if (sig->params [i]->byref) {
 715                         add_general (&gr, &stack_size, ainfo);
 716                         continue;
 717                 }
 718                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 719                 switch (ptype->type) {
 720                 case MONO_TYPE_BOOLEAN:
 721                 case MONO_TYPE_I1:
 722                 case MONO_TYPE_U1:
 723                         add_general (&gr, &stack_size, ainfo);
 724                         break;
 725                 case MONO_TYPE_I2:
 726                 case MONO_TYPE_U2:
 727                 case MONO_TYPE_CHAR:
 728                         add_general (&gr, &stack_size, ainfo);
 729                         break;
 730                 case MONO_TYPE_I4:
 731                 case MONO_TYPE_U4:
 732                         add_general (&gr, &stack_size, ainfo);
 733                         break;
 734                 case MONO_TYPE_I:
 735                 case MONO_TYPE_U:
 736                 case MONO_TYPE_PTR:
 737                 case MONO_TYPE_FNPTR:
 738                 case MONO_TYPE_CLASS:
 739                 case MONO_TYPE_OBJECT:
 740                 case MONO_TYPE_STRING:
 741                 case MONO_TYPE_SZARRAY:
 742                 case MONO_TYPE_ARRAY:
 743                         add_general (&gr, &stack_size, ainfo);
 744                         break;
 745                 case MONO_TYPE_GENERICINST:
 746                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 747                                 add_general (&gr, &stack_size, ainfo);
 748                                 break;
 749                         }
 750                         /* fall through */
 751                 case MONO_TYPE_VALUETYPE:
 752                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 753                         break;
 754                 case MONO_TYPE_TYPEDBYREF:
 755 #ifdef PLATFORM_WIN32
 756                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 757 #else
 758                         stack_size += sizeof (MonoTypedRef);
 759                         ainfo->storage = ArgOnStack;
 760 #endif
 761                         break;
 762                 case MONO_TYPE_U8:
 763                 case MONO_TYPE_I8:
 764                         add_general (&gr, &stack_size, ainfo);
 765                         break;
 766                 case MONO_TYPE_R4:
 767                         add_float (&fr, &stack_size, ainfo, FALSE);
 768                         break;
 769                 case MONO_TYPE_R8:
 770                         add_float (&fr, &stack_size, ainfo, TRUE);
 771                         break;
 772                 default:
 773                         g_assert_not_reached ();
 774                 }
 775         }
 776
 777         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 778                 gr = PARAM_REGS;
 779                 fr = FLOAT_PARAM_REGS;
 780
 781                 /* Emit the signature cookie just before the implicit arguments */
 782                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 783         }
 784
 785 #ifdef PLATFORM_WIN32
 786         // There always is 32 bytes reserved on the stack when calling on Winx64
 787         stack_size += 0x20;
 788 #endif
 789
 790         if (stack_size & 0x8) {
 791                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 792                 cinfo->need_stack_align = TRUE;
 793                 stack_size += 8;
 794         }
 795
 796         cinfo->stack_usage = stack_size;
 797         cinfo->reg_usage = gr;
 798         cinfo->freg_usage = fr;
 799         return cinfo;
 800 }
 801
 802 /*
 803  * mono_arch_get_argument_info:
 804  * @csig:  a method signature
 805  * @param_count: the number of parameters to consider
 806  * @arg_info: an array to store the result infos
 807  *
 808  * Gathers information on parameters such as size, alignment and
 809  * padding. arg_info should be large enought to hold param_count + 1 entries.
 810  *
 811  * Returns the size of the argument area on the stack.
 812  */
 813 int
 814 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 815 {
 816         int k;
 817         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 818         guint32 args_size = cinfo->stack_usage;
 819
 820         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 821         if (csig->hasthis) {
 822                 arg_info [0].offset = 0;
 823         }
 824
 825         for (k = 0; k < param_count; k++) {
 826                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 827                 /* FIXME: */
 828                 arg_info [k + 1].size = 0;
 829         }
 830
 831         g_free (cinfo);
 832
 833         return args_size;
 834 }
 835
 836 static int
 837 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 838 {
 839 #ifndef _MSC_VER
 840         __asm__ __volatile__ ("cpuid"
 841                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 842                 : "a" (id));
 843 #else
 844         int info[4];
 845         __cpuid(info, id);
 846         *p_eax = info[0];
 847         *p_ebx = info[1];
 848         *p_ecx = info[2];
 849         *p_edx = info[3];
 850 #endif
 851         return 1;
 852 }
 853
 854 /*
 855  * Initialize the cpu to execute managed code.
 856  */
 857 void
 858 mono_arch_cpu_init (void)
 859 {
 860 #ifndef _MSC_VER
 861         guint16 fpcw;
 862
 863         /* spec compliance requires running with double precision */
 864         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 865         fpcw &= ~X86_FPCW_PRECC_MASK;
 866         fpcw |= X86_FPCW_PREC_DOUBLE;
 867         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 868         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 869 #else
 870         /* TODO: This is crashing on Win64 right now.
 871         * _control87 (_PC_53, MCW_PC);
 872         */
 873 #endif
 874 }
 875
 876 /*
 877  * Initialize architecture specific code.
 878  */
 879 void
 880 mono_arch_init (void)
 881 {
 882         InitializeCriticalSection (&mini_arch_mutex);
 883 }
 884
 885 /*
 886  * Cleanup architecture specific code.
 887  */
 888 void
 889 mono_arch_cleanup (void)
 890 {
 891         DeleteCriticalSection (&mini_arch_mutex);
 892 }
 893
 894 /*
 895  * This function returns the optimizations supported on this cpu.
 896  */
 897 guint32
 898 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 899 {
 900         int eax, ebx, ecx, edx;
 901         guint32 opts = 0;
 902
 903         /* FIXME: AMD64 */
 904
 905         *exclude_mask = 0;
 906         /* Feature Flags function, flags returned in EDX. */
 907         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 908                 if (edx & (1 << 15)) {
 909                         opts |= MONO_OPT_CMOV;
 910                         if (edx & 1)
 911                                 opts |= MONO_OPT_FCMOV;
 912                         else
 913                                 *exclude_mask |= MONO_OPT_FCMOV;
 914                 } else
 915                         *exclude_mask |= MONO_OPT_CMOV;
 916         }
 917
 918         return opts;
 919 }
 920
 921 GList *
 922 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 923 {
 924         GList *vars = NULL;
 925         int i;
 926
 927         for (i = 0; i < cfg->num_varinfo; i++) {
 928                 MonoInst *ins = cfg->varinfo [i];
 929                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 930
 931                 /* unused vars */
 932                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 933                         continue;
 934
 935                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 936                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 937                         continue;
 938
 939                 if (mono_is_regsize_var (ins->inst_vtype)) {
 940                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 941                         g_assert (i == vmv->idx);
 942                         vars = g_list_prepend (vars, vmv);
 943                 }
 944         }
 945
 946         vars = mono_varlist_sort (cfg, vars, 0);
 947
 948         return vars;
 949 }
 950
 951 /**
 952  * mono_arch_compute_omit_fp:
 953  *
 954  *   Determine whenever the frame pointer can be eliminated.
 955  */
 956 static void
 957 mono_arch_compute_omit_fp (MonoCompile *cfg)
 958 {
 959         MonoMethodSignature *sig;
 960         MonoMethodHeader *header;
 961         int i, locals_size;
 962         CallInfo *cinfo;
 963
 964         if (cfg->arch.omit_fp_computed)
 965                 return;
 966
 967         header = mono_method_get_header (cfg->method);
 968
 969         sig = mono_method_signature (cfg->method);
 970
 971         if (!cfg->arch.cinfo)
 972                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 973         cinfo = cfg->arch.cinfo;
 974
 975         /*
 976          * FIXME: Remove some of the restrictions.
 977          */
 978         cfg->arch.omit_fp = TRUE;
 979         cfg->arch.omit_fp_computed = TRUE;
 980
 981         if (cfg->disable_omit_fp)
 982                 cfg->arch.omit_fp = FALSE;
 983
 984         if (!debug_omit_fp ())
 985                 cfg->arch.omit_fp = FALSE;
 986         /*
 987         if (cfg->method->save_lmf)
 988                 cfg->arch.omit_fp = FALSE;
 989         */
 990         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 991                 cfg->arch.omit_fp = FALSE;
 992         if (header->num_clauses)
 993                 cfg->arch.omit_fp = FALSE;
 994         if (cfg->param_area)
 995                 cfg->arch.omit_fp = FALSE;
 996         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 997                 cfg->arch.omit_fp = FALSE;
 998         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 999                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1000                 cfg->arch.omit_fp = FALSE;
1001         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1002                 ArgInfo *ainfo = &cinfo->args [i];
1003
1004                 if (ainfo->storage == ArgOnStack) {
1005                         /*
1006                          * The stack offset can only be determined when the frame
1007                          * size is known.
1008                          */
1009                         cfg->arch.omit_fp = FALSE;
1010                 }
1011         }
1012
1013         locals_size = 0;
1014         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1015                 MonoInst *ins = cfg->varinfo [i];
1016                 int ialign;
1017
1018                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1019         }
1020
1021         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1022                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1023                 cfg->arch.omit_fp = FALSE;
1024         }
1025 }
1026
1027 GList *
1028 mono_arch_get_global_int_regs (MonoCompile *cfg)
1029 {
1030         GList *regs = NULL;
1031
1032         mono_arch_compute_omit_fp (cfg);
1033
1034         if (cfg->globalra) {
1035                 if (cfg->arch.omit_fp)
1036                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1037
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1041                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1042                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1043
1044                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1045                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1046                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1047                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1051                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1052         } else {
1053                 if (cfg->arch.omit_fp)
1054                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1055
1056                 /* We use the callee saved registers for global allocation */
1057                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1058                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1059                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1060                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1061                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1062         }
1063
1064         return regs;
1065 }
1066
1067 GList*
1068 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1069 {
1070         GList *regs = NULL;
1071         int i;
1072
1073         /* All XMM registers */
1074         for (i = 0; i < 16; ++i)
1075                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1076
1077         return regs;
1078 }
1079
1080 GList*
1081 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1082 {
1083         static GList *r = NULL;
1084
1085         if (r == NULL) {
1086                 GList *regs = NULL;
1087
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1093                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1094
1095                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1096                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1097                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1098                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1099                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1100                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1101                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1102                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1103
1104                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1105         }
1106
1107         return r;
1108 }
1109
1110 GList*
1111 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1112 {
1113         int i;
1114         static GList *r = NULL;
1115
1116         if (r == NULL) {
1117                 GList *regs = NULL;
1118
1119                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1120                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1121
1122                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1123         }
1124
1125         return r;
1126 }
1127
1128 /*
1129  * mono_arch_regalloc_cost:
1130  *
1131  *  Return the cost, in number of memory references, of the action of
1132  * allocating the variable VMV into a register during global register
1133  * allocation.
1134  */
1135 guint32
1136 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1137 {
1138         MonoInst *ins = cfg->varinfo [vmv->idx];
1139
1140         if (cfg->method->save_lmf)
1141                 /* The register is already saved */
1142                 /* substract 1 for the invisible store in the prolog */
1143                 return (ins->opcode == OP_ARG) ? 0 : 1;
1144         else
1145                 /* push+pop */
1146                 return (ins->opcode == OP_ARG) ? 1 : 2;
1147 }
1148
1149 /*
1150  * mono_arch_fill_argument_info:
1151  *
1152  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1153  * of the method.
1154  */
1155 void
1156 mono_arch_fill_argument_info (MonoCompile *cfg)
1157 {
1158         MonoMethodSignature *sig;
1159         MonoMethodHeader *header;
1160         MonoInst *ins;
1161         int i;
1162         CallInfo *cinfo;
1163
1164         header = mono_method_get_header (cfg->method);
1165
1166         sig = mono_method_signature (cfg->method);
1167
1168         cinfo = cfg->arch.cinfo;
1169
1170         /*
1171          * Contrary to mono_arch_allocate_vars (), the information should describe
1172          * where the arguments are at the beginning of the method, not where they can be
1173          * accessed during the execution of the method. The later makes no sense for the
1174          * global register allocator, since a variable can be in more than one location.
1175          */
1176         if (sig->ret->type != MONO_TYPE_VOID) {
1177                 switch (cinfo->ret.storage) {
1178                 case ArgInIReg:
1179                 case ArgInFloatSSEReg:
1180                 case ArgInDoubleSSEReg:
1181                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1182                                 cfg->vret_addr->opcode = OP_REGVAR;
1183                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1184                         }
1185                         else {
1186                                 cfg->ret->opcode = OP_REGVAR;
1187                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1188                         }
1189                         break;
1190                 case ArgValuetypeInReg:
1191                         cfg->ret->opcode = OP_REGOFFSET;
1192                         cfg->ret->inst_basereg = -1;
1193                         cfg->ret->inst_offset = -1;
1194                         break;
1195                 default:
1196                         g_assert_not_reached ();
1197                 }
1198         }
1199
1200         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1201                 ArgInfo *ainfo = &cinfo->args [i];
1202                 MonoType *arg_type;
1203
1204                 ins = cfg->args [i];
1205
1206                 if (sig->hasthis && (i == 0))
1207                         arg_type = &mono_defaults.object_class->byval_arg;
1208                 else
1209                         arg_type = sig->params [i - sig->hasthis];
1210
1211                 switch (ainfo->storage) {
1212                 case ArgInIReg:
1213                 case ArgInFloatSSEReg:
1214                 case ArgInDoubleSSEReg:
1215                         ins->opcode = OP_REGVAR;
1216                         ins->inst_c0 = ainfo->reg;
1217                         break;
1218                 case ArgOnStack:
1219                         ins->opcode = OP_REGOFFSET;
1220                         ins->inst_basereg = -1;
1221                         ins->inst_offset = -1;
1222                         break;
1223                 case ArgValuetypeInReg:
1224                         /* Dummy */
1225                         ins->opcode = OP_NOP;
1226                         break;
1227                 default:
1228                         g_assert_not_reached ();
1229                 }
1230         }
1231 }
1232
1233 void
1234 mono_arch_allocate_vars (MonoCompile *cfg)
1235 {
1236         MonoMethodSignature *sig;
1237         MonoMethodHeader *header;
1238         MonoInst *ins;
1239         int i, offset;
1240         guint32 locals_stack_size, locals_stack_align;
1241         gint32 *offsets;
1242         CallInfo *cinfo;
1243
1244         header = mono_method_get_header (cfg->method);
1245
1246         sig = mono_method_signature (cfg->method);
1247
1248         cinfo = cfg->arch.cinfo;
1249
1250         mono_arch_compute_omit_fp (cfg);
1251
1252         /*
1253          * We use the ABI calling conventions for managed code as well.
1254          * Exception: valuetypes are never passed or returned in registers.
1255          */
1256
1257         if (cfg->arch.omit_fp) {
1258                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1259                 cfg->frame_reg = AMD64_RSP;
1260                 offset = 0;
1261         } else {
1262                 /* Locals are allocated backwards from %fp */
1263                 cfg->frame_reg = AMD64_RBP;
1264                 offset = 0;
1265         }
1266
1267         if (cfg->method->save_lmf) {
1268                 /* Reserve stack space for saving LMF */
1269                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1270                 g_assert (offset == 0);
1271                 if (cfg->arch.omit_fp) {
1272                         cfg->arch.lmf_offset = offset;
1273                         offset += sizeof (MonoLMF);
1274                 }
1275                 else {
1276                         offset += sizeof (MonoLMF);
1277                         cfg->arch.lmf_offset = -offset;
1278                 }
1279         } else {
1280                 if (cfg->arch.omit_fp)
1281                         cfg->arch.reg_save_area_offset = offset;
1282                 /* Reserve space for caller saved registers */
1283                 for (i = 0; i < AMD64_NREG; ++i)
1284                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1285                                 offset += sizeof (gpointer);
1286                         }
1287         }
1288
1289         if (sig->ret->type != MONO_TYPE_VOID) {
1290                 switch (cinfo->ret.storage) {
1291                 case ArgInIReg:
1292                 case ArgInFloatSSEReg:
1293                 case ArgInDoubleSSEReg:
1294                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1295                                 if (cfg->globalra) {
1296                                         cfg->vret_addr->opcode = OP_REGVAR;
1297                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1298                                 } else {
1299                                         /* The register is volatile */
1300                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1301                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1302                                         if (cfg->arch.omit_fp) {
1303                                                 cfg->vret_addr->inst_offset = offset;
1304                                                 offset += 8;
1305                                         } else {
1306                                                 offset += 8;
1307                                                 cfg->vret_addr->inst_offset = -offset;
1308                                         }
1309                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1310                                                 printf ("vret_addr =");
1311                                                 mono_print_ins (cfg->vret_addr);
1312                                         }
1313                                 }
1314                         }
1315                         else {
1316                                 cfg->ret->opcode = OP_REGVAR;
1317                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1318                         }
1319                         break;
1320                 case ArgValuetypeInReg:
1321                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1322                         cfg->ret->opcode = OP_REGOFFSET;
1323                         cfg->ret->inst_basereg = cfg->frame_reg;
1324                         if (cfg->arch.omit_fp) {
1325                                 cfg->ret->inst_offset = offset;
1326                                 offset += 16;
1327                         } else {
1328                                 offset += 16;
1329                                 cfg->ret->inst_offset = - offset;
1330                         }
1331                         break;
1332                 default:
1333                         g_assert_not_reached ();
1334                 }
1335                 if (!cfg->globalra)
1336                         cfg->ret->dreg = cfg->ret->inst_c0;
1337         }
1338
1339         /* Allocate locals */
1340         if (!cfg->globalra) {
1341                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1342                 if (locals_stack_align) {
1343                         offset += (locals_stack_align - 1);
1344                         offset &= ~(locals_stack_align - 1);
1345                 }
1346                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1347                         if (offsets [i] != -1) {
1348                                 MonoInst *ins = cfg->varinfo [i];
1349                                 ins->opcode = OP_REGOFFSET;
1350                                 ins->inst_basereg = cfg->frame_reg;
1351                                 if (cfg->arch.omit_fp)
1352                                         ins->inst_offset = (offset + offsets [i]);
1353                                 else
1354                                         ins->inst_offset = - (offset + offsets [i]);
1355                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1356                         }
1357                 }
1358                 offset += locals_stack_size;
1359         }
1360
1361         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1362                 g_assert (!cfg->arch.omit_fp);
1363                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1364                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1365         }
1366
1367         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1368                 ins = cfg->args [i];
1369                 if (ins->opcode != OP_REGVAR) {
1370                         ArgInfo *ainfo = &cinfo->args [i];
1371                         gboolean inreg = TRUE;
1372                         MonoType *arg_type;
1373
1374                         if (sig->hasthis && (i == 0))
1375                                 arg_type = &mono_defaults.object_class->byval_arg;
1376                         else
1377                                 arg_type = sig->params [i - sig->hasthis];
1378
1379                         if (cfg->globalra) {
1380                                 /* The new allocator needs info about the original locations of the arguments */
1381                                 switch (ainfo->storage) {
1382                                 case ArgInIReg:
1383                                 case ArgInFloatSSEReg:
1384                                 case ArgInDoubleSSEReg:
1385                                         ins->opcode = OP_REGVAR;
1386                                         ins->inst_c0 = ainfo->reg;
1387                                         break;
1388                                 case ArgOnStack:
1389                                         g_assert (!cfg->arch.omit_fp);
1390                                         ins->opcode = OP_REGOFFSET;
1391                                         ins->inst_basereg = cfg->frame_reg;
1392                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1393                                         break;
1394                                 case ArgValuetypeInReg:
1395                                         ins->opcode = OP_REGOFFSET;
1396                                         ins->inst_basereg = cfg->frame_reg;
1397                                         /* These arguments are saved to the stack in the prolog */
1398                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1399                                         if (cfg->arch.omit_fp) {
1400                                                 ins->inst_offset = offset;
1401                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1402                                         } else {
1403                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1404                                                 ins->inst_offset = - offset;
1405                                         }
1406                                         break;
1407                                 default:
1408                                         g_assert_not_reached ();
1409                                 }
1410
1411                                 continue;
1412                         }
1413
1414                         /* FIXME: Allocate volatile arguments to registers */
1415                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1416                                 inreg = FALSE;
1417
1418                         /*
1419                          * Under AMD64, all registers used to pass arguments to functions
1420                          * are volatile across calls.
1421                          * FIXME: Optimize this.
1422                          */
1423                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1424                                 inreg = FALSE;
1425
1426                         ins->opcode = OP_REGOFFSET;
1427
1428                         switch (ainfo->storage) {
1429                         case ArgInIReg:
1430                         case ArgInFloatSSEReg:
1431                         case ArgInDoubleSSEReg:
1432                                 if (inreg) {
1433                                         ins->opcode = OP_REGVAR;
1434                                         ins->dreg = ainfo->reg;
1435                                 }
1436                                 break;
1437                         case ArgOnStack:
1438                                 g_assert (!cfg->arch.omit_fp);
1439                                 ins->opcode = OP_REGOFFSET;
1440                                 ins->inst_basereg = cfg->frame_reg;
1441                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1442                                 break;
1443                         case ArgValuetypeInReg:
1444                                 break;
1445                         case ArgValuetypeAddrInIReg: {
1446                                 MonoInst *indir;
1447                                 g_assert (!cfg->arch.omit_fp);
1448
1449                                 MONO_INST_NEW (cfg, indir, 0);
1450                                 indir->opcode = OP_REGOFFSET;
1451                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1452                                         indir->inst_basereg = cfg->frame_reg;
1453                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1454                                         offset += (sizeof (gpointer));
1455                                         indir->inst_offset = - offset;
1456                                 }
1457                                 else {
1458                                         indir->inst_basereg = cfg->frame_reg;
1459                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1460                                 }
1461
1462                                 ins->opcode = OP_VTARG_ADDR;
1463                                 ins->inst_left = indir;
1464
1465                                 break;
1466                         }
1467                         default:
1468                                 NOT_IMPLEMENTED;
1469                         }
1470
1471                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1472                                 ins->opcode = OP_REGOFFSET;
1473                                 ins->inst_basereg = cfg->frame_reg;
1474                                 /* These arguments are saved to the stack in the prolog */
1475                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1476                                 if (cfg->arch.omit_fp) {
1477                                         ins->inst_offset = offset;
1478                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1479                                 } else {
1480                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1481                                         ins->inst_offset = - offset;
1482                                 }
1483                         }
1484                 }
1485         }
1486
1487         cfg->stack_offset = offset;
1488 }
1489
1490 void
1491 mono_arch_create_vars (MonoCompile *cfg)
1492 {
1493         MonoMethodSignature *sig;
1494         CallInfo *cinfo;
1495
1496         sig = mono_method_signature (cfg->method);
1497
1498         if (!cfg->arch.cinfo)
1499                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1500         cinfo = cfg->arch.cinfo;
1501
1502         if (cinfo->ret.storage == ArgValuetypeInReg)
1503                 cfg->ret_var_is_local = TRUE;
1504
1505         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1506                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1507                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1508                         printf ("vret_addr = ");
1509                         mono_print_ins (cfg->vret_addr);
1510                 }
1511         }
1512 }
1513
1514 static void
1515 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1516 {
1517         switch (storage) {
1518         case ArgInIReg:
1519                 arg->opcode = OP_OUTARG_REG;
1520                 arg->inst_left = tree;
1521                 arg->inst_call = call;
1522                 arg->backend.reg3 = reg;
1523                 break;
1524         case ArgInFloatSSEReg:
1525                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1526                 arg->inst_left = tree;
1527                 arg->inst_call = call;
1528                 arg->backend.reg3 = reg;
1529                 break;
1530         case ArgInDoubleSSEReg:
1531                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1532                 arg->inst_left = tree;
1533                 arg->inst_call = call;
1534                 arg->backend.reg3 = reg;
1535                 break;
1536         default:
1537                 g_assert_not_reached ();
1538         }
1539 }
1540
1541 static void
1542 add_outarg_reg2 (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1543 {
1544         MonoInst *ins;
1545
1546         switch (storage) {
1547         case ArgInIReg:
1548                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1549                 ins->dreg = mono_alloc_ireg (cfg);
1550                 ins->sreg1 = tree->dreg;
1551                 MONO_ADD_INS (cfg->cbb, ins);
1552                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1553                 break;
1554         case ArgInFloatSSEReg:
1555                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1556                 ins->dreg = mono_alloc_freg (cfg);
1557                 ins->sreg1 = tree->dreg;
1558                 MONO_ADD_INS (cfg->cbb, ins);
1559
1560                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1561                 break;
1562         case ArgInDoubleSSEReg:
1563                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1564                 ins->dreg = mono_alloc_freg (cfg);
1565                 ins->sreg1 = tree->dreg;
1566                 MONO_ADD_INS (cfg->cbb, ins);
1567
1568                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1569
1570                 break;
1571         default:
1572                 g_assert_not_reached ();
1573         }
1574 }
1575
1576 static int
1577 arg_storage_to_ldind (ArgStorage storage)
1578 {
1579         switch (storage) {
1580         case ArgInIReg:
1581                 return CEE_LDIND_I;
1582         case ArgInDoubleSSEReg:
1583                 return CEE_LDIND_R8;
1584         case ArgInFloatSSEReg:
1585                 return CEE_LDIND_R4;
1586         default:
1587                 g_assert_not_reached ();
1588         }
1589
1590         return -1;
1591 }
1592
1593 static int
1594 arg_storage_to_load_membase (ArgStorage storage)
1595 {
1596         switch (storage) {
1597         case ArgInIReg:
1598                 return OP_LOAD_MEMBASE;
1599         case ArgInDoubleSSEReg:
1600                 return OP_LOADR8_MEMBASE;
1601         case ArgInFloatSSEReg:
1602                 return OP_LOADR4_MEMBASE;
1603         default:
1604                 g_assert_not_reached ();
1605         }
1606
1607         return -1;
1608 }
1609
1610 static void
1611 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1612 {
1613         MonoInst *arg;
1614         MonoMethodSignature *tmp_sig;
1615         MonoInst *sig_arg;
1616
1617         /* FIXME: Add support for signature tokens to AOT */
1618         cfg->disable_aot = TRUE;
1619
1620         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1621
1622         /*
1623          * mono_ArgIterator_Setup assumes the signature cookie is
1624          * passed first and all the arguments which were before it are
1625          * passed on the stack after the signature. So compensate by
1626          * passing a different signature.
1627          */
1628         tmp_sig = mono_metadata_signature_dup (call->signature);
1629         tmp_sig->param_count -= call->signature->sentinelpos;
1630         tmp_sig->sentinelpos = 0;
1631         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1632
1633         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1634         sig_arg->inst_p0 = tmp_sig;
1635
1636         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1637         arg->inst_left = sig_arg;
1638         arg->type = STACK_PTR;
1639
1640         /* prepend, so they get reversed */
1641         arg->next = call->out_args;
1642         call->out_args = arg;
1643 }
1644
1645 /*
1646  * take the arguments and generate the arch-specific
1647  * instructions to properly call the function in call.
1648  * This includes pushing, moving arguments to the right register
1649  * etc.
1650  */
1651 MonoCallInst*
1652 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1653         MonoInst *arg, *in;
1654         MonoMethodSignature *sig;
1655         int i, n, stack_size;
1656         CallInfo *cinfo;
1657         ArgInfo *ainfo;
1658
1659         stack_size = 0;
1660
1661         sig = call->signature;
1662         n = sig->param_count + sig->hasthis;
1663
1664         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1665
1666         if (cfg->method->save_lmf) {
1667                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1668                 arg->next = call->out_args;
1669                 call->out_args = arg;
1670         }
1671
1672         for (i = 0; i < n; ++i) {
1673                 ainfo = cinfo->args + i;
1674
1675                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1676                         /* Emit the signature cookie just before the implicit arguments */
1677                         emit_sig_cookie (cfg, call, cinfo);
1678                 }
1679
1680                 if (is_virtual && i == 0) {
1681                         /* the argument will be attached to the call instruction */
1682                         in = call->args [i];
1683                 } else {
1684                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1685                         in = call->args [i];
1686                         arg->cil_code = in->cil_code;
1687                         arg->inst_left = in;
1688                         arg->type = in->type;
1689                         /* prepend, so they get reversed */
1690                         arg->next = call->out_args;
1691                         call->out_args = arg;
1692 #if 0
1693                         if (!cinfo->stack_usage)
1694                                 /* Keep the assignments to the arg registers in order if possible */
1695                                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1696                         else
1697                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1698 #endif
1699
1700                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1701                                 guint32 align;
1702                                 guint32 size;
1703
1704                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1705                                         size = sizeof (MonoTypedRef);
1706                                         align = sizeof (gpointer);
1707                                 }
1708                                 else
1709                                 if (sig->pinvoke)
1710                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1711                                 else {
1712                                         /*
1713                                          * Other backends use mini_type_stack_size (), but that
1714                                          * aligns the size to 8, which is larger than the size of
1715                                          * the source, leading to reads of invalid memory if the
1716                                          * source is at the end of address space.
1717                                          */
1718                                         size = mono_class_value_size (in->klass, &align);
1719                                 }
1720                                 if (ainfo->storage == ArgValuetypeInReg) {
1721                                         if (ainfo->pair_storage [1] == ArgNone) {
1722                                                 MonoInst *load;
1723
1724                                                 /* Simpler case */
1725
1726                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1727                                                 load->inst_left = in;
1728
1729                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1730                                         }
1731                                         else {
1732                                                 /* Trees can't be shared so make a copy */
1733                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1734                                                 MonoInst *load, *load2, *offset_ins;
1735
1736                                                 /* Reg1 */
1737                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1738                                                 load->ssa_op = MONO_SSA_LOAD;
1739                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1740
1741                                                 NEW_ICONST (cfg, offset_ins, 0);
1742                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1743                                                 load2->inst_left = load;
1744                                                 load2->inst_right = offset_ins;
1745
1746                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1747                                                 load->inst_left = load2;
1748
1749                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1750
1751                                                 /* Reg2 */
1752                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1753                                                 load->ssa_op = MONO_SSA_LOAD;
1754                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1755
1756                                                 NEW_ICONST (cfg, offset_ins, 8);
1757                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1758                                                 load2->inst_left = load;
1759                                                 load2->inst_right = offset_ins;
1760
1761                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1762                                                 load->inst_left = load2;
1763
1764                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1765                                                 arg->cil_code = in->cil_code;
1766                                                 arg->type = in->type;
1767                                                 /* prepend, so they get reversed */
1768                                                 arg->next = call->out_args;
1769                                                 call->out_args = arg;
1770
1771                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1772
1773                                                 /* Prepend a copy inst */
1774                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1775                                                 arg->cil_code = in->cil_code;
1776                                                 arg->ssa_op = MONO_SSA_STORE;
1777                                                 arg->inst_left = vtaddr;
1778                                                 arg->inst_right = in;
1779                                                 arg->type = in->type;
1780
1781                                                 /* prepend, so they get reversed */
1782                                                 arg->next = call->out_args;
1783                                                 call->out_args = arg;
1784                                         }
1785                                 }
1786                                 else if (ainfo->storage == ArgValuetypeAddrInIReg){
1787
1788                                         /* Add a temp variable to the method*/
1789                                         MonoInst *load;
1790                                         MonoInst *vtaddr = mono_compile_create_var (cfg, &in->klass->byval_arg, OP_LOCAL);
1791
1792                                         MONO_INST_NEW (cfg, load, OP_LDADDR);
1793                                         load->ssa_op = MONO_SSA_LOAD;
1794                                         load->inst_left = vtaddr;
1795
1796                                         if (ainfo->pair_storage [0] == ArgInIReg) {
1797                                                 /* Inserted after the copy.  Load the address of the temp to the argument regster.*/
1798                                                 arg->opcode = OP_OUTARG_REG;
1799                                                 arg->inst_left = load;
1800                                                 arg->inst_call = call;
1801                                                 arg->backend.reg3 =  ainfo->pair_regs [0];
1802                                         }
1803                                         else {
1804                                                 /* Inserted after the copy.  Load the address of the temp on the stack.*/
1805                                                 arg->opcode = OP_OUTARG_VT;
1806                                                 arg->inst_left = load;
1807                                                 arg->type = STACK_PTR;
1808                                                 arg->klass = mono_defaults.int_class;
1809                                                 arg->backend.is_pinvoke = sig->pinvoke;
1810                                                 arg->inst_imm = size;
1811                                         }
1812
1813                                         /*Copy the argument to the temp variable.*/
1814                                         MONO_INST_NEW (cfg, load, OP_MEMCPY);
1815                                         load->backend.memcpy_args = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoMemcpyArgs));
1816                                         load->backend.memcpy_args->size = size;
1817                                         load->backend.memcpy_args->align = align;
1818                                         load->inst_left = (cfg)->varinfo [vtaddr->inst_c0];
1819                                         load->inst_right = in->inst_i0;
1820
1821                                         // FIXME:
1822                                         g_assert_not_reached ();
1823                                         //MONO_INST_LIST_ADD (&load->node, &call->out_args);
1824                                 }
1825                                 else {
1826                                         arg->opcode = OP_OUTARG_VT;
1827                                         arg->klass = in->klass;
1828                                         arg->backend.is_pinvoke = sig->pinvoke;
1829                                         arg->inst_imm = size;
1830                                 }
1831                         }
1832                         else {
1833                                 switch (ainfo->storage) {
1834                                 case ArgInIReg:
1835                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1836                                         break;
1837                                 case ArgInFloatSSEReg:
1838                                 case ArgInDoubleSSEReg:
1839                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1840                                         break;
1841                                 case ArgOnStack:
1842                                         arg->opcode = OP_OUTARG;
1843                                         if (!sig->params [i - sig->hasthis]->byref) {
1844                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1845                                                         arg->opcode = OP_OUTARG_R4;
1846                                                 else
1847                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1848                                                                 arg->opcode = OP_OUTARG_R8;
1849                                         }
1850                                         break;
1851                                 default:
1852                                         g_assert_not_reached ();
1853                                 }
1854                         }
1855                 }
1856         }
1857
1858         /* Handle the case where there are no implicit arguments */
1859         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1860                 emit_sig_cookie (cfg, call, cinfo);
1861         }
1862
1863         if (cinfo->ret.storage == ArgValuetypeInReg) {
1864                 /* This is needed by mono_arch_emit_this_vret_args () */
1865                 if (!cfg->arch.vret_addr_loc) {
1866                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1867                         /* Prevent it from being register allocated or optimized away */
1868                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1869                 }
1870         }
1871
1872         if (cinfo->need_stack_align) {
1873                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1874                 arg->inst_c0 = 8;
1875                 /* prepend, so they get reversed */
1876                 arg->next = call->out_args;
1877                 call->out_args = arg;
1878         }
1879
1880 #ifdef PLATFORM_WIN32
1881         /* Always reserve 32 bytes of stack space on Win64 */
1882         /*MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1883         arg->inst_c0 = 32;
1884         MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);*/
1885         NOT_IMPLEMENTED;
1886 #endif
1887
1888 #if 0
1889         if (cfg->method->save_lmf) {
1890                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1891                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1892         }
1893 #endif
1894
1895         call->stack_usage = cinfo->stack_usage;
1896         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1897         cfg->flags |= MONO_CFG_HAS_CALLS;
1898
1899         return call;
1900 }
1901
1902 static void
1903 emit_sig_cookie2 (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1904 {
1905         MonoInst *arg;
1906         MonoMethodSignature *tmp_sig;
1907         MonoInst *sig_arg;
1908
1909         if (call->tail_call)
1910                 NOT_IMPLEMENTED;
1911
1912         /* FIXME: Add support for signature tokens to AOT */
1913         cfg->disable_aot = TRUE;
1914
1915         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1916
1917         /*
1918          * mono_ArgIterator_Setup assumes the signature cookie is
1919          * passed first and all the arguments which were before it are
1920          * passed on the stack after the signature. So compensate by
1921          * passing a different signature.
1922          */
1923         tmp_sig = mono_metadata_signature_dup (call->signature);
1924         tmp_sig->param_count -= call->signature->sentinelpos;
1925         tmp_sig->sentinelpos = 0;
1926         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1927
1928         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1929         sig_arg->dreg = mono_alloc_ireg (cfg);
1930         sig_arg->inst_p0 = tmp_sig;
1931         MONO_ADD_INS (cfg->cbb, sig_arg);
1932
1933         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1934         arg->sreg1 = sig_arg->dreg;
1935         MONO_ADD_INS (cfg->cbb, arg);
1936 }
1937
1938 #define NEW_VARSTORE(cfg,dest,var,vartype,inst) do {    \
1939         MONO_INST_NEW ((cfg), (dest), OP_MOVE); \
1940                 (dest)->opcode = mono_type_to_regmove ((cfg), (vartype));    \
1941                 (dest)->klass = (var)->klass;   \
1942         (dest)->sreg1 = (inst)->dreg; \
1943                 (dest)->dreg = (var)->dreg;   \
1944         if ((dest)->opcode == OP_VMOVE) (dest)->klass = mono_class_from_mono_type ((vartype)); \
1945         } while (0)
1946
1947 #define NEW_ARGSTORE(cfg,dest,num,inst) NEW_VARSTORE ((cfg), (dest), cfg->args [(num)], cfg->arg_types [(num)], (inst))
1948
1949 #define EMIT_NEW_ARGSTORE(cfg,dest,num,inst) do { NEW_ARGSTORE ((cfg), (dest), (num), (inst)); MONO_ADD_INS ((cfg)->cbb, (dest)); } while (0)
1950
1951 void
1952 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1953 {
1954         MonoInst *arg, *in;
1955         MonoMethodSignature *sig;
1956         int i, n, stack_size;
1957         CallInfo *cinfo;
1958         ArgInfo *ainfo;
1959
1960         stack_size = 0;
1961
1962         sig = call->signature;
1963         n = sig->param_count + sig->hasthis;
1964
1965         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1966
1967         if (cinfo->need_stack_align) {
1968                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1969         }
1970
1971         /*
1972          * Emit all parameters passed in registers in non-reverse order for better readability
1973          * and to help the optimization in emit_prolog ().
1974          */
1975         for (i = 0; i < n; ++i) {
1976                 ainfo = cinfo->args + i;
1977
1978                 in = call->args [i];
1979
1980                 if (ainfo->storage == ArgInIReg)
1981                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1982         }
1983
1984         for (i = n - 1; i >= 0; --i) {
1985                 ainfo = cinfo->args + i;
1986
1987                 in = call->args [i];
1988
1989                 switch (ainfo->storage) {
1990                 case ArgInIReg:
1991                         /* Already done */
1992                         break;
1993                 case ArgInFloatSSEReg:
1994                 case ArgInDoubleSSEReg:
1995                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1996                         break;
1997                 case ArgOnStack:
1998                 case ArgValuetypeInReg:
1999                 case ArgValuetypeAddrInIReg:
2000                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2001                                 MonoInst *call_inst = (MonoInst*)call;
2002                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2003                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2004                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2005                                 guint32 align;
2006                                 guint32 size;
2007
2008                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2009                                         size = sizeof (MonoTypedRef);
2010                                         align = sizeof (gpointer);
2011                                 }
2012                                 else {
2013                                         if (sig->pinvoke)
2014                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2015                                         else {
2016                                                 /*
2017                                                  * Other backends use mono_type_stack_size (), but that
2018                                                  * aligns the size to 8, which is larger than the size of
2019                                                  * the source, leading to reads of invalid memory if the
2020                                                  * source is at the end of address space.
2021                                                  */
2022                                                 size = mono_class_value_size (in->klass, &align);
2023                                         }
2024                                 }
2025                                 g_assert (in->klass);
2026
2027                                 if (size > 0) {
2028                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2029                                         arg->sreg1 = in->dreg;
2030                                         arg->klass = in->klass;
2031                                         arg->backend.size = size;
2032                                         arg->inst_p0 = call;
2033                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2034                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2035
2036                                         MONO_ADD_INS (cfg->cbb, arg);
2037                                 }
2038                         } else {
2039                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2040                                 arg->sreg1 = in->dreg;
2041                                 if (!sig->params [i - sig->hasthis]->byref) {
2042                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2043                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2044                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
2045                                                 arg->inst_destbasereg = X86_ESP;
2046                                                 arg->inst_offset = 0;
2047                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2048                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2049                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
2050                                                 arg->inst_destbasereg = X86_ESP;
2051                                                 arg->inst_offset = 0;
2052                                         }
2053                                 }
2054                                 MONO_ADD_INS (cfg->cbb, arg);
2055                         }
2056                         break;
2057                 default:
2058                         g_assert_not_reached ();
2059                 }
2060
2061                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2062                         /* Emit the signature cookie just before the implicit arguments */
2063                         emit_sig_cookie2 (cfg, call, cinfo);
2064                 }
2065         }
2066
2067         /* Handle the case where there are no implicit arguments */
2068         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
2069                 emit_sig_cookie2 (cfg, call, cinfo);
2070         }
2071
2072         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2073                 MonoInst *vtarg;
2074
2075                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2076                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2077                                 /*
2078                                  * Tell the JIT to use a more efficient calling convention: call using
2079                                  * OP_CALL, compute the result location after the call, and save the
2080                                  * result there.
2081                                  */
2082                                 call->vret_in_reg = TRUE;
2083                                 /*
2084                                  * Nullify the instruction computing the vret addr to enable
2085                                  * future optimizations.
2086                                  */
2087                                 if (call->vret_var)
2088                                         NULLIFY_INS (call->vret_var);
2089                         } else {
2090                                 if (call->tail_call)
2091                                         NOT_IMPLEMENTED;
2092                                 /*
2093                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2094                                  * the stack. Push the address here, so the call instruction can
2095                                  * access it.
2096                                  */
2097                                 if (!cfg->arch.vret_addr_loc) {
2098                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2099                                         /* Prevent it from being register allocated or optimized away */
2100                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2101                                 }
2102
2103                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2104                         }
2105                 }
2106                 else {
2107                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2108                         vtarg->sreg1 = call->vret_var->dreg;
2109                         vtarg->dreg = mono_alloc_preg (cfg);
2110                         MONO_ADD_INS (cfg->cbb, vtarg);
2111
2112                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2113                 }
2114         }
2115
2116 #ifdef PLATFORM_WIN32
2117         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2118                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2119         }
2120 #endif
2121
2122         if (cfg->method->save_lmf) {
2123                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2124                 MONO_ADD_INS (cfg->cbb, arg);
2125         }
2126
2127         call->stack_usage = cinfo->stack_usage;
2128 }
2129
2130 void
2131 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2132 {
2133         MonoInst *arg;
2134         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2135         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2136         int size = ins->backend.size;
2137
2138         if (ainfo->storage == ArgValuetypeInReg) {
2139                 MonoInst *load;
2140                 int part;
2141
2142                 for (part = 0; part < 2; ++part) {
2143                         if (ainfo->pair_storage [part] == ArgNone)
2144                                 continue;
2145
2146                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2147                         load->inst_basereg = src->dreg;
2148                         load->inst_offset = part * sizeof (gpointer);
2149
2150                         switch (ainfo->pair_storage [part]) {
2151                         case ArgInIReg:
2152                                 load->dreg = mono_alloc_ireg (cfg);
2153                                 break;
2154                         case ArgInDoubleSSEReg:
2155                         case ArgInFloatSSEReg:
2156                                 load->dreg = mono_alloc_freg (cfg);
2157                                 break;
2158                         default:
2159                                 g_assert_not_reached ();
2160                         }
2161                         MONO_ADD_INS (cfg->cbb, load);
2162
2163                         add_outarg_reg2 (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2164                 }
2165         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2166                 MonoInst *vtaddr, *load;
2167                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2168
2169                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2170                 load->inst_p0 = vtaddr;
2171                 vtaddr->flags |= MONO_INST_INDIRECT;
2172                 load->type = STACK_MP;
2173                 load->klass = vtaddr->klass;
2174                 load->dreg = mono_alloc_ireg (cfg);
2175                 MONO_ADD_INS (cfg->cbb, load);
2176                 mini_emit_memcpy2 (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2177
2178                 if (ainfo->pair_storage [0] == ArgInIReg) {
2179                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2180                         arg->dreg = mono_alloc_ireg (cfg);
2181                         arg->sreg1 = load->dreg;
2182                         arg->inst_imm = 0;
2183                         MONO_ADD_INS (cfg->cbb, arg);
2184                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2185                 } else {
2186                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2187                         arg->sreg1 = load->dreg;
2188                         MONO_ADD_INS (cfg->cbb, arg);
2189                 }
2190         } else {
2191                 if (size == 8) {
2192                         /* Can't use this for < 8 since it does an 8 byte memory load */
2193                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2194                         arg->inst_basereg = src->dreg;
2195                         arg->inst_offset = 0;
2196                         MONO_ADD_INS (cfg->cbb, arg);
2197                 } else if (size <= 40) {
2198                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2199                         mini_emit_memcpy2 (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2200                 } else {
2201                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2202                         arg->inst_basereg = src->dreg;
2203                         arg->inst_offset = 0;
2204                         arg->inst_imm = size;
2205                         MONO_ADD_INS (cfg->cbb, arg);
2206                 }
2207         }
2208 }
2209
2210 void
2211 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2212 {
2213         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2214
2215         if (!ret->byref) {
2216                 if (ret->type == MONO_TYPE_R4) {
2217                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2218                         return;
2219                 } else if (ret->type == MONO_TYPE_R8) {
2220                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2221                         return;
2222                 }
2223         }
2224
2225         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2226 }
2227
2228 #define EMIT_COND_BRANCH(ins,cond,sign) \
2229 if (ins->flags & MONO_INST_BRLABEL) { \
2230         if (ins->inst_i0->inst_c0) { \
2231                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
2232         } else { \
2233                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
2234                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2235                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
2236                         x86_branch8 (code, cond, 0, sign); \
2237                 else \
2238                         x86_branch32 (code, cond, 0, sign); \
2239         } \
2240 } else { \
2241         if (ins->inst_true_bb->native_offset) { \
2242                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2243         } else { \
2244                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2245                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2246                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
2247                         x86_branch8 (code, cond, 0, sign); \
2248                 else \
2249                         x86_branch32 (code, cond, 0, sign); \
2250         } \
2251 }
2252
2253 /* emit an exception if condition is fail */
2254 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2255         do {                                                        \
2256                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2257                 if (tins == NULL) {                                                                             \
2258                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2259                                         MONO_PATCH_INFO_EXC, exc_name);  \
2260                         x86_branch32 (code, cond, 0, signed);               \
2261                 } else {        \
2262                         EMIT_COND_BRANCH (tins, cond, signed);  \
2263                 }                       \
2264         } while (0);
2265
2266 #define EMIT_FPCOMPARE(code) do { \
2267         amd64_fcompp (code); \
2268         amd64_fnstsw (code); \
2269 } while (0);
2270
2271 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2272     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2273         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2274         amd64_ ##op (code); \
2275         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2276         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2277 } while (0);
2278
2279 static guint8*
2280 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2281 {
2282         gboolean no_patch = FALSE;
2283
2284         /*
2285          * FIXME: Add support for thunks
2286          */
2287         {
2288                 gboolean near_call = FALSE;
2289
2290                 /*
2291                  * Indirect calls are expensive so try to make a near call if possible.
2292                  * The caller memory is allocated by the code manager so it is
2293                  * guaranteed to be at a 32 bit offset.
2294                  */
2295
2296                 if (patch_type != MONO_PATCH_INFO_ABS) {
2297                         /* The target is in memory allocated using the code manager */
2298                         near_call = TRUE;
2299
2300                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2301                                 if (((MonoMethod*)data)->klass->image->aot_module)
2302                                         /* The callee might be an AOT method */
2303                                         near_call = FALSE;
2304                                 if (((MonoMethod*)data)->dynamic)
2305                                         /* The target is in malloc-ed memory */
2306                                         near_call = FALSE;
2307                         }
2308
2309                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2310                                 /*
2311                                  * The call might go directly to a native function without
2312                                  * the wrapper.
2313                                  */
2314                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2315                                 if (mi) {
2316                                         gconstpointer target = mono_icall_get_wrapper (mi);
2317                                         if ((((guint64)target) >> 32) != 0)
2318                                                 near_call = FALSE;
2319                                 }
2320                         }
2321                 }
2322                 else {
2323                         if (!cfg->new_ir && mono_find_class_init_trampoline_by_addr (data))
2324                                 near_call = TRUE;
2325                         else if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2326                                 /*
2327                                  * This is not really an optimization, but required because the
2328                                  * generic class init trampolines use R11 to pass the vtable.
2329                                  */
2330                                 near_call = TRUE;
2331                         } else {
2332                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2333                                 if (info) {
2334                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2335                                                 strstr (cfg->method->name, info->name)) {
2336                                                 /* A call to the wrapped function */
2337                                                 if ((((guint64)data) >> 32) == 0)
2338                                                         near_call = TRUE;
2339                                                 no_patch = TRUE;
2340                                         }
2341                                         else if (info->func == info->wrapper) {
2342                                                 /* No wrapper */
2343                                                 if ((((guint64)info->func) >> 32) == 0)
2344                                                         near_call = TRUE;
2345                                         }
2346                                         else {
2347                                                 /* See the comment in mono_codegen () */
2348                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2349                                                         near_call = TRUE;
2350                                         }
2351                                 }
2352                                 else if ((((guint64)data) >> 32) == 0) {
2353                                         near_call = TRUE;
2354                                         no_patch = TRUE;
2355                                 }
2356                         }
2357                 }
2358
2359                 if (cfg->method->dynamic)
2360                         /* These methods are allocated using malloc */
2361                         near_call = FALSE;
2362
2363                 if (cfg->compile_aot)
2364                         near_call = TRUE;
2365
2366 #ifdef MONO_ARCH_NOMAP32BIT
2367                 near_call = FALSE;
2368 #endif
2369
2370                 if (near_call) {
2371                         /*
2372                          * Align the call displacement to an address divisible by 4 so it does
2373                          * not span cache lines. This is required for code patching to work on SMP
2374                          * systems.
2375                          */
2376                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2377                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2378                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2379                         amd64_call_code (code, 0);
2380                 }
2381                 else {
2382                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2383                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2384                         amd64_call_reg (code, GP_SCRATCH_REG);
2385                 }
2386         }
2387
2388         return code;
2389 }
2390
2391 static inline guint8*
2392 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2393 {
2394 #ifdef PLATFORM_WIN32
2395         if (win64_adjust_stack)
2396                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2397 #endif
2398         code = emit_call_body (cfg, code, patch_type, data);
2399 #ifdef PLATFORM_WIN32
2400         if (win64_adjust_stack)
2401                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2402 #endif
2403
2404         return code;
2405 }
2406
2407 static inline int
2408 store_membase_imm_to_store_membase_reg (int opcode)
2409 {
2410         switch (opcode) {
2411         case OP_STORE_MEMBASE_IMM:
2412                 return OP_STORE_MEMBASE_REG;
2413         case OP_STOREI4_MEMBASE_IMM:
2414                 return OP_STOREI4_MEMBASE_REG;
2415         case OP_STOREI8_MEMBASE_IMM:
2416                 return OP_STOREI8_MEMBASE_REG;
2417         }
2418
2419         return -1;
2420 }
2421
2422 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2423
2424 /*
2425  * mono_arch_peephole_pass_1:
2426  *
2427  *   Perform peephole opts which should/can be performed before local regalloc
2428  */
2429 void
2430 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2431 {
2432         MonoInst *ins, *n;
2433
2434         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2435                 MonoInst *last_ins = ins->prev;
2436
2437                 switch (ins->opcode) {
2438                 case OP_ADD_IMM:
2439                 case OP_IADD_IMM:
2440                 case OP_LADD_IMM:
2441                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2442                                 /*
2443                                  * X86_LEA is like ADD, but doesn't have the
2444                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2445                                  * its operand to 64 bit.
2446                                  */
2447                                 ins->opcode = OP_X86_LEA_MEMBASE;
2448                                 ins->inst_basereg = ins->sreg1;
2449                         }
2450                         break;
2451                 case OP_LXOR:
2452                 case OP_IXOR:
2453                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2454                                 MonoInst *ins2;
2455
2456                                 /*
2457                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2458                                  * the latter has length 2-3 instead of 6 (reverse constant
2459                                  * propagation). These instruction sequences are very common
2460                                  * in the initlocals bblock.
2461                                  */
2462                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2463                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2464                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2465                                                 ins2->sreg1 = ins->dreg;
2466                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2467                                                 /* Continue */
2468                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2469                                                 NULLIFY_INS (ins2);
2470                                                 /* Continue */
2471                                         } else {
2472                                                 break;
2473                                         }
2474                                 }
2475                         }
2476                         break;
2477                 case OP_COMPARE_IMM:
2478                 case OP_LCOMPARE_IMM:
2479                         /* OP_COMPARE_IMM (reg, 0)
2480                          * -->
2481                          * OP_AMD64_TEST_NULL (reg)
2482                          */
2483                         if (!ins->inst_imm)
2484                                 ins->opcode = OP_AMD64_TEST_NULL;
2485                         break;
2486                 case OP_ICOMPARE_IMM:
2487                         if (!ins->inst_imm)
2488                                 ins->opcode = OP_X86_TEST_NULL;
2489                         break;
2490                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2491                         /*
2492                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2493                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2494                          * -->
2495                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2496                          * OP_COMPARE_IMM reg, imm
2497                          *
2498                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2499                          */
2500                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2501                             ins->inst_basereg == last_ins->inst_destbasereg &&
2502                             ins->inst_offset == last_ins->inst_offset) {
2503                                         ins->opcode = OP_ICOMPARE_IMM;
2504                                         ins->sreg1 = last_ins->sreg1;
2505
2506                                         /* check if we can remove cmp reg,0 with test null */
2507                                         if (!ins->inst_imm)
2508                                                 ins->opcode = OP_X86_TEST_NULL;
2509                                 }
2510
2511                         break;
2512                 }
2513
2514                 mono_peephole_ins (bb, ins);
2515         }
2516 }
2517
2518 void
2519 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2520 {
2521         MonoInst *ins, *n;
2522
2523         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2524                 switch (ins->opcode) {
2525                 case OP_ICONST:
2526                 case OP_I8CONST: {
2527                         /* reg = 0 -> XOR (reg, reg) */
2528                         /* XOR sets cflags on x86, so we cant do it always */
2529                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2530                                 ins->opcode = OP_LXOR;
2531                                 ins->sreg1 = ins->dreg;
2532                                 ins->sreg2 = ins->dreg;
2533                                 /* Fall through */
2534                         } else {
2535                                 break;
2536                         }
2537                 }
2538                 case OP_LXOR:
2539                         /*
2540                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2541                          * 0 result into 64 bits.
2542                          */
2543                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2544                                 ins->opcode = OP_IXOR;
2545                         }
2546                         /* Fall through */
2547                 case OP_IXOR:
2548                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2549                                 MonoInst *ins2;
2550
2551                                 /*
2552                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2553                                  * the latter has length 2-3 instead of 6 (reverse constant
2554                                  * propagation). These instruction sequences are very common
2555                                  * in the initlocals bblock.
2556                                  */
2557                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2558                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2559                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2560                                                 ins2->sreg1 = ins->dreg;
2561                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2562                                                 /* Continue */
2563                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2564                                                 NULLIFY_INS (ins2);
2565                                                 /* Continue */
2566                                         } else {
2567                                                 break;
2568                                         }
2569                                 }
2570                         }
2571                         break;
2572                 case OP_IADD_IMM:
2573                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2574                                 ins->opcode = OP_X86_INC_REG;
2575                         break;
2576                 case OP_ISUB_IMM:
2577                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2578                                 ins->opcode = OP_X86_DEC_REG;
2579                         break;
2580                 }
2581
2582                 mono_peephole_ins (bb, ins);
2583         }
2584 }
2585
2586 #define NEW_INS(cfg,ins,dest,op) do {   \
2587                 MONO_INST_NEW ((cfg), (dest), (op)); \
2588         (dest)->cil_code = (ins)->cil_code; \
2589         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2590         } while (0)
2591
2592 /*
2593  * mono_arch_lowering_pass:
2594  *
2595  *  Converts complex opcodes into simpler ones so that each IR instruction
2596  * corresponds to one machine instruction.
2597  */
2598 void
2599 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2600 {
2601         MonoInst *ins, *n, *temp;
2602
2603         if (bb->max_vreg > cfg->rs->next_vreg)
2604                 cfg->rs->next_vreg = bb->max_vreg;
2605
2606         /*
2607          * FIXME: Need to add more instructions, but the current machine
2608          * description can't model some parts of the composite instructions like
2609          * cdq.
2610          */
2611         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2612                 switch (ins->opcode) {
2613                 case OP_DIV_IMM:
2614                 case OP_REM_IMM:
2615                 case OP_IDIV_IMM:
2616                 case OP_IREM_IMM:
2617                 case OP_IDIV_UN_IMM:
2618                 case OP_IREM_UN_IMM:
2619                         mono_decompose_op_imm (cfg, bb, ins);
2620                         break;
2621                 case OP_COMPARE_IMM:
2622                 case OP_LCOMPARE_IMM:
2623                         if (!amd64_is_imm32 (ins->inst_imm)) {
2624                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2625                                 temp->inst_c0 = ins->inst_imm;
2626                                 if (cfg->globalra)
2627                                         temp->dreg = mono_alloc_ireg (cfg);
2628                                 else
2629                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2630                                 ins->opcode = OP_COMPARE;
2631                                 ins->sreg2 = temp->dreg;
2632                         }
2633                         break;
2634                 case OP_LOAD_MEMBASE:
2635                 case OP_LOADI8_MEMBASE:
2636                         if (!amd64_is_imm32 (ins->inst_offset)) {
2637                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2638                                 temp->inst_c0 = ins->inst_offset;
2639                                 if (cfg->globalra)
2640                                         temp->dreg = mono_alloc_ireg (cfg);
2641                                 else
2642                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2643                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2644                                 ins->inst_indexreg = temp->dreg;
2645                         }
2646                         break;
2647                 case OP_STORE_MEMBASE_IMM:
2648                 case OP_STOREI8_MEMBASE_IMM:
2649                         if (!amd64_is_imm32 (ins->inst_imm)) {
2650                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2651                                 temp->inst_c0 = ins->inst_imm;
2652                                 if (cfg->globalra)
2653                                         temp->dreg = mono_alloc_ireg (cfg);
2654                                 else
2655                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2656                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2657                                 ins->sreg1 = temp->dreg;
2658                         }
2659                         break;
2660                 default:
2661                         break;
2662                 }
2663         }
2664
2665         bb->max_vreg = cfg->rs->next_vreg;
2666 }
2667
2668 static const int
2669 branch_cc_table [] = {
2670         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2671         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2672         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2673 };
2674
2675 /* Maps CMP_... constants to X86_CC_... constants */
2676 static const int
2677 cc_table [] = {
2678         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2679         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2680 };
2681
2682 static const int
2683 cc_signed_table [] = {
2684         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2685         FALSE, FALSE, FALSE, FALSE
2686 };
2687
2688 /*#include "cprop.c"*/
2689
2690 static unsigned char*
2691 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2692 {
2693         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2694
2695         if (size == 1)
2696                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2697         else if (size == 2)
2698                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2699         return code;
2700 }
2701
2702 static unsigned char*
2703 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2704 {
2705         int sreg = tree->sreg1;
2706         int need_touch = FALSE;
2707
2708 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2709         if (!tree->flags & MONO_INST_INIT)
2710                 need_touch = TRUE;
2711 #endif
2712
2713         if (need_touch) {
2714                 guint8* br[5];
2715
2716                 /*
2717                  * Under Windows:
2718                  * If requested stack size is larger than one page,
2719                  * perform stack-touch operation
2720                  */
2721                 /*
2722                  * Generate stack probe code.
2723                  * Under Windows, it is necessary to allocate one page at a time,
2724                  * "touching" stack after each successful sub-allocation. This is
2725                  * because of the way stack growth is implemented - there is a
2726                  * guard page before the lowest stack page that is currently commited.
2727                  * Stack normally grows sequentially so OS traps access to the
2728                  * guard page and commits more pages when needed.
2729                  */
2730                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2731                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2732
2733                 br[2] = code; /* loop */
2734                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2735                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2736                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2737                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2738                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2739                 amd64_patch (br[3], br[2]);
2740                 amd64_test_reg_reg (code, sreg, sreg);
2741                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2742                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2743
2744                 br[1] = code; x86_jump8 (code, 0);
2745
2746                 amd64_patch (br[0], code);
2747                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2748                 amd64_patch (br[1], code);
2749                 amd64_patch (br[4], code);
2750         }
2751         else
2752                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2753
2754         if (tree->flags & MONO_INST_INIT) {
2755                 int offset = 0;
2756                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2757                         amd64_push_reg (code, AMD64_RAX);
2758                         offset += 8;
2759                 }
2760                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2761                         amd64_push_reg (code, AMD64_RCX);
2762                         offset += 8;
2763                 }
2764                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2765                         amd64_push_reg (code, AMD64_RDI);
2766                         offset += 8;
2767                 }
2768
2769                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2770                 if (sreg != AMD64_RCX)
2771                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2772                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2773
2774                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2775                 amd64_cld (code);
2776                 amd64_prefix (code, X86_REP_PREFIX);
2777                 amd64_stosl (code);
2778
2779                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2780                         amd64_pop_reg (code, AMD64_RDI);
2781                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2782                         amd64_pop_reg (code, AMD64_RCX);
2783                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2784                         amd64_pop_reg (code, AMD64_RAX);
2785         }
2786         return code;
2787 }
2788
2789 static guint8*
2790 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2791 {
2792         CallInfo *cinfo;
2793         guint32 quad;
2794
2795         /* Move return value to the target register */
2796         /* FIXME: do this in the local reg allocator */
2797         switch (ins->opcode) {
2798         case OP_CALL:
2799         case OP_CALL_REG:
2800         case OP_CALL_MEMBASE:
2801         case OP_LCALL:
2802         case OP_LCALL_REG:
2803         case OP_LCALL_MEMBASE:
2804                 g_assert (ins->dreg == AMD64_RAX);
2805                 break;
2806         case OP_FCALL:
2807         case OP_FCALL_REG:
2808         case OP_FCALL_MEMBASE:
2809                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2810                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2811                 }
2812                 else {
2813                         if (ins->dreg != AMD64_XMM0)
2814                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2815                 }
2816                 break;
2817         case OP_VCALL:
2818         case OP_VCALL_REG:
2819         case OP_VCALL_MEMBASE:
2820         case OP_VCALL2:
2821         case OP_VCALL2_REG:
2822         case OP_VCALL2_MEMBASE:
2823                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2824                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2825                         MonoInst *loc = cfg->arch.vret_addr_loc;
2826
2827                         /* Load the destination address */
2828                         g_assert (loc->opcode == OP_REGOFFSET);
2829                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2830
2831                         for (quad = 0; quad < 2; quad ++) {
2832                                 switch (cinfo->ret.pair_storage [quad]) {
2833                                 case ArgInIReg:
2834                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2835                                         break;
2836                                 case ArgInFloatSSEReg:
2837                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2838                                         break;
2839                                 case ArgInDoubleSSEReg:
2840                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2841                                         break;
2842                                 case ArgNone:
2843                                         break;
2844                                 default:
2845                                         NOT_IMPLEMENTED;
2846                                 }
2847                         }
2848                 }
2849                 break;
2850         }
2851
2852         return code;
2853 }
2854
2855 /*
2856  * emit_tls_get:
2857  * @code: buffer to store code to
2858  * @dreg: hard register where to place the result
2859  * @tls_offset: offset info
2860  *
2861  * emit_tls_get emits in @code the native code that puts in the dreg register
2862  * the item in the thread local storage identified by tls_offset.
2863  *
2864  * Returns: a pointer to the end of the stored code
2865  */
2866 static guint8*
2867 emit_tls_get (guint8* code, int dreg, int tls_offset)
2868 {
2869 #ifdef PLATFORM_WIN32
2870         g_assert (tls_offset < 64);
2871         x86_prefix (code, X86_GS_PREFIX);
2872         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2873 #else
2874         if (optimize_for_xen) {
2875                 x86_prefix (code, X86_FS_PREFIX);
2876                 amd64_mov_reg_mem (code, dreg, 0, 8);
2877                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2878         } else {
2879                 x86_prefix (code, X86_FS_PREFIX);
2880                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2881         }
2882 #endif
2883         return code;
2884 }
2885
2886 /*
2887  * emit_load_volatile_arguments:
2888  *
2889  *  Load volatile arguments from the stack to the original input registers.
2890  * Required before a tail call.
2891  */
2892 static guint8*
2893 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2894 {
2895         MonoMethod *method = cfg->method;
2896         MonoMethodSignature *sig;
2897         MonoInst *ins;
2898         CallInfo *cinfo;
2899         guint32 i, quad;
2900
2901         /* FIXME: Generate intermediate code instead */
2902
2903         sig = mono_method_signature (method);
2904
2905         cinfo = cfg->arch.cinfo;
2906
2907         /* This is the opposite of the code in emit_prolog */
2908         if (sig->ret->type != MONO_TYPE_VOID) {
2909                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2910                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2911         }
2912
2913         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2914                 ArgInfo *ainfo = cinfo->args + i;
2915                 MonoType *arg_type;
2916                 ins = cfg->args [i];
2917
2918                 if (sig->hasthis && (i == 0))
2919                         arg_type = &mono_defaults.object_class->byval_arg;
2920                 else
2921                         arg_type = sig->params [i - sig->hasthis];
2922
2923                 if (ins->opcode != OP_REGVAR) {
2924                         switch (ainfo->storage) {
2925                         case ArgInIReg: {
2926                                 guint32 size = 8;
2927
2928                                 /* FIXME: I1 etc */
2929                                 amd64_mov_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset, size);
2930                                 break;
2931                         }
2932                         case ArgInFloatSSEReg:
2933                                 amd64_movss_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2934                                 break;
2935                         case ArgInDoubleSSEReg:
2936                                 amd64_movsd_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2937                                 break;
2938                         case ArgValuetypeInReg:
2939                                 for (quad = 0; quad < 2; quad ++) {
2940                                         switch (ainfo->pair_storage [quad]) {
2941                                         case ArgInIReg:
2942                                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
2943                                                 break;
2944                                         case ArgInFloatSSEReg:
2945                                         case ArgInDoubleSSEReg:
2946                                                 g_assert_not_reached ();
2947                                                 break;
2948                                         case ArgNone:
2949                                                 break;
2950                                         default:
2951                                                 g_assert_not_reached ();
2952                                         }
2953                                 }
2954                                 break;
2955                         case ArgValuetypeAddrInIReg:
2956                                 if (ainfo->pair_storage [0] == ArgInIReg)
2957                                         amd64_mov_reg_membase (code, ainfo->pair_regs [0], ins->inst_left->inst_basereg, ins->inst_left->inst_offset,  sizeof (gpointer));
2958                                 break;
2959                         default:
2960                                 break;
2961                         }
2962                 }
2963                 else {
2964                         g_assert (ainfo->storage == ArgInIReg);
2965
2966                         amd64_mov_reg_reg (code, ainfo->reg, ins->dreg, 8);
2967                 }
2968         }
2969
2970         return code;
2971 }
2972
2973 #define REAL_PRINT_REG(text,reg) \
2974 mono_assert (reg >= 0); \
2975 amd64_push_reg (code, AMD64_RAX); \
2976 amd64_push_reg (code, AMD64_RDX); \
2977 amd64_push_reg (code, AMD64_RCX); \
2978 amd64_push_reg (code, reg); \
2979 amd64_push_imm (code, reg); \
2980 amd64_push_imm (code, text " %d %p\n"); \
2981 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2982 amd64_call_reg (code, AMD64_RAX); \
2983 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2984 amd64_pop_reg (code, AMD64_RCX); \
2985 amd64_pop_reg (code, AMD64_RDX); \
2986 amd64_pop_reg (code, AMD64_RAX);
2987
2988 /* benchmark and set based on cpu */
2989 #define LOOP_ALIGNMENT 8
2990 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2991
2992 #ifndef DISABLE_JIT
2993
2994 void
2995 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2996 {
2997         MonoInst *ins;
2998         MonoCallInst *call;
2999         guint offset;
3000         guint8 *code = cfg->native_code + cfg->code_len;
3001         MonoInst *last_ins = NULL;
3002         guint last_offset = 0;
3003         int max_len, cpos;
3004
3005         if (cfg->opt & MONO_OPT_LOOP) {
3006                 int pad, align = LOOP_ALIGNMENT;
3007                 /* set alignment depending on cpu */
3008                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3009                         pad = align - pad;
3010                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3011                         amd64_padding (code, pad);
3012                         cfg->code_len += pad;
3013                         bb->native_offset = cfg->code_len;
3014                 }
3015         }
3016
3017         if (cfg->verbose_level > 2)
3018                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3019
3020         cpos = bb->max_offset;
3021
3022         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3023                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3024                 g_assert (!cfg->compile_aot);
3025                 cpos += 6;
3026
3027                 cov->data [bb->dfn].cil_code = bb->cil_code;
3028                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3029                 /* this is not thread save, but good enough */
3030                 amd64_inc_membase (code, AMD64_R11, 0);
3031         }
3032
3033         offset = code - cfg->native_code;
3034
3035         mono_debug_open_block (cfg, bb, offset);
3036
3037     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3038                 x86_breakpoint (code);
3039
3040         MONO_BB_FOR_EACH_INS (bb, ins) {
3041                 offset = code - cfg->native_code;
3042
3043                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3044
3045                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3046                         cfg->code_size *= 2;
3047                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3048                         code = cfg->native_code + offset;
3049                         mono_jit_stats.code_reallocs++;
3050                 }
3051
3052                 if (cfg->debug_info)
3053                         mono_debug_record_line_number (cfg, ins, offset);
3054
3055                 switch (ins->opcode) {
3056                 case OP_BIGMUL:
3057                         amd64_mul_reg (code, ins->sreg2, TRUE);
3058                         break;
3059                 case OP_BIGMUL_UN:
3060                         amd64_mul_reg (code, ins->sreg2, FALSE);
3061                         break;
3062                 case OP_X86_SETEQ_MEMBASE:
3063                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3064                         break;
3065                 case OP_STOREI1_MEMBASE_IMM:
3066                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3067                         break;
3068                 case OP_STOREI2_MEMBASE_IMM:
3069                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3070                         break;
3071                 case OP_STOREI4_MEMBASE_IMM:
3072                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3073                         break;
3074                 case OP_STOREI1_MEMBASE_REG:
3075                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3076                         break;
3077                 case OP_STOREI2_MEMBASE_REG:
3078                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3079                         break;
3080                 case OP_STORE_MEMBASE_REG:
3081                 case OP_STOREI8_MEMBASE_REG:
3082                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3083                         break;
3084                 case OP_STOREI4_MEMBASE_REG:
3085                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3086                         break;
3087                 case OP_STORE_MEMBASE_IMM:
3088                 case OP_STOREI8_MEMBASE_IMM:
3089                         g_assert (amd64_is_imm32 (ins->inst_imm));
3090                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3091                         break;
3092                 case OP_LOAD_MEM:
3093                 case OP_LOADI8_MEM:
3094                         // FIXME: Decompose this earlier
3095                         if (amd64_is_imm32 (ins->inst_imm))
3096                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3097                         else {
3098                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3099                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3100                         }
3101                         break;
3102                 case OP_LOADI4_MEM:
3103                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3104                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3105                         break;
3106                 case OP_LOADU4_MEM:
3107                         // FIXME: Decompose this earlier
3108                         if (cfg->new_ir) {
3109                                 if (amd64_is_imm32 (ins->inst_imm))
3110                                         amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3111                                 else {
3112                                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3113                                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3114                                 }
3115                         } else {
3116                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
3117                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3118                         }
3119                         break;
3120                 case OP_LOADU1_MEM:
3121                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3122                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3123                         break;
3124                 case OP_LOADU2_MEM:
3125                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3126                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3127                         break;
3128                 case OP_LOAD_MEMBASE:
3129                 case OP_LOADI8_MEMBASE:
3130                         g_assert (amd64_is_imm32 (ins->inst_offset));
3131                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3132                         break;
3133                 case OP_LOADI4_MEMBASE:
3134                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3135                         break;
3136                 case OP_LOADU4_MEMBASE:
3137                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3138                         break;
3139                 case OP_LOADU1_MEMBASE:
3140                         /* The cpu zero extends the result into 64 bits */
3141                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3142                         break;
3143                 case OP_LOADI1_MEMBASE:
3144                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3145                         break;
3146                 case OP_LOADU2_MEMBASE:
3147                         /* The cpu zero extends the result into 64 bits */
3148                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3149                         break;
3150                 case OP_LOADI2_MEMBASE:
3151                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3152                         break;
3153                 case OP_AMD64_LOADI8_MEMINDEX:
3154                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3155                         break;
3156                 case OP_LCONV_TO_I1:
3157                 case OP_ICONV_TO_I1:
3158                 case OP_SEXT_I1:
3159                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3160                         break;
3161                 case OP_LCONV_TO_I2:
3162                 case OP_ICONV_TO_I2:
3163                 case OP_SEXT_I2:
3164                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3165                         break;
3166                 case OP_LCONV_TO_U1:
3167                 case OP_ICONV_TO_U1:
3168                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3169                         break;
3170                 case OP_LCONV_TO_U2:
3171                 case OP_ICONV_TO_U2:
3172                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3173                         break;
3174                 case OP_ZEXT_I4:
3175                         /* Clean out the upper word */
3176                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3177                         break;
3178                 case OP_SEXT_I4:
3179                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3180                         break;
3181                 case OP_COMPARE:
3182                 case OP_LCOMPARE:
3183                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3184                         break;
3185                 case OP_COMPARE_IMM:
3186                 case OP_LCOMPARE_IMM:
3187                         g_assert (amd64_is_imm32 (ins->inst_imm));
3188                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3189                         break;
3190                 case OP_X86_COMPARE_REG_MEMBASE:
3191                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3192                         break;
3193                 case OP_X86_TEST_NULL:
3194                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3195                         break;
3196                 case OP_AMD64_TEST_NULL:
3197                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3198                         break;
3199
3200                 case OP_X86_ADD_REG_MEMBASE:
3201                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3202                         break;
3203                 case OP_X86_SUB_REG_MEMBASE:
3204                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3205                         break;
3206                 case OP_X86_AND_REG_MEMBASE:
3207                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3208                         break;
3209                 case OP_X86_OR_REG_MEMBASE:
3210                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3211                         break;
3212                 case OP_X86_XOR_REG_MEMBASE:
3213                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3214                         break;
3215
3216                 case OP_X86_ADD_MEMBASE_IMM:
3217                         /* FIXME: Make a 64 version too */
3218                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3219                         break;
3220                 case OP_X86_SUB_MEMBASE_IMM:
3221                         g_assert (amd64_is_imm32 (ins->inst_imm));
3222                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3223                         break;
3224                 case OP_X86_AND_MEMBASE_IMM:
3225                         g_assert (amd64_is_imm32 (ins->inst_imm));
3226                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3227                         break;
3228                 case OP_X86_OR_MEMBASE_IMM:
3229                         g_assert (amd64_is_imm32 (ins->inst_imm));
3230                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3231                         break;
3232                 case OP_X86_XOR_MEMBASE_IMM:
3233                         g_assert (amd64_is_imm32 (ins->inst_imm));
3234                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3235                         break;
3236                 case OP_X86_ADD_MEMBASE_REG:
3237                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3238                         break;
3239                 case OP_X86_SUB_MEMBASE_REG:
3240                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3241                         break;
3242                 case OP_X86_AND_MEMBASE_REG:
3243                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3244                         break;
3245                 case OP_X86_OR_MEMBASE_REG:
3246                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3247                         break;
3248                 case OP_X86_XOR_MEMBASE_REG:
3249                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3250                         break;
3251                 case OP_X86_INC_MEMBASE:
3252                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3253                         break;
3254                 case OP_X86_INC_REG:
3255                         amd64_inc_reg_size (code, ins->dreg, 4);
3256                         break;
3257                 case OP_X86_DEC_MEMBASE:
3258                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3259                         break;
3260                 case OP_X86_DEC_REG:
3261                         amd64_dec_reg_size (code, ins->dreg, 4);
3262                         break;
3263                 case OP_X86_MUL_REG_MEMBASE:
3264                 case OP_X86_MUL_MEMBASE_REG:
3265                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3266                         break;
3267                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3268                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3269                         break;
3270                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3271                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3272                         break;
3273                 case OP_AMD64_COMPARE_MEMBASE_REG:
3274                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3275                         break;
3276                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3277                         g_assert (amd64_is_imm32 (ins->inst_imm));
3278                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3279                         break;
3280                 case OP_X86_COMPARE_MEMBASE8_IMM:
3281                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3282                         break;
3283                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3284                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3285                         break;
3286                 case OP_AMD64_COMPARE_REG_MEMBASE:
3287                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3288                         break;
3289
3290                 case OP_AMD64_ADD_REG_MEMBASE:
3291                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3292                         break;
3293                 case OP_AMD64_SUB_REG_MEMBASE:
3294                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3295                         break;
3296                 case OP_AMD64_AND_REG_MEMBASE:
3297                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3298                         break;
3299                 case OP_AMD64_OR_REG_MEMBASE:
3300                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3301                         break;
3302                 case OP_AMD64_XOR_REG_MEMBASE:
3303                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3304                         break;
3305
3306                 case OP_AMD64_ADD_MEMBASE_REG:
3307                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3308                         break;
3309                 case OP_AMD64_SUB_MEMBASE_REG:
3310                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3311                         break;
3312                 case OP_AMD64_AND_MEMBASE_REG:
3313                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3314                         break;
3315                 case OP_AMD64_OR_MEMBASE_REG:
3316                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3317                         break;
3318                 case OP_AMD64_XOR_MEMBASE_REG:
3319                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3320                         break;
3321
3322                 case OP_AMD64_ADD_MEMBASE_IMM:
3323                         g_assert (amd64_is_imm32 (ins->inst_imm));
3324                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3325                         break;
3326                 case OP_AMD64_SUB_MEMBASE_IMM:
3327                         g_assert (amd64_is_imm32 (ins->inst_imm));
3328                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3329                         break;
3330                 case OP_AMD64_AND_MEMBASE_IMM:
3331                         g_assert (amd64_is_imm32 (ins->inst_imm));
3332                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3333                         break;
3334                 case OP_AMD64_OR_MEMBASE_IMM:
3335                         g_assert (amd64_is_imm32 (ins->inst_imm));
3336                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3337                         break;
3338                 case OP_AMD64_XOR_MEMBASE_IMM:
3339                         g_assert (amd64_is_imm32 (ins->inst_imm));
3340                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3341                         break;
3342
3343                 case OP_BREAK:
3344                         amd64_breakpoint (code);
3345                         break;
3346                 case OP_RELAXED_NOP:
3347                         x86_prefix (code, X86_REP_PREFIX);
3348                         x86_nop (code);
3349                         break;
3350                 case OP_NOP:
3351                 case OP_DUMMY_USE:
3352                 case OP_DUMMY_STORE:
3353                 case OP_NOT_REACHED:
3354                 case OP_NOT_NULL:
3355                         break;
3356                 case OP_ADDCC:
3357                 case OP_LADD:
3358                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3359                         break;
3360                 case OP_ADC:
3361                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3362                         break;
3363                 case OP_ADD_IMM:
3364                 case OP_LADD_IMM:
3365                         g_assert (amd64_is_imm32 (ins->inst_imm));
3366                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3367                         break;
3368                 case OP_ADC_IMM:
3369                         g_assert (amd64_is_imm32 (ins->inst_imm));
3370                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3371                         break;
3372                 case OP_SUBCC:
3373                 case OP_LSUB:
3374                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3375                         break;
3376                 case OP_SBB:
3377                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3378                         break;
3379                 case OP_SUB_IMM:
3380                 case OP_LSUB_IMM:
3381                         g_assert (amd64_is_imm32 (ins->inst_imm));
3382                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3383                         break;
3384                 case OP_SBB_IMM:
3385                         g_assert (amd64_is_imm32 (ins->inst_imm));
3386                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3387                         break;
3388                 case OP_LAND:
3389                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3390                         break;
3391                 case OP_AND_IMM:
3392                 case OP_LAND_IMM:
3393                         g_assert (amd64_is_imm32 (ins->inst_imm));
3394                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3395                         break;
3396                 case OP_LMUL:
3397                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3398                         break;
3399                 case OP_MUL_IMM:
3400                 case OP_LMUL_IMM:
3401                 case OP_IMUL_IMM: {
3402                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3403
3404                         switch (ins->inst_imm) {
3405                         case 2:
3406                                 /* MOV r1, r2 */
3407                                 /* ADD r1, r1 */
3408                                 if (ins->dreg != ins->sreg1)
3409                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3410                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3411                                 break;
3412                         case 3:
3413                                 /* LEA r1, [r2 + r2*2] */
3414                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3415                                 break;
3416                         case 5:
3417                                 /* LEA r1, [r2 + r2*4] */
3418                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3419                                 break;
3420                         case 6:
3421                                 /* LEA r1, [r2 + r2*2] */
3422                                 /* ADD r1, r1          */
3423                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3424                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3425                                 break;
3426                         case 9:
3427                                 /* LEA r1, [r2 + r2*8] */
3428                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3429                                 break;
3430                         case 10:
3431                                 /* LEA r1, [r2 + r2*4] */
3432                                 /* ADD r1, r1          */
3433                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3434                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3435                                 break;
3436                         case 12:
3437                                 /* LEA r1, [r2 + r2*2] */
3438                                 /* SHL r1, 2           */
3439                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3440                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3441                                 break;
3442                         case 25:
3443                                 /* LEA r1, [r2 + r2*4] */
3444                                 /* LEA r1, [r1 + r1*4] */
3445                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3446                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3447                                 break;
3448                         case 100:
3449                                 /* LEA r1, [r2 + r2*4] */
3450                                 /* SHL r1, 2           */
3451                                 /* LEA r1, [r1 + r1*4] */
3452                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3453                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3454                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3455                                 break;
3456                         default:
3457                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3458                                 break;
3459                         }
3460                         break;
3461                 }
3462                 case OP_LDIV:
3463                 case OP_LREM:
3464                         /* Regalloc magic makes the div/rem cases the same */
3465                         if (ins->sreg2 == AMD64_RDX) {
3466                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3467                                 amd64_cdq (code);
3468                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3469                         } else {
3470                                 amd64_cdq (code);
3471                                 amd64_div_reg (code, ins->sreg2, TRUE);
3472                         }
3473                         break;
3474                 case OP_LDIV_UN:
3475                 case OP_LREM_UN:
3476                         if (ins->sreg2 == AMD64_RDX) {
3477                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3478                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3479                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3480                         } else {
3481                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3482                                 amd64_div_reg (code, ins->sreg2, FALSE);
3483                         }
3484                         break;
3485                 case OP_IDIV:
3486                 case OP_IREM:
3487                         if (ins->sreg2 == AMD64_RDX) {
3488                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3489                                 amd64_cdq_size (code, 4);
3490                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3491                         } else {
3492                                 amd64_cdq_size (code, 4);
3493                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3494                         }
3495                         break;
3496                 case OP_IDIV_UN:
3497                 case OP_IREM_UN:
3498                         if (ins->sreg2 == AMD64_RDX) {
3499                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3500                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3501                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3502                         } else {
3503                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3504                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3505                         }
3506                         break;
3507                 case OP_LMUL_OVF:
3508                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3509                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3510                         break;
3511                 case OP_LOR:
3512                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3513                         break;
3514                 case OP_OR_IMM:
3515                 case OP_LOR_IMM:
3516                         g_assert (amd64_is_imm32 (ins->inst_imm));
3517                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3518                         break;
3519                 case OP_LXOR:
3520                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3521                         break;
3522                 case OP_XOR_IMM:
3523                 case OP_LXOR_IMM:
3524                         g_assert (amd64_is_imm32 (ins->inst_imm));
3525                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3526                         break;
3527                 case OP_LSHL:
3528                         g_assert (ins->sreg2 == AMD64_RCX);
3529                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3530                         break;
3531                 case OP_LSHR:
3532                         g_assert (ins->sreg2 == AMD64_RCX);
3533                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3534                         break;
3535                 case OP_SHR_IMM:
3536                         g_assert (amd64_is_imm32 (ins->inst_imm));
3537                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3538                         break;
3539                 case OP_LSHR_IMM:
3540                         g_assert (amd64_is_imm32 (ins->inst_imm));
3541                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3542                         break;
3543                 case OP_SHR_UN_IMM:
3544                         g_assert (amd64_is_imm32 (ins->inst_imm));
3545                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3546                         break;
3547                 case OP_LSHR_UN_IMM:
3548                         g_assert (amd64_is_imm32 (ins->inst_imm));
3549                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3550                         break;
3551                 case OP_LSHR_UN:
3552                         g_assert (ins->sreg2 == AMD64_RCX);
3553                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3554                         break;
3555                 case OP_SHL_IMM:
3556                         g_assert (amd64_is_imm32 (ins->inst_imm));
3557                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3558                         break;
3559                 case OP_LSHL_IMM:
3560                         g_assert (amd64_is_imm32 (ins->inst_imm));
3561                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3562                         break;
3563
3564                 case OP_IADDCC:
3565                 case OP_IADD:
3566                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3567                         break;
3568                 case OP_IADC:
3569                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3570                         break;
3571                 case OP_IADD_IMM:
3572                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3573                         break;
3574                 case OP_IADC_IMM:
3575                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3576                         break;
3577                 case OP_ISUBCC:
3578                 case OP_ISUB:
3579                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3580                         break;
3581                 case OP_ISBB:
3582                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3583                         break;
3584                 case OP_ISUB_IMM:
3585                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3586                         break;
3587                 case OP_ISBB_IMM:
3588                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3589                         break;
3590                 case OP_IAND:
3591                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3592                         break;
3593                 case OP_IAND_IMM:
3594                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3595                         break;
3596                 case OP_IOR:
3597                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3598                         break;
3599                 case OP_IOR_IMM:
3600                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3601                         break;
3602                 case OP_IXOR:
3603                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3604                         break;
3605                 case OP_IXOR_IMM:
3606                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3607                         break;
3608                 case OP_INEG:
3609                         amd64_neg_reg_size (code, ins->sreg1, 4);
3610                         break;
3611                 case OP_INOT:
3612                         amd64_not_reg_size (code, ins->sreg1, 4);
3613                         break;
3614                 case OP_ISHL:
3615                         g_assert (ins->sreg2 == AMD64_RCX);
3616                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3617                         break;
3618                 case OP_ISHR:
3619                         g_assert (ins->sreg2 == AMD64_RCX);
3620                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3621                         break;
3622                 case OP_ISHR_IMM:
3623                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3624                         break;
3625                 case OP_ISHR_UN_IMM:
3626                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3627                         break;
3628                 case OP_ISHR_UN:
3629                         g_assert (ins->sreg2 == AMD64_RCX);
3630                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3631                         break;
3632                 case OP_ISHL_IMM:
3633                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3634                         break;
3635                 case OP_IMUL:
3636                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3637                         break;
3638                 case OP_IMUL_OVF:
3639                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3640                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3641                         break;
3642                 case OP_IMUL_OVF_UN:
3643                 case OP_LMUL_OVF_UN: {
3644                         /* the mul operation and the exception check should most likely be split */
3645                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3646                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3647                         /*g_assert (ins->sreg2 == X86_EAX);
3648                         g_assert (ins->dreg == X86_EAX);*/
3649                         if (ins->sreg2 == X86_EAX) {
3650                                 non_eax_reg = ins->sreg1;
3651                         } else if (ins->sreg1 == X86_EAX) {
3652                                 non_eax_reg = ins->sreg2;
3653                         } else {
3654                                 /* no need to save since we're going to store to it anyway */
3655                                 if (ins->dreg != X86_EAX) {
3656                                         saved_eax = TRUE;
3657                                         amd64_push_reg (code, X86_EAX);
3658                                 }
3659                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3660                                 non_eax_reg = ins->sreg2;
3661                         }
3662                         if (ins->dreg == X86_EDX) {
3663                                 if (!saved_eax) {
3664                                         saved_eax = TRUE;
3665                                         amd64_push_reg (code, X86_EAX);
3666                                 }
3667                         } else {
3668                                 saved_edx = TRUE;
3669                                 amd64_push_reg (code, X86_EDX);
3670                         }
3671                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3672                         /* save before the check since pop and mov don't change the flags */
3673                         if (ins->dreg != X86_EAX)
3674                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3675                         if (saved_edx)
3676                                 amd64_pop_reg (code, X86_EDX);
3677                         if (saved_eax)
3678                                 amd64_pop_reg (code, X86_EAX);
3679                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3680                         break;
3681                 }
3682                 case OP_ICOMPARE:
3683                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3684                         break;
3685                 case OP_ICOMPARE_IMM:
3686                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3687                         break;
3688                 case OP_IBEQ:
3689                 case OP_IBLT:
3690                 case OP_IBGT:
3691                 case OP_IBGE:
3692                 case OP_IBLE:
3693                 case OP_LBEQ:
3694                 case OP_LBLT:
3695                 case OP_LBGT:
3696                 case OP_LBGE:
3697                 case OP_LBLE:
3698                 case OP_IBNE_UN:
3699                 case OP_IBLT_UN:
3700                 case OP_IBGT_UN:
3701                 case OP_IBGE_UN:
3702                 case OP_IBLE_UN:
3703                 case OP_LBNE_UN:
3704                 case OP_LBLT_UN:
3705                 case OP_LBGT_UN:
3706                 case OP_LBGE_UN:
3707                 case OP_LBLE_UN:
3708                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3709                         break;
3710
3711                 case OP_CMOV_IEQ:
3712                 case OP_CMOV_IGE:
3713                 case OP_CMOV_IGT:
3714                 case OP_CMOV_ILE:
3715                 case OP_CMOV_ILT:
3716                 case OP_CMOV_INE_UN:
3717                 case OP_CMOV_IGE_UN:
3718                 case OP_CMOV_IGT_UN:
3719                 case OP_CMOV_ILE_UN:
3720                 case OP_CMOV_ILT_UN:
3721                 case OP_CMOV_LEQ:
3722                 case OP_CMOV_LGE:
3723                 case OP_CMOV_LGT:
3724                 case OP_CMOV_LLE:
3725                 case OP_CMOV_LLT:
3726                 case OP_CMOV_LNE_UN:
3727                 case OP_CMOV_LGE_UN:
3728                 case OP_CMOV_LGT_UN:
3729                 case OP_CMOV_LLE_UN:
3730                 case OP_CMOV_LLT_UN:
3731                         g_assert (ins->dreg == ins->sreg1);
3732                         /* This needs to operate on 64 bit values */
3733                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3734                         break;
3735
3736                 case OP_LNOT:
3737                         amd64_not_reg (code, ins->sreg1);
3738                         break;
3739                 case OP_LNEG:
3740                         amd64_neg_reg (code, ins->sreg1);
3741                         break;
3742
3743                 case OP_ICONST:
3744                 case OP_I8CONST:
3745                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3746                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3747                         else
3748                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3749                         break;
3750                 case OP_AOTCONST:
3751                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3752                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3753                         break;
3754                 case OP_JUMP_TABLE:
3755                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3756                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3757                         break;
3758                 case OP_MOVE:
3759                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3760                         break;
3761                 case OP_AMD64_SET_XMMREG_R4: {
3762                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3763                         break;
3764                 }
3765                 case OP_AMD64_SET_XMMREG_R8: {
3766                         if (ins->dreg != ins->sreg1)
3767                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3768                         break;
3769                 }
3770                 case OP_JMP:
3771                 case OP_TAILCALL: {
3772                         /*
3773                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3774                          * Keep in sync with the code in emit_epilog.
3775                          */
3776                         int pos = 0, i;
3777
3778                         /* FIXME: no tracing support... */
3779                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3780                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3781
3782                         g_assert (!cfg->method->save_lmf);
3783
3784                         if (ins->opcode == OP_JMP)
3785                                 code = emit_load_volatile_arguments (cfg, code);
3786
3787                         if (cfg->arch.omit_fp) {
3788                                 guint32 save_offset = 0;
3789                                 /* Pop callee-saved registers */
3790                                 for (i = 0; i < AMD64_NREG; ++i)
3791                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3792                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3793                                                 save_offset += 8;
3794                                         }
3795                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3796                         }
3797                         else {
3798                                 for (i = 0; i < AMD64_NREG; ++i)
3799                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3800                                                 pos -= sizeof (gpointer);
3801
3802                                 if (pos)
3803                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3804
3805                                 /* Pop registers in reverse order */
3806                                 for (i = AMD64_NREG - 1; i > 0; --i)
3807                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3808                                                 amd64_pop_reg (code, i);
3809                                         }
3810
3811                                 amd64_leave (code);
3812                         }
3813
3814                         offset = code - cfg->native_code;
3815                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3816                         if (cfg->compile_aot)
3817                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3818                         else
3819                                 amd64_set_reg_template (code, AMD64_R11);
3820                         amd64_jump_reg (code, AMD64_R11);
3821                         break;
3822                 }
3823                 case OP_CHECK_THIS:
3824                         /* ensure ins->sreg1 is not NULL */
3825                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3826                         break;
3827                 case OP_ARGLIST: {
3828                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3829                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3830                         break;
3831                 }
3832                 case OP_CALL:
3833                 case OP_FCALL:
3834                 case OP_LCALL:
3835                 case OP_VCALL:
3836                 case OP_VCALL2:
3837                 case OP_VOIDCALL:
3838                         call = (MonoCallInst*)ins;
3839                         /*
3840                          * The AMD64 ABI forces callers to know about varargs.
3841                          */
3842                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3843                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3844                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3845                                 /*
3846                                  * Since the unmanaged calling convention doesn't contain a
3847                                  * 'vararg' entry, we have to treat every pinvoke call as a
3848                                  * potential vararg call.
3849                                  */
3850                                 guint32 nregs, i;
3851                                 nregs = 0;
3852                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3853                                         if (call->used_fregs & (1 << i))
3854                                                 nregs ++;
3855                                 if (!nregs)
3856                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3857                                 else
3858                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3859                         }
3860
3861                         if (ins->flags & MONO_INST_HAS_METHOD)
3862                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3863                         else
3864                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3865                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3866                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3867                         code = emit_move_return_value (cfg, ins, code);
3868                         break;
3869                 case OP_FCALL_REG:
3870                 case OP_LCALL_REG:
3871                 case OP_VCALL_REG:
3872                 case OP_VCALL2_REG:
3873                 case OP_VOIDCALL_REG:
3874                 case OP_CALL_REG:
3875                         call = (MonoCallInst*)ins;
3876
3877                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3878                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3879                                 ins->sreg1 = AMD64_R11;
3880                         }
3881
3882                         /*
3883                          * The AMD64 ABI forces callers to know about varargs.
3884                          */
3885                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3886                                 if (ins->sreg1 == AMD64_RAX) {
3887                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3888                                         ins->sreg1 = AMD64_R11;
3889                                 }
3890                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3891                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3892                                 /*
3893                                  * Since the unmanaged calling convention doesn't contain a
3894                                  * 'vararg' entry, we have to treat every pinvoke call as a
3895                                  * potential vararg call.
3896                                  */
3897                                 guint32 nregs, i;
3898                                 nregs = 0;
3899                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3900                                         if (call->used_fregs & (1 << i))
3901                                                 nregs ++;
3902                                 if (ins->sreg1 == AMD64_RAX) {
3903                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3904                                         ins->sreg1 = AMD64_R11;
3905                                 }
3906                                 if (!nregs)
3907                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3908                                 else
3909                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3910                         }
3911
3912                         amd64_call_reg (code, ins->sreg1);
3913                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3914                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3915                         code = emit_move_return_value (cfg, ins, code);
3916                         break;
3917                 case OP_FCALL_MEMBASE:
3918                 case OP_LCALL_MEMBASE:
3919                 case OP_VCALL_MEMBASE:
3920                 case OP_VCALL2_MEMBASE:
3921                 case OP_VOIDCALL_MEMBASE:
3922                 case OP_CALL_MEMBASE:
3923                         call = (MonoCallInst*)ins;
3924
3925                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3926                                 /*
3927                                  * Can't use R11 because it is clobbered by the trampoline
3928                                  * code, and the reg value is needed by get_vcall_slot_addr.
3929                                  */
3930                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3931                                 ins->sreg1 = AMD64_RAX;
3932                         }
3933
3934                         if (call->method && ins->inst_offset < 0) {
3935                                 gssize val;
3936
3937                                 /*
3938                                  * This is a possible IMT call so save the IMT method in the proper
3939                                  * register. We don't use the generic code in method-to-ir.c, because
3940                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3941                                  * maintain control over the layout of the code.
3942                                  * Also put the base reg in %rax to simplify find_imt_method ().
3943                                  */
3944                                 if (ins->sreg1 != AMD64_RAX) {
3945                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3946                                         ins->sreg1 = AMD64_RAX;
3947                                 }
3948                                 val = (gssize)(gpointer)call->method;
3949
3950                                 // FIXME: Generics sharing
3951 #if 0
3952                                 if ((((guint64)val) >> 32) == 0)
3953                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3954                                 else
3955                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3956 #endif
3957                         }
3958
3959                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3960                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3961                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3962                         code = emit_move_return_value (cfg, ins, code);
3963                         break;
3964                 case OP_AMD64_SAVE_SP_TO_LMF:
3965                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3966                         break;
3967                 case OP_OUTARG:
3968                 case OP_X86_PUSH:
3969                         amd64_push_reg (code, ins->sreg1);
3970                         break;
3971                 case OP_X86_PUSH_IMM:
3972                         g_assert (amd64_is_imm32 (ins->inst_imm));
3973                         amd64_push_imm (code, ins->inst_imm);
3974                         break;
3975                 case OP_X86_PUSH_MEMBASE:
3976                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3977                         break;
3978                 case OP_X86_PUSH_OBJ: {
3979                         int size = ALIGN_TO (ins->inst_imm, 8);
3980                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3981                         amd64_push_reg (code, AMD64_RDI);
3982                         amd64_push_reg (code, AMD64_RSI);
3983                         amd64_push_reg (code, AMD64_RCX);
3984                         if (ins->inst_offset)
3985                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3986                         else
3987                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3988                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8) + (size - ins->inst_imm));
3989                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3990                         amd64_cld (code);
3991                         amd64_prefix (code, X86_REP_PREFIX);
3992                         amd64_movsd (code);
3993                         amd64_pop_reg (code, AMD64_RCX);
3994                         amd64_pop_reg (code, AMD64_RSI);
3995                         amd64_pop_reg (code, AMD64_RDI);
3996                         break;
3997                 }
3998                 case OP_X86_LEA:
3999                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4000                         break;
4001                 case OP_X86_LEA_MEMBASE:
4002                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4003                         break;
4004                 case OP_X86_XCHG:
4005                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4006                         break;
4007                 case OP_LOCALLOC:
4008                         /* keep alignment */
4009                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4010                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4011                         code = mono_emit_stack_alloc (code, ins);
4012                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4013                         break;
4014                 case OP_LOCALLOC_IMM: {
4015                         guint32 size = ins->inst_imm;
4016                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4017
4018                         if (ins->flags & MONO_INST_INIT) {
4019                                 if (size < 64) {
4020                                         int i;
4021
4022                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4023                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4024
4025                                         for (i = 0; i < size; i += 8)
4026                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4027                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4028                                 } else {
4029                                         amd64_mov_reg_imm (code, ins->dreg, size);
4030                                         ins->sreg1 = ins->dreg;
4031
4032                                         code = mono_emit_stack_alloc (code, ins);
4033                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4034                                 }
4035                         } else {
4036                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4037                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4038                         }
4039                         break;
4040                 }
4041                 case OP_THROW: {
4042                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4043                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4044                                              (gpointer)"mono_arch_throw_exception", FALSE);
4045                         break;
4046                 }
4047                 case OP_RETHROW: {
4048                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4049                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4050                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4051                         break;
4052                 }
4053                 case OP_CALL_HANDLER:
4054                         /* Align stack */
4055                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4056                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4057                         amd64_call_imm (code, 0);
4058                         /* Restore stack alignment */
4059                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4060                         break;
4061                 case OP_START_HANDLER: {
4062                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4063                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4064                         break;
4065                 }
4066                 case OP_ENDFINALLY: {
4067                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4068                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4069                         amd64_ret (code);
4070                         break;
4071                 }
4072                 case OP_ENDFILTER: {
4073                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4074                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4075                         /* The local allocator will put the result into RAX */
4076                         amd64_ret (code);
4077                         break;
4078                 }
4079
4080                 case OP_LABEL:
4081                         ins->inst_c0 = code - cfg->native_code;
4082                         break;
4083                 case OP_BR:
4084                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4085                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4086                         //break;
4087                         if (ins->flags & MONO_INST_BRLABEL) {
4088                                 if (ins->inst_i0->inst_c0) {
4089                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
4090                                 } else {
4091                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
4092                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4093                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
4094                                                 x86_jump8 (code, 0);
4095                                         else
4096                                                 x86_jump32 (code, 0);
4097                                 }
4098                         } else {
4099                                 if (ins->inst_target_bb->native_offset) {
4100                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4101                                 } else {
4102                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4103                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4104                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
4105                                                 x86_jump8 (code, 0);
4106                                         else
4107                                                 x86_jump32 (code, 0);
4108                                 }
4109                         }
4110                         break;
4111                 case OP_BR_REG:
4112                         amd64_jump_reg (code, ins->sreg1);
4113                         break;
4114                 case OP_CEQ:
4115                 case OP_LCEQ:
4116                 case OP_ICEQ:
4117                 case OP_CLT:
4118                 case OP_LCLT:
4119                 case OP_ICLT:
4120                 case OP_CGT:
4121                 case OP_ICGT:
4122                 case OP_LCGT:
4123                 case OP_CLT_UN:
4124                 case OP_LCLT_UN:
4125                 case OP_ICLT_UN:
4126                 case OP_CGT_UN:
4127                 case OP_LCGT_UN:
4128                 case OP_ICGT_UN:
4129                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4130                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4131                         break;
4132                 case OP_COND_EXC_EQ:
4133                 case OP_COND_EXC_NE_UN:
4134                 case OP_COND_EXC_LT:
4135                 case OP_COND_EXC_LT_UN:
4136                 case OP_COND_EXC_GT:
4137                 case OP_COND_EXC_GT_UN:
4138                 case OP_COND_EXC_GE:
4139                 case OP_COND_EXC_GE_UN:
4140                 case OP_COND_EXC_LE:
4141                 case OP_COND_EXC_LE_UN:
4142                 case OP_COND_EXC_IEQ:
4143                 case OP_COND_EXC_INE_UN:
4144                 case OP_COND_EXC_ILT:
4145                 case OP_COND_EXC_ILT_UN:
4146                 case OP_COND_EXC_IGT:
4147                 case OP_COND_EXC_IGT_UN:
4148                 case OP_COND_EXC_IGE:
4149                 case OP_COND_EXC_IGE_UN:
4150                 case OP_COND_EXC_ILE:
4151                 case OP_COND_EXC_ILE_UN:
4152                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4153                         break;
4154                 case OP_COND_EXC_OV:
4155                 case OP_COND_EXC_NO:
4156                 case OP_COND_EXC_C:
4157                 case OP_COND_EXC_NC:
4158                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4159                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4160                         break;
4161                 case OP_COND_EXC_IOV:
4162                 case OP_COND_EXC_INO:
4163                 case OP_COND_EXC_IC:
4164                 case OP_COND_EXC_INC:
4165                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4166                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4167                         break;
4168
4169                 /* floating point opcodes */
4170                 case OP_R8CONST: {
4171                         double d = *(double *)ins->inst_p0;
4172
4173                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4174                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4175                         }
4176                         else {
4177                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4178                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4179                         }
4180                         break;
4181                 }
4182                 case OP_R4CONST: {
4183                         float f = *(float *)ins->inst_p0;
4184
4185                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4186                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4187                         }
4188                         else {
4189                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4190                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4191                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4192                         }
4193                         break;
4194                 }
4195                 case OP_STORER8_MEMBASE_REG:
4196                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4197                         break;
4198                 case OP_LOADR8_SPILL_MEMBASE:
4199                         g_assert_not_reached ();
4200                         break;
4201                 case OP_LOADR8_MEMBASE:
4202                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4203                         break;
4204                 case OP_STORER4_MEMBASE_REG:
4205                         /* This requires a double->single conversion */
4206                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4207                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4208                         break;
4209                 case OP_LOADR4_MEMBASE:
4210                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4211                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4212                         break;
4213                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4214                 case OP_ICONV_TO_R8:
4215                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4216                         break;
4217                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4218                 case OP_LCONV_TO_R8:
4219                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4220                         break;
4221                 case OP_FCONV_TO_R4:
4222                         /* FIXME: nothing to do ?? */
4223                         break;
4224                 case OP_FCONV_TO_I1:
4225                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4226                         break;
4227                 case OP_FCONV_TO_U1:
4228                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4229                         break;
4230                 case OP_FCONV_TO_I2:
4231                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4232                         break;
4233                 case OP_FCONV_TO_U2:
4234                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4235                         break;
4236                 case OP_FCONV_TO_U4:
4237                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4238                         break;
4239                 case OP_FCONV_TO_I4:
4240                 case OP_FCONV_TO_I:
4241                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4242                         break;
4243                 case OP_FCONV_TO_I8:
4244                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4245                         break;
4246                 case OP_LCONV_TO_R_UN: {
4247                         guint8 *br [2];
4248
4249                         /* Based on gcc code */
4250                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4251                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4252
4253                         /* Positive case */
4254                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4255                         br [1] = code; x86_jump8 (code, 0);
4256                         amd64_patch (br [0], code);
4257
4258                         /* Negative case */
4259                         /* Save to the red zone */
4260                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4261                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4262                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4263                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4264                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4265                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4266                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4267                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4268                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4269                         /* Restore */
4270                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4271                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4272                         amd64_patch (br [1], code);
4273                         break;
4274                 }
4275                 case OP_LCONV_TO_OVF_U4:
4276                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4277                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4278                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4279                         break;
4280                 case OP_LCONV_TO_OVF_I4_UN:
4281                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4282                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4283                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4284                         break;
4285                 case OP_FMOVE:
4286                         if (ins->dreg != ins->sreg1)
4287                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4288                         break;
4289                 case OP_FADD:
4290                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4291                         break;
4292                 case OP_FSUB:
4293                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4294                         break;
4295                 case OP_FMUL:
4296                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4297                         break;
4298                 case OP_FDIV:
4299                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4300                         break;
4301                 case OP_FNEG: {
4302                         static double r8_0 = -0.0;
4303
4304                         g_assert (ins->sreg1 == ins->dreg);
4305
4306                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4307                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4308                         break;
4309                 }
4310                 case OP_SIN:
4311                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4312                         break;
4313                 case OP_COS:
4314                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4315                         break;
4316                 case OP_ABS: {
4317                         static guint64 d = 0x7fffffffffffffffUL;
4318
4319                         g_assert (ins->sreg1 == ins->dreg);
4320
4321                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4322                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4323                         break;
4324                 }
4325                 case OP_SQRT:
4326                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4327                         break;
4328                 case OP_IMIN:
4329                         g_assert (cfg->opt & MONO_OPT_CMOV);
4330                         g_assert (ins->dreg == ins->sreg1);
4331                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4332                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4333                         break;
4334                 case OP_IMIN_UN:
4335                         g_assert (cfg->opt & MONO_OPT_CMOV);
4336                         g_assert (ins->dreg == ins->sreg1);
4337                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4338                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4339                         break;
4340                 case OP_IMAX:
4341                         g_assert (cfg->opt & MONO_OPT_CMOV);
4342                         g_assert (ins->dreg == ins->sreg1);
4343                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4344                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4345                         break;
4346                 case OP_IMAX_UN:
4347                         g_assert (cfg->opt & MONO_OPT_CMOV);
4348                         g_assert (ins->dreg == ins->sreg1);
4349                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4350                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4351                         break;
4352                 case OP_LMIN:
4353                         g_assert (cfg->opt & MONO_OPT_CMOV);
4354                         g_assert (ins->dreg == ins->sreg1);
4355                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4356                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4357                         break;
4358                 case OP_LMIN_UN:
4359                         g_assert (cfg->opt & MONO_OPT_CMOV);
4360                         g_assert (ins->dreg == ins->sreg1);
4361                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4362                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4363                         break;
4364                 case OP_LMAX:
4365                         g_assert (cfg->opt & MONO_OPT_CMOV);
4366                         g_assert (ins->dreg == ins->sreg1);
4367                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4368                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4369                         break;
4370                 case OP_LMAX_UN:
4371                         g_assert (cfg->opt & MONO_OPT_CMOV);
4372                         g_assert (ins->dreg == ins->sreg1);
4373                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4374                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4375                         break;
4376                 case OP_X86_FPOP:
4377                         break;
4378                 case OP_FCOMPARE:
4379                         /*
4380                          * The two arguments are swapped because the fbranch instructions
4381                          * depend on this for the non-sse case to work.
4382                          */
4383                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4384                         break;
4385                 case OP_FCEQ: {
4386                         /* zeroing the register at the start results in
4387                          * shorter and faster code (we can also remove the widening op)
4388                          */
4389                         guchar *unordered_check;
4390                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4391                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4392                         unordered_check = code;
4393                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4394                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4395                         amd64_patch (unordered_check, code);
4396                         break;
4397                 }
4398                 case OP_FCLT:
4399                 case OP_FCLT_UN:
4400                         /* zeroing the register at the start results in
4401                          * shorter and faster code (we can also remove the widening op)
4402                          */
4403                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4404                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4405                         if (ins->opcode == OP_FCLT_UN) {
4406                                 guchar *unordered_check = code;
4407                                 guchar *jump_to_end;
4408                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4409                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4410                                 jump_to_end = code;
4411                                 x86_jump8 (code, 0);
4412                                 amd64_patch (unordered_check, code);
4413                                 amd64_inc_reg (code, ins->dreg);
4414                                 amd64_patch (jump_to_end, code);
4415                         } else {
4416                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4417                         }
4418                         break;
4419                 case OP_FCGT:
4420                 case OP_FCGT_UN: {
4421                         /* zeroing the register at the start results in
4422                          * shorter and faster code (we can also remove the widening op)
4423                          */
4424                         guchar *unordered_check;
4425                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4426                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4427                         if (ins->opcode == OP_FCGT) {
4428                                 unordered_check = code;
4429                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4430                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4431                                 amd64_patch (unordered_check, code);
4432                         } else {
4433                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4434                         }
4435                         break;
4436                 }
4437                 case OP_FCLT_MEMBASE:
4438                 case OP_FCGT_MEMBASE:
4439                 case OP_FCLT_UN_MEMBASE:
4440                 case OP_FCGT_UN_MEMBASE:
4441                 case OP_FCEQ_MEMBASE: {
4442                         guchar *unordered_check, *jump_to_end;
4443                         int x86_cond;
4444
4445                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4446                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4447
4448                         switch (ins->opcode) {
4449                         case OP_FCEQ_MEMBASE:
4450                                 x86_cond = X86_CC_EQ;
4451                                 break;
4452                         case OP_FCLT_MEMBASE:
4453                         case OP_FCLT_UN_MEMBASE:
4454                                 x86_cond = X86_CC_LT;
4455                                 break;
4456                         case OP_FCGT_MEMBASE:
4457                         case OP_FCGT_UN_MEMBASE:
4458                                 x86_cond = X86_CC_GT;
4459                                 break;
4460                         default:
4461                                 g_assert_not_reached ();
4462                         }
4463
4464                         unordered_check = code;
4465                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4466                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4467
4468                         switch (ins->opcode) {
4469                         case OP_FCEQ_MEMBASE:
4470                         case OP_FCLT_MEMBASE:
4471                         case OP_FCGT_MEMBASE:
4472                                 amd64_patch (unordered_check, code);
4473                                 break;
4474                         case OP_FCLT_UN_MEMBASE:
4475                         case OP_FCGT_UN_MEMBASE:
4476                                 jump_to_end = code;
4477                                 x86_jump8 (code, 0);
4478                                 amd64_patch (unordered_check, code);
4479                                 amd64_inc_reg (code, ins->dreg);
4480                                 amd64_patch (jump_to_end, code);
4481                                 break;
4482                         default:
4483                                 break;
4484                         }
4485                         break;
4486                 }
4487                 case OP_FBEQ: {
4488                         guchar *jump = code;
4489                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4490                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4491                         amd64_patch (jump, code);
4492                         break;
4493                 }
4494                 case OP_FBNE_UN:
4495                         /* Branch if C013 != 100 */
4496                         /* branch if !ZF or (PF|CF) */
4497                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4498                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4499                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4500                         break;
4501                 case OP_FBLT:
4502                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4503                         break;
4504                 case OP_FBLT_UN:
4505                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4506                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4507                         break;
4508                 case OP_FBGT:
4509                 case OP_FBGT_UN:
4510                         if (ins->opcode == OP_FBGT) {
4511                                 guchar *br1;
4512
4513                                 /* skip branch if C1=1 */
4514                                 br1 = code;
4515                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4516                                 /* branch if (C0 | C3) = 1 */
4517                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4518                                 amd64_patch (br1, code);
4519                                 break;
4520                         } else {
4521                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4522                         }
4523                         break;
4524                 case OP_FBGE: {
4525                         /* Branch if C013 == 100 or 001 */
4526                         guchar *br1;
4527
4528                         /* skip branch if C1=1 */
4529                         br1 = code;
4530                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4531                         /* branch if (C0 | C3) = 1 */
4532                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4533                         amd64_patch (br1, code);
4534                         break;
4535                 }
4536                 case OP_FBGE_UN:
4537                         /* Branch if C013 == 000 */
4538                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4539                         break;
4540                 case OP_FBLE: {
4541                         /* Branch if C013=000 or 100 */
4542                         guchar *br1;
4543
4544                         /* skip branch if C1=1 */
4545                         br1 = code;
4546                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4547                         /* branch if C0=0 */
4548                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4549                         amd64_patch (br1, code);
4550                         break;
4551                 }
4552                 case OP_FBLE_UN:
4553                         /* Branch if C013 != 001 */
4554                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4555                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4556                         break;
4557                 case OP_CKFINITE:
4558                         /* Transfer value to the fp stack */
4559                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4560                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4561                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4562
4563                         amd64_push_reg (code, AMD64_RAX);
4564                         amd64_fxam (code);
4565                         amd64_fnstsw (code);
4566                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4567                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4568                         amd64_pop_reg (code, AMD64_RAX);
4569                         amd64_fstp (code, 0);
4570                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4571                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4572                         break;
4573                 case OP_TLS_GET: {
4574                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4575                         break;
4576                 }
4577                 case OP_MEMORY_BARRIER: {
4578                         /* Not needed on amd64 */
4579                         break;
4580                 }
4581                 case OP_ATOMIC_ADD_I4:
4582                 case OP_ATOMIC_ADD_I8: {
4583                         int dreg = ins->dreg;
4584                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4585
4586                         if (dreg == ins->inst_basereg)
4587                                 dreg = AMD64_R11;
4588
4589                         if (dreg != ins->sreg2)
4590                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4591
4592                         x86_prefix (code, X86_LOCK_PREFIX);
4593                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4594
4595                         if (dreg != ins->dreg)
4596                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4597
4598                         break;
4599                 }
4600                 case OP_ATOMIC_ADD_NEW_I4:
4601                 case OP_ATOMIC_ADD_NEW_I8: {
4602                         int dreg = ins->dreg;
4603                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4604
4605                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4606                                 dreg = AMD64_R11;
4607
4608                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4609                         amd64_prefix (code, X86_LOCK_PREFIX);
4610                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4611                         /* dreg contains the old value, add with sreg2 value */
4612                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4613
4614                         if (ins->dreg != dreg)
4615                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4616
4617                         break;
4618                 }
4619                 case OP_ATOMIC_EXCHANGE_I4:
4620                 case OP_ATOMIC_EXCHANGE_I8:
4621                 case OP_ATOMIC_CAS_IMM_I4: {
4622                         guchar *br[2];
4623                         int sreg2 = ins->sreg2;
4624                         int breg = ins->inst_basereg;
4625                         guint32 size;
4626                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4627
4628                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4629                                 size = 8;
4630                         else
4631                                 size = 4;
4632
4633                         /*
4634                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4635                          * an explanation of how this works.
4636                          */
4637
4638                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4639                          * hack to overcome limits in x86 reg allocator
4640                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4641                          */
4642                         g_assert (ins->dreg == AMD64_RAX);
4643
4644                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4645                                 /* Highly unlikely, but possible */
4646                                 need_push = TRUE;
4647
4648                         /* The pushes invalidate rsp */
4649                         if ((breg == AMD64_RAX) || need_push) {
4650                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4651                                 breg = AMD64_R11;
4652                         }
4653
4654                         /* We need the EAX reg for the comparand */
4655                         if (ins->sreg2 == AMD64_RAX) {
4656                                 if (breg != AMD64_R11) {
4657                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4658                                         sreg2 = AMD64_R11;
4659                                 } else {
4660                                         g_assert (need_push);
4661                                         amd64_push_reg (code, AMD64_RDX);
4662                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4663                                         sreg2 = AMD64_RDX;
4664                                         rdx_pushed = TRUE;
4665                                 }
4666                         }
4667
4668                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4669                                 if (ins->backend.data == NULL)
4670                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4671                                 else
4672                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4673
4674                                 amd64_prefix (code, X86_LOCK_PREFIX);
4675                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4676                         } else {
4677                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4678
4679                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4680                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4681                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4682                                 amd64_patch (br [1], br [0]);
4683                         }
4684
4685                         if (rdx_pushed)
4686                                 amd64_pop_reg (code, AMD64_RDX);
4687
4688                         break;
4689                 }
4690                 default:
4691                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4692                         g_assert_not_reached ();
4693                 }
4694
4695                 if ((code - cfg->native_code - offset) > max_len) {
4696                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4697                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4698                         g_assert_not_reached ();
4699                 }
4700
4701                 cpos += max_len;
4702
4703                 last_ins = ins;
4704                 last_offset = offset;
4705         }
4706
4707         cfg->code_len = code - cfg->native_code;
4708 }
4709
4710 #endif /* DISABLE_JIT */
4711
4712 void
4713 mono_arch_register_lowlevel_calls (void)
4714 {
4715         /* The signature doesn't matter */
4716         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4717 }
4718
4719 void
4720 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4721 {
4722         MonoJumpInfo *patch_info;
4723         gboolean compile_aot = !run_cctors;
4724
4725         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4726                 unsigned char *ip = patch_info->ip.i + code;
4727                 unsigned char *target;
4728
4729                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4730
4731                 if (compile_aot) {
4732                         switch (patch_info->type) {
4733                         case MONO_PATCH_INFO_BB:
4734                         case MONO_PATCH_INFO_LABEL:
4735                                 break;
4736                         default:
4737                                 /* No need to patch these */
4738                                 continue;
4739                         }
4740                 }
4741
4742                 switch (patch_info->type) {
4743                 case MONO_PATCH_INFO_NONE:
4744                         continue;
4745                 case MONO_PATCH_INFO_METHOD_REL:
4746                 case MONO_PATCH_INFO_R8:
4747                 case MONO_PATCH_INFO_R4:
4748                         g_assert_not_reached ();
4749                         continue;
4750                 case MONO_PATCH_INFO_BB:
4751                         break;
4752                 default:
4753                         break;
4754                 }
4755
4756                 /*
4757                  * Debug code to help track down problems where the target of a near call is
4758                  * is not valid.
4759                  */
4760                 if (amd64_is_near_call (ip)) {
4761                         gint64 disp = (guint8*)target - (guint8*)ip;
4762
4763                         if (!amd64_is_imm32 (disp)) {
4764                                 printf ("TYPE: %d\n", patch_info->type);
4765                                 switch (patch_info->type) {
4766                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4767                                         printf ("V: %s\n", patch_info->data.name);
4768                                         break;
4769                                 case MONO_PATCH_INFO_METHOD_JUMP:
4770                                 case MONO_PATCH_INFO_METHOD:
4771                                         printf ("V: %s\n", patch_info->data.method->name);
4772                                         break;
4773                                 default:
4774                                         break;
4775                                 }
4776                         }
4777                 }
4778
4779                 amd64_patch (ip, (gpointer)target);
4780         }
4781 }
4782
4783 static int
4784 get_max_epilog_size (MonoCompile *cfg)
4785 {
4786         int max_epilog_size = 16;
4787
4788         if (cfg->method->save_lmf)
4789                 max_epilog_size += 256;
4790
4791         if (mono_jit_trace_calls != NULL)
4792                 max_epilog_size += 50;
4793
4794         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4795                 max_epilog_size += 50;
4796
4797         max_epilog_size += (AMD64_NREG * 2);
4798
4799         return max_epilog_size;
4800 }
4801
4802 /*
4803  * This macro is used for testing whenever the unwinder works correctly at every point
4804  * where an async exception can happen.
4805  */
4806 /* This will generate a SIGSEGV at the given point in the code */
4807 #define async_exc_point(code) do { \
4808     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4809          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4810              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4811          cfg->arch.async_point_count ++; \
4812     } \
4813 } while (0)
4814
4815 guint8 *
4816 mono_arch_emit_prolog (MonoCompile *cfg)
4817 {
4818         MonoMethod *method = cfg->method;
4819         MonoBasicBlock *bb;
4820         MonoMethodSignature *sig;
4821         MonoInst *ins;
4822         int alloc_size, pos, max_offset, i, quad, max_epilog_size;
4823         guint8 *code;
4824         CallInfo *cinfo;
4825         gint32 lmf_offset = cfg->arch.lmf_offset;
4826         gboolean args_clobbered = FALSE;
4827         gboolean trace = FALSE;
4828
4829         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4830
4831         code = cfg->native_code = g_malloc (cfg->code_size);
4832
4833         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4834                 trace = TRUE;
4835
4836         /* Amount of stack space allocated by register saving code */
4837         pos = 0;
4838
4839         /*
4840          * The prolog consists of the following parts:
4841          * FP present:
4842          * - push rbp, mov rbp, rsp
4843          * - save callee saved regs using pushes
4844          * - allocate frame
4845          * - save rgctx if needed
4846          * - save lmf if needed
4847          * FP not present:
4848          * - allocate frame
4849          * - save rgctx if needed
4850          * - save lmf if needed
4851          * - save callee saved regs using moves
4852          */
4853
4854         async_exc_point (code);
4855
4856         if (!cfg->arch.omit_fp) {
4857                 amd64_push_reg (code, AMD64_RBP);
4858                 async_exc_point (code);
4859 #ifdef PLATFORM_WIN32
4860                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4861 #endif
4862
4863                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4864                 async_exc_point (code);
4865 #ifdef PLATFORM_WIN32
4866                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4867 #endif
4868         }
4869
4870         /* Save callee saved registers */
4871         if (!cfg->arch.omit_fp && !method->save_lmf) {
4872                 for (i = 0; i < AMD64_NREG; ++i)
4873                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4874                                 amd64_push_reg (code, i);
4875                                 pos += sizeof (gpointer);
4876                                 async_exc_point (code);
4877                         }
4878         }
4879
4880         if (cfg->arch.omit_fp) {
4881                 /*
4882                  * On enter, the stack is misaligned by the the pushing of the return
4883                  * address. It is either made aligned by the pushing of %rbp, or by
4884                  * this.
4885                  */
4886                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4887                 if ((alloc_size % 16) == 0)
4888                         alloc_size += 8;
4889         } else {
4890                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4891
4892                 alloc_size -= pos;
4893         }
4894
4895         cfg->arch.stack_alloc_size = alloc_size;
4896
4897         /* Allocate stack frame */
4898         if (alloc_size) {
4899                 /* See mono_emit_stack_alloc */
4900 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4901                 guint32 remaining_size = alloc_size;
4902                 while (remaining_size >= 0x1000) {
4903                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4904                         async_exc_point (code);
4905 #ifdef PLATFORM_WIN32
4906                         if (cfg->arch.omit_fp)
4907                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4908 #endif
4909
4910                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4911                         remaining_size -= 0x1000;
4912                 }
4913                 if (remaining_size) {
4914                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4915                         async_exc_point (code);
4916 #ifdef PLATFORM_WIN32
4917                         if (cfg->arch.omit_fp)
4918                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4919 #endif
4920                 }
4921 #else
4922                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4923                 async_exc_point (code);
4924 #endif
4925         }
4926
4927         /* Stack alignment check */
4928 #if 0
4929         {
4930                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4931                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4932                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4933                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4934                 amd64_breakpoint (code);
4935         }
4936 #endif
4937
4938         /* Save LMF */
4939         if (method->save_lmf) {
4940                 /*
4941                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4942                  */
4943                 /* sp is saved right before calls */
4944                 /* Skip method (only needed for trampoline LMF frames) */
4945                 /* Save callee saved regs */
4946                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4947                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4948                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4949                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4950                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4951                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4952         }
4953
4954         /* Save callee saved registers */
4955         if (cfg->arch.omit_fp && !method->save_lmf) {
4956                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4957
4958                 /* Save caller saved registers after sp is adjusted */
4959                 /* The registers are saved at the bottom of the frame */
4960                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4961                 for (i = 0; i < AMD64_NREG; ++i)
4962                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4963                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4964                                 save_area_offset += 8;
4965                                 async_exc_point (code);
4966                         }
4967         }
4968
4969         /* store runtime generic context */
4970         if (cfg->rgctx_var) {
4971                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4972                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4973
4974                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4975         }
4976
4977         /* compute max_offset in order to use short forward jumps */
4978         max_offset = 0;
4979         max_epilog_size = get_max_epilog_size (cfg);
4980         if (cfg->opt & MONO_OPT_BRANCH) {
4981                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4982                         MonoInst *ins;
4983                         bb->max_offset = max_offset;
4984
4985                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4986                                 max_offset += 6;
4987                         /* max alignment for loops */
4988                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4989                                 max_offset += LOOP_ALIGNMENT;
4990
4991                         MONO_BB_FOR_EACH_INS (bb, ins) {
4992                                 if (ins->opcode == OP_LABEL)
4993                                         ins->inst_c1 = max_offset;
4994
4995                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4996                         }
4997
4998                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4999                                 /* The tracing code can be quite large */
5000                                 max_offset += max_epilog_size;
5001                 }
5002         }
5003
5004         sig = mono_method_signature (method);
5005         pos = 0;
5006
5007         cinfo = cfg->arch.cinfo;
5008
5009         if (sig->ret->type != MONO_TYPE_VOID) {
5010                 /* Save volatile arguments to the stack */
5011                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5012                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5013         }
5014
5015         /* Keep this in sync with emit_load_volatile_arguments */
5016         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5017                 ArgInfo *ainfo = cinfo->args + i;
5018                 gint32 stack_offset;
5019                 MonoType *arg_type;
5020
5021                 ins = cfg->args [i];
5022
5023                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5024                         /* Unused arguments */
5025                         continue;
5026
5027                 if (sig->hasthis && (i == 0))
5028                         arg_type = &mono_defaults.object_class->byval_arg;
5029                 else
5030                         arg_type = sig->params [i - sig->hasthis];
5031
5032                 stack_offset = ainfo->offset + ARGS_OFFSET;
5033
5034                 if (cfg->globalra) {
5035                         /* All the other moves are done by the register allocator */
5036                         switch (ainfo->storage) {
5037                         case ArgInFloatSSEReg:
5038                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5039                                 break;
5040                         case ArgValuetypeInReg:
5041                                 for (quad = 0; quad < 2; quad ++) {
5042                                         switch (ainfo->pair_storage [quad]) {
5043                                         case ArgInIReg:
5044                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5045                                                 break;
5046                                         case ArgInFloatSSEReg:
5047                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5048                                                 break;
5049                                         case ArgInDoubleSSEReg:
5050                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5051                                                 break;
5052                                         case ArgNone:
5053                                                 break;
5054                                         default:
5055                                                 g_assert_not_reached ();
5056                                         }
5057                                 }
5058                                 break;
5059                         default:
5060                                 break;
5061                         }
5062
5063                         continue;
5064                 }
5065
5066                 /* Save volatile arguments to the stack */
5067                 if (ins->opcode != OP_REGVAR) {
5068                         switch (ainfo->storage) {
5069                         case ArgInIReg: {
5070                                 guint32 size = 8;
5071
5072                                 /* FIXME: I1 etc */
5073                                 /*
5074                                 if (stack_offset & 0x1)
5075                                         size = 1;
5076                                 else if (stack_offset & 0x2)
5077                                         size = 2;
5078                                 else if (stack_offset & 0x4)
5079                                         size = 4;
5080                                 else
5081                                         size = 8;
5082                                 */
5083                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5084                                 break;
5085                         }
5086                         case ArgInFloatSSEReg:
5087                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5088                                 break;
5089                         case ArgInDoubleSSEReg:
5090                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5091                                 break;
5092                         case ArgValuetypeInReg:
5093                                 for (quad = 0; quad < 2; quad ++) {
5094                                         switch (ainfo->pair_storage [quad]) {
5095                                         case ArgInIReg:
5096                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5097                                                 break;
5098                                         case ArgInFloatSSEReg:
5099                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5100                                                 break;
5101                                         case ArgInDoubleSSEReg:
5102                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5103                                                 break;
5104                                         case ArgNone:
5105                                                 break;
5106                                         default:
5107                                                 g_assert_not_reached ();
5108                                         }
5109                                 }
5110                                 break;
5111                         case ArgValuetypeAddrInIReg:
5112                                 if (ainfo->pair_storage [0] == ArgInIReg)
5113                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5114                                 break;
5115                         default:
5116                                 break;
5117                         }
5118                 } else {
5119                         /* Argument allocated to (non-volatile) register */
5120                         switch (ainfo->storage) {
5121                         case ArgInIReg:
5122                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5123                                 break;
5124                         case ArgOnStack:
5125                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5126                                 break;
5127                         default:
5128                                 g_assert_not_reached ();
5129                         }
5130                 }
5131         }
5132
5133         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5134         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5135                 guint64 domain = (guint64)cfg->domain;
5136
5137                 args_clobbered = TRUE;
5138
5139                 /*
5140                  * The call might clobber argument registers, but they are already
5141                  * saved to the stack/global regs.
5142                  */
5143                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5144                         guint8 *buf, *no_domain_branch;
5145
5146                         code = emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5147                         if ((domain >> 32) == 0)
5148                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5149                         else
5150                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5151                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
5152                         no_domain_branch = code;
5153                         x86_branch8 (code, X86_CC_NE, 0, 0);
5154                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
5155                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5156                         buf = code;
5157                         x86_branch8 (code, X86_CC_NE, 0, 0);
5158                         amd64_patch (no_domain_branch, code);
5159                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5160                                           (gpointer)"mono_jit_thread_attach", TRUE);
5161                         amd64_patch (buf, code);
5162 #ifdef PLATFORM_WIN32
5163                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5164                         /* FIXME: Add a separate key for LMF to avoid this */
5165                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5166 #endif
5167                 } else {
5168                         g_assert (!cfg->compile_aot);
5169                         if ((domain >> 32) == 0)
5170                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5171                         else
5172                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5173                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5174                                           (gpointer)"mono_jit_thread_attach", TRUE);
5175                 }
5176         }
5177
5178         if (method->save_lmf) {
5179                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5180                         /*
5181                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5182                          * through the mono_lmf_addr TLS variable.
5183                          */
5184                         /* %rax = previous_lmf */
5185                         x86_prefix (code, X86_FS_PREFIX);
5186                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5187
5188                         /* Save previous_lmf */
5189                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
5190                         /* Set new lmf */
5191                         if (lmf_offset == 0) {
5192                                 x86_prefix (code, X86_FS_PREFIX);
5193                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
5194                         } else {
5195                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5196                                 x86_prefix (code, X86_FS_PREFIX);
5197                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5198                         }
5199                 } else {
5200                         if (lmf_addr_tls_offset != -1) {
5201                                 /* Load lmf quicky using the FS register */
5202                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
5203 #ifdef PLATFORM_WIN32
5204                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5205                                 /* FIXME: Add a separate key for LMF to avoid this */
5206                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5207 #endif
5208                         }
5209                         else {
5210                                 /*
5211                                  * The call might clobber argument registers, but they are already
5212                                  * saved to the stack/global regs.
5213                                  */
5214                                 args_clobbered = TRUE;
5215                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5216                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
5217                         }
5218
5219                         /* Save lmf_addr */
5220                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
5221                         /* Save previous_lmf */
5222                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
5223                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
5224                         /* Set new lmf */
5225                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5226                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
5227                 }
5228         }
5229
5230         if (trace) {
5231                 args_clobbered = TRUE;
5232                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5233         }
5234
5235         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5236                 args_clobbered = TRUE;
5237
5238         /*
5239          * Optimize the common case of the first bblock making a call with the same
5240          * arguments as the method. This works because the arguments are still in their
5241          * original argument registers.
5242          * FIXME: Generalize this
5243          */
5244         if (!args_clobbered) {
5245                 MonoBasicBlock *first_bb = cfg->bb_entry;
5246                 MonoInst *next;
5247
5248                 next = mono_bb_first_ins (first_bb);
5249                 if (!next && first_bb->next_bb) {
5250                         first_bb = first_bb->next_bb;
5251                         next = mono_bb_first_ins (first_bb);
5252                 }
5253
5254                 if (first_bb->in_count > 1)
5255                         next = NULL;
5256
5257                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
5258                         ArgInfo *ainfo = cinfo->args + i;
5259                         gboolean match = FALSE;
5260
5261                         ins = cfg->args [i];
5262                         if (ins->opcode != OP_REGVAR) {
5263                                 switch (ainfo->storage) {
5264                                 case ArgInIReg: {
5265                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
5266                                                 if (next->dreg == ainfo->reg) {
5267                                                         NULLIFY_INS (next);
5268                                                         match = TRUE;
5269                                                 } else {
5270                                                         next->opcode = OP_MOVE;
5271                                                         next->sreg1 = ainfo->reg;
5272                                                         /* Only continue if the instruction doesn't change argument regs */
5273                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
5274                                                                 match = TRUE;
5275                                                 }
5276                                         }
5277                                         break;
5278                                 }
5279                                 default:
5280                                         break;
5281                                 }
5282                         } else {
5283                                 /* Argument allocated to (non-volatile) register */
5284                                 switch (ainfo->storage) {
5285                                 case ArgInIReg:
5286                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
5287                                                 NULLIFY_INS (next);
5288                                                 match = TRUE;
5289                                         }
5290                                         break;
5291                                 default:
5292                                         break;
5293                                 }
5294                         }
5295
5296                         if (match) {
5297                                 next = next->next;
5298                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
5299                                 if (!next)
5300                                         break;
5301                         }
5302                 }
5303         }
5304
5305         cfg->code_len = code - cfg->native_code;
5306
5307         g_assert (cfg->code_len < cfg->code_size);
5308
5309         return code;
5310 }
5311
5312 void
5313 mono_arch_emit_epilog (MonoCompile *cfg)
5314 {
5315         MonoMethod *method = cfg->method;
5316         int quad, pos, i;
5317         guint8 *code;
5318         int max_epilog_size;
5319         CallInfo *cinfo;
5320         gint32 lmf_offset = cfg->arch.lmf_offset;
5321
5322         max_epilog_size = get_max_epilog_size (cfg);
5323
5324         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5325                 cfg->code_size *= 2;
5326                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5327                 mono_jit_stats.code_reallocs++;
5328         }
5329
5330         code = cfg->native_code + cfg->code_len;
5331
5332         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5333                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5334
5335         /* the code restoring the registers must be kept in sync with OP_JMP */
5336         pos = 0;
5337
5338         if (method->save_lmf) {
5339                 /* check if we need to restore protection of the stack after a stack overflow */
5340                 if (mono_get_jit_tls_offset () != -1) {
5341                         guint8 *patch;
5342                         code = emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5343                         /* we load the value in a separate instruction: this mechanism may be
5344                          * used later as a safer way to do thread interruption
5345                          */
5346                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
5347                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5348                         patch = code;
5349                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
5350                         /* note that the call trampoline will preserve eax/edx */
5351                         x86_call_reg (code, X86_ECX);
5352                         x86_patch (patch, code);
5353                 } else {
5354                         /* FIXME: maybe save the jit tls in the prolog */
5355                 }
5356                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5357                         /*
5358                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5359                          * through the mono_lmf_addr TLS variable.
5360                          */
5361                         /* reg = previous_lmf */
5362                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5363                         x86_prefix (code, X86_FS_PREFIX);
5364                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5365                 } else {
5366                         /* Restore previous lmf */
5367                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5368                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5369                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5370                 }
5371
5372                 /* Restore caller saved regs */
5373                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5374                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5375                 }
5376                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5377                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5378                 }
5379                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5380                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5381                 }
5382                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5383                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5384                 }
5385                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5386                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5387                 }
5388                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5389                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5390                 }
5391         } else {
5392
5393                 if (cfg->arch.omit_fp) {
5394                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5395
5396                         for (i = 0; i < AMD64_NREG; ++i)
5397                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5398                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5399                                         save_area_offset += 8;
5400                                 }
5401                 }
5402                 else {
5403                         for (i = 0; i < AMD64_NREG; ++i)
5404                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5405                                         pos -= sizeof (gpointer);
5406
5407                         if (pos) {
5408                                 if (pos == - sizeof (gpointer)) {
5409                                         /* Only one register, so avoid lea */
5410                                         for (i = AMD64_NREG - 1; i > 0; --i)
5411                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5412                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5413                                                 }
5414                                 }
5415                                 else {
5416                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5417
5418                                         /* Pop registers in reverse order */
5419                                         for (i = AMD64_NREG - 1; i > 0; --i)
5420                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5421                                                         amd64_pop_reg (code, i);
5422                                                 }
5423                                 }
5424                         }
5425                 }
5426         }
5427
5428         /* Load returned vtypes into registers if needed */
5429         cinfo = cfg->arch.cinfo;
5430         if (cinfo->ret.storage == ArgValuetypeInReg) {
5431                 ArgInfo *ainfo = &cinfo->ret;
5432                 MonoInst *inst = cfg->ret;
5433
5434                 for (quad = 0; quad < 2; quad ++) {
5435                         switch (ainfo->pair_storage [quad]) {
5436                         case ArgInIReg:
5437                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5438                                 break;
5439                         case ArgInFloatSSEReg:
5440                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5441                                 break;
5442                         case ArgInDoubleSSEReg:
5443                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5444                                 break;
5445                         case ArgNone:
5446                                 break;
5447                         default:
5448                                 g_assert_not_reached ();
5449                         }
5450                 }
5451         }
5452
5453         if (cfg->arch.omit_fp) {
5454                 if (cfg->arch.stack_alloc_size)
5455                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5456         } else {
5457                 amd64_leave (code);
5458         }
5459         async_exc_point (code);
5460         amd64_ret (code);
5461
5462         cfg->code_len = code - cfg->native_code;
5463
5464         g_assert (cfg->code_len < cfg->code_size);
5465
5466         if (cfg->arch.omit_fp) {
5467                 /*
5468                  * Encode the stack size into used_int_regs so the exception handler
5469                  * can access it.
5470                  */
5471                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5472                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5473         }
5474 }
5475
5476 void
5477 mono_arch_emit_exceptions (MonoCompile *cfg)
5478 {
5479         MonoJumpInfo *patch_info;
5480         int nthrows, i;
5481         guint8 *code;
5482         MonoClass *exc_classes [16];
5483         guint8 *exc_throw_start [16], *exc_throw_end [16];
5484         guint32 code_size = 0;
5485
5486         /* Compute needed space */
5487         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5488                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5489                         code_size += 40;
5490                 if (patch_info->type == MONO_PATCH_INFO_R8)
5491                         code_size += 8 + 15; /* sizeof (double) + alignment */
5492                 if (patch_info->type == MONO_PATCH_INFO_R4)
5493                         code_size += 4 + 15; /* sizeof (float) + alignment */
5494         }
5495
5496         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5497                 cfg->code_size *= 2;
5498                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5499                 mono_jit_stats.code_reallocs++;
5500         }
5501
5502         code = cfg->native_code + cfg->code_len;
5503
5504         /* add code to raise exceptions */
5505         nthrows = 0;
5506         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5507                 switch (patch_info->type) {
5508                 case MONO_PATCH_INFO_EXC: {
5509                         MonoClass *exc_class;
5510                         guint8 *buf, *buf2;
5511                         guint32 throw_ip;
5512
5513                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5514
5515                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5516                         g_assert (exc_class);
5517                         throw_ip = patch_info->ip.i;
5518
5519                         //x86_breakpoint (code);
5520                         /* Find a throw sequence for the same exception class */
5521                         for (i = 0; i < nthrows; ++i)
5522                                 if (exc_classes [i] == exc_class)
5523                                         break;
5524                         if (i < nthrows) {
5525                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5526                                 x86_jump_code (code, exc_throw_start [i]);
5527                                 patch_info->type = MONO_PATCH_INFO_NONE;
5528                         }
5529                         else {
5530                                 buf = code;
5531                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5532                                 buf2 = code;
5533
5534                                 if (nthrows < 16) {
5535                                         exc_classes [nthrows] = exc_class;
5536                                         exc_throw_start [nthrows] = code;
5537                                 }
5538                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5539
5540                                 patch_info->type = MONO_PATCH_INFO_NONE;
5541
5542                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5543
5544                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5545                                 while (buf < buf2)
5546                                         x86_nop (buf);
5547
5548                                 if (nthrows < 16) {
5549                                         exc_throw_end [nthrows] = code;
5550                                         nthrows ++;
5551                                 }
5552                         }
5553                         break;
5554                 }
5555                 default:
5556                         /* do nothing */
5557                         break;
5558                 }
5559         }
5560
5561         /* Handle relocations with RIP relative addressing */
5562         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5563                 gboolean remove = FALSE;
5564
5565                 switch (patch_info->type) {
5566                 case MONO_PATCH_INFO_R8:
5567                 case MONO_PATCH_INFO_R4: {
5568                         guint8 *pos;
5569
5570                         /* The SSE opcodes require a 16 byte alignment */
5571                         code = (guint8*)ALIGN_TO (code, 16);
5572
5573                         pos = cfg->native_code + patch_info->ip.i;
5574
5575                         if (IS_REX (pos [1]))
5576                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5577                         else
5578                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5579
5580                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5581                                 *(double*)code = *(double*)patch_info->data.target;
5582                                 code += sizeof (double);
5583                         } else {
5584                                 *(float*)code = *(float*)patch_info->data.target;
5585                                 code += sizeof (float);
5586                         }
5587
5588                         remove = TRUE;
5589                         break;
5590                 }
5591                 default:
5592                         break;
5593                 }
5594
5595                 if (remove) {
5596                         if (patch_info == cfg->patch_info)
5597                                 cfg->patch_info = patch_info->next;
5598                         else {
5599                                 MonoJumpInfo *tmp;
5600
5601                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5602                                         ;
5603                                 tmp->next = patch_info->next;
5604                         }
5605                 }
5606         }
5607
5608         cfg->code_len = code - cfg->native_code;
5609
5610         g_assert (cfg->code_len < cfg->code_size);
5611
5612 }
5613
5614 void*
5615 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5616 {
5617         guchar *code = p;
5618         CallInfo *cinfo = NULL;
5619         MonoMethodSignature *sig;
5620         MonoInst *inst;
5621         int i, n, stack_area = 0;
5622
5623         /* Keep this in sync with mono_arch_get_argument_info */
5624
5625         if (enable_arguments) {
5626                 /* Allocate a new area on the stack and save arguments there */
5627                 sig = mono_method_signature (cfg->method);
5628
5629                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5630
5631                 n = sig->param_count + sig->hasthis;
5632
5633                 stack_area = ALIGN_TO (n * 8, 16);
5634
5635                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5636
5637                 for (i = 0; i < n; ++i) {
5638                         inst = cfg->args [i];
5639
5640                         if (inst->opcode == OP_REGVAR)
5641                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5642                         else {
5643                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5644                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5645                         }
5646                 }
5647         }
5648
5649         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5650         amd64_set_reg_template (code, AMD64_ARG_REG1);
5651         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5652         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5653
5654         if (enable_arguments)
5655                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5656
5657         return code;
5658 }
5659
5660 enum {
5661         SAVE_NONE,
5662         SAVE_STRUCT,
5663         SAVE_EAX,
5664         SAVE_EAX_EDX,
5665         SAVE_XMM
5666 };
5667
5668 void*
5669 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5670 {
5671         guchar *code = p;
5672         int save_mode = SAVE_NONE;
5673         MonoMethod *method = cfg->method;
5674         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5675
5676         switch (rtype) {
5677         case MONO_TYPE_VOID:
5678                 /* special case string .ctor icall */
5679                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5680                         save_mode = SAVE_EAX;
5681                 else
5682                         save_mode = SAVE_NONE;
5683                 break;
5684         case MONO_TYPE_I8:
5685         case MONO_TYPE_U8:
5686                 save_mode = SAVE_EAX;
5687                 break;
5688         case MONO_TYPE_R4:
5689         case MONO_TYPE_R8:
5690                 save_mode = SAVE_XMM;
5691                 break;
5692         case MONO_TYPE_GENERICINST:
5693                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5694                         save_mode = SAVE_EAX;
5695                         break;
5696                 }
5697                 /* Fall through */
5698         case MONO_TYPE_VALUETYPE:
5699                 save_mode = SAVE_STRUCT;
5700                 break;
5701         default:
5702                 save_mode = SAVE_EAX;
5703                 break;
5704         }
5705
5706         /* Save the result and copy it into the proper argument register */
5707         switch (save_mode) {
5708         case SAVE_EAX:
5709                 amd64_push_reg (code, AMD64_RAX);
5710                 /* Align stack */
5711                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5712                 if (enable_arguments)
5713                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5714                 break;
5715         case SAVE_STRUCT:
5716                 /* FIXME: */
5717                 if (enable_arguments)
5718                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5719                 break;
5720         case SAVE_XMM:
5721                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5722                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5723                 /* Align stack */
5724                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5725                 /*
5726                  * The result is already in the proper argument register so no copying
5727                  * needed.
5728                  */
5729                 break;
5730         case SAVE_NONE:
5731                 break;
5732         default:
5733                 g_assert_not_reached ();
5734         }
5735
5736         /* Set %al since this is a varargs call */
5737         if (save_mode == SAVE_XMM)
5738                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5739         else
5740                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5741
5742         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5743         amd64_set_reg_template (code, AMD64_ARG_REG1);
5744         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5745
5746         /* Restore result */
5747         switch (save_mode) {
5748         case SAVE_EAX:
5749                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5750                 amd64_pop_reg (code, AMD64_RAX);
5751                 break;
5752         case SAVE_STRUCT:
5753                 /* FIXME: */
5754                 break;
5755         case SAVE_XMM:
5756                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5757                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5758                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5759                 break;
5760         case SAVE_NONE:
5761                 break;
5762         default:
5763                 g_assert_not_reached ();
5764         }
5765
5766         return code;
5767 }
5768
5769 void
5770 mono_arch_flush_icache (guint8 *code, gint size)
5771 {
5772         /* Not needed */
5773 }
5774
5775 void
5776 mono_arch_flush_register_windows (void)
5777 {
5778 }
5779
5780 gboolean
5781 mono_arch_is_inst_imm (gint64 imm)
5782 {
5783         return amd64_is_imm32 (imm);
5784 }
5785
5786 /*
5787  * Determine whenever the trap whose info is in SIGINFO is caused by
5788  * integer overflow.
5789  */
5790 gboolean
5791 mono_arch_is_int_overflow (void *sigctx, void *info)
5792 {
5793         MonoContext ctx;
5794         guint8* rip;
5795         int reg;
5796         gint64 value;
5797
5798         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5799
5800         rip = (guint8*)ctx.rip;
5801
5802         if (IS_REX (rip [0])) {
5803                 reg = amd64_rex_b (rip [0]);
5804                 rip ++;
5805         }
5806         else
5807                 reg = 0;
5808
5809         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5810                 /* idiv REG */
5811                 reg += x86_modrm_rm (rip [1]);
5812
5813                 switch (reg) {
5814                 case AMD64_RAX:
5815                         value = ctx.rax;
5816                         break;
5817                 case AMD64_RBX:
5818                         value = ctx.rbx;
5819                         break;
5820                 case AMD64_RCX:
5821                         value = ctx.rcx;
5822                         break;
5823                 case AMD64_RDX:
5824                         value = ctx.rdx;
5825                         break;
5826                 case AMD64_RBP:
5827                         value = ctx.rbp;
5828                         break;
5829                 case AMD64_RSP:
5830                         value = ctx.rsp;
5831                         break;
5832                 case AMD64_RSI:
5833                         value = ctx.rsi;
5834                         break;
5835                 case AMD64_RDI:
5836                         value = ctx.rdi;
5837                         break;
5838                 case AMD64_R12:
5839                         value = ctx.r12;
5840                         break;
5841                 case AMD64_R13:
5842                         value = ctx.r13;
5843                         break;
5844                 case AMD64_R14:
5845                         value = ctx.r14;
5846                         break;
5847                 case AMD64_R15:
5848                         value = ctx.r15;
5849                         break;
5850                 default:
5851                         g_assert_not_reached ();
5852                         reg = -1;
5853                 }
5854
5855                 if (value == -1)
5856                         return TRUE;
5857         }
5858
5859         return FALSE;
5860 }
5861
5862 guint32
5863 mono_arch_get_patch_offset (guint8 *code)
5864 {
5865         return 3;
5866 }
5867
5868 /**
5869  * mono_breakpoint_clean_code:
5870  *
5871  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5872  * breakpoints in the original code, they are removed in the copy.
5873  *
5874  * Returns TRUE if no sw breakpoint was present.
5875  */
5876 gboolean
5877 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5878 {
5879         int i;
5880         gboolean can_write = TRUE;
5881         /*
5882          * If method_start is non-NULL we need to perform bound checks, since we access memory
5883          * at code - offset we could go before the start of the method and end up in a different
5884          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5885          * instead.
5886          */
5887         if (!method_start || code - offset >= method_start) {
5888                 memcpy (buf, code - offset, size);
5889         } else {
5890                 int diff = code - method_start;
5891                 memset (buf, 0, size);
5892                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5893         }
5894         code -= offset;
5895         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5896                 int idx = mono_breakpoint_info_index [i];
5897                 guint8 *ptr;
5898                 if (idx < 1)
5899                         continue;
5900                 ptr = mono_breakpoint_info [idx].address;
5901                 if (ptr >= code && ptr < code + size) {
5902                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5903                         can_write = FALSE;
5904                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5905                         buf [ptr - code] = saved_byte;
5906                 }
5907         }
5908         return can_write;
5909 }
5910
5911 gpointer
5912 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5913 {
5914         guint8 buf [10];
5915         guint32 reg;
5916         gint32 disp;
5917         guint8 rex = 0;
5918
5919         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5920         code = buf + 9;
5921
5922         *displacement = 0;
5923
5924         /* go to the start of the call instruction
5925          *
5926          * address_byte = (m << 6) | (o << 3) | reg
5927          * call opcode: 0xff address_byte displacement
5928          * 0xff m=1,o=2 imm8
5929          * 0xff m=2,o=2 imm32
5930          */
5931         code -= 7;
5932
5933         /*
5934          * A given byte sequence can match more than case here, so we have to be
5935          * really careful about the ordering of the cases. Longer sequences
5936          * come first.
5937          */
5938 #ifdef MONO_ARCH_HAVE_IMT
5939         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5940                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5941                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5942                  * ff 50 fc                call   *0xfffffffc(%rax)
5943                  */
5944                 reg = amd64_modrm_rm (code [5]);
5945                 disp = (signed char)code [6];
5946                 /* R10 is clobbered by the IMT thunk code */
5947                 g_assert (reg != AMD64_R10);
5948         }
5949 #else
5950         if (0) {
5951         }
5952 #endif
5953         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5954                         /*
5955                          * This is a interface call
5956                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5957                          * ff 10                  callq  *(%rax)
5958                          */
5959                 if (IS_REX (code [4]))
5960                         rex = code [4];
5961                 reg = amd64_modrm_rm (code [6]);
5962                 disp = 0;
5963                 /* R10 is clobbered by the IMT thunk code */
5964                 g_assert (reg != AMD64_R10);
5965         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5966                 /* call OFFSET(%rip) */
5967                 disp = *(guint32*)(code + 3);
5968                 return (gpointer*)(code + disp + 7);
5969         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5970                 /* call *[r12+disp32] */
5971                 if (IS_REX (code [-1]))
5972                         rex = code [-1];
5973                 reg = AMD64_RSP;
5974                 disp = *(gint32*)(code + 3);
5975         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5976                 /* call *[reg+disp32] */
5977                 if (IS_REX (code [0]))
5978                         rex = code [0];
5979                 reg = amd64_modrm_rm (code [2]);
5980                 disp = *(gint32*)(code + 3);
5981                 /* R10 is clobbered by the IMT thunk code */
5982                 g_assert (reg != AMD64_R10);
5983         } else if (code [2] == 0xe8) {
5984                 /* call <ADDR> */
5985                 return NULL;
5986         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5987                 /* call *[r12+disp32] */
5988                 if (IS_REX (code [2]))
5989                         rex = code [2];
5990                 reg = AMD64_RSP;
5991                 disp = *(gint8*)(code + 6);
5992         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5993                 /* call *%reg */
5994                 return NULL;
5995         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5996                 /* call *[reg+disp8] */
5997                 if (IS_REX (code [3]))
5998                         rex = code [3];
5999                 reg = amd64_modrm_rm (code [5]);
6000                 disp = *(gint8*)(code + 6);
6001                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6002         }
6003         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6004                         /*
6005                          * This is a interface call: should check the above code can't catch it earlier
6006                          * 8b 40 30   mov    0x30(%eax),%eax
6007                          * ff 10      call   *(%eax)
6008                          */
6009                 if (IS_REX (code [4]))
6010                         rex = code [4];
6011                 reg = amd64_modrm_rm (code [6]);
6012                 disp = 0;
6013         }
6014         else
6015                 g_assert_not_reached ();
6016
6017         reg += amd64_rex_b (rex);
6018
6019         /* R11 is clobbered by the trampoline code */
6020         g_assert (reg != AMD64_R11);
6021
6022         *displacement = disp;
6023         return regs [reg];
6024 }
6025
6026 gpointer*
6027 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
6028 {
6029         gpointer vt;
6030         int displacement;
6031         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
6032         if (!vt)
6033                 return NULL;
6034         return (gpointer*)((char*)vt + displacement);
6035 }
6036
6037 int
6038 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6039 {
6040         int this_reg = AMD64_ARG_REG1;
6041
6042         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6043                 CallInfo *cinfo;
6044
6045                 if (!gsctx && code)
6046                         gsctx = mono_get_generic_context_from_code (code);
6047
6048                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6049
6050                 if (cinfo->ret.storage != ArgValuetypeInReg)
6051                         this_reg = AMD64_ARG_REG2;
6052                 g_free (cinfo);
6053         }
6054
6055         return this_reg;
6056 }
6057
6058 gpointer
6059 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
6060 {
6061         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6062 }
6063
6064 #define MAX_ARCH_DELEGATE_PARAMS 10
6065
6066 gpointer
6067 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6068 {
6069         guint8 *code, *start;
6070         int i;
6071
6072         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6073                 return NULL;
6074
6075         /* FIXME: Support more cases */
6076         if (MONO_TYPE_ISSTRUCT (sig->ret))
6077                 return NULL;
6078
6079         if (has_target) {
6080                 static guint8* cached = NULL;
6081
6082                 if (cached)
6083                         return cached;
6084
6085                 start = code = mono_global_codeman_reserve (64);
6086
6087                 /* Replace the this argument with the target */
6088                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6089                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6090                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6091
6092                 g_assert ((code - start) < 64);
6093
6094                 mono_debug_add_delegate_trampoline (start, code - start);
6095
6096                 mono_memory_barrier ();
6097
6098                 cached = start;
6099         } else {
6100                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6101                 for (i = 0; i < sig->param_count; ++i)
6102                         if (!mono_is_regsize_var (sig->params [i]))
6103                                 return NULL;
6104                 if (sig->param_count > 4)
6105                         return NULL;
6106
6107                 code = cache [sig->param_count];
6108                 if (code)
6109                         return code;
6110
6111                 start = code = mono_global_codeman_reserve (64);
6112
6113                 if (sig->param_count == 0) {
6114                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6115                 } else {
6116                         /* We have to shift the arguments left */
6117                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6118                         for (i = 0; i < sig->param_count; ++i) {
6119 #ifdef PLATFORM_WIN32
6120                                 if (i < 3)
6121                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6122                                 else
6123                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6124 #else
6125                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6126 #endif
6127                         }
6128
6129                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6130                 }
6131                 g_assert ((code - start) < 64);
6132
6133                 mono_debug_add_delegate_trampoline (start, code - start);
6134
6135                 mono_memory_barrier ();
6136
6137                 cache [sig->param_count] = start;
6138         }
6139
6140         return start;
6141 }
6142
6143 /*
6144  * Support for fast access to the thread-local lmf structure using the GS
6145  * segment register on NPTL + kernel 2.6.x.
6146  */
6147
6148 static gboolean tls_offset_inited = FALSE;
6149
6150 void
6151 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
6152 {
6153         if (!tls_offset_inited) {
6154 #ifdef PLATFORM_WIN32
6155                 /*
6156                  * We need to init this multiple times, since when we are first called, the key might not
6157                  * be initialized yet.
6158                  */
6159                 appdomain_tls_offset = mono_domain_get_tls_key ();
6160                 lmf_tls_offset = mono_get_jit_tls_key ();
6161                 thread_tls_offset = mono_thread_get_tls_key ();
6162                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
6163
6164                 /* Only 64 tls entries can be accessed using inline code */
6165                 if (appdomain_tls_offset >= 64)
6166                         appdomain_tls_offset = -1;
6167                 if (lmf_tls_offset >= 64)
6168                         lmf_tls_offset = -1;
6169                 if (thread_tls_offset >= 64)
6170                         thread_tls_offset = -1;
6171 #else
6172                 tls_offset_inited = TRUE;
6173 #ifdef MONO_XEN_OPT
6174                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
6175 #endif
6176                 appdomain_tls_offset = mono_domain_get_tls_offset ();
6177                 lmf_tls_offset = mono_get_lmf_tls_offset ();
6178                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
6179                 thread_tls_offset = mono_thread_get_tls_offset ();
6180 #endif
6181         }
6182 }
6183
6184 void
6185 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6186 {
6187 }
6188
6189 void
6190 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
6191 {
6192         MonoCallInst *call = (MonoCallInst*)inst;
6193         CallInfo * cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, inst->signature, FALSE);
6194
6195         if (vt_reg != -1) {
6196                 MonoInst *vtarg;
6197
6198                 if (cinfo->ret.storage == ArgValuetypeInReg) {
6199                         /*
6200                          * The valuetype is in RAX:RDX after the call, need to be copied to
6201                          * the stack. Save the address here, so the call instruction can
6202                          * access it.
6203                          */
6204                         MonoInst *loc = cfg->arch.vret_addr_loc;
6205
6206                         g_assert (loc);
6207                         g_assert (loc->opcode == OP_REGOFFSET);
6208
6209                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, loc->inst_basereg, loc->inst_offset, vt_reg);
6210                 } else {
6211                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
6212                         vtarg->sreg1 = vt_reg;
6213                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
6214                         mono_bblock_add_inst (cfg->cbb, vtarg);
6215
6216                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
6217                 }
6218         }
6219
6220         /* add the this argument */
6221         if (this_reg != -1) {
6222                 MonoInst *this;
6223                 MONO_INST_NEW (cfg, this, OP_MOVE);
6224                 this->type = this_type;
6225                 this->sreg1 = this_reg;
6226                 this->dreg = mono_regstate_next_int (cfg->rs);
6227                 mono_bblock_add_inst (cfg->cbb, this);
6228
6229                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
6230         }
6231 }
6232
6233 #ifdef MONO_ARCH_HAVE_IMT
6234
6235 #define CMP_SIZE (6 + 1)
6236 #define CMP_REG_REG_SIZE (4 + 1)
6237 #define BR_SMALL_SIZE 2
6238 #define BR_LARGE_SIZE 6
6239 #define MOV_REG_IMM_SIZE 10
6240 #define MOV_REG_IMM_32BIT_SIZE 6
6241 #define JUMP_REG_SIZE (2 + 1)
6242
6243 static int
6244 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
6245 {
6246         int i, distance = 0;
6247         for (i = start; i < target; ++i)
6248                 distance += imt_entries [i]->chunk_size;
6249         return distance;
6250 }
6251
6252 /*
6253  * LOCKING: called with the domain lock held
6254  */
6255 gpointer
6256 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6257         gpointer fail_tramp)
6258 {
6259         int i;
6260         int size = 0;
6261         guint8 *code, *start;
6262         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
6263
6264         for (i = 0; i < count; ++i) {
6265                 MonoIMTCheckItem *item = imt_entries [i];
6266                 if (item->is_equals) {
6267                         if (item->check_target_idx) {
6268                                 if (!item->compare_done) {
6269                                         if (amd64_is_imm32 (item->key))
6270                                                 item->chunk_size += CMP_SIZE;
6271                                         else
6272                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6273                                 }
6274                                 if (vtable_is_32bit)
6275                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6276                                 else
6277                                         item->chunk_size += MOV_REG_IMM_SIZE;
6278                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
6279                         } else {
6280                                 if (fail_tramp) {
6281                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
6282                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
6283                                 } else {
6284                                         if (vtable_is_32bit)
6285                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6286                                         else
6287                                                 item->chunk_size += MOV_REG_IMM_SIZE;
6288                                         item->chunk_size += JUMP_REG_SIZE;
6289                                         /* with assert below:
6290                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
6291                                          */
6292                                 }
6293                         }
6294                 } else {
6295                         if (amd64_is_imm32 (item->key))
6296                                 item->chunk_size += CMP_SIZE;
6297                         else
6298                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6299                         item->chunk_size += BR_LARGE_SIZE;
6300                         imt_entries [item->check_target_idx]->compare_done = TRUE;
6301                 }
6302                 size += item->chunk_size;
6303         }
6304         if (fail_tramp)
6305                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6306         else
6307                 code = mono_code_manager_reserve (domain->code_mp, size);
6308         start = code;
6309         for (i = 0; i < count; ++i) {
6310                 MonoIMTCheckItem *item = imt_entries [i];
6311                 item->code_target = code;
6312                 if (item->is_equals) {
6313                         if (item->check_target_idx) {
6314                                 if (!item->compare_done) {
6315                                         if (amd64_is_imm32 (item->key))
6316                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6317                                         else {
6318                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6319                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6320                                         }
6321                                 }
6322                                 item->jmp_code = code;
6323                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6324                                 /* See the comment below about R10 */
6325                                 if (fail_tramp) {
6326                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
6327                                         amd64_jump_reg (code, AMD64_R10);
6328                                 } else {
6329                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6330                                         amd64_jump_membase (code, AMD64_R10, 0);
6331                                 }
6332                         } else {
6333                                 if (fail_tramp) {
6334                                         if (amd64_is_imm32 (item->key))
6335                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6336                                         else {
6337                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6338                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6339                                         }
6340                                         item->jmp_code = code;
6341                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6342                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
6343                                         amd64_jump_reg (code, AMD64_R10);
6344                                         amd64_patch (item->jmp_code, code);
6345                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
6346                                         amd64_jump_reg (code, AMD64_R10);
6347                                         item->jmp_code = NULL;
6348
6349                                 } else {
6350                                         /* enable the commented code to assert on wrong method */
6351 #if 0
6352                                         if (amd64_is_imm32 (item->key))
6353                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6354                                         else {
6355                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6356                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6357                                         }
6358                                         item->jmp_code = code;
6359                                         amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6360                                         /* See the comment below about R10 */
6361                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6362                                         amd64_jump_membase (code, AMD64_R10, 0);
6363                                         amd64_patch (item->jmp_code, code);
6364                                         amd64_breakpoint (code);
6365                                         item->jmp_code = NULL;
6366 #else
6367                                         /* We're using R10 here because R11
6368                                            needs to be preserved.  R10 needs
6369                                            to be preserved for calls which
6370                                            require a runtime generic context,
6371                                            but interface calls don't. */
6372                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6373                                         amd64_jump_membase (code, AMD64_R10, 0);
6374 #endif
6375                                 }
6376                         }
6377                 } else {
6378                         if (amd64_is_imm32 (item->key))
6379                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6380                         else {
6381                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6382                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6383                         }
6384                         item->jmp_code = code;
6385                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6386                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6387                         else
6388                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6389                 }
6390                 g_assert (code - item->code_target <= item->chunk_size);
6391         }
6392         /* patch the branches to get to the target items */
6393         for (i = 0; i < count; ++i) {
6394                 MonoIMTCheckItem *item = imt_entries [i];
6395                 if (item->jmp_code) {
6396                         if (item->check_target_idx) {
6397                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6398                         }
6399                 }
6400         }
6401
6402         if (!fail_tramp)
6403                 mono_stats.imt_thunks_size += code - start;
6404         g_assert (code - start <= size);
6405
6406         return start;
6407 }
6408
6409 MonoMethod*
6410 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6411 {
6412         return regs [MONO_ARCH_IMT_REG];
6413 }
6414
6415 MonoObject*
6416 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6417 {
6418         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6419 }
6420
6421 void
6422 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6423 {
6424         /* Done by the implementation of the CALL_MEMBASE opcodes */
6425 }
6426 #endif
6427
6428 MonoVTable*
6429 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6430 {
6431         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6432 }
6433
6434 MonoInst*
6435 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6436 {
6437         MonoInst *ins = NULL;
6438
6439         if (cmethod->klass == mono_defaults.math_class) {
6440                 if (strcmp (cmethod->name, "Sin") == 0) {
6441                         MONO_INST_NEW (cfg, ins, OP_SIN);
6442                         ins->inst_i0 = args [0];
6443                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6444                         MONO_INST_NEW (cfg, ins, OP_COS);
6445                         ins->inst_i0 = args [0];
6446                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6447                         MONO_INST_NEW (cfg, ins, OP_SQRT);
6448                         ins->inst_i0 = args [0];
6449                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6450                         MONO_INST_NEW (cfg, ins, OP_ABS);
6451                         ins->inst_i0 = args [0];
6452                 }
6453
6454                 if (cfg->opt & MONO_OPT_CMOV) {
6455                         int opcode = 0;
6456
6457                         if (strcmp (cmethod->name, "Min") == 0) {
6458                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6459                                         opcode = OP_IMIN;
6460                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6461                                         opcode = OP_IMIN_UN;
6462                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6463                                         opcode = OP_LMIN;
6464                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6465                                         opcode = OP_LMIN_UN;
6466                         } else if (strcmp (cmethod->name, "Max") == 0) {
6467                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6468                                         opcode = OP_IMAX;
6469                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6470                                         opcode = OP_IMAX_UN;
6471                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6472                                         opcode = OP_LMAX;
6473                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6474                                         opcode = OP_LMAX_UN;
6475                         }
6476
6477                         if (opcode) {
6478                                 MONO_INST_NEW (cfg, ins, opcode);
6479                                 ins->inst_i0 = args [0];
6480                                 ins->inst_i1 = args [1];
6481                         }
6482                 }
6483
6484 #if 0
6485                 /* OP_FREM is not IEEE compatible */
6486                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6487                         MONO_INST_NEW (cfg, ins, OP_FREM);
6488                         ins->inst_i0 = args [0];
6489                         ins->inst_i1 = args [1];
6490                 }
6491 #endif
6492         }
6493
6494         return ins;
6495 }
6496
6497 MonoInst*
6498 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6499 {
6500         MonoInst *ins = NULL;
6501         int opcode = 0;
6502
6503         if (cmethod->klass == mono_defaults.math_class) {
6504                 if (strcmp (cmethod->name, "Sin") == 0) {
6505                         opcode = OP_SIN;
6506                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6507                         opcode = OP_COS;
6508                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6509                         opcode = OP_SQRT;
6510                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6511                         opcode = OP_ABS;
6512                 }
6513
6514                 if (opcode) {
6515                         MONO_INST_NEW (cfg, ins, opcode);
6516                         ins->type = STACK_R8;
6517                         ins->dreg = mono_alloc_freg (cfg);
6518                         ins->sreg1 = args [0]->dreg;
6519                         MONO_ADD_INS (cfg->cbb, ins);
6520                 }
6521
6522                 opcode = 0;
6523                 if (cfg->opt & MONO_OPT_CMOV) {
6524                         if (strcmp (cmethod->name, "Min") == 0) {
6525                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6526                                         opcode = OP_IMIN;
6527                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6528                                         opcode = OP_IMIN_UN;
6529                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6530                                         opcode = OP_LMIN;
6531                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6532                                         opcode = OP_LMIN_UN;
6533                         } else if (strcmp (cmethod->name, "Max") == 0) {
6534                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6535                                         opcode = OP_IMAX;
6536                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6537                                         opcode = OP_IMAX_UN;
6538                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6539                                         opcode = OP_LMAX;
6540                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6541                                         opcode = OP_LMAX_UN;
6542                         }
6543                 }
6544
6545                 if (opcode) {
6546                         MONO_INST_NEW (cfg, ins, opcode);
6547                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6548                         ins->dreg = mono_alloc_ireg (cfg);
6549                         ins->sreg1 = args [0]->dreg;
6550                         ins->sreg2 = args [1]->dreg;
6551                         MONO_ADD_INS (cfg->cbb, ins);
6552                 }
6553
6554 #if 0
6555                 /* OP_FREM is not IEEE compatible */
6556                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6557                         MONO_INST_NEW (cfg, ins, OP_FREM);
6558                         ins->inst_i0 = args [0];
6559                         ins->inst_i1 = args [1];
6560                 }
6561 #endif
6562         }
6563
6564         /*
6565          * Can't implement CompareExchange methods this way since they have
6566          * three arguments.
6567          */
6568
6569         return ins;
6570 }
6571
6572 gboolean
6573 mono_arch_print_tree (MonoInst *tree, int arity)
6574 {
6575         return 0;
6576 }
6577
6578 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6579 {
6580         MonoInst* ins;
6581
6582         if (appdomain_tls_offset == -1)
6583                 return NULL;
6584
6585         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6586         ins->inst_offset = appdomain_tls_offset;
6587         return ins;
6588 }
6589
6590 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6591 {
6592         MonoInst* ins;
6593
6594         if (thread_tls_offset == -1)
6595                 return NULL;
6596
6597         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6598         ins->inst_offset = thread_tls_offset;
6599         return ins;
6600 }
6601
6602 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6603
6604 gpointer
6605 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6606 {
6607         switch (reg) {
6608         case AMD64_RCX: return (gpointer)ctx->rcx;
6609         case AMD64_RDX: return (gpointer)ctx->rdx;
6610         case AMD64_RBX: return (gpointer)ctx->rbx;
6611         case AMD64_RBP: return (gpointer)ctx->rbp;
6612         case AMD64_RSP: return (gpointer)ctx->rsp;
6613         default:
6614                 if (reg < 8)
6615                         return _CTX_REG (ctx, rax, reg);
6616                 else if (reg >= 12)
6617                         return _CTX_REG (ctx, r12, reg - 12);
6618                 else
6619                         g_assert_not_reached ();
6620         }
6621 }