mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *   Johan Lorensson (lateralusx.github@gmail.com)
  12  *
  13  * (C) 2003 Ximian, Inc.
  14  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  15  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  16  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  17  */
  18 #include "mini.h"
  19 #include <string.h>
  20 #include <math.h>
  21 #ifdef HAVE_UNISTD_H
  22 #include <unistd.h>
  23 #endif
  24
  25 #include <mono/metadata/abi-details.h>
  26 #include <mono/metadata/appdomain.h>
  27 #include <mono/metadata/debug-helpers.h>
  28 #include <mono/metadata/threads.h>
  29 #include <mono/metadata/profiler-private.h>
  30 #include <mono/metadata/mono-debug.h>
  31 #include <mono/metadata/gc-internals.h>
  32 #include <mono/utils/mono-math.h>
  33 #include <mono/utils/mono-mmap.h>
  34 #include <mono/utils/mono-memory-model.h>
  35 #include <mono/utils/mono-tls.h>
  36 #include <mono/utils/mono-hwcap.h>
  37 #include <mono/utils/mono-threads.h>
  38
  39 #include "trace.h"
  40 #include "ir-emit.h"
  41 #include "mini-amd64.h"
  42 #include "cpu-amd64.h"
  43 #include "debugger-agent.h"
  44 #include "mini-gc.h"
  45
  46 #ifdef MONO_XEN_OPT
  47 static gboolean optimize_for_xen = TRUE;
  48 #else
  49 #define optimize_for_xen 0
  50 #endif
  51
  52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  53
  54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  55
  56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  57
  58 #ifdef TARGET_WIN32
  59 /* Under windows, the calling convention is never stdcall */
  60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  61 #else
  62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  63 #endif
  64
  65 /* This mutex protects architecture specific caches */
  66 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  67 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  68 static mono_mutex_t mini_arch_mutex;
  69
  70 /* The single step trampoline */
  71 static gpointer ss_trampoline;
  72
  73 /* The breakpoint trampoline */
  74 static gpointer bp_trampoline;
  75
  76 /* Offset between fp and the first argument in the callee */
  77 #define ARGS_OFFSET 16
  78 #define GP_SCRATCH_REG AMD64_R11
  79
  80 /*
  81  * AMD64 register usage:
  82  * - callee saved registers are used for global register allocation
  83  * - %r11 is used for materializing 64 bit constants in opcodes
  84  * - the rest is used for local allocation
  85  */
  86
  87 /*
  88  * Floating point comparison results:
  89  *                  ZF PF CF
  90  * A > B            0  0  0
  91  * A < B            0  0  1
  92  * A = B            1  0  0
  93  * A > B            0  0  0
  94  * UNORDERED        1  1  1
  95  */
  96
  97 const char*
  98 mono_arch_regname (int reg)
  99 {
 100         switch (reg) {
 101         case AMD64_RAX: return "%rax";
 102         case AMD64_RBX: return "%rbx";
 103         case AMD64_RCX: return "%rcx";
 104         case AMD64_RDX: return "%rdx";
 105         case AMD64_RSP: return "%rsp";
 106         case AMD64_RBP: return "%rbp";
 107         case AMD64_RDI: return "%rdi";
 108         case AMD64_RSI: return "%rsi";
 109         case AMD64_R8: return "%r8";
 110         case AMD64_R9: return "%r9";
 111         case AMD64_R10: return "%r10";
 112         case AMD64_R11: return "%r11";
 113         case AMD64_R12: return "%r12";
 114         case AMD64_R13: return "%r13";
 115         case AMD64_R14: return "%r14";
 116         case AMD64_R15: return "%r15";
 117         }
 118         return "unknown";
 119 }
 120
 121 static const char * packed_xmmregs [] = {
 122         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 123         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 124 };
 125
 126 static const char * single_xmmregs [] = {
 127         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 128         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 129 };
 130
 131 const char*
 132 mono_arch_fregname (int reg)
 133 {
 134         if (reg < AMD64_XMM_NREG)
 135                 return single_xmmregs [reg];
 136         else
 137                 return "unknown";
 138 }
 139
 140 const char *
 141 mono_arch_xregname (int reg)
 142 {
 143         if (reg < AMD64_XMM_NREG)
 144                 return packed_xmmregs [reg];
 145         else
 146                 return "unknown";
 147 }
 148
 149 static gboolean
 150 debug_omit_fp (void)
 151 {
 152 #if 0
 153         return mono_debug_count ();
 154 #else
 155         return TRUE;
 156 #endif
 157 }
 158
 159 static inline gboolean
 160 amd64_is_near_call (guint8 *code)
 161 {
 162         /* Skip REX */
 163         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 164                 code += 1;
 165
 166         return code [0] == 0xe8;
 167 }
 168
 169 static inline gboolean
 170 amd64_use_imm32 (gint64 val)
 171 {
 172         if (mini_get_debug_options()->single_imm_size)
 173                 return FALSE;
 174
 175         return amd64_is_imm32 (val);
 176 }
 177
 178 static void
 179 amd64_patch (unsigned char* code, gpointer target)
 180 {
 181         guint8 rex = 0;
 182
 183         /* Skip REX */
 184         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 185                 rex = code [0];
 186                 code += 1;
 187         }
 188
 189         if ((code [0] & 0xf8) == 0xb8) {
 190                 /* amd64_set_reg_template */
 191                 *(guint64*)(code + 1) = (guint64)target;
 192         }
 193         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 194                 /* mov 0(%rip), %dreg */
 195                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 196         }
 197         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 198                 /* call *<OFFSET>(%rip) */
 199                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 200         }
 201         else if (code [0] == 0xe8) {
 202                 /* call <DISP> */
 203                 gint64 disp = (guint8*)target - (guint8*)code;
 204                 g_assert (amd64_is_imm32 (disp));
 205                 x86_patch (code, (unsigned char*)target);
 206         }
 207         else
 208                 x86_patch (code, (unsigned char*)target);
 209 }
 210
 211 void
 212 mono_amd64_patch (unsigned char* code, gpointer target)
 213 {
 214         amd64_patch (code, target);
 215 }
 216
 217 #define DEBUG(a) if (cfg->verbose_level > 1) a
 218
 219 static void inline
 220 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 221 {
 222     ainfo->offset = *stack_size;
 223
 224     if (*gr >= PARAM_REGS) {
 225                 ainfo->storage = ArgOnStack;
 226                 ainfo->arg_size = sizeof (mgreg_t);
 227                 /* Since the same stack slot size is used for all arg */
 228                 /*  types, it needs to be big enough to hold them all */
 229                 (*stack_size) += sizeof(mgreg_t);
 230     }
 231     else {
 232                 ainfo->storage = ArgInIReg;
 233                 ainfo->reg = param_regs [*gr];
 234                 (*gr) ++;
 235     }
 236 }
 237
 238 static void inline
 239 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 240 {
 241     ainfo->offset = *stack_size;
 242
 243     if (*gr >= FLOAT_PARAM_REGS) {
 244                 ainfo->storage = ArgOnStack;
 245                 ainfo->arg_size = sizeof (mgreg_t);
 246                 /* Since the same stack slot size is used for both float */
 247                 /*  types, it needs to be big enough to hold them both */
 248                 (*stack_size) += sizeof(mgreg_t);
 249     }
 250     else {
 251                 /* A double register */
 252                 if (is_double)
 253                         ainfo->storage = ArgInDoubleSSEReg;
 254                 else
 255                         ainfo->storage = ArgInFloatSSEReg;
 256                 ainfo->reg = *gr;
 257                 (*gr) += 1;
 258     }
 259 }
 260
 261 typedef enum ArgumentClass {
 262         ARG_CLASS_NO_CLASS,
 263         ARG_CLASS_MEMORY,
 264         ARG_CLASS_INTEGER,
 265         ARG_CLASS_SSE
 266 } ArgumentClass;
 267
 268 static ArgumentClass
 269 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 270 {
 271         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 272         MonoType *ptype;
 273
 274         ptype = mini_get_underlying_type (type);
 275         switch (ptype->type) {
 276         case MONO_TYPE_I1:
 277         case MONO_TYPE_U1:
 278         case MONO_TYPE_I2:
 279         case MONO_TYPE_U2:
 280         case MONO_TYPE_I4:
 281         case MONO_TYPE_U4:
 282         case MONO_TYPE_I:
 283         case MONO_TYPE_U:
 284         case MONO_TYPE_STRING:
 285         case MONO_TYPE_OBJECT:
 286         case MONO_TYPE_CLASS:
 287         case MONO_TYPE_SZARRAY:
 288         case MONO_TYPE_PTR:
 289         case MONO_TYPE_FNPTR:
 290         case MONO_TYPE_ARRAY:
 291         case MONO_TYPE_I8:
 292         case MONO_TYPE_U8:
 293                 class2 = ARG_CLASS_INTEGER;
 294                 break;
 295         case MONO_TYPE_R4:
 296         case MONO_TYPE_R8:
 297 #ifdef TARGET_WIN32
 298                 class2 = ARG_CLASS_INTEGER;
 299 #else
 300                 class2 = ARG_CLASS_SSE;
 301 #endif
 302                 break;
 303
 304         case MONO_TYPE_TYPEDBYREF:
 305                 g_assert_not_reached ();
 306
 307         case MONO_TYPE_GENERICINST:
 308                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 309                         class2 = ARG_CLASS_INTEGER;
 310                         break;
 311                 }
 312                 /* fall through */
 313         case MONO_TYPE_VALUETYPE: {
 314                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 315                 int i;
 316
 317                 for (i = 0; i < info->num_fields; ++i) {
 318                         class2 = class1;
 319                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 320                 }
 321                 break;
 322         }
 323         default:
 324                 g_assert_not_reached ();
 325         }
 326
 327         /* Merge */
 328         if (class1 == class2)
 329                 ;
 330         else if (class1 == ARG_CLASS_NO_CLASS)
 331                 class1 = class2;
 332         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 333                 class1 = ARG_CLASS_MEMORY;
 334         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 335                 class1 = ARG_CLASS_INTEGER;
 336         else
 337                 class1 = ARG_CLASS_SSE;
 338
 339         return class1;
 340 }
 341
 342 typedef struct {
 343         MonoType *type;
 344         int size, offset;
 345 } StructFieldInfo;
 346
 347 /*
 348  * collect_field_info_nested:
 349  *
 350  *   Collect field info from KLASS recursively into FIELDS.
 351  */
 352 static void
 353 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
 354 {
 355         MonoMarshalType *info;
 356         int i;
 357
 358         if (pinvoke) {
 359                 info = mono_marshal_load_type_info (klass);
 360                 g_assert(info);
 361                 for (i = 0; i < info->num_fields; ++i) {
 362                         if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 363                                 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
 364                         } else {
 365                                 guint32 align;
 366                                 StructFieldInfo f;
 367
 368                                 f.type = info->fields [i].field->type;
 369                                 f.size = mono_marshal_type_size (info->fields [i].field->type,
 370                                                                                                                            info->fields [i].mspec,
 371                                                                                                                            &align, TRUE, unicode);
 372                                 f.offset = offset + info->fields [i].offset;
 373                                 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
 374                                         /* This can happen with .pack directives eg. 'fixed' arrays */
 375                                         if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
 376                                                 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
 377                                                 g_array_append_val (fields_array, f);
 378                                                 while (f.size + f.offset < info->native_size) {
 379                                                         f.offset += f.size;
 380                                                         g_array_append_val (fields_array, f);
 381                                                 }
 382                                         } else {
 383                                                 f.size = info->native_size - f.offset;
 384                                                 g_array_append_val (fields_array, f);
 385                                         }
 386                                 } else {
 387                                         g_array_append_val (fields_array, f);
 388                                 }
 389                         }
 390                 }
 391         } else {
 392                 gpointer iter;
 393                 MonoClassField *field;
 394
 395                 iter = NULL;
 396                 while ((field = mono_class_get_fields (klass, &iter))) {
 397                         if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
 398                                 continue;
 399                         if (MONO_TYPE_ISSTRUCT (field->type)) {
 400                                 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
 401                         } else {
 402                                 int align;
 403                                 StructFieldInfo f;
 404
 405                                 f.type = field->type;
 406                                 f.size = mono_type_size (field->type, &align);
 407                                 f.offset = field->offset - sizeof (MonoObject) + offset;
 408
 409                                 g_array_append_val (fields_array, f);
 410                         }
 411                 }
 412         }
 413 }
 414
 415 #ifdef TARGET_WIN32
 416
 417 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
 418 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
 419
 420 static gboolean
 421 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
 422 {
 423         gboolean result = FALSE;
 424
 425         assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
 426         assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
 427
 428         arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 429         arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
 430         arg_info->pair_size [0] = 0;
 431         arg_info->pair_size [1] = 0;
 432         arg_info->nregs = 0;
 433
 434         if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
 435                 /* Pass parameter in integer register. */
 436                 arg_info->pair_storage [0] = ArgInIReg;
 437                 arg_info->pair_regs [0] = int_regs [*current_int_reg];
 438                 (*current_int_reg) ++;
 439                 result = TRUE;
 440         } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
 441                 /* Pass parameter in float register. */
 442                 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
 443                 arg_info->pair_regs [0] = float_regs [*current_float_reg];
 444                 (*current_float_reg) ++;
 445                 result = TRUE;
 446         }
 447
 448         if (result == TRUE) {
 449                 arg_info->pair_size [0] = arg_size;
 450                 arg_info->nregs = 1;
 451         }
 452
 453         return result;
 454 }
 455
 456 static inline gboolean
 457 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 458 {
 459         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
 460 }
 461
 462 static inline gboolean
 463 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 464 {
 465         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
 466 }
 467
 468 static void
 469 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
 470                                                                           guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 471 {
 472         /* Windows x64 value type ABI.
 473         *
 474         * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
 475         *
 476         * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
 477         *    Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
 478         * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 479         *    Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
 480         *
 481         * Return values:  https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
 482         *
 483         * Integers/Float types smaller than or equal to 8 bytes
 484         *    Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
 485         * Properly sized struct/unions (1,2,4,8)
 486         *    Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
 487         * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 488         *    Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
 489         */
 490
 491         assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 492
 493         if (!is_return) {
 494
 495                 /* Parameter cases. */
 496                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 497                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 498
 499                         /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
 500                         arg_info->storage = ArgValuetypeInReg;
 501                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 502                                 /* No more registers, fallback passing parameter on stack as value. */
 503                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 504
 505                                 /* Passing value directly on stack, so use size of value. */
 506                                 arg_info->storage = ArgOnStack;
 507                                 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 508                                 arg_info->offset = *stack_size;
 509                                 arg_info->arg_size = arg_size;
 510                                 *stack_size += arg_size;
 511                         }
 512                 } else {
 513                         /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
 514                         arg_info->storage = ArgValuetypeAddrInIReg;
 515                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 516                                 /* No more registers, fallback passing address to parameter on stack. */
 517                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 518
 519                                 /* Passing an address to value on stack, so use size of register as argument size. */
 520                                 arg_info->storage = ArgValuetypeAddrOnStack;
 521                                 arg_size = sizeof (mgreg_t);
 522                                 arg_info->offset = *stack_size;
 523                                 arg_info->arg_size = arg_size;
 524                                 *stack_size += arg_size;
 525                         }
 526                 }
 527         } else {
 528                 /* Return value cases. */
 529                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 530                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 531
 532                         /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
 533                         arg_info->storage = ArgValuetypeInReg;
 534                         allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 535
 536                         /* Only RAX/XMM0 should be used to return valuetype. */
 537                         assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
 538                 } else {
 539                         /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
 540                         arg_info->storage = ArgValuetypeAddrInIReg;
 541                         allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 542
 543                         /* Only RAX should be used to return valuetype address. */
 544                         assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
 545
 546                         arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 547                         arg_info->offset = *stack_size;
 548                         *stack_size += arg_size;
 549                 }
 550         }
 551 }
 552
 553 static void
 554 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
 555 {
 556         *arg_size = 0;
 557         *arg_class = ARG_CLASS_NO_CLASS;
 558
 559         assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
 560
 561         if (pinvoke) {
 562                 /* Calculate argument class type and size of marshalled type. */
 563                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 564                 *arg_size = info->native_size;
 565         } else {
 566                 /* Calculate argument class type and size of managed type. */
 567                 *arg_size = mono_class_value_size (klass, NULL);
 568         }
 569
 570         /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
 571         *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
 572
 573         if (*arg_class == ARG_CLASS_MEMORY) {
 574                 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
 575                 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
 576         }
 577
 578         /*
 579         * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
 580         * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
 581         * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
 582         * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
 583         * it must be represented in call and cannot be dropped.
 584         */
 585         if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
 586                 arg_info->pass_empty_struct = TRUE;
 587                 *arg_size = SIZEOF_REGISTER;
 588                 *arg_class = ARG_CLASS_INTEGER;
 589         }
 590
 591         assert (*arg_class != ARG_CLASS_NO_CLASS);
 592 }
 593
 594 static void
 595 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
 596                                                 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 597 {
 598         guint32 arg_size = SIZEOF_REGISTER;
 599         MonoClass *klass = NULL;
 600         ArgumentClass arg_class;
 601
 602         assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 603
 604         klass = mono_class_from_mono_type (type);
 605         get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
 606
 607         /* Only drop value type if its not an empty struct as input that must be represented in call */
 608         if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
 609                 arg_info->storage = ArgValuetypeInReg;
 610                 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 611         } else {
 612                 /* Alocate storage for value type. */
 613                 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
 614         }
 615 }
 616
 617 #endif /* TARGET_WIN32 */
 618
 619 static void
 620 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 621                            gboolean is_return,
 622                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 623 {
 624 #ifdef TARGET_WIN32
 625         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 626 #else
 627         guint32 size, quad, nquads, i, nfields;
 628         /* Keep track of the size used in each quad so we can */
 629         /* use the right size when copying args/return vars.  */
 630         guint32 quadsize [2] = {8, 8};
 631         ArgumentClass args [2];
 632         StructFieldInfo *fields = NULL;
 633         GArray *fields_array;
 634         MonoClass *klass;
 635         gboolean pass_on_stack = FALSE;
 636         int struct_size;
 637
 638         klass = mono_class_from_mono_type (type);
 639         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 640
 641         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 642                 /* We pass and return vtypes of size 8 in a register */
 643         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 644                 pass_on_stack = TRUE;
 645         }
 646
 647         /* If this struct can't be split up naturally into 8-byte */
 648         /* chunks (registers), pass it on the stack.              */
 649         if (sig->pinvoke) {
 650                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 651                 g_assert (info);
 652                 struct_size = info->native_size;
 653         } else {
 654                 struct_size = mono_class_value_size (klass, NULL);
 655         }
 656         /*
 657          * Collect field information recursively to be able to
 658          * handle nested structures.
 659          */
 660         fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
 661         collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
 662         fields = (StructFieldInfo*)fields_array->data;
 663         nfields = fields_array->len;
 664
 665         for (i = 0; i < nfields; ++i) {
 666                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 667                         pass_on_stack = TRUE;
 668                         break;
 669                 }
 670         }
 671
 672         if (size == 0) {
 673                 ainfo->storage = ArgValuetypeInReg;
 674                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 675                 return;
 676         }
 677
 678         if (pass_on_stack) {
 679                 /* Allways pass in memory */
 680                 ainfo->offset = *stack_size;
 681                 *stack_size += ALIGN_TO (size, 8);
 682                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 683                 if (!is_return)
 684                         ainfo->arg_size = ALIGN_TO (size, 8);
 685
 686                 g_array_free (fields_array, TRUE);
 687                 return;
 688         }
 689
 690         if (size > 8)
 691                 nquads = 2;
 692         else
 693                 nquads = 1;
 694
 695         if (!sig->pinvoke) {
 696                 int n = mono_class_value_size (klass, NULL);
 697
 698                 quadsize [0] = n >= 8 ? 8 : n;
 699                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 700
 701                 /* Always pass in 1 or 2 integer registers */
 702                 args [0] = ARG_CLASS_INTEGER;
 703                 args [1] = ARG_CLASS_INTEGER;
 704                 /* Only the simplest cases are supported */
 705                 if (is_return && nquads != 1) {
 706                         args [0] = ARG_CLASS_MEMORY;
 707                         args [1] = ARG_CLASS_MEMORY;
 708                 }
 709         } else {
 710                 /*
 711                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 712                  * The X87 and SSEUP stuff is left out since there are no such types in
 713                  * the CLR.
 714                  */
 715                 if (!nfields) {
 716                         ainfo->storage = ArgValuetypeInReg;
 717                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 718                         return;
 719                 }
 720
 721                 if (struct_size > 16) {
 722                         ainfo->offset = *stack_size;
 723                         *stack_size += ALIGN_TO (struct_size, 8);
 724                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 725                         if (!is_return)
 726                                 ainfo->arg_size = ALIGN_TO (struct_size, 8);
 727
 728                         g_array_free (fields_array, TRUE);
 729                         return;
 730                 }
 731
 732                 args [0] = ARG_CLASS_NO_CLASS;
 733                 args [1] = ARG_CLASS_NO_CLASS;
 734                 for (quad = 0; quad < nquads; ++quad) {
 735                         ArgumentClass class1;
 736
 737                         if (nfields == 0)
 738                                 class1 = ARG_CLASS_MEMORY;
 739                         else
 740                                 class1 = ARG_CLASS_NO_CLASS;
 741                         for (i = 0; i < nfields; ++i) {
 742                                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 743                                         /* Unaligned field */
 744                                         NOT_IMPLEMENTED;
 745                                 }
 746
 747                                 /* Skip fields in other quad */
 748                                 if ((quad == 0) && (fields [i].offset >= 8))
 749                                         continue;
 750                                 if ((quad == 1) && (fields [i].offset < 8))
 751                                         continue;
 752
 753                                 /* How far into this quad this data extends.*/
 754                                 /* (8 is size of quad) */
 755                                 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
 756
 757                                 class1 = merge_argument_class_from_type (fields [i].type, class1);
 758                         }
 759                         /* Empty structs have a nonzero size, causing this assert to be hit */
 760                         if (sig->pinvoke)
 761                                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 762                         args [quad] = class1;
 763                 }
 764         }
 765
 766         g_array_free (fields_array, TRUE);
 767
 768         /* Post merger cleanup */
 769         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 770                 args [0] = args [1] = ARG_CLASS_MEMORY;
 771
 772         /* Allocate registers */
 773         {
 774                 int orig_gr = *gr;
 775                 int orig_fr = *fr;
 776
 777                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 778                         quadsize [0] ++;
 779                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 780                         quadsize [1] ++;
 781
 782                 ainfo->storage = ArgValuetypeInReg;
 783                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 784                 g_assert (quadsize [0] <= 8);
 785                 g_assert (quadsize [1] <= 8);
 786                 ainfo->pair_size [0] = quadsize [0];
 787                 ainfo->pair_size [1] = quadsize [1];
 788                 ainfo->nregs = nquads;
 789                 for (quad = 0; quad < nquads; ++quad) {
 790                         switch (args [quad]) {
 791                         case ARG_CLASS_INTEGER:
 792                                 if (*gr >= PARAM_REGS)
 793                                         args [quad] = ARG_CLASS_MEMORY;
 794                                 else {
 795                                         ainfo->pair_storage [quad] = ArgInIReg;
 796                                         if (is_return)
 797                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 798                                         else
 799                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 800                                         (*gr) ++;
 801                                 }
 802                                 break;
 803                         case ARG_CLASS_SSE:
 804                                 if (*fr >= FLOAT_PARAM_REGS)
 805                                         args [quad] = ARG_CLASS_MEMORY;
 806                                 else {
 807                                         if (quadsize[quad] <= 4)
 808                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 809                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 810                                         ainfo->pair_regs [quad] = *fr;
 811                                         (*fr) ++;
 812                                 }
 813                                 break;
 814                         case ARG_CLASS_MEMORY:
 815                                 break;
 816                         case ARG_CLASS_NO_CLASS:
 817                                 break;
 818                         default:
 819                                 g_assert_not_reached ();
 820                         }
 821                 }
 822
 823                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 824                         int arg_size;
 825                         /* Revert possible register assignments */
 826                         *gr = orig_gr;
 827                         *fr = orig_fr;
 828
 829                         ainfo->offset = *stack_size;
 830                         if (sig->pinvoke)
 831                                 arg_size = ALIGN_TO (struct_size, 8);
 832                         else
 833                                 arg_size = nquads * sizeof(mgreg_t);
 834                         *stack_size += arg_size;
 835                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 836                         if (!is_return)
 837                                 ainfo->arg_size = arg_size;
 838                 }
 839         }
 840 #endif /* !TARGET_WIN32 */
 841 }
 842
 843 /*
 844  * get_call_info:
 845  *
 846  * Obtain information about a call according to the calling convention.
 847  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 848  * Draft Version 0.23" document for more information.
 849  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 850  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 851  */
 852 static CallInfo*
 853 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 854 {
 855         guint32 i, gr, fr, pstart;
 856         MonoType *ret_type;
 857         int n = sig->hasthis + sig->param_count;
 858         guint32 stack_size = 0;
 859         CallInfo *cinfo;
 860         gboolean is_pinvoke = sig->pinvoke;
 861
 862         if (mp)
 863                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 864         else
 865                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 866
 867         cinfo->nargs = n;
 868         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 869
 870         gr = 0;
 871         fr = 0;
 872
 873 #ifdef TARGET_WIN32
 874         /* Reserve space where the callee can save the argument registers */
 875         stack_size = 4 * sizeof (mgreg_t);
 876 #endif
 877
 878         /* return value */
 879         ret_type = mini_get_underlying_type (sig->ret);
 880         switch (ret_type->type) {
 881         case MONO_TYPE_I1:
 882         case MONO_TYPE_U1:
 883         case MONO_TYPE_I2:
 884         case MONO_TYPE_U2:
 885         case MONO_TYPE_I4:
 886         case MONO_TYPE_U4:
 887         case MONO_TYPE_I:
 888         case MONO_TYPE_U:
 889         case MONO_TYPE_PTR:
 890         case MONO_TYPE_FNPTR:
 891         case MONO_TYPE_CLASS:
 892         case MONO_TYPE_OBJECT:
 893         case MONO_TYPE_SZARRAY:
 894         case MONO_TYPE_ARRAY:
 895         case MONO_TYPE_STRING:
 896                 cinfo->ret.storage = ArgInIReg;
 897                 cinfo->ret.reg = AMD64_RAX;
 898                 break;
 899         case MONO_TYPE_U8:
 900         case MONO_TYPE_I8:
 901                 cinfo->ret.storage = ArgInIReg;
 902                 cinfo->ret.reg = AMD64_RAX;
 903                 break;
 904         case MONO_TYPE_R4:
 905                 cinfo->ret.storage = ArgInFloatSSEReg;
 906                 cinfo->ret.reg = AMD64_XMM0;
 907                 break;
 908         case MONO_TYPE_R8:
 909                 cinfo->ret.storage = ArgInDoubleSSEReg;
 910                 cinfo->ret.reg = AMD64_XMM0;
 911                 break;
 912         case MONO_TYPE_GENERICINST:
 913                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 914                         cinfo->ret.storage = ArgInIReg;
 915                         cinfo->ret.reg = AMD64_RAX;
 916                         break;
 917                 }
 918                 if (mini_is_gsharedvt_type (ret_type)) {
 919                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 920                         break;
 921                 }
 922                 /* fall through */
 923         case MONO_TYPE_VALUETYPE:
 924         case MONO_TYPE_TYPEDBYREF: {
 925                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 926
 927                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 928                 g_assert (cinfo->ret.storage != ArgInIReg);
 929                 break;
 930         }
 931         case MONO_TYPE_VAR:
 932         case MONO_TYPE_MVAR:
 933                 g_assert (mini_is_gsharedvt_type (ret_type));
 934                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 935                 break;
 936         case MONO_TYPE_VOID:
 937                 break;
 938         default:
 939                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 940         }
 941
 942         pstart = 0;
 943         /*
 944          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 945          * the first argument, allowing 'this' to be always passed in the first arg reg.
 946          * Also do this if the first argument is a reference type, since virtual calls
 947          * are sometimes made using calli without sig->hasthis set, like in the delegate
 948          * invoke wrappers.
 949          */
 950         ArgStorage ret_storage = cinfo->ret.storage;
 951         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 952                 if (sig->hasthis) {
 953                         add_general (&gr, &stack_size, cinfo->args + 0);
 954                 } else {
 955                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 956                         pstart = 1;
 957                 }
 958                 add_general (&gr, &stack_size, &cinfo->ret);
 959                 cinfo->ret.storage = ret_storage;
 960                 cinfo->vret_arg_index = 1;
 961         } else {
 962                 /* this */
 963                 if (sig->hasthis)
 964                         add_general (&gr, &stack_size, cinfo->args + 0);
 965
 966                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 967                         add_general (&gr, &stack_size, &cinfo->ret);
 968                         cinfo->ret.storage = ret_storage;
 969                 }
 970         }
 971
 972         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 973                 gr = PARAM_REGS;
 974                 fr = FLOAT_PARAM_REGS;
 975
 976                 /* Emit the signature cookie just before the implicit arguments */
 977                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 978         }
 979
 980         for (i = pstart; i < sig->param_count; ++i) {
 981                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 982                 MonoType *ptype;
 983
 984 #ifdef TARGET_WIN32
 985                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 986                 if (gr > fr)
 987                         fr = gr;
 988                 else if (fr > gr)
 989                         gr = fr;
 990 #endif
 991
 992                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 993                         /* We allways pass the sig cookie on the stack for simplicity */
 994                         /*
 995                          * Prevent implicit arguments + the sig cookie from being passed
 996                          * in registers.
 997                          */
 998                         gr = PARAM_REGS;
 999                         fr = FLOAT_PARAM_REGS;
1000
1001                         /* Emit the signature cookie just before the implicit arguments */
1002                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1003                 }
1004
1005                 ptype = mini_get_underlying_type (sig->params [i]);
1006                 switch (ptype->type) {
1007                 case MONO_TYPE_I1:
1008                 case MONO_TYPE_U1:
1009                         add_general (&gr, &stack_size, ainfo);
1010                         break;
1011                 case MONO_TYPE_I2:
1012                 case MONO_TYPE_U2:
1013                         add_general (&gr, &stack_size, ainfo);
1014                         break;
1015                 case MONO_TYPE_I4:
1016                 case MONO_TYPE_U4:
1017                         add_general (&gr, &stack_size, ainfo);
1018                         break;
1019                 case MONO_TYPE_I:
1020                 case MONO_TYPE_U:
1021                 case MONO_TYPE_PTR:
1022                 case MONO_TYPE_FNPTR:
1023                 case MONO_TYPE_CLASS:
1024                 case MONO_TYPE_OBJECT:
1025                 case MONO_TYPE_STRING:
1026                 case MONO_TYPE_SZARRAY:
1027                 case MONO_TYPE_ARRAY:
1028                         add_general (&gr, &stack_size, ainfo);
1029                         break;
1030                 case MONO_TYPE_GENERICINST:
1031                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1032                                 add_general (&gr, &stack_size, ainfo);
1033                                 break;
1034                         }
1035                         if (mini_is_gsharedvt_variable_type (ptype)) {
1036                                 /* gsharedvt arguments are passed by ref */
1037                                 add_general (&gr, &stack_size, ainfo);
1038                                 if (ainfo->storage == ArgInIReg)
1039                                         ainfo->storage = ArgGSharedVtInReg;
1040                                 else
1041                                         ainfo->storage = ArgGSharedVtOnStack;
1042                                 break;
1043                         }
1044                         /* fall through */
1045                 case MONO_TYPE_VALUETYPE:
1046                 case MONO_TYPE_TYPEDBYREF:
1047                         add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1048                         break;
1049                 case MONO_TYPE_U8:
1050
1051                 case MONO_TYPE_I8:
1052                         add_general (&gr, &stack_size, ainfo);
1053                         break;
1054                 case MONO_TYPE_R4:
1055                         add_float (&fr, &stack_size, ainfo, FALSE);
1056                         break;
1057                 case MONO_TYPE_R8:
1058                         add_float (&fr, &stack_size, ainfo, TRUE);
1059                         break;
1060                 case MONO_TYPE_VAR:
1061                 case MONO_TYPE_MVAR:
1062                         /* gsharedvt arguments are passed by ref */
1063                         g_assert (mini_is_gsharedvt_type (ptype));
1064                         add_general (&gr, &stack_size, ainfo);
1065                         if (ainfo->storage == ArgInIReg)
1066                                 ainfo->storage = ArgGSharedVtInReg;
1067                         else
1068                                 ainfo->storage = ArgGSharedVtOnStack;
1069                         break;
1070                 default:
1071                         g_assert_not_reached ();
1072                 }
1073         }
1074
1075         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1076                 gr = PARAM_REGS;
1077                 fr = FLOAT_PARAM_REGS;
1078
1079                 /* Emit the signature cookie just before the implicit arguments */
1080                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1081         }
1082
1083         cinfo->stack_usage = stack_size;
1084         cinfo->reg_usage = gr;
1085         cinfo->freg_usage = fr;
1086         return cinfo;
1087 }
1088
1089 /*
1090  * mono_arch_get_argument_info:
1091  * @csig:  a method signature
1092  * @param_count: the number of parameters to consider
1093  * @arg_info: an array to store the result infos
1094  *
1095  * Gathers information on parameters such as size, alignment and
1096  * padding. arg_info should be large enought to hold param_count + 1 entries.
1097  *
1098  * Returns the size of the argument area on the stack.
1099  */
1100 int
1101 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1102 {
1103         int k;
1104         CallInfo *cinfo = get_call_info (NULL, csig);
1105         guint32 args_size = cinfo->stack_usage;
1106
1107         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1108         if (csig->hasthis) {
1109                 arg_info [0].offset = 0;
1110         }
1111
1112         for (k = 0; k < param_count; k++) {
1113                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1114                 /* FIXME: */
1115                 arg_info [k + 1].size = 0;
1116         }
1117
1118         g_free (cinfo);
1119
1120         return args_size;
1121 }
1122
1123 gboolean
1124 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1125 {
1126         CallInfo *c1, *c2;
1127         gboolean res;
1128         MonoType *callee_ret;
1129
1130         c1 = get_call_info (NULL, caller_sig);
1131         c2 = get_call_info (NULL, callee_sig);
1132         res = c1->stack_usage >= c2->stack_usage;
1133         callee_ret = mini_get_underlying_type (callee_sig->ret);
1134         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1135                 /* An address on the callee's stack is passed as the first argument */
1136                 res = FALSE;
1137
1138         g_free (c1);
1139         g_free (c2);
1140
1141         return res;
1142 }
1143
1144 /*
1145  * Initialize the cpu to execute managed code.
1146  */
1147 void
1148 mono_arch_cpu_init (void)
1149 {
1150 #ifndef _MSC_VER
1151         guint16 fpcw;
1152
1153         /* spec compliance requires running with double precision */
1154         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1155         fpcw &= ~X86_FPCW_PRECC_MASK;
1156         fpcw |= X86_FPCW_PREC_DOUBLE;
1157         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1158         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1159 #else
1160         /* TODO: This is crashing on Win64 right now.
1161         * _control87 (_PC_53, MCW_PC);
1162         */
1163 #endif
1164 }
1165
1166 /*
1167  * Initialize architecture specific code.
1168  */
1169 void
1170 mono_arch_init (void)
1171 {
1172         mono_os_mutex_init_recursive (&mini_arch_mutex);
1173
1174         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1175         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1176         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1177         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1178         mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1179
1180 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1181         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1182 #endif
1183
1184         if (!mono_aot_only)
1185                 bp_trampoline = mini_get_breakpoint_trampoline ();
1186 }
1187
1188 /*
1189  * Cleanup architecture specific code.
1190  */
1191 void
1192 mono_arch_cleanup (void)
1193 {
1194         mono_os_mutex_destroy (&mini_arch_mutex);
1195 }
1196
1197 /*
1198  * This function returns the optimizations supported on this cpu.
1199  */
1200 guint32
1201 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1202 {
1203         guint32 opts = 0;
1204
1205         *exclude_mask = 0;
1206
1207         if (mono_hwcap_x86_has_cmov) {
1208                 opts |= MONO_OPT_CMOV;
1209
1210                 if (mono_hwcap_x86_has_fcmov)
1211                         opts |= MONO_OPT_FCMOV;
1212                 else
1213                         *exclude_mask |= MONO_OPT_FCMOV;
1214         } else {
1215                 *exclude_mask |= MONO_OPT_CMOV;
1216         }
1217
1218 #ifdef TARGET_WIN32
1219         /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1220         /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1221         /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1222         /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1223         /* will now have a reference to an argument that won't be fully decomposed. */
1224         *exclude_mask |= MONO_OPT_SIMD;
1225 #endif
1226
1227         return opts;
1228 }
1229
1230 /*
1231  * This function test for all SSE functions supported.
1232  *
1233  * Returns a bitmask corresponding to all supported versions.
1234  *
1235  */
1236 guint32
1237 mono_arch_cpu_enumerate_simd_versions (void)
1238 {
1239         guint32 sse_opts = 0;
1240
1241         if (mono_hwcap_x86_has_sse1)
1242                 sse_opts |= SIMD_VERSION_SSE1;
1243
1244         if (mono_hwcap_x86_has_sse2)
1245                 sse_opts |= SIMD_VERSION_SSE2;
1246
1247         if (mono_hwcap_x86_has_sse3)
1248                 sse_opts |= SIMD_VERSION_SSE3;
1249
1250         if (mono_hwcap_x86_has_ssse3)
1251                 sse_opts |= SIMD_VERSION_SSSE3;
1252
1253         if (mono_hwcap_x86_has_sse41)
1254                 sse_opts |= SIMD_VERSION_SSE41;
1255
1256         if (mono_hwcap_x86_has_sse42)
1257                 sse_opts |= SIMD_VERSION_SSE42;
1258
1259         if (mono_hwcap_x86_has_sse4a)
1260                 sse_opts |= SIMD_VERSION_SSE4a;
1261
1262         return sse_opts;
1263 }
1264
1265 #ifndef DISABLE_JIT
1266
1267 GList *
1268 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1269 {
1270         GList *vars = NULL;
1271         int i;
1272
1273         for (i = 0; i < cfg->num_varinfo; i++) {
1274                 MonoInst *ins = cfg->varinfo [i];
1275                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1276
1277                 /* unused vars */
1278                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1279                         continue;
1280
1281                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1282                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1283                         continue;
1284
1285                 if (mono_is_regsize_var (ins->inst_vtype)) {
1286                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1287                         g_assert (i == vmv->idx);
1288                         vars = g_list_prepend (vars, vmv);
1289                 }
1290         }
1291
1292         vars = mono_varlist_sort (cfg, vars, 0);
1293
1294         return vars;
1295 }
1296
1297 /**
1298  * mono_arch_compute_omit_fp:
1299  *
1300  *   Determine whenever the frame pointer can be eliminated.
1301  */
1302 static void
1303 mono_arch_compute_omit_fp (MonoCompile *cfg)
1304 {
1305         MonoMethodSignature *sig;
1306         MonoMethodHeader *header;
1307         int i, locals_size;
1308         CallInfo *cinfo;
1309
1310         if (cfg->arch.omit_fp_computed)
1311                 return;
1312
1313         header = cfg->header;
1314
1315         sig = mono_method_signature (cfg->method);
1316
1317         if (!cfg->arch.cinfo)
1318                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1319         cinfo = (CallInfo *)cfg->arch.cinfo;
1320
1321         /*
1322          * FIXME: Remove some of the restrictions.
1323          */
1324         cfg->arch.omit_fp = TRUE;
1325         cfg->arch.omit_fp_computed = TRUE;
1326
1327         if (cfg->disable_omit_fp)
1328                 cfg->arch.omit_fp = FALSE;
1329
1330         if (!debug_omit_fp ())
1331                 cfg->arch.omit_fp = FALSE;
1332         /*
1333         if (cfg->method->save_lmf)
1334                 cfg->arch.omit_fp = FALSE;
1335         */
1336         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1337                 cfg->arch.omit_fp = FALSE;
1338         if (header->num_clauses)
1339                 cfg->arch.omit_fp = FALSE;
1340         if (cfg->param_area)
1341                 cfg->arch.omit_fp = FALSE;
1342         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1343                 cfg->arch.omit_fp = FALSE;
1344         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1345                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1346                 cfg->arch.omit_fp = FALSE;
1347         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1348                 ArgInfo *ainfo = &cinfo->args [i];
1349
1350                 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1351                         /*
1352                          * The stack offset can only be determined when the frame
1353                          * size is known.
1354                          */
1355                         cfg->arch.omit_fp = FALSE;
1356                 }
1357         }
1358
1359         locals_size = 0;
1360         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1361                 MonoInst *ins = cfg->varinfo [i];
1362                 int ialign;
1363
1364                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1365         }
1366 }
1367
1368 GList *
1369 mono_arch_get_global_int_regs (MonoCompile *cfg)
1370 {
1371         GList *regs = NULL;
1372
1373         mono_arch_compute_omit_fp (cfg);
1374
1375         if (cfg->arch.omit_fp)
1376                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1377
1378         /* We use the callee saved registers for global allocation */
1379         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1380         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1381         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1382         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1383         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1384 #ifdef TARGET_WIN32
1385         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1386         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1387 #endif
1388
1389         return regs;
1390 }
1391
1392 GList*
1393 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1394 {
1395         GList *regs = NULL;
1396         int i;
1397
1398         /* All XMM registers */
1399         for (i = 0; i < 16; ++i)
1400                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1401
1402         return regs;
1403 }
1404
1405 GList*
1406 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1407 {
1408         static GList *r = NULL;
1409
1410         if (r == NULL) {
1411                 GList *regs = NULL;
1412
1413                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1414                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1415                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1416                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1417                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1418                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1419
1420                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1421                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1422                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1423                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1424                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1425                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1426                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1427                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1428
1429                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1430         }
1431
1432         return r;
1433 }
1434
1435 GList*
1436 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1437 {
1438         int i;
1439         static GList *r = NULL;
1440
1441         if (r == NULL) {
1442                 GList *regs = NULL;
1443
1444                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1445                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1446
1447                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1448         }
1449
1450         return r;
1451 }
1452
1453 /*
1454  * mono_arch_regalloc_cost:
1455  *
1456  *  Return the cost, in number of memory references, of the action of
1457  * allocating the variable VMV into a register during global register
1458  * allocation.
1459  */
1460 guint32
1461 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1462 {
1463         MonoInst *ins = cfg->varinfo [vmv->idx];
1464
1465         if (cfg->method->save_lmf)
1466                 /* The register is already saved */
1467                 /* substract 1 for the invisible store in the prolog */
1468                 return (ins->opcode == OP_ARG) ? 0 : 1;
1469         else
1470                 /* push+pop */
1471                 return (ins->opcode == OP_ARG) ? 1 : 2;
1472 }
1473
1474 /*
1475  * mono_arch_fill_argument_info:
1476  *
1477  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1478  * of the method.
1479  */
1480 void
1481 mono_arch_fill_argument_info (MonoCompile *cfg)
1482 {
1483         MonoType *sig_ret;
1484         MonoMethodSignature *sig;
1485         MonoInst *ins;
1486         int i;
1487         CallInfo *cinfo;
1488
1489         sig = mono_method_signature (cfg->method);
1490
1491         cinfo = (CallInfo *)cfg->arch.cinfo;
1492         sig_ret = mini_get_underlying_type (sig->ret);
1493
1494         /*
1495          * Contrary to mono_arch_allocate_vars (), the information should describe
1496          * where the arguments are at the beginning of the method, not where they can be
1497          * accessed during the execution of the method. The later makes no sense for the
1498          * global register allocator, since a variable can be in more than one location.
1499          */
1500         switch (cinfo->ret.storage) {
1501         case ArgInIReg:
1502         case ArgInFloatSSEReg:
1503         case ArgInDoubleSSEReg:
1504                 cfg->ret->opcode = OP_REGVAR;
1505                 cfg->ret->inst_c0 = cinfo->ret.reg;
1506                 break;
1507         case ArgValuetypeInReg:
1508                 cfg->ret->opcode = OP_REGOFFSET;
1509                 cfg->ret->inst_basereg = -1;
1510                 cfg->ret->inst_offset = -1;
1511                 break;
1512         case ArgNone:
1513                 break;
1514         default:
1515                 g_assert_not_reached ();
1516         }
1517
1518         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1519                 ArgInfo *ainfo = &cinfo->args [i];
1520
1521                 ins = cfg->args [i];
1522
1523                 switch (ainfo->storage) {
1524                 case ArgInIReg:
1525                 case ArgInFloatSSEReg:
1526                 case ArgInDoubleSSEReg:
1527                         ins->opcode = OP_REGVAR;
1528                         ins->inst_c0 = ainfo->reg;
1529                         break;
1530                 case ArgOnStack:
1531                         ins->opcode = OP_REGOFFSET;
1532                         ins->inst_basereg = -1;
1533                         ins->inst_offset = -1;
1534                         break;
1535                 case ArgValuetypeInReg:
1536                         /* Dummy */
1537                         ins->opcode = OP_NOP;
1538                         break;
1539                 default:
1540                         g_assert_not_reached ();
1541                 }
1542         }
1543 }
1544
1545 void
1546 mono_arch_allocate_vars (MonoCompile *cfg)
1547 {
1548         MonoType *sig_ret;
1549         MonoMethodSignature *sig;
1550         MonoInst *ins;
1551         int i, offset;
1552         guint32 locals_stack_size, locals_stack_align;
1553         gint32 *offsets;
1554         CallInfo *cinfo;
1555
1556         sig = mono_method_signature (cfg->method);
1557
1558         cinfo = (CallInfo *)cfg->arch.cinfo;
1559         sig_ret = mini_get_underlying_type (sig->ret);
1560
1561         mono_arch_compute_omit_fp (cfg);
1562
1563         /*
1564          * We use the ABI calling conventions for managed code as well.
1565          * Exception: valuetypes are only sometimes passed or returned in registers.
1566          */
1567
1568         /*
1569          * The stack looks like this:
1570          * <incoming arguments passed on the stack>
1571          * <return value>
1572          * <lmf/caller saved registers>
1573          * <locals>
1574          * <spill area>
1575          * <localloc area>  -> grows dynamically
1576          * <params area>
1577          */
1578
1579         if (cfg->arch.omit_fp) {
1580                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1581                 cfg->frame_reg = AMD64_RSP;
1582                 offset = 0;
1583         } else {
1584                 /* Locals are allocated backwards from %fp */
1585                 cfg->frame_reg = AMD64_RBP;
1586                 offset = 0;
1587         }
1588
1589         cfg->arch.saved_iregs = cfg->used_int_regs;
1590         if (cfg->method->save_lmf) {
1591                 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1592                 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1593                 cfg->arch.saved_iregs |= iregs_to_save;
1594         }
1595
1596         if (cfg->arch.omit_fp)
1597                 cfg->arch.reg_save_area_offset = offset;
1598         /* Reserve space for callee saved registers */
1599         for (i = 0; i < AMD64_NREG; ++i)
1600                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1601                         offset += sizeof(mgreg_t);
1602                 }
1603         if (!cfg->arch.omit_fp)
1604                 cfg->arch.reg_save_area_offset = -offset;
1605
1606         if (sig_ret->type != MONO_TYPE_VOID) {
1607                 switch (cinfo->ret.storage) {
1608                 case ArgInIReg:
1609                 case ArgInFloatSSEReg:
1610                 case ArgInDoubleSSEReg:
1611                         cfg->ret->opcode = OP_REGVAR;
1612                         cfg->ret->inst_c0 = cinfo->ret.reg;
1613                         cfg->ret->dreg = cinfo->ret.reg;
1614                         break;
1615                 case ArgValuetypeAddrInIReg:
1616                 case ArgGsharedvtVariableInReg:
1617                         /* The register is volatile */
1618                         cfg->vret_addr->opcode = OP_REGOFFSET;
1619                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1620                         if (cfg->arch.omit_fp) {
1621                                 cfg->vret_addr->inst_offset = offset;
1622                                 offset += 8;
1623                         } else {
1624                                 offset += 8;
1625                                 cfg->vret_addr->inst_offset = -offset;
1626                         }
1627                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1628                                 printf ("vret_addr =");
1629                                 mono_print_ins (cfg->vret_addr);
1630                         }
1631                         break;
1632                 case ArgValuetypeInReg:
1633                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1634                         cfg->ret->opcode = OP_REGOFFSET;
1635                         cfg->ret->inst_basereg = cfg->frame_reg;
1636                         if (cfg->arch.omit_fp) {
1637                                 cfg->ret->inst_offset = offset;
1638                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1639                         } else {
1640                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1641                                 cfg->ret->inst_offset = - offset;
1642                         }
1643                         break;
1644                 default:
1645                         g_assert_not_reached ();
1646                 }
1647         }
1648
1649         /* Allocate locals */
1650         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1651         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1652                 char *mname = mono_method_full_name (cfg->method, TRUE);
1653                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1654                 g_free (mname);
1655                 return;
1656         }
1657
1658         if (locals_stack_align) {
1659                 offset += (locals_stack_align - 1);
1660                 offset &= ~(locals_stack_align - 1);
1661         }
1662         if (cfg->arch.omit_fp) {
1663                 cfg->locals_min_stack_offset = offset;
1664                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1665         } else {
1666                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1667                 cfg->locals_max_stack_offset = - offset;
1668         }
1669
1670         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1671                 if (offsets [i] != -1) {
1672                         MonoInst *ins = cfg->varinfo [i];
1673                         ins->opcode = OP_REGOFFSET;
1674                         ins->inst_basereg = cfg->frame_reg;
1675                         if (cfg->arch.omit_fp)
1676                                 ins->inst_offset = (offset + offsets [i]);
1677                         else
1678                                 ins->inst_offset = - (offset + offsets [i]);
1679                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1680                 }
1681         }
1682         offset += locals_stack_size;
1683
1684         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1685                 g_assert (!cfg->arch.omit_fp);
1686                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1687                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1688         }
1689
1690         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1691                 ins = cfg->args [i];
1692                 if (ins->opcode != OP_REGVAR) {
1693                         ArgInfo *ainfo = &cinfo->args [i];
1694                         gboolean inreg = TRUE;
1695
1696                         /* FIXME: Allocate volatile arguments to registers */
1697                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1698                                 inreg = FALSE;
1699
1700                         /*
1701                          * Under AMD64, all registers used to pass arguments to functions
1702                          * are volatile across calls.
1703                          * FIXME: Optimize this.
1704                          */
1705                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1706                                 inreg = FALSE;
1707
1708                         ins->opcode = OP_REGOFFSET;
1709
1710                         switch (ainfo->storage) {
1711                         case ArgInIReg:
1712                         case ArgInFloatSSEReg:
1713                         case ArgInDoubleSSEReg:
1714                         case ArgGSharedVtInReg:
1715                                 if (inreg) {
1716                                         ins->opcode = OP_REGVAR;
1717                                         ins->dreg = ainfo->reg;
1718                                 }
1719                                 break;
1720                         case ArgOnStack:
1721                         case ArgGSharedVtOnStack:
1722                                 g_assert (!cfg->arch.omit_fp);
1723                                 ins->opcode = OP_REGOFFSET;
1724                                 ins->inst_basereg = cfg->frame_reg;
1725                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1726                                 break;
1727                         case ArgValuetypeInReg:
1728                                 break;
1729                         case ArgValuetypeAddrInIReg:
1730                         case ArgValuetypeAddrOnStack: {
1731                                 MonoInst *indir;
1732                                 g_assert (!cfg->arch.omit_fp);
1733                                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1734                                 MONO_INST_NEW (cfg, indir, 0);
1735
1736                                 indir->opcode = OP_REGOFFSET;
1737                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1738                                         indir->inst_basereg = cfg->frame_reg;
1739                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1740                                         offset += (sizeof (gpointer));
1741                                         indir->inst_offset = - offset;
1742                                 }
1743                                 else {
1744                                         indir->inst_basereg = cfg->frame_reg;
1745                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1746                                 }
1747
1748                                 ins->opcode = OP_VTARG_ADDR;
1749                                 ins->inst_left = indir;
1750
1751                                 break;
1752                         }
1753                         default:
1754                                 NOT_IMPLEMENTED;
1755                         }
1756
1757                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1758                                 ins->opcode = OP_REGOFFSET;
1759                                 ins->inst_basereg = cfg->frame_reg;
1760                                 /* These arguments are saved to the stack in the prolog */
1761                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1762                                 if (cfg->arch.omit_fp) {
1763                                         ins->inst_offset = offset;
1764                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1765                                         // Arguments are yet supported by the stack map creation code
1766                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1767                                 } else {
1768                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1769                                         ins->inst_offset = - offset;
1770                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1771                                 }
1772                         }
1773                 }
1774         }
1775
1776         cfg->stack_offset = offset;
1777 }
1778
1779 void
1780 mono_arch_create_vars (MonoCompile *cfg)
1781 {
1782         MonoMethodSignature *sig;
1783         CallInfo *cinfo;
1784         MonoType *sig_ret;
1785
1786         sig = mono_method_signature (cfg->method);
1787
1788         if (!cfg->arch.cinfo)
1789                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1790         cinfo = (CallInfo *)cfg->arch.cinfo;
1791
1792         if (cinfo->ret.storage == ArgValuetypeInReg)
1793                 cfg->ret_var_is_local = TRUE;
1794
1795         sig_ret = mini_get_underlying_type (sig->ret);
1796         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1797                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1798                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1799                         printf ("vret_addr = ");
1800                         mono_print_ins (cfg->vret_addr);
1801                 }
1802         }
1803
1804         if (cfg->gen_sdb_seq_points) {
1805                 MonoInst *ins;
1806
1807                 if (cfg->compile_aot) {
1808                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1809                         ins->flags |= MONO_INST_VOLATILE;
1810                         cfg->arch.seq_point_info_var = ins;
1811                 }
1812                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1813                 ins->flags |= MONO_INST_VOLATILE;
1814                 cfg->arch.ss_tramp_var = ins;
1815
1816                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1817                 ins->flags |= MONO_INST_VOLATILE;
1818                 cfg->arch.bp_tramp_var = ins;
1819         }
1820
1821         if (cfg->method->save_lmf)
1822                 cfg->create_lmf_var = TRUE;
1823
1824         if (cfg->method->save_lmf) {
1825                 cfg->lmf_ir = TRUE;
1826 #if !defined(TARGET_WIN32)
1827                 if (!optimize_for_xen)
1828                         cfg->lmf_ir_mono_lmf = TRUE;
1829 #endif
1830         }
1831 }
1832
1833 static void
1834 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1835 {
1836         MonoInst *ins;
1837
1838         switch (storage) {
1839         case ArgInIReg:
1840                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1841                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1842                 ins->sreg1 = tree->dreg;
1843                 MONO_ADD_INS (cfg->cbb, ins);
1844                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1845                 break;
1846         case ArgInFloatSSEReg:
1847                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1848                 ins->dreg = mono_alloc_freg (cfg);
1849                 ins->sreg1 = tree->dreg;
1850                 MONO_ADD_INS (cfg->cbb, ins);
1851
1852                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1853                 break;
1854         case ArgInDoubleSSEReg:
1855                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1856                 ins->dreg = mono_alloc_freg (cfg);
1857                 ins->sreg1 = tree->dreg;
1858                 MONO_ADD_INS (cfg->cbb, ins);
1859
1860                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1861
1862                 break;
1863         default:
1864                 g_assert_not_reached ();
1865         }
1866 }
1867
1868 static int
1869 arg_storage_to_load_membase (ArgStorage storage)
1870 {
1871         switch (storage) {
1872         case ArgInIReg:
1873 #if defined(__mono_ilp32__)
1874                 return OP_LOADI8_MEMBASE;
1875 #else
1876                 return OP_LOAD_MEMBASE;
1877 #endif
1878         case ArgInDoubleSSEReg:
1879                 return OP_LOADR8_MEMBASE;
1880         case ArgInFloatSSEReg:
1881                 return OP_LOADR4_MEMBASE;
1882         default:
1883                 g_assert_not_reached ();
1884         }
1885
1886         return -1;
1887 }
1888
1889 static void
1890 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1891 {
1892         MonoMethodSignature *tmp_sig;
1893         int sig_reg;
1894
1895         if (call->tail_call)
1896                 NOT_IMPLEMENTED;
1897
1898         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1899
1900         /*
1901          * mono_ArgIterator_Setup assumes the signature cookie is
1902          * passed first and all the arguments which were before it are
1903          * passed on the stack after the signature. So compensate by
1904          * passing a different signature.
1905          */
1906         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1907         tmp_sig->param_count -= call->signature->sentinelpos;
1908         tmp_sig->sentinelpos = 0;
1909         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1910
1911         sig_reg = mono_alloc_ireg (cfg);
1912         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1913
1914         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1915 }
1916
1917 #ifdef ENABLE_LLVM
1918 static inline LLVMArgStorage
1919 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1920 {
1921         switch (storage) {
1922         case ArgInIReg:
1923                 return LLVMArgInIReg;
1924         case ArgNone:
1925                 return LLVMArgNone;
1926         case ArgGSharedVtInReg:
1927         case ArgGSharedVtOnStack:
1928                 return LLVMArgGSharedVt;
1929         default:
1930                 g_assert_not_reached ();
1931                 return LLVMArgNone;
1932         }
1933 }
1934
1935 LLVMCallInfo*
1936 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1937 {
1938         int i, n;
1939         CallInfo *cinfo;
1940         ArgInfo *ainfo;
1941         int j;
1942         LLVMCallInfo *linfo;
1943         MonoType *t, *sig_ret;
1944
1945         n = sig->param_count + sig->hasthis;
1946         sig_ret = mini_get_underlying_type (sig->ret);
1947
1948         cinfo = get_call_info (cfg->mempool, sig);
1949
1950         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1951
1952         /*
1953          * LLVM always uses the native ABI while we use our own ABI, the
1954          * only difference is the handling of vtypes:
1955          * - we only pass/receive them in registers in some cases, and only
1956          *   in 1 or 2 integer registers.
1957          */
1958         switch (cinfo->ret.storage) {
1959         case ArgNone:
1960                 linfo->ret.storage = LLVMArgNone;
1961                 break;
1962         case ArgInIReg:
1963         case ArgInFloatSSEReg:
1964         case ArgInDoubleSSEReg:
1965                 linfo->ret.storage = LLVMArgNormal;
1966                 break;
1967         case ArgValuetypeInReg: {
1968                 ainfo = &cinfo->ret;
1969
1970                 if (sig->pinvoke &&
1971                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1972                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1973                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1974                         cfg->disable_llvm = TRUE;
1975                         return linfo;
1976                 }
1977
1978                 linfo->ret.storage = LLVMArgVtypeInReg;
1979                 for (j = 0; j < 2; ++j)
1980                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1981                 break;
1982         }
1983         case ArgValuetypeAddrInIReg:
1984         case ArgGsharedvtVariableInReg:
1985                 /* Vtype returned using a hidden argument */
1986                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1987                 linfo->vret_arg_index = cinfo->vret_arg_index;
1988                 break;
1989         default:
1990                 g_assert_not_reached ();
1991                 break;
1992         }
1993
1994         for (i = 0; i < n; ++i) {
1995                 ainfo = cinfo->args + i;
1996
1997                 if (i >= sig->hasthis)
1998                         t = sig->params [i - sig->hasthis];
1999                 else
2000                         t = &mono_defaults.int_class->byval_arg;
2001                 t = mini_type_get_underlying_type (t);
2002
2003                 linfo->args [i].storage = LLVMArgNone;
2004
2005                 switch (ainfo->storage) {
2006                 case ArgInIReg:
2007                         linfo->args [i].storage = LLVMArgNormal;
2008                         break;
2009                 case ArgInDoubleSSEReg:
2010                 case ArgInFloatSSEReg:
2011                         linfo->args [i].storage = LLVMArgNormal;
2012                         break;
2013                 case ArgOnStack:
2014                         if (MONO_TYPE_ISSTRUCT (t))
2015                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2016                         else
2017                                 linfo->args [i].storage = LLVMArgNormal;
2018                         break;
2019                 case ArgValuetypeInReg:
2020                         if (sig->pinvoke &&
2021                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2022                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2023                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2024                                 cfg->disable_llvm = TRUE;
2025                                 return linfo;
2026                         }
2027
2028                         linfo->args [i].storage = LLVMArgVtypeInReg;
2029                         for (j = 0; j < 2; ++j)
2030                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2031                         break;
2032                 case ArgGSharedVtInReg:
2033                 case ArgGSharedVtOnStack:
2034                         linfo->args [i].storage = LLVMArgGSharedVt;
2035                         break;
2036                 default:
2037                         cfg->exception_message = g_strdup ("ainfo->storage");
2038                         cfg->disable_llvm = TRUE;
2039                         break;
2040                 }
2041         }
2042
2043         return linfo;
2044 }
2045 #endif
2046
2047 void
2048 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2049 {
2050         MonoInst *arg, *in;
2051         MonoMethodSignature *sig;
2052         MonoType *sig_ret;
2053         int i, n;
2054         CallInfo *cinfo;
2055         ArgInfo *ainfo;
2056
2057         sig = call->signature;
2058         n = sig->param_count + sig->hasthis;
2059
2060         cinfo = get_call_info (cfg->mempool, sig);
2061
2062         sig_ret = sig->ret;
2063
2064         if (COMPILE_LLVM (cfg)) {
2065                 /* We shouldn't be called in the llvm case */
2066                 cfg->disable_llvm = TRUE;
2067                 return;
2068         }
2069
2070         /*
2071          * Emit all arguments which are passed on the stack to prevent register
2072          * allocation problems.
2073          */
2074         for (i = 0; i < n; ++i) {
2075                 MonoType *t;
2076                 ainfo = cinfo->args + i;
2077
2078                 in = call->args [i];
2079
2080                 if (sig->hasthis && i == 0)
2081                         t = &mono_defaults.object_class->byval_arg;
2082                 else
2083                         t = sig->params [i - sig->hasthis];
2084
2085                 t = mini_get_underlying_type (t);
2086                 //XXX what about ArgGSharedVtOnStack here?
2087                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2088                         if (!t->byref) {
2089                                 if (t->type == MONO_TYPE_R4)
2090                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2091                                 else if (t->type == MONO_TYPE_R8)
2092                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2093                                 else
2094                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2095                         } else {
2096                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2097                         }
2098                         if (cfg->compute_gc_maps) {
2099                                 MonoInst *def;
2100
2101                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2102                         }
2103                 }
2104         }
2105
2106         /*
2107          * Emit all parameters passed in registers in non-reverse order for better readability
2108          * and to help the optimization in emit_prolog ().
2109          */
2110         for (i = 0; i < n; ++i) {
2111                 ainfo = cinfo->args + i;
2112
2113                 in = call->args [i];
2114
2115                 if (ainfo->storage == ArgInIReg)
2116                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2117         }
2118
2119         for (i = n - 1; i >= 0; --i) {
2120                 MonoType *t;
2121
2122                 ainfo = cinfo->args + i;
2123
2124                 in = call->args [i];
2125
2126                 if (sig->hasthis && i == 0)
2127                         t = &mono_defaults.object_class->byval_arg;
2128                 else
2129                         t = sig->params [i - sig->hasthis];
2130                 t = mini_get_underlying_type (t);
2131
2132                 switch (ainfo->storage) {
2133                 case ArgInIReg:
2134                         /* Already done */
2135                         break;
2136                 case ArgInFloatSSEReg:
2137                 case ArgInDoubleSSEReg:
2138                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2139                         break;
2140                 case ArgOnStack:
2141                 case ArgValuetypeInReg:
2142                 case ArgValuetypeAddrInIReg:
2143                 case ArgValuetypeAddrOnStack:
2144                 case ArgGSharedVtInReg:
2145                 case ArgGSharedVtOnStack: {
2146                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2147                                 /* Already emitted above */
2148                                 break;
2149                         //FIXME what about ArgGSharedVtOnStack ?
2150                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2151                                 MonoInst *call_inst = (MonoInst*)call;
2152                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2153                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2154                                 break;
2155                         }
2156
2157                         guint32 align;
2158                         guint32 size;
2159
2160                         if (sig->pinvoke)
2161                                 size = mono_type_native_stack_size (t, &align);
2162                         else {
2163                                 /*
2164                                  * Other backends use mono_type_stack_size (), but that
2165                                  * aligns the size to 8, which is larger than the size of
2166                                  * the source, leading to reads of invalid memory if the
2167                                  * source is at the end of address space.
2168                                  */
2169                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2170                         }
2171
2172                         if (size >= 10000) {
2173                                 /* Avoid asserts in emit_memcpy () */
2174                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2175                                 /* Continue normally */
2176                         }
2177
2178                         if (size > 0 || ainfo->pass_empty_struct) {
2179                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2180                                 arg->sreg1 = in->dreg;
2181                                 arg->klass = mono_class_from_mono_type (t);
2182                                 arg->backend.size = size;
2183                                 arg->inst_p0 = call;
2184                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2185                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2186
2187                                 MONO_ADD_INS (cfg->cbb, arg);
2188                         }
2189                         break;
2190                 }
2191                 default:
2192                         g_assert_not_reached ();
2193                 }
2194
2195                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2196                         /* Emit the signature cookie just before the implicit arguments */
2197                         emit_sig_cookie (cfg, call, cinfo);
2198         }
2199
2200         /* Handle the case where there are no implicit arguments */
2201         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2202                 emit_sig_cookie (cfg, call, cinfo);
2203
2204         switch (cinfo->ret.storage) {
2205         case ArgValuetypeInReg:
2206                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2207                         /*
2208                          * Tell the JIT to use a more efficient calling convention: call using
2209                          * OP_CALL, compute the result location after the call, and save the
2210                          * result there.
2211                          */
2212                         call->vret_in_reg = TRUE;
2213                         /*
2214                          * Nullify the instruction computing the vret addr to enable
2215                          * future optimizations.
2216                          */
2217                         if (call->vret_var)
2218                                 NULLIFY_INS (call->vret_var);
2219                 } else {
2220                         if (call->tail_call)
2221                                 NOT_IMPLEMENTED;
2222                         /*
2223                          * The valuetype is in RAX:RDX after the call, need to be copied to
2224                          * the stack. Push the address here, so the call instruction can
2225                          * access it.
2226                          */
2227                         if (!cfg->arch.vret_addr_loc) {
2228                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2229                                 /* Prevent it from being register allocated or optimized away */
2230                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2231                         }
2232
2233                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2234                 }
2235                 break;
2236         case ArgValuetypeAddrInIReg:
2237         case ArgGsharedvtVariableInReg: {
2238                 MonoInst *vtarg;
2239                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2240                 vtarg->sreg1 = call->vret_var->dreg;
2241                 vtarg->dreg = mono_alloc_preg (cfg);
2242                 MONO_ADD_INS (cfg->cbb, vtarg);
2243
2244                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2245                 break;
2246         }
2247         default:
2248                 break;
2249         }
2250
2251         if (cfg->method->save_lmf) {
2252                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2253                 MONO_ADD_INS (cfg->cbb, arg);
2254         }
2255
2256         call->stack_usage = cinfo->stack_usage;
2257 }
2258
2259 void
2260 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2261 {
2262         MonoInst *arg;
2263         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2264         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2265         int size = ins->backend.size;
2266
2267         switch (ainfo->storage) {
2268         case ArgValuetypeInReg: {
2269                 MonoInst *load;
2270                 int part;
2271
2272                 for (part = 0; part < 2; ++part) {
2273                         if (ainfo->pair_storage [part] == ArgNone)
2274                                 continue;
2275
2276                         if (ainfo->pass_empty_struct) {
2277                                 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2278                                 NEW_ICONST (cfg, load, 0);
2279                         }
2280                         else {
2281                                 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2282                                 load->inst_basereg = src->dreg;
2283                                 load->inst_offset = part * sizeof(mgreg_t);
2284
2285                                 switch (ainfo->pair_storage [part]) {
2286                                 case ArgInIReg:
2287                                         load->dreg = mono_alloc_ireg (cfg);
2288                                         break;
2289                                 case ArgInDoubleSSEReg:
2290                                 case ArgInFloatSSEReg:
2291                                         load->dreg = mono_alloc_freg (cfg);
2292                                         break;
2293                                 default:
2294                                         g_assert_not_reached ();
2295                                 }
2296                         }
2297
2298                         MONO_ADD_INS (cfg->cbb, load);
2299
2300                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2301                 }
2302                 break;
2303         }
2304         case ArgValuetypeAddrInIReg:
2305         case ArgValuetypeAddrOnStack: {
2306                 MonoInst *vtaddr, *load;
2307
2308                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2309
2310                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2311
2312                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2313                 cfg->has_indirection = TRUE;
2314                 load->inst_p0 = vtaddr;
2315                 vtaddr->flags |= MONO_INST_INDIRECT;
2316                 load->type = STACK_MP;
2317                 load->klass = vtaddr->klass;
2318                 load->dreg = mono_alloc_ireg (cfg);
2319                 MONO_ADD_INS (cfg->cbb, load);
2320                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2321
2322                 if (ainfo->pair_storage [0] == ArgInIReg) {
2323                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2324                         arg->dreg = mono_alloc_ireg (cfg);
2325                         arg->sreg1 = load->dreg;
2326                         arg->inst_imm = 0;
2327                         MONO_ADD_INS (cfg->cbb, arg);
2328                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2329                 } else {
2330                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2331                 }
2332                 break;
2333         }
2334         case ArgGSharedVtInReg:
2335                 /* Pass by addr */
2336                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2337                 break;
2338         case ArgGSharedVtOnStack:
2339                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2340                 break;
2341         default:
2342                 if (size == 8) {
2343                         int dreg = mono_alloc_ireg (cfg);
2344
2345                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2346                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2347                 } else if (size <= 40) {
2348                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2349                 } else {
2350                         // FIXME: Code growth
2351                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2352                 }
2353
2354                 if (cfg->compute_gc_maps) {
2355                         MonoInst *def;
2356                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2357                 }
2358         }
2359 }
2360
2361 void
2362 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2363 {
2364         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2365
2366         if (ret->type == MONO_TYPE_R4) {
2367                 if (COMPILE_LLVM (cfg))
2368                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2369                 else
2370                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2371                 return;
2372         } else if (ret->type == MONO_TYPE_R8) {
2373                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2374                 return;
2375         }
2376
2377         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2378 }
2379
2380 #endif /* DISABLE_JIT */
2381
2382 #define EMIT_COND_BRANCH(ins,cond,sign) \
2383         if (ins->inst_true_bb->native_offset) { \
2384                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2385         } else { \
2386                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2387                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2388             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2389                         x86_branch8 (code, cond, 0, sign); \
2390                 else \
2391                         x86_branch32 (code, cond, 0, sign); \
2392 }
2393
2394 typedef struct {
2395         MonoMethodSignature *sig;
2396         CallInfo *cinfo;
2397 } ArchDynCallInfo;
2398
2399 static gboolean
2400 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2401 {
2402         int i;
2403
2404         switch (cinfo->ret.storage) {
2405         case ArgNone:
2406         case ArgInIReg:
2407         case ArgInFloatSSEReg:
2408         case ArgInDoubleSSEReg:
2409         case ArgValuetypeAddrInIReg:
2410         case ArgValuetypeInReg:
2411                 break;
2412         default:
2413                 return FALSE;
2414         }
2415
2416         for (i = 0; i < cinfo->nargs; ++i) {
2417                 ArgInfo *ainfo = &cinfo->args [i];
2418                 switch (ainfo->storage) {
2419                 case ArgInIReg:
2420                 case ArgInFloatSSEReg:
2421                 case ArgInDoubleSSEReg:
2422                 case ArgValuetypeInReg:
2423                         break;
2424                 case ArgOnStack:
2425                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2426                                 return FALSE;
2427                         break;
2428                 default:
2429                         return FALSE;
2430                 }
2431         }
2432
2433         return TRUE;
2434 }
2435
2436 /*
2437  * mono_arch_dyn_call_prepare:
2438  *
2439  *   Return a pointer to an arch-specific structure which contains information
2440  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2441  * supported for SIG.
2442  * This function is equivalent to ffi_prep_cif in libffi.
2443  */
2444 MonoDynCallInfo*
2445 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2446 {
2447         ArchDynCallInfo *info;
2448         CallInfo *cinfo;
2449
2450         cinfo = get_call_info (NULL, sig);
2451
2452         if (!dyn_call_supported (sig, cinfo)) {
2453                 g_free (cinfo);
2454                 return NULL;
2455         }
2456
2457         info = g_new0 (ArchDynCallInfo, 1);
2458         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2459         info->sig = sig;
2460         info->cinfo = cinfo;
2461
2462         return (MonoDynCallInfo*)info;
2463 }
2464
2465 /*
2466  * mono_arch_dyn_call_free:
2467  *
2468  *   Free a MonoDynCallInfo structure.
2469  */
2470 void
2471 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2472 {
2473         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2474
2475         g_free (ainfo->cinfo);
2476         g_free (ainfo);
2477 }
2478
2479 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2480 #define GREG_TO_PTR(greg) (gpointer)(greg)
2481
2482 /*
2483  * mono_arch_get_start_dyn_call:
2484  *
2485  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2486  * store the result into BUF.
2487  * ARGS should be an array of pointers pointing to the arguments.
2488  * RET should point to a memory buffer large enought to hold the result of the
2489  * call.
2490  * This function should be as fast as possible, any work which does not depend
2491  * on the actual values of the arguments should be done in
2492  * mono_arch_dyn_call_prepare ().
2493  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2494  * libffi.
2495  */
2496 void
2497 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2498 {
2499         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2500         DynCallArgs *p = (DynCallArgs*)buf;
2501         int arg_index, greg, freg, i, pindex;
2502         MonoMethodSignature *sig = dinfo->sig;
2503         int buffer_offset = 0;
2504         static int param_reg_to_index [16];
2505         static gboolean param_reg_to_index_inited;
2506
2507         if (!param_reg_to_index_inited) {
2508                 for (i = 0; i < PARAM_REGS; ++i)
2509                         param_reg_to_index [param_regs [i]] = i;
2510                 mono_memory_barrier ();
2511                 param_reg_to_index_inited = 1;
2512         }
2513
2514         g_assert (buf_len >= sizeof (DynCallArgs));
2515
2516         p->res = 0;
2517         p->ret = ret;
2518
2519         arg_index = 0;
2520         greg = 0;
2521         freg = 0;
2522         pindex = 0;
2523
2524         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2525                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2526                 if (!sig->hasthis)
2527                         pindex = 1;
2528         }
2529
2530         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2531                 p->regs [greg ++] = PTR_TO_GREG(ret);
2532
2533         for (; pindex < sig->param_count; pindex++) {
2534                 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2535                 gpointer *arg = args [arg_index ++];
2536                 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2537                 int slot;
2538
2539                 if (ainfo->storage == ArgOnStack) {
2540                         slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2541                 } else {
2542                         slot = param_reg_to_index [ainfo->reg];
2543                 }
2544
2545                 if (t->byref) {
2546                         p->regs [slot] = PTR_TO_GREG(*(arg));
2547                         greg ++;
2548                         continue;
2549                 }
2550
2551                 switch (t->type) {
2552                 case MONO_TYPE_STRING:
2553                 case MONO_TYPE_CLASS:
2554                 case MONO_TYPE_ARRAY:
2555                 case MONO_TYPE_SZARRAY:
2556                 case MONO_TYPE_OBJECT:
2557                 case MONO_TYPE_PTR:
2558                 case MONO_TYPE_I:
2559                 case MONO_TYPE_U:
2560 #if !defined(__mono_ilp32__)
2561                 case MONO_TYPE_I8:
2562                 case MONO_TYPE_U8:
2563 #endif
2564                         p->regs [slot] = PTR_TO_GREG(*(arg));
2565                         break;
2566 #if defined(__mono_ilp32__)
2567                 case MONO_TYPE_I8:
2568                 case MONO_TYPE_U8:
2569                         p->regs [slot] = *(guint64*)(arg);
2570                         break;
2571 #endif
2572                 case MONO_TYPE_U1:
2573                         p->regs [slot] = *(guint8*)(arg);
2574                         break;
2575                 case MONO_TYPE_I1:
2576                         p->regs [slot] = *(gint8*)(arg);
2577                         break;
2578                 case MONO_TYPE_I2:
2579                         p->regs [slot] = *(gint16*)(arg);
2580                         break;
2581                 case MONO_TYPE_U2:
2582                         p->regs [slot] = *(guint16*)(arg);
2583                         break;
2584                 case MONO_TYPE_I4:
2585                         p->regs [slot] = *(gint32*)(arg);
2586                         break;
2587                 case MONO_TYPE_U4:
2588                         p->regs [slot] = *(guint32*)(arg);
2589                         break;
2590                 case MONO_TYPE_R4: {
2591                         double d;
2592
2593                         *(float*)&d = *(float*)(arg);
2594                         p->has_fp = 1;
2595                         p->fregs [freg ++] = d;
2596                         break;
2597                 }
2598                 case MONO_TYPE_R8:
2599                         p->has_fp = 1;
2600                         p->fregs [freg ++] = *(double*)(arg);
2601                         break;
2602                 case MONO_TYPE_GENERICINST:
2603                     if (MONO_TYPE_IS_REFERENCE (t)) {
2604                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2605                                 break;
2606                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2607                                         MonoClass *klass = mono_class_from_mono_type (t);
2608                                         guint8 *nullable_buf;
2609                                         int size;
2610
2611                                         size = mono_class_value_size (klass, NULL);
2612                                         nullable_buf = p->buffer + buffer_offset;
2613                                         buffer_offset += size;
2614                                         g_assert (buffer_offset <= 256);
2615
2616                                         /* The argument pointed to by arg is either a boxed vtype or null */
2617                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2618
2619                                         arg = (gpointer*)nullable_buf;
2620                                         /* Fall though */
2621
2622                         } else {
2623                                 /* Fall through */
2624                         }
2625                 case MONO_TYPE_VALUETYPE: {
2626                         switch (ainfo->storage) {
2627                         case ArgValuetypeInReg:
2628                                 for (i = 0; i < 2; ++i) {
2629                                         switch (ainfo->pair_storage [i]) {
2630                                         case ArgNone:
2631                                                 break;
2632                                         case ArgInIReg:
2633                                                 slot = param_reg_to_index [ainfo->pair_regs [i]];
2634                                                 p->regs [slot] = ((mgreg_t*)(arg))[i];
2635                                                 break;
2636                                         case ArgInDoubleSSEReg:
2637                                                 p->has_fp = 1;
2638                                                 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2639                                                 break;
2640                                         default:
2641                                                 g_assert_not_reached ();
2642                                                 break;
2643                                         }
2644                                 }
2645                                 break;
2646                         case ArgOnStack:
2647                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2648                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2649                                 break;
2650                         default:
2651                                 g_assert_not_reached ();
2652                                 break;
2653                         }
2654                         break;
2655                 }
2656                 default:
2657                         g_assert_not_reached ();
2658                 }
2659         }
2660 }
2661
2662 /*
2663  * mono_arch_finish_dyn_call:
2664  *
2665  *   Store the result of a dyn call into the return value buffer passed to
2666  * start_dyn_call ().
2667  * This function should be as fast as possible, any work which does not depend
2668  * on the actual values of the arguments should be done in
2669  * mono_arch_dyn_call_prepare ().
2670  */
2671 void
2672 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2673 {
2674         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2675         MonoMethodSignature *sig = dinfo->sig;
2676         DynCallArgs *dargs = (DynCallArgs*)buf;
2677         guint8 *ret = dargs->ret;
2678         mgreg_t res = dargs->res;
2679         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2680         int i;
2681
2682         switch (sig_ret->type) {
2683         case MONO_TYPE_VOID:
2684                 *(gpointer*)ret = NULL;
2685                 break;
2686         case MONO_TYPE_STRING:
2687         case MONO_TYPE_CLASS:
2688         case MONO_TYPE_ARRAY:
2689         case MONO_TYPE_SZARRAY:
2690         case MONO_TYPE_OBJECT:
2691         case MONO_TYPE_I:
2692         case MONO_TYPE_U:
2693         case MONO_TYPE_PTR:
2694                 *(gpointer*)ret = GREG_TO_PTR(res);
2695                 break;
2696         case MONO_TYPE_I1:
2697                 *(gint8*)ret = res;
2698                 break;
2699         case MONO_TYPE_U1:
2700                 *(guint8*)ret = res;
2701                 break;
2702         case MONO_TYPE_I2:
2703                 *(gint16*)ret = res;
2704                 break;
2705         case MONO_TYPE_U2:
2706                 *(guint16*)ret = res;
2707                 break;
2708         case MONO_TYPE_I4:
2709                 *(gint32*)ret = res;
2710                 break;
2711         case MONO_TYPE_U4:
2712                 *(guint32*)ret = res;
2713                 break;
2714         case MONO_TYPE_I8:
2715                 *(gint64*)ret = res;
2716                 break;
2717         case MONO_TYPE_U8:
2718                 *(guint64*)ret = res;
2719                 break;
2720         case MONO_TYPE_R4:
2721                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2722                 break;
2723         case MONO_TYPE_R8:
2724                 *(double*)ret = dargs->fregs [0];
2725                 break;
2726         case MONO_TYPE_GENERICINST:
2727                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2728                         *(gpointer*)ret = GREG_TO_PTR(res);
2729                         break;
2730                 } else {
2731                         /* Fall through */
2732                 }
2733         case MONO_TYPE_VALUETYPE:
2734                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2735                         /* Nothing to do */
2736                 } else {
2737                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2738
2739                         g_assert (ainfo->storage == ArgValuetypeInReg);
2740
2741                         for (i = 0; i < 2; ++i) {
2742                                 switch (ainfo->pair_storage [0]) {
2743                                 case ArgInIReg:
2744                                         ((mgreg_t*)ret)[i] = res;
2745                                         break;
2746                                 case ArgInDoubleSSEReg:
2747                                         ((double*)ret)[i] = dargs->fregs [i];
2748                                         break;
2749                                 case ArgNone:
2750                                         break;
2751                                 default:
2752                                         g_assert_not_reached ();
2753                                         break;
2754                                 }
2755                         }
2756                 }
2757                 break;
2758         default:
2759                 g_assert_not_reached ();
2760         }
2761 }
2762
2763 /* emit an exception if condition is fail */
2764 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2765         do {                                                        \
2766                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2767                 if (tins == NULL) {                                                                             \
2768                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2769                                         MONO_PATCH_INFO_EXC, exc_name);  \
2770                         x86_branch32 (code, cond, 0, signed);               \
2771                 } else {        \
2772                         EMIT_COND_BRANCH (tins, cond, signed);  \
2773                 }                       \
2774         } while (0);
2775
2776 #define EMIT_FPCOMPARE(code) do { \
2777         amd64_fcompp (code); \
2778         amd64_fnstsw (code); \
2779 } while (0);
2780
2781 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2782     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2783         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2784         amd64_ ##op (code); \
2785         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2786         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2787 } while (0);
2788
2789 static guint8*
2790 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2791 {
2792         gboolean no_patch = FALSE;
2793
2794         /*
2795          * FIXME: Add support for thunks
2796          */
2797         {
2798                 gboolean near_call = FALSE;
2799
2800                 /*
2801                  * Indirect calls are expensive so try to make a near call if possible.
2802                  * The caller memory is allocated by the code manager so it is
2803                  * guaranteed to be at a 32 bit offset.
2804                  */
2805
2806                 if (patch_type != MONO_PATCH_INFO_ABS) {
2807                         /* The target is in memory allocated using the code manager */
2808                         near_call = TRUE;
2809
2810                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2811                                 if (((MonoMethod*)data)->klass->image->aot_module)
2812                                         /* The callee might be an AOT method */
2813                                         near_call = FALSE;
2814                                 if (((MonoMethod*)data)->dynamic)
2815                                         /* The target is in malloc-ed memory */
2816                                         near_call = FALSE;
2817                         }
2818
2819                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2820                                 /*
2821                                  * The call might go directly to a native function without
2822                                  * the wrapper.
2823                                  */
2824                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2825                                 if (mi) {
2826                                         gconstpointer target = mono_icall_get_wrapper (mi);
2827                                         if ((((guint64)target) >> 32) != 0)
2828                                                 near_call = FALSE;
2829                                 }
2830                         }
2831                 }
2832                 else {
2833                         MonoJumpInfo *jinfo = NULL;
2834
2835                         if (cfg->abs_patches)
2836                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2837                         if (jinfo) {
2838                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2839                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2840                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2841                                                 near_call = TRUE;
2842                                         no_patch = TRUE;
2843                                 } else {
2844                                         /*
2845                                          * This is not really an optimization, but required because the
2846                                          * generic class init trampolines use R11 to pass the vtable.
2847                                          */
2848                                         near_call = TRUE;
2849                                 }
2850                         } else {
2851                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2852                                 if (info) {
2853                                         if (info->func == info->wrapper) {
2854                                                 /* No wrapper */
2855                                                 if ((((guint64)info->func) >> 32) == 0)
2856                                                         near_call = TRUE;
2857                                         }
2858                                         else {
2859                                                 /* See the comment in mono_codegen () */
2860                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2861                                                         near_call = TRUE;
2862                                         }
2863                                 }
2864                                 else if ((((guint64)data) >> 32) == 0) {
2865                                         near_call = TRUE;
2866                                         no_patch = TRUE;
2867                                 }
2868                         }
2869                 }
2870
2871                 if (cfg->method->dynamic)
2872                         /* These methods are allocated using malloc */
2873                         near_call = FALSE;
2874
2875 #ifdef MONO_ARCH_NOMAP32BIT
2876                 near_call = FALSE;
2877 #endif
2878                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2879                 if (optimize_for_xen)
2880                         near_call = FALSE;
2881
2882                 if (cfg->compile_aot) {
2883                         near_call = TRUE;
2884                         no_patch = TRUE;
2885                 }
2886
2887                 if (near_call) {
2888                         /*
2889                          * Align the call displacement to an address divisible by 4 so it does
2890                          * not span cache lines. This is required for code patching to work on SMP
2891                          * systems.
2892                          */
2893                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2894                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2895                                 amd64_padding (code, pad_size);
2896                         }
2897                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2898                         amd64_call_code (code, 0);
2899                 }
2900                 else {
2901                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2902                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2903                         amd64_call_reg (code, GP_SCRATCH_REG);
2904                 }
2905         }
2906
2907         return code;
2908 }
2909
2910 static inline guint8*
2911 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2912 {
2913 #ifdef TARGET_WIN32
2914         if (win64_adjust_stack)
2915                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2916 #endif
2917         code = emit_call_body (cfg, code, patch_type, data);
2918 #ifdef TARGET_WIN32
2919         if (win64_adjust_stack)
2920                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2921 #endif
2922
2923         return code;
2924 }
2925
2926 static inline int
2927 store_membase_imm_to_store_membase_reg (int opcode)
2928 {
2929         switch (opcode) {
2930         case OP_STORE_MEMBASE_IMM:
2931                 return OP_STORE_MEMBASE_REG;
2932         case OP_STOREI4_MEMBASE_IMM:
2933                 return OP_STOREI4_MEMBASE_REG;
2934         case OP_STOREI8_MEMBASE_IMM:
2935                 return OP_STOREI8_MEMBASE_REG;
2936         }
2937
2938         return -1;
2939 }
2940
2941 #ifndef DISABLE_JIT
2942
2943 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2944
2945 /*
2946  * mono_arch_peephole_pass_1:
2947  *
2948  *   Perform peephole opts which should/can be performed before local regalloc
2949  */
2950 void
2951 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2952 {
2953         MonoInst *ins, *n;
2954
2955         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2956                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2957
2958                 switch (ins->opcode) {
2959                 case OP_ADD_IMM:
2960                 case OP_IADD_IMM:
2961                 case OP_LADD_IMM:
2962                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2963                                 /*
2964                                  * X86_LEA is like ADD, but doesn't have the
2965                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2966                                  * its operand to 64 bit.
2967                                  */
2968                                 ins->opcode = OP_X86_LEA_MEMBASE;
2969                                 ins->inst_basereg = ins->sreg1;
2970                         }
2971                         break;
2972                 case OP_LXOR:
2973                 case OP_IXOR:
2974                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2975                                 MonoInst *ins2;
2976
2977                                 /*
2978                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2979                                  * the latter has length 2-3 instead of 6 (reverse constant
2980                                  * propagation). These instruction sequences are very common
2981                                  * in the initlocals bblock.
2982                                  */
2983                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2984                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2985                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2986                                                 ins2->sreg1 = ins->dreg;
2987                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2988                                                 /* Continue */
2989                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2990                                                 NULLIFY_INS (ins2);
2991                                                 /* Continue */
2992                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2993                                                 /* Continue */
2994                                         } else {
2995                                                 break;
2996                                         }
2997                                 }
2998                         }
2999                         break;
3000                 case OP_COMPARE_IMM:
3001                 case OP_LCOMPARE_IMM:
3002                         /* OP_COMPARE_IMM (reg, 0)
3003                          * -->
3004                          * OP_AMD64_TEST_NULL (reg)
3005                          */
3006                         if (!ins->inst_imm)
3007                                 ins->opcode = OP_AMD64_TEST_NULL;
3008                         break;
3009                 case OP_ICOMPARE_IMM:
3010                         if (!ins->inst_imm)
3011                                 ins->opcode = OP_X86_TEST_NULL;
3012                         break;
3013                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3014                         /*
3015                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3016                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3017                          * -->
3018                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3019                          * OP_COMPARE_IMM reg, imm
3020                          *
3021                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3022                          */
3023                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3024                             ins->inst_basereg == last_ins->inst_destbasereg &&
3025                             ins->inst_offset == last_ins->inst_offset) {
3026                                         ins->opcode = OP_ICOMPARE_IMM;
3027                                         ins->sreg1 = last_ins->sreg1;
3028
3029                                         /* check if we can remove cmp reg,0 with test null */
3030                                         if (!ins->inst_imm)
3031                                                 ins->opcode = OP_X86_TEST_NULL;
3032                                 }
3033
3034                         break;
3035                 }
3036
3037                 mono_peephole_ins (bb, ins);
3038         }
3039 }
3040
3041 void
3042 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3043 {
3044         MonoInst *ins, *n;
3045
3046         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3047                 switch (ins->opcode) {
3048                 case OP_ICONST:
3049                 case OP_I8CONST: {
3050                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3051                         /* reg = 0 -> XOR (reg, reg) */
3052                         /* XOR sets cflags on x86, so we cant do it always */
3053                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3054                                 ins->opcode = OP_LXOR;
3055                                 ins->sreg1 = ins->dreg;
3056                                 ins->sreg2 = ins->dreg;
3057                                 /* Fall through */
3058                         } else {
3059                                 break;
3060                         }
3061                 }
3062                 case OP_LXOR:
3063                         /*
3064                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3065                          * 0 result into 64 bits.
3066                          */
3067                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3068                                 ins->opcode = OP_IXOR;
3069                         }
3070                         /* Fall through */
3071                 case OP_IXOR:
3072                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3073                                 MonoInst *ins2;
3074
3075                                 /*
3076                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3077                                  * the latter has length 2-3 instead of 6 (reverse constant
3078                                  * propagation). These instruction sequences are very common
3079                                  * in the initlocals bblock.
3080                                  */
3081                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3082                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3083                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3084                                                 ins2->sreg1 = ins->dreg;
3085                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3086                                                 /* Continue */
3087                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3088                                                 NULLIFY_INS (ins2);
3089                                                 /* Continue */
3090                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3091                                                 /* Continue */
3092                                         } else {
3093                                                 break;
3094                                         }
3095                                 }
3096                         }
3097                         break;
3098                 case OP_IADD_IMM:
3099                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3100                                 ins->opcode = OP_X86_INC_REG;
3101                         break;
3102                 case OP_ISUB_IMM:
3103                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3104                                 ins->opcode = OP_X86_DEC_REG;
3105                         break;
3106                 }
3107
3108                 mono_peephole_ins (bb, ins);
3109         }
3110 }
3111
3112 #define NEW_INS(cfg,ins,dest,op) do {   \
3113                 MONO_INST_NEW ((cfg), (dest), (op)); \
3114         (dest)->cil_code = (ins)->cil_code; \
3115         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3116         } while (0)
3117
3118 /*
3119  * mono_arch_lowering_pass:
3120  *
3121  *  Converts complex opcodes into simpler ones so that each IR instruction
3122  * corresponds to one machine instruction.
3123  */
3124 void
3125 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3126 {
3127         MonoInst *ins, *n, *temp;
3128
3129         /*
3130          * FIXME: Need to add more instructions, but the current machine
3131          * description can't model some parts of the composite instructions like
3132          * cdq.
3133          */
3134         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3135                 switch (ins->opcode) {
3136                 case OP_DIV_IMM:
3137                 case OP_REM_IMM:
3138                 case OP_IDIV_IMM:
3139                 case OP_IDIV_UN_IMM:
3140                 case OP_IREM_UN_IMM:
3141                 case OP_LREM_IMM:
3142                 case OP_IREM_IMM:
3143                         mono_decompose_op_imm (cfg, bb, ins);
3144                         break;
3145                 case OP_COMPARE_IMM:
3146                 case OP_LCOMPARE_IMM:
3147                         if (!amd64_use_imm32 (ins->inst_imm)) {
3148                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3149                                 temp->inst_c0 = ins->inst_imm;
3150                                 temp->dreg = mono_alloc_ireg (cfg);
3151                                 ins->opcode = OP_COMPARE;
3152                                 ins->sreg2 = temp->dreg;
3153                         }
3154                         break;
3155 #ifndef __mono_ilp32__
3156                 case OP_LOAD_MEMBASE:
3157 #endif
3158                 case OP_LOADI8_MEMBASE:
3159                 /*  Don't generate memindex opcodes (to simplify */
3160                 /*  read sandboxing) */
3161                         if (!amd64_use_imm32 (ins->inst_offset)) {
3162                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3163                                 temp->inst_c0 = ins->inst_offset;
3164                                 temp->dreg = mono_alloc_ireg (cfg);
3165                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3166                                 ins->inst_indexreg = temp->dreg;
3167                         }
3168                         break;
3169 #ifndef __mono_ilp32__
3170                 case OP_STORE_MEMBASE_IMM:
3171 #endif
3172                 case OP_STOREI8_MEMBASE_IMM:
3173                         if (!amd64_use_imm32 (ins->inst_imm)) {
3174                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3175                                 temp->inst_c0 = ins->inst_imm;
3176                                 temp->dreg = mono_alloc_ireg (cfg);
3177                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3178                                 ins->sreg1 = temp->dreg;
3179                         }
3180                         break;
3181 #ifdef MONO_ARCH_SIMD_INTRINSICS
3182                 case OP_EXPAND_I1: {
3183                                 int temp_reg1 = mono_alloc_ireg (cfg);
3184                                 int temp_reg2 = mono_alloc_ireg (cfg);
3185                                 int original_reg = ins->sreg1;
3186
3187                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3188                                 temp->sreg1 = original_reg;
3189                                 temp->dreg = temp_reg1;
3190
3191                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3192                                 temp->sreg1 = temp_reg1;
3193                                 temp->dreg = temp_reg2;
3194                                 temp->inst_imm = 8;
3195
3196                                 NEW_INS (cfg, ins, temp, OP_LOR);
3197                                 temp->sreg1 = temp->dreg = temp_reg2;
3198                                 temp->sreg2 = temp_reg1;
3199
3200                                 ins->opcode = OP_EXPAND_I2;
3201                                 ins->sreg1 = temp_reg2;
3202                         }
3203                         break;
3204 #endif
3205                 default:
3206                         break;
3207                 }
3208         }
3209
3210         bb->max_vreg = cfg->next_vreg;
3211 }
3212
3213 static const int
3214 branch_cc_table [] = {
3215         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3216         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3217         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3218 };
3219
3220 /* Maps CMP_... constants to X86_CC_... constants */
3221 static const int
3222 cc_table [] = {
3223         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3224         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3225 };
3226
3227 static const int
3228 cc_signed_table [] = {
3229         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3230         FALSE, FALSE, FALSE, FALSE
3231 };
3232
3233 /*#include "cprop.c"*/
3234
3235 static unsigned char*
3236 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3237 {
3238         if (size == 8)
3239                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3240         else
3241                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3242
3243         if (size == 1)
3244                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3245         else if (size == 2)
3246                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3247         return code;
3248 }
3249
3250 static unsigned char*
3251 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3252 {
3253         int sreg = tree->sreg1;
3254         int need_touch = FALSE;
3255
3256 #if defined(TARGET_WIN32)
3257         need_touch = TRUE;
3258 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3259         if (!tree->flags & MONO_INST_INIT)
3260                 need_touch = TRUE;
3261 #endif
3262
3263         if (need_touch) {
3264                 guint8* br[5];
3265
3266                 /*
3267                  * Under Windows:
3268                  * If requested stack size is larger than one page,
3269                  * perform stack-touch operation
3270                  */
3271                 /*
3272                  * Generate stack probe code.
3273                  * Under Windows, it is necessary to allocate one page at a time,
3274                  * "touching" stack after each successful sub-allocation. This is
3275                  * because of the way stack growth is implemented - there is a
3276                  * guard page before the lowest stack page that is currently commited.
3277                  * Stack normally grows sequentially so OS traps access to the
3278                  * guard page and commits more pages when needed.
3279                  */
3280                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3281                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3282
3283                 br[2] = code; /* loop */
3284                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3285                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3286                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3287                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3288                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3289                 amd64_patch (br[3], br[2]);
3290                 amd64_test_reg_reg (code, sreg, sreg);
3291                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3292                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3293
3294                 br[1] = code; x86_jump8 (code, 0);
3295
3296                 amd64_patch (br[0], code);
3297                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3298                 amd64_patch (br[1], code);
3299                 amd64_patch (br[4], code);
3300         }
3301         else
3302                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3303
3304         if (tree->flags & MONO_INST_INIT) {
3305                 int offset = 0;
3306                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3307                         amd64_push_reg (code, AMD64_RAX);
3308                         offset += 8;
3309                 }
3310                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3311                         amd64_push_reg (code, AMD64_RCX);
3312                         offset += 8;
3313                 }
3314                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3315                         amd64_push_reg (code, AMD64_RDI);
3316                         offset += 8;
3317                 }
3318
3319                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3320                 if (sreg != AMD64_RCX)
3321                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3322                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3323
3324                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3325                 if (cfg->param_area)
3326                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3327                 amd64_cld (code);
3328                 amd64_prefix (code, X86_REP_PREFIX);
3329                 amd64_stosl (code);
3330
3331                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3332                         amd64_pop_reg (code, AMD64_RDI);
3333                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3334                         amd64_pop_reg (code, AMD64_RCX);
3335                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3336                         amd64_pop_reg (code, AMD64_RAX);
3337         }
3338         return code;
3339 }
3340
3341 static guint8*
3342 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3343 {
3344         CallInfo *cinfo;
3345         guint32 quad;
3346
3347         /* Move return value to the target register */
3348         /* FIXME: do this in the local reg allocator */
3349         switch (ins->opcode) {
3350         case OP_CALL:
3351         case OP_CALL_REG:
3352         case OP_CALL_MEMBASE:
3353         case OP_LCALL:
3354         case OP_LCALL_REG:
3355         case OP_LCALL_MEMBASE:
3356                 g_assert (ins->dreg == AMD64_RAX);
3357                 break;
3358         case OP_FCALL:
3359         case OP_FCALL_REG:
3360         case OP_FCALL_MEMBASE: {
3361                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3362                 if (rtype->type == MONO_TYPE_R4) {
3363                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3364                 }
3365                 else {
3366                         if (ins->dreg != AMD64_XMM0)
3367                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3368                 }
3369                 break;
3370         }
3371         case OP_RCALL:
3372         case OP_RCALL_REG:
3373         case OP_RCALL_MEMBASE:
3374                 if (ins->dreg != AMD64_XMM0)
3375                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3376                 break;
3377         case OP_VCALL:
3378         case OP_VCALL_REG:
3379         case OP_VCALL_MEMBASE:
3380         case OP_VCALL2:
3381         case OP_VCALL2_REG:
3382         case OP_VCALL2_MEMBASE:
3383                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3384                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3385                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3386
3387                         /* Load the destination address */
3388                         g_assert (loc->opcode == OP_REGOFFSET);
3389                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3390
3391                         for (quad = 0; quad < 2; quad ++) {
3392                                 switch (cinfo->ret.pair_storage [quad]) {
3393                                 case ArgInIReg:
3394                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3395                                         break;
3396                                 case ArgInFloatSSEReg:
3397                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3398                                         break;
3399                                 case ArgInDoubleSSEReg:
3400                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3401                                         break;
3402                                 case ArgNone:
3403                                         break;
3404                                 default:
3405                                         NOT_IMPLEMENTED;
3406                                 }
3407                         }
3408                 }
3409                 break;
3410         }
3411
3412         return code;
3413 }
3414
3415 #endif /* DISABLE_JIT */
3416
3417 #ifdef TARGET_MACH
3418 static int tls_gs_offset;
3419 #endif
3420
3421 gboolean
3422 mono_arch_have_fast_tls (void)
3423 {
3424 #ifdef TARGET_MACH
3425         static gboolean have_fast_tls = FALSE;
3426         static gboolean inited = FALSE;
3427         guint8 *ins;
3428
3429         if (mini_get_debug_options ()->use_fallback_tls)
3430                 return FALSE;
3431
3432         if (inited)
3433                 return have_fast_tls;
3434
3435         ins = (guint8*)pthread_getspecific;
3436
3437         /*
3438          * We're looking for these two instructions:
3439          *
3440          * mov    %gs:[offset](,%rdi,8),%rax
3441          * retq
3442          */
3443         have_fast_tls = ins [0] == 0x65 &&
3444                        ins [1] == 0x48 &&
3445                        ins [2] == 0x8b &&
3446                        ins [3] == 0x04 &&
3447                        ins [4] == 0xfd &&
3448                        ins [6] == 0x00 &&
3449                        ins [7] == 0x00 &&
3450                        ins [8] == 0x00 &&
3451                        ins [9] == 0xc3;
3452
3453         tls_gs_offset = ins[5];
3454
3455         /*
3456          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3457          * For that version we're looking for these instructions:
3458          *
3459          * pushq  %rbp
3460          * movq   %rsp, %rbp
3461          * mov    %gs:[offset](,%rdi,8),%rax
3462          * popq   %rbp
3463          * retq
3464          */
3465         if (!have_fast_tls) {
3466                 have_fast_tls = ins [0] == 0x55 &&
3467                                ins [1] == 0x48 &&
3468                                ins [2] == 0x89 &&
3469                                ins [3] == 0xe5 &&
3470                                ins [4] == 0x65 &&
3471                                ins [5] == 0x48 &&
3472                                ins [6] == 0x8b &&
3473                                ins [7] == 0x04 &&
3474                                ins [8] == 0xfd &&
3475                                ins [10] == 0x00 &&
3476                                ins [11] == 0x00 &&
3477                                ins [12] == 0x00 &&
3478                                ins [13] == 0x5d &&
3479                                ins [14] == 0xc3;
3480
3481                 tls_gs_offset = ins[9];
3482         }
3483         inited = TRUE;
3484
3485         return have_fast_tls;
3486 #elif defined(TARGET_ANDROID)
3487         return FALSE;
3488 #else
3489         if (mini_get_debug_options ()->use_fallback_tls)
3490                 return FALSE;
3491         return TRUE;
3492 #endif
3493 }
3494
3495 int
3496 mono_amd64_get_tls_gs_offset (void)
3497 {
3498 #ifdef TARGET_OSX
3499         return tls_gs_offset;
3500 #else
3501         g_assert_not_reached ();
3502         return -1;
3503 #endif
3504 }
3505
3506 /*
3507  * mono_amd64_emit_tls_get:
3508  * @code: buffer to store code to
3509  * @dreg: hard register where to place the result
3510  * @tls_offset: offset info
3511  *
3512  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3513  * the dreg register the item in the thread local storage identified
3514  * by tls_offset.
3515  *
3516  * Returns: a pointer to the end of the stored code
3517  */
3518 static guint8*
3519 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3520 {
3521 #ifdef TARGET_WIN32
3522         if (tls_offset < 64) {
3523                 x86_prefix (code, X86_GS_PREFIX);
3524                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3525         } else {
3526                 guint8 *buf [16];
3527
3528                 g_assert (tls_offset < 0x440);
3529                 /* Load TEB->TlsExpansionSlots */
3530                 x86_prefix (code, X86_GS_PREFIX);
3531                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3532                 amd64_test_reg_reg (code, dreg, dreg);
3533                 buf [0] = code;
3534                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3535                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3536                 amd64_patch (buf [0], code);
3537         }
3538 #elif defined(TARGET_MACH)
3539         x86_prefix (code, X86_GS_PREFIX);
3540         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3541 #else
3542         if (optimize_for_xen) {
3543                 x86_prefix (code, X86_FS_PREFIX);
3544                 amd64_mov_reg_mem (code, dreg, 0, 8);
3545                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3546         } else {
3547                 x86_prefix (code, X86_FS_PREFIX);
3548                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3549         }
3550 #endif
3551         return code;
3552 }
3553
3554 static guint8*
3555 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3556 {
3557 #ifdef TARGET_WIN32
3558         g_assert_not_reached ();
3559 #elif defined(TARGET_MACH)
3560         x86_prefix (code, X86_GS_PREFIX);
3561         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3562 #else
3563         g_assert (!optimize_for_xen);
3564         x86_prefix (code, X86_FS_PREFIX);
3565         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3566 #endif
3567         return code;
3568 }
3569
3570 /*
3571  * emit_setup_lmf:
3572  *
3573  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3574  */
3575 static guint8*
3576 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3577 {
3578         /*
3579          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3580          */
3581         /*
3582          * sp is saved right before calls but we need to save it here too so
3583          * async stack walks would work.
3584          */
3585         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3586         /* Save rbp */
3587         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3588         if (cfg->arch.omit_fp && cfa_offset != -1)
3589                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3590
3591         /* These can't contain refs */
3592         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3593         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3594         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3595         /* These are handled automatically by the stack marking code */
3596         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3597
3598         return code;
3599 }
3600
3601 #ifdef TARGET_WIN32
3602
3603 #define TEB_LAST_ERROR_OFFSET 0x068
3604
3605 static guint8*
3606 emit_get_last_error (guint8* code, int dreg)
3607 {
3608         /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3609         x86_prefix (code, X86_GS_PREFIX);
3610         amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3611
3612         return code;
3613 }
3614
3615 #else
3616
3617 static guint8*
3618 emit_get_last_error (guint8* code, int dreg)
3619 {
3620         g_assert_not_reached ();
3621 }
3622
3623 #endif
3624
3625 /* benchmark and set based on cpu */
3626 #define LOOP_ALIGNMENT 8
3627 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3628
3629 #ifndef DISABLE_JIT
3630 void
3631 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3632 {
3633         MonoInst *ins;
3634         MonoCallInst *call;
3635         guint offset;
3636         guint8 *code = cfg->native_code + cfg->code_len;
3637         int max_len;
3638
3639         /* Fix max_offset estimate for each successor bb */
3640         if (cfg->opt & MONO_OPT_BRANCH) {
3641                 int current_offset = cfg->code_len;
3642                 MonoBasicBlock *current_bb;
3643                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3644                         current_bb->max_offset = current_offset;
3645                         current_offset += current_bb->max_length;
3646                 }
3647         }
3648
3649         if (cfg->opt & MONO_OPT_LOOP) {
3650                 int pad, align = LOOP_ALIGNMENT;
3651                 /* set alignment depending on cpu */
3652                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3653                         pad = align - pad;
3654                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3655                         amd64_padding (code, pad);
3656                         cfg->code_len += pad;
3657                         bb->native_offset = cfg->code_len;
3658                 }
3659         }
3660
3661         if (cfg->verbose_level > 2)
3662                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3663
3664         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3665                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3666                 g_assert (!cfg->compile_aot);
3667
3668                 cov->data [bb->dfn].cil_code = bb->cil_code;
3669                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3670                 /* this is not thread save, but good enough */
3671                 amd64_inc_membase (code, AMD64_R11, 0);
3672         }
3673
3674         offset = code - cfg->native_code;
3675
3676         mono_debug_open_block (cfg, bb, offset);
3677
3678     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3679                 x86_breakpoint (code);
3680
3681         MONO_BB_FOR_EACH_INS (bb, ins) {
3682                 offset = code - cfg->native_code;
3683
3684                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3685
3686 #define EXTRA_CODE_SPACE (16)
3687
3688                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3689                         cfg->code_size *= 2;
3690                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3691                         code = cfg->native_code + offset;
3692                         cfg->stat_code_reallocs++;
3693                 }
3694
3695                 if (cfg->debug_info)
3696                         mono_debug_record_line_number (cfg, ins, offset);
3697
3698                 switch (ins->opcode) {
3699                 case OP_BIGMUL:
3700                         amd64_mul_reg (code, ins->sreg2, TRUE);
3701                         break;
3702                 case OP_BIGMUL_UN:
3703                         amd64_mul_reg (code, ins->sreg2, FALSE);
3704                         break;
3705                 case OP_X86_SETEQ_MEMBASE:
3706                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3707                         break;
3708                 case OP_STOREI1_MEMBASE_IMM:
3709                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3710                         break;
3711                 case OP_STOREI2_MEMBASE_IMM:
3712                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3713                         break;
3714                 case OP_STOREI4_MEMBASE_IMM:
3715                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3716                         break;
3717                 case OP_STOREI1_MEMBASE_REG:
3718                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3719                         break;
3720                 case OP_STOREI2_MEMBASE_REG:
3721                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3722                         break;
3723                 /* In AMD64 NaCl, pointers are 4 bytes, */
3724                 /*  so STORE_* != STOREI8_*. Likewise below. */
3725                 case OP_STORE_MEMBASE_REG:
3726                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3727                         break;
3728                 case OP_STOREI8_MEMBASE_REG:
3729                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3730                         break;
3731                 case OP_STOREI4_MEMBASE_REG:
3732                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3733                         break;
3734                 case OP_STORE_MEMBASE_IMM:
3735                         /* In NaCl, this could be a PCONST type, which could */
3736                         /* mean a pointer type was copied directly into the  */
3737                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3738                         /* the value would be 0x00000000FFFFFFFF which is    */
3739                         /* not proper for an imm32 unless you cast it.       */
3740                         g_assert (amd64_is_imm32 (ins->inst_imm));
3741                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3742                         break;
3743                 case OP_STOREI8_MEMBASE_IMM:
3744                         g_assert (amd64_is_imm32 (ins->inst_imm));
3745                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3746                         break;
3747                 case OP_LOAD_MEM:
3748 #ifdef __mono_ilp32__
3749                         /* In ILP32, pointers are 4 bytes, so separate these */
3750                         /* cases, use literal 8 below where we really want 8 */
3751                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3752                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3753                         break;
3754 #endif
3755                 case OP_LOADI8_MEM:
3756                         // FIXME: Decompose this earlier
3757                         if (amd64_use_imm32 (ins->inst_imm))
3758                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3759                         else {
3760                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3761                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3762                         }
3763                         break;
3764                 case OP_LOADI4_MEM:
3765                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3766                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3767                         break;
3768                 case OP_LOADU4_MEM:
3769                         // FIXME: Decompose this earlier
3770                         if (amd64_use_imm32 (ins->inst_imm))
3771                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3772                         else {
3773                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3774                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3775                         }
3776                         break;
3777                 case OP_LOADU1_MEM:
3778                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3779                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3780                         break;
3781                 case OP_LOADU2_MEM:
3782                         /* For NaCl, pointers are 4 bytes, so separate these */
3783                         /* cases, use literal 8 below where we really want 8 */
3784                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3785                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3786                         break;
3787                 case OP_LOAD_MEMBASE:
3788                         g_assert (amd64_is_imm32 (ins->inst_offset));
3789                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3790                         break;
3791                 case OP_LOADI8_MEMBASE:
3792                         /* Use literal 8 instead of sizeof pointer or */
3793                         /* register, we really want 8 for this opcode */
3794                         g_assert (amd64_is_imm32 (ins->inst_offset));
3795                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3796                         break;
3797                 case OP_LOADI4_MEMBASE:
3798                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3799                         break;
3800                 case OP_LOADU4_MEMBASE:
3801                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3802                         break;
3803                 case OP_LOADU1_MEMBASE:
3804                         /* The cpu zero extends the result into 64 bits */
3805                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3806                         break;
3807                 case OP_LOADI1_MEMBASE:
3808                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3809                         break;
3810                 case OP_LOADU2_MEMBASE:
3811                         /* The cpu zero extends the result into 64 bits */
3812                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3813                         break;
3814                 case OP_LOADI2_MEMBASE:
3815                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3816                         break;
3817                 case OP_AMD64_LOADI8_MEMINDEX:
3818                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3819                         break;
3820                 case OP_LCONV_TO_I1:
3821                 case OP_ICONV_TO_I1:
3822                 case OP_SEXT_I1:
3823                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3824                         break;
3825                 case OP_LCONV_TO_I2:
3826                 case OP_ICONV_TO_I2:
3827                 case OP_SEXT_I2:
3828                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3829                         break;
3830                 case OP_LCONV_TO_U1:
3831                 case OP_ICONV_TO_U1:
3832                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3833                         break;
3834                 case OP_LCONV_TO_U2:
3835                 case OP_ICONV_TO_U2:
3836                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3837                         break;
3838                 case OP_ZEXT_I4:
3839                         /* Clean out the upper word */
3840                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3841                         break;
3842                 case OP_SEXT_I4:
3843                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3844                         break;
3845                 case OP_COMPARE:
3846                 case OP_LCOMPARE:
3847                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3848                         break;
3849                 case OP_COMPARE_IMM:
3850 #if defined(__mono_ilp32__)
3851                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3852                         g_assert (amd64_is_imm32 (ins->inst_imm));
3853                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3854                         break;
3855 #endif
3856                 case OP_LCOMPARE_IMM:
3857                         g_assert (amd64_is_imm32 (ins->inst_imm));
3858                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3859                         break;
3860                 case OP_X86_COMPARE_REG_MEMBASE:
3861                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3862                         break;
3863                 case OP_X86_TEST_NULL:
3864                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3865                         break;
3866                 case OP_AMD64_TEST_NULL:
3867                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3868                         break;
3869
3870                 case OP_X86_ADD_REG_MEMBASE:
3871                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3872                         break;
3873                 case OP_X86_SUB_REG_MEMBASE:
3874                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3875                         break;
3876                 case OP_X86_AND_REG_MEMBASE:
3877                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3878                         break;
3879                 case OP_X86_OR_REG_MEMBASE:
3880                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3881                         break;
3882                 case OP_X86_XOR_REG_MEMBASE:
3883                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3884                         break;
3885
3886                 case OP_X86_ADD_MEMBASE_IMM:
3887                         /* FIXME: Make a 64 version too */
3888                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3889                         break;
3890                 case OP_X86_SUB_MEMBASE_IMM:
3891                         g_assert (amd64_is_imm32 (ins->inst_imm));
3892                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3893                         break;
3894                 case OP_X86_AND_MEMBASE_IMM:
3895                         g_assert (amd64_is_imm32 (ins->inst_imm));
3896                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3897                         break;
3898                 case OP_X86_OR_MEMBASE_IMM:
3899                         g_assert (amd64_is_imm32 (ins->inst_imm));
3900                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3901                         break;
3902                 case OP_X86_XOR_MEMBASE_IMM:
3903                         g_assert (amd64_is_imm32 (ins->inst_imm));
3904                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3905                         break;
3906                 case OP_X86_ADD_MEMBASE_REG:
3907                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3908                         break;
3909                 case OP_X86_SUB_MEMBASE_REG:
3910                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3911                         break;
3912                 case OP_X86_AND_MEMBASE_REG:
3913                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3914                         break;
3915                 case OP_X86_OR_MEMBASE_REG:
3916                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3917                         break;
3918                 case OP_X86_XOR_MEMBASE_REG:
3919                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3920                         break;
3921                 case OP_X86_INC_MEMBASE:
3922                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3923                         break;
3924                 case OP_X86_INC_REG:
3925                         amd64_inc_reg_size (code, ins->dreg, 4);
3926                         break;
3927                 case OP_X86_DEC_MEMBASE:
3928                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3929                         break;
3930                 case OP_X86_DEC_REG:
3931                         amd64_dec_reg_size (code, ins->dreg, 4);
3932                         break;
3933                 case OP_X86_MUL_REG_MEMBASE:
3934                 case OP_X86_MUL_MEMBASE_REG:
3935                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3936                         break;
3937                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3938                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3939                         break;
3940                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3941                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3942                         break;
3943                 case OP_AMD64_COMPARE_MEMBASE_REG:
3944                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3945                         break;
3946                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3947                         g_assert (amd64_is_imm32 (ins->inst_imm));
3948                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3949                         break;
3950                 case OP_X86_COMPARE_MEMBASE8_IMM:
3951                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3952                         break;
3953                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3954                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3955                         break;
3956                 case OP_AMD64_COMPARE_REG_MEMBASE:
3957                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3958                         break;
3959
3960                 case OP_AMD64_ADD_REG_MEMBASE:
3961                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3962                         break;
3963                 case OP_AMD64_SUB_REG_MEMBASE:
3964                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3965                         break;
3966                 case OP_AMD64_AND_REG_MEMBASE:
3967                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3968                         break;
3969                 case OP_AMD64_OR_REG_MEMBASE:
3970                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3971                         break;
3972                 case OP_AMD64_XOR_REG_MEMBASE:
3973                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3974                         break;
3975
3976                 case OP_AMD64_ADD_MEMBASE_REG:
3977                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3978                         break;
3979                 case OP_AMD64_SUB_MEMBASE_REG:
3980                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3981                         break;
3982                 case OP_AMD64_AND_MEMBASE_REG:
3983                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3984                         break;
3985                 case OP_AMD64_OR_MEMBASE_REG:
3986                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3987                         break;
3988                 case OP_AMD64_XOR_MEMBASE_REG:
3989                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3990                         break;
3991
3992                 case OP_AMD64_ADD_MEMBASE_IMM:
3993                         g_assert (amd64_is_imm32 (ins->inst_imm));
3994                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3995                         break;
3996                 case OP_AMD64_SUB_MEMBASE_IMM:
3997                         g_assert (amd64_is_imm32 (ins->inst_imm));
3998                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3999                         break;
4000                 case OP_AMD64_AND_MEMBASE_IMM:
4001                         g_assert (amd64_is_imm32 (ins->inst_imm));
4002                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4003                         break;
4004                 case OP_AMD64_OR_MEMBASE_IMM:
4005                         g_assert (amd64_is_imm32 (ins->inst_imm));
4006                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4007                         break;
4008                 case OP_AMD64_XOR_MEMBASE_IMM:
4009                         g_assert (amd64_is_imm32 (ins->inst_imm));
4010                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4011                         break;
4012
4013                 case OP_BREAK:
4014                         amd64_breakpoint (code);
4015                         break;
4016                 case OP_RELAXED_NOP:
4017                         x86_prefix (code, X86_REP_PREFIX);
4018                         x86_nop (code);
4019                         break;
4020                 case OP_HARD_NOP:
4021                         x86_nop (code);
4022                         break;
4023                 case OP_NOP:
4024                 case OP_DUMMY_USE:
4025                 case OP_DUMMY_STORE:
4026                 case OP_DUMMY_ICONST:
4027                 case OP_DUMMY_R8CONST:
4028                 case OP_NOT_REACHED:
4029                 case OP_NOT_NULL:
4030                         break;
4031                 case OP_IL_SEQ_POINT:
4032                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4033                         break;
4034                 case OP_SEQ_POINT: {
4035                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4036                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4037                                 guint8 *label;
4038
4039                                 /* Load ss_tramp_var */
4040                                 /* This is equal to &ss_trampoline */
4041                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4042                                 /* Load the trampoline address */
4043                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4044                                 /* Call it if it is non-null */
4045                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4046                                 label = code;
4047                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4048                                 amd64_call_reg (code, AMD64_R11);
4049                                 amd64_patch (label, code);
4050                         }
4051
4052                         /*
4053                          * This is the address which is saved in seq points,
4054                          */
4055                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4056
4057                         if (cfg->compile_aot) {
4058                                 guint32 offset = code - cfg->native_code;
4059                                 guint32 val;
4060                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4061                                 guint8 *label;
4062
4063                                 /* Load info var */
4064                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4065                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4066                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4067                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4068                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4069                                 label = code;
4070                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4071                                 /* Call the trampoline */
4072                                 amd64_call_reg (code, AMD64_R11);
4073                                 amd64_patch (label, code);
4074                         } else {
4075                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4076                                 guint8 *label;
4077
4078                                 /*
4079                                  * Emit a test+branch against a constant, the constant will be overwritten
4080                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4081                                  */
4082                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4083                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4084                                 label = code;
4085                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4086
4087                                 g_assert (var);
4088                                 g_assert (var->opcode == OP_REGOFFSET);
4089                                 /* Load bp_tramp_var */
4090                                 /* This is equal to &bp_trampoline */
4091                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4092                                 /* Call the trampoline */
4093                                 amd64_call_membase (code, AMD64_R11, 0);
4094                                 amd64_patch (label, code);
4095                         }
4096                         /*
4097                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4098                          * to another IL offset.
4099                          */
4100                         x86_nop (code);
4101                         break;
4102                 }
4103                 case OP_ADDCC:
4104                 case OP_LADDCC:
4105                 case OP_LADD:
4106                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4107                         break;
4108                 case OP_ADC:
4109                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4110                         break;
4111                 case OP_ADD_IMM:
4112                 case OP_LADD_IMM:
4113                         g_assert (amd64_is_imm32 (ins->inst_imm));
4114                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4115                         break;
4116                 case OP_ADC_IMM:
4117                         g_assert (amd64_is_imm32 (ins->inst_imm));
4118                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4119                         break;
4120                 case OP_SUBCC:
4121                 case OP_LSUBCC:
4122                 case OP_LSUB:
4123                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4124                         break;
4125                 case OP_SBB:
4126                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4127                         break;
4128                 case OP_SUB_IMM:
4129                 case OP_LSUB_IMM:
4130                         g_assert (amd64_is_imm32 (ins->inst_imm));
4131                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4132                         break;
4133                 case OP_SBB_IMM:
4134                         g_assert (amd64_is_imm32 (ins->inst_imm));
4135                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4136                         break;
4137                 case OP_LAND:
4138                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4139                         break;
4140                 case OP_AND_IMM:
4141                 case OP_LAND_IMM:
4142                         g_assert (amd64_is_imm32 (ins->inst_imm));
4143                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4144                         break;
4145                 case OP_LMUL:
4146                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4147                         break;
4148                 case OP_MUL_IMM:
4149                 case OP_LMUL_IMM:
4150                 case OP_IMUL_IMM: {
4151                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4152
4153                         switch (ins->inst_imm) {
4154                         case 2:
4155                                 /* MOV r1, r2 */
4156                                 /* ADD r1, r1 */
4157                                 if (ins->dreg != ins->sreg1)
4158                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4159                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4160                                 break;
4161                         case 3:
4162                                 /* LEA r1, [r2 + r2*2] */
4163                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4164                                 break;
4165                         case 5:
4166                                 /* LEA r1, [r2 + r2*4] */
4167                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4168                                 break;
4169                         case 6:
4170                                 /* LEA r1, [r2 + r2*2] */
4171                                 /* ADD r1, r1          */
4172                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4173                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4174                                 break;
4175                         case 9:
4176                                 /* LEA r1, [r2 + r2*8] */
4177                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4178                                 break;
4179                         case 10:
4180                                 /* LEA r1, [r2 + r2*4] */
4181                                 /* ADD r1, r1          */
4182                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4183                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4184                                 break;
4185                         case 12:
4186                                 /* LEA r1, [r2 + r2*2] */
4187                                 /* SHL r1, 2           */
4188                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4189                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4190                                 break;
4191                         case 25:
4192                                 /* LEA r1, [r2 + r2*4] */
4193                                 /* LEA r1, [r1 + r1*4] */
4194                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4195                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4196                                 break;
4197                         case 100:
4198                                 /* LEA r1, [r2 + r2*4] */
4199                                 /* SHL r1, 2           */
4200                                 /* LEA r1, [r1 + r1*4] */
4201                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4202                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4203                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4204                                 break;
4205                         default:
4206                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4207                                 break;
4208                         }
4209                         break;
4210                 }
4211                 case OP_LDIV:
4212                 case OP_LREM:
4213                         /* Regalloc magic makes the div/rem cases the same */
4214                         if (ins->sreg2 == AMD64_RDX) {
4215                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4216                                 amd64_cdq (code);
4217                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4218                         } else {
4219                                 amd64_cdq (code);
4220                                 amd64_div_reg (code, ins->sreg2, TRUE);
4221                         }
4222                         break;
4223                 case OP_LDIV_UN:
4224                 case OP_LREM_UN:
4225                         if (ins->sreg2 == AMD64_RDX) {
4226                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4227                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4228                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4229                         } else {
4230                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4231                                 amd64_div_reg (code, ins->sreg2, FALSE);
4232                         }
4233                         break;
4234                 case OP_IDIV:
4235                 case OP_IREM:
4236                         if (ins->sreg2 == AMD64_RDX) {
4237                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4238                                 amd64_cdq_size (code, 4);
4239                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4240                         } else {
4241                                 amd64_cdq_size (code, 4);
4242                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4243                         }
4244                         break;
4245                 case OP_IDIV_UN:
4246                 case OP_IREM_UN:
4247                         if (ins->sreg2 == AMD64_RDX) {
4248                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4249                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4250                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4251                         } else {
4252                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4253                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4254                         }
4255                         break;
4256                 case OP_LMUL_OVF:
4257                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4258                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4259                         break;
4260                 case OP_LOR:
4261                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4262                         break;
4263                 case OP_OR_IMM:
4264                 case OP_LOR_IMM:
4265                         g_assert (amd64_is_imm32 (ins->inst_imm));
4266                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4267                         break;
4268                 case OP_LXOR:
4269                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4270                         break;
4271                 case OP_XOR_IMM:
4272                 case OP_LXOR_IMM:
4273                         g_assert (amd64_is_imm32 (ins->inst_imm));
4274                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4275                         break;
4276                 case OP_LSHL:
4277                         g_assert (ins->sreg2 == AMD64_RCX);
4278                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4279                         break;
4280                 case OP_LSHR:
4281                         g_assert (ins->sreg2 == AMD64_RCX);
4282                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4283                         break;
4284                 case OP_SHR_IMM:
4285                 case OP_LSHR_IMM:
4286                         g_assert (amd64_is_imm32 (ins->inst_imm));
4287                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4288                         break;
4289                 case OP_SHR_UN_IMM:
4290                         g_assert (amd64_is_imm32 (ins->inst_imm));
4291                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4292                         break;
4293                 case OP_LSHR_UN_IMM:
4294                         g_assert (amd64_is_imm32 (ins->inst_imm));
4295                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4296                         break;
4297                 case OP_LSHR_UN:
4298                         g_assert (ins->sreg2 == AMD64_RCX);
4299                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4300                         break;
4301                 case OP_SHL_IMM:
4302                 case OP_LSHL_IMM:
4303                         g_assert (amd64_is_imm32 (ins->inst_imm));
4304                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4305                         break;
4306
4307                 case OP_IADDCC:
4308                 case OP_IADD:
4309                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4310                         break;
4311                 case OP_IADC:
4312                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4313                         break;
4314                 case OP_IADD_IMM:
4315                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4316                         break;
4317                 case OP_IADC_IMM:
4318                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4319                         break;
4320                 case OP_ISUBCC:
4321                 case OP_ISUB:
4322                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4323                         break;
4324                 case OP_ISBB:
4325                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4326                         break;
4327                 case OP_ISUB_IMM:
4328                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4329                         break;
4330                 case OP_ISBB_IMM:
4331                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4332                         break;
4333                 case OP_IAND:
4334                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4335                         break;
4336                 case OP_IAND_IMM:
4337                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4338                         break;
4339                 case OP_IOR:
4340                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4341                         break;
4342                 case OP_IOR_IMM:
4343                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4344                         break;
4345                 case OP_IXOR:
4346                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4347                         break;
4348                 case OP_IXOR_IMM:
4349                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4350                         break;
4351                 case OP_INEG:
4352                         amd64_neg_reg_size (code, ins->sreg1, 4);
4353                         break;
4354                 case OP_INOT:
4355                         amd64_not_reg_size (code, ins->sreg1, 4);
4356                         break;
4357                 case OP_ISHL:
4358                         g_assert (ins->sreg2 == AMD64_RCX);
4359                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4360                         break;
4361                 case OP_ISHR:
4362                         g_assert (ins->sreg2 == AMD64_RCX);
4363                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4364                         break;
4365                 case OP_ISHR_IMM:
4366                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4367                         break;
4368                 case OP_ISHR_UN_IMM:
4369                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4370                         break;
4371                 case OP_ISHR_UN:
4372                         g_assert (ins->sreg2 == AMD64_RCX);
4373                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4374                         break;
4375                 case OP_ISHL_IMM:
4376                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4377                         break;
4378                 case OP_IMUL:
4379                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4380                         break;
4381                 case OP_IMUL_OVF:
4382                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4383                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4384                         break;
4385                 case OP_IMUL_OVF_UN:
4386                 case OP_LMUL_OVF_UN: {
4387                         /* the mul operation and the exception check should most likely be split */
4388                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4389                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4390                         /*g_assert (ins->sreg2 == X86_EAX);
4391                         g_assert (ins->dreg == X86_EAX);*/
4392                         if (ins->sreg2 == X86_EAX) {
4393                                 non_eax_reg = ins->sreg1;
4394                         } else if (ins->sreg1 == X86_EAX) {
4395                                 non_eax_reg = ins->sreg2;
4396                         } else {
4397                                 /* no need to save since we're going to store to it anyway */
4398                                 if (ins->dreg != X86_EAX) {
4399                                         saved_eax = TRUE;
4400                                         amd64_push_reg (code, X86_EAX);
4401                                 }
4402                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4403                                 non_eax_reg = ins->sreg2;
4404                         }
4405                         if (ins->dreg == X86_EDX) {
4406                                 if (!saved_eax) {
4407                                         saved_eax = TRUE;
4408                                         amd64_push_reg (code, X86_EAX);
4409                                 }
4410                         } else {
4411                                 saved_edx = TRUE;
4412                                 amd64_push_reg (code, X86_EDX);
4413                         }
4414                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4415                         /* save before the check since pop and mov don't change the flags */
4416                         if (ins->dreg != X86_EAX)
4417                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4418                         if (saved_edx)
4419                                 amd64_pop_reg (code, X86_EDX);
4420                         if (saved_eax)
4421                                 amd64_pop_reg (code, X86_EAX);
4422                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4423                         break;
4424                 }
4425                 case OP_ICOMPARE:
4426                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4427                         break;
4428                 case OP_ICOMPARE_IMM:
4429                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4430                         break;
4431                 case OP_IBEQ:
4432                 case OP_IBLT:
4433                 case OP_IBGT:
4434                 case OP_IBGE:
4435                 case OP_IBLE:
4436                 case OP_LBEQ:
4437                 case OP_LBLT:
4438                 case OP_LBGT:
4439                 case OP_LBGE:
4440                 case OP_LBLE:
4441                 case OP_IBNE_UN:
4442                 case OP_IBLT_UN:
4443                 case OP_IBGT_UN:
4444                 case OP_IBGE_UN:
4445                 case OP_IBLE_UN:
4446                 case OP_LBNE_UN:
4447                 case OP_LBLT_UN:
4448                 case OP_LBGT_UN:
4449                 case OP_LBGE_UN:
4450                 case OP_LBLE_UN:
4451                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4452                         break;
4453
4454                 case OP_CMOV_IEQ:
4455                 case OP_CMOV_IGE:
4456                 case OP_CMOV_IGT:
4457                 case OP_CMOV_ILE:
4458                 case OP_CMOV_ILT:
4459                 case OP_CMOV_INE_UN:
4460                 case OP_CMOV_IGE_UN:
4461                 case OP_CMOV_IGT_UN:
4462                 case OP_CMOV_ILE_UN:
4463                 case OP_CMOV_ILT_UN:
4464                 case OP_CMOV_LEQ:
4465                 case OP_CMOV_LGE:
4466                 case OP_CMOV_LGT:
4467                 case OP_CMOV_LLE:
4468                 case OP_CMOV_LLT:
4469                 case OP_CMOV_LNE_UN:
4470                 case OP_CMOV_LGE_UN:
4471                 case OP_CMOV_LGT_UN:
4472                 case OP_CMOV_LLE_UN:
4473                 case OP_CMOV_LLT_UN:
4474                         g_assert (ins->dreg == ins->sreg1);
4475                         /* This needs to operate on 64 bit values */
4476                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4477                         break;
4478
4479                 case OP_LNOT:
4480                         amd64_not_reg (code, ins->sreg1);
4481                         break;
4482                 case OP_LNEG:
4483                         amd64_neg_reg (code, ins->sreg1);
4484                         break;
4485
4486                 case OP_ICONST:
4487                 case OP_I8CONST:
4488                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4489                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4490                         else
4491                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4492                         break;
4493                 case OP_AOTCONST:
4494                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4495                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4496                         break;
4497                 case OP_JUMP_TABLE:
4498                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4499                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4500                         break;
4501                 case OP_MOVE:
4502                         if (ins->dreg != ins->sreg1)
4503                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4504                         break;
4505                 case OP_AMD64_SET_XMMREG_R4: {
4506                         if (cfg->r4fp) {
4507                                 if (ins->dreg != ins->sreg1)
4508                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4509                         } else {
4510                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4511                         }
4512                         break;
4513                 }
4514                 case OP_AMD64_SET_XMMREG_R8: {
4515                         if (ins->dreg != ins->sreg1)
4516                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4517                         break;
4518                 }
4519                 case OP_TAILCALL: {
4520                         MonoCallInst *call = (MonoCallInst*)ins;
4521                         int i, save_area_offset;
4522
4523                         g_assert (!cfg->method->save_lmf);
4524
4525                         /* Restore callee saved registers */
4526                         save_area_offset = cfg->arch.reg_save_area_offset;
4527                         for (i = 0; i < AMD64_NREG; ++i)
4528                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4529                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4530                                         save_area_offset += 8;
4531                                 }
4532
4533                         if (cfg->arch.omit_fp) {
4534                                 if (cfg->arch.stack_alloc_size)
4535                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4536                                 // FIXME:
4537                                 if (call->stack_usage)
4538                                         NOT_IMPLEMENTED;
4539                         } else {
4540                                 /* Copy arguments on the stack to our argument area */
4541                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4542                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4543                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4544                                 }
4545
4546                                 amd64_leave (code);
4547                         }
4548
4549                         offset = code - cfg->native_code;
4550                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4551                         if (cfg->compile_aot)
4552                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4553                         else
4554                                 amd64_set_reg_template (code, AMD64_R11);
4555                         amd64_jump_reg (code, AMD64_R11);
4556                         ins->flags |= MONO_INST_GC_CALLSITE;
4557                         ins->backend.pc_offset = code - cfg->native_code;
4558                         break;
4559                 }
4560                 case OP_CHECK_THIS:
4561                         /* ensure ins->sreg1 is not NULL */
4562                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4563                         break;
4564                 case OP_ARGLIST: {
4565                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4566                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4567                         break;
4568                 }
4569                 case OP_CALL:
4570                 case OP_FCALL:
4571                 case OP_RCALL:
4572                 case OP_LCALL:
4573                 case OP_VCALL:
4574                 case OP_VCALL2:
4575                 case OP_VOIDCALL:
4576                         call = (MonoCallInst*)ins;
4577                         /*
4578                          * The AMD64 ABI forces callers to know about varargs.
4579                          */
4580                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4581                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4582                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4583                                 /*
4584                                  * Since the unmanaged calling convention doesn't contain a
4585                                  * 'vararg' entry, we have to treat every pinvoke call as a
4586                                  * potential vararg call.
4587                                  */
4588                                 guint32 nregs, i;
4589                                 nregs = 0;
4590                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4591                                         if (call->used_fregs & (1 << i))
4592                                                 nregs ++;
4593                                 if (!nregs)
4594                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4595                                 else
4596                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4597                         }
4598
4599                         if (ins->flags & MONO_INST_HAS_METHOD)
4600                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4601                         else
4602                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4603                         ins->flags |= MONO_INST_GC_CALLSITE;
4604                         ins->backend.pc_offset = code - cfg->native_code;
4605                         code = emit_move_return_value (cfg, ins, code);
4606                         break;
4607                 case OP_FCALL_REG:
4608                 case OP_RCALL_REG:
4609                 case OP_LCALL_REG:
4610                 case OP_VCALL_REG:
4611                 case OP_VCALL2_REG:
4612                 case OP_VOIDCALL_REG:
4613                 case OP_CALL_REG:
4614                         call = (MonoCallInst*)ins;
4615
4616                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4617                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4618                                 ins->sreg1 = AMD64_R11;
4619                         }
4620
4621                         /*
4622                          * The AMD64 ABI forces callers to know about varargs.
4623                          */
4624                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4625                                 if (ins->sreg1 == AMD64_RAX) {
4626                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4627                                         ins->sreg1 = AMD64_R11;
4628                                 }
4629                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4630                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4631                                 /*
4632                                  * Since the unmanaged calling convention doesn't contain a
4633                                  * 'vararg' entry, we have to treat every pinvoke call as a
4634                                  * potential vararg call.
4635                                  */
4636                                 guint32 nregs, i;
4637                                 nregs = 0;
4638                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4639                                         if (call->used_fregs & (1 << i))
4640                                                 nregs ++;
4641                                 if (ins->sreg1 == AMD64_RAX) {
4642                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4643                                         ins->sreg1 = AMD64_R11;
4644                                 }
4645                                 if (!nregs)
4646                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4647                                 else
4648                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4649                         }
4650
4651                         amd64_call_reg (code, ins->sreg1);
4652                         ins->flags |= MONO_INST_GC_CALLSITE;
4653                         ins->backend.pc_offset = code - cfg->native_code;
4654                         code = emit_move_return_value (cfg, ins, code);
4655                         break;
4656                 case OP_FCALL_MEMBASE:
4657                 case OP_RCALL_MEMBASE:
4658                 case OP_LCALL_MEMBASE:
4659                 case OP_VCALL_MEMBASE:
4660                 case OP_VCALL2_MEMBASE:
4661                 case OP_VOIDCALL_MEMBASE:
4662                 case OP_CALL_MEMBASE:
4663                         call = (MonoCallInst*)ins;
4664
4665                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4666                         ins->flags |= MONO_INST_GC_CALLSITE;
4667                         ins->backend.pc_offset = code - cfg->native_code;
4668                         code = emit_move_return_value (cfg, ins, code);
4669                         break;
4670                 case OP_DYN_CALL: {
4671                         int i;
4672                         MonoInst *var = cfg->dyn_call_var;
4673                         guint8 *label;
4674
4675                         g_assert (var->opcode == OP_REGOFFSET);
4676
4677                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4678                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4679                         /* r10 = ftn */
4680                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4681
4682                         /* Save args buffer */
4683                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4684
4685                         /* Set fp arg regs */
4686                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4687                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4688                         label = code;
4689                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4690                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4691                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4692                         amd64_patch (label, code);
4693
4694                         /* Set stack args */
4695                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4696                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4697                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4698                         }
4699
4700                         /* Set argument registers */
4701                         for (i = 0; i < PARAM_REGS; ++i)
4702                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4703
4704                         /* Make the call */
4705                         amd64_call_reg (code, AMD64_R10);
4706
4707                         ins->flags |= MONO_INST_GC_CALLSITE;
4708                         ins->backend.pc_offset = code - cfg->native_code;
4709
4710                         /* Save result */
4711                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4712                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4713                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4714                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4715                         break;
4716                 }
4717                 case OP_AMD64_SAVE_SP_TO_LMF: {
4718                         MonoInst *lmf_var = cfg->lmf_var;
4719                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4720                         break;
4721                 }
4722                 case OP_X86_PUSH:
4723                         g_assert_not_reached ();
4724                         amd64_push_reg (code, ins->sreg1);
4725                         break;
4726                 case OP_X86_PUSH_IMM:
4727                         g_assert_not_reached ();
4728                         g_assert (amd64_is_imm32 (ins->inst_imm));
4729                         amd64_push_imm (code, ins->inst_imm);
4730                         break;
4731                 case OP_X86_PUSH_MEMBASE:
4732                         g_assert_not_reached ();
4733                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4734                         break;
4735                 case OP_X86_PUSH_OBJ: {
4736                         int size = ALIGN_TO (ins->inst_imm, 8);
4737
4738                         g_assert_not_reached ();
4739
4740                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4741                         amd64_push_reg (code, AMD64_RDI);
4742                         amd64_push_reg (code, AMD64_RSI);
4743                         amd64_push_reg (code, AMD64_RCX);
4744                         if (ins->inst_offset)
4745                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4746                         else
4747                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4748                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4749                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4750                         amd64_cld (code);
4751                         amd64_prefix (code, X86_REP_PREFIX);
4752                         amd64_movsd (code);
4753                         amd64_pop_reg (code, AMD64_RCX);
4754                         amd64_pop_reg (code, AMD64_RSI);
4755                         amd64_pop_reg (code, AMD64_RDI);
4756                         break;
4757                 }
4758                 case OP_GENERIC_CLASS_INIT: {
4759                         guint8 *jump;
4760
4761                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4762
4763                         amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4764                         jump = code;
4765                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4766
4767                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4768                         ins->flags |= MONO_INST_GC_CALLSITE;
4769                         ins->backend.pc_offset = code - cfg->native_code;
4770
4771                         x86_patch (jump, code);
4772                         break;
4773                 }
4774
4775                 case OP_X86_LEA:
4776                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4777                         break;
4778                 case OP_X86_LEA_MEMBASE:
4779                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4780                         break;
4781                 case OP_X86_XCHG:
4782                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4783                         break;
4784                 case OP_LOCALLOC:
4785                         /* keep alignment */
4786                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4787                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4788                         code = mono_emit_stack_alloc (cfg, code, ins);
4789                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4790                         if (cfg->param_area)
4791                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4792                         break;
4793                 case OP_LOCALLOC_IMM: {
4794                         guint32 size = ins->inst_imm;
4795                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4796
4797                         if (ins->flags & MONO_INST_INIT) {
4798                                 if (size < 64) {
4799                                         int i;
4800
4801                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4802                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4803
4804                                         for (i = 0; i < size; i += 8)
4805                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4806                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4807                                 } else {
4808                                         amd64_mov_reg_imm (code, ins->dreg, size);
4809                                         ins->sreg1 = ins->dreg;
4810
4811                                         code = mono_emit_stack_alloc (cfg, code, ins);
4812                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4813                                 }
4814                         } else {
4815                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4816                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4817                         }
4818                         if (cfg->param_area)
4819                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4820                         break;
4821                 }
4822                 case OP_THROW: {
4823                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4824                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4825                                              (gpointer)"mono_arch_throw_exception", FALSE);
4826                         ins->flags |= MONO_INST_GC_CALLSITE;
4827                         ins->backend.pc_offset = code - cfg->native_code;
4828                         break;
4829                 }
4830                 case OP_RETHROW: {
4831                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4832                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4833                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4834                         ins->flags |= MONO_INST_GC_CALLSITE;
4835                         ins->backend.pc_offset = code - cfg->native_code;
4836                         break;
4837                 }
4838                 case OP_CALL_HANDLER:
4839                         /* Align stack */
4840                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4841                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4842                         amd64_call_imm (code, 0);
4843                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4844                         /* Restore stack alignment */
4845                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4846                         break;
4847                 case OP_START_HANDLER: {
4848                         /* Even though we're saving RSP, use sizeof */
4849                         /* gpointer because spvar is of type IntPtr */
4850                         /* see: mono_create_spvar_for_region */
4851                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4852                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4853
4854                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4855                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4856                                 cfg->param_area) {
4857                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4858                         }
4859                         break;
4860                 }
4861                 case OP_ENDFINALLY: {
4862                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4863                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4864                         amd64_ret (code);
4865                         break;
4866                 }
4867                 case OP_ENDFILTER: {
4868                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4869                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4870                         /* The local allocator will put the result into RAX */
4871                         amd64_ret (code);
4872                         break;
4873                 }
4874                 case OP_GET_EX_OBJ:
4875                         if (ins->dreg != AMD64_RAX)
4876                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4877                         break;
4878                 case OP_LABEL:
4879                         ins->inst_c0 = code - cfg->native_code;
4880                         break;
4881                 case OP_BR:
4882                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4883                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4884                         //break;
4885                                 if (ins->inst_target_bb->native_offset) {
4886                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4887                                 } else {
4888                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4889                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4890                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4891                                                 x86_jump8 (code, 0);
4892                                         else
4893                                                 x86_jump32 (code, 0);
4894                         }
4895                         break;
4896                 case OP_BR_REG:
4897                         amd64_jump_reg (code, ins->sreg1);
4898                         break;
4899                 case OP_ICNEQ:
4900                 case OP_ICGE:
4901                 case OP_ICLE:
4902                 case OP_ICGE_UN:
4903                 case OP_ICLE_UN:
4904
4905                 case OP_CEQ:
4906                 case OP_LCEQ:
4907                 case OP_ICEQ:
4908                 case OP_CLT:
4909                 case OP_LCLT:
4910                 case OP_ICLT:
4911                 case OP_CGT:
4912                 case OP_ICGT:
4913                 case OP_LCGT:
4914                 case OP_CLT_UN:
4915                 case OP_LCLT_UN:
4916                 case OP_ICLT_UN:
4917                 case OP_CGT_UN:
4918                 case OP_LCGT_UN:
4919                 case OP_ICGT_UN:
4920                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4921                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4922                         break;
4923                 case OP_COND_EXC_EQ:
4924                 case OP_COND_EXC_NE_UN:
4925                 case OP_COND_EXC_LT:
4926                 case OP_COND_EXC_LT_UN:
4927                 case OP_COND_EXC_GT:
4928                 case OP_COND_EXC_GT_UN:
4929                 case OP_COND_EXC_GE:
4930                 case OP_COND_EXC_GE_UN:
4931                 case OP_COND_EXC_LE:
4932                 case OP_COND_EXC_LE_UN:
4933                 case OP_COND_EXC_IEQ:
4934                 case OP_COND_EXC_INE_UN:
4935                 case OP_COND_EXC_ILT:
4936                 case OP_COND_EXC_ILT_UN:
4937                 case OP_COND_EXC_IGT:
4938                 case OP_COND_EXC_IGT_UN:
4939                 case OP_COND_EXC_IGE:
4940                 case OP_COND_EXC_IGE_UN:
4941                 case OP_COND_EXC_ILE:
4942                 case OP_COND_EXC_ILE_UN:
4943                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4944                         break;
4945                 case OP_COND_EXC_OV:
4946                 case OP_COND_EXC_NO:
4947                 case OP_COND_EXC_C:
4948                 case OP_COND_EXC_NC:
4949                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4950                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4951                         break;
4952                 case OP_COND_EXC_IOV:
4953                 case OP_COND_EXC_INO:
4954                 case OP_COND_EXC_IC:
4955                 case OP_COND_EXC_INC:
4956                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4957                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4958                         break;
4959
4960                 /* floating point opcodes */
4961                 case OP_R8CONST: {
4962                         double d = *(double *)ins->inst_p0;
4963
4964                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4965                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4966                         }
4967                         else {
4968                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4969                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4970                         }
4971                         break;
4972                 }
4973                 case OP_R4CONST: {
4974                         float f = *(float *)ins->inst_p0;
4975
4976                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4977                                 if (cfg->r4fp)
4978                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4979                                 else
4980                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4981                         }
4982                         else {
4983                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4984                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4985                                 if (!cfg->r4fp)
4986                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4987                         }
4988                         break;
4989                 }
4990                 case OP_STORER8_MEMBASE_REG:
4991                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4992                         break;
4993                 case OP_LOADR8_MEMBASE:
4994                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4995                         break;
4996                 case OP_STORER4_MEMBASE_REG:
4997                         if (cfg->r4fp) {
4998                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4999                         } else {
5000                                 /* This requires a double->single conversion */
5001                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5002                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5003                         }
5004                         break;
5005                 case OP_LOADR4_MEMBASE:
5006                         if (cfg->r4fp) {
5007                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5008                         } else {
5009                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5010                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5011                         }
5012                         break;
5013                 case OP_ICONV_TO_R4:
5014                         if (cfg->r4fp) {
5015                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5016                         } else {
5017                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5018                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5019                         }
5020                         break;
5021                 case OP_ICONV_TO_R8:
5022                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5023                         break;
5024                 case OP_LCONV_TO_R4:
5025                         if (cfg->r4fp) {
5026                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5027                         } else {
5028                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5029                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5030                         }
5031                         break;
5032                 case OP_LCONV_TO_R8:
5033                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5034                         break;
5035                 case OP_FCONV_TO_R4:
5036                         if (cfg->r4fp) {
5037                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5038                         } else {
5039                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5040                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5041                         }
5042                         break;
5043                 case OP_FCONV_TO_I1:
5044                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5045                         break;
5046                 case OP_FCONV_TO_U1:
5047                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5048                         break;
5049                 case OP_FCONV_TO_I2:
5050                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5051                         break;
5052                 case OP_FCONV_TO_U2:
5053                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5054                         break;
5055                 case OP_FCONV_TO_U4:
5056                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5057                         break;
5058                 case OP_FCONV_TO_I4:
5059                 case OP_FCONV_TO_I:
5060                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5061                         break;
5062                 case OP_FCONV_TO_I8:
5063                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5064                         break;
5065
5066                 case OP_RCONV_TO_I1:
5067                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5068                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5069                         break;
5070                 case OP_RCONV_TO_U1:
5071                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5072                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5073                         break;
5074                 case OP_RCONV_TO_I2:
5075                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5076                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5077                         break;
5078                 case OP_RCONV_TO_U2:
5079                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5080                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5081                         break;
5082                 case OP_RCONV_TO_I4:
5083                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5084                         break;
5085                 case OP_RCONV_TO_U4:
5086                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5087                         break;
5088                 case OP_RCONV_TO_I8:
5089                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5090                         break;
5091                 case OP_RCONV_TO_R8:
5092                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5093                         break;
5094                 case OP_RCONV_TO_R4:
5095                         if (ins->dreg != ins->sreg1)
5096                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5097                         break;
5098
5099                 case OP_LCONV_TO_R_UN: {
5100                         guint8 *br [2];
5101
5102                         /* Based on gcc code */
5103                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5104                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5105
5106                         /* Positive case */
5107                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5108                         br [1] = code; x86_jump8 (code, 0);
5109                         amd64_patch (br [0], code);
5110
5111                         /* Negative case */
5112                         /* Save to the red zone */
5113                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5114                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5115                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5116                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5117                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5118                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5119                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5120                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5121                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5122                         /* Restore */
5123                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5124                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5125                         amd64_patch (br [1], code);
5126                         break;
5127                 }
5128                 case OP_LCONV_TO_OVF_U4:
5129                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5130                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5131                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5132                         break;
5133                 case OP_LCONV_TO_OVF_I4_UN:
5134                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5135                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5136                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5137                         break;
5138                 case OP_FMOVE:
5139                         if (ins->dreg != ins->sreg1)
5140                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5141                         break;
5142                 case OP_RMOVE:
5143                         if (ins->dreg != ins->sreg1)
5144                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5145                         break;
5146                 case OP_MOVE_F_TO_I4:
5147                         if (cfg->r4fp) {
5148                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5149                         } else {
5150                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5151                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5152                         }
5153                         break;
5154                 case OP_MOVE_I4_TO_F:
5155                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5156                         if (!cfg->r4fp)
5157                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5158                         break;
5159                 case OP_MOVE_F_TO_I8:
5160                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5161                         break;
5162                 case OP_MOVE_I8_TO_F:
5163                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5164                         break;
5165                 case OP_FADD:
5166                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5167                         break;
5168                 case OP_FSUB:
5169                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5170                         break;
5171                 case OP_FMUL:
5172                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5173                         break;
5174                 case OP_FDIV:
5175                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5176                         break;
5177                 case OP_FNEG: {
5178                         static double r8_0 = -0.0;
5179
5180                         g_assert (ins->sreg1 == ins->dreg);
5181
5182                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5183                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5184                         break;
5185                 }
5186                 case OP_SIN:
5187                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5188                         break;
5189                 case OP_COS:
5190                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5191                         break;
5192                 case OP_ABS: {
5193                         static guint64 d = 0x7fffffffffffffffUL;
5194
5195                         g_assert (ins->sreg1 == ins->dreg);
5196
5197                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5198                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5199                         break;
5200                 }
5201                 case OP_SQRT:
5202                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5203                         break;
5204
5205                 case OP_RADD:
5206                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5207                         break;
5208                 case OP_RSUB:
5209                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5210                         break;
5211                 case OP_RMUL:
5212                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5213                         break;
5214                 case OP_RDIV:
5215                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5216                         break;
5217                 case OP_RNEG: {
5218                         static float r4_0 = -0.0;
5219
5220                         g_assert (ins->sreg1 == ins->dreg);
5221
5222                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5223                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5224                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5225                         break;
5226                 }
5227
5228                 case OP_IMIN:
5229                         g_assert (cfg->opt & MONO_OPT_CMOV);
5230                         g_assert (ins->dreg == ins->sreg1);
5231                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5232                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5233                         break;
5234                 case OP_IMIN_UN:
5235                         g_assert (cfg->opt & MONO_OPT_CMOV);
5236                         g_assert (ins->dreg == ins->sreg1);
5237                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5238                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5239                         break;
5240                 case OP_IMAX:
5241                         g_assert (cfg->opt & MONO_OPT_CMOV);
5242                         g_assert (ins->dreg == ins->sreg1);
5243                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5244                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5245                         break;
5246                 case OP_IMAX_UN:
5247                         g_assert (cfg->opt & MONO_OPT_CMOV);
5248                         g_assert (ins->dreg == ins->sreg1);
5249                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5250                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5251                         break;
5252                 case OP_LMIN:
5253                         g_assert (cfg->opt & MONO_OPT_CMOV);
5254                         g_assert (ins->dreg == ins->sreg1);
5255                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5256                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5257                         break;
5258                 case OP_LMIN_UN:
5259                         g_assert (cfg->opt & MONO_OPT_CMOV);
5260                         g_assert (ins->dreg == ins->sreg1);
5261                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5262                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5263                         break;
5264                 case OP_LMAX:
5265                         g_assert (cfg->opt & MONO_OPT_CMOV);
5266                         g_assert (ins->dreg == ins->sreg1);
5267                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5268                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5269                         break;
5270                 case OP_LMAX_UN:
5271                         g_assert (cfg->opt & MONO_OPT_CMOV);
5272                         g_assert (ins->dreg == ins->sreg1);
5273                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5274                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5275                         break;
5276                 case OP_X86_FPOP:
5277                         break;
5278                 case OP_FCOMPARE:
5279                         /*
5280                          * The two arguments are swapped because the fbranch instructions
5281                          * depend on this for the non-sse case to work.
5282                          */
5283                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5284                         break;
5285                 case OP_RCOMPARE:
5286                         /*
5287                          * FIXME: Get rid of this.
5288                          * The two arguments are swapped because the fbranch instructions
5289                          * depend on this for the non-sse case to work.
5290                          */
5291                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5292                         break;
5293                 case OP_FCNEQ:
5294                 case OP_FCEQ: {
5295                         /* zeroing the register at the start results in
5296                          * shorter and faster code (we can also remove the widening op)
5297                          */
5298                         guchar *unordered_check;
5299
5300                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5301                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5302                         unordered_check = code;
5303                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5304
5305                         if (ins->opcode == OP_FCEQ) {
5306                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5307                                 amd64_patch (unordered_check, code);
5308                         } else {
5309                                 guchar *jump_to_end;
5310                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5311                                 jump_to_end = code;
5312                                 x86_jump8 (code, 0);
5313                                 amd64_patch (unordered_check, code);
5314                                 amd64_inc_reg (code, ins->dreg);
5315                                 amd64_patch (jump_to_end, code);
5316                         }
5317                         break;
5318                 }
5319                 case OP_FCLT:
5320                 case OP_FCLT_UN: {
5321                         /* zeroing the register at the start results in
5322                          * shorter and faster code (we can also remove the widening op)
5323                          */
5324                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5325                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5326                         if (ins->opcode == OP_FCLT_UN) {
5327                                 guchar *unordered_check = code;
5328                                 guchar *jump_to_end;
5329                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5330                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5331                                 jump_to_end = code;
5332                                 x86_jump8 (code, 0);
5333                                 amd64_patch (unordered_check, code);
5334                                 amd64_inc_reg (code, ins->dreg);
5335                                 amd64_patch (jump_to_end, code);
5336                         } else {
5337                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5338                         }
5339                         break;
5340                 }
5341                 case OP_FCLE: {
5342                         guchar *unordered_check;
5343                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5344                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5345                         unordered_check = code;
5346                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5347                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5348                         amd64_patch (unordered_check, code);
5349                         break;
5350                 }
5351                 case OP_FCGT:
5352                 case OP_FCGT_UN: {
5353                         /* zeroing the register at the start results in
5354                          * shorter and faster code (we can also remove the widening op)
5355                          */
5356                         guchar *unordered_check;
5357
5358                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5359                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5360                         if (ins->opcode == OP_FCGT) {
5361                                 unordered_check = code;
5362                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5363                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5364                                 amd64_patch (unordered_check, code);
5365                         } else {
5366                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5367                         }
5368                         break;
5369                 }
5370                 case OP_FCGE: {
5371                         guchar *unordered_check;
5372                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5373                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5374                         unordered_check = code;
5375                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5376                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5377                         amd64_patch (unordered_check, code);
5378                         break;
5379                 }
5380
5381                 case OP_RCEQ:
5382                 case OP_RCGT:
5383                 case OP_RCLT:
5384                 case OP_RCLT_UN:
5385                 case OP_RCGT_UN: {
5386                         int x86_cond;
5387                         gboolean unordered = FALSE;
5388
5389                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5390                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5391
5392                         switch (ins->opcode) {
5393                         case OP_RCEQ:
5394                                 x86_cond = X86_CC_EQ;
5395                                 break;
5396                         case OP_RCGT:
5397                                 x86_cond = X86_CC_LT;
5398                                 break;
5399                         case OP_RCLT:
5400                                 x86_cond = X86_CC_GT;
5401                                 break;
5402                         case OP_RCLT_UN:
5403                                 x86_cond = X86_CC_GT;
5404                                 unordered = TRUE;
5405                                 break;
5406                         case OP_RCGT_UN:
5407                                 x86_cond = X86_CC_LT;
5408                                 unordered = TRUE;
5409                                 break;
5410                         default:
5411                                 g_assert_not_reached ();
5412                                 break;
5413                         }
5414
5415                         if (unordered) {
5416                                 guchar *unordered_check;
5417                                 guchar *jump_to_end;
5418
5419                                 unordered_check = code;
5420                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5421                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5422                                 jump_to_end = code;
5423                                 x86_jump8 (code, 0);
5424                                 amd64_patch (unordered_check, code);
5425                                 amd64_inc_reg (code, ins->dreg);
5426                                 amd64_patch (jump_to_end, code);
5427                         } else {
5428                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5429                         }
5430                         break;
5431                 }
5432                 case OP_FCLT_MEMBASE:
5433                 case OP_FCGT_MEMBASE:
5434                 case OP_FCLT_UN_MEMBASE:
5435                 case OP_FCGT_UN_MEMBASE:
5436                 case OP_FCEQ_MEMBASE: {
5437                         guchar *unordered_check, *jump_to_end;
5438                         int x86_cond;
5439
5440                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5441                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5442
5443                         switch (ins->opcode) {
5444                         case OP_FCEQ_MEMBASE:
5445                                 x86_cond = X86_CC_EQ;
5446                                 break;
5447                         case OP_FCLT_MEMBASE:
5448                         case OP_FCLT_UN_MEMBASE:
5449                                 x86_cond = X86_CC_LT;
5450                                 break;
5451                         case OP_FCGT_MEMBASE:
5452                         case OP_FCGT_UN_MEMBASE:
5453                                 x86_cond = X86_CC_GT;
5454                                 break;
5455                         default:
5456                                 g_assert_not_reached ();
5457                         }
5458
5459                         unordered_check = code;
5460                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5461                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5462
5463                         switch (ins->opcode) {
5464                         case OP_FCEQ_MEMBASE:
5465                         case OP_FCLT_MEMBASE:
5466                         case OP_FCGT_MEMBASE:
5467                                 amd64_patch (unordered_check, code);
5468                                 break;
5469                         case OP_FCLT_UN_MEMBASE:
5470                         case OP_FCGT_UN_MEMBASE:
5471                                 jump_to_end = code;
5472                                 x86_jump8 (code, 0);
5473                                 amd64_patch (unordered_check, code);
5474                                 amd64_inc_reg (code, ins->dreg);
5475                                 amd64_patch (jump_to_end, code);
5476                                 break;
5477                         default:
5478                                 break;
5479                         }
5480                         break;
5481                 }
5482                 case OP_FBEQ: {
5483                         guchar *jump = code;
5484                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5485                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5486                         amd64_patch (jump, code);
5487                         break;
5488                 }
5489                 case OP_FBNE_UN:
5490                         /* Branch if C013 != 100 */
5491                         /* branch if !ZF or (PF|CF) */
5492                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5493                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5494                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5495                         break;
5496                 case OP_FBLT:
5497                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5498                         break;
5499                 case OP_FBLT_UN:
5500                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5501                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5502                         break;
5503                 case OP_FBGT:
5504                 case OP_FBGT_UN:
5505                         if (ins->opcode == OP_FBGT) {
5506                                 guchar *br1;
5507
5508                                 /* skip branch if C1=1 */
5509                                 br1 = code;
5510                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5511                                 /* branch if (C0 | C3) = 1 */
5512                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5513                                 amd64_patch (br1, code);
5514                                 break;
5515                         } else {
5516                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5517                         }
5518                         break;
5519                 case OP_FBGE: {
5520                         /* Branch if C013 == 100 or 001 */
5521                         guchar *br1;
5522
5523                         /* skip branch if C1=1 */
5524                         br1 = code;
5525                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5526                         /* branch if (C0 | C3) = 1 */
5527                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5528                         amd64_patch (br1, code);
5529                         break;
5530                 }
5531                 case OP_FBGE_UN:
5532                         /* Branch if C013 == 000 */
5533                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5534                         break;
5535                 case OP_FBLE: {
5536                         /* Branch if C013=000 or 100 */
5537                         guchar *br1;
5538
5539                         /* skip branch if C1=1 */
5540                         br1 = code;
5541                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5542                         /* branch if C0=0 */
5543                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5544                         amd64_patch (br1, code);
5545                         break;
5546                 }
5547                 case OP_FBLE_UN:
5548                         /* Branch if C013 != 001 */
5549                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5550                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5551                         break;
5552                 case OP_CKFINITE:
5553                         /* Transfer value to the fp stack */
5554                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5555                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5556                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5557
5558                         amd64_push_reg (code, AMD64_RAX);
5559                         amd64_fxam (code);
5560                         amd64_fnstsw (code);
5561                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5562                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5563                         amd64_pop_reg (code, AMD64_RAX);
5564                         amd64_fstp (code, 0);
5565                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5566                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5567                         break;
5568                 case OP_TLS_GET: {
5569                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5570                         break;
5571                 }
5572                 case OP_TLS_SET: {
5573                         code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5574                         break;
5575                 }
5576                 case OP_MEMORY_BARRIER: {
5577                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5578                                 x86_mfence (code);
5579                         break;
5580                 }
5581                 case OP_ATOMIC_ADD_I4:
5582                 case OP_ATOMIC_ADD_I8: {
5583                         int dreg = ins->dreg;
5584                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5585
5586                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5587                                 dreg = AMD64_R11;
5588
5589                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5590                         amd64_prefix (code, X86_LOCK_PREFIX);
5591                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5592                         /* dreg contains the old value, add with sreg2 value */
5593                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5594
5595                         if (ins->dreg != dreg)
5596                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5597
5598                         break;
5599                 }
5600                 case OP_ATOMIC_EXCHANGE_I4:
5601                 case OP_ATOMIC_EXCHANGE_I8: {
5602                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5603
5604                         /* LOCK prefix is implied. */
5605                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5606                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5607                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5608                         break;
5609                 }
5610                 case OP_ATOMIC_CAS_I4:
5611                 case OP_ATOMIC_CAS_I8: {
5612                         guint32 size;
5613
5614                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5615                                 size = 8;
5616                         else
5617                                 size = 4;
5618
5619                         /*
5620                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5621                          * an explanation of how this works.
5622                          */
5623                         g_assert (ins->sreg3 == AMD64_RAX);
5624                         g_assert (ins->sreg1 != AMD64_RAX);
5625                         g_assert (ins->sreg1 != ins->sreg2);
5626
5627                         amd64_prefix (code, X86_LOCK_PREFIX);
5628                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5629
5630                         if (ins->dreg != AMD64_RAX)
5631                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5632                         break;
5633                 }
5634                 case OP_ATOMIC_LOAD_I1: {
5635                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5636                         break;
5637                 }
5638                 case OP_ATOMIC_LOAD_U1: {
5639                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5640                         break;
5641                 }
5642                 case OP_ATOMIC_LOAD_I2: {
5643                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5644                         break;
5645                 }
5646                 case OP_ATOMIC_LOAD_U2: {
5647                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5648                         break;
5649                 }
5650                 case OP_ATOMIC_LOAD_I4: {
5651                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5652                         break;
5653                 }
5654                 case OP_ATOMIC_LOAD_U4:
5655                 case OP_ATOMIC_LOAD_I8:
5656                 case OP_ATOMIC_LOAD_U8: {
5657                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5658                         break;
5659                 }
5660                 case OP_ATOMIC_LOAD_R4: {
5661                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5662                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5663                         break;
5664                 }
5665                 case OP_ATOMIC_LOAD_R8: {
5666                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5667                         break;
5668                 }
5669                 case OP_ATOMIC_STORE_I1:
5670                 case OP_ATOMIC_STORE_U1:
5671                 case OP_ATOMIC_STORE_I2:
5672                 case OP_ATOMIC_STORE_U2:
5673                 case OP_ATOMIC_STORE_I4:
5674                 case OP_ATOMIC_STORE_U4:
5675                 case OP_ATOMIC_STORE_I8:
5676                 case OP_ATOMIC_STORE_U8: {
5677                         int size;
5678
5679                         switch (ins->opcode) {
5680                         case OP_ATOMIC_STORE_I1:
5681                         case OP_ATOMIC_STORE_U1:
5682                                 size = 1;
5683                                 break;
5684                         case OP_ATOMIC_STORE_I2:
5685                         case OP_ATOMIC_STORE_U2:
5686                                 size = 2;
5687                                 break;
5688                         case OP_ATOMIC_STORE_I4:
5689                         case OP_ATOMIC_STORE_U4:
5690                                 size = 4;
5691                                 break;
5692                         case OP_ATOMIC_STORE_I8:
5693                         case OP_ATOMIC_STORE_U8:
5694                                 size = 8;
5695                                 break;
5696                         }
5697
5698                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5699
5700                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5701                                 x86_mfence (code);
5702                         break;
5703                 }
5704                 case OP_ATOMIC_STORE_R4: {
5705                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5706                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5707
5708                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5709                                 x86_mfence (code);
5710                         break;
5711                 }
5712                 case OP_ATOMIC_STORE_R8: {
5713                         x86_nop (code);
5714                         x86_nop (code);
5715                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5716                         x86_nop (code);
5717                         x86_nop (code);
5718
5719                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5720                                 x86_mfence (code);
5721                         break;
5722                 }
5723                 case OP_CARD_TABLE_WBARRIER: {
5724                         int ptr = ins->sreg1;
5725                         int value = ins->sreg2;
5726                         guchar *br = 0;
5727                         int nursery_shift, card_table_shift;
5728                         gpointer card_table_mask;
5729                         size_t nursery_size;
5730
5731                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5732                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5733                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5734
5735                         /*If either point to the stack we can simply avoid the WB. This happens due to
5736                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5737                          */
5738                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5739                                 continue;
5740
5741                         /*
5742                          * We need one register we can clobber, we choose EDX and make sreg1
5743                          * fixed EAX to work around limitations in the local register allocator.
5744                          * sreg2 might get allocated to EDX, but that is not a problem since
5745                          * we use it before clobbering EDX.
5746                          */
5747                         g_assert (ins->sreg1 == AMD64_RAX);
5748
5749                         /*
5750                          * This is the code we produce:
5751                          *
5752                          *   edx = value
5753                          *   edx >>= nursery_shift
5754                          *   cmp edx, (nursery_start >> nursery_shift)
5755                          *   jne done
5756                          *   edx = ptr
5757                          *   edx >>= card_table_shift
5758                          *   edx += cardtable
5759                          *   [edx] = 1
5760                          * done:
5761                          */
5762
5763                         if (mono_gc_card_table_nursery_check ()) {
5764                                 if (value != AMD64_RDX)
5765                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5766                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5767                                 if (shifted_nursery_start >> 31) {
5768                                         /*
5769                                          * The value we need to compare against is 64 bits, so we need
5770                                          * another spare register.  We use RBX, which we save and
5771                                          * restore.
5772                                          */
5773                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5774                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5775                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5776                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5777                                 } else {
5778                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5779                                 }
5780                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5781                         }
5782                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5783                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5784                         if (card_table_mask)
5785                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5786
5787                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5788                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5789
5790                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5791
5792                         if (mono_gc_card_table_nursery_check ())
5793                                 x86_patch (br, code);
5794                         break;
5795                 }
5796 #ifdef MONO_ARCH_SIMD_INTRINSICS
5797                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5798                 case OP_ADDPS:
5799                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5800                         break;
5801                 case OP_DIVPS:
5802                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5803                         break;
5804                 case OP_MULPS:
5805                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5806                         break;
5807                 case OP_SUBPS:
5808                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5809                         break;
5810                 case OP_MAXPS:
5811                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5812                         break;
5813                 case OP_MINPS:
5814                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5815                         break;
5816                 case OP_COMPPS:
5817                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5818                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5819                         break;
5820                 case OP_ANDPS:
5821                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5822                         break;
5823                 case OP_ANDNPS:
5824                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5825                         break;
5826                 case OP_ORPS:
5827                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5828                         break;
5829                 case OP_XORPS:
5830                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5831                         break;
5832                 case OP_SQRTPS:
5833                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5834                         break;
5835                 case OP_RSQRTPS:
5836                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5837                         break;
5838                 case OP_RCPPS:
5839                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5840                         break;
5841                 case OP_ADDSUBPS:
5842                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5843                         break;
5844                 case OP_HADDPS:
5845                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5846                         break;
5847                 case OP_HSUBPS:
5848                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5849                         break;
5850                 case OP_DUPPS_HIGH:
5851                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5852                         break;
5853                 case OP_DUPPS_LOW:
5854                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5855                         break;
5856
5857                 case OP_PSHUFLEW_HIGH:
5858                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5859                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5860                         break;
5861                 case OP_PSHUFLEW_LOW:
5862                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5863                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5864                         break;
5865                 case OP_PSHUFLED:
5866                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5867                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5868                         break;
5869                 case OP_SHUFPS:
5870                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5871                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5872                         break;
5873                 case OP_SHUFPD:
5874                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5875                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5876                         break;
5877
5878                 case OP_ADDPD:
5879                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5880                         break;
5881                 case OP_DIVPD:
5882                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5883                         break;
5884                 case OP_MULPD:
5885                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5886                         break;
5887                 case OP_SUBPD:
5888                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5889                         break;
5890                 case OP_MAXPD:
5891                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5892                         break;
5893                 case OP_MINPD:
5894                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5895                         break;
5896                 case OP_COMPPD:
5897                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5898                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5899                         break;
5900                 case OP_ANDPD:
5901                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5902                         break;
5903                 case OP_ANDNPD:
5904                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5905                         break;
5906                 case OP_ORPD:
5907                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5908                         break;
5909                 case OP_XORPD:
5910                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5911                         break;
5912                 case OP_SQRTPD:
5913                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5914                         break;
5915                 case OP_ADDSUBPD:
5916                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5917                         break;
5918                 case OP_HADDPD:
5919                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5920                         break;
5921                 case OP_HSUBPD:
5922                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5923                         break;
5924                 case OP_DUPPD:
5925                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5926                         break;
5927
5928                 case OP_EXTRACT_MASK:
5929                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5930                         break;
5931
5932                 case OP_PAND:
5933                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5934                         break;
5935                 case OP_POR:
5936                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5937                         break;
5938                 case OP_PXOR:
5939                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5940                         break;
5941
5942                 case OP_PADDB:
5943                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5944                         break;
5945                 case OP_PADDW:
5946                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 case OP_PADDD:
5949                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5950                         break;
5951                 case OP_PADDQ:
5952                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5953                         break;
5954
5955                 case OP_PSUBB:
5956                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5957                         break;
5958                 case OP_PSUBW:
5959                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5960                         break;
5961                 case OP_PSUBD:
5962                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5963                         break;
5964                 case OP_PSUBQ:
5965                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5966                         break;
5967
5968                 case OP_PMAXB_UN:
5969                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5970                         break;
5971                 case OP_PMAXW_UN:
5972                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5973                         break;
5974                 case OP_PMAXD_UN:
5975                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5976                         break;
5977
5978                 case OP_PMAXB:
5979                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5980                         break;
5981                 case OP_PMAXW:
5982                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984                 case OP_PMAXD:
5985                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5986                         break;
5987
5988                 case OP_PAVGB_UN:
5989                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5990                         break;
5991                 case OP_PAVGW_UN:
5992                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5993                         break;
5994
5995                 case OP_PMINB_UN:
5996                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998                 case OP_PMINW_UN:
5999                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_PMIND_UN:
6002                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6003                         break;
6004
6005                 case OP_PMINB:
6006                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6007                         break;
6008                 case OP_PMINW:
6009                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011                 case OP_PMIND:
6012                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014
6015                 case OP_PCMPEQB:
6016                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018                 case OP_PCMPEQW:
6019                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021                 case OP_PCMPEQD:
6022                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024                 case OP_PCMPEQQ:
6025                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027
6028                 case OP_PCMPGTB:
6029                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6030                         break;
6031                 case OP_PCMPGTW:
6032                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_PCMPGTD:
6035                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_PCMPGTQ:
6038                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040
6041                 case OP_PSUM_ABS_DIFF:
6042                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044
6045                 case OP_UNPACK_LOWB:
6046                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6047                         break;
6048                 case OP_UNPACK_LOWW:
6049                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051                 case OP_UNPACK_LOWD:
6052                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054                 case OP_UNPACK_LOWQ:
6055                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_UNPACK_LOWPS:
6058                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060                 case OP_UNPACK_LOWPD:
6061                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063
6064                 case OP_UNPACK_HIGHB:
6065                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067                 case OP_UNPACK_HIGHW:
6068                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_UNPACK_HIGHD:
6071                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_UNPACK_HIGHQ:
6074                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076                 case OP_UNPACK_HIGHPS:
6077                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079                 case OP_UNPACK_HIGHPD:
6080                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082
6083                 case OP_PACKW:
6084                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6085                         break;
6086                 case OP_PACKD:
6087                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089                 case OP_PACKW_UN:
6090                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_PACKD_UN:
6093                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095
6096                 case OP_PADDB_SAT_UN:
6097                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099                 case OP_PSUBB_SAT_UN:
6100                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102                 case OP_PADDW_SAT_UN:
6103                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105                 case OP_PSUBW_SAT_UN:
6106                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6107                         break;
6108
6109                 case OP_PADDB_SAT:
6110                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_PSUBB_SAT:
6113                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_PADDW_SAT:
6116                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118                 case OP_PSUBW_SAT:
6119                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121
6122                 case OP_PMULW:
6123                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6124                         break;
6125                 case OP_PMULD:
6126                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6127                         break;
6128                 case OP_PMULQ:
6129                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131                 case OP_PMULW_HIGH_UN:
6132                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6133                         break;
6134                 case OP_PMULW_HIGH:
6135                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6136                         break;
6137
6138                 case OP_PSHRW:
6139                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6140                         break;
6141                 case OP_PSHRW_REG:
6142                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6143                         break;
6144
6145                 case OP_PSARW:
6146                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6147                         break;
6148                 case OP_PSARW_REG:
6149                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6150                         break;
6151
6152                 case OP_PSHLW:
6153                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6154                         break;
6155                 case OP_PSHLW_REG:
6156                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6157                         break;
6158
6159                 case OP_PSHRD:
6160                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6161                         break;
6162                 case OP_PSHRD_REG:
6163                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6164                         break;
6165
6166                 case OP_PSARD:
6167                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6168                         break;
6169                 case OP_PSARD_REG:
6170                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6171                         break;
6172
6173                 case OP_PSHLD:
6174                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6175                         break;
6176                 case OP_PSHLD_REG:
6177                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6178                         break;
6179
6180                 case OP_PSHRQ:
6181                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6182                         break;
6183                 case OP_PSHRQ_REG:
6184                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6185                         break;
6186
6187                 /*TODO: This is appart of the sse spec but not added
6188                 case OP_PSARQ:
6189                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6190                         break;
6191                 case OP_PSARQ_REG:
6192                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6193                         break;
6194                 */
6195
6196                 case OP_PSHLQ:
6197                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6198                         break;
6199                 case OP_PSHLQ_REG:
6200                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6201                         break;
6202                 case OP_CVTDQ2PD:
6203                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6204                         break;
6205                 case OP_CVTDQ2PS:
6206                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6207                         break;
6208                 case OP_CVTPD2DQ:
6209                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6210                         break;
6211                 case OP_CVTPD2PS:
6212                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6213                         break;
6214                 case OP_CVTPS2DQ:
6215                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6216                         break;
6217                 case OP_CVTPS2PD:
6218                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6219                         break;
6220                 case OP_CVTTPD2DQ:
6221                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6222                         break;
6223                 case OP_CVTTPS2DQ:
6224                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6225                         break;
6226
6227                 case OP_ICONV_TO_X:
6228                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6229                         break;
6230                 case OP_EXTRACT_I4:
6231                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6232                         break;
6233                 case OP_EXTRACT_I8:
6234                         if (ins->inst_c0) {
6235                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6236                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6237                         } else {
6238                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6239                         }
6240                         break;
6241                 case OP_EXTRACT_I1:
6242                 case OP_EXTRACT_U1:
6243                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6244                         if (ins->inst_c0)
6245                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6246                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6247                         break;
6248                 case OP_EXTRACT_I2:
6249                 case OP_EXTRACT_U2:
6250                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6251                         if (ins->inst_c0)
6252                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6253                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6254                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6255                         break;
6256                 case OP_EXTRACT_R8:
6257                         if (ins->inst_c0)
6258                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6259                         else
6260                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6261                         break;
6262                 case OP_INSERT_I2:
6263                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6264                         break;
6265                 case OP_EXTRACTX_U2:
6266                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6267                         break;
6268                 case OP_INSERTX_U1_SLOW:
6269                         /*sreg1 is the extracted ireg (scratch)
6270                         /sreg2 is the to be inserted ireg (scratch)
6271                         /dreg is the xreg to receive the value*/
6272
6273                         /*clear the bits from the extracted word*/
6274                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6275                         /*shift the value to insert if needed*/
6276                         if (ins->inst_c0 & 1)
6277                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6278                         /*join them together*/
6279                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6280                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6281                         break;
6282                 case OP_INSERTX_I4_SLOW:
6283                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6284                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6285                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6286                         break;
6287                 case OP_INSERTX_I8_SLOW:
6288                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6289                         if (ins->inst_c0)
6290                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6291                         else
6292                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6293                         break;
6294
6295                 case OP_INSERTX_R4_SLOW:
6296                         switch (ins->inst_c0) {
6297                         case 0:
6298                                 if (cfg->r4fp)
6299                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6300                                 else
6301                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6302                                 break;
6303                         case 1:
6304                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6305                                 if (cfg->r4fp)
6306                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6307                                 else
6308                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6309                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6310                                 break;
6311                         case 2:
6312                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6313                                 if (cfg->r4fp)
6314                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6315                                 else
6316                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6317                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6318                                 break;
6319                         case 3:
6320                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6321                                 if (cfg->r4fp)
6322                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6323                                 else
6324                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6325                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6326                                 break;
6327                         }
6328                         break;
6329                 case OP_INSERTX_R8_SLOW:
6330                         if (ins->inst_c0)
6331                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6332                         else
6333                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6334                         break;
6335                 case OP_STOREX_MEMBASE_REG:
6336                 case OP_STOREX_MEMBASE:
6337                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6338                         break;
6339                 case OP_LOADX_MEMBASE:
6340                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6341                         break;
6342                 case OP_LOADX_ALIGNED_MEMBASE:
6343                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6344                         break;
6345                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6346                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6347                         break;
6348                 case OP_STOREX_NTA_MEMBASE_REG:
6349                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6350                         break;
6351                 case OP_PREFETCH_MEMBASE:
6352                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6353                         break;
6354
6355                 case OP_XMOVE:
6356                         /*FIXME the peephole pass should have killed this*/
6357                         if (ins->dreg != ins->sreg1)
6358                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6359                         break;
6360                 case OP_XZERO:
6361                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6362                         break;
6363                 case OP_XONES:
6364                         amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6365                         break;
6366                 case OP_ICONV_TO_R4_RAW:
6367                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6368                         if (!cfg->r4fp)
6369                           amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6370                         break;
6371
6372                 case OP_FCONV_TO_R8_X:
6373                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6374                         break;
6375
6376                 case OP_XCONV_R8_TO_I4:
6377                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6378                         switch (ins->backend.source_opcode) {
6379                         case OP_FCONV_TO_I1:
6380                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6381                                 break;
6382                         case OP_FCONV_TO_U1:
6383                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6384                                 break;
6385                         case OP_FCONV_TO_I2:
6386                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6387                                 break;
6388                         case OP_FCONV_TO_U2:
6389                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6390                                 break;
6391                         }
6392                         break;
6393
6394                 case OP_EXPAND_I2:
6395                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6396                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6397                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6398                         break;
6399                 case OP_EXPAND_I4:
6400                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6401                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6402                         break;
6403                 case OP_EXPAND_I8:
6404                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6405                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6406                         break;
6407                 case OP_EXPAND_R4:
6408                         if (cfg->r4fp) {
6409                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6410                         } else {
6411                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6412                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6413                         }
6414                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6415                         break;
6416                 case OP_EXPAND_R8:
6417                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6418                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6419                         break;
6420 #endif
6421                 case OP_LIVERANGE_START: {
6422                         if (cfg->verbose_level > 1)
6423                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6424                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6425                         break;
6426                 }
6427                 case OP_LIVERANGE_END: {
6428                         if (cfg->verbose_level > 1)
6429                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6430                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6431                         break;
6432                 }
6433                 case OP_GC_SAFE_POINT: {
6434                         guint8 *br [1];
6435
6436                         g_assert (mono_threads_is_coop_enabled ());
6437
6438                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6439                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6440                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6441                         amd64_patch (br[0], code);
6442                         break;
6443                 }
6444
6445                 case OP_GC_LIVENESS_DEF:
6446                 case OP_GC_LIVENESS_USE:
6447                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6448                         ins->backend.pc_offset = code - cfg->native_code;
6449                         break;
6450                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6451                         ins->backend.pc_offset = code - cfg->native_code;
6452                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6453                         break;
6454                 case OP_GET_LAST_ERROR:
6455                         emit_get_last_error(code, ins->dreg);
6456                         break;
6457                 default:
6458                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6459                         g_assert_not_reached ();
6460                 }
6461
6462                 if ((code - cfg->native_code - offset) > max_len) {
6463                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6464                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6465                         g_assert_not_reached ();
6466                 }
6467         }
6468
6469         cfg->code_len = code - cfg->native_code;
6470 }
6471
6472 #endif /* DISABLE_JIT */
6473
6474 void
6475 mono_arch_register_lowlevel_calls (void)
6476 {
6477         /* The signature doesn't matter */
6478         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6479 }
6480
6481 void
6482 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6483 {
6484         unsigned char *ip = ji->ip.i + code;
6485
6486         /*
6487          * Debug code to help track down problems where the target of a near call is
6488          * is not valid.
6489          */
6490         if (amd64_is_near_call (ip)) {
6491                 gint64 disp = (guint8*)target - (guint8*)ip;
6492
6493                 if (!amd64_is_imm32 (disp)) {
6494                         printf ("TYPE: %d\n", ji->type);
6495                         switch (ji->type) {
6496                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6497                                 printf ("V: %s\n", ji->data.name);
6498                                 break;
6499                         case MONO_PATCH_INFO_METHOD_JUMP:
6500                         case MONO_PATCH_INFO_METHOD:
6501                                 printf ("V: %s\n", ji->data.method->name);
6502                                 break;
6503                         default:
6504                                 break;
6505                         }
6506                 }
6507         }
6508
6509         amd64_patch (ip, (gpointer)target);
6510 }
6511
6512 #ifndef DISABLE_JIT
6513
6514 static int
6515 get_max_epilog_size (MonoCompile *cfg)
6516 {
6517         int max_epilog_size = 16;
6518
6519         if (cfg->method->save_lmf)
6520                 max_epilog_size += 256;
6521
6522         if (mono_jit_trace_calls != NULL)
6523                 max_epilog_size += 50;
6524
6525         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6526                 max_epilog_size += 50;
6527
6528         max_epilog_size += (AMD64_NREG * 2);
6529
6530         return max_epilog_size;
6531 }
6532
6533 /*
6534  * This macro is used for testing whenever the unwinder works correctly at every point
6535  * where an async exception can happen.
6536  */
6537 /* This will generate a SIGSEGV at the given point in the code */
6538 #define async_exc_point(code) do { \
6539     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6540          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6541              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6542          cfg->arch.async_point_count ++; \
6543     } \
6544 } while (0)
6545
6546 guint8 *
6547 mono_arch_emit_prolog (MonoCompile *cfg)
6548 {
6549         MonoMethod *method = cfg->method;
6550         MonoBasicBlock *bb;
6551         MonoMethodSignature *sig;
6552         MonoInst *ins;
6553         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6554         guint8 *code;
6555         CallInfo *cinfo;
6556         MonoInst *lmf_var = cfg->lmf_var;
6557         gboolean args_clobbered = FALSE;
6558         gboolean trace = FALSE;
6559
6560         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6561
6562         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6563
6564         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6565                 trace = TRUE;
6566
6567         /* Amount of stack space allocated by register saving code */
6568         pos = 0;
6569
6570         /* Offset between RSP and the CFA */
6571         cfa_offset = 0;
6572
6573         /*
6574          * The prolog consists of the following parts:
6575          * FP present:
6576          * - push rbp, mov rbp, rsp
6577          * - save callee saved regs using pushes
6578          * - allocate frame
6579          * - save rgctx if needed
6580          * - save lmf if needed
6581          * FP not present:
6582          * - allocate frame
6583          * - save rgctx if needed
6584          * - save lmf if needed
6585          * - save callee saved regs using moves
6586          */
6587
6588         // CFA = sp + 8
6589         cfa_offset = 8;
6590         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6591         // IP saved at CFA - 8
6592         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6593         async_exc_point (code);
6594         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6595
6596         if (!cfg->arch.omit_fp) {
6597                 amd64_push_reg (code, AMD64_RBP);
6598                 cfa_offset += 8;
6599                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6600                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6601                 async_exc_point (code);
6602 #ifdef TARGET_WIN32
6603                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6604 #endif
6605                 /* These are handled automatically by the stack marking code */
6606                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6607
6608                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6609                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6610                 async_exc_point (code);
6611 #ifdef TARGET_WIN32
6612                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6613 #endif
6614         }
6615
6616         /* The param area is always at offset 0 from sp */
6617         /* This needs to be allocated here, since it has to come after the spill area */
6618         if (cfg->param_area) {
6619                 if (cfg->arch.omit_fp)
6620                         // FIXME:
6621                         g_assert_not_reached ();
6622                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6623         }
6624
6625         if (cfg->arch.omit_fp) {
6626                 /*
6627                  * On enter, the stack is misaligned by the pushing of the return
6628                  * address. It is either made aligned by the pushing of %rbp, or by
6629                  * this.
6630                  */
6631                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6632                 if ((alloc_size % 16) == 0) {
6633                         alloc_size += 8;
6634                         /* Mark the padding slot as NOREF */
6635                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6636                 }
6637         } else {
6638                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6639                 if (cfg->stack_offset != alloc_size) {
6640                         /* Mark the padding slot as NOREF */
6641                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6642                 }
6643                 cfg->arch.sp_fp_offset = alloc_size;
6644                 alloc_size -= pos;
6645         }
6646
6647         cfg->arch.stack_alloc_size = alloc_size;
6648
6649         /* Allocate stack frame */
6650         if (alloc_size) {
6651                 /* See mono_emit_stack_alloc */
6652 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6653                 guint32 remaining_size = alloc_size;
6654                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6655                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6656                 guint32 offset = code - cfg->native_code;
6657                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6658                         while (required_code_size >= (cfg->code_size - offset))
6659                                 cfg->code_size *= 2;
6660                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6661                         code = cfg->native_code + offset;
6662                         cfg->stat_code_reallocs++;
6663                 }
6664
6665                 while (remaining_size >= 0x1000) {
6666                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6667                         if (cfg->arch.omit_fp) {
6668                                 cfa_offset += 0x1000;
6669                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6670                         }
6671                         async_exc_point (code);
6672 #ifdef TARGET_WIN32
6673                         if (cfg->arch.omit_fp)
6674                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6675 #endif
6676
6677                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6678                         remaining_size -= 0x1000;
6679                 }
6680                 if (remaining_size) {
6681                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6682                         if (cfg->arch.omit_fp) {
6683                                 cfa_offset += remaining_size;
6684                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6685                                 async_exc_point (code);
6686                         }
6687 #ifdef TARGET_WIN32
6688                         if (cfg->arch.omit_fp)
6689                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6690 #endif
6691                 }
6692 #else
6693                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6694                 if (cfg->arch.omit_fp) {
6695                         cfa_offset += alloc_size;
6696                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6697                         async_exc_point (code);
6698                 }
6699 #endif
6700         }
6701
6702         /* Stack alignment check */
6703 #if 0
6704         {
6705                 guint8 *buf;
6706
6707                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6708                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6709                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6710                 buf = code;
6711                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6712                 amd64_breakpoint (code);
6713                 amd64_patch (buf, code);
6714         }
6715 #endif
6716
6717         if (mini_get_debug_options ()->init_stacks) {
6718                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6719
6720                 /* Save registers to the red zone */
6721                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6722                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6723
6724                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6725                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6726                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6727
6728                 amd64_cld (code);
6729                 amd64_prefix (code, X86_REP_PREFIX);
6730                 amd64_stosl (code);
6731
6732                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6733                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6734         }
6735
6736         /* Save LMF */
6737         if (method->save_lmf)
6738                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6739
6740         /* Save callee saved registers */
6741         if (cfg->arch.omit_fp) {
6742                 save_area_offset = cfg->arch.reg_save_area_offset;
6743                 /* Save caller saved registers after sp is adjusted */
6744                 /* The registers are saved at the bottom of the frame */
6745                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6746         } else {
6747                 /* The registers are saved just below the saved rbp */
6748                 save_area_offset = cfg->arch.reg_save_area_offset;
6749         }
6750
6751         for (i = 0; i < AMD64_NREG; ++i) {
6752                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6753                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6754
6755                         if (cfg->arch.omit_fp) {
6756                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6757                                 /* These are handled automatically by the stack marking code */
6758                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6759                         } else {
6760                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6761                                 // FIXME: GC
6762                         }
6763
6764                         save_area_offset += 8;
6765                         async_exc_point (code);
6766                 }
6767         }
6768
6769         /* store runtime generic context */
6770         if (cfg->rgctx_var) {
6771                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6772                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6773
6774                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6775
6776                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6777                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6778         }
6779
6780         /* compute max_length in order to use short forward jumps */
6781         max_epilog_size = get_max_epilog_size (cfg);
6782         if (cfg->opt & MONO_OPT_BRANCH) {
6783                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6784                         MonoInst *ins;
6785                         int max_length = 0;
6786
6787                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6788                                 max_length += 6;
6789                         /* max alignment for loops */
6790                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6791                                 max_length += LOOP_ALIGNMENT;
6792
6793                         MONO_BB_FOR_EACH_INS (bb, ins) {
6794                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6795                         }
6796
6797                         /* Take prolog and epilog instrumentation into account */
6798                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6799                                 max_length += max_epilog_size;
6800
6801                         bb->max_length = max_length;
6802                 }
6803         }
6804
6805         sig = mono_method_signature (method);
6806         pos = 0;
6807
6808         cinfo = (CallInfo *)cfg->arch.cinfo;
6809
6810         if (sig->ret->type != MONO_TYPE_VOID) {
6811                 /* Save volatile arguments to the stack */
6812                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6813                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6814         }
6815
6816         /* Keep this in sync with emit_load_volatile_arguments */
6817         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6818                 ArgInfo *ainfo = cinfo->args + i;
6819
6820                 ins = cfg->args [i];
6821
6822                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6823                         /* Unused arguments */
6824                         continue;
6825
6826                 /* Save volatile arguments to the stack */
6827                 if (ins->opcode != OP_REGVAR) {
6828                         switch (ainfo->storage) {
6829                         case ArgInIReg: {
6830                                 guint32 size = 8;
6831
6832                                 /* FIXME: I1 etc */
6833                                 /*
6834                                 if (stack_offset & 0x1)
6835                                         size = 1;
6836                                 else if (stack_offset & 0x2)
6837                                         size = 2;
6838                                 else if (stack_offset & 0x4)
6839                                         size = 4;
6840                                 else
6841                                         size = 8;
6842                                 */
6843                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6844
6845                                 /*
6846                                  * Save the original location of 'this',
6847                                  * get_generic_info_from_stack_frame () needs this to properly look up
6848                                  * the argument value during the handling of async exceptions.
6849                                  */
6850                                 if (ins == cfg->args [0]) {
6851                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6852                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6853                                 }
6854                                 break;
6855                         }
6856                         case ArgInFloatSSEReg:
6857                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6858                                 break;
6859                         case ArgInDoubleSSEReg:
6860                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6861                                 break;
6862                         case ArgValuetypeInReg:
6863                                 for (quad = 0; quad < 2; quad ++) {
6864                                         switch (ainfo->pair_storage [quad]) {
6865                                         case ArgInIReg:
6866                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6867                                                 break;
6868                                         case ArgInFloatSSEReg:
6869                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6870                                                 break;
6871                                         case ArgInDoubleSSEReg:
6872                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6873                                                 break;
6874                                         case ArgNone:
6875                                                 break;
6876                                         default:
6877                                                 g_assert_not_reached ();
6878                                         }
6879                                 }
6880                                 break;
6881                         case ArgValuetypeAddrInIReg:
6882                                 if (ainfo->pair_storage [0] == ArgInIReg)
6883                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6884                                 break;
6885                         case ArgValuetypeAddrOnStack:
6886                                 break;
6887                         case ArgGSharedVtInReg:
6888                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6889                                 break;
6890                         default:
6891                                 break;
6892                         }
6893                 } else {
6894                         /* Argument allocated to (non-volatile) register */
6895                         switch (ainfo->storage) {
6896                         case ArgInIReg:
6897                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6898                                 break;
6899                         case ArgOnStack:
6900                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6901                                 break;
6902                         default:
6903                                 g_assert_not_reached ();
6904                         }
6905
6906                         if (ins == cfg->args [0]) {
6907                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6908                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6909                         }
6910                 }
6911         }
6912
6913         if (cfg->method->save_lmf)
6914                 args_clobbered = TRUE;
6915
6916         if (trace) {
6917                 args_clobbered = TRUE;
6918                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6919         }
6920
6921         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6922                 args_clobbered = TRUE;
6923
6924         /*
6925          * Optimize the common case of the first bblock making a call with the same
6926          * arguments as the method. This works because the arguments are still in their
6927          * original argument registers.
6928          * FIXME: Generalize this
6929          */
6930         if (!args_clobbered) {
6931                 MonoBasicBlock *first_bb = cfg->bb_entry;
6932                 MonoInst *next;
6933                 int filter = FILTER_IL_SEQ_POINT;
6934
6935                 next = mono_bb_first_inst (first_bb, filter);
6936                 if (!next && first_bb->next_bb) {
6937                         first_bb = first_bb->next_bb;
6938                         next = mono_bb_first_inst (first_bb, filter);
6939                 }
6940
6941                 if (first_bb->in_count > 1)
6942                         next = NULL;
6943
6944                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6945                         ArgInfo *ainfo = cinfo->args + i;
6946                         gboolean match = FALSE;
6947
6948                         ins = cfg->args [i];
6949                         if (ins->opcode != OP_REGVAR) {
6950                                 switch (ainfo->storage) {
6951                                 case ArgInIReg: {
6952                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6953                                                 if (next->dreg == ainfo->reg) {
6954                                                         NULLIFY_INS (next);
6955                                                         match = TRUE;
6956                                                 } else {
6957                                                         next->opcode = OP_MOVE;
6958                                                         next->sreg1 = ainfo->reg;
6959                                                         /* Only continue if the instruction doesn't change argument regs */
6960                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6961                                                                 match = TRUE;
6962                                                 }
6963                                         }
6964                                         break;
6965                                 }
6966                                 default:
6967                                         break;
6968                                 }
6969                         } else {
6970                                 /* Argument allocated to (non-volatile) register */
6971                                 switch (ainfo->storage) {
6972                                 case ArgInIReg:
6973                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6974                                                 NULLIFY_INS (next);
6975                                                 match = TRUE;
6976                                         }
6977                                         break;
6978                                 default:
6979                                         break;
6980                                 }
6981                         }
6982
6983                         if (match) {
6984                                 next = mono_inst_next (next, filter);
6985                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6986                                 if (!next)
6987                                         break;
6988                         }
6989                 }
6990         }
6991
6992         if (cfg->gen_sdb_seq_points) {
6993                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
6994
6995                 /* Initialize seq_point_info_var */
6996                 if (cfg->compile_aot) {
6997                         /* Initialize the variable from a GOT slot */
6998                         /* Same as OP_AOTCONST */
6999                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7000                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7001                         g_assert (info_var->opcode == OP_REGOFFSET);
7002                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7003                 }
7004
7005                 if (cfg->compile_aot) {
7006                         /* Initialize ss_tramp_var */
7007                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7008                         g_assert (ins->opcode == OP_REGOFFSET);
7009
7010                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7011                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7012                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7013                 } else {
7014                         /* Initialize ss_tramp_var */
7015                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7016                         g_assert (ins->opcode == OP_REGOFFSET);
7017
7018                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7019                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7020
7021                         /* Initialize bp_tramp_var */
7022                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7023                         g_assert (ins->opcode == OP_REGOFFSET);
7024
7025                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7026                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7027                 }
7028         }
7029
7030         cfg->code_len = code - cfg->native_code;
7031
7032         g_assert (cfg->code_len < cfg->code_size);
7033
7034         return code;
7035 }
7036
7037 void
7038 mono_arch_emit_epilog (MonoCompile *cfg)
7039 {
7040         MonoMethod *method = cfg->method;
7041         int quad, i;
7042         guint8 *code;
7043         int max_epilog_size;
7044         CallInfo *cinfo;
7045         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7046         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7047
7048         max_epilog_size = get_max_epilog_size (cfg);
7049
7050         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7051                 cfg->code_size *= 2;
7052                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7053                 cfg->stat_code_reallocs++;
7054         }
7055         code = cfg->native_code + cfg->code_len;
7056
7057         cfg->has_unwind_info_for_epilog = TRUE;
7058
7059         /* Mark the start of the epilog */
7060         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7061
7062         /* Save the uwind state which is needed by the out-of-line code */
7063         mono_emit_unwind_op_remember_state (cfg, code);
7064
7065         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7066                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7067
7068         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7069
7070         if (method->save_lmf) {
7071                 /* check if we need to restore protection of the stack after a stack overflow */
7072                 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7073                         guint8 *patch;
7074                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7075                         /* we load the value in a separate instruction: this mechanism may be
7076                          * used later as a safer way to do thread interruption
7077                          */
7078                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7079                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7080                         patch = code;
7081                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7082                         /* note that the call trampoline will preserve eax/edx */
7083                         x86_call_reg (code, X86_ECX);
7084                         x86_patch (patch, code);
7085                 } else {
7086                         /* FIXME: maybe save the jit tls in the prolog */
7087                 }
7088                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7089                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7090                 }
7091         }
7092
7093         /* Restore callee saved regs */
7094         for (i = 0; i < AMD64_NREG; ++i) {
7095                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7096                         /* Restore only used_int_regs, not arch.saved_iregs */
7097 #if defined(MONO_SUPPORT_TASKLETS)
7098                         int restore_reg=1;
7099 #else
7100                         int restore_reg=(cfg->used_int_regs & (1 << i));
7101 #endif
7102                         if (restore_reg) {
7103                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7104                                 mono_emit_unwind_op_same_value (cfg, code, i);
7105                                 async_exc_point (code);
7106                         }
7107                         save_area_offset += 8;
7108                 }
7109         }
7110
7111         /* Load returned vtypes into registers if needed */
7112         cinfo = (CallInfo *)cfg->arch.cinfo;
7113         if (cinfo->ret.storage == ArgValuetypeInReg) {
7114                 ArgInfo *ainfo = &cinfo->ret;
7115                 MonoInst *inst = cfg->ret;
7116
7117                 for (quad = 0; quad < 2; quad ++) {
7118                         switch (ainfo->pair_storage [quad]) {
7119                         case ArgInIReg:
7120                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7121                                 break;
7122                         case ArgInFloatSSEReg:
7123                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7124                                 break;
7125                         case ArgInDoubleSSEReg:
7126                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7127                                 break;
7128                         case ArgNone:
7129                                 break;
7130                         default:
7131                                 g_assert_not_reached ();
7132                         }
7133                 }
7134         }
7135
7136         if (cfg->arch.omit_fp) {
7137                 if (cfg->arch.stack_alloc_size) {
7138                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7139                 }
7140         } else {
7141                 amd64_leave (code);
7142                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7143         }
7144         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7145         async_exc_point (code);
7146         amd64_ret (code);
7147
7148         /* Restore the unwind state to be the same as before the epilog */
7149         mono_emit_unwind_op_restore_state (cfg, code);
7150
7151         cfg->code_len = code - cfg->native_code;
7152
7153         g_assert (cfg->code_len < cfg->code_size);
7154 }
7155
7156 void
7157 mono_arch_emit_exceptions (MonoCompile *cfg)
7158 {
7159         MonoJumpInfo *patch_info;
7160         int nthrows, i;
7161         guint8 *code;
7162         MonoClass *exc_classes [16];
7163         guint8 *exc_throw_start [16], *exc_throw_end [16];
7164         guint32 code_size = 0;
7165
7166         /* Compute needed space */
7167         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7168                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7169                         code_size += 40;
7170                 if (patch_info->type == MONO_PATCH_INFO_R8)
7171                         code_size += 8 + 15; /* sizeof (double) + alignment */
7172                 if (patch_info->type == MONO_PATCH_INFO_R4)
7173                         code_size += 4 + 15; /* sizeof (float) + alignment */
7174                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7175                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7176         }
7177
7178         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7179                 cfg->code_size *= 2;
7180                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7181                 cfg->stat_code_reallocs++;
7182         }
7183
7184         code = cfg->native_code + cfg->code_len;
7185
7186         /* add code to raise exceptions */
7187         nthrows = 0;
7188         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7189                 switch (patch_info->type) {
7190                 case MONO_PATCH_INFO_EXC: {
7191                         MonoClass *exc_class;
7192                         guint8 *buf, *buf2;
7193                         guint32 throw_ip;
7194
7195                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7196
7197                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7198                         throw_ip = patch_info->ip.i;
7199
7200                         //x86_breakpoint (code);
7201                         /* Find a throw sequence for the same exception class */
7202                         for (i = 0; i < nthrows; ++i)
7203                                 if (exc_classes [i] == exc_class)
7204                                         break;
7205                         if (i < nthrows) {
7206                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7207                                 x86_jump_code (code, exc_throw_start [i]);
7208                                 patch_info->type = MONO_PATCH_INFO_NONE;
7209                         }
7210                         else {
7211                                 buf = code;
7212                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7213                                 buf2 = code;
7214
7215                                 if (nthrows < 16) {
7216                                         exc_classes [nthrows] = exc_class;
7217                                         exc_throw_start [nthrows] = code;
7218                                 }
7219                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7220
7221                                 patch_info->type = MONO_PATCH_INFO_NONE;
7222
7223                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7224
7225                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7226                                 while (buf < buf2)
7227                                         x86_nop (buf);
7228
7229                                 if (nthrows < 16) {
7230                                         exc_throw_end [nthrows] = code;
7231                                         nthrows ++;
7232                                 }
7233                         }
7234                         break;
7235                 }
7236                 default:
7237                         /* do nothing */
7238                         break;
7239                 }
7240                 g_assert(code < cfg->native_code + cfg->code_size);
7241         }
7242
7243         /* Handle relocations with RIP relative addressing */
7244         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7245                 gboolean remove = FALSE;
7246                 guint8 *orig_code = code;
7247
7248                 switch (patch_info->type) {
7249                 case MONO_PATCH_INFO_R8:
7250                 case MONO_PATCH_INFO_R4: {
7251                         guint8 *pos, *patch_pos;
7252                         guint32 target_pos;
7253
7254                         /* The SSE opcodes require a 16 byte alignment */
7255                         code = (guint8*)ALIGN_TO (code, 16);
7256
7257                         pos = cfg->native_code + patch_info->ip.i;
7258                         if (IS_REX (pos [1])) {
7259                                 patch_pos = pos + 5;
7260                                 target_pos = code - pos - 9;
7261                         }
7262                         else {
7263                                 patch_pos = pos + 4;
7264                                 target_pos = code - pos - 8;
7265                         }
7266
7267                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7268                                 *(double*)code = *(double*)patch_info->data.target;
7269                                 code += sizeof (double);
7270                         } else {
7271                                 *(float*)code = *(float*)patch_info->data.target;
7272                                 code += sizeof (float);
7273                         }
7274
7275                         *(guint32*)(patch_pos) = target_pos;
7276
7277                         remove = TRUE;
7278                         break;
7279                 }
7280                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7281                         guint8 *pos;
7282
7283                         if (cfg->compile_aot)
7284                                 continue;
7285
7286                         /*loading is faster against aligned addresses.*/
7287                         code = (guint8*)ALIGN_TO (code, 8);
7288                         memset (orig_code, 0, code - orig_code);
7289
7290                         pos = cfg->native_code + patch_info->ip.i;
7291
7292                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7293                         if (IS_REX (pos [1]))
7294                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7295                         else
7296                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7297
7298                         *(gpointer*)code = (gpointer)patch_info->data.target;
7299                         code += sizeof (gpointer);
7300
7301                         remove = TRUE;
7302                         break;
7303                 }
7304                 default:
7305                         break;
7306                 }
7307
7308                 if (remove) {
7309                         if (patch_info == cfg->patch_info)
7310                                 cfg->patch_info = patch_info->next;
7311                         else {
7312                                 MonoJumpInfo *tmp;
7313
7314                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7315                                         ;
7316                                 tmp->next = patch_info->next;
7317                         }
7318                 }
7319                 g_assert (code < cfg->native_code + cfg->code_size);
7320         }
7321
7322         cfg->code_len = code - cfg->native_code;
7323
7324         g_assert (cfg->code_len < cfg->code_size);
7325
7326 }
7327
7328 #endif /* DISABLE_JIT */
7329
7330 void*
7331 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7332 {
7333         guchar *code = (guchar *)p;
7334         MonoMethodSignature *sig;
7335         MonoInst *inst;
7336         int i, n, stack_area = 0;
7337
7338         /* Keep this in sync with mono_arch_get_argument_info */
7339
7340         if (enable_arguments) {
7341                 /* Allocate a new area on the stack and save arguments there */
7342                 sig = mono_method_signature (cfg->method);
7343
7344                 n = sig->param_count + sig->hasthis;
7345
7346                 stack_area = ALIGN_TO (n * 8, 16);
7347
7348                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7349
7350                 for (i = 0; i < n; ++i) {
7351                         inst = cfg->args [i];
7352
7353                         if (inst->opcode == OP_REGVAR)
7354                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7355                         else {
7356                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7357                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7358                         }
7359                 }
7360         }
7361
7362         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7363         amd64_set_reg_template (code, AMD64_ARG_REG1);
7364         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7365         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7366
7367         if (enable_arguments)
7368                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7369
7370         return code;
7371 }
7372
7373 enum {
7374         SAVE_NONE,
7375         SAVE_STRUCT,
7376         SAVE_EAX,
7377         SAVE_EAX_EDX,
7378         SAVE_XMM
7379 };
7380
7381 void*
7382 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7383 {
7384         guchar *code = (guchar *)p;
7385         int save_mode = SAVE_NONE;
7386         MonoMethod *method = cfg->method;
7387         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7388         int i;
7389
7390         switch (ret_type->type) {
7391         case MONO_TYPE_VOID:
7392                 /* special case string .ctor icall */
7393                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7394                         save_mode = SAVE_EAX;
7395                 else
7396                         save_mode = SAVE_NONE;
7397                 break;
7398         case MONO_TYPE_I8:
7399         case MONO_TYPE_U8:
7400                 save_mode = SAVE_EAX;
7401                 break;
7402         case MONO_TYPE_R4:
7403         case MONO_TYPE_R8:
7404                 save_mode = SAVE_XMM;
7405                 break;
7406         case MONO_TYPE_GENERICINST:
7407                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7408                         save_mode = SAVE_EAX;
7409                         break;
7410                 }
7411                 /* Fall through */
7412         case MONO_TYPE_VALUETYPE:
7413                 save_mode = SAVE_STRUCT;
7414                 break;
7415         default:
7416                 save_mode = SAVE_EAX;
7417                 break;
7418         }
7419
7420         /* Save the result and copy it into the proper argument register */
7421         switch (save_mode) {
7422         case SAVE_EAX:
7423                 amd64_push_reg (code, AMD64_RAX);
7424                 /* Align stack */
7425                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7426                 if (enable_arguments)
7427                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7428                 break;
7429         case SAVE_STRUCT:
7430                 /* FIXME: */
7431                 if (enable_arguments)
7432                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7433                 break;
7434         case SAVE_XMM:
7435                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7436                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7437                 /* Align stack */
7438                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7439                 /*
7440                  * The result is already in the proper argument register so no copying
7441                  * needed.
7442                  */
7443                 break;
7444         case SAVE_NONE:
7445                 break;
7446         default:
7447                 g_assert_not_reached ();
7448         }
7449
7450         /* Set %al since this is a varargs call */
7451         if (save_mode == SAVE_XMM)
7452                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7453         else
7454                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7455
7456         if (preserve_argument_registers) {
7457                 for (i = 0; i < PARAM_REGS; ++i)
7458                         amd64_push_reg (code, param_regs [i]);
7459         }
7460
7461         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7462         amd64_set_reg_template (code, AMD64_ARG_REG1);
7463         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7464
7465         if (preserve_argument_registers) {
7466                 for (i = PARAM_REGS - 1; i >= 0; --i)
7467                         amd64_pop_reg (code, param_regs [i]);
7468         }
7469
7470         /* Restore result */
7471         switch (save_mode) {
7472         case SAVE_EAX:
7473                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7474                 amd64_pop_reg (code, AMD64_RAX);
7475                 break;
7476         case SAVE_STRUCT:
7477                 /* FIXME: */
7478                 break;
7479         case SAVE_XMM:
7480                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7481                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7482                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7483                 break;
7484         case SAVE_NONE:
7485                 break;
7486         default:
7487                 g_assert_not_reached ();
7488         }
7489
7490         return code;
7491 }
7492
7493 void
7494 mono_arch_flush_icache (guint8 *code, gint size)
7495 {
7496         /* Not needed */
7497 }
7498
7499 void
7500 mono_arch_flush_register_windows (void)
7501 {
7502 }
7503
7504 gboolean
7505 mono_arch_is_inst_imm (gint64 imm)
7506 {
7507         return amd64_use_imm32 (imm);
7508 }
7509
7510 /*
7511  * Determine whenever the trap whose info is in SIGINFO is caused by
7512  * integer overflow.
7513  */
7514 gboolean
7515 mono_arch_is_int_overflow (void *sigctx, void *info)
7516 {
7517         MonoContext ctx;
7518         guint8* rip;
7519         int reg;
7520         gint64 value;
7521
7522         mono_sigctx_to_monoctx (sigctx, &ctx);
7523
7524         rip = (guint8*)ctx.gregs [AMD64_RIP];
7525
7526         if (IS_REX (rip [0])) {
7527                 reg = amd64_rex_b (rip [0]);
7528                 rip ++;
7529         }
7530         else
7531                 reg = 0;
7532
7533         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7534                 /* idiv REG */
7535                 reg += x86_modrm_rm (rip [1]);
7536
7537                 value = ctx.gregs [reg];
7538
7539                 if (value == -1)
7540                         return TRUE;
7541         }
7542
7543         return FALSE;
7544 }
7545
7546 guint32
7547 mono_arch_get_patch_offset (guint8 *code)
7548 {
7549         return 3;
7550 }
7551
7552 /**
7553  * mono_breakpoint_clean_code:
7554  *
7555  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7556  * breakpoints in the original code, they are removed in the copy.
7557  *
7558  * Returns TRUE if no sw breakpoint was present.
7559  */
7560 gboolean
7561 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7562 {
7563         /*
7564          * If method_start is non-NULL we need to perform bound checks, since we access memory
7565          * at code - offset we could go before the start of the method and end up in a different
7566          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7567          * instead.
7568          */
7569         if (!method_start || code - offset >= method_start) {
7570                 memcpy (buf, code - offset, size);
7571         } else {
7572                 int diff = code - method_start;
7573                 memset (buf, 0, size);
7574                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7575         }
7576         return TRUE;
7577 }
7578
7579 int
7580 mono_arch_get_this_arg_reg (guint8 *code)
7581 {
7582         return AMD64_ARG_REG1;
7583 }
7584
7585 gpointer
7586 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7587 {
7588         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7589 }
7590
7591 #define MAX_ARCH_DELEGATE_PARAMS 10
7592
7593 static gpointer
7594 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7595 {
7596         guint8 *code, *start;
7597         GSList *unwind_ops = NULL;
7598         int i;
7599
7600         unwind_ops = mono_arch_get_cie_program ();
7601
7602         if (has_target) {
7603                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7604
7605                 /* Replace the this argument with the target */
7606                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7607                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7608                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7609
7610                 g_assert ((code - start) < 64);
7611         } else {
7612                 start = code = (guint8 *)mono_global_codeman_reserve (64);
7613
7614                 if (param_count == 0) {
7615                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7616                 } else {
7617                         /* We have to shift the arguments left */
7618                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7619                         for (i = 0; i < param_count; ++i) {
7620 #ifdef TARGET_WIN32
7621                                 if (i < 3)
7622                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7623                                 else
7624                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7625 #else
7626                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7627 #endif
7628                         }
7629
7630                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7631                 }
7632                 g_assert ((code - start) < 64);
7633         }
7634
7635         mono_arch_flush_icache (start, code - start);
7636
7637         if (has_target) {
7638                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7639         } else {
7640                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7641                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7642                 g_free (name);
7643         }
7644
7645         if (mono_jit_map_is_enabled ()) {
7646                 char *buff;
7647                 if (has_target)
7648                         buff = (char*)"delegate_invoke_has_target";
7649                 else
7650                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7651                 mono_emit_jit_tramp (start, code - start, buff);
7652                 if (!has_target)
7653                         g_free (buff);
7654         }
7655         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7656
7657         return start;
7658 }
7659
7660 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7661
7662 static gpointer
7663 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7664 {
7665         guint8 *code, *start;
7666         int size = 20;
7667         char *tramp_name;
7668         GSList *unwind_ops;
7669
7670         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7671                 return NULL;
7672
7673         start = code = (guint8 *)mono_global_codeman_reserve (size);
7674
7675         unwind_ops = mono_arch_get_cie_program ();
7676
7677         /* Replace the this argument with the target */
7678         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7679         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7680
7681         if (load_imt_reg) {
7682                 /* Load the IMT reg */
7683                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7684         }
7685
7686         /* Load the vtable */
7687         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7688         amd64_jump_membase (code, AMD64_RAX, offset);
7689         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7690
7691         tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7692         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7693         g_free (tramp_name);
7694
7695         return start;
7696 }
7697
7698 /*
7699  * mono_arch_get_delegate_invoke_impls:
7700  *
7701  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7702  * trampolines.
7703  */
7704 GSList*
7705 mono_arch_get_delegate_invoke_impls (void)
7706 {
7707         GSList *res = NULL;
7708         MonoTrampInfo *info;
7709         int i;
7710
7711         get_delegate_invoke_impl (&info, TRUE, 0);
7712         res = g_slist_prepend (res, info);
7713
7714         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7715                 get_delegate_invoke_impl (&info, FALSE, i);
7716                 res = g_slist_prepend (res, info);
7717         }
7718
7719         for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7720                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7721                 res = g_slist_prepend (res, info);
7722         }
7723
7724         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7725                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7726                 res = g_slist_prepend (res, info);
7727                 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7728                 res = g_slist_prepend (res, info);
7729         }
7730
7731         return res;
7732 }
7733
7734 gpointer
7735 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7736 {
7737         guint8 *code, *start;
7738         int i;
7739
7740         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7741                 return NULL;
7742
7743         /* FIXME: Support more cases */
7744         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7745                 return NULL;
7746
7747         if (has_target) {
7748                 static guint8* cached = NULL;
7749
7750                 if (cached)
7751                         return cached;
7752
7753                 if (mono_aot_only) {
7754                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7755                 } else {
7756                         MonoTrampInfo *info;
7757                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7758                         mono_tramp_info_register (info, NULL);
7759                 }
7760
7761                 mono_memory_barrier ();
7762
7763                 cached = start;
7764         } else {
7765                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7766                 for (i = 0; i < sig->param_count; ++i)
7767                         if (!mono_is_regsize_var (sig->params [i]))
7768                                 return NULL;
7769                 if (sig->param_count > 4)
7770                         return NULL;
7771
7772                 code = cache [sig->param_count];
7773                 if (code)
7774                         return code;
7775
7776                 if (mono_aot_only) {
7777                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7778                         start = (guint8 *)mono_aot_get_trampoline (name);
7779                         g_free (name);
7780                 } else {
7781                         MonoTrampInfo *info;
7782                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7783                         mono_tramp_info_register (info, NULL);
7784                 }
7785
7786                 mono_memory_barrier ();
7787
7788                 cache [sig->param_count] = start;
7789         }
7790
7791         return start;
7792 }
7793
7794 gpointer
7795 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7796 {
7797         MonoTrampInfo *info;
7798         gpointer code;
7799
7800         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7801         if (code)
7802                 mono_tramp_info_register (info, NULL);
7803         return code;
7804 }
7805
7806 void
7807 mono_arch_finish_init (void)
7808 {
7809 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7810         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7811 #endif
7812 }
7813
7814 void
7815 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7816 {
7817 }
7818
7819 #define CMP_SIZE (6 + 1)
7820 #define CMP_REG_REG_SIZE (4 + 1)
7821 #define BR_SMALL_SIZE 2
7822 #define BR_LARGE_SIZE 6
7823 #define MOV_REG_IMM_SIZE 10
7824 #define MOV_REG_IMM_32BIT_SIZE 6
7825 #define JUMP_REG_SIZE (2 + 1)
7826
7827 static int
7828 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7829 {
7830         int i, distance = 0;
7831         for (i = start; i < target; ++i)
7832                 distance += imt_entries [i]->chunk_size;
7833         return distance;
7834 }
7835
7836 /*
7837  * LOCKING: called with the domain lock held
7838  */
7839 gpointer
7840 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7841         gpointer fail_tramp)
7842 {
7843         int i;
7844         int size = 0;
7845         guint8 *code, *start;
7846         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7847         GSList *unwind_ops;
7848
7849         for (i = 0; i < count; ++i) {
7850                 MonoIMTCheckItem *item = imt_entries [i];
7851                 if (item->is_equals) {
7852                         if (item->check_target_idx) {
7853                                 if (!item->compare_done) {
7854                                         if (amd64_use_imm32 ((gint64)item->key))
7855                                                 item->chunk_size += CMP_SIZE;
7856                                         else
7857                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7858                                 }
7859                                 if (item->has_target_code) {
7860                                         item->chunk_size += MOV_REG_IMM_SIZE;
7861                                 } else {
7862                                         if (vtable_is_32bit)
7863                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7864                                         else
7865                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7866                                 }
7867                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7868                         } else {
7869                                 if (fail_tramp) {
7870                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7871                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7872                                 } else {
7873                                         if (vtable_is_32bit)
7874                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7875                                         else
7876                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7877                                         item->chunk_size += JUMP_REG_SIZE;
7878                                         /* with assert below:
7879                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7880                                          */
7881                                 }
7882                         }
7883                 } else {
7884                         if (amd64_use_imm32 ((gint64)item->key))
7885                                 item->chunk_size += CMP_SIZE;
7886                         else
7887                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7888                         item->chunk_size += BR_LARGE_SIZE;
7889                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7890                 }
7891                 size += item->chunk_size;
7892         }
7893         if (fail_tramp)
7894                 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size);
7895         else
7896                 code = (guint8 *)mono_domain_code_reserve (domain, size);
7897         start = code;
7898
7899         unwind_ops = mono_arch_get_cie_program ();
7900
7901         for (i = 0; i < count; ++i) {
7902                 MonoIMTCheckItem *item = imt_entries [i];
7903                 item->code_target = code;
7904                 if (item->is_equals) {
7905                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7906
7907                         if (item->check_target_idx || fail_case) {
7908                                 if (!item->compare_done || fail_case) {
7909                                         if (amd64_use_imm32 ((gint64)item->key))
7910                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7911                                         else {
7912                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7913                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7914                                         }
7915                                 }
7916                                 item->jmp_code = code;
7917                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7918                                 if (item->has_target_code) {
7919                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7920                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7921                                 } else {
7922                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7923                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7924                                 }
7925
7926                                 if (fail_case) {
7927                                         amd64_patch (item->jmp_code, code);
7928                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7929                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7930                                         item->jmp_code = NULL;
7931                                 }
7932                         } else {
7933                                 /* enable the commented code to assert on wrong method */
7934 #if 0
7935                                 if (amd64_is_imm32 (item->key))
7936                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7937                                 else {
7938                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7939                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7940                                 }
7941                                 item->jmp_code = code;
7942                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7943                                 /* See the comment below about R10 */
7944                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7945                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7946                                 amd64_patch (item->jmp_code, code);
7947                                 amd64_breakpoint (code);
7948                                 item->jmp_code = NULL;
7949 #else
7950                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7951                                    needs to be preserved.  R10 needs
7952                                    to be preserved for calls which
7953                                    require a runtime generic context,
7954                                    but interface calls don't. */
7955                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7956                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7957 #endif
7958                         }
7959                 } else {
7960                         if (amd64_use_imm32 ((gint64)item->key))
7961                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
7962                         else {
7963                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
7964                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7965                         }
7966                         item->jmp_code = code;
7967                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7968                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7969                         else
7970                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7971                 }
7972                 g_assert (code - item->code_target <= item->chunk_size);
7973         }
7974         /* patch the branches to get to the target items */
7975         for (i = 0; i < count; ++i) {
7976                 MonoIMTCheckItem *item = imt_entries [i];
7977                 if (item->jmp_code) {
7978                         if (item->check_target_idx) {
7979                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7980                         }
7981                 }
7982         }
7983
7984         if (!fail_tramp)
7985                 mono_stats.imt_trampolines_size += code - start;
7986         g_assert (code - start <= size);
7987
7988         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
7989
7990         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
7991
7992         return start;
7993 }
7994
7995 MonoMethod*
7996 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7997 {
7998         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7999 }
8000
8001 MonoVTable*
8002 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8003 {
8004         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8005 }
8006
8007 GSList*
8008 mono_arch_get_cie_program (void)
8009 {
8010         GSList *l = NULL;
8011
8012         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8013         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8014
8015         return l;
8016 }
8017
8018 #ifndef DISABLE_JIT
8019
8020 MonoInst*
8021 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8022 {
8023         MonoInst *ins = NULL;
8024         int opcode = 0;
8025
8026         if (cmethod->klass == mono_defaults.math_class) {
8027                 if (strcmp (cmethod->name, "Sin") == 0) {
8028                         opcode = OP_SIN;
8029                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8030                         opcode = OP_COS;
8031                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8032                         opcode = OP_SQRT;
8033                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8034                         opcode = OP_ABS;
8035                 }
8036
8037                 if (opcode && fsig->param_count == 1) {
8038                         MONO_INST_NEW (cfg, ins, opcode);
8039                         ins->type = STACK_R8;
8040                         ins->dreg = mono_alloc_freg (cfg);
8041                         ins->sreg1 = args [0]->dreg;
8042                         MONO_ADD_INS (cfg->cbb, ins);
8043                 }
8044
8045                 opcode = 0;
8046                 if (cfg->opt & MONO_OPT_CMOV) {
8047                         if (strcmp (cmethod->name, "Min") == 0) {
8048                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8049                                         opcode = OP_IMIN;
8050                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8051                                         opcode = OP_IMIN_UN;
8052                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8053                                         opcode = OP_LMIN;
8054                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8055                                         opcode = OP_LMIN_UN;
8056                         } else if (strcmp (cmethod->name, "Max") == 0) {
8057                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8058                                         opcode = OP_IMAX;
8059                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8060                                         opcode = OP_IMAX_UN;
8061                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8062                                         opcode = OP_LMAX;
8063                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8064                                         opcode = OP_LMAX_UN;
8065                         }
8066                 }
8067
8068                 if (opcode && fsig->param_count == 2) {
8069                         MONO_INST_NEW (cfg, ins, opcode);
8070                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8071                         ins->dreg = mono_alloc_ireg (cfg);
8072                         ins->sreg1 = args [0]->dreg;
8073                         ins->sreg2 = args [1]->dreg;
8074                         MONO_ADD_INS (cfg->cbb, ins);
8075                 }
8076
8077 #if 0
8078                 /* OP_FREM is not IEEE compatible */
8079                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8080                         MONO_INST_NEW (cfg, ins, OP_FREM);
8081                         ins->inst_i0 = args [0];
8082                         ins->inst_i1 = args [1];
8083                 }
8084 #endif
8085         }
8086
8087         return ins;
8088 }
8089 #endif
8090
8091 gboolean
8092 mono_arch_print_tree (MonoInst *tree, int arity)
8093 {
8094         return 0;
8095 }
8096
8097 mgreg_t
8098 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8099 {
8100         return ctx->gregs [reg];
8101 }
8102
8103 void
8104 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8105 {
8106         ctx->gregs [reg] = val;
8107 }
8108
8109 gpointer
8110 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8111 {
8112         gpointer *sp, old_value;
8113         char *bp;
8114
8115         /*Load the spvar*/
8116         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8117         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8118
8119         old_value = *sp;
8120         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8121                 return old_value;
8122
8123         *sp = new_value;
8124
8125         return old_value;
8126 }
8127
8128 /*
8129  * mono_arch_emit_load_aotconst:
8130  *
8131  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8132  * TARGET from the mscorlib GOT in full-aot code.
8133  * On AMD64, the result is placed into R11.
8134  */
8135 guint8*
8136 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8137 {
8138         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8139         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8140
8141         return code;
8142 }
8143
8144 /*
8145  * mono_arch_get_trampolines:
8146  *
8147  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8148  * for AOT.
8149  */
8150 GSList *
8151 mono_arch_get_trampolines (gboolean aot)
8152 {
8153         return mono_amd64_get_exception_trampolines (aot);
8154 }
8155
8156 /* Soft Debug support */
8157 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8158
8159 /*
8160  * mono_arch_set_breakpoint:
8161  *
8162  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8163  * The location should contain code emitted by OP_SEQ_POINT.
8164  */
8165 void
8166 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8167 {
8168         guint8 *code = ip;
8169
8170         if (ji->from_aot) {
8171                 guint32 native_offset = ip - (guint8*)ji->code_start;
8172                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8173
8174                 g_assert (info->bp_addrs [native_offset] == 0);
8175                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8176         } else {
8177                 /* ip points to a mov r11, 0 */
8178                 g_assert (code [0] == 0x41);
8179                 g_assert (code [1] == 0xbb);
8180                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8181         }
8182 }
8183
8184 /*
8185  * mono_arch_clear_breakpoint:
8186  *
8187  *   Clear the breakpoint at IP.
8188  */
8189 void
8190 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8191 {
8192         guint8 *code = ip;
8193
8194         if (ji->from_aot) {
8195                 guint32 native_offset = ip - (guint8*)ji->code_start;
8196                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8197
8198                 info->bp_addrs [native_offset] = NULL;
8199         } else {
8200                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8201         }
8202 }
8203
8204 gboolean
8205 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8206 {
8207         /* We use soft breakpoints on amd64 */
8208         return FALSE;
8209 }
8210
8211 /*
8212  * mono_arch_skip_breakpoint:
8213  *
8214  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8215  * we resume, the instruction is not executed again.
8216  */
8217 void
8218 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8219 {
8220         g_assert_not_reached ();
8221 }
8222
8223 /*
8224  * mono_arch_start_single_stepping:
8225  *
8226  *   Start single stepping.
8227  */
8228 void
8229 mono_arch_start_single_stepping (void)
8230 {
8231         ss_trampoline = mini_get_single_step_trampoline ();
8232 }
8233
8234 /*
8235  * mono_arch_stop_single_stepping:
8236  *
8237  *   Stop single stepping.
8238  */
8239 void
8240 mono_arch_stop_single_stepping (void)
8241 {
8242         ss_trampoline = NULL;
8243 }
8244
8245 /*
8246  * mono_arch_is_single_step_event:
8247  *
8248  *   Return whenever the machine state in SIGCTX corresponds to a single
8249  * step event.
8250  */
8251 gboolean
8252 mono_arch_is_single_step_event (void *info, void *sigctx)
8253 {
8254         /* We use soft breakpoints on amd64 */
8255         return FALSE;
8256 }
8257
8258 /*
8259  * mono_arch_skip_single_step:
8260  *
8261  *   Modify CTX so the ip is placed after the single step trigger instruction,
8262  * we resume, the instruction is not executed again.
8263  */
8264 void
8265 mono_arch_skip_single_step (MonoContext *ctx)
8266 {
8267         g_assert_not_reached ();
8268 }
8269
8270 /*
8271  * mono_arch_create_seq_point_info:
8272  *
8273  *   Return a pointer to a data structure which is used by the sequence
8274  * point implementation in AOTed code.
8275  */
8276 gpointer
8277 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8278 {
8279         SeqPointInfo *info;
8280         MonoJitInfo *ji;
8281
8282         // FIXME: Add a free function
8283
8284         mono_domain_lock (domain);
8285         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8286                                                                 code);
8287         mono_domain_unlock (domain);
8288
8289         if (!info) {
8290                 ji = mono_jit_info_table_find (domain, (char*)code);
8291                 g_assert (ji);
8292
8293                 // FIXME: Optimize the size
8294                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8295
8296                 info->ss_tramp_addr = &ss_trampoline;
8297
8298                 mono_domain_lock (domain);
8299                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8300                                                          code, info);
8301                 mono_domain_unlock (domain);
8302         }
8303
8304         return info;
8305 }
8306
8307 void
8308 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8309 {
8310         ext->lmf.previous_lmf = prev_lmf;
8311         /* Mark that this is a MonoLMFExt */
8312         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8313         ext->lmf.rsp = (gssize)ext;
8314 }
8315
8316 #endif
8317
8318 gboolean
8319 mono_arch_opcode_supported (int opcode)
8320 {
8321         switch (opcode) {
8322         case OP_ATOMIC_ADD_I4:
8323         case OP_ATOMIC_ADD_I8:
8324         case OP_ATOMIC_EXCHANGE_I4:
8325         case OP_ATOMIC_EXCHANGE_I8:
8326         case OP_ATOMIC_CAS_I4:
8327         case OP_ATOMIC_CAS_I8:
8328         case OP_ATOMIC_LOAD_I1:
8329         case OP_ATOMIC_LOAD_I2:
8330         case OP_ATOMIC_LOAD_I4:
8331         case OP_ATOMIC_LOAD_I8:
8332         case OP_ATOMIC_LOAD_U1:
8333         case OP_ATOMIC_LOAD_U2:
8334         case OP_ATOMIC_LOAD_U4:
8335         case OP_ATOMIC_LOAD_U8:
8336         case OP_ATOMIC_LOAD_R4:
8337         case OP_ATOMIC_LOAD_R8:
8338         case OP_ATOMIC_STORE_I1:
8339         case OP_ATOMIC_STORE_I2:
8340         case OP_ATOMIC_STORE_I4:
8341         case OP_ATOMIC_STORE_I8:
8342         case OP_ATOMIC_STORE_U1:
8343         case OP_ATOMIC_STORE_U2:
8344         case OP_ATOMIC_STORE_U4:
8345         case OP_ATOMIC_STORE_U8:
8346         case OP_ATOMIC_STORE_R4:
8347         case OP_ATOMIC_STORE_R8:
8348                 return TRUE;
8349         default:
8350                 return FALSE;
8351         }
8352 }
8353
8354 CallInfo*
8355 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8356 {
8357         return get_call_info (mp, sig);
8358 }